Creating a Gate Library

WARNING: This page is outdated and might not be applicable to recent versions of HAL. We will update this description as soon as possible.

Providing a gate library is essential to correctly parse HDL netlists into HAL. Since the HDL format does not specify which ports of gates are inputs or outputs, this information has to be provided by a gate library. Additionally, a gate library can specify the Boolean functions implemented by the gates of the library. Special input pins such as clock, enable, set, and reset can also be dealt with accordingly.

Creating a Gate Library

For the moment, only a single format for gate libraries is supported by HAL. However, due to the modularity of HAL, adding a parser for a different library format is rather straightforward. In general, gate libraries should be placed within the plugins/gate_libraries/definitions folder. They will automatically be loaded when building HAL.

Liberty Gate Library

A gate library can be defined using a liberty file, the standard file format for standard cell libraries. In addition to the existing standard, we added a few new statements to also facilitate FPGA libraries.

Additional liberty group statements

To allow for LUTs within FPGA netlists, a lut group statement can been added to the cell statement. This statement works quite similar to the ff statement. It allows for a function name to be specified within the () braces of the lut statement. The name can then be used in place of the function of an output pin to make the function of the pin being defined by the configuration string of the LUT. Within the lut group statement, three attributes concerning the configuration string of a LUT can be configured. While data_category and data_identifier handle the location in which the configuration string is stored, the bit_order specifies the order of the configuration string. An example for a LUT2, which specifies its configuration string in the generics of the respective HDL instance using the identifier INIT, is given in the following:

cell(LUT2) {
    lut ("lut_out") {
        data_category     : "generic";
        data_identifier   : "INIT";
        bit_order         : "ascending";
    }
    pin(ADR0) { direction: input; }
    pin(ADR1) { direction: input; }
    pin(O) {
        direction: output;
        function: "lut_out";
    }
}

An example gate instance taken from a Verilog Netlist is given below:

LUT2 #(.INIT(3'h6)) 
inst_name (
    .\I0 (in0),
    .\I1 (in1),
    .\O (out)
);

Similarly, for flip-flops the two simple attribute statements data_category and data_identifier have been added within the existing ff group statement. This enables HAL to deal with a user defined initialization value, which can for example be specified within the generics of an HDL instance. Such a value is commonly used to specify the initial state of a flip-flop upon startup of an FPGA.