Add NMOS and PMOS transistors type for gate library and compatible with simulation plugin

[i-pere]

Hi,

I would like to use HAL to simulate standard cells defined by NMOS and PMOS transistors.

Visualisation works fine with a custom .hgl library and a vhdl netlist with 3 PMOS and 3 NMOS gates forming a simple OR.

However, I have issues for the simulation part.

I tried to simulate one cell by:

• translating NMOS as a "mux" in the gate library where one input is the source, the second input is mapped to "Z" in vhdl netlist, select signal is the gate and the output is the drain. output function is ((gate & source) | ((! gate) & secondinput))
• translating PMOS as a "mux" in the gate library where one input is the source, the second input is mapped to "Z" in vhdl netlist ,select signal is the gate and the output is the drain. output function is ((gate & secondinput) | ((! gate) & source))

1. If I choose verilator as simulation engine, I get "simulation successful, add waveform data to visualize results" but I observed that the "Z" value is overwritten by 0 when I add secondinput waveform in the simulation window.

I tried to pass Z or X in the csv file for simulation instead of mapping it in the vhdl netlist but the simulator fails to parse my simulation file.

2. If I choose hal_simulator I see that my second input is equal to "x" as expected, ((gate & secondinput) | ((! gate) & source)) is equal to x when gate is equal to 1 for example.
   However, for my output connecting the N and P side, when I have a 1 on Pside and x on Nside I would like to get 1 and not x , similarly 0 on Nside and x on Pside would give 0 and not x.

How do you deel with "Z" values in your simulation ?
Did you develop a feature which could match my needs ?

Thanks in advance,
Isabelle