Support field arrays

[yodaldevoid]

Arrays of registers are currently supported, but the program does not support arrays of fields.

A strinpped-down example of an unsupported field array...

<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <vendor>Test</vendor>
  <vendorID>test</vendorID>
  <name>generic</name>
  <series>Generic</series>
  <version>1.0</version>
  <description>Generic</description>
  <cpu>
    <name>CM0PLUS</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <vtorPresent>1</vtorPresent>
    <nvicPrioBits>2</nvicPrioBits>
    <vendorSystickConfig>0</vendorSystickConfig>
  </cpu>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <resetValue>0x00000000</resetValue>
  <resetMask>0xFFFFFFFF</resetMask>
  <peripherals>
    <peripheral>
      <name>GPIO</name>
      <baseAddress>0x00000000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>512</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>OUT0</name>
          <addressOffset>0x000</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x00</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <dim>32</dim>
              <dimIncrement>1</dimIncrement>
              <name>PIN[%s]</name>
              <bitRange>[0:0]</bitRange>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>

and the resulting error.

> cargo run generate --svd .\field_array_test.svd
    Finished dev [unoptimized + debuginfo] target(s) in 0.10s
     Running `target\debug\chiptool.exe generate --svd .\field_array_test.svd`
thread 'main' panicked at '"pin%s" is not a valid Ident', C:\Users\ga29s\.cargo\registry\src\index.crates.io-6f17d22bba15001f\proc-macro2-1.0.36\src\fallback.rs:708:9
stack backtrace:
   0: std::panicking::begin_panic_handler
             at /rustc/e9e1bbc7a820c472b39d3de54b3049bf14050655/library\std\src\panicking.rs:578
   1: core::panicking::panic_fmt
             at /rustc/e9e1bbc7a820c472b39d3de54b3049bf14050655/library\core\src\panicking.rs:67
   2: proc_macro2::fallback::validate_ident
             at C:\Users\ga29s\.cargo\registry\src\index.crates.io-6f17d22bba15001f\proc-macro2-1.0.36\src\fallback.rs:708
   3: proc_macro2::fallback::Ident::_new
             at C:\Users\ga29s\.cargo\registry\src\index.crates.io-6f17d22bba15001f\proc-macro2-1.0.36\src\fallback.rs:642
   4: proc_macro2::fallback::Ident::new
             at C:\Users\ga29s\.cargo\registry\src\index.crates.io-6f17d22bba15001f\proc-macro2-1.0.36\src\fallback.rs:652
   5: enum2$<proc_macro2::imp::Ident>::new
             at C:\Users\ga29s\.cargo\registry\src\index.crates.io-6f17d22bba15001f\proc-macro2-1.0.36\src\wrapper.rs:691
   6: proc_macro2::Ident::new
             at C:\Users\ga29s\.cargo\registry\src\index.crates.io-6f17d22bba15001f\proc-macro2-1.0.36\src\lib.rs:952
   7: chiptool::generate::fieldset::render
             at .\src\generate\fieldset.rs:24
   8: chiptool::generate::render
             at .\src\generate\mod.rs:121
   9: chiptool::gen
             at .\src\main.rs:192
  10: chiptool::main
             at .\src\main.rs:105
  11: core::ops::function::FnOnce::call_once<enum2$<core::result::Result<tuple$<>,anyhow::Error> > (*)(),tuple$<> >
             at /rustc/e9e1bbc7a820c472b39d3de54b3049bf14050655\library\core\src\ops\function.rs:250
note: Some details are omitted, run with `RUST_BACKTRACE=full` for a verbose backtrace.
error: process didn't exit successfully: `target\debug\chiptool.exe generate --svd .\field_array_test.svd` (exit code: 101)

Until this is added I can manually modify the SVD file.

It doesn't look like it would take too much to add support for this, but it is late, and I may forget about this before fixing it.

[Dirbaio]

arrays of fields are already supported, you use them like this:

fieldset/MODER:
  description: GPIO port mode register
  fields:
  - name: MODER
    description: Port x configuration bits (y = 0..15)
    bit_offset: 0
    bit_size: 2
    array:
      len: 16
      stride: 2
    enum: MODER

[yodaldevoid]

Sorry, I was not specific enough. I am not talking about merging multiple fields into an array, but instead generating code from an SVD containing a field array already. I've updated my top post to give an example.

[bh1xuw]

Generating register array(and block array) works seamlessly in https://github.com/andelf/hpm-data

The SVD usage should be a <cluster>:

        <cluster>
          <dim>15</dim>
          <dimIncrement>0x10</dimIncrement>
          <dimIndex>gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy</dimIndex>
          <name>DO[%s]</name>
          <description>no description available</description>
          <addressOffset>0x100</addressOffset>
          <register>
            <name>VALUE</name>
            <description>GPIO output value</description>
            <addressOffset>0x0</addressOffset>
            <size>32</size>
            <resetValue>0x00000000</resetValue>
            <resetMask>0xFFFFFFFF</resetMask>
            <fields>
              <field>
                <name>OUTPUT</name>
                <description>GPIO output register value, each bit represents a bus bit
0: chip pin output low level when direction is output
1: chip pin output high level when direction is output</description>
                <bitOffset>0</bitOffset>
                <bitWidth>32</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
 ....