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godson_icache_module.v
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godson_icache_module.v
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "global.h"
`include "bus.h"
module godson_icache_module(
clock,reset,
commitbus_ex,i_laddr,icachepaddr,memres,
dicache,
inst_cache_block,
inst_uncache_block,
PENDING_IBE,IEXI, DERET_IFLAG, iresbus,imemraddr,
IBE_FROM_CACHE
,ram_to_icache,icache_to_ram,
icache_stalli,icache_refill_ok,
//performance counter
icache_access, icache_hit_perf,
icache_update, icache_way_hit,
cache28_refill_ok,
stalled_cycles_icachemiss_o,
cr_cfg7_icache_i,
cr_cfg6_cache0_all_i,
brbus_to_icache
);
input clock,reset;
input commitbus_ex;
input [`Licachepaddr-1:0] icachepaddr;
input [64:0] i_laddr;
input [`Lmemres-1:0] memres;
input [1:0] brbus_to_icache;
input PENDING_IBE;
input IEXI;
input DERET_IFLAG;
input[1:0] cr_cfg7_icache_i;
input cr_cfg6_cache0_all_i;
output [`Liresbus_2issue-1:0] iresbus;//fetch two instruction
output [`Lmemraddr-1:0] imemraddr;
output IBE_FROM_CACHE;
output cache28_refill_ok;
input [`Lram_to_icache-1:0] ram_to_icache;
output [`Licache_to_ram-1:0] icache_to_ram;
input [`Ltlb_to_icache-1:0] dicache; //modified for MIPS32
input inst_cache_block;
input inst_uncache_block;
output icache_stalli, icache_refill_ok;
output icache_hit_perf, icache_access;
output icache_way_hit, icache_update;
output stalled_cycles_icachemiss_o;
//////////////////////////////////////////////////////////////
// transform the memres signals to memres_mid used internally.
wire [53:0] memres_mid;
wire is_block;
reg [7:0] cs_a;
wire memres_dr_dw;
wire [7:0] memres_index;
wire [3:0] memres_width;
wire memres_block_rdy;
wire block_word7;
wire block_rrdy;
wire dw_dr_rrdy;
wire single_rrdy;
////// all fields of cp0_memres_i bus
wire valid = memres[0];
//wire cancel = memres[1];
wire [ 2:0] memres_id = memres[4:2];
wire [ 2:0] counter = memres[7:5];
wire memres_rd_rdy = memres[8];
wire memres_wr_rdy = memres[9];
wire memres_uncache_rdy = memres[10];
wire is_dw = memres[11];
wire [31:0] memres_data = memres[43:12];
assign is_block = (memres_id == 3'b011);
always @(counter)
begin
case(counter)
3'b000:cs_a=8'b00000001;
3'b001:cs_a=8'b00000010;
3'b010:cs_a=8'b00000100;
3'b011:cs_a=8'b00001000;
3'b100:cs_a=8'b00010000;
3'b101:cs_a=8'b00100000;
3'b110:cs_a=8'b01000000;
3'b111:cs_a=8'b10000000;
endcase
end
reg dw_reg;
always @( posedge clock)
if (reset)
dw_reg<=1'b0;
else
if (valid&is_dw)
dw_reg<=~dw_reg;
reg [2:0] base_counter;
always @(posedge clock)
if (reset)
base_counter<=3'b0;
else
if (block_rrdy)
base_counter<=3'b000;
else
if (valid&is_block)
base_counter<=base_counter+1;
assign block_word7=(base_counter[2:0]==3'b111)?1'b1:1'b0;
assign block_rrdy=block_word7&valid&is_block;
assign dw_dr_rrdy=dw_reg&valid&is_dw&(memres_id==3'b111);
assign memres_dr_dw=dw_dr_rrdy;
assign memres_block_rdy=block_rrdy;
assign memres_index={8{is_block}}&cs_a[7:0]&{8{valid}};
assign memres_width=(is_block)?4'b0001:4'b0000;//used only when is_block
wire memres_is_icache = is_block;
assign memres_mid[0] = is_dw&(memres_id==3'b111);// whether is dw.
assign memres_mid[1] = valid;
assign memres_mid[4:2] = counter;
assign memres_mid[5] = memres_is_icache;
assign memres_mid[6] = memres_dr_dw;// indicates directly-read dw
assign memres_mid[7] = memres_rd_rdy;
assign memres_mid[8] = memres_uncache_rdy;
assign memres_mid[9] = memres_block_rdy;
assign memres_mid[17:10] = memres_index;
assign memres_mid[21:18] = memres_width;
assign memres_mid[53:22] = memres_data;
wire[5:0] memres_to_write = {memres_block_rdy , memres_width, memres_is_icache};
//////////////////////////////////////////////////////////////
wire brbus_brvalid = brbus_to_icache[0];
wire brbus_brerr = brbus_to_icache[1];
wire commitbus_ex_br = commitbus_ex | (brbus_brerr&brbus_brvalid);
wire di_valid;
wire [19:0] i_tag;
wire [4:0] i_offset;
wire [6:0] di_index;
wire [21:0] iram_index;
wire cancel_write;
wire [19:0] di_tag; //added for cache16
wire [31:0] di_taglow; //added for cache8
wire di_cache0, di_cache8, di_cache16, di_cache28;
wire [255:0] cacheline_writtendata;
wire read_instr_again;
wire [31:0] imemrqueue_addr;
wire current_imemreq;
wire di_vaddr_dicache_valid;
wire [2:0] icache_v_offset;
/*for way prediction*/
wire way_select0, way_select1, way_select2, way_select3;
wire second_read;
wire[39:0] update_link;
wire update_link_way0, update_link_way1, update_link_way2, update_link_way3;
wire[7:0] data_cen;
wire di_cache28_miss;
wire cache28_refill_ok;
wire [1:0] di_set;
wire i0_tag_match,i0_tag_valid,i1_tag_match,i1_tag_valid;
wire i2_tag_match,i2_tag_valid,i3_tag_match,i3_tag_valid;
wire [31:0] i0_tag,i1_tag;
wire [31:0] i2_tag,i3_tag;
wire [63:0] i0_data,i1_data;
wire [63:0] i2_data,i3_data;
wire i0_lock,i1_lock;
wire i2_lock,i3_lock;
wire cr_icachestate0_value,cr_icachestate1_value;
wire cr_icachestate2_value,cr_icachestate3_value;
wire cache0_validtime0,cache0_validtime1;
wire cache0_validtime2,cache0_validtime3;
icache_control icache_ctrl_4way(.clock(clock),.reset(reset),
.DERET_IFLAG(DERET_IFLAG),
.commitbus_ex(commitbus_ex_br),
.i1_laddr(i_laddr),.icachepaddr(icachepaddr),
.PENDING_IBE(PENDING_IBE),.IEXI(IEXI),
.iresbus(iresbus),.memres(memres_mid),
.imemraddr(imemraddr),
.inst_cache_block(inst_cache_block),
.inst_uncache_block(inst_uncache_block),
.dicache(dicache),
.cr_icachestate0_value(cr_icachestate0_value),
.cr_icachestate1_value(cr_icachestate1_value),
.cr_icachestate2_value(cr_icachestate2_value),
.cr_icachestate3_value(cr_icachestate3_value),
.iram_index(iram_index),
.i_tag(i_tag),.i_offset(i_offset),
.di_valid(di_valid),.di_index(di_index),.di_set(di_set),
.di_tag(di_tag),.di_taglow(di_taglow),
.di_cache0(di_cache0),.di_cache8(di_cache8),
.di_cache16(di_cache16), .di_cache28(di_cache28),
.di_vaddr_dicache_valid(di_vaddr_dicache_valid),
.i0_tag_match(i0_tag_match),.i0_tag_valid(i0_tag_valid),
.i0_tag(i0_tag),.i0_lock(i0_lock),.i0_data(i0_data),
.i1_tag_match(i1_tag_match),.i1_tag_valid(i1_tag_valid),
.i1_tag(i1_tag),.i1_lock(i1_lock),.i1_data(i1_data),
.i2_tag_match(i2_tag_match),.i2_tag_valid(i2_tag_valid),
.i2_tag(i2_tag),.i2_lock(i2_lock),.i2_data(i2_data),
.i3_tag_match(i3_tag_match),.i3_tag_valid(i3_tag_valid),
.i3_tag(i3_tag),.i3_lock(i3_lock),.i3_data(i3_data),
.cr_cfg7_icache_i(cr_cfg7_icache_i),
.cancel_write(cancel_write),
.current_imemreq(current_imemreq),
.imemrqueue_addr(imemrqueue_addr),
.read_instr_again(read_instr_again),
.cacheline_writtendata(cacheline_writtendata),
.cache0_validtime0(cache0_validtime0),
.cache0_validtime1(cache0_validtime1),
.cache0_validtime2(cache0_validtime2),
.cache0_validtime3(cache0_validtime3),
.IBE_FROM_CACHE(IBE_FROM_CACHE),
.icache_v_offset(icache_v_offset),
.way_select0(way_select0),
.way_select1(way_select1),
.way_select2(way_select2),
.way_select3(way_select3),
.second_read(second_read),
.update_link(update_link),
.update_link_way0(update_link_way0),
.update_link_way1(update_link_way1),
.update_link_way2(update_link_way2),
.update_link_way3(update_link_way3),
.data_cen(data_cen),
.di_cache28_miss(di_cache28_miss),
.cache28_refill_ok(cache28_refill_ok),
.icache_stalli(icache_stalli),.icache_refill_ok(icache_refill_ok),
.icache_hit_perf(icache_hit_perf),
.icache_access(icache_access),
.icache_way_hit(icache_way_hit),
.stalled_cycles_icachemiss_o(stalled_cycles_icachemiss_o),
.icache_update(icache_update));
//ICache Read & Write//
//Set 0//
icache_read_write icache_wr0(.clock(clock),.reset(reset),.i_set(2'b00),
.cr_icachestate_value(cr_icachestate0_value),
.iram_index(iram_index),
.icache_v_offset(icache_v_offset),
.i_tag(i_tag),.i_offset(i_offset),
.di_valid(di_valid),.di_index(di_index),.di_set(di_set),
.di_tag(di_tag),.di_taglow(di_taglow),
.di_cache0(di_cache0),.di_cache8(di_cache8),
.di_cache16(di_cache16), .di_cache28(di_cache28),
.di_vaddr_dicache_valid(di_vaddr_dicache_valid),
.memres(memres_to_write),.cancel_write(cancel_write),
.i_tag_match(i0_tag_match),.i_tag_valid(i0_tag_valid),
.i_0_tag(i0_tag),.i_0_lock(i0_lock),.i_0_data(i0_data),
.from_ram(ram_to_icache[287:0]),
.to_ram(icache_to_ram[360:0]),
.current_imemreq(current_imemreq),
.imemrqueue_addr(imemrqueue_addr),
.read_instr_again(read_instr_again),
.cr_cfg6_cache0_all(cr_cfg6_cache0_all_i),
.way_select(way_select0),
.second_read(second_read),
.update_link_way(update_link_way0),
.update_link(update_link),
.cacheline_writtendata(cacheline_writtendata),
.data_cen({data_cen[7:4],data_cen[0]}),
.di_cache28_miss(di_cache28_miss),
.cache0_validtime(cache0_validtime0));
//Set 1//
icache_read_write icache_wr1(.clock(clock),.reset(reset),.i_set(2'b01),
.cr_icachestate_value(cr_icachestate1_value),
.iram_index(iram_index),
.icache_v_offset(icache_v_offset),
.i_tag(i_tag),.i_offset(i_offset),
.di_valid(di_valid),.di_index(di_index),.di_set(di_set),
.di_tag(di_tag),.di_taglow(di_taglow),
.di_cache0(di_cache0),.di_cache8(di_cache8),
.di_cache16(di_cache16), .di_cache28(di_cache28),
.di_vaddr_dicache_valid(di_vaddr_dicache_valid),
.memres(memres_to_write),.cancel_write(cancel_write),
.i_tag_match(i1_tag_match),.i_tag_valid(i1_tag_valid),
.i_0_tag(i1_tag),.i_0_lock(i1_lock),.i_0_data(i1_data),
.from_ram(ram_to_icache[575:288]),
.to_ram(icache_to_ram[721:361]),
.current_imemreq(current_imemreq),
.imemrqueue_addr(imemrqueue_addr),
.read_instr_again(read_instr_again),
.cr_cfg6_cache0_all(cr_cfg6_cache0_all_i),
.way_select(way_select1),
.second_read(second_read),
.update_link_way(update_link_way1),
.update_link(update_link),
.cacheline_writtendata(cacheline_writtendata),
.data_cen({data_cen[7:4],data_cen[1]}),
.di_cache28_miss(di_cache28_miss),
.cache0_validtime(cache0_validtime1));
//Set 2//
icache_read_write icache_wr2(.clock(clock),.reset(reset),.i_set(2'b10),
.cr_icachestate_value(cr_icachestate2_value),
.iram_index(iram_index),
.icache_v_offset(icache_v_offset),
.i_tag(i_tag),.i_offset(i_offset),
.di_valid(di_valid),.di_index(di_index),.di_set(di_set),
.di_tag(di_tag),.di_taglow(di_taglow),
.di_cache0(di_cache0),.di_cache8(di_cache8),
.di_cache16(di_cache16), .di_cache28(di_cache28),
.di_vaddr_dicache_valid(di_vaddr_dicache_valid),
.memres(memres_to_write),.cancel_write(cancel_write),
.i_tag_match(i2_tag_match),.i_tag_valid(i2_tag_valid),
.i_0_tag(i2_tag),.i_0_lock(i2_lock),.i_0_data(i2_data),
.from_ram(ram_to_icache[863:576]),
.to_ram(icache_to_ram[1082:722]),
.current_imemreq(current_imemreq),
.imemrqueue_addr(imemrqueue_addr),
.read_instr_again(read_instr_again),
.cr_cfg6_cache0_all(cr_cfg6_cache0_all_i),
.way_select(way_select2),
.second_read(second_read),
.update_link_way(update_link_way2),
.update_link(update_link),
.data_cen({data_cen[7:4],data_cen[2]}),
.di_cache28_miss(di_cache28_miss),
.cacheline_writtendata(cacheline_writtendata),
.cache0_validtime(cache0_validtime2));
//Set 3//
icache_read_write icache_wr3(.clock(clock),.reset(reset),.i_set(2'b11),
.cr_icachestate_value(cr_icachestate3_value),
.iram_index(iram_index),
.icache_v_offset(icache_v_offset),
.i_tag(i_tag),.i_offset(i_offset),
.di_valid(di_valid),.di_index(di_index),.di_set(di_set),
.di_tag(di_tag),.di_taglow(di_taglow),
.di_cache0(di_cache0),.di_cache8(di_cache8),
.di_cache16(di_cache16), .di_cache28(di_cache28),
.di_vaddr_dicache_valid(di_vaddr_dicache_valid),
.memres(memres_to_write),.cancel_write(cancel_write),
.i_tag_match(i3_tag_match),.i_tag_valid(i3_tag_valid),
.i_0_tag(i3_tag),.i_0_lock(i3_lock),.i_0_data(i3_data),
.from_ram(ram_to_icache[1151:864]),
.to_ram(icache_to_ram[1443:1083]),
.current_imemreq(current_imemreq),
.imemrqueue_addr(imemrqueue_addr),
.read_instr_again(read_instr_again),
.cr_cfg6_cache0_all(cr_cfg6_cache0_all_i),
.way_select(way_select3),
.second_read(second_read),
.update_link_way(update_link_way3),
.update_link(update_link),
.data_cen({data_cen[7:4],data_cen[3]}),
.di_cache28_miss(di_cache28_miss),
.cacheline_writtendata(cacheline_writtendata),
.cache0_validtime(cache0_validtime3));
endmodule
//////////////////////////////////////////////////////////////////////
// //
// Instruction Cache Control Module //
// //
//////////////////////////////////////////////////////////////////////
module icache_control(clock,reset,commitbus_ex,i1_laddr,
icachepaddr,iresbus,memres,imemraddr,dicache,
inst_cache_block, inst_uncache_block,
cr_icachestate0_value,cr_icachestate1_value,
cr_icachestate2_value,cr_icachestate3_value,
iram_index,i_tag,i_offset,
di_valid,di_index,di_set,cancel_write,
di_tag,di_taglow,di_cache0,di_cache8,di_cache16,di_cache28,
di_vaddr_dicache_valid,
i0_tag_match,i0_tag_valid,i0_tag,i0_lock,i0_data,
i1_tag_match,i1_tag_valid,i1_tag,i1_lock,i1_data,
i2_tag_match,i2_tag_valid,i2_tag,i2_lock,i2_data,
i3_tag_match,i3_tag_valid,i3_tag,i3_lock,i3_data,
cr_cfg7_icache_i,
PENDING_IBE,IEXI,
DERET_IFLAG,
current_imemreq,
imemrqueue_addr,
cacheline_writtendata,
read_instr_again,
cache0_validtime0,
cache0_validtime1,
cache0_validtime2,
cache0_validtime3,
IBE_FROM_CACHE,
icache_v_offset,
way_select0,way_select1, way_select2,way_select3,
second_read, update_link,
update_link_way0, update_link_way1,update_link_way2, update_link_way3,
//for critical path
data_cen,
di_cache28_miss,
cache28_refill_ok,
icache_stalli, icache_refill_ok,
//performance counter
icache_hit_perf,
icache_access,
icache_way_hit,
stalled_cycles_icachemiss_o,
icache_update
);
input clock,reset,commitbus_ex;
input [`Licachepaddr-1:0] icachepaddr;
input [64:0] i1_laddr;
input [53:0] memres;
input [`Ltlb_to_icache-1:0] dicache;
input inst_cache_block;
input inst_uncache_block;
input PENDING_IBE,IEXI;
input DERET_IFLAG;
output [`Liresbus_2issue-1:0] iresbus;
output [`Lmemraddr-1:0] imemraddr;
output[2:0] icache_v_offset;
input [31:0] i0_tag ,i1_tag, i2_tag, i3_tag;
input i0_lock,i1_lock,i2_lock,i3_lock;
input [63:0] i0_data,i1_data,i2_data,i3_data;
input i0_tag_match,i1_tag_match,i2_tag_match,i3_tag_match;
input i0_tag_valid,i1_tag_valid,i2_tag_valid,i3_tag_valid;
input cache0_validtime0,cache0_validtime1,cache0_validtime2,cache0_validtime3;
input [ 1:0] cr_cfg7_icache_i;
output cr_icachestate0_value,cr_icachestate1_value;
output cr_icachestate2_value,cr_icachestate3_value;
output di_valid;
output [19:0] i_tag, di_tag; //added for cache16
output [4:0] i_offset;
output [6:0] di_index;
output [21:0] iram_index;
output [1:0] di_set;
output cancel_write;
output [31:0] di_taglow; //added for cache8
output di_cache0, di_cache8, di_cache16, di_cache28;
output di_vaddr_dicache_valid;
output [31:0] imemrqueue_addr;
output [255:0] cacheline_writtendata;
output read_instr_again;
output current_imemreq;
output IBE_FROM_CACHE;
//for data read
output way_select0, way_select1;
output way_select2, way_select3;
/*for way predict miss and then read the hit data way */
output second_read;
output[39:0] update_link;
output update_link_way0, update_link_way1;
output update_link_way2, update_link_way3;
//for critical path
output[7:0] data_cen;
//for cache28 miss
output di_cache28_miss;
output cache28_refill_ok;
output icache_stalli, icache_refill_ok;
//for performance counter
output icache_hit_perf;
output icache_access;
output stalled_cycles_icachemiss_o;
output icache_way_hit;
output icache_update;
wire icachepaddr_valid_t; // it has no insout_valid, for critical path
wire icachepaddr_valid;
wire icachepaddr_cached;
wire [31:0] icachepaddr_addr;
wire icachepaddr_adei;
wire icachepaddr_tlbii;
wire icachepaddr_tlbir;
wire icachepaddr_dib_0;
wire icachepaddr_dib_1;
wire pred_no_update; //when prediction came from RAS or inline sequential, needn't update link
wire[1:0] pred_way_hit; //the way link info came from
wire[9:0] pred_link_info; //all the link info (five)
wire[19:0] pred_link_tag; //the tag where link info came form
wire[1:0] pred_link_offset; //for select which no_sequential link for update
wire[6:0] pred_link_index; //the index where link info came from
wire pred_seq_link; //wether the link info is sequential link
wire[1:0] pred_v_lock;
wire irstalli;
wire pc_en_nowayhit; //pc_in_en = pc_en_nowayhit | iresbus_way_hit
wire[1:0] way_pred ;
wire pc_in_en;
wire [11:0] i_laddr;
wire di_vaddr_cache28;
wire di_vaddr_cache16;
wire di_vaddr_valid;
wire[6:0] di_vaddr_index;
wire [63:0] iresbus_value; //for two instructions
wire iresbus_valid_0;
wire iresbus_cacherdy_0;
wire [31:0] iresbus_value_0;
wire iresbus_adei_0;
wire iresbus_tlbii_0;
wire iresbus_tlbir_0;
wire iresbus_ibe_0;
wire iresbus_dib_0;
wire iresbus_valid_1;
wire iresbus_cacherdy_1;
wire [31:0] iresbus_value_1;
wire iresbus_adei_1;
wire iresbus_tlbii_1;
wire iresbus_tlbir_1;
wire iresbus_ibe_1;
wire iresbus_dib_1;
//send them to fetch, for way prediction miss recover
wire[11:0] link_info_t; //11: valid, 10: lock
wire[9:0] iresbus_link_info;
wire[1:0] iresbus_way_hit;
wire[19:0] iresbus_paddr_tag;
wire[1:0] iresbus_v_lock;
wire iresbus_no_update;
wire iresbus_one_word;//for no dw align
reg cacheline_keyto8;
reg read_instr_again;
wire imemraddr_valid;
wire [3:0] imemraddr_width;
wire [31:0] imemraddr_addr;
wire [2:0] imemraddr_id;
assign icachepaddr_valid_t =icachepaddr[39];
assign icachepaddr_dib_1=icachepaddr[38];
assign icachepaddr_dib_0=icachepaddr[37];
assign icachepaddr_valid=icachepaddr[36];
assign icachepaddr_cached=icachepaddr[35];
assign icachepaddr_addr=icachepaddr[34:3];
assign icachepaddr_adei=icachepaddr[2];
assign icachepaddr_tlbii=icachepaddr[1];
assign icachepaddr_tlbir=icachepaddr[0];
wire [21:0] iram_index;
wire [31:0] i_addr;
assign pc_en_nowayhit = i1_laddr[64];
assign irstalli = i1_laddr[63];
assign pred_v_lock = i1_laddr[62:61];
assign pred_no_update = i1_laddr[60:60];
assign pred_way_hit = i1_laddr[59:58];
assign pred_link_info = i1_laddr[57:48]; //all the link information which current way prediction come from
assign pred_link_tag = i1_laddr[47:28]; //the physical tag which which current way prediction come from
assign pred_link_index = i1_laddr[27:21]; //select current way prediction come from which noseq link info
assign pred_link_offset = i1_laddr[20:19];//the index which current way_prediction come from
assign pred_seq_link = i1_laddr[15]; //wether current way prediction is sequential link/
assign way_pred = i1_laddr[14:13]; // current way prediction
assign pc_in_en = i1_laddr[12];
assign i_laddr = i1_laddr[11:0];
assign icache_v_offset = pc_en_nowayhit ? i_laddr[4:2] : i_addr[4:2]; //for bank read
//: read_instr_again
wire[31:0] di_paddr = dicache[34:3];
assign di_vaddr_cache28 = dicache[79]; //vaddr cache28
assign di_cache28 = dicache[78]; //paddr cache28
assign di_vaddr_cache16 = dicache[77];
assign di_vaddr_valid = dicache[76];
assign di_vaddr_index = dicache[75:69];
assign di_taglow = dicache[68:37]; //added for cache8
assign di_valid = dicache[36];
assign di_tag = dicache[34:15]; //added for cache16, hit invlaid
assign di_index = dicache[14:8];
assign di_set = dicache[81:80];
assign di_cache16 = dicache[2];
assign di_cache8 = dicache[1];
assign di_cache0 = dicache[0];
wire memres_is_dw = memres[0];
wire memres_valid = memres[1];
wire[2:0] memres_counter = memres[4:2];
wire memres_is_icache = memres[5] ;
wire memres_dr_dw = memres[6] ;
wire memres_rd_rdy = memres[7] ;
wire memres_uncache_rdy = memres[8] ;
wire memres_block_rdy = memres[9] ;
wire[7 :0]memres_index = memres[17:10];
wire[3 :0]memres_width = memres[21:18];
wire[31:0]memres_data = memres[53:22] ;
assign iresbus[113] = iresbus_one_word; // when data come from returning and uncached, we needn't update link
assign iresbus[112] = iresbus_no_update; // when data come from returning and uncached, we needn't update link
assign iresbus[111:110] = iresbus_v_lock; // tag's valid bits of current fetch
assign iresbus[109:90] = iresbus_paddr_tag; //paddr of current fetch
assign iresbus[89:88] = iresbus_way_hit; //hit way of current fetch
assign iresbus[87:78] = iresbus_link_info; //link information for way predictiom miss recover
assign iresbus[77]=iresbus_dib_1;
assign iresbus[76]=iresbus_valid_1;
assign iresbus[75]=iresbus_cacherdy_1;
assign iresbus[74:43]=iresbus_value_1;
assign iresbus[42]=iresbus_ibe_1;
assign iresbus[41]=iresbus_adei_1;
assign iresbus[40]=iresbus_tlbii_1;
assign iresbus[39]=iresbus_tlbir_1;
assign iresbus[38]=iresbus_dib_0;
assign iresbus[37]=iresbus_valid_0;
assign iresbus[36]=iresbus_cacherdy_0;
assign iresbus[35:4]=iresbus_value_0;
assign iresbus[3]=iresbus_ibe_0;
assign iresbus[2]=iresbus_adei_0;
assign iresbus[1]=iresbus_tlbii_0;
assign iresbus[0]=iresbus_tlbir_0;
assign imemraddr[39:37]=imemraddr_id;
assign imemraddr[36]=imemraddr_valid;
assign imemraddr[35:32]=imemraddr_width;
assign imemraddr[31:0]=imemraddr_addr;
wire i_valid,i_cached,i_valid_t;
wire [19:0] i_tag; //physical tag
wire [4 :0] i_offset;
wire [31:0] i0_tag, i1_tag, i2_tag, i3_tag;
wire i0_lock,i1_lock,i2_lock,i3_lock;
wire [63:0] i1_data,i0_data,i3_data,i2_data;
wire i0_tag_match,i1_tag_match,i2_tag_match,i3_tag_match;
wire i0_tag_valid,i1_tag_valid,i2_tag_valid,i3_tag_valid;
reg imemrqueue_valid;
reg [31:0] imemrqueue_addr;
reg imemrqueue_dr;
reg[1:0] imemrqueue_way; //for refill way
reg imemrqueue_cache28_miss;
reg miss_update_link; //for cache miss, need update link
reg fake_icache_hit;
wire i0_match = i0_tag_match& (i0_tag_valid& ~fake_icache_hit);
wire i1_match = i1_tag_match& (i1_tag_valid& ~fake_icache_hit);
wire i2_match = i2_tag_match& (i2_tag_valid& ~fake_icache_hit);
wire i3_match = i3_tag_match& (i3_tag_valid& ~fake_icache_hit);
wire icache_hit = i0_match | i1_match | i2_match | i3_match;
wire imemres_flag;
reg cr_icachestate0,cr_icachestate1,cr_icachestate2,cr_icachestate3,cr_icachestate5;
wire [1:0] select_set;
wire cr_icachestate0_value=cr_icachestate0;
wire cr_icachestate1_value=cr_icachestate1;
wire cr_icachestate2_value=cr_icachestate2;
wire cr_icachestate3_value=cr_icachestate3;
wire cr_icachestate5_value=cr_icachestate5;
wire ireq_block = i_cached&inst_cache_block | ~i_cached&inst_uncache_block;
assign icache_refill_ok = imemres_flag;
assign icache_stalli = imemrqueue_valid &~imemres_flag | imemraddr_valid&~ireq_block;
/*****************************for way predictiion****************************/
reg second_hit; //when cache hit but way prediction miss, direct the second hit
reg[1:0] second_hit_way; //direct second hit way, because when second read, do link update. after link update, may be has two way match. we need know the right hit way
reg[1:0] way_pred_reg; //current way prediction for judge whether way prediction miss and for second read
reg[6:0] link_index_reg; //for link update
reg[1:0] link_offset_reg;
reg[19:0] link_tag_reg;
reg link_seq_reg;
reg[9:0] link_info_reg;
reg[1:0] link_way_reg;
reg[1:0] link_v_lock_reg;
reg update_link_en;
wire[31:0] update_link_value;
wire icache_hit_way_0, icache_hit_way_1,icache_hit_way_2,icache_hit_way_3;
always @ (posedge clock)
if(pc_in_en)
begin
way_pred_reg <= way_pred;
link_index_reg<= pred_link_index;
link_offset_reg<= pred_link_offset;
link_tag_reg<= pred_link_tag;
link_info_reg<= pred_link_info;
link_seq_reg <= pred_seq_link;
link_way_reg <= pred_way_hit;
link_v_lock_reg <= pred_v_lock;
//if link come from ex, jr31, inline seq, needn't update link info.
//and if new instr fetch and refill cache conflict, needn't update link. Because, the new cache line may be refill into the cache line which link came from
update_link_en <= ~(commitbus_ex | reset | pred_no_update) ;
end
wire way_pred_hit0 = i0_match & (way_pred_reg==2'b00) ;
wire way_pred_hit1 = i1_match & (way_pred_reg==2'b01) ;
wire way_pred_hit2 = i2_match & (way_pred_reg==2'b10) ;
wire way_pred_hit3 = i3_match & (way_pred_reg==2'b11) ;
wire way_pred_hit = way_pred_hit0 | way_pred_hit1 | way_pred_hit2 | way_pred_hit3;
wire way_pred_miss = ~(i0_match &(way_pred_reg==2'b00)|
i1_match &(way_pred_reg==2'b01)|
i2_match &(way_pred_reg==2'b10)|
i3_match &(way_pred_reg==2'b11));
assign icache_hit_way_0 = i0_match& (way_pred_reg!=2'b00);
assign icache_hit_way_1 = i1_match& (way_pred_reg!=2'b01);
assign icache_hit_way_2 = i2_match& (way_pred_reg!=2'b10);
assign icache_hit_way_3 = i3_match& (way_pred_reg!=2'b11);
wire way_select0 = pc_en_nowayhit ? (way_pred == 2'b00) :
read_instr_again ? (way_pred_reg == 2'b00) : icache_hit_way_0 ;
wire way_select1 = pc_en_nowayhit ? (way_pred == 2'b01) :
read_instr_again ? (way_pred_reg == 2'b01) : icache_hit_way_1 ;
wire way_select2 = pc_en_nowayhit ? (way_pred == 2'b10) :
read_instr_again ? (way_pred_reg == 2'b10) : icache_hit_way_2 ;
wire way_select3 = pc_en_nowayhit ? (way_pred == 2'b11) :
read_instr_again ? (way_pred_reg == 2'b11) : icache_hit_way_3 ;
wire way_select0_t = (way_pred == 2'b00);
wire way_select1_t = (way_pred == 2'b01);
wire way_select2_t = (way_pred == 2'b10);
wire way_select3_t = (way_pred == 2'b11);
wire imemres_wayhit;
assign data_cen[3:0] = {way_select3_t,way_select2_t,way_select1_t,way_select0_t};
assign data_cen[4] = imemres_wayhit;
assign data_cen[7:5] = i_laddr[4:2];
wire iresbus_returning_cacheline_hit;
assign second_read = (~reset&~commitbus_ex&~irstalli & i_cached & i_valid & ~read_instr_again & ~second_hit
&~(imemres_flag & ~imemrqueue_dr)) & way_pred_miss & icache_hit;
//when refill and second read conflict, needn't second read. just read instruction again
assign update_link_value[31:30] = link_v_lock_reg;
assign update_link_value[29:28] = ~link_seq_reg ? link_info_reg[9:8] :
icache_hit_way_0 ? 2'b00 :
icache_hit_way_1 ? 2'b01 :
icache_hit_way_2 ? 2'b10 :
icache_hit_way_3 ? 2'b11 : imemrqueue_way; //for cache miss
assign update_link_value[27:26] = (~(link_offset_reg == 2'b11)& ~link_seq_reg | link_seq_reg) ? link_info_reg[7:6] :
icache_hit_way_0 ? 2'b00 :
icache_hit_way_1 ? 2'b01 :
icache_hit_way_2 ? 2'b10 :
icache_hit_way_3 ? 2'b11 : imemrqueue_way;
assign update_link_value[25:24] = (~(link_offset_reg == 2'b10)& ~link_seq_reg | link_seq_reg) ? link_info_reg[5:4] :
icache_hit_way_0 ? 2'b00 :
icache_hit_way_1 ? 2'b01 :
icache_hit_way_2 ? 2'b10 :
icache_hit_way_3 ? 2'b11 : imemrqueue_way;
assign update_link_value[23:22] = (~(link_offset_reg == 2'b01)& ~link_seq_reg | link_seq_reg) ? link_info_reg[3:2] :
icache_hit_way_0 ? 2'b00 :
icache_hit_way_1 ? 2'b01 :
icache_hit_way_2 ? 2'b10 :
icache_hit_way_3 ? 2'b11 : imemrqueue_way;
assign update_link_value[21:20] = (~(link_offset_reg == 2'b00)& ~link_seq_reg | link_seq_reg) ? link_info_reg[1:0] :
icache_hit_way_0 ? 2'b00 :
icache_hit_way_1 ? 2'b01 :
icache_hit_way_2 ? 2'b10 :
icache_hit_way_3 ? 2'b11 : imemrqueue_way;
assign update_link_value[19:0] = link_tag_reg;
wire update_link_way0, update_link_way1, update_link_way2, update_link_way3;
wire [39:0] update_link;
reg[6:0] refill_index_reg_0;
reg[1:0] refill_way_reg_0;
reg[6:0] refill_index_reg_1;
reg[1:0] refill_way_reg_1;
assign update_link_way0 = (link_way_reg == 2'b00);
assign update_link_way1 = (link_way_reg == 2'b01);
assign update_link_way2 = (link_way_reg == 2'b10);
assign update_link_way3 = (link_way_reg == 2'b11);
assign update_link[39:33] = link_index_reg;
assign update_link[32] = (update_link_en &
//~((imemrqueue_addr[11:5] == link_index_reg)&(imemrqueue_way == link_way_reg))&
~((refill_index_reg_0 == link_index_reg)&(link_way_reg == refill_way_reg_0)) &
~((refill_index_reg_1 == link_index_reg)&(link_way_reg == refill_way_reg_1)) ) &
//when dealing refill cache line has wrong link, needn't update
( second_read | miss_update_link&~commitbus_ex) ;
//when way prediction miss and cache miss, update link
assign update_link[31:0] = update_link_value;
always@(posedge clock)
begin
if(reset)
begin
refill_index_reg_0 <= 7'b0;
refill_way_reg_0 <= 2'b0;
refill_index_reg_1 <= 7'b0;
refill_way_reg_1 <= 2'b0;
end
else if (imemres_flag)
begin
refill_index_reg_0 <= imemrqueue_addr[11:5];
refill_way_reg_0 <= imemrqueue_way;
refill_index_reg_1 <= refill_index_reg_0;
refill_way_reg_1 <= refill_way_reg_0;
end
else if (update_link[32])
begin
refill_index_reg_0 <= 7'b0;
refill_way_reg_0 <= 2'b0;
refill_index_reg_1 <= 7'b0;
refill_way_reg_1 <= 2'b0;
end
end
always @(posedge clock)
if (pc_in_en | read_instr_again)
begin
second_hit<=1'b0;
second_hit_way <= 2'b00;
end
else if (second_read)
begin
second_hit <= 1'b1;
second_hit_way <= way_select0 ? 2'b00:
way_select1 ? 2'b01:
way_select2 ? 2'b10: 2'b11;
end
reg icache_miss;
always @ (posedge clock)
if (pc_in_en | read_instr_again)
fake_icache_hit <=0;
else if (update_link[32])
fake_icache_hit <= 1;
//for performance counter
reg pc_in_en_r;
always @(posedge clock)
pc_in_en_r <= pc_in_en;
assign icache_hit_perf = icache_hit & pc_in_en_r & i_cached;
assign icache_access = pc_in_en_r & i_cached;
assign icache_way_hit = way_pred_hit & pc_in_en_r & i_cached;
assign icache_update = update_link[32] ;
/*************************************************************************************/
wire i_mem_allow;
//icachepaddr_valid = icachepaddr_valid_t&instout_valid
assign i_valid= (icachepaddr_valid&(~icachepaddr_tlbii)&(~icachepaddr_tlbir)&(~icachepaddr_dib_0) )&
(~icachepaddr_adei);
assign i_valid_t= (icachepaddr_valid_t&(~icachepaddr_tlbii)&(~icachepaddr_tlbir)&(~icachepaddr_dib_0) )&
(~icachepaddr_adei);
//when dib and cache miss ,it still mem
assign i_addr=icachepaddr_addr;
assign i_tag=i_addr[31:12];
assign i_offset=i_addr[4:0];
assign i_cached=icachepaddr_cached;
//to cache_read_write for rw_index
assign iram_index[0] = pc_en_nowayhit ;
assign iram_index[7:1] = i_laddr[11:5];
assign iram_index[14:8] = i_addr[11:5];
assign iram_index[21:15] = di_vaddr_index;
assign di_vaddr_dicache_valid = di_vaddr_valid&(di_vaddr_cache16 | di_vaddr_cache28);
//when cache 28 miss, then need refill this cache line
wire cache28_miss_t = di_valid&di_cache28&
~((di_tag == i3_tag[19:0])&i3_tag_valid| (di_tag == i2_tag[19:0])&i2_tag_valid|
(di_tag == i1_tag[19:0])&i1_tag_valid| (di_tag == i0_tag[19:0])&i0_tag_valid);
wire cache28_hit = di_valid&di_cache28&
((di_tag == i3_tag[19:0])&i3_tag_valid| (di_tag == i2_tag[19:0])&i2_tag_valid|
(di_tag == i1_tag[19:0])&i1_tag_valid| (di_tag == i0_tag[19:0])&i0_tag_valid);
wire icache_miss_t = i_valid&i_cached& ~read_instr_again &~irstalli & ~icache_hit&~second_hit | cache28_miss_t;
reg cache28_miss;
wire i_dr=i_valid&(~i_cached);
assign i_mem_allow=(~cr_icachestate0_value)&(~cr_icachestate1_value)&(~cr_icachestate2_value)&(~cr_icachestate3_value)&
(~cr_icachestate5_value)&~read_instr_again&
(memres_rd_rdy&i_cached | memres_rd_rdy&memres_uncache_rdy&~i_cached);
//Send Read Memory Request//
assign imemraddr_valid=i_mem_allow & icache_miss ;
assign imemraddr_addr= cache28_miss ? di_paddr : i_addr;
assign imemraddr_width=cache28_miss ? 4'b0001: {3'b000, i_cached} | {4{~i_cached}};
assign imemraddr_id=(cache28_miss | i_cached) ? 3'b011 : 3'b111;
wire [1:0] cr_iset_value = select_set;
always @(posedge clock)
if (reset)
begin
imemrqueue_valid <=1'b0;
imemrqueue_addr <=32'b0;
imemrqueue_dr <=1'b0;
imemrqueue_way <=2'b0;
miss_update_link <=1'b0;
imemrqueue_cache28_miss <=1'b0;
end
else
begin
if (imemraddr_valid&(~ireq_block))
imemrqueue_valid<=1'b1;
else
if (imemres_flag|iresbus_ibe_0)
begin
imemrqueue_valid<=1'b0;
imemrqueue_cache28_miss <= 1'b0;
end
if (imemraddr_valid&~ireq_block)
begin
imemrqueue_addr<=imemraddr_addr;
imemrqueue_dr<=i_dr;