Power-on-reset needs to be robust to late 1.8V supply power-up

[RTimothyEdwards]

The existing power-on-reset circuit is only connected to VDDIO and does not monitor the 1.8V supply. It was designed with the expectation that the 1.8V supply comes up directly after the 3.3V supply, as it would in the normal setup where an off-chip 1.8V LDO is running off of the 3.3V power supply. The timing of the existing LDO is meant to cover the delay between the 3.3V supply and the 1.8V supply. However, if the 1.8V supply is provided independently and is raised after the POR has already triggered, and the RESETB pin is left floating (with a pull-up to VDDIO) then the entire digital system will attempt to start running as soon as it reaches the digital threshold. This is an uncontrolled startup sequence and has been shown to fail in silicon testing at less than or approximately 0 degrees C.

The best solution is to add a secondary POR to the 1.8V supply and to gate the digital system reset with its output. The POR can be the same base circuit as the existing POR but without the level shifter at the end. It will be necessary to create a 1.8V schmitt-trigger inverter, as I don't think there is one in the existing PDK 1.8V standard cell libraries.