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kvm_svm.c
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kvm_svm.c
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/*
* Kernel-based Virtual Machine driver for Linux
*
* AMD SVM support
*
* Copyright (C) 2006 Qumranet, Inc.
*
* Authors:
* Yaniv Kamay <[email protected]>
* Avi Kivity <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Copyright 2011 Joshua M. Clulow <[email protected]>
* Copyright 2011 Richard Lowe
*/
#include <sys/sysmacros.h>
#include <sys/types.h>
#include <sys/mach_mmu.h>
#include <asm/cpu.h>
#include <sys/x86_archext.h>
#include <sys/xc_levels.h>
#include <sys/ddi.h>
#include <sys/sunddi.h>
#include <sys/machsystm.h>
#include "kvm_bitops.h"
#include "kvm_msr.h"
#include "kvm_cpuid.h"
#include "kvm_impl.h"
#include "kvm_x86impl.h"
#include "kvm_cache_regs.h"
#include "kvm_host.h"
#include "kvm_iodev.h"
#include "kvm_irq.h"
#include "kvm_mmu.h"
#include "kvm_svm.h"
#include "kvm_glue_alloc.h"
#define __ex(x) __kvm_handle_fault_on_reboot(x)
static kmem_cache_t *kvm_svm_vcpu_cache = NULL;
static kmem_cache_t *kvm_svm_vmcb_cache = NULL;
static kmem_cache_t *kvm_svm_msrpm_cache = NULL;
static kmem_cache_t *kvm_svm_cpudata_cache = NULL;
static kmem_cache_t *kvm_svm_savearea_cache = NULL;
/* per-CPU structure: */
static struct svm_cpu_data **kvm_svm_cpu_data;
#define IOPM_ALLOC_ORDER 2
#define MSRPM_ALLOC_ORDER 1
#define SEG_TYPE_LDT 2
#define SEG_TYPE_BUSY_TSS16 3
#define SVM_FEATURE_NPT (1 << 0)
#define SVM_FEATURE_LBRV (1 << 1)
#define SVM_FEATURE_SVML (1 << 2)
#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
static const uint32_t host_save_user_msrs[] = {
MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
MSR_FS_BASE,
MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
};
struct vmcb_control_area {
uint16_t intercept_cr_read;
uint16_t intercept_cr_write;
uint16_t intercept_dr_read;
uint16_t intercept_dr_write;
uint32_t intercept_exceptions;
uint64_t intercept;
uint8_t reserved_1[42];
uint16_t pause_filter_count;
uint64_t iopm_base_pa;
uint64_t msrpm_base_pa;
uint64_t tsc_offset;
uint32_t asid;
uint8_t tlb_ctl;
uint8_t reserved_2[3];
uint32_t int_ctl;
uint32_t int_vector;
uint32_t int_state;
uint8_t reserved_3[4];
uint32_t exit_code;
uint32_t exit_code_hi;
uint64_t exit_info_1;
uint64_t exit_info_2;
uint32_t exit_int_info;
uint32_t exit_int_info_err;
uint64_t nested_ctl;
uint8_t reserved_4[16];
uint32_t event_inj;
uint32_t event_inj_err;
uint64_t nested_cr3;
uint64_t lbr_ctl;
uint8_t reserved_5[832];
} __attribute__((__packed__));
struct vmcb_seg {
uint16_t selector;
uint16_t attrib;
uint32_t limit;
uint64_t base;
} __attribute__((__packed__));
struct vmcb_save_area {
struct vmcb_seg es;
struct vmcb_seg cs;
struct vmcb_seg ss;
struct vmcb_seg ds;
struct vmcb_seg fs;
struct vmcb_seg gs;
struct vmcb_seg gdtr;
struct vmcb_seg ldtr;
struct vmcb_seg idtr;
struct vmcb_seg tr;
uint8_t reserved_1[43];
uint8_t cpl;
uint8_t reserved_2[4];
uint64_t efer;
uint8_t reserved_3[112];
uint64_t cr4;
uint64_t cr3;
uint64_t cr0;
uint64_t dr7;
uint64_t dr6;
uint64_t rflags;
uint64_t rip;
uint8_t reserved_4[88];
uint64_t rsp;
uint8_t reserved_5[24];
uint64_t rax;
uint64_t star;
uint64_t lstar;
uint64_t cstar;
uint64_t sfmask;
uint64_t kernel_gs_base;
uint64_t sysenter_cs;
uint64_t sysenter_esp;
uint64_t sysenter_eip;
uint64_t cr2;
uint8_t reserved_6[32];
uint64_t g_pat;
uint64_t dbgctl;
uint64_t br_from;
uint64_t br_to;
uint64_t last_excp_from;
uint64_t last_excp_to;
} __attribute__((__packed__));
struct vmcb {
struct vmcb_control_area control;
struct vmcb_save_area save;
} __attribute__((__packed__));
struct kvm_vcpu;
#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
typedef struct vcpu_svm {
struct kvm_vcpu vcpu;
struct vmcb *vmcb;
uint64_t vmcb_pa; /* physical address of svm's vmcb */
struct svm_cpu_data *svm_data;
uint64_t asid_generation;
uint64_t sysenter_esp;
uint64_t sysenter_eip;
uint64_t next_rip;
uint64_t host_user_msrs[NR_HOST_SAVE_USER_MSRS];
uint64_t host_gs_base;
uint32_t *msrpm;
char nmi_singlestep;
} vcpu_svm_t;
static int kvm_svm_has_kvm_support_override = 0;
static char npt_enabled = 1;
static int npt = 1;
/* module_param(npt, int, S_IRUGO); */
static void svm_flush_tlb(struct kvm_vcpu *vcpu);
static void svm_complete_interrupts(struct vcpu_svm *svm);
static struct vcpu_svm *
to_svm(struct kvm_vcpu *vcpu)
{
return ((struct vcpu_svm *)((uintptr_t)vcpu -
offsetof(struct vcpu_svm, vcpu)));
}
static void
enable_gif(struct vcpu_svm *svm)
{
svm->vcpu.arch.hflags |= HF_GIF_MASK;
}
static void
disable_gif(struct vcpu_svm *svm)
{
svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
}
static char
gif_set(struct vcpu_svm *svm)
{
return (!!(svm->vcpu.arch.hflags & HF_GIF_MASK));
}
static unsigned long iopm_base;
static void *iopm_va;
struct svm_cpu_data {
int cpu;
uint64_t asid_generation;
uint32_t max_asid;
uint32_t next_asid;
void *save_area;
uint64_t save_area_pa;
};
static uint32_t svm_features;
struct svm_init_data {
int cpu;
int r;
};
static uint32_t msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
#define MSRS_RANGE_SIZE 2048
#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
#define MAX_INST_SIZE 15
static char
svm_has(uint32_t feat)
{
return (!!(svm_features & feat));
}
static void
cpu_svm_disable(void)
{
uint64_t efer;
wrmsrl(MSR_VM_HSAVE_PA, 0);
rdmsrl(MSR_EFER, efer);
wrmsrl(MSR_EFER, efer & ~EFER_SVME);
}
static int
cpuid_ebx(unsigned int op)
{
struct cpuid_regs cp;
cp.cp_eax = op;
cp.cp_ecx = 0;
(void) __cpuid_insn(&cp);
return (cp.cp_ebx);
}
static int
cpuid_edx(unsigned int op)
{
struct cpuid_regs cp;
cp.cp_eax = op;
cp.cp_ecx = 0;
(void) __cpuid_insn(&cp);
return (cp.cp_edx);
}
/*
* CLGI: clear global interrupt flag
*/
static void
clgi(void)
{
__asm__ volatile(__ex(SVM_CLGI));
}
/*
* STGI: set global interrupt flag
*/
static void
stgi(void)
{
__asm__ volatile(__ex(SVM_STGI));
}
/*
* INVLPGA: invalidate TLB mapping for given virtual page + asid
*/
static void invlpga(unsigned long addr, uint32_t asid)
{
__asm__ volatile(__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
}
static void
force_new_asid(struct kvm_vcpu *vcpu)
{
to_svm(vcpu)->asid_generation--;
}
static void
flush_guest_tlb(struct kvm_vcpu *vcpu)
{
force_new_asid(vcpu);
}
static void
svm_set_efer(struct kvm_vcpu *vcpu, uint64_t efer)
{
if (!npt_enabled && !(efer & EFER_LMA))
efer &= ~EFER_LME;
to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
vcpu->arch.efer = efer;
}
static void
svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
int has_error_code, uint32_t error_code)
{
struct vcpu_svm *svm = to_svm(vcpu);
svm->vmcb->control.event_inj = nr
| SVM_EVTINJ_VALID
| (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
| SVM_EVTINJ_TYPE_EXEPT;
svm->vmcb->control.event_inj_err = error_code;
}
static int
is_external_interrupt(uint32_t intr_info)
{
return ((intr_info & (SVM_EVTINJ_TYPE_MASK |
SVM_EVTINJ_VALID)) == (SVM_EVTINJ_VALID |
SVM_EVTINJ_TYPE_INTR));
}
static uint32_t
svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
{
struct vcpu_svm *svm = to_svm(vcpu);
uint32_t ret = 0;
if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
return (ret & mask);
}
static void
svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
{
struct vcpu_svm *svm = to_svm(vcpu);
if (mask == 0)
svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
else
svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
}
static void
skip_emulated_instruction(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
if (!svm->next_rip) {
if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
EMULATE_DONE)
cmn_err(CE_NOTE, "%s: NOP\n", __func__);
return;
}
if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
cmn_err(CE_WARN, "%s: ip 0x%lx next 0x%llx\n",
__func__, kvm_rip_read(vcpu), (long long unsigned)svm->next_rip);
kvm_rip_write(vcpu, svm->next_rip);
svm_set_interrupt_shadow(vcpu, 0);
}
static int
kvm_svm_has_kvm_support(void)
{
if (kvm_svm_has_kvm_support_override)
return (kvm_svm_has_kvm_support_override > 0 ? 0 : -1);
if (is_x86_feature(x86_featureset, X86FSET_SVM))
return (0);
return (-1);
}
static void
svm_hardware_disable(void *garbage)
{
cpu_svm_disable();
}
static int
svm_hardware_enable(void *garbage)
{
struct svm_cpu_data *sd;
uint64_t efer;
int cpu = curthread->t_cpu->cpu_seqid;
rdmsrl(MSR_EFER, efer);
if (efer & EFER_SVME)
return (DDI_FAILURE);
sd = kvm_svm_cpu_data[cpu];
if (!sd) {
cmn_err(CE_WARN, "svm_hardware_enable: svm_data is "
"NULL on %d\n", cpu);
return (DDI_FAILURE);
}
sd->asid_generation = 1;
sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
sd->next_asid = sd->max_asid + 1;
wrmsrl(MSR_EFER, efer | EFER_SVME);
wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa);
return (0);
}
static void
svm_cpu_uninit(int cpu)
{
struct svm_cpu_data *sd = kvm_svm_cpu_data[cpu];
if (!sd)
return;
kvm_svm_cpu_data[cpu] = NULL;
kmem_cache_free(kvm_svm_savearea_cache, sd->save_area);
kmem_cache_free(kvm_svm_cpudata_cache, sd);
}
static int
svm_cpu_init(int cpu)
{
struct svm_cpu_data *sd;
int r;
sd = kmem_cache_alloc(kvm_svm_cpudata_cache, KM_SLEEP);
if (!sd)
return (ENOMEM);
sd->cpu = cpu;
sd->save_area = kmem_cache_alloc(kvm_svm_savearea_cache, KM_SLEEP);
if (!sd->save_area) {
kmem_cache_free(kvm_svm_cpudata_cache, sd);
return (ENOMEM);
}
/*
* Store the physical address now so that we don't try and
* take locks we cannot hold in a crosscall later.
*/
sd->save_area_pa = kvm_va2pa((caddr_t)sd->save_area);
kvm_svm_cpu_data[cpu] = sd;
return (0);
}
static void
set_msr_interception(uint32_t *msrpm, unsigned msr, int read, int write)
{
int i;
for (i = 0; i < NUM_MSR_MAPS; i++) {
if (msr >= msrpm_ranges[i] &&
msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
uint32_t msr_offset = (i * MSRS_IN_RANGE + msr -
msrpm_ranges[i]) * 2;
uint32_t *base = msrpm + (msr_offset / 32);
uint32_t msr_shift = msr_offset % 32;
uint32_t mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
*base = (*base & ~(0x3 << msr_shift)) |
(mask << msr_shift);
return;
}
}
cmn_err(CE_PANIC, "reached end of set_msr_interception()\n");
}
static void
svm_vcpu_init_msrpm(uint32_t *msrpm)
{
memset(msrpm, 0xff, SVM_ALLOC_MSRPM_SIZE);
set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
}
static void
svm_enable_lbrv(struct vcpu_svm *svm)
{
uint32_t *msrpm = svm->msrpm;
svm->vmcb->control.lbr_ctl = 1;
set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
}
static void
svm_disable_lbrv(struct vcpu_svm *svm)
{
uint32_t *msrpm = svm->msrpm;
svm->vmcb->control.lbr_ctl = 0;
set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
}
static int
svm_hardware_setup(void)
{
int cpu;
int r, i;
iopm_va = kvm_glue_alloc(SVM_ALLOC_IOPM_SIZE, SVM_ALLOC_IOPM_ALIGN, 0);
if (iopm_va == NULL)
return (ENOMEM);
memset(iopm_va, 0xff, SVM_ALLOC_IOPM_SIZE);
iopm_base = kvm_va2pa((caddr_t)iopm_va);
if (is_x86_feature(x86_featureset, X86FSET_NX))
kvm_enable_efer_bits(EFER_NX);
/* XXX figure this out */
#if 0
if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
kvm_enable_efer_bits(EFER_FFXSR);
#endif
kvm_svm_cpu_data = kmem_alloc(ncpus * sizeof (struct svm_cpu_data *),
KM_SLEEP);
for (i = 0; i < ncpus; i++) {
kvm_svm_cpu_data[i] = NULL;
}
for (i = 0; i < ncpus; i++) {
r = svm_cpu_init(i);
if (r) {
kvm_glue_free(iopm_va, SVM_ALLOC_IOPM_SIZE);
iopm_base = 0;
iopm_va = NULL;
return (r);
}
}
svm_features = cpuid_edx(SVM_CPUID_FUNC);
if (!svm_has(SVM_FEATURE_NPT))
npt_enabled = 0;
if (npt_enabled && !npt) {
npt_enabled = 0;
}
if (npt_enabled) {
kvm_enable_tdp();
} else
kvm_disable_tdp();
return (0);
}
static void
svm_hardware_unsetup(void)
{
int cpu;
for (cpu = 0; cpu < ncpus; cpu++) {
svm_cpu_uninit(cpu);
}
kvm_glue_free(iopm_va, SVM_ALLOC_IOPM_SIZE);
iopm_base = 0;
iopm_va = NULL;
}
static void
init_seg(struct vmcb_seg *seg)
{
seg->selector = 0;
seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
seg->limit = 0xffff;
seg->base = 0;
}
static void
init_sys_seg(struct vmcb_seg *seg, uint32_t type)
{
seg->selector = 0;
seg->attrib = SVM_SELECTOR_P_MASK | type;
seg->limit = 0xffff;
seg->base = 0;
}
static void
init_vmcb(struct vcpu_svm *svm)
{
struct vmcb_control_area *control = &svm->vmcb->control;
struct vmcb_save_area *save = &svm->vmcb->save;
svm->vcpu.fpu_active = 1;
control->intercept_cr_read = INTERCEPT_CR0_MASK |
INTERCEPT_CR3_MASK |
INTERCEPT_CR4_MASK;
control->intercept_cr_write = INTERCEPT_CR0_MASK |
INTERCEPT_CR3_MASK |
INTERCEPT_CR4_MASK |
INTERCEPT_CR8_MASK;
control->intercept_dr_read = INTERCEPT_DR0_MASK |
INTERCEPT_DR1_MASK |
INTERCEPT_DR2_MASK |
INTERCEPT_DR3_MASK |
INTERCEPT_DR4_MASK |
INTERCEPT_DR5_MASK |
INTERCEPT_DR6_MASK |
INTERCEPT_DR7_MASK;
control->intercept_dr_write = INTERCEPT_DR0_MASK |
INTERCEPT_DR1_MASK |
INTERCEPT_DR2_MASK |
INTERCEPT_DR3_MASK |
INTERCEPT_DR4_MASK |
INTERCEPT_DR5_MASK |
INTERCEPT_DR6_MASK |
INTERCEPT_DR7_MASK;
control->intercept_exceptions = (1 << PF_VECTOR) |
(1 << UD_VECTOR) |
(1 << MC_VECTOR);
control->intercept = (1ULL << INTERCEPT_INTR) |
(1ULL << INTERCEPT_NMI) |
(1ULL << INTERCEPT_SMI) |
(1ULL << INTERCEPT_SELECTIVE_CR0) |
(1ULL << INTERCEPT_CPUID) |
(1ULL << INTERCEPT_INVD) |
(1ULL << INTERCEPT_HLT) |
(1ULL << INTERCEPT_INVLPG) |
(1ULL << INTERCEPT_INVLPGA) |
(1ULL << INTERCEPT_IOIO_PROT) |
(1ULL << INTERCEPT_MSR_PROT) |
(1ULL << INTERCEPT_TASK_SWITCH) |
(1ULL << INTERCEPT_SHUTDOWN) |
(1ULL << INTERCEPT_VMRUN) |
(1ULL << INTERCEPT_VMMCALL) |
(1ULL << INTERCEPT_VMLOAD) |
(1ULL << INTERCEPT_VMSAVE) |
(1ULL << INTERCEPT_STGI) |
(1ULL << INTERCEPT_CLGI) |
(1ULL << INTERCEPT_SKINIT) |
(1ULL << INTERCEPT_WBINVD) |
(1ULL << INTERCEPT_MONITOR) |
(1ULL << INTERCEPT_MWAIT);
control->iopm_base_pa = iopm_base;
control->msrpm_base_pa = kvm_va2pa((caddr_t)svm->msrpm);
control->tsc_offset = 0;
control->int_ctl = V_INTR_MASKING_MASK;
init_seg(&save->es);
init_seg(&save->ss);
init_seg(&save->ds);
init_seg(&save->fs);
init_seg(&save->gs);
save->cs.selector = 0xf000;
/* Executable/Readable Code Segment */
save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
save->cs.limit = 0xffff;
/*
* cs.base should really be 0xffff0000, but vmx can't handle that, so
* be consistent with it.
*
* Replace when we have real mode working for vmx.
*/
save->cs.base = 0xf0000;
save->gdtr.limit = 0xffff;
save->idtr.limit = 0xffff;
init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
save->efer = EFER_SVME;
save->dr6 = 0xffff0ff0;
save->dr7 = 0x400;
save->rflags = 2;
save->rip = 0x0000fff0;
svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
/*
* This is the guest-visible cr0 value.
* svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
*/
svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
save->cr4 = X86_CR4_PAE;
/* rdx = ?? */
if (npt_enabled) {
/* Setup VMCB for Nested Paging */
control->nested_ctl = 1;
control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
(1ULL << INTERCEPT_INVLPG));
control->intercept_exceptions &= ~(1 << PF_VECTOR);
control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
save->g_pat = 0x0007040600070406ULL;
save->cr3 = 0;
save->cr4 = 0;
}
force_new_asid(&svm->vcpu);
svm->vcpu.arch.hflags = 0;
if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
control->pause_filter_count = 3000;
control->intercept |= (1ULL << INTERCEPT_PAUSE);
}
enable_gif(svm);
}
static int
svm_vcpu_reset(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
init_vmcb(svm);
if (!kvm_vcpu_is_bsp(vcpu)) {
kvm_rip_write(vcpu, 0);
svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
}
vcpu->arch.regs_avail = ~0;
vcpu->arch.regs_dirty = ~0;
return (0);
}
static struct kvm_vcpu *
svm_create_vcpu(struct kvm *kvm, unsigned int id)
{
struct vcpu_svm *svm;
int err;
svm = kmem_cache_alloc(kvm_svm_vcpu_cache, KM_SLEEP);
if (!svm) {
return (NULL);
}
err = kvm_vcpu_init(&svm->vcpu, kvm, id);
if (err) {
kmem_cache_free(kvm_svm_vcpu_cache, svm);
return (NULL);
}
/* VMCBs need to be aligned on 4k boundaries */
svm->vmcb = kmem_cache_alloc(kvm_svm_vmcb_cache, KM_SLEEP);
if (!svm->vmcb) {
kvm_vcpu_uninit(&svm->vcpu);
kmem_cache_free(kvm_svm_vcpu_cache, svm);
return (NULL);
}
svm->vmcb_pa = kvm_va2pa((caddr_t)svm->vmcb);
svm->msrpm = kmem_cache_alloc(kvm_svm_msrpm_cache, KM_SLEEP);
if (!svm->msrpm) {
kmem_cache_free(kvm_svm_vmcb_cache, svm->vmcb);
kvm_vcpu_uninit(&svm->vcpu);
kmem_cache_free(kvm_svm_vcpu_cache, svm);
return (NULL);
}
svm_vcpu_init_msrpm(svm->msrpm);
svm->asid_generation = 0;
init_vmcb(svm);
fx_init(&svm->vcpu);
svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
if (kvm_vcpu_is_bsp(&svm->vcpu))
svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
return (&svm->vcpu);
}
static void
svm_free_vcpu(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
kmem_cache_free(kvm_svm_vmcb_cache, svm->vmcb);
kmem_cache_free(kvm_svm_msrpm_cache, svm->msrpm);
kvm_vcpu_uninit(vcpu);
kmem_cache_free(kvm_svm_vcpu_cache, svm);
}
static void
svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
int i;
if (cpu != vcpu->cpu) {
vcpu->cpu = cpu;
/* kvm_migrate_timers(vcpu); */
svm->asid_generation = 0;
/*
* XXX per-cpu TSS/GDT/IDT/GSBASE is, I believe,
* taken care of mostly by the VMRUN instruction
* but also by save/load behaviour in vcpu_run.
*/
/*
* Make sure the time stamp counter is monotonic.
*/
svm->vmcb->control.tsc_offset = tsc_gethrtime_tick_delta();
}
for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) {
rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
}
}
static void
svm_vcpu_put(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
int i;
KVM_VCPU_KSTAT_INC(vcpu, kvmvs_host_state_reload);
for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) {
wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
}
}
static unsigned long
svm_get_rflags(struct kvm_vcpu *vcpu)
{
return (to_svm(vcpu)->vmcb->save.rflags);
}
static void
svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
{
to_svm(vcpu)->vmcb->save.rflags = rflags;
}
static void
svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
{
switch (reg) {
case VCPU_EXREG_PDPTR:
if (!npt_enabled)
cmn_err(CE_PANIC, "had !npt_enabled in "
"svm_cache_reg()\n");
load_pdptrs(vcpu, vcpu->arch.cr3);
break;
default:
cmn_err(CE_PANIC, "fell through switch in svm_cache_reg()\n");
}
}
static void
svm_set_vintr(struct vcpu_svm *svm)
{
svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
}
static void
svm_clear_vintr(struct vcpu_svm *svm)
{
svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
}
static struct vmcb_seg *
svm_seg(struct kvm_vcpu *vcpu, int seg)
{
struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
switch (seg) {
case VCPU_SREG_CS: return (&save->cs);
case VCPU_SREG_DS: return (&save->ds);
case VCPU_SREG_ES: return (&save->es);
case VCPU_SREG_FS: return (&save->fs);
case VCPU_SREG_GS: return (&save->gs);
case VCPU_SREG_SS: return (&save->ss);
case VCPU_SREG_TR: return (&save->tr);
case VCPU_SREG_LDTR: return (&save->ldtr);
}
cmn_err(CE_PANIC, "fell through switch in svm_seg()\n");
return (NULL);
}
static uint64_t
svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
{
struct vmcb_seg *s = svm_seg(vcpu, seg);
return (s->base);
}
static void
svm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
{
struct vmcb_seg *s = svm_seg(vcpu, seg);
var->base = s->base;
var->limit = s->limit;
var->selector = s->selector;
var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
/*
* AMD's VMCB does not have an explicit unusable field, so emulate it
* for cross vendor migration purposes by "not present"
*/
var->unusable = !var->present || (var->type == 0);
switch (seg) {
case VCPU_SREG_CS:
/*
* SVM always stores 0 for the 'G' bit in the CS selector in
* the VMCB on a VMEXIT. This hurts cross-vendor migration:
* Intel's VMENTRY has a check on the 'G' bit.
*/
var->g = s->limit > 0xfffff;
break;
case VCPU_SREG_TR:
/*
* Work around a bug where the busy flag in the tr selector
* isn't exposed
*/