diff --git a/src/Data/Array/Accelerate/Pretty/Exp.hs b/src/Data/Array/Accelerate/Pretty/Exp.hs
index 4f2db1667..bbc552f0b 100644
--- a/src/Data/Array/Accelerate/Pretty/Exp.hs
+++ b/src/Data/Array/Accelerate/Pretty/Exp.hs
@@ -135,7 +135,8 @@ prettyPreOpenExp ctx prettyArrayInstr env exp =
         --
         single = parensIf (needsParens ctx (Operator "?:" Infix N 0))
                $ sep [ p', pretty '?', t', pretty ':', e' ]
-        multi  = hang 3
+        multi  = parensIf (ctxPrecedence ctx > 0)
+               $ hang 3
                $ vsep [ if_ <+> p'
                       , hang shiftwidth (sep [ then_, t' ])
                       , hang shiftwidth (sep [ else_, e' ]) ]
diff --git a/src/Data/Array/Accelerate/Trafo/Schedule/Uniform/Future.hs b/src/Data/Array/Accelerate/Trafo/Schedule/Uniform/Future.hs
index 1f664a039..2cb65ac83 100644
--- a/src/Data/Array/Accelerate/Trafo/Schedule/Uniform/Future.hs
+++ b/src/Data/Array/Accelerate/Trafo/Schedule/Uniform/Future.hs
@@ -707,7 +707,7 @@ loopFuture resolved (FutureBuffer tp ref (Move readLockSignal) (Just (Move write
             $ Just $ Borrow (Just signalW) resolverR
       | otherwise -> internalError "input or output impossible"
   }
-loopFuture resolved (FutureBuffer tp ref (Lock readLockSignal readLockResolver) (Just (Lock writeLockSignal writeLockResolver))) = undefined
+loopFuture resolved (FutureBuffer tp ref (Lock readLockSignal readLockResolver) (Just (Lock writeLockSignal writeLockResolver))) =
   -- A borrowed writable buffer
   -- We must add two signals (and accompanying signal resolvers) to the state
   -- to synchronize read and write access. Furthermore we need to declare two