diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index af59b609a47b2..c56747940f5fd 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -1597,12 +1597,15 @@ bool Compiler::CheckHWIntrinsicImmRange(NamedIntrinsic intrinsic, #ifdef TARGET_ARM64 switch (intrinsic) { + case NI_AdvSimd_ShiftLeftLogical: + case NI_AdvSimd_ShiftLeftLogicalScalar: case NI_AdvSimd_ShiftRightLogical: + case NI_AdvSimd_ShiftRightLogicalScalar: + case NI_AdvSimd_ShiftRightArithmetic: + case NI_AdvSimd_ShiftRightArithmeticScalar: *useFallback = true; break; - // TODO: Implement more AdvSimd fallbacks in Compiler::impNonConstFallback - default: assert(*useFallback == false); break; @@ -1633,7 +1636,7 @@ bool Compiler::CheckHWIntrinsicImmRange(NamedIntrinsic intrinsic, } } else -#endif // TARGET_XARCH +#endif // TARGET_X86 { *useFallback = true; return false; diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 9647cc826ca08..e7bde27b11d12 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -564,20 +564,59 @@ void HWIntrinsicInfo::lookupImmBounds( // GenTree* Compiler::impNonConstFallback(NamedIntrinsic intrinsic, var_types simdType, CorInfoType simdBaseJitType) { + bool isRightShift = true; + switch (intrinsic) { + case NI_AdvSimd_ShiftLeftLogical: + case NI_AdvSimd_ShiftLeftLogicalScalar: + isRightShift = false; + FALLTHROUGH; + case NI_AdvSimd_ShiftRightLogical: + case NI_AdvSimd_ShiftRightLogicalScalar: + case NI_AdvSimd_ShiftRightArithmetic: + case NI_AdvSimd_ShiftRightArithmeticScalar: { - // AdvSimd.ShiftRightLogical be replaced with AdvSimd.ShiftLogical, which takes op2 in a simd register + // AdvSimd.ShiftLeft* and AdvSimd.ShiftRight* can be replaced with AdvSimd.Shift*, which takes op2 in a simd + // register GenTree* op2 = impPopStack().val; GenTree* op1 = impSIMDPopStack(); // AdvSimd.ShiftLogical does right-shifts with negative immediates, hence the negation - GenTree* tmpOp = - gtNewSimdCreateBroadcastNode(simdType, gtNewOperNode(GT_NEG, genActualType(op2->TypeGet()), op2), - simdBaseJitType, genTypeSize(simdType)); - return gtNewSimdHWIntrinsicNode(simdType, op1, tmpOp, NI_AdvSimd_ShiftLogical, simdBaseJitType, + if (isRightShift) + { + op2 = gtNewOperNode(GT_NEG, genActualType(op2->TypeGet()), op2); + } + + NamedIntrinsic fallbackIntrinsic; + switch (intrinsic) + { + case NI_AdvSimd_ShiftLeftLogical: + case NI_AdvSimd_ShiftRightLogical: + fallbackIntrinsic = NI_AdvSimd_ShiftLogical; + break; + + case NI_AdvSimd_ShiftLeftLogicalScalar: + case NI_AdvSimd_ShiftRightLogicalScalar: + fallbackIntrinsic = NI_AdvSimd_ShiftLogicalScalar; + break; + + case NI_AdvSimd_ShiftRightArithmetic: + fallbackIntrinsic = NI_AdvSimd_ShiftArithmetic; + break; + + case NI_AdvSimd_ShiftRightArithmeticScalar: + fallbackIntrinsic = NI_AdvSimd_ShiftArithmeticScalar; + break; + + default: + unreached(); + } + + GenTree* tmpOp = gtNewSimdCreateBroadcastNode(simdType, op2, simdBaseJitType, genTypeSize(simdType)); + return gtNewSimdHWIntrinsicNode(simdType, op1, tmpOp, fallbackIntrinsic, simdBaseJitType, genTypeSize(simdType)); } diff --git a/src/coreclr/jit/hwintrinsiclistarm64.h b/src/coreclr/jit/hwintrinsiclistarm64.h index 703600171e5f1..c3649cb64beb5 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64.h +++ b/src/coreclr/jit/hwintrinsiclistarm64.h @@ -433,12 +433,12 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturateScalar, HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftAndInsert, -1, 3, {INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sli, INS_sli, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar) -HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogical, -1, 2, {INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand) +HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogical, -1, 2, {INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_NoJmpTableIMM) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturate, -1, 2, {INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateUnsigned, -1, 2, {INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateUnsignedScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshlu, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) -HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) +HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar|HW_Flag_NoJmpTableIMM) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalWideningLower, 8, 2, {INS_sshll, INS_ushll, INS_sshll, INS_ushll, INS_sshll, INS_ushll, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand) HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalWideningUpper, 16, 2, {INS_sshll2, INS_ushll2, INS_sshll2, INS_ushll2, INS_sshll2, INS_ushll2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand) HARDWARE_INTRINSIC(AdvSimd, ShiftLogical, -1, 2, {INS_ushl, INS_ushl, INS_ushl, INS_ushl, INS_ushl, INS_ushl, INS_ushl, INS_ushl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_NoFlag) @@ -451,7 +451,7 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturateScalar, HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushl, INS_ushl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar) HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsert, -1, 3, {INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sri, INS_sri, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar) -HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand) +HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_NoJmpTableIMM) HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAdd, -1, 3, {INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAddScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar) HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticNarrowingSaturateLower, 8, 2, {INS_sqshrn, INS_invalid, INS_sqshrn, INS_invalid, INS_sqshrn, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand) @@ -466,8 +466,8 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedNarrowingSaturateUn HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedNarrowingSaturateUnsignedUpper, 16, 3, {INS_invalid, INS_sqrshrun2, INS_invalid, INS_sqrshrun2, INS_invalid, INS_sqrshrun2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedNarrowingSaturateUpper, 16, 3, {INS_sqrshrn2, INS_invalid, INS_sqrshrn2, INS_invalid, INS_sqrshrn2, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_srshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) -HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) -HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogical, -1, 2, {INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand) +HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar|HW_Flag_NoJmpTableIMM) +HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogical, -1, 2, {INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_NoJmpTableIMM) HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAdd, -1, 3, {INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAddScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_usra, INS_usra, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar) HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalNarrowingLower, 8, 2, {INS_shrn, INS_shrn, INS_shrn, INS_shrn, INS_shrn, INS_shrn, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand) @@ -482,7 +482,7 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedNarrowingSaturateLower HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedNarrowingSaturateUpper, 16, 3, {INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedNarrowingUpper, 16, 3, {INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_urshr, INS_urshr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) -HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar) +HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar|HW_Flag_NoJmpTableIMM) HARDWARE_INTRINSIC(AdvSimd, SignExtendWideningLower, 8, 1, {INS_sxtl, INS_invalid, INS_sxtl, INS_invalid, INS_sxtl, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg) HARDWARE_INTRINSIC(AdvSimd, SignExtendWideningUpper, 16, 1, {INS_sxtl2, INS_invalid, INS_sxtl2, INS_invalid, INS_sxtl2, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg) HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMD, HW_Flag_SIMDScalar) diff --git a/src/coreclr/jit/simd.h b/src/coreclr/jit/simd.h index 0e10abd29fcd8..507fbd62406de 100644 --- a/src/coreclr/jit/simd.h +++ b/src/coreclr/jit/simd.h @@ -668,10 +668,10 @@ void EvaluateUnarySimd(genTreeOps oper, bool scalar, var_types baseType, TSimd* template TBase EvaluateBinaryScalarRSZ(TBase arg0, TBase arg1) { -#if defined(TARGET_XARCH) +#if defined(TARGET_XARCH) || defined(TARGET_ARM64) if ((arg1 < 0) || (arg1 >= (sizeof(TBase) * 8))) { - // For SIMD, xarch allows overshifting and treats + // For SIMD, xarch and ARM64 allow overshifting and treat // it as zeroing. So ensure we do the same here. // // The xplat APIs ensure the shiftAmount is masked @@ -760,10 +760,10 @@ TBase EvaluateBinaryScalarSpecialized(genTreeOps oper, TBase arg0, TBase arg1) case GT_LSH: { -#if defined(TARGET_XARCH) +#if defined(TARGET_XARCH) || defined(TARGET_ARM64) if ((arg1 < 0) || (arg1 >= (sizeof(TBase) * 8))) { - // For SIMD, xarch allows overshifting and treats + // For SIMD, xarch and ARM64 allow overshifting and treat // it as zeroing. So ensure we do the same here. // // The xplat APIs ensure the shiftAmount is masked @@ -817,10 +817,10 @@ TBase EvaluateBinaryScalarSpecialized(genTreeOps oper, TBase arg0, TBase arg1) case GT_RSH: { -#if defined(TARGET_XARCH) +#if defined(TARGET_XARCH) || defined(TARGET_ARM64) if ((arg1 < 0) || (arg1 >= (sizeof(TBase) * 8))) { - // For SIMD, xarch allows overshifting and treats + // For SIMD, xarch and ARM64 allow overshifting and treat // it as propagating the sign bit (returning Zero // or AllBitsSet). So ensure we do the same here. // diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105621/Runtime_105621.cs b/src/tests/JIT/Regression/JitBlue/Runtime_105621/Runtime_105621.cs index ee772943aef89..cf06e3e71144e 100644 --- a/src/tests/JIT/Regression/JitBlue/Runtime_105621/Runtime_105621.cs +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105621/Runtime_105621.cs @@ -14,19 +14,89 @@ public class Runtime_105621 { + private static byte getByteImmOOB() => 9; + private static byte getShortImmOOB() => 17; + private static byte getLongImmOOB() => 65; + + [Fact] + public static void TestShiftLeftLogicalByZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(1); + var vr4 = AdvSimd.ShiftLeftLogical(vr3, 0); + Assert.Equal(vr3, vr4); + } + } + + [Fact] + public static void TestShiftLeftLogicalToZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftLeftLogical(vr3, 9); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftLeftLogicalToZeroNonConst() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftLeftLogical(vr3, getByteImmOOB()); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftLeftLogicalScalarByZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(1); + var vr4 = AdvSimd.ShiftLeftLogicalScalar(vr3, 0); + Assert.Equal(vr3, vr4); + } + } + + [Fact] + public static void TestShiftLeftLogicalScalarToZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftLeftLogicalScalar(vr3, 65); + Assert.Equal(vr4, Vector64.Zero); + } + } + [Fact] - public static void TestShiftByZero() + public static void TestShiftLeftLogicalScalarToZeroNonConst() { if (AdvSimd.IsSupported) { - var vr3 = Vector64.Create(0); + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftLeftLogicalScalar(vr3, getLongImmOOB()); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftRightLogicalByZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(1); var vr4 = AdvSimd.ShiftRightLogical(vr3, 0); Assert.Equal(vr3, vr4); } } [Fact] - public static void TestShiftToZero() + public static void TestShiftRightLogicalToZero() { if (AdvSimd.IsSupported) { @@ -35,4 +105,114 @@ public static void TestShiftToZero() Assert.Equal(vr4, Vector64.Zero); } } + + [Fact] + public static void TestShiftRightLogicalToZeroNonConst() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftRightLogical(vr3, getByteImmOOB()); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftRightLogicalScalarByZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(1); + var vr4 = AdvSimd.ShiftRightLogicalScalar(vr3, 0); + Assert.Equal(vr3, vr4); + } + } + + [Fact] + public static void TestShiftRightLogicalScalarToZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftRightLogicalScalar(vr3, 65); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftRightLogicalScalarToZeroNonConst() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftRightLogicalScalar(vr3, getLongImmOOB()); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftRightArithmeticByZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector128.Create(1); + var vr4 = AdvSimd.ShiftRightArithmetic(vr3, 0); + Assert.Equal(vr3, vr4); + } + } + + [Fact] + public static void TestShiftRightArithmeticToZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector128.Create(128); + var vr4 = AdvSimd.ShiftRightArithmetic(vr3, 17); + Assert.Equal(vr4, Vector128.Zero); + } + } + + [Fact] + public static void TestShiftRightArithmeticToZeroNonConst() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector128.Create(128); + var vr4 = AdvSimd.ShiftRightArithmetic(vr3, getShortImmOOB()); + Assert.Equal(vr4, Vector128.Zero); + } + } + + [Fact] + public static void TestShiftRightArithmeticScalarByZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(1); + var vr4 = AdvSimd.ShiftRightArithmeticScalar(vr3, 0); + Assert.Equal(vr3, vr4); + } + } + + [Fact] + public static void TestShiftRightArithmeticScalarToZero() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftRightArithmeticScalar(vr3, 65); + Assert.Equal(vr4, Vector64.Zero); + } + } + + [Fact] + public static void TestShiftRightArithmeticScalarToZeroNonConst() + { + if (AdvSimd.IsSupported) + { + var vr3 = Vector64.Create(128); + var vr4 = AdvSimd.ShiftRightArithmeticScalar(vr3, getLongImmOOB()); + Assert.Equal(vr4, Vector64.Zero); + } + } } diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105817/Runtime_105817.cs b/src/tests/JIT/Regression/JitBlue/Runtime_105817/Runtime_105817.cs new file mode 100644 index 0000000000000..1b6f4b206861d --- /dev/null +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105817/Runtime_105817.cs @@ -0,0 +1,82 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +// Generated by Fuzzlyn v2.2 on 2024-08-01 14:37:47 +// Run on Arm64 MacOS +// Seed: 14773448547728333023-vectort,vector64,vector128,armadvsimd,armadvsimdarm64,armaes,armarmbase,armarmbasearm64,armcrc32,armcrc32arm64,armdp,armrdm,armrdmarm64,armsha1,armsha256 +// Reduced from 270.2 KiB to 0.4 KiB in 00:01:48 +// Debug: Outputs 0 +// Release: Outputs 1 +using System; +using System.Runtime.Intrinsics; +using System.Runtime.Intrinsics.Arm; +using Xunit; + +public class Runtime_105817 +{ + [Fact] + public static void TestOverShiftLeftLogical() + { + if (AdvSimd.IsSupported) + { + var vr6 = Vector128.Create(1); + var vr7 = AdvSimd.ShiftLeftLogical(vr6, 16); + Assert.Equal(vr7, Vector128.Zero); + } + } + + [Fact] + public static void TestOverShiftLeftLogicalScalar() + { + if (AdvSimd.IsSupported) + { + var vr6 = Vector64.Create(1); + var vr7 = AdvSimd.ShiftLeftLogicalScalar(vr6, 64); + Assert.Equal(vr7, Vector64.Zero); + } + } + + [Fact] + public static void TestOverShiftRightLogical() + { + if (AdvSimd.IsSupported) + { + var vr6 = Vector128.Create(1); + var vr7 = AdvSimd.ShiftRightLogical(vr6, 16); + Assert.Equal(vr7, Vector128.Zero); + } + } + + [Fact] + public static void TestOverShiftRightLogicalScalar() + { + if (AdvSimd.IsSupported) + { + var vr6 = Vector64.Create(1); + var vr7 = AdvSimd.ShiftRightLogicalScalar(vr6, 64); + Assert.Equal(vr7, Vector64.Zero); + } + } + + [Fact] + public static void TestOverShiftRightArithmetic() + { + if (AdvSimd.IsSupported) + { + var vr6 = Vector128.Create(1); + var vr7 = AdvSimd.ShiftRightArithmetic(vr6, 16); + Assert.Equal(vr7, Vector128.Zero); + } + } + + [Fact] + public static void TestOverShiftRightArithmeticScalar() + { + if (AdvSimd.IsSupported) + { + var vr6 = Vector64.Create(1); + var vr7 = AdvSimd.ShiftRightArithmeticScalar(vr6, 64); + Assert.Equal(vr7, Vector64.Zero); + } + } +} \ No newline at end of file diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105817/Runtime_105817.csproj b/src/tests/JIT/Regression/JitBlue/Runtime_105817/Runtime_105817.csproj new file mode 100644 index 0000000000000..15edd99711a1a --- /dev/null +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105817/Runtime_105817.csproj @@ -0,0 +1,8 @@ + + + True + + + + + \ No newline at end of file