Is it possible to port to CYD with SPI ST7789 and a Ra-02 SX1278?

[eben80]

Would it be possible to get the firmware to work with an SPI TFT based board?
https://github.com/witnessmenow/ESP32-Cheap-Yellow-Display/blob/main/DisplayConfig/CYD2USB/User_Setup.h
If i understand correctly it looks like it only supports i2c ST7789 under hardware configuration.
I know that the biggest issue would be to get the free SPI GPIOs to connect the SX1278 but I suppose the SD Card SPI could be cannibalized on hardware level. Iv'e flashed the firmware to the CYD and it starts up with the AP but of course the display doesn't work since I cannot set up the SPI pins for it.

Is there anything I could try?

[dl9rdz]

Hi,

The support for ILI9225/9341/9342/ST7789 is all based on SPI connections, so this should be fine.

I just took a look at the CYD. The Display seems to be on HSPI and the SDCARD on VSPI.

Usually the software assumes the SX1278 to be on the VSPI, so as long as you don't use the SD-Card this should be fine.
Note that "DC" is the same as "RS" in the config, and MISO is not needed/not present in config.

In theory the SPI bus can be shared between devices (with different chip select pins).

• Sharing between Display and SX1278 works fine on the M5Stack. However, there is this part:
  

  rdz_ttgo_sonde/RX_FSK/src/Display.cpp

  Line 520 in 331fa13

  if(sonde.config.type == TYPE_M5_CORE2 || sonde.config.type == TYPE_M5_CORE ) {

  
  where the use of the SPI bus (vspi or hspi) is hard coded. The SX1278 is always supposed to be on the VSPI and the display usually is on the HSPI, but VSPI is used if a M5Stack is detected (this is not configurable in the config at the moment).
• Sharing between Display and SD-Card has some issues on my test setup that I need to debug (TODO...)
• Sharing between SD-Card and SX1278 is untested so far and probably will not work. Synchronization missing

[eben80]

Thank you for the response. OK so the Display doesn't work but let me try and get the lora working first.
For LORA:
Do I understand correctly that I only need to connect MISO(GPIO19), MOSI(GPIO23), SCK(GPIO18), NSS(GPIO5) and 3V3 and Ground?
DIO0 and RST are not connected and configurable?

For TFT:
Display Type = 5
OLED SDA/TFT SDA = MOSI/SDO = GPIO12
OLED SCL/TFT CLK = SCK = GPIO14
OLED RST/TFT RST = -1
TFT RS = GPIO2
TFT CS = GPIO15

The TFT backlight is GPIO21, how do I configure that?
The Green colour on RGB is GPIO16

I'm getting this in logs:

[20:57:37]Setup sx1278
[20:57:37]Configuing SX1278FSK SPI with miso=19, mosi=23, sck=18, ss=5
[20:57:37]0
[20:57:37]Setting freq: SUCCESS
[20:57:37]Frequency set to 0.00
[20:57:38]0
[20:57:38]Setting freq: SUCCESS
[20:57:38]Frequency set to 0.00
[20:57:38]RX LNA Gain is -999
[20:57:38]SX1278 configuration finished
[20:57:38]Setup finished
[20:57:38]
[20:57:38]Sonde.cpp: Invalid rxtask.currentSonde: -1
[20:57:38]0
[20:57:38]Setting SX1278 power on FAILED

And then this in a loop:

[20:57:50]Setting SX1278 power on FAILED
[20:57:50]TOO MUCH DATA
[20:57:50]0

The display is not showing anything.

Any advice please?

[dl9rdz]

For the backlight you could use the "Power output control". Set it to 21 to pull it low, set it to 149 (21+128) to pull it high - I did not check what the display backlight needs... probably high?

According to https://randomnerdtutorials.com/esp32-cheap-yellow-display-cyd-pinout-esp32-2432s028r/
MOSI is Pin 13, not Pin 12

SX1278:
This should work this way, yes.
The chip will do a power-on reset automatically, on the other boards I do not do any reset in software, and that is fine. The reset pin needs to be high (and this should be ok if it is just left open I guess, but to be sure a pull up to 3V3 should also be fine).
DIO pins are not used

[eben80]

Aah yes, setting it to 149 worked and correcting the MOSI error brought the screen to life and it is displaying properly. I also dropped the SPI speed to 20MHz as it was suggested in the CYD docs.

I'm still having an issue with the Lora though.

It is still looping with:

[20:57:50]Setting SX1278 power on FAILED
[20:57:50]TOO MUCH DATA
[20:57:50]0

Even after pulling RST to 3.3V

What triggers this TOO MUCH DATA?

[dl9rdz]

Technically it means that more than 512 bytes were read from the SX1278 FIFO in packet mode (which is used for RS41). During this time, the SX1278 IRQ FLAGS2 continuously indicates that the FIFO is not empty, but also that the payload is not ready. This should never happen (for RS41, the SX1278 is programmed to received a max 320 byte frame, so after 320 bytes it should indicate frame complete).

Practically, this usually means that all data read from the bus is 0, as then the FIFO empty bit is 0 (=not empty), and the payload ready bit is also 0 (=not ready).