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  (text "One per VDD pin" (at 181.61 27.305 0)
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  (text "This source describes Open Hardware and is licensed under the CERN-OHL-P v2\nYou may redistribute and modify this documentation and make products using it under the terms of the\nCERN-OHL-P v2 (https:/cern.ch/cern-ohl).\nThis documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF\nMERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the\nCERN-OHL-P v2 for applicable conditions.\n\nOriginal schematic (stm32f446-based Model M \"Overnumpad\" controller) credit to Andre Purdei "
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  (text "a9 forbidden\n" (at 163.83 105.41 0)
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  (text "Notes on various special GPIOs of this chip (warning: written for STM32F446, not 401):\n\n* The following can be output during bootloader mode,\n   make sure nothing is driving into them during programming:\n   * PA9 (USART1 TX), PB10 (maybe USART3 TX), PC10\n     (USART3 TX), PB13 (CAN2_TX), PB14 (SPI2_MISO), PA6 (SPI1_MISO)\n\n* The following pins need to be stable and unchanging during\n   programming in order to guarantee that DFU mode activates:\n   * PA10 (USART1 RX)   (decided to pull high)\n   * PC11 (USART3 RX)   (decided to pull low)\n   * PB5 (CAN2 RX)   (decided to pull low)\n   * PB9,PB6 (I2C1 SDA,SCL) (decided to force low)\n   * PC9 (I2C3 SDA) (decided to pull high)\n   * PA5 (SPI1_SCK) (decided to pull high)\n   * PC7 (SPI2_SCK) (decided to pull high)\n\n* On this chip the following GPIOs are not 5V-tolerant:\n   * PA4, PA5, and any GPIOs with pull-up/downs enabled\n\n* On this chip the following GPIOs have stronger pull-up/downs:\n   * PA10, PB10   (normal max: 50k PA10/PB10 max: 14k)\n\n* On this chip the following GPIOs are current-limited:\n   * PC13, PC14, PC15 output mode current is limited to +-3mA\n\n* On this chip, according to AN2606, an external pull-up\n   resistor on the USB_DP pin is NOT required\n\n* On this chip, according to AN2606, the bootloader uses Pattern 1,\n   which also requires the BP2 BOOT1 pin to be low.\n\nOther Notes:\n\n* For this chip AN2606 Bootloader document says, clock must\n   be a multiple of 1MHz, between 4 and 26MHz\n"
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  (text "C5 close to VDDA" (at 242.57 32.385 0)
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  (text "These are all pulled up to disable all\nnon-DFU bootloader modes"
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  (text "Has resistor in case this pin accidentally\ngets configured as output and gets pulled up"
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