diff --git a/.github/workflows/build-test.yaml b/.github/workflows/build-test.yaml index 4a3e0ced649c..99666686f24c 100644 --- a/.github/workflows/build-test.yaml +++ b/.github/workflows/build-test.yaml @@ -4,7 +4,7 @@ on: [push, pull_request] jobs: build: - runs-on: ubuntu-18.04 + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 diff --git a/.github/workflows/stale-issue-bot.yaml b/.github/workflows/stale-issue-bot.yaml index 3720e72cf4f6..b6369d8dced0 100644 --- a/.github/workflows/stale-issue-bot.yaml +++ b/.github/workflows/stale-issue-bot.yaml @@ -332,7 +332,7 @@ jobs: if: github.repository == 'Klipper3d/klipper' runs-on: ubuntu-latest steps: - - uses: dessant/lock-threads@v3 + - uses: dessant/lock-threads@v4 with: issue-inactive-days: '180' issue-lock-reason: '' diff --git a/config/generic-bigtreetech-manta-e3ez.cfg b/config/generic-bigtreetech-manta-e3ez.cfg new file mode 100644 index 000000000000..199eae708419 --- /dev/null +++ b/config/generic-bigtreetech-manta-e3ez.cfg @@ -0,0 +1,200 @@ +# This file contains common pin mappings for the BIGTREETECH Manta E3EZ +# To use this config, the firmware should be compiled for the +# STM32G0B1 with a "8KiB bootloader" "8 MHz crystal" +# and "USB (on PA11/PA12)" or "CAN bus (on PB12/PB13)". + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PA14 +dir_pin: !PA10 +enable_pin: !PA13 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PC4 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_y] +step_pin: PC8 +dir_pin: !PA15 +enable_pin: !PC14 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PB0 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_z] +step_pin: PD2 +dir_pin: PD4 +enable_pin: !PD3 +microsteps: 16 +rotation_distance: 8 +endstop_pin: ^PC6 +position_endstop: 0 +position_max: 270 + +[extruder] +step_pin: PD5 +dir_pin: !PD6 +enable_pin: !PB3 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PB11 #HE0 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PA4 #TH0 +control: pid +pid_Kp: 21.527 +pid_Ki: 1.063 +pid_Kd: 108.982 +min_temp: 0 +max_temp: 250 + +#[filament_switch_sensor material_0] +#switch_pin: PC5 + +#[extruder1] +#step_pin: PB7 +#dir_pin: PB6 +#enable_pin: !PB4 +#heater_pin: PB10 # HE1 +#sensor_pin: PA5 # T1 + +#[filament_switch_sensor material_1] +#switch_pin: PB1 + +[heater_bed] +heater_pin: PB2 #HB +sensor_type: EPCOS 100K B57560G104F #Generic 3950 +sensor_pin: PA3 #TB +control: watermark +min_temp: 0 +max_temp: 130 + +[fan] +pin: PA8 + +#[heater_fan fan1] +#pin: PB15 + +#[heater_fan fan2] +#pin: PB14 + +[mcu] +serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +######################################## +# TMC2209 configuration +######################################## + +#[tmc2209 stepper_x] +#uart_pin: PB8 +##diag_pin: PC4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_y] +#uart_pin: PC9 +##diag_pin: PB0 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_z] +#uart_pin: PD0 +##diag_pin: PC6 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder] +#uart_pin: PD1 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder1] +#uart_pin: PB5 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +######################################## +# TMC2130 configuration +######################################## + +#[tmc2130 stepper_x] +#cs_pin: PB8 +#spi_software_miso_pin: PC11 +#spi_software_mosi_pin: PC12 +#spi_software_sclk_pin: PC10 +##diag1_pin: PF3 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_y] +#cs_pin: PC9 +#spi_software_miso_pin: PC11 +#spi_software_mosi_pin: PC12 +#spi_software_sclk_pin: PC10 +##diag1_pin: PF4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_z] +#cs_pin: PD0 +#spi_software_miso_pin: PC11 +#spi_software_mosi_pin: PC12 +#spi_software_sclk_pin: PC10 +##diag1_pin: PF5 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder] +#cs_pin: PD1 +#spi_software_miso_pin: PC11 +#spi_software_mosi_pin: PC12 +#spi_software_sclk_pin: PC10 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder1] +#cs_pin: PB5 +#spi_software_miso_pin: PC11 +#spi_software_mosi_pin: PC12 +#spi_software_sclk_pin: PC10 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +[board_pins] +aliases: + # EXP1 header + EXP1_1=PC1, EXP1_3=PC3, EXP1_5=PC0, EXP1_7=PA2, EXP1_9=, + EXP1_2=PC2, EXP1_4=, EXP1_6=PA0, EXP1_8=PA1, EXP1_10=<5V> + +#[bltouch] +#sensor_pin: PA6 +#control_pin: PA7 + +#[output_pin PS_ON] +#pin: PA9 + +#[output_pin pb9_pin] +#pin: PB9 + +#[neopixel my_neopixel] +#pin: PC7 + +#[adxl345] +#cs_pin: PC15 +#spi_software_miso_pin: PC11 +#spi_software_mosi_pin: PC12 +#spi_software_sclk_pin: PC10 diff --git a/config/generic-bigtreetech-manta-m4p.cfg b/config/generic-bigtreetech-manta-m4p.cfg index efd9007d5a54..caf5326743fe 100644 --- a/config/generic-bigtreetech-manta-m4p.cfg +++ b/config/generic-bigtreetech-manta-m4p.cfg @@ -75,8 +75,8 @@ pin: PD2 #pin: PD4 #[heater_fan SoC_fan] -#pin: CB1: gpio79 -#pin: RPI: gpio26 +#pin: CB1:gpio79 +#pin: RPI:gpio26 [mcu] serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 diff --git a/config/generic-bigtreetech-manta-m5p.cfg b/config/generic-bigtreetech-manta-m5p.cfg new file mode 100644 index 000000000000..cb1cad4938ba --- /dev/null +++ b/config/generic-bigtreetech-manta-m5p.cfg @@ -0,0 +1,199 @@ +# This file contains common pin mappings for the BIGTREETECH Manta M5P +# To use this config, the firmware should be compiled for the +# STM32G0B1 with a "8KiB bootloader" "8 MHz crystal" +# and "USB (on PA11/PA12)" or "CAN bus (on PD0/PD1)". + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PC8 +dir_pin: !PC9 +enable_pin: !PA15 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PD3 +position_endstop: 0 +position_max: 200 +homing_speed: 50 + +[stepper_y] +step_pin: PA10 +dir_pin: !PA14 +enable_pin: !PA13 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PD2 +position_endstop: 0 +position_max: 200 +homing_speed: 50 + +[stepper_z] +step_pin: PC6 +dir_pin: PC7 +enable_pin: !PA9 +microsteps: 16 +rotation_distance: 8 +endstop_pin: ^PC3 +position_endstop: 0.0 +position_max: 200 + +[extruder] +step_pin: PB12 +dir_pin: !PB11 +enable_pin: !PA8 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PC5 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PA1 +control: pid +pid_Kp: 21.527 +pid_Ki: 1.063 +pid_Kd: 108.982 +min_temp: 0 +max_temp: 250 + +#sensor_type:MAX31865 +#sensor_pin: PA4 +#spi_bus: spi1 +#rtd_nominal_r: 100 +#rtd_reference_r: 430 +#rtd_num_of_wires: 2 + +#[filament_switch_sensor material_0] +#switch_pin: PC2 + +#[extruder1] +#step_pin: PB0 +#dir_pin: PB1 +#enable_pin: !PC4 +#heater_pin: PA7 +#sensor_pin: PA2 +#... + +[heater_bed] +heater_pin: PA5 +sensor_type: Generic 3950 +sensor_pin: PA0 +control: watermark +min_temp: 0 +max_temp: 130 + +[fan] +pin: PA4 + +#[heater_fan fan1] +#pin: PA3 + +#[heater_fan SoC_fan] +#pin: CB1:gpio79 +#pin: RPI:gpio26 + +[mcu] +serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +######################################## +# TMC2209 configuration +######################################## + +#[tmc2209 stepper_x] +#uart_pin: PD9 +#run_current: 0.800 +#diag_pin: PD3 + +#[tmc2209 stepper_y] +#uart_pin: PD8 +#run_current: 0.800 +#diag_pin: PD2 + +#[tmc2209 stepper_z] +#uart_pin: PB10 +#run_current: 0.800 +#diag_pin: PC3 + +#[tmc2209 extruder] +#uart_pin: PB2 +#run_current: 0.600 +#diag_pin: PC2 + +#[tmc2209 extruder1] +#uart_pin: PA6 +#run_current: 0.600 +#diag_pin: + +######################################## +# TMC2130 configuration +######################################## + +#[tmc2130 stepper_x] +#cs_pin: PD9 +#spi_bus: spi2 +#run_current: 0.800 +#stealthchop_threshold: 999999 +#diag1_pin: PD3 + +#[tmc2130 stepper_y] +#cs_pin: PD8 +#spi_bus: spi2 +#run_current: 0.800 +#stealthchop_threshold: 999999 +#diag1_pin: PD2 + +#[tmc2130 stepper_z] +#cs_pin: PB10 +#spi_bus: spi2 +#run_current: 0.650 +#stealthchop_threshold: 999999 +#diag1_pin: PC3 + +#[tmc2130 extruder] +#cs_pin: PB2 +#spi_bus: spi2 +#run_current: 0.800 +#stealthchop_threshold: 999999 +#diag1_pin: PC2 + +#[tmc2130 extruder1] +#cs_pin: PA6 +#spi_bus: spi2 +#run_current: 0.800 +#stealthchop_threshold: 999999 +#diag1_pin: + +[board_pins] +aliases: + # EXP1 header + EXP1_1=PD5, EXP1_3=PB3, EXP1_5=PB5, EXP1_7=PB7, EXP1_9=, + EXP1_2=PD4, EXP1_4=PD6, EXP1_6=PB4, EXP1_8=PB6, EXP1_10=<5V>, + # EXP2 header + EXP2_1=PB14, EXP2_3=PB8, EXP2_5=PC10, EXP2_7=PC12, EXP2_9=, + EXP2_2=PB13, EXP2_4=PB9, EXP2_6=PB15, EXP2_8=, EXP2_10= + +# See the sample-lcd.cfg file for definitions of common LCD displays. + +#[bltouch] +#sensor_pin: PC13 +#control_pin: PC15 + +# Proximity switch +#[probe] +#pin: PC15 + +#[neopixel my_neopixel1] +#pin: PC11 + +#[neopixel my_neopixel2] +#pin: PC14 + +#[adxl345] +#cs_pin: PC0 +#spi_bus: spi2 diff --git a/config/generic-bigtreetech-manta-m8p.cfg b/config/generic-bigtreetech-manta-m8p-v1.0.cfg similarity index 98% rename from config/generic-bigtreetech-manta-m8p.cfg rename to config/generic-bigtreetech-manta-m8p-v1.0.cfg index 495fc2ab57c7..2a801cded459 100644 --- a/config/generic-bigtreetech-manta-m8p.cfg +++ b/config/generic-bigtreetech-manta-m8p-v1.0.cfg @@ -43,7 +43,7 @@ position_max: 270 #[stepper_] #step_pin: PD3 #dir_pin: PD2 -#enable_pin: PD5 +#enable_pin: !PD5 #endstop_pin: PC0 #... @@ -258,7 +258,7 @@ aliases: EXP2_3=PF7, EXP2_4=PB12, EXP2_5=PE7, EXP2_6=PB11, # Slot in the socket on this side EXP2_7=PE8, EXP2_8=, - EXP2_9=, EXP2_10=PC5 + EXP2_9=, EXP2_10= # See the sample-lcd.cfg file for definitions of common LCD displays. @@ -282,3 +282,7 @@ aliases: #[hall_filament_width_sensor] #adc1: PC5 #adc2: PB0 + +#[adxl345] +#cs_pin: PB15 +#spi_bus: spi1 diff --git a/config/generic-bigtreetech-manta-m8p-v1.1.cfg b/config/generic-bigtreetech-manta-m8p-v1.1.cfg new file mode 100644 index 000000000000..36ef710cde07 --- /dev/null +++ b/config/generic-bigtreetech-manta-m8p-v1.1.cfg @@ -0,0 +1,295 @@ +# This file contains common pin mappings for the BIGTREETECH Manta M8P +# To use this config, the firmware should be compiled for the +# STM32G0B1 with a "8KiB bootloader" "8 MHz crystal" +# and "USB (on PA11/PA12)" or "CAN bus (on PD12/PD13)". + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PE2 +dir_pin: PB4 +enable_pin: !PC11 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PF3 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_y] +step_pin: PF12 +dir_pin: PF11 +enable_pin: !PB3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PF4 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_z] +step_pin: PD7 +dir_pin: !PD6 +enable_pin: !PF10 +microsteps: 16 +rotation_distance: 8 +endstop_pin: ^PF5 +position_endstop: 0 +position_max: 270 + +# Motor4 +# The M8P only has 4 heater outputs which leaves an extra stepper +# This can be used for a second Z stepper, dual_carriage, extruder co-stepper, +# or other accesory such as an MMU +#[stepper_] +#step_pin: PD3 +#dir_pin: PD2 +#enable_pin: !PD5 +#endstop_pin: PC0 +#... + +[extruder] +step_pin: PC9 +dir_pin: PC8 +enable_pin: !PD1 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.4 +filament_diameter: 1.75 +heater_pin: PE3 # HE0 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PA1 # T0 +control: pid +pid_Kp: 22.2 +pid_Ki: 1.08 +pid_Kd: 114 +min_temp: 0 +max_temp: 250 + +#[filament_switch_sensor material_0] +#switch_pin: PC1 + +# Motor6 +#[extruder1] +#step_pin: PA10 +#dir_pin: PA14 +#enable_pin: !PA15 +#heater_pin: PB5 # HE1 +#sensor_pin: PA2 # T1 +#... + +#[filament_switch_sensor material_1] +#switch_pin: PC2 + +# Motor7 +#[extruder2] +#step_pin: PD11 +#dir_pin: PD9 +#enable_pin: !PD15 +#heater_pin: PB6 # HE2 +#sensor_pin: PA3 # T2 +#... + +# Motor8 +#[extruder3] +#step_pin: PD8 +#dir_pin: PC6 +#enable_pin: !PC7 +#heater_pin: PE1 # HE3 +#sensor_pin: PA4 # T3 +#... + +[heater_bed] +heater_pin: PB7 +sensor_type: Generic 3950 +sensor_pin: PA0 # TB +control: watermark +min_temp: 0 +max_temp: 130 + +[fan] +pin: PE6 + +#[heater_fan fan1] +#pin: PE0 + +#[heater_fan fan2] +#pin: PC12 + +#[heater_fan fan3] +#pin: PE5 + +#[heater_fan fan4] +#pin: PE4 + +#[heater_fan fan5] +#pin: PB8 +#tachometer_pin: PC14 + +#[heater_fan fan6] +#pin: PB9 +#tachometer_pin: PC15 + +#[heater_fan SoC_fan] +#pin: CB1:gpio79 +#pin: RPI:gpio26 + +[mcu] +serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +######################################## +# TMC2209 configuration +######################################## + +#[tmc2209 stepper_x] +#uart_pin: PC10 +##diag_pin: PF3 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_y] +#uart_pin: PF13 +##diag_pin: PF4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_z] +#uart_pin: PF9 +##diag_pin: PF5 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_] +#uart_pin: PD4 +##diag_pin: PC0 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder] +#uart_pin: PD0 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder1] +#uart_pin: PF8 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder2] +#uart_pin: PD14 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder3] +#uart_pin: PD10 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +######################################## +# TMC2130 configuration +######################################## + +#[tmc2130 stepper_x] +#cs_pin: PC10 +#spi_bus: spi1 +##diag1_pin: PF3 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_y] +#cs_pin: PF13 +#spi_bus: spi1 +##diag1_pin: PF4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_z] +#cs_pin: PF9 +#spi_bus: spi1 +##diag1_pin: PF5 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_] +#cs_pin: PD4 +#spi_bus: spi1 +##diag1_pin: PC0 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder] +#cs_pin: PD0 +#spi_bus: spi1 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder1] +#cs_pin: PF8 +#spi_bus: spi1 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder2] +#cs_pin: PD14 +#spi_bus: spi1 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder3] +#cs_pin: PD10 +#spi_bus: spi1 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +[board_pins] +aliases: + # EXP1 header + EXP1_1=PE9, EXP1_2=PE10, + EXP1_3=PE11, EXP1_4=PE12, + EXP1_5=PE13, EXP1_6=PE14, # Slot in the socket on this side + EXP1_7=PE15, EXP1_8=PB10, + EXP1_9=, EXP1_10=<5V>, + + # EXP2 header + EXP2_1=PB14, EXP2_2=PB13, + EXP2_3=PF7, EXP2_4=PB12, + EXP2_5=PE7, EXP2_6=PB11, # Slot in the socket on this side + EXP2_7=PE8, EXP2_8=, + EXP2_9=, EXP2_10= + +# See the sample-lcd.cfg file for definitions of common LCD displays. + +#[bltouch] +#sensor_pin: PB2 +#control_pin: PB1 + +# Proximity switch +#[probe] +#pin: PF6 + +#[output_pin ps_on_pin] +#pin: PC3 + +#[output_pin pc13_pin] +#pin: PC13 + +#[neopixel my_neopixel_1] +#pin: PA9 + +#[neopixel my_neopixel_2] +#pin: PB15 + +#[hall_filament_width_sensor] +#adc1: PC5 +#adc2: PB0 + +#[adxl345] +#cs_pin: PC4 +#spi_bus: spi1 diff --git a/config/generic-bigtreetech-octopus-max-ez.cfg b/config/generic-bigtreetech-octopus-max-ez.cfg new file mode 100644 index 000000000000..f1f153e86bb3 --- /dev/null +++ b/config/generic-bigtreetech-octopus-max-ez.cfg @@ -0,0 +1,332 @@ +# This file contains common pin mappings for the BIGTREETECH Octopus Max EZ. +# To use this config, the firmware should be compiled for the +# STM32H723 with a "128KiB bootloader" "25 MHz crystal" +# and "USB (on PA11/PA12)" or "CAN bus (on PD0/PD1)". + +# See docs/Config_Reference.md for a description of parameters. + +# Motor-1 +[stepper_x] +step_pin: PC13 +dir_pin: PC14 +enable_pin: !PE6 +microsteps: 16 +rotation_distance: 40 +endstop_pin: PF0 +position_endstop: 0 +position_max: 200 +homing_speed: 50 + +# Motor-2 +[stepper_y] +step_pin: PE4 +dir_pin: PE5 +enable_pin: !PE3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: PF2 +position_endstop: 0 +position_max: 200 +homing_speed: 50 + +# Motor-3 +[stepper_z] +step_pin: PE1 +dir_pin: PE0 +enable_pin: !PE2 +microsteps: 16 +rotation_distance: 8 +endstop_pin: PF4 +position_endstop: 0.5 +position_max: 200 + +# Motor-4 +# The Octopus only has 4 heater outputs which leaves an extra stepper +# This can be used for a second Z stepper, dual_carriage, extruder co-stepper, +# or other accesory such as an MMU +#[stepper_] +#step_pin: PB8 +#dir_pin: PB9 +#enable_pin: PB7 +#endstop_pin: PF3 +#... + +# Motor-5 +[extruder] +step_pin: PB5 +dir_pin: PB4 +enable_pin: !PB6 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PF6 # HE0 +sensor_pin: PB0 # T0 +sensor_type: EPCOS 100K B57560G104F +control: pid +pid_Kp: 22.2 +pid_Ki: 1.08 +pid_Kd: 114 +min_temp: 0 +max_temp: 250 + +#[filament_switch_sensor material_0] +#switch_pin: PF1 + +# Motor-6 +#[extruder1] +#step_pin: PG15 +#dir_pin: PB3 +#enable_pin: !PD5 +#heater_pin: PA0 # HE1 +#sensor_pin: PC5 # T1 +#... + +#[filament_switch_sensor material_1] +#switch_pin: PC15 + +# Motor-7 +#[extruder2] +#step_pin: PD3 +#dir_pin: PD2 +#enable_pin: !PD4 +#heater_pin: PF9 # HE2 +#sensor_pin: PC4 # T2 +#... + +# Motor-8 +#[extruder3] +#step_pin: PA10 +#dir_pin: PA9 +#enable_pin: !PA15 +#heater_pin: PF7 # HE3 +#sensor_pin: PA7 # T3 +#... + +# Motor-9 +#[extruder4] +#step_pin: PA8 +#dir_pin: PC7 +#enable_pin: !PC9 +#... + +# Motor-10 +#[extruder5] +#step_pin: PG6 +#dir_pin: PC6 +#enable_pin: !PC8 +#... + +[heater_bed] +heater_pin: PF5 +sensor_pin: PB1 # TB +sensor_type: ATC Semitec 104GT-2 +control: watermark +min_temp: 0 +max_temp: 130 + +[fan] +pin: PA6 + +#[heater_fan fan1] +#pin: PA5 + +#[heater_fan fan2] +#pin: PA4 + +#[heater_fan fan3] +#pin: PA3 + +#[heater_fan fan4] +#pin: PA1 +#tachometer_pin: PC3 + +#[heater_fan fan5] +#pin: PF8 +#tachometer_pin: PC1 + +#[heater_fan fan6] +#pin: PA2 +#tachometer_pin: PC2 + +[mcu] +serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +######################################## +# TMC2209 configuration +######################################## + +#[tmc2209 stepper_x] +#uart_pin: PG14 +##diag_pin: PF0 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_y] +#uart_pin: PG13 +##diag_pin: PF2 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_z] +#uart_pin: PG12 +##diag_pin: PF4 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2209 stepper_] +#uart_pin: PG11 +##diag_pin: PF3 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder] +#uart_pin: PG10 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder1] +#uart_pin: PG9 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder2] +#uart_pin: PD7 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder3] +#uart_pin: PD6 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder4] +#uart_pin: PG8 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2209 extruder5] +#uart_pin: PG7 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +######################################## +# TMC2130 configuration +######################################## + +#[tmc2130 stepper_x] +#cs_pin: PG14 +#spi_bus: spi4 +##diag1_pin: PF0 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_y] +#cs_pin: PG13 +#spi_bus: spi4 +##diag1_pin: PF2 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_z] +#cs_pin: PG12 +#spi_bus: spi4 +##diag1_pin: PF4 +#run_current: 0.650 +#stealthchop_threshold: 999999 + +#[tmc2130 stepper_] +#cs_pin: PG11 +#spi_bus: spi4 +##diag1_pin: PF3 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder] +#cs_pin: PG10 +#spi_bus: spi4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder1] +#cs_pin: PG9 +#spi_bus: spi4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder2] +#cs_pin: PD7 +#spi_bus: spi4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder3] +#cs_pin: PD6 +#spi_bus: spi4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder4] +#cs_pin: PG8 +#spi_bus: spi4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +#[tmc2130 extruder5] +#cs_pin: PG7 +#spi_bus: spi4 +#run_current: 0.800 +#stealthchop_threshold: 999999 + +[board_pins] +aliases: + # FPC header, Aliases EXP1 & EXP2 for mini12864 + EXP1_1=PG2, EXP1_2=PD15, + EXP1_3=PD14, EXP1_4=PD13, + EXP1_5=PD12, EXP1_6=PD11, + EXP1_7=PD10, EXP1_8=PE15, + EXP1_9=, EXP1_10=<5V>, + + # EXP2 header + EXP2_1=PE13, EXP2_2=PE12, + EXP2_3=PG5, EXP2_4=PE11, + EXP2_5=PG4, EXP2_6=PE14, + EXP2_7=PG3, EXP2_8=, + EXP2_9=, EXP2_10= + +# See the sample-lcd.cfg file for definitions of common LCD displays. + +#[bltouch] +#sensor_pin: PB14 +#control_pin: PB15 + +# Proximity switch +#[probe] +#pin: PF11 + +#[output_pin ps_on_pin] +#pin: PF13 + +#[output_pin pf12_pin] +#pin: PF12 + +#[neopixel my_neopixel_1] +#pin: PE10 + +#[neopixel my_neopixel_2] +#pin: PE9 + +#[hall_filament_width_sensor] +#adc1: PC0 +#adc2: PF10 + +#[adxl345] +#cs_pin: PF14 +#spi_bus: spi4 diff --git a/config/generic-bigtreetech-octopus.cfg b/config/generic-bigtreetech-octopus.cfg index d8deb0da5f7e..73bd584ca884 100644 --- a/config/generic-bigtreetech-octopus.cfg +++ b/config/generic-bigtreetech-octopus.cfg @@ -1,6 +1,12 @@ -# This file contains common pin mappings for the BigTreeTech Octopus. -# To use this config, the firmware should be compiled for the -# STM32F446 with a "32KiB bootloader" and a "12MHz crystal" clock reference. +# This file contains common pin mappings for the BigTreeTech Octopus +# and Octopus Pro boards. To use this config, start by identifying the +# micro-controller on the board - it may be an STM32F446, STM32F429, +# or an STM32H723. Select the appropriate micro-controller in "make +# menuconfig" and select "Enable low-level configuration options". For +# STM32F446 boards the firmware should be compiled with a "32KiB +# bootloader" and a "12MHz crystal" clock reference. For STM32F429 +# boards use a "32KiB bootloader" and an "8MHz crystal". For STM32H723 +# boards use a "128KiB bootloader" and a "25Mhz crystal". # See docs/Config_Reference.md for a description of parameters. diff --git a/config/generic-bigtreetech-skr-3.cfg b/config/generic-bigtreetech-skr-3.cfg index c769ae0399af..97570cd514fc 100644 --- a/config/generic-bigtreetech-skr-3.cfg +++ b/config/generic-bigtreetech-skr-3.cfg @@ -1,6 +1,8 @@ # This file contains common pin mappings for the BigTreeTech SKR 3. +# This board can ship with one of two chips, STM32H743 or STM32H723. # To use this config, during "make menuconfig" enable "low-level -# options", "STM32H743", "128KiB bootloader", and "25MHz clock". +# options", "STM32H743" or "STM32H723", "128KiB bootloader", +# and "25MHz clock". # See docs/Config_Reference.md for a description of parameters. diff --git a/config/generic-duet3-6hc.cfg b/config/generic-duet3-6hc.cfg new file mode 100644 index 000000000000..e8f552055571 --- /dev/null +++ b/config/generic-duet3-6hc.cfg @@ -0,0 +1,152 @@ +# This file contains common pin mappings for the Duet3 6HC. To use +# this config, the firmware should be compiled for the SAME70Q20B. + +# To flash the board, erase the existing firmware by jumpering the erase jumper. +# Boot the board, wait for reset to complete, remove the jumper, and then reboot the board, +# as described in Duet's documentation: +# https://docs.duet3d.com/en/User_manual/RepRapFirmware/Updating_firmware#all-other-duet-boards +# Then run: make flash FLASH_DEVICE=/dev/ttyACM0 + +# See docs/Config_Reference.md for a description of parameters. + + +# Pins for reference, v1.02 board: +# Driver Step Pins - 0:PC18 1:PC16 2:PC28 3:PC1 4:PC4 5:PC9 +# Driver Dir Pins - 0:PB5 1:PD10 2:PA4 3:PA22 4:PC3 5:PD14 +# Driver Enable - !PA9 +# Driver CS - PD17 +# Thermistor Pins - TEMP0:PC15 TEMP1:PC29 TEMP2:PC30 TEMP3:PC31 +# Pullup Resistor - 2200 +# Vssa Sense:PC13 | Vref Sense:PC0 +# Current Sense resistor for drivers - 0.05ohm +# SPI lines:{PC25} -> SPIMosi:PC27 SPIMiso:PC26 SPISCLK:PC24 +# Vin Monitor:PA20 +# CAN Pins - TX0:PB2 RX0:PB3 TX1:PD12 RX1:PC12 +# Heaters - Out0:PA7 Out1:PA24 Out2:PA16 Out3:PA11 +# Fan outputs - Out4:PA15 Out5:PC5 Out6:PA8 Out7:PC11 Out8:PC8 Out9:PA12 | Out9 is shared with VFD_Out +# Tach Pins for Fans - Out4.Tach:PC7 Out5.Tach:PD23 Out6.Tach:PA1 +# GPIO_out - IO0:PD26 IO1:PD16 IO2:PD27 IO3:PA3 IO4:PE0 IO5:PD21 IO6:PA0 IO7:PD23 IO8:PE1 +# GPIO_in - IO0:PD25 IO1:PD15 IO2:PD28 IO3:PE5 IO4:PD30 IO5:PA19 IO6:PA18 IO7:PA17 IO8:PE3 +# Driver Diag - 0:PD29 1:PC17 2:PD13 3:PC2 4:PD31 5:PC10 + +[stepper_x] +#driver 0 +step_pin: PC18 +dir_pin: PB5 +enable_pin: !PA9 +microsteps: 128 +rotation_distance: 40 +endstop_pin: PD25 #IO0 +position_endstop: 0 +position_max: 450 + +[tmc5160 stepper_x] +cs_pin: PD17 +spi_bus: usart1 +chain_position: 1 +chain_length: 6 +interpolate: False +run_current: 1 +sense_resistor: 0.05 + +[stepper_y] +#driver 1 +step_pin: PC16 +dir_pin: PD10 +enable_pin: !PA9 +microsteps: 128 +rotation_distance: 40 +endstop_pin: PD15 #IO1 +position_endstop: 0 +position_max: 450 + +[tmc5160 stepper_y] +cs_pin: PD17 +chain_position: 2 +chain_length: 6 +interpolate: False +run_current: 1.0 +sense_resistor: 0.05 + +[stepper_z] +#driver2 +step_pin: PC28 +dir_pin: PA4 +enable_pin: !PA9 +microsteps: 64 +rotation_distance: 8 +endstop_pin: PD28 #IO2 +position_endstop: 0 +position_min: 0 +position_max: 400 + +[tmc5160 stepper_z] +cs_pin: PD17 +chain_position: 3 +chain_length: 6 +interpolate: False +run_current: 1.0 +sense_resistor: 0.05 + +[adc_scaled vref_scaled] +vref_pin: PC0 +vssa_pin: PC13 + +[extruder] +#driver3 +step_pin: PC1 +dir_pin: PA22 +enable_pin: !PA9 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA24 #Out1 +sensor_type: ATC Semitec 104GT-2 +pullup_resistor: 2200 +sensor_pin: vref_scaled:PC29 #Temp1 +control: pid +pid_Kp: 30.089 +pid_Ki: 2.229 +pid_Kd: 101.550 +min_temp: 0 +max_temp: 285 + +[tmc5160 extruder] +cs_pin: PD17 +chain_position: 4 +chain_length: 6 +interpolate: False +run_current: .6 +sense_resistor: 0.05 + +[heater_fan heatbreak_fan] +pin: PC8 #Out8 +heater: extruder +heater_temp: 50.0 + +[heater_bed] +heater_pin: PA7 #Out0 +sensor_type: Generic 3950 +sensor_pin: vref_scaled:PC15 #Temp0 +control: pid +pullup_resistor: 2200 +pid_Kp: 61.049 +pid_Ki: 2.339 +pid_Kd: 398.344 +min_temp: 0 +max_temp: 130 + +[heater_fan heatbreak_fan] +pin: PA15 #Out4 + +[fan] +pin: PC5 #Out5 + +[mcu] +serial: /dev/ttyACM0 + +[printer] +kinematics: cartesian +max_velocity: 350 +max_accel: 3000 diff --git a/config/generic-duet3-6xd.cfg b/config/generic-duet3-6xd.cfg new file mode 100644 index 000000000000..d4681f8be3a6 --- /dev/null +++ b/config/generic-duet3-6xd.cfg @@ -0,0 +1,108 @@ +# This file contains common pin mappings for the Duet3 6XD. To use +# this config, the firmware should be compiled for the SAME70Q20B. + +# To flash the board, erase the existing firmware by jumpering the erase jumper. +# Boot the board, wait for reset to complete, remove the jumper, and then reboot the board, +# as described in Duet's documentation: +# https://docs.duet3d.com/en/User_manual/RepRapFirmware/Updating_firmware#all-other-duet-boards +# Then run: make flash FLASH_DEVICE=/dev/ttyACM0 + +# See docs/Config_Reference.md for a description of parameters. + + +# Pins for reference, v1.0 board: +# Driver Step Pins - 0:PC18 1:PC16 2:PC28 3:PC1 4:PC4 5:PC9 +# Driver Dir Pins - 0:PB5 1:PD10 2:PA4 3:PA22 4:PC3 5:PD14 +# Driver En Pins - 0:PB4 1:PA21 2:PC20 3:PA23 4:PA2 5:PD17 +# Driver Err Pins - 0:PD29 1:PC17 2:PD13 3:PC2 4:PD31 5:PC10 +# Thermistor Pins - TEMP0:PC15 TEMP1:PC29 TEMP2:PC0 TEMP3:PC31 +# Pullup Resistor - 2200 +# Vssa Sense:PC13 | Vref Sense:PC30 +# SPI0:{PD19, PA5, PA6, PD20, PC22} -> SPIMosi:PB1 SPIMiso:PB0 SPISCLK:PB13 +# SPI1:{PC25} -> SPIMosi:PC27 SPIMiso:PC26 SPISCLK:PC24 DATA_RDY:PE2 +# Vin Monitor:PA20 +# LED's - Diag:PB6, Act:PB7 +# CAN Pins - TX0:PB2 RX0:PB3 TX1:PD12 RX1:PC12 +# Heaters - Out0:PA24 Out1:PA16 Out2:PA11 +# Fan outputs - Out3:PA15 Out4:PC5 Out5:PA8 Out6:PC11 Out7:PC8 Out8:PA12 +# Tach Pins for Fans - Out3.Tach:PC7 Out4.Tach:PD23 Out5.Tach:PA1 +# VFD - PA7 +# GPIO_out - IO0:PD26 IO1:PD16 IO2:PD27 IO3:PA3 IO4:PE0 IO5:PD21 IO6:PA0 IO7:PD23 IO8:PE1 +# GPIO_in - IO0:PD25 IO1:PD15 IO2:PD28 IO3:PE5 IO4:PD30 IO5:PA19 IO6:PA18 IO7:PA17 IO8:PE3 + +[stepper_x] +#driver 0 +step_pin: PC18 +dir_pin: PB5 +enable_pin: PB4 +microsteps: 128 +rotation_distance: 40 +endstop_pin: PD25 #IO0 +position_endstop: 0 +position_max: 450 + +[stepper_y] +#driver 1 +step_pin: PC16 +dir_pin: PD10 +enable_pin: PA21 +microsteps: 128 +rotation_distance: 40 +endstop_pin: PD15 #IO1 +position_endstop: 0 +position_max: 450 + +[stepper_z] +#driver2 +step_pin: PC28 +dir_pin: PA4 +enable_pin: PC20 +microsteps: 64 +rotation_distance: 8 +endstop_pin: PD28 #IO2 +position_endstop: 0 +position_min: 0 +position_max: 400 + +[adc_scaled vref_scaled] +vref_pin: PC30 +vssa_pin: PC13 + +[extruder] +#driver3 +step_pin: PC1 +dir_pin: PA22 +enable_pin: PA23 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA24 #Out0 +sensor_type: ATC Semitec 104GT-2 +pullup_resistor: 2200 +sensor_pin: vref_scaled:PC29 #Temp1 +control: pid +pid_Kp: 30.089 +pid_Ki: 2.229 +pid_Kd: 101.550 +min_temp: 0 +max_temp: 285 + +[heater_fan heatbreak_fan] +pin: PC8 #Out7 +heater: extruder +heater_temp: 50.0 + +[heater_fan heatbreak_fan] +pin: PA15 #Out3 + +[fan] +pin: PC5 #Out4 + +[mcu] +serial: /dev/ttyACM0 + +[printer] +kinematics: cartesian +max_velocity: 350 +max_accel: 3000 diff --git a/config/generic-fysetc-cheetah-v2.0.cfg b/config/generic-fysetc-cheetah-v2.0.cfg new file mode 100644 index 000000000000..b157403f1501 --- /dev/null +++ b/config/generic-fysetc-cheetah-v2.0.cfg @@ -0,0 +1,138 @@ +# This file contains common pin mappings for the Fysetc Cheetah V2.0 +# To use this config, the firmware should be compiled for the +# STM32F401 with a "32KiB bootloader". + +# Rename "klipper.bin" to "firmware.bin", copy to Sdcard and insert in motherboard + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PC0 +dir_pin: PC1 +enable_pin: !PA8 +rotation_distance: 40 +microsteps: 64 +endstop_pin: ^PB4 +position_endstop: 0 +position_max: 200 +homing_speed: 50 + +[tmc2209 stepper_x] +uart_pin: PA3 +tx_pin: PA2 +uart_address: 0 +run_current: 0.800 +interpolate: false +stealthchop_threshold: 0 + +[stepper_y] +step_pin: PC14 +dir_pin: !PC13 +enable_pin: !PC15 +rotation_distance: 40 +microsteps: 64 +endstop_pin: ^PC8 +position_endstop: 0 +position_max: 200 +homing_speed: 50 + +[tmc2209 stepper_y] +uart_pin: PA3 +tx_pin: PA2 +uart_address: 2 +run_current: 0.800 +interpolate: false +stealthchop_threshold: 0 + +[stepper_z] +step_pin: PB9 +dir_pin: PB8 +enable_pin: !PC2 +rotation_distance: 8 +microsteps: 64 +endstop_pin: ^PB1 +position_endstop: 0 +position_max: 200 + +[tmc2209 stepper_z] +uart_pin: PA3 +tx_pin: PA2 +uart_address: 1 +run_current: 0.800 +interpolate: false +stealthchop_threshold: 0 + +[extruder] +step_pin: PB2 +dir_pin: !PA15 +enable_pin: !PD2 +rotation_distance: 33.500 +microsteps: 16 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PC6 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC4 +control: pid +pid_kp: 21.527 +pid_ki: 1.063 +pid_kd: 108.982 +min_temp: 0 +max_temp: 250 + +[tmc2209 extruder] +uart_pin: PA3 +tx_pin: PA2 +uart_address: 3 +run_current: 0.800 +interpolate: false +stealthchop_threshold: 0 + +[heater_bed] +heater_pin: PC7 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC5 +control: pid +pid_kp: 54.027 +pid_ki: 0.770 +pid_kd: 948.182 +min_temp: 0 +max_temp: 120 + +[fan] +pin: PA1 + +[heater_fan my_hotend_fan] +pin: PA13 +heater: extruder +heater_temp: 50.0 + +[controller_fan my_controller_fan] +pin: PA14 +heater: extruder, heater_bed +stepper: stepper_x, stepper_y, stepper_z, extruder + +[printer] +kinematics: cartesian +max_velocity: 500 +max_accel: 5000 +max_z_velocity: 5 +max_z_accel: 1000 + +[mcu] +serial: INSERTSERIALIDHERE + +[board_pins] +aliases: + # EXP1 header + EXP1_1=<5V>, EXP1_3=, EXP1_5=PA7, EXP1_7=PA4, EXP1_9=PA5, + EXP1_2=, EXP1_4=PC3, EXP1_6=PC11, EXP1_8=PC10, EXP1_10=PA6, + + # EXP2 header + EXP2_1=<5V>, EXP2_3=PB7, EXP2_5=PB14, EXP2_7=PB12, EXP2_9=PC12, + EXP2_2=, EXP2_4=PB6, EXP2_6=PB13, EXP2_8=PB15, EXP2_10=PC9, + + # EXP3 header + EXP3_1=PC9, EXP3_3=PC10, EXP3_5=PC11, EXP3_7=PB12, EXP3_9=, + EXP3_2=PC12, EXP3_4=PB14, EXP3_6=PB13, EXP3_8=PB15, EXP3_10=<5V> + # Pins EXP1_4, EXP1_8, EXP1_6 are also MISO, MOSI, SCK of bus "spi2" diff --git a/config/generic-th3d-ezboard-lite-v2.0.cfg b/config/generic-th3d-ezboard-v2.0.cfg similarity index 97% rename from config/generic-th3d-ezboard-lite-v2.0.cfg rename to config/generic-th3d-ezboard-v2.0.cfg index 731f48a25d62..4d32280ff8a9 100644 --- a/config/generic-th3d-ezboard-lite-v2.0.cfg +++ b/config/generic-th3d-ezboard-v2.0.cfg @@ -1,4 +1,4 @@ -# This file contains common pin mappings for the TH3D EZBoard Lite v2. +# This file contains common pin mappings for the TH3D EZBoard v2. # To use this config, check "Enable extra low-level configuration options" # and compile the firmware for the STM32F405 with 12mhz Crystal, # 48KiB Bootloader, and USB communication. diff --git a/config/printer-anycubic-kobra-go-2022.cfg b/config/printer-anycubic-kobra-go-2022.cfg new file mode 100644 index 000000000000..525a50bd2837 --- /dev/null +++ b/config/printer-anycubic-kobra-go-2022.cfg @@ -0,0 +1,133 @@ +# This file contains a configuration for the Anycubic Kobra Go printer. +# +# See docs/Config_Reference.md for a description of parameters. +# +# To build the firmware, use the following configuration: +# - Micro-controller: Huada Semiconductor HC32F460 +# - Communication interface: Serial (PA3 & PA2) - Anycubic +# +# Installation: +# 1. Rename the klipper bin to `firmware.bin` and copy it to an SD Card. +# 2. Power off the Printer, insert the SD Card and power it on. +# 3. The the LCD will be stuck on the Firmware-update screen. +# Just Wait for 3-5 minutes to ensure the firmware is flashed. +# 4. After waiting, shutdown the printer and remove the SD Card. + +[stepper_x] +step_pin: PA12 +dir_pin: PA11 +enable_pin: !PA15 +microsteps: 16 +rotation_distance: 40 +endstop_pin: !PH2 +position_endstop: -13 +position_min:-13 +position_max: 238 +homing_speed: 50 + +[stepper_y] +step_pin: PA9 +dir_pin: PA8 +enable_pin: !PA15 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^!PC13 +position_endstop: -9 +position_min:-9 +position_max: 238 +homing_speed: 50 + +[stepper_z] +step_pin: PC7 +dir_pin: !PC6 +enable_pin: !PA15 +microsteps: 16 +rotation_distance: 8 +endstop_pin: ^PC14 +position_endstop: 0 +position_min: -10 +position_max: 250 +homing_speed: 5 + +[extruder] +step_pin: PB15 +dir_pin: PB14 +enable_pin: !PA15 +microsteps: 16 +rotation_distance: 31.07 +max_extrude_only_velocity: 25 +max_extrude_only_accel: 1000 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PB8 +sensor_type: ATC Semitec 104GT-2 +sensor_pin: PC3 +min_extrude_temp: 170 +min_temp: 0 +max_temp: 250 +control: pid +pid_kp: 19.56 +pid_ki: 1.62 +pid_kd: 200.00 + +[heater_bed] +heater_pin: PB9 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC1 +min_temp: 0 +max_temp: 120 +control: pid +pid_kp: 97.1 +pid_ki: 1.41 +pid_kd: 1675.16 + +[bed_mesh] +speed: 200 +horizontal_move_z: 2.5 +mesh_min: 5, 5 +mesh_max: 217.2, 207.8 +probe_count: 5, 5 + +[probe] +pin: PA1 +x_offset: -20.8 +y_offset: 0 +z_offset: 0 +samples: 3 +samples_result: average +samples_tolerance_retries: 3 +sample_retract_dist: 0.5 +speed: 2 +lift_speed: 4 + +[safe_z_home] +home_xy_position: 0, 0 +speed: 5 +z_hop: 10 +z_hop_speed: 15 + +[controller_fan controller_fan] +pin: PB12 + +[heater_fan extruder_fan] +pin: PB13 + +[fan] +pin: PB5 +cycle_time: 0.00005 #20kHz + +[output_pin enable_pin] +pin: PB6 +static_value: 1 + #This pin enables the bed, hotend, extruder fan, part fan. + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 500 +max_z_velocity: 4 +max_z_accel: 100 diff --git a/config/printer-anycubic-kobra-plus-2022.cfg b/config/printer-anycubic-kobra-plus-2022.cfg new file mode 100644 index 000000000000..96099797042c --- /dev/null +++ b/config/printer-anycubic-kobra-plus-2022.cfg @@ -0,0 +1,197 @@ +# This file contains a configuration for the Anycubic Kobra Plus printer. +# +# The Kobra Plus mainboard must be modified to correct conflicting UART +# addresses. As delivered, the X stepper and E0 stepper use UART address 0. +# To correct, move resistor R65 to R66. This moves the X stepper to address 3. +# +# After making this modification, any future firmwares will need to use the new +# address for the X stepper. To revert to the stock firmware, either undo the +# modification, or recompile the stock firmware using the correct addresses for +# X_SLAVE_ADDRESS and E0_SLAVE_ADDRESS. +# +# See docs/Config_Reference.md for a description of parameters. +# +# To build the firmware, use the following configuration: +# - Micro-controller: Huada Semiconductor HC32F460 +# - Communication interface: Serial (PA3 & PA2) - Anycube +# +# Installation: +# 1. Rename the klipper bin to `firmware.bin` and copy it to an SD Card. +# 2. Power off the Printer, insert the SD Card and power it on. +# 3. The printer should beep several times and the LCD will be stuck on the +# Splash screen. + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 1800 +max_z_velocity: 40 +max_z_accel: 100 + +[stepper_x] +step_pin: PA5 +dir_pin: PA4 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: !PA6 +position_min: -4 +position_endstop: -4 +position_max: 304 +homing_speed: 100 + +[tmc2209 stepper_x] +uart_pin: PA15 +tx_pin: PA9 +sense_resistor: 0.100 +run_current: 0.9 +uart_address: 3 +stealthchop_threshold: 999999 + +[stepper_y] +step_pin: PC4 +dir_pin: PA7 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 32 +endstop_pin: !PC5 +position_min: -6 +position_endstop: -6 +position_max: 300 +homing_speed: 100 + +[tmc2209 stepper_y] +uart_pin: PA15 +tx_pin: PA9 +sense_resistor: 0.100 +run_current: 0.9 +uart_address: 1 +stealthchop_threshold: 999999 + +[stepper_z] +step_pin: PC7 +dir_pin: !PC6 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 8 +endstop_pin: PA8 +position_endstop: 0 +position_min: -15 +position_max: 350 +homing_speed: 10 + +[tmc2209 stepper_z] +uart_pin: PA15 +tx_pin: PA9 +sense_resistor: 0.100 +run_current: 0.9 +uart_address: 2 +stealthchop_threshold: 999999 + +[stepper_z1] +step_pin: PB1 +dir_pin: !PB0 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 8 + +[extruder] +max_extrude_only_distance: 200 +max_extrude_only_velocity: 60 +max_extrude_only_accel: 3000 +step_pin: PC14 +dir_pin: !PC15 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 7.71 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC1 +min_extrude_temp: 170 +control: pid +pid_kp: 22.20 +pid_ki: 1.08 +pid_kd: 119.0 +min_temp: 0 +max_temp: 275 + +[tmc2208 extruder] +uart_pin: PA15 +tx_pin: PA9 +sense_resistor: 0.100 +run_current: 0.8 +uart_address: 0 +stealthchop_threshold: 999999 + +[heater_bed] +heater_pin: PA0 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC0 +control: pid +pid_kp: 97.1 +pid_ki: 1.41 +pid_kd: 1675.16 +min_temp: 0 +max_temp: 120 + +[filament_switch_sensor runout] +pause_on_runout: True +switch_pin: !PC13 + +[heater_fan controller_fan] +pin: PA14 +heater: heater_bed +heater_temp: 45.0 + +[heater_fan hotend_fan] +pin: PA13 + +[fan] +pin: PB9 + +[probe] +pin: !PB6 +speed: 2.0 +lift_speed: 4.0 +samples: 2 +sample_retract_dist: 5 +samples_tolerance_retries: 3 +z_offset: 0.2 +activate_gcode: probe_reset + +[output_pin probe_reset_pin] +pin: PB7 +value: 1 + +[safe_z_home] +home_xy_position: 0, 0 +speed: 100 +z_hop: 10 +z_hop_speed: 15 +move_to_previous: False + +[bed_mesh] +speed: 100 +mesh_min: 10, 10 +mesh_max: 290, 290 +algorithm: bicubic +probe_count: 5, 5 + +[gcode_macro probe_reset] +gcode: + SET_PIN PIN=probe_reset_pin VALUE=0 + G4 P300 + SET_PIN PIN=probe_reset_pin VALUE=1 + G4 P100 + +[output_pin LED] +pin: PB8 + +[output_pin beeper] +pin: PB5 diff --git a/config/printer-anycubic-vyper-2021.cfg b/config/printer-anycubic-vyper-2021.cfg index 08cf56e8d646..a98cb2bc7174 100644 --- a/config/printer-anycubic-vyper-2021.cfg +++ b/config/printer-anycubic-vyper-2021.cfg @@ -102,6 +102,10 @@ max_temp: 110 [fan] pin: PA0 +[controller_fan controller_fan] +pin: PA14 +stepper: stepper_x,stepper_y,stepper_z,stepper_z1 + [probe] pin: !PB12 z_offset: 0 diff --git a/config/printer-artillery-sidewinder-x2-2022.cfg b/config/printer-artillery-sidewinder-x2-2022.cfg index cc92dbf4ba79..67e83587f14f 100644 --- a/config/printer-artillery-sidewinder-x2-2022.cfg +++ b/config/printer-artillery-sidewinder-x2-2022.cfg @@ -132,9 +132,9 @@ screw1_name: front left screw2: 223,63 screw2_name: front right screw3: 223,263 -screw3_name: back left +screw3_name: back right screw4: 23,263 -screw4_name: back right +screw4_name: back left speed: 100.0 screw_thread: CW-M5 diff --git a/config/printer-creality-cr5pro-ht-2022.cfg b/config/printer-creality-cr5pro-ht-2022.cfg new file mode 100644 index 000000000000..6e8d3db04c5e --- /dev/null +++ b/config/printer-creality-cr5pro-ht-2022.cfg @@ -0,0 +1,152 @@ +# This file contains common pin mappings for the Creality CR5 Pro HT. +# The mainboard is a Creality 3D v2.5.1 (8-bit mainboard with +# ATMega2560). To use this config, the firmware should be compiled for +# the AVR atmega2560. + +# See docs/Config_Reference.md for a description of parameters. +[stepper_x] +step_pin: PF0 #ar54 +dir_pin: !PF1 #ar55 +enable_pin: !PD7 #!ar38 +microsteps: 16 +rotation_distance: 40 # 16 microsteps * 200 steps/rotation / 80 steps/mm +endstop_pin: ^!PE5 #^ar3 +position_min: 0 +position_max: 300 +position_endstop: 0 +homing_speed: 50 + +[stepper_y] +step_pin: PF6 #ar60 +dir_pin: !PF7 #ar61 +enable_pin: !PF2 #!ar56 +microsteps: 16 +rotation_distance: 40 # 16 microsteps * 200 steps/rotation / 80 steps/mm +endstop_pin: ^!PJ1 #^ar14 +position_endstop: 0 +position_max: 220 +homing_speed: 50 + +[stepper_z] +step_pin: PL3 #ar46 +dir_pin: !PL1 #!ar48 +enable_pin: !PK0 #!ar62 +microsteps: 16 +rotation_distance: 4 # 16 microsteps * 200 steps/rotation / 800 steps/mm +position_max: 380 +position_min: -10 +endstop_pin: probe:z_virtual_endstop + +[safe_z_home] +home_xy_position: 140, 110 +speed: 80 +z_hop: 10 +z_hop_speed: 10 + +[extruder] +step_pin: PA4 # ar26 +dir_pin: !PA6 # !ar28 +enable_pin: !PA2 # !ar24 +microsteps: 16 +rotation_distance: 23.24736 # 16 microsteps * 200 steps/rotation / 137.65 steps/mm +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PB4 #ar10 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PK5 #analog13 +control: pid +pid_kp: 17.647 +pid_ki: 1.079 +pid_kd: 72.131 +min_temp: 0 +max_temp: 300 + +[heater_bed] +heater_pin: PH5 #ar8 +sensor_type: ATC Semitec 104GT-2 +sensor_pin: PK6 #analog14 +control: pid +pid_kp: 75.501 +pid_ki: 2.542 +pid_kd: 560.598 +min_temp: 0 +max_temp: 130 + +[fan] +pin: PH6 #ar9 + +[mcu] +serial: /dev/ttyUSB0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 2000 +max_z_velocity: 5 +max_z_accel: 100 + +#[display] +# DWIN screen currently unsupported + +[bltouch] +sensor_pin: ^PD2 #^ar19 +control_pin: PB5 #ar11 +set_output_mode: 5V +pin_move_time: 0.4 +x_offset: 37.0 +y_offset: 0.0 +z_offset: 2.40 +samples: 2 +sample_retract_dist: 2 +samples_result: average + +[bed_mesh] +speed: 50 +horizontal_move_z: 6 +mesh_min: 47,10 +mesh_max: 270,210 +probe_count: 7,7 +algorithm: bicubic + +[pause_resume] +recover_velocity: 50 + +[filament_switch_sensor fil_runout_sensor] +pause_on_runout: True +switch_pin: !PE4 #ar2 + +[bed_screws] +screw1: 8,5 +screw1_name: front left screw +screw2: 8,210 +screw2_name: rear left screw +screw3: 218,210 +screw3_name: rear right screw +screw4: 218,5 +screw4_name: front right screw + +[screws_tilt_adjust] +screw1: 8,5 +screw1_name: front left screw +screw2: 8,210 +screw2_name: rear left screw +screw3: 218,210 +screw3_name: rear right screw +screw4: 218,5 +screw4_name: front right screw +speed: 50 +horizontal_move_z: 10 +screw_thread: CW-M4 + +[output_pin case_light] +pin: PH4 #ar7 +value: 1 + +[gcode_macro CASE_LIGHT_ON] +gcode: + SET_PIN PIN=case_light VALUE=1 + +[gcode_macro CASE_LIGHT_OFF] +gcode: + SET_PIN PIN=case_light VALUE=0 diff --git a/config/printer-creality-ender2pro-2021.cfg b/config/printer-creality-ender2pro-2021.cfg index 3400890baf86..b105622c3905 100644 --- a/config/printer-creality-ender2pro-2021.cfg +++ b/config/printer-creality-ender2pro-2021.cfg @@ -5,7 +5,7 @@ # If you prefer a direct serial connection, in "make menuconfig" # select "Enable extra low-level configuration options" and select -# serial (on USART3 PB11/PB10), which is broken out on the 10 pin IDC +# serial (on USART2 PA3/PA2), which is broken out on the 10 pin IDC # cable used for the LCD module as follows: # 3: Tx, 4: Rx, 9: GND, 10: VCC diff --git a/config/printer-creality-ender3-s1-2021.cfg b/config/printer-creality-ender3-s1-2021.cfg index e46ae6def30f..6c64be0e3f71 100644 --- a/config/printer-creality-ender3-s1-2021.cfg +++ b/config/printer-creality-ender3-s1-2021.cfg @@ -129,3 +129,9 @@ runout_gcode: PAUSE [pause_resume] recover_velocity: 25 + +[bed_screws] +screw1: 20, 29 +screw2: 195, 29 +screw3: 195, 198 +screw4: 20, 198 diff --git a/config/printer-creality-ender3-v2-neo-2022.cfg b/config/printer-creality-ender3-v2-neo-2022.cfg new file mode 100644 index 000000000000..169778bca121 --- /dev/null +++ b/config/printer-creality-ender3-v2-neo-2022.cfg @@ -0,0 +1,155 @@ +# This file contains pin mappings for the stock 2020 Creality Ender 3 +# V2 Neo. To use this config, during "make menuconfig" select the +# STM32F103 with a "28KiB bootloader" and serial (on USART1 PA10/PA9) +# communication. + +# If you prefer a direct serial connection, in "make menuconfig" +# select "Enable extra low-level configuration options" and select +# serial (on USART3 PB11/PB10), which is broken out on the 10 pin IDC +# cable used for the LCD module as follows: +# 3: Tx, 4: Rx, 9: GND, 10: VCC + +# Flash this firmware by copying "out/klipper.bin" to a SD card and +# turning on the printer with the card inserted. The firmware +# filename must end in ".bin" and must not match the last filename +# that was flashed. + +# This also works for the GD32F303 based Creality 4.2.2 board. + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PC2 +dir_pin: PB9 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PA5 +position_endstop: 0 +position_max: 235 +homing_speed: 80 + +[stepper_y] +step_pin: PB8 +dir_pin: PB7 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PA6 +position_endstop: 0 +position_max: 235 +homing_speed: 80 + +[stepper_z] +step_pin: PB6 +dir_pin: !PB5 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 8 +endstop_pin: probe:z_virtual_endstop +position_max: 250 +homing_speed: 4 +second_homing_speed: 1 +homing_retract_dist: 2.0 + +[extruder] +max_extrude_only_distance: 100.0 +step_pin: PB4 +dir_pin: PB3 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 34.406 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC5 +control: pid +# tuned for stock hardware with 200 degree Celsius target +pid_Kp: 21.527 +pid_Ki: 1.063 +pid_Kd: 108.982 +min_temp: 0 +max_temp: 250 + +[heater_bed] +heater_pin: PA2 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC4 +control: pid +# tuned for stock hardware with 70 degree Celsius target +pid_kp: 70.405 +pid_ki: 1.229 +pid_kd: 1008.553 +min_temp: 0 +max_temp: 130 + +[fan] +pin: PA0 + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 5000 +max_z_velocity: 5 +square_corner_velocity: 5.0 +max_z_accel: 100 + +[bltouch] +sensor_pin: ^PB1 +control_pin: PB0 +x_offset: -45.0 +y_offset: -10.0 +z_offset: 0 +speed: 20 +samples: 1 +sample_retract_dist: 8.0 + +[safe_z_home] +home_xy_position: 160,120 +speed: 150 +z_hop: 10 +z_hop_speed: 10 + +[bed_mesh] +speed: 120 +mesh_min: 30,30 # Need to handle head distance with cr-touch (bl_touch) +mesh_max: 189,189 # Max probe range +probe_count: 5,5 +fade_start: 1 +fade_end: 10 +fade_target: 0 +algorithm: bicubic + +[bed_screws] +screw1:30,25 +screw1_name:1 +screw2:200,25 +screw2_name:2 +screw3:200,195 +screw3_name:3 +screw4:30,195 +screw4_name:4 + +[screws_tilt_adjust] +screw1: 67, 42 +screw1_name: front left screw +screw2: 237.60, 42 +screw2_name: front right screw +screw3: 237.60, 212 +screw3_name: rear right screw +screw4: 67.60, 212 +screw4_name: rear left screw +horizontal_move_z: 10 +speed: 200 +screw_thread: CW-M4 # Use CW for Clockwise and CCW for Counter Clockwise + +# [display] +# The Ender 3 v2 Neo's 4.3" LCD display is not supported by klipper + +[output_pin beeper] +pin: PB13 diff --git a/config/printer-elegoo-neptune3-pro-2023.cfg b/config/printer-elegoo-neptune3-pro-2023.cfg new file mode 100644 index 000000000000..c736544b57c6 --- /dev/null +++ b/config/printer-elegoo-neptune3-pro-2023.cfg @@ -0,0 +1,126 @@ +# This file contains pin mappings for the stock Elegoo Neptune 3 Pro (ZNP Robin Nano_DW V2.2) +# To use this config, during "make menuconfig" select the STM32F401 with a +# "32KiB bootloader" and serial (on USART1 PA10/PA9) communication. + +# Note that the "make flash" command does not work with ZNP Robin boards. +# After running "make", rename the out/klipper.bin file to out/ZNP_ROBIN_NANO.bin +# Copy the file out/ZNP_ROBIN_NANO.bin to an SD card formatted to FAT32 +# and then restart the printer with the SD card inserted. + +# See docs/Config_Reference.md for a description of parameters. + +# Core + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +# Steppers + +[stepper_x] +step_pin: PC12 +dir_pin: PB3 +enable_pin: !PD2 +microsteps: 16 +rotation_distance: 40 +endstop_pin: PA13 +position_min: -5 +position_endstop: -5 +position_max: 235 +homing_speed: 50 + +[stepper_y] +step_pin: PC11 +dir_pin: PA15 +enable_pin: !PC10 +microsteps: 16 +rotation_distance: 40 +endstop_pin: PB8 +position_endstop: 0 +position_max: 234 +homing_speed: 50 + +[stepper_z] +step_pin: PC7 +dir_pin: !PC9 +enable_pin: !PC8 +microsteps: 16 +rotation_distance: 8 +position_min: -0.8 +endstop_pin: probe:z_virtual_endstop +position_max: 283 +homing_speed: 10 + +[probe] +pin: PA8 +# NOTE: Set this to a value based on your printer and bed. +z_offset: 0 +x_offset: -28.5 +y_offset: 22 + +[extruder] +step_pin: PB10 +dir_pin: PB1 +enable_pin: !PC6 +microsteps: 16 +rotation_distance: 8.42 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA6 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC1 +control: pid +# NOTE: These settings are for PETG, thus 240C at 30% fan. +pid_Kp: 26.27 +pid_Ki: 1.607 +pid_Kd: 107.380 +min_temp: 0 +max_temp: 260 +max_extrude_only_distance: 100 + +[heater_bed] +heater_pin: PA5 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC0 +control: pid +# NOTE: These settings are for PETG, thus 80C bed temperature. +pid_Kp: 70.173 +pid_Ki: 1.418 +pid_Kd: 868.388 +min_temp: 0 +max_temp: 100 + +# Coooling + +[fan] +pin: PA7 + +[heater_fan hotend_fan] +pin: PB0 + +# Rest + +# This is put on the FAN3 pin. +[led top_LEDs] +white_pin: PB9 +cycle_time: 0.005 + +[filament_switch_sensor filament_runout_sensor] +switch_pin: PB4 + +[safe_z_home] +home_xy_position: 143.5, 93 + +[bed_mesh] +mesh_min: 10, 25 +mesh_max: 205, 220 +probe_count: 6, 6 +algorithm: bicubic +speed: 100 diff --git a/config/printer-kingroon-kp3s-2020.cfg b/config/printer-kingroon-kp3s-2020.cfg new file mode 100644 index 000000000000..99dd2f87688a --- /dev/null +++ b/config/printer-kingroon-kp3s-2020.cfg @@ -0,0 +1,108 @@ +# This file contains common pin mappings for the Kingroon KP3S printer, +# which uses a modified MKS Robin board. +# To use this config, the firmware should be compiled for the +# STM32F103. When running "make menuconfig", enable "extra low-level +# configuration setup", select the 28KiB bootloader, and serial (on +# USART3 PB11/PB10) communication. Also, select "Enable extra low-level +# configuration options" and configure "GPIO pins to set at +# micro-controller startup" to "!PC6,!PD13" to disable the LCD as it is not +# compatible with klipper + +# Note that the "make flash" command does not work with MKS Robin +# boards. After running "make", run the following command: +# ./scripts/update_mks_robin.py out/klipper.bin out/Robin_nano.bin +# Copy the file out/Robin_nano.bin to an SD card and then restart the +# printer with that SD card. + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PE3 +dir_pin: !PE2 +enable_pin: !PE4 +microsteps: 32 +rotation_distance: 40 +endstop_pin: !PA15 +position_endstop: 0 +position_max: 180 +homing_speed: 50 + +[stepper_y] +step_pin: PE0 +dir_pin: !PB9 +enable_pin: !PE1 +microsteps: 32 +rotation_distance: 40 +endstop_pin: !PA12 +position_endstop: 0 +position_max: 180 +homing_speed: 50 + +[stepper_z] +step_pin: PB5 +dir_pin: PB4 +enable_pin: !PB8 +microsteps: 32 +rotation_distance: 8 +endstop_pin: !PA11 +position_endstop: 0.5 +position_max: 180 + +[safe_z_home] +home_xy_position: 90,90 +z_hop: 10 + +[thermistor Kingroon_B3950] +temperature1: 25.0 +resistance1: 103180.0 +temperature2: 150.0 +resistance2: 1366.2 +temperature3: 250.0 +resistance3: 168.6 + +[extruder] +step_pin: PD6 +dir_pin: !PD3 +enable_pin: !PB3 +microsteps: 32 +gear_ratio: 3:1 +rotation_distance: 23.244 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PC3 +sensor_type: Kingroon_B3950 +sensor_pin: PC1 +control: pid +pid_kp: 27.057 +pid_ki: 1.171 +pid_kd: 156.254 +min_temp: 0 +max_temp: 250 + +[heater_bed] +heater_pin: PA0 +sensor_type: Kingroon_B3950 +sensor_pin: PC0 +control: pid +pid_kp: 61.779 +pid_ki: 1.572 +pid_kd: 606.980 +min_temp: 0 +max_temp: 130 + +[fan] +pin: PB1 + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 250 +max_accel: 2000 +max_z_velocity: 25 +max_z_accel: 100 + +[static_digital_output display_reset] +pins: !PC6, !PD13 diff --git a/config/printer-lulzbot-mini2-2018.cfg b/config/printer-lulzbot-mini2-2018.cfg new file mode 100644 index 000000000000..df6e91428ed8 --- /dev/null +++ b/config/printer-lulzbot-mini2-2018.cfg @@ -0,0 +1,157 @@ +#This file contains pin mappings for the stock Lulzbot Mini 2 which uses +#EinsyRetro mainboard and SingleExtruder(0.5mm) hotend. +#To use this config, the firmware should be compiled for the AVR atmega2560. + +# Pin numbers checked against Lulzbot fork of Marlin pins_EINSYRETRO.h +# https://gitlab.com/lulzbot3d/marlin/-/blob/master/Marlin/src/pins/rambo/ +#pins_EINSY_RETRO.h +# validated against https://github.com/ultimachine/EinsyRetro/blob/1.0b/board/ +#Project%20Outputs%20for%20EinsyRetro/Schematic%20Prints_EinsyRetro_1.0b.PDF + +# See docs/Config_Reference.md for a description of parameters. + +[mcu] +serial: /dev/ttyACM0 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 2000 +max_z_velocity: 40 +max_z_accel: 100 + +[stepper_x] +step_pin: PC0 +dir_pin: !PL0 +enable_pin: !PA7 +rotation_distance: 32 +microsteps: 16 +endstop_pin: tmc2130_stepper_x:virtual_endstop +position_endstop: -7 +position_min: -7 +position_max: 168 +homing_retract_dist: 0 +homing_speed: 30 + +[stepper_y] +step_pin: PC1 +dir_pin: !PL1 +enable_pin: !PA6 +rotation_distance: 32 +microsteps: 16 +endstop_pin: tmc2130_stepper_y:virtual_endstop +position_endstop: -5 +position_min: -5 +position_max: 192 +homing_retract_dist: 0 +homing_speed: 30 + +[stepper_z] +step_pin: PC2 +dir_pin: !PL2 +enable_pin: !PA5 +rotation_distance: 32 +microsteps: 16 +endstop_pin: PH4 +position_endstop: 183 +position_max: 185 +position_min: -2 + +[extruder] +step_pin: PC3 +dir_pin: PL6 +enable_pin: !PA4 +microsteps: 16 +rotation_distance: 7.465 +nozzle_diameter: 0.5 +filament_diameter: 2.85 +heater_pin: PE5 +sensor_type: ATC Semitec 104GT-2 +sensor_pin: PF0 +min_temp: 0 +max_temp: 280 +control: pid +pid_kp: 24.121 +pid_ki: 1.079 +pid_kd: 134.779 + +[heater_bed] +heater_pin: PG5 +sensor_type: Honeywell 100K 135-104LAG-J01 +sensor_pin: PF2 +min_temp: 0 +max_temp: 130 +control: pid +pid_kp: 71.304 +pid_ki: 1.662 +pid_kd: 764.734 + +[fan] +pin: PH5 + +[heater_fan nozzle_cooling_fan] +pin: PH3 + +[probe] +pin: ^!PB4 +z_offset: 1.377 +#z offset will need to be adjusted if you use the magnetic bed upgrade as the +#washer thickness will apply a different offset between the nozzle and true +#bed level. +samples: 3 +sample_retract_dist: 1.0 +samples_tolerance: 0.200 + +[bed_tilt] +points: -5, 22 + -5, 190 + 160, 190 + 160, 22 +speed: 30 +horizontal_move_z: 5 + +[tmc2130 stepper_x] +cs_pin: PG0 +run_current: 0.975 +diag0_pin: ^!PK2 +driver_SGT: 4 +sense_resistor: 0.120 + +[tmc2130 stepper_y] +cs_pin: PG2 +run_current: 0.975 +diag0_pin: ^!PK7 +driver_SGT: 4 +sense_resistor: 0.120 + +[tmc2130 stepper_z] +cs_pin: PK5 +run_current: 0.960 +diag0_pin: ^!PK6 +stealthchop_threshold: 999999 +sense_resistor: 0.120 + +[tmc2130 extruder] +cs_pin: PK4 +run_current: 0.960 +diag0_pin: ^!PK3 +stealthchop_threshold: 999999 +sense_resistor: 0.120 + +[static_digital_output sd_card] +pins: PB0 + +[safe_z_home] +home_xy_position: 75, 75 +speed: 30.0 +z_hop: 5 + +[display] +lcd_type: st7920 +cs_pin: PD5 +sclk_pin: PD2 +sid_pin: PD3 +menu_timeout: 5 +encoder_pins: ^PJ1,^PJ2 +encoder_steps_per_detent: 2 +click_pin: ^!PH6 diff --git a/config/printer-ratrig-v-minion-2021.cfg b/config/printer-ratrig-v-minion-2021.cfg new file mode 100644 index 000000000000..d50d6462f9fc --- /dev/null +++ b/config/printer-ratrig-v-minion-2021.cfg @@ -0,0 +1,180 @@ +# This file contains pin mappings for a full Ratrig V-Minion kit +# with an Octopus Pro v1.1 board. +# +# This will not work with RatOS +# +# To use this config, during "make menuconfig" select the STM32F446 +# with a "32KiB bootloader", USB (on PA11/PA12) communication, and +# a "12MHZ Crystal" +# +# Flash this firmware on the MCU by copying "out/klipper.bin" to an SD +# card and turning the printer on with the card inserted. The firmware +# filename must be named "firmware.bin" +# +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PF13 +dir_pin: !PF12 +enable_pin: !PF14 +endstop_pin: ^PG6 +rotation_distance: 40 +microsteps: 64 +position_max: 180 +position_min: 0 +homing_speed: 60 +position_endstop: 0 + +[tmc2209 stepper_x] +uart_pin: PC4 +run_current: 0.8 +interpolate: false +stealthchop_threshold: 0 + +[stepper_y] +step_pin: PG0 +dir_pin: PG1 +enable_pin: !PF15 +endstop_pin: ^PG9 +rotation_distance: 40 +microsteps: 64 +position_max: 180 +position_min: 0 +homing_speed: 60 +position_endstop: 0 + +[tmc2209 stepper_y] +uart_pin: PD11 +run_current: 0.8 +interpolate: false +stealthchop_threshold: 0 + +[stepper_z] +step_pin: PC13 +dir_pin: !PF0 +enable_pin: !PF1 +endstop_pin: probe:z_virtual_endstop +rotation_distance: 4 +position_min: -5 +microsteps: 64 +position_max: 180 + +[tmc2209 stepper_z] +uart_pin: PE4 +run_current: 0.8 +interpolate: false +stealthchop_threshold: 0 + +[extruder] +rotation_distance: 5.57 +full_steps_per_rotation: 200 +filament_diameter: 1.750 +step_pin: PF11 +dir_pin: !PG3 +enable_pin: !PG5 +microsteps: 64 +nozzle_diameter: 0.4 +heater_pin: PA2 +sensor_type: Generic 3950 +sensor_pin: PF4 +control: pid +pid_Kp: 22.2 +pid_Ki: 1.08 +pid_Kd: 114 + +min_temp: 0 +max_temp: 290 + +[tmc2209 extruder] +uart_pin: PC6 +run_current: 0.70 +stealthchop_threshold: 0 +interpolate: False + +[probe] +pin: ^PB7 +x_offset: -24.0 +y_offset: -13.0 +z_offset: 0.0 +speed: 5 +samples: 2 +sample_retract_dist: 2 +lift_speed: 5.0 +samples_result: median +samples_tolerance: 0.02 +samples_tolerance_retries: 5 + +[bed_mesh] +speed: 300 +horizontal_move_z: 5 +mesh_min: 15,15 +mesh_max: 150,160 +probe_count: 5,5 +fade_start: 1.0 +fade_end: 10.0 +mesh_pps: 2,2 +algorithm: bicubic +bicubic_tension: .2 + +[screws_tilt_adjust] +screw1: 80, 108 +screw1_name: Left Screw +screw2: 155, 72 +screw2_name: Front Right Screw +screw3: 155, 147 +screw3_name: Rear Right Screw +horizontal_move_z: 10 +speed: 300 +screw_thread: CCW-M4 + +[safe_z_home] +home_xy_position: 90,90 +z_hop: 5 +speed: 300 + +[heater_bed] +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PF3 +control: pid +pid_kp: 54.027 +pid_ki: 0.770 +pid_kd: 948.182 +min_temp: 0 +max_temp: 120 + +[fan] +pin: PA8 +shutdown_speed: 0.0 + +[heater_fan hotend_cooling_fan] +pin: PE5 +fan_speed: 1.0 +heater: extruder +heater_temp: 50.0 + +[controller_fan controller_fan] +pin: PD12 +fan_speed: 1.0 +stepper: stepper_x, stepper_y, stepper_z + +[printer] +kinematics: cartesian +max_velocity: 500 +max_accel: 20000 +max_z_velocity: 15 +max_z_accel: 2000 + +[mcu] +serial: INSERTSERIALIDHERE + +[board_pins octopus_11_tmc2209] +aliases: +## Expansion ports + # EXP1 header + EXP1_1=PE8, EXP1_3=PE9, EXP1_5=PE12, EXP1_7=PE14, EXP1_9=, + EXP1_2=PE7, EXP1_4=PE10, EXP1_6=PE13, EXP1_8=PE15, EXP1_10=<5V>, + # EXP2 header + EXP2_1=PA6, EXP2_3=PB1, EXP2_5=PB2, EXP2_7=PC15, EXP2_9=, + EXP2_2=PA5, EXP2_4=PA4, EXP2_6=PA7, EXP2_8=, EXP2_10=PC5, + # Pins EXP2_1, EXP2_6, EXP2_2 are also MISO, MOSI, SCK of bus "spi2" diff --git a/config/printer-sovol-sv05-2022.cfg b/config/printer-sovol-sv05-2022.cfg new file mode 100644 index 000000000000..dafc6f3cf322 --- /dev/null +++ b/config/printer-sovol-sv05-2022.cfg @@ -0,0 +1,144 @@ +# This file contains pin mappings for the stock 2022 Sovol SV05 +# with the 32-bit Creality 4.2.2 board. +# +# To use this config, during "make menuconfig" select the STM32F103 +# with a "28KiB bootloader" and serial (on USART1 PA10/PA9) +# communication. +# +# Flash this firmware by copying "out/klipper.bin" to a SD card and +# turning on the printer with the card inserted. The firmware +# filename must end in ".bin" and must not match the last filename +# that was flashed. Might need a renaming if printer dosnt flash. + +# See docs/Config_Reference.md for a description of parameters. +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 1000 +max_accel_to_decel: 1000 +max_z_velocity: 5 +max_z_accel: 100 + +[stepper_x] +step_pin: PC2 +dir_pin: PB9 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PA5 +position_endstop: 220 +position_max: 220 +homing_speed: 50 +position_min: -4 + +[stepper_y] +step_pin: PB8 +dir_pin: PB7 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PA6 +position_endstop: 220 +position_max: 220 +position_min: -4 +homing_speed: 50 + +[stepper_z] +step_pin: PB6 +dir_pin: PB5 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 8 +endstop_pin: probe:z_virtual_endstop +position_max: 300 +position_min: -3 + +[heater_bed] +heater_pin: PA2 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC4 +min_temp: 0 +max_temp: 130 +control: pid +pid_kp: 64.742 +pid_ki: 0.827 +pid_kd: 1267.326 + +[fan] +pin: PA0 + +[safe_z_home] +home_xy_position: 70, 103 +speed: 100 +z_hop: 10 +z_hop_speed: 20 + +[extruder] +step_pin: PB4 +dir_pin: PB3 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 7.394 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +max_extrude_only_distance: 100.0 +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC5 +min_temp: 0 +max_temp: 280 +control: pid +pid_kp: 28.850 +pid_ki: 1.658 +pid_kd: 125.496 + +[bltouch] +sensor_pin: ^PB1 +control_pin: PB0 +z_offset: 0 +x_offset: 40 +y_offset: 7 +samples: 2 +samples_tolerance: 0.015 +samples_tolerance_retries: 5 + +[bed_mesh] +speed: 100 +horizontal_move_z: 5 +mesh_min: 40, 7 +mesh_max: 220, 220 +probe_count: 5, 5 +algorithm: bicubic +fade_start: 1 +fade_end: 10 + +[bed_screws] +screw1: 25,28 +screw2: 195,28 +screw3: 195,197 +screw4: 25,197 + +[screws_tilt_adjust] +screw1: -4,21 +screw1_name: front left screw +screw2: 155,21 +screw2_name: front right screw +screw3: 155,190 +screw3_name: rear right screw +screw4: -4,190 +screw4_name: rear left screw +horizontal_move_z: 10 +speed: 50 +screw_thread: CW-M4 + +[display] +lcd_type: st7920 +cs_pin: PB12 +sclk_pin: PB13 +sid_pin: PB15 +encoder_pins: ^PB14, ^PB10 +click_pin: ^!PB2 diff --git a/config/printer-sovol-sv06-2022.cfg b/config/printer-sovol-sv06-2022.cfg new file mode 100644 index 000000000000..78a627c7ddca --- /dev/null +++ b/config/printer-sovol-sv06-2022.cfg @@ -0,0 +1,159 @@ +# This file contains pin mappings for the stock Sovol SV06 +# To use this config, during "make menuconfig" select the +# STM32F103 with a "28KiB bootloader" and serial (on USART1 PA10/PA9) communication. +# Also, since it is using the GD32F103, please select Disable SWD at startup +# +# Flash this firmware by copying "out/klipper.bin" to a SD card and +# turning on the printer with the card inserted. The firmware +# filename must end in ".bin" and must not match the last filename +# that was flashed. +# +# See docs/Config_Reference.md for a description of parameters. +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB2.0-Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +[stepper_x] +step_pin: PC2 +dir_pin: !PB9 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: tmc2209_stepper_x:virtual_endstop +position_endstop: 0 +position_max: 225 +homing_speed: 40 +homing_retract_dist: 0 + +[tmc2209 stepper_x] +uart_pin: PC1 +run_current: 0.860 +stealthchop_threshold: 0 +interpolate: False +sense_resistor: 0.150 +uart_address: 3 +driver_SGTHRS: 81 +diag_pin: PA5 + +[stepper_y] +step_pin: PB8 +dir_pin: PB7 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: tmc2209_stepper_y:virtual_endstop +position_endstop: 0 +position_max: 225 +homing_speed: 40 +homing_retract_dist: 0 + +[tmc2209 stepper_y] +uart_pin: PC0 +run_current: 0.900 +stealthchop_threshold: 0 +interpolate: False +sense_resistor: 0.150 +uart_address: 3 +driver_SGTHRS: 82 +diag_pin: PA6 + +[stepper_z] +step_pin: PB6 +dir_pin: !PB5 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 4 +endstop_pin: probe:z_virtual_endstop +position_min: -4 +position_max: 261 +homing_speed: 4 + +[tmc2209 stepper_z] +uart_pin: PA15 +run_current: 1.000 +stealthchop_threshold: 0 +interpolate: False +sense_resistor: 0.150 +uart_address: 3 +diag_pin: PA7 + +[extruder] +max_extrude_only_distance: 100.0 +step_pin: PB4 +dir_pin: !PB3 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 4.56 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC5 +control: pid +pid_kd: 86.991 +pid_kp: 21.479 +pid_ki: 1.326 +min_temp: 0 +max_temp: 300 + +[tmc2209 extruder] +uart_pin: PC14 +run_current: 0.550 +stealthchop_threshold: 0 +interpolate: False +sense_resistor: 0.150 +uart_address: 3 + +[heater_bed] +heater_pin: PA2 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC4 +control: pid +pid_kp: 64.440 +pid_ki: 0.773 +pid_kd: 1343.571 +min_temp: 0 +max_temp: 130 + +[fan] +pin: PA0 + +[probe] +pin: PB1 +x_offset: 28 +y_offset: -20 +z_offset: 0 +samples: 2 +samples_tolerance: 0.015 +samples_tolerance_retries: 5 + +[safe_z_home] +home_xy_position: 85,135 +z_hop: 10 +z_hop_speed: 5 + +[bed_mesh] +speed: 120 +horizontal_move_z: 5 +mesh_min: 28, 20 +mesh_max: 210, 205 +probe_count: 10 +algorithm: bicubic +fade_start: 1 +fade_end: 10 +fade_target: 0 + +[display] +lcd_type: st7920 +cs_pin: PB12 +sclk_pin: PB13 +sid_pin: PB15 +encoder_pins: ^PB14, ^PB10 +click_pin: ^!PB2 diff --git a/config/printer-sunlu-t3-2022.cfg b/config/printer-sunlu-t3-2022.cfg new file mode 100644 index 000000000000..f9bf26246e0f --- /dev/null +++ b/config/printer-sunlu-t3-2022.cfg @@ -0,0 +1,198 @@ +# This file contains common pin mappings for the SUNLU Terminator T3 board + +# To use this config, the firmware should be compiled for the +# STM32F103 with a "28KiB bootloader" and USB communication. +# Select "Disable SWD at startup (for GigaDevice stmf32f103 clones)" +# Also, select "Enable extra low-level configuration options" and configure +# "GPIO pins to set at micro-controller startup" to "!PA14". + +# The "make flash" command does not work on the SUNLU Terminator T3 board. Instead, +# after running "make", copy the generated "out/klipper.bin" file to a +# file named "firmware.bin" on an SD card and then restart the board with that SD card. + +# See docs/Config_Reference.md for a description of parameters. + +# Rename the file to printer.cfg + +################################################################## +# Printer +################################################################## + +[mcu] +#obtain your MCU id using ls /dev/serial/by-path/* +serial: dev/serial/by-id/usb-Klipper_stm32f103xe_00000000000 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 + +[static_digital_output usb_pullup_enable] +pins: !PA14 + +[bltouch] +sensor_pin: PC14 +control_pin: PA1 +x_offset: -28.45 +y_offset: 4 +z_offset: 1.915 +pin_up_touch_mode_reports_triggered: FALSE #needed bc of the bltouch clone used by sunlu + +[safe_z_home] +home_xy_position: 115,115 +speed: 75 +z_hop: 10 +z_hop_speed: 5 + +[bed_mesh] +speed: 120 +horizontal_move_z: 5 +mesh_min: 10, 10 +mesh_max: 190, 220 +probe_count: 5,5 +fade_start: 1 +fade_end: 10 + +[bed_screws] +#for BED_SCREWS_ADJUST +screw1: 31,38 #X,Y Position +screw1_name: Front Left +screw2: 201,38 #X,Y Position +screw2_name: Front Right +screw3: 201,204 #X,Y Position +screw3_name: Rear Right +screw4: 31,204 #X,Y Position +screw4_name: Rear Left + +##IMPORTANT. If using the filament sensor add CLEAR_PAUSE to your slicer's start gcode or to your print start macro.## +##The act of loading and unloading filament will trigger a paused state## +[filament_motion_sensor Filament_Sensor] +detection_length: 7.0 +extruder: extruder +switch_pin: !PC15 +pause_on_runout: FALSE +runout_gcode: PAUSE + +######################################################### +# Motion Axis +######################################################### + +[stepper_x] +step_pin: PB13 +dir_pin: !PB12 +enable_pin: !PB14 +microsteps: 16 +rotation_distance: 40 +endstop_pin: !PC0 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_y] +step_pin: PB10 +dir_pin: !PB2 +enable_pin: !PB11 +microsteps: 16 +rotation_distance: 40 +endstop_pin: !PC1 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_z] +step_pin: PB0 +dir_pin: PC5 +enable_pin: !PB1 +microsteps: 16 +rotation_distance: 4 +position_max: 250 +endstop_pin: probe:z_virtual_endstop + +################################################### +# Heaters +################################################### + +[extruder] +step_pin: PB3 +dir_pin: !PB4 +enable_pin: !PD2 +microsteps: 16 +rotation_distance: 23.18840579710145 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PC8 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PA0 +control: pid +pid_Kp: 19.479 +pid_Ki: 1.073 +pid_Kd: 88.385 +min_temp: 0 +max_temp: 250 + +[heater_bed] +heater_pin: PC9 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC3 +control: pid +pid_Kp: 62.673 +pid_Ki: 1.530 +pid_Kd: 641.619 +min_temp: 0 +max_temp: 130 + +######################################### +# Fans +######################################### + +[heater_fan Hotend] +pin: PC7 +heater: extruder +heater_temp: 50.0 + +[fan] +pin: PC6 + +############################################### +# Stock Screen +############################################### + +[board_pins] +aliases: + # EXP1 header + EXP1_1=PB5, EXP1_3=PA9, EXP1_5=PA10, EXP1_7=PB8, EXP1_9=, + EXP1_2=PA15, EXP1_4=, EXP1_6=PB9, EXP1_8=PB15, EXP1_10=<5V> + +[display] +lcd_type: st7920 +cs_pin: PB8 #EXP1_7 +sclk_pin: PB9 #EXP1_6 +sid_pin: PB15 #EXP1_8 +encoder_pins: ^PA10, ^PA9 #^EXP1_5, ^EXP1_3 +click_pin: ^!PA15 #^!EXP1_2 + +[output_pin beeper] +pin: PB5 #EXP1_1 +pwm: True +value: 0 +shutdown_value: 0 +cycle_time: 0.001 +scale: 1 +[gcode_macro M300] +gcode: + {% set S = params.S|default(1000)|int %} ; S sets the tone frequency + {% set P = params.P|default(100)|int %} ; P sets the tone duration + {% set L = 0.5 %} ; L varies the PWM on time, close to 0 or 1 the tone gets a bit quieter. 0.5 is a symmetric waveform + {% if S <= 0 %} ; dont divide through zero + {% set F = 1 %} + {% set L = 0 %} + {% elif S >= 10000 %} ;max frequency set to 10kHz + {% set F = 0 %} + {% else %} + {% set F = 1/S %} ;convert frequency to seconds + {% endif %} + SET_PIN PIN=beeper VALUE={L} CYCLE_TIME={F} ;Play tone + G4 P{P} ;tone duration + SET_PIN PIN=beeper VALUE=0 diff --git a/config/printer-voxelab-aquila-2021.cfg b/config/printer-voxelab-aquila-2021.cfg new file mode 100644 index 000000000000..a23d00c6f01a --- /dev/null +++ b/config/printer-voxelab-aquila-2021.cfg @@ -0,0 +1,84 @@ +# This file contains pin mappings for the Voxelab Aquila +# with the FFP0173 1.0.1 mainboard. To use this config, during +# "make menuconfig" select the STM32F103 for STM32/G32, or +# Nation N32G452 for N32 version, 28KB boot, serial PA9/PA10. + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PC2 +dir_pin: PB9 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PA5 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_y] +step_pin: PB8 +dir_pin: PB7 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: ^PA6 +position_endstop: 0 +position_max: 235 +homing_speed: 50 + +[stepper_z] +step_pin: PB6 +dir_pin: !PB5 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 8 +endstop_pin: ^PA7 +position_endstop: 0.0 +position_max: 250 + +[extruder] +max_extrude_only_distance: 100.0 +step_pin: PB4 +dir_pin: PB3 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 34.406 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC5 +control: pid +# tuned for stock hardware with 200 degree Celsius target +pid_Kp: 21.527 +pid_Ki: 1.063 +pid_Kd: 108.982 +min_temp: 0 +max_temp: 250 + +[heater_bed] +heater_pin: PA2 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC4 +control: pid +# tuned for stock hardware with 50 degree Celsius target +pid_Kp: 54.027 +pid_Ki: 0.770 +pid_Kd: 948.182 +min_temp: 0 +max_temp: 130 + +[fan] +pin: PA0 + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 5 +max_z_accel: 100 diff --git a/config/sample-bigtreetech-ebb-canbus-v1.0.cfg b/config/sample-bigtreetech-ebb-canbus-v1.0.cfg index 3771b9847483..3909784123e9 100644 --- a/config/sample-bigtreetech-ebb-canbus-v1.0.cfg +++ b/config/sample-bigtreetech-ebb-canbus-v1.0.cfg @@ -10,21 +10,21 @@ serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 #canbus_uuid: 0e0d81e4210c [adxl345] -cs_pin: EBBCan: PB12 +cs_pin: EBBCan:PB12 spi_bus: spi2 axes_map: x,y,z [extruder] -step_pin: EBBCan: PA9 -dir_pin: !EBBCan: PA8 -enable_pin: !EBBCan: PA10 +step_pin: EBBCan:PA9 +dir_pin: !EBBCan:PA8 +enable_pin: !EBBCan:PA10 microsteps: 16 rotation_distance: 33.500 nozzle_diameter: 0.400 filament_diameter: 1.750 -heater_pin: EBBCan: PB1 +heater_pin: EBBCan:PB1 sensor_type: EPCOS 100K B57560G104F -sensor_pin: EBBCan: PA0 +sensor_pin: EBBCan:PA0 control: pid pid_Kp: 21.527 pid_Ki: 1.063 @@ -33,22 +33,22 @@ min_temp: 0 max_temp: 250 #sensor_type:MAX31865 -#sensor_pin: EBBCan: PA15 +#sensor_pin: EBBCan:PA15 #spi_bus: spi1a #rtd_nominal_r: 100 #rtd_reference_r: 430 #rtd_num_of_wires: 2 [tmc2209 extruder] -uart_pin: EBBCan: PA13 +uart_pin: EBBCan:PA13 run_current: 0.650 stealthchop_threshold: 999999 [fan] -pin: EBBCan: PA1 +pin: EBBCan:PA1 [heater_fan hotend_fan] -pin: EBBCan: PA2 +pin: EBBCan:PA2 heater: extruder heater_temp: 50.0 diff --git a/config/sample-bigtreetech-ebb-canbus-v1.1.cfg b/config/sample-bigtreetech-ebb-canbus-v1.1.cfg index d71655414df9..c84abf17328b 100644 --- a/config/sample-bigtreetech-ebb-canbus-v1.1.cfg +++ b/config/sample-bigtreetech-ebb-canbus-v1.1.cfg @@ -10,23 +10,23 @@ serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 #canbus_uuid: 0e0d81e4210c [adxl345] -cs_pin: EBBCan: PB12 -spi_software_sclk_pin: EBBCan: PB10 -spi_software_mosi_pin: EBBCan: PB11 -spi_software_miso_pin: EBBCan: PB2 +cs_pin: EBBCan:PB12 +spi_software_sclk_pin: EBBCan:PB10 +spi_software_mosi_pin: EBBCan:PB11 +spi_software_miso_pin: EBBCan:PB2 axes_map: x,y,z [extruder] -step_pin: EBBCan: PD0 -dir_pin: !EBBCan: PD1 -enable_pin: !EBBCan: PD2 +step_pin: EBBCan:PD0 +dir_pin: !EBBCan:PD1 +enable_pin: !EBBCan:PD2 microsteps: 16 rotation_distance: 33.500 nozzle_diameter: 0.400 filament_diameter: 1.750 -heater_pin: EBBCan: PA2 +heater_pin: EBBCan:PA2 sensor_type: EPCOS 100K B57560G104F -sensor_pin: EBBCan: PA3 +sensor_pin: EBBCan:PA3 control: pid pid_Kp: 21.527 pid_Ki: 1.063 @@ -35,22 +35,22 @@ min_temp: 0 max_temp: 250 # sensor_type:MAX31865 -# sensor_pin: EBBCan: PA4 +# sensor_pin: EBBCan:PA4 # spi_bus: spi1 # rtd_nominal_r: 100 # rtd_reference_r: 430 # rtd_num_of_wires: 2 [tmc2209 extruder] -uart_pin: EBBCan: PA15 +uart_pin: EBBCan:PA15 run_current: 0.650 stealthchop_threshold: 999999 [fan] -pin: EBBCan: PA0 +pin: EBBCan:PA0 [heater_fan hotend_fan] -pin: EBBCan: PA1 +pin: EBBCan:PA1 heater: extruder heater_temp: 50.0 diff --git a/config/sample-bigtreetech-ebb-canbus-v1.2.cfg b/config/sample-bigtreetech-ebb-canbus-v1.2.cfg new file mode 100644 index 000000000000..053b783c389c --- /dev/null +++ b/config/sample-bigtreetech-ebb-canbus-v1.2.cfg @@ -0,0 +1,68 @@ +# This file contains common pin mappings for the BIGTREETECH EBBCan +# Canbus board. To use this config, the firmware should be compiled for the +# STM32G0B1 with "8 MHz crystal" and "USB (on PA11/PA12)" or "CAN bus (on PB0/PB1)". +# The "EBB Can" micro-controller will be used to control the components on the nozzle. + +# See docs/Config_Reference.md for a description of parameters. + +[mcu EBBCan] +serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 +#canbus_uuid: 0e0d81e4210c + +[adxl345] +cs_pin: EBBCan:PB12 +spi_software_sclk_pin: EBBCan:PB10 +spi_software_mosi_pin: EBBCan:PB11 +spi_software_miso_pin: EBBCan:PB2 +axes_map: x,y,z + +[extruder] +step_pin: EBBCan:PD0 +dir_pin: !EBBCan:PD1 +enable_pin: !EBBCan:PD2 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: EBBCan:PB13 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: EBBCan:PA3 +control: pid +pid_Kp: 21.527 +pid_Ki: 1.063 +pid_Kd: 108.982 +min_temp: 0 +max_temp: 250 + +# sensor_type:MAX31865 +# sensor_pin: EBBCan:PA4 +# spi_bus: spi1 +# rtd_nominal_r: 100 +# rtd_reference_r: 430 +# rtd_num_of_wires: 2 + +[tmc2209 extruder] +uart_pin: EBBCan:PA15 +run_current: 0.650 +stealthchop_threshold: 999999 + +[fan] +pin: EBBCan:PA0 + +[heater_fan hotend_fan] +pin: EBBCan:PA1 +heater: extruder +heater_temp: 50.0 + +#[neopixel hotend_rgb] +#pin: EBBCan:PD3 + +#[bltouch] +#sensor_pin: ^EBBCan:PB8 +#control_pin: EBBCan:PB9 + +#[filament_switch_sensor switch_sensor] +#switch_pin: EBBCan:PB4 + +#[filament_motion_sensor motion_sensor] +#switch_pin: ^EBBCan:PB3 diff --git a/config/sample-bigtreetech-ebb-sb-canbus-v1.0.cfg b/config/sample-bigtreetech-ebb-sb-canbus-v1.0.cfg new file mode 100644 index 000000000000..192d385e5d09 --- /dev/null +++ b/config/sample-bigtreetech-ebb-sb-canbus-v1.0.cfg @@ -0,0 +1,84 @@ +# This file contains common pin mappings for the BIGTREETECH EBBCan +# Canbus board. To use this config, the firmware should be compiled for the +# STM32G0B1 with "8 MHz crystal" and "USB (on PA11/PA12)" or "CAN bus (on PB0/PB1)". +# The "EBB Can" micro-controller will be used to control the components on the nozzle. + +# See docs/Config_Reference.md for a description of parameters. + +[mcu EBBCan] +serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 +#canbus_uuid: 0e0d81e4210c + +[temperature_sensor EBB_NTC] +sensor_type: Generic 3950 +sensor_pin: EBBCan:PA2 + +[adxl345] +cs_pin: EBBCan:PB12 +spi_software_sclk_pin: EBBCan:PB10 +spi_software_mosi_pin: EBBCan:PB11 +spi_software_miso_pin: EBBCan:PB2 +axes_map: x,y,z + +[extruder] +step_pin: EBBCan:PD0 +dir_pin: !EBBCan:PD1 +enable_pin: !EBBCan:PD2 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: EBBCan:PB13 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: EBBCan:PA3 +control: pid +pid_Kp: 21.527 +pid_Ki: 1.063 +pid_Kd: 108.982 +min_temp: 0 +max_temp: 250 + +# sensor_type:MAX31865 +# sensor_pin: EBBCan:PA4 +# spi_bus: spi1 +# rtd_nominal_r: 100 +# rtd_reference_r: 430 +# rtd_num_of_wires: 2 + +[tmc2209 extruder] +uart_pin: EBBCan:PA15 +run_current: 0.650 +stealthchop_threshold: 999999 + +[fan] +pin: EBBCan:PA0 + +[heater_fan hotend_fan] +pin: EBBCan:PA1 +heater: extruder +heater_temp: 50.0 + +#[heater_fan 4W_FAN0] +#pin: EBBCan:PB14 +#tachometer_pin: EBBCan:PB15 +#tachometer_ppr: 1 + +#[neopixel hotend_rgb] +#pin: EBBCan:PD3 + +#[bltouch] +#sensor_pin: ^EBBCan:PB8 +#control_pin: EBBCan:PB9 + +## NPN and PNP proximity switch types can be set by jumper +#[probe] +#pin: ^EBBCan:PC13 + +#[output_pin PB5] +#pin: EBBCan:PB5 + +#[output_pin PB7] +#pin: EBBCan:PB7 + +#[output_pin PB6] +#pin: EBBCan:PB6 diff --git a/config/sample-bigtreetech-hermit-crab-canbus.cfg b/config/sample-bigtreetech-hermit-crab-canbus.cfg index ce3b3045859f..beec65b167b1 100644 --- a/config/sample-bigtreetech-hermit-crab-canbus.cfg +++ b/config/sample-bigtreetech-hermit-crab-canbus.cfg @@ -10,21 +10,21 @@ serial: /dev/serial/by-id/usb-Klipper_Klipper_firmware_12345-if00 #canbus_uuid: 0e0d81e4210c [adxl345] -cs_pin: HermitCrab: PB12 +cs_pin: HermitCrab:PB12 spi_bus: spi2 axes_map: y,z,-x [extruder] -step_pin: HermitCrab: PA6 -dir_pin: !HermitCrab: PA7 -enable_pin: !HermitCrab: PA5 +step_pin: HermitCrab:PA6 +dir_pin: !HermitCrab:PA7 +enable_pin: !HermitCrab:PA5 microsteps: 16 rotation_distance: 33.500 nozzle_diameter: 0.400 filament_diameter: 1.750 -heater_pin: HermitCrab: PA2 +heater_pin: HermitCrab:PA2 sensor_type: EPCOS 100K B57560G104F -sensor_pin: HermitCrab: PA1 +sensor_pin: HermitCrab:PA1 control: pid pid_Kp: 21.527 pid_Ki: 1.063 @@ -33,15 +33,15 @@ min_temp: 0 max_temp: 250 [tmc2209 extruder] -uart_pin: HermitCrab: PB0 +uart_pin: HermitCrab:PB0 run_current: 0.650 stealthchop_threshold: 999999 [fan] -pin: HermitCrab: PA4 +pin: HermitCrab:PA4 [heater_fan hotend_fan] -pin: HermitCrab: PA3 +pin: HermitCrab:PA3 heater: extruder heater_temp: 50.0 diff --git a/config/sample-huvud-v0.61.cfg b/config/sample-huvud-v0.61.cfg index ac78318953a6..1a6c0ba07737 100644 --- a/config/sample-huvud-v0.61.cfg +++ b/config/sample-huvud-v0.61.cfg @@ -19,15 +19,15 @@ canbus_uuid: ac20f0bbda05 # ~/klippy-env/bin/python ~/klipper/scripts/canbus_query.py can0 [extruder] -step_pin: huvud: PB3 -dir_pin: huvud: PB4 -enable_pin: !huvud: PB5 +step_pin: huvud:PB3 +dir_pin: huvud:PB4 +enable_pin: !huvud:PB5 rotation_distance: 22.52453125 nozzle_diameter: 0.400 filament_diameter: 1.75 -heater_pin: huvud: PA6 +heater_pin: huvud:PA6 sensor_type: NTC 100K MGB18-104F39050L32 -sensor_pin: huvud: PA0 +sensor_pin: huvud:PA0 pullup_resistor: 2200 min_temp: 0 max_temp: 300 @@ -37,22 +37,22 @@ pid_ki: 1.304 pid_kd: 131.721 [tmc2209 extruder] -uart_pin: huvud: PA10 -tx_pin: huvud: PA9 +uart_pin: huvud:PA10 +tx_pin: huvud:PA9 run_current: 0.35 [probe] -pin: huvud: PB12 +pin: huvud:PB12 z_offset: 0 [fan] -pin: huvud: PA8 +pin: huvud:PA8 [heater_fan extruder_fan] -pin: huvud: PA7 +pin: huvud:PA7 [adxl345] cs_pin: PB1 [led huvud_led] -blue_pin: huvud: PC13 +blue_pin: huvud:PC13 diff --git a/config/sample-macros.cfg b/config/sample-macros.cfg index 7b68f5d04040..5132e1c99c37 100644 --- a/config/sample-macros.cfg +++ b/config/sample-macros.cfg @@ -10,7 +10,7 @@ ###################################################################### # Replace the slicer's custom start and end g-code scripts with -# START_PRINT and END_PRINT. +# START_PRINT and END_PRINT. See docs/Slicers.md for more information on using these macros. [gcode_macro START_PRINT] gcode: diff --git a/docs/Bed_Mesh.md b/docs/Bed_Mesh.md index 34ac276801e3..c45ca2ab2f51 100644 --- a/docs/Bed_Mesh.md +++ b/docs/Bed_Mesh.md @@ -1,8 +1,8 @@ # Bed Mesh -The Bed Mesh module may be used to compensate for bed surface irregularties to -achieve a better first layer across the entire bed. It should be noted that -software based correction will not achieve perfect results, it can only +The Bed Mesh module may be used to compensate for bed surface irregularities +to achieve a better first layer across the entire bed. It should be noted +that software based correction will not achieve perfect results, it can only approximate the shape of the bed. Bed Mesh also cannot compensate for mechanical and electrical issues. If an axis is skewed or a probe is not accurate then the bed_mesh module will not receive accurate results from @@ -46,7 +46,7 @@ probe_count: 5, 3 _Required_\ The probed coordinate farthest farthest from the origin. This is not necessarily the last point probed, as the probing process occurs in a - zig-zag fashion. As with `mesh_min`, this coordiante is relative to + zig-zag fashion. As with `mesh_min`, this coordinate is relative to the probe's location. - `probe_count: 5, 3`\ @@ -101,7 +101,7 @@ round_probe_count: 5 that the center of the mesh is probed. The illustration below shows how the probed points are generated. As you can see, -setting the `mesh_origin` to (-10, 0) allows us to specifiy a larger mesh radius +setting the `mesh_origin` to (-10, 0) allows us to specify a larger mesh radius of 85. ![bedmesh_round_basic](img/bedmesh_round_basic.svg) @@ -114,7 +114,7 @@ Each of the advanced options apply to round beds in the same manner. ### Mesh Interpolation -While its possible to sample the probed matrix directly using simple bilinear +While its possible to sample the probed matrix directly using simple bi-linear interpolation to determine the Z-Values between probed points, it is often useful to interpolate extra points using more advanced interpolation algorithms to increase mesh density. These algorithms add curvature to the mesh, @@ -207,7 +207,7 @@ split_delta_z: .025 Generally the default values for these options are sufficient, in fact the default value of 5mm for the `move_check_distance` may be overkill. However an advanced user may wish to experiment with these options in an effort to squeeze -out the optimial first layer. +out the optimal first layer. ### Mesh Fade @@ -255,17 +255,17 @@ fade_target: 0 example, lets assume your homing position on the bed is an outlier, its .2 mm lower than the average probed height of the bed. If the `fade_target` is 0, fade will shrink the print by an average of .2 mm across the bed. By - setting the `fade_target` to .2, the homed area will expand by .2 mm, however - the rest of the bed will have an accurately sized. Generally its a good idea + setting the `fade_target` to .2, the homed area will expand by .2 mm, however, + the rest of the bed will be accurately sized. Generally its a good idea to leave `fade_target` out of the configuration so the average height of the mesh is used, however it may be desirable to manually adjust the fade target if one wants to print on a specific portion of the bed. ### The Relative Reference Index -Most probes are suceptible to drift, ie: inaccuracies in probing introduced by +Most probes are susceptible to drift, ie: inaccuracies in probing introduced by heat or interference. This can make calculating the probe's z-offset -challenging, particuarly at different bed temperatures. As such, some printers +challenging, particularly at different bed temperatures. As such, some printers use an endstop for homing the Z axis, and a probe for calibrating the mesh. These printers can benefit from configuring the relative reference index. @@ -371,7 +371,7 @@ following parameters are available: - `MESH_ORIGIN` - `ROUND_PROBE_COUNT` - All beds: - - `RELATIVE_REFERNCE_INDEX` + - `RELATIVE_REFERENCE_INDEX` - `ALGORITHM` See the configuration documentation above for details on how each parameter @@ -390,15 +390,33 @@ to write the profile to printer.cfg. Profiles can be loaded by executing `BED_MESH_PROFILE LOAD=`. It should be noted that each time a BED_MESH_CALIBRATE occurs, the current -state is automatically saved to the _default_ profile. If this profile -exists it is automatically loaded when Klipper starts. If this behavior -is not desirable the _default_ profile can be removed as follows: +state is automatically saved to the _default_ profile. The _default_ profile can be removed as follows: `BED_MESH_PROFILE REMOVE=default` Any other saved profile can be removed in the same fashion, replacing _default_ with the named profile you wish to remove. + +#### Loading the default profile + +Previous versions of `bed_mesh` always loaded the profile named _default_ +on startup if it was present. This behavior has been removed in favor of +allowing the user to determine when a profile is loaded. If a user wishes to +load the `default` profile it is recommended to add +`BED_MESH_PROFILE LOAD=default` to either their `START_PRINT` macro or their +slicer's "Start G-Code" configuration, whichever is applicable. + +Alternatively the old behavior of loading a profile at startup can be +restored with a `[delayed_gcode]`: + +```ini +[delayed_gcode bed_mesh_init] +initial_duration: .01 +gcode: + BED_MESH_PROFILE LOAD=default +``` + ### Output `BED_MESH_OUTPUT PGP=[0 | 1]` diff --git a/docs/Benchmarks.md b/docs/Benchmarks.md index f9d0c92bed8b..1256c580119a 100644 --- a/docs/Benchmarks.md +++ b/docs/Benchmarks.md @@ -354,6 +354,27 @@ micro-controller. | 1 stepper (200Mhz) | 39 | | 3 stepper (200Mhz) | 181 | +### AR100 step rate benchmark ### + +The following configuration sequence is used on AR100 CPU (Allwinner A64): +``` +allocate_oids count=3 +config_stepper oid=0 step_pin=PL10 dir_pin=PE14 invert_step=-1 step_pulse_ticks=0 +config_stepper oid=1 step_pin=PL11 dir_pin=PE15 invert_step=-1 step_pulse_ticks=0 +config_stepper oid=2 step_pin=PL12 dir_pin=PE16 invert_step=-1 step_pulse_ticks=0 +finalize_config crc=0 + +``` + +The test was last run on commit `08d037c6` with gcc version +`or1k-linux-musl-gcc (GCC) 9.2.0` on an Allwinner A64-H +micro-controller. + +| AR100 R_PIO | ticks | +| -------------------- | ----- | +| 1 stepper | 85 | +| 3 stepper | 359 | + ### RP2040 step rate benchmark The following configuration sequence is used on the RP2040: @@ -425,6 +446,7 @@ hub. | atmega2560 (serial) | 23K | b161a69e | avr-gcc (GCC) 4.8.1 | | sam3x8e (serial) | 23K | b161a69e | arm-none-eabi-gcc (Fedora 7.1.0-5.fc27) 7.1.0 | | at90usb1286 (USB) | 75K | 01d2183f | avr-gcc (GCC) 5.4.0 | +| ar100 (serial) | 138K | 08d037c6 | or1k-linux-musl-gcc 9.3.0 | | samd21 (USB) | 223K | 01d2183f | arm-none-eabi-gcc (Fedora 7.4.0-1.fc30) 7.4.0 | | pru (shared memory) | 260K | c5968a08 | pru-gcc (GCC) 8.0.0 20170530 (experimental) | | stm32f103 (USB) | 355K | 01d2183f | arm-none-eabi-gcc (Fedora 7.4.0-1.fc30) 7.4.0 | diff --git a/docs/Bootloaders.md b/docs/Bootloaders.md index 9c7d42d97eb7..1f7aa24db713 100644 --- a/docs/Bootloaders.md +++ b/docs/Bootloaders.md @@ -305,7 +305,7 @@ is a [fork with builds specific to the SKR Mini E3 1.2]( https://github.com/Arksine/STM32_HID_Bootloader/releases/latest). For generic STM32F103 boards such as the blue pill it is possible to flash -the bootloader via 3.3v serial using stm32flash as noted in the stm32duino +the bootloader via 3.3V serial using stm32flash as noted in the stm32duino section above, substituting the file name for the desired hid bootloader binary (ie: hid_generic_pc13.bin for the blue pill). @@ -382,7 +382,7 @@ make flash FLASH_DEVICE=/dev/ttyACM0 It may be necessary to manually enter the bootloader, this can be done by setting "boot 0" low and "boot 1" high. On the SKR Mini E3 "Boot 1" is not available, so it may be done by setting pin PA2 low if you flashed -"hid_btt_skr_mini_e3.bin". This pin is labeld "TX0" on the TFT header in +"hid_btt_skr_mini_e3.bin". This pin is labeled "TX0" on the TFT header in the SKR Mini E3's "PIN" document. There is a ground pin next to PA2 which you can use to pull PA2 low. @@ -390,7 +390,7 @@ which you can use to pull PA2 low. The [MSC bootloader](https://github.com/Telekatz/MSC-stm32f103-bootloader) is a driverless bootloader capable of flashing over USB. -It is possible to flash the bootloader via 3.3v serial using stm32flash as noted +It is possible to flash the bootloader via 3.3V serial using stm32flash as noted in the stm32duino section above, substituting the file name for the desired MSC bootloader binary (ie: MSCboot-Bluepill.bin for the blue pill). @@ -419,7 +419,7 @@ It is recommended to use a ST-Link Programmer to flash CanBoot, however it should be possible to flash using `stm32flash` on STM32F103 devices, and `dfu-util` on STM32F042/STM32F072 devices. See the previous sections in this document for instructions on these flashing methods, substituting `canboot.bin` -for the file name where appropriate. The CanBoot repo linked above provides +for the file name where appropriate. The CanBoot repository linked above provides instructions for building the bootloader. The first time CanBoot has been flashed it should detect that no application @@ -448,8 +448,8 @@ When building Klipper for use with CanBoot, select the 8 KiB Bootloader option. ## STM32F4 micro-controllers (SKR Pro 1.1) -STM32F4 microcontrollers come equipped with a built-in system bootloader -capable of flashing over USB (via DFU), 3.3v Serial, and various other +STM32F4 micro-controllers come equipped with a built-in system bootloader +capable of flashing over USB (via DFU), 3.3V Serial, and various other methods (see STM Document AN2606 for more information). Some STM32F4 boards, such as the SKR Pro 1.1, are not able to enter the DFU bootloader. The HID bootloader is available for STM32F405/407 @@ -458,8 +458,8 @@ Note that you may need to configure and build a version specific to your board, a [build for the SKR Pro 1.1 is available here]( https://github.com/Arksine/STM32_HID_Bootloader/releases/latest). -Unless your board is DFU capable the most accessable flashing method -is likely via 3.3v serial, which follows the same procedure as +Unless your board is DFU capable the most accessible flashing method +is likely via 3.3V serial, which follows the same procedure as [flashing the STM32F103 using stm32flash](#stm32f103-micro-controllers-blue-pill-devices). For example: ``` diff --git a/docs/CONTRIBUTING.md b/docs/CONTRIBUTING.md index 793fc7d5fd70..db664c86e0f3 100644 --- a/docs/CONTRIBUTING.md +++ b/docs/CONTRIBUTING.md @@ -253,8 +253,8 @@ The Klipper "reviewers" are: | ---------------------- | ----------------- | ----------------- | | Dmitry Butyugin | @dmbutyugin | Input shaping, resonance testing, kinematics | | Eric Callahan | @Arksine | Bed leveling, MCU flashing | +| James Hartley | @JamesH1978 | Configuration files | | Kevin O'Connor | @KevinOConnor | Core motion system, Micro-controller code | -| Paul McGowan | @mental405 | Configuration files, documentation | Please do not "ping" any of the reviewers and please do not direct submissions at them. All of the reviewers monitor the forums and PRs, diff --git a/docs/Config_Changes.md b/docs/Config_Changes.md index 75b4d0b13f43..14c3b12bfbda 100644 --- a/docs/Config_Changes.md +++ b/docs/Config_Changes.md @@ -8,6 +8,34 @@ All dates in this document are approximate. ## Changes +20230407: The `stalled_bytes` counter in the log and in the +`printer.mcu.last_stats` field has been renamed to `upcoming_bytes`. + +20230304: The `SET_TMC_CURRENT` command now properly adjusts the globalscaler +register for drivers that have it. This removes a limitation where on tmc5160, +the currents could not be raised higher with `SET_TMC_CURRENT` than the +`run_current` value set in the config file. +However, this has a side effect: After running `SET_TMC_CURRENT`, the stepper +must be held at standstill for >130ms in case StealthChop2 is used so that the +AT#1 calibration gets executed by the driver. + +20230202: The format of the `printer.screws_tilt_adjust` status +information has changed. The information is now stored as a dictionary of +screws with the resulting measurements. See the +[status reference](Status_Reference.md#screws_tilt_adjust) for details. + +20230201: The `[bed_mesh]` module no longer loads the `default` profile +on startup. It is recommended that users who use the `default` profile +add `BED_MESH_PROFILE LOAD=default` to their `START_PRINT` macro (or +to their slicer's "Start G-Code" configuration when applicable). + +20230103: It is now possible with the flash-sdcard.sh script to flash +both variants of the Bigtreetech SKR-2, STM32F407 and STM32F429. +This means that the original tag of btt-skr2 now has changed to either +btt-skr-2-f407 or btt-skr-2-f429. + +20221128: Klipper v0.11.0 released. + 20221122: Previously, with safe_z_home, it was possible that the z_hop after the g28 homing would go in the negative z direction. Now, a z_hop is performed after g28 only if it results in a positive diff --git a/docs/Config_Reference.md b/docs/Config_Reference.md index 4319a0568b81..dd4449567699 100644 --- a/docs/Config_Reference.md +++ b/docs/Config_Reference.md @@ -346,7 +346,7 @@ max_z_velocity: #min_angle: 5 # This represents the minimum angle (in degrees) relative to horizontal # that the deltesian arms are allowed to achieve. This parameter is -# intended to restrict the arms from becomming completely horizontal, +# intended to restrict the arms from becoming completely horizontal, # which would risk accidental inversion of the XZ axis. The default is 5. #print_width: # The distance (in mm) of valid toolhead X coordinates. One may use @@ -383,7 +383,7 @@ arm_x_length: # for stepper_right, this parameter defaults to the value specified for # stepper_left. -# The stepper_right section is used to desribe the stepper controlling the +# The stepper_right section is used to describe the stepper controlling the # right tower. [stepper_right] @@ -1093,12 +1093,12 @@ information. # The height (in mm) that the head should be commanded to move to # just prior to starting a probe operation. The default is 5. #screw_thread: CW-M3 -# The type of screw used for bed level, M3, M4 or M5 and the -# direction of the knob used to level the bed, clockwise decrease -# counter-clockwise decrease. +# The type of screw used for bed leveling, M3, M4, or M5, and the +# rotation direction of the knob that is used to level the bed. # Accepted values: CW-M3, CCW-M3, CW-M4, CCW-M4, CW-M5, CCW-M5. -# Default value is CW-M3, most printers use an M3 screw and -# turning the knob clockwise decrease distance. +# Default value is CW-M3 which most printers use. A clockwise +# rotation of the knob decreases the gap between the nozzle and the +# bed. Conversely, a counter-clockwise rotation increases the gap. ``` ### [z_tilt] @@ -1640,7 +1640,7 @@ cs_pin: ### [mpu9250] -Support for MPU-9250, MPU-9255, MPU-9255, MPU-6050, and MPU-6500 +Support for MPU-9250, MPU-9255, MPU-6515, MPU-6050, and MPU-6500 accelerometers (one may define any number of sections with an "mpu9250" prefix). @@ -2375,6 +2375,30 @@ sensor_type: BME280 # above parameters. ``` +### AHT10/AHT20/AHT21 temperature sensor + +AHT10/AHT20/AHT21 two wire interface (I2C) environmental sensors. +Note that these sensors are not intended for use with extruders and +heater beds, but rather for monitoring ambient temperature (C) and +relative humidity. See +[sample-macros.cfg](../config/sample-macros.cfg) for a gcode_macro +that may be used to report humidity in addition to temperature. + +``` +sensor_type: AHT10 +# Also use AHT10 for AHT20 and AHT21 sensors. +#i2c_address: +# Default is 56 (0x38). Some AHT10 sensors give the option to use +# 57 (0x39) by moving a resistor. +#i2c_mcu: +#i2c_bus: +#i2c_speed: +# See the "common I2C settings" section for a description of the +# above parameters. +#aht10_report_time: +# Interval in seconds between readings. Default is 30, minimum is 5 +``` + ### HTU21D sensor HTU21D family two wire interface (I2C) environmental sensor. Note that @@ -3073,6 +3097,30 @@ run_current: # set, "stealthChop" mode will be enabled if the stepper motor # velocity is below this value. The default is 0, which disables # "stealthChop" mode. +#driver_MSLUT0: 2863314260 +#driver_MSLUT1: 1251300522 +#driver_MSLUT2: 608774441 +#driver_MSLUT3: 269500962 +#driver_MSLUT4: 4227858431 +#driver_MSLUT5: 3048961917 +#driver_MSLUT6: 1227445590 +#driver_MSLUT7: 4211234 +#driver_W0: 2 +#driver_W1: 1 +#driver_W2: 1 +#driver_W3: 1 +#driver_X1: 128 +#driver_X2: 255 +#driver_X3: 255 +#driver_START_SIN: 0 +#driver_START_SIN90: 247 +# These fields control the Microstep Table registers directly. The optimal +# wave table is specific to each motor and might vary with current. An +# optimal configuration will have minimal print artifacts caused by +# non-linear stepper movement. The values specified above are the default +# values used by the driver. The value must be specified as a decimal integer +# (hex form is not supported). In order to compute the wave table fields, +# see the tmc2130 "Calculation Sheet" from the Trinamic website. #driver_IHOLDDELAY: 8 #driver_TPOWERDOWN: 0 #driver_TBL: 1 @@ -3283,6 +3331,126 @@ run_current: # HDEC) is interpreted as the MSB of HSTRT in this case). ``` +### [tmc2240] + +Configure a TMC2240 stepper motor driver via SPI bus. To use this +feature, define a config section with a "tmc2240" prefix followed by +the name of the corresponding stepper config section (for example, +"[tmc2240 stepper_x]"). + +``` +[tmc2240 stepper_x] +cs_pin: +# The pin corresponding to the TMC2240 chip select line. This pin +# will be set to low at the start of SPI messages and raised to high +# after the message completes. This parameter must be provided. +#spi_speed: +#spi_bus: +#spi_software_sclk_pin: +#spi_software_mosi_pin: +#spi_software_miso_pin: +# See the "common SPI settings" section for a description of the +# above parameters. +#chain_position: +#chain_length: +# These parameters configure an SPI daisy chain. The two parameters +# define the stepper position in the chain and the total chain length. +# Position 1 corresponds to the stepper that connects to the MOSI signal. +# The default is to not use an SPI daisy chain. +#interpolate: True +# If true, enable step interpolation (the driver will internally +# step at a rate of 256 micro-steps). The default is True. +run_current: +# The amount of current (in amps RMS) to configure the driver to use +# during stepper movement. This parameter must be provided. +#hold_current: +# The amount of current (in amps RMS) to configure the driver to use +# when the stepper is not moving. Setting a hold_current is not +# recommended (see TMC_Drivers.md for details). The default is to +# not reduce the current. +#rref: 12000 +# The resistance (in ohms) of the resistor between IREF and GND. The +# default is 12000. +#stealthchop_threshold: 0 +# The velocity (in mm/s) to set the "stealthChop" threshold to. When +# set, "stealthChop" mode will be enabled if the stepper motor +# velocity is below this value. The default is 0, which disables +# "stealthChop" mode. +#driver_MSLUT0: 2863314260 +#driver_MSLUT1: 1251300522 +#driver_MSLUT2: 608774441 +#driver_MSLUT3: 269500962 +#driver_MSLUT4: 4227858431 +#driver_MSLUT5: 3048961917 +#driver_MSLUT6: 1227445590 +#driver_MSLUT7: 4211234 +#driver_W0: 2 +#driver_W1: 1 +#driver_W2: 1 +#driver_W3: 1 +#driver_X1: 128 +#driver_X2: 255 +#driver_X3: 255 +#driver_START_SIN: 0 +#driver_START_SIN90: 247 +#driver_OFFSET_SIN90: 0 +# These fields control the Microstep Table registers directly. The optimal +# wave table is specific to each motor and might vary with current. An +# optimal configuration will have minimal print artifacts caused by +# non-linear stepper movement. The values specified above are the default +# values used by the driver. The value must be specified as a decimal integer +# (hex form is not supported). In order to compute the wave table fields, +# see the tmc2130 "Calculation Sheet" from the Trinamic website. +# Additionally, this driver also has the OFFSET_SIN90 field which can be used +# to tune a motor with unbalanced coils. See the `Sine Wave Lookup Table` +# section in the datasheet for information about this field and how to tune +# it. +#driver_IHOLDDELAY: 6 +#driver_IRUNDELAY: 4 +#driver_TPOWERDOWN: 10 +#driver_TBL: 2 +#driver_TOFF: 3 +#driver_HEND: 2 +#driver_HSTRT: 5 +#driver_FD3: 0 +#driver_TPFD: 4 +#driver_CHM: 0 +#driver_VHIGHFS: 0 +#driver_VHIGHCHM: 0 +#driver_DISS2G: 0 +#driver_DISS2VS: 0 +#driver_PWM_AUTOSCALE: True +#driver_PWM_AUTOGRAD: True +#driver_PWM_FREQ: 0 +#driver_FREEWHEEL: 0 +#driver_PWM_GRAD: 0 +#driver_PWM_OFS: 29 +#driver_PWM_REG: 4 +#driver_PWM_LIM: 12 +#driver_SGT: 0 +#driver_SEMIN: 0 +#driver_SEUP: 0 +#driver_SEMAX: 0 +#driver_SEDN: 0 +#driver_SEIMIN: 0 +#driver_SFILT: 0 +#driver_SG4_ANGLE_OFFSET: 1 +# Set the given register during the configuration of the TMC2240 +# chip. This may be used to set custom motor parameters. The +# defaults for each parameter are next to the parameter name in the +# above list. +#diag0_pin: +#diag1_pin: +# The micro-controller pin attached to one of the DIAG lines of the +# TMC2240 chip. Only a single diag pin should be specified. The pin +# is "active low" and is thus normally prefaced with "^!". Setting +# this creates a "tmc2240_stepper_x:virtual_endstop" virtual pin +# which may be used as the stepper's endstop_pin. Doing this enables +# "sensorless homing". (Be sure to also set driver_SGT to an +# appropriate sensitivity value.) The default is to not enable +# sensorless homing. +``` + ### [tmc5160] Configure a TMC5160 stepper motor driver via SPI bus. To use this @@ -3328,6 +3496,30 @@ run_current: # set, "stealthChop" mode will be enabled if the stepper motor # velocity is below this value. The default is 0, which disables # "stealthChop" mode. +#driver_MSLUT0: 2863314260 +#driver_MSLUT1: 1251300522 +#driver_MSLUT2: 608774441 +#driver_MSLUT3: 269500962 +#driver_MSLUT4: 4227858431 +#driver_MSLUT5: 3048961917 +#driver_MSLUT6: 1227445590 +#driver_MSLUT7: 4211234 +#driver_W0: 2 +#driver_W1: 1 +#driver_W2: 1 +#driver_W3: 1 +#driver_X1: 128 +#driver_X2: 255 +#driver_X3: 255 +#driver_START_SIN: 0 +#driver_START_SIN90: 247 +# These fields control the Microstep Table registers directly. The optimal +# wave table is specific to each motor and might vary with current. An +# optimal configuration will have minimal print artifacts caused by +# non-linear stepper movement. The values specified above are the default +# values used by the driver. The value must be specified as a decimal integer +# (hex form is not supported). In order to compute the wave table fields, +# see the tmc2130 "Calculation Sheet" from the Trinamic website. #driver_IHOLDDELAY: 6 #driver_TPOWERDOWN: 10 #driver_TBL: 2 @@ -3356,6 +3548,10 @@ run_current: #driver_SEDN: 0 #driver_SEIMIN: 0 #driver_SFILT: 0 +#driver_DRVSTRENGTH: 0 +#driver_BBMCLKS: 4 +#driver_BBMTIME: 0 +#driver_FILT_ISENSE: 0 # Set the given register during the configuration of the TMC5160 # chip. This may be used to set custom motor parameters. The # defaults for each parameter are next to the parameter name in the @@ -4275,7 +4471,7 @@ serial: #auto_load_speed: 2 # Extrude feedrate when autoloading, default is 2 (mm/s) #auto_cancel_variation: 0.1 -# Auto cancel print when ping varation is above this threshold +# Auto cancel print when ping variation is above this threshold ``` ### [angle] @@ -4341,20 +4537,20 @@ SPI bus. The following parameters are generally available for devices using an I2C bus. -Note that Klipper's current micro-controller support for i2c is -generally not tolerant to line noise. Unexpected errors on the i2c +Note that Klipper's current micro-controller support for I2C is +generally not tolerant to line noise. Unexpected errors on the I2C wires may result in Klipper raising a run-time error. Klipper's support for error recovery varies between each micro-controller type. -It is generally recommended to only use i2c devices that are on the +It is generally recommended to only use I2C devices that are on the same printed circuit board as the micro-controller. Most Klipper micro-controller implementations only support an -`i2c_speed` of 100000. The Klipper "linux" micro-controller supports a -400000 speed, but it must be +`i2c_speed` of 100000 (*standard mode*, 100kbit/s). The Klipper "Linux" +micro-controller supports a 400000 speed (*fast mode*, 400kbit/s), but it must be [set in the operating system](RPi_microcontroller.md#optional-enabling-i2c) and the `i2c_speed` parameter is otherwise ignored. The Klipper -"rp2040" micro-controller supports a rate of 400000 via the -`i2c_speed` parameter. All other Klipper micro-controllers use a +"RP2040" micro-controller and ATmega AVR family support a rate of 400000 +via the `i2c_speed` parameter. All other Klipper micro-controllers use a 100000 rate and ignore the `i2c_speed` parameter. ``` @@ -4372,5 +4568,5 @@ and the `i2c_speed` parameter is otherwise ignored. The Klipper # The I2C speed (in Hz) to use when communicating with the device. # The Klipper implementation on most micro-controllers is hard-coded # to 100000 and changing this value has no effect. The default is -# 100000. +# 100000. Linux, RP2040 and ATmega support 400000. ``` diff --git a/docs/Debugging.md b/docs/Debugging.md index 8fd69b5edbc8..be3699c286a0 100644 --- a/docs/Debugging.md +++ b/docs/Debugging.md @@ -216,7 +216,7 @@ after the above compilation: ``` ls ./build/pysimulavr/_pysimulavr.*.so ``` -This commmand should report a specific file (e.g. +This command should report a specific file (e.g. **./build/pysimulavr/_pysimulavr.cpython-39-x86_64-linux-gnu.so**) and not an error. diff --git a/docs/Features.md b/docs/Features.md index aa56876033ac..96b17a756f1d 100644 --- a/docs/Features.md +++ b/docs/Features.md @@ -12,10 +12,10 @@ Klipper has several compelling features: kinematic estimations (such as the Bresenham algorithm) - instead it calculates precise step times based on the physics of acceleration and the physics of the machine kinematics. More precise stepper - movement translates to quieter and more stable printer operation. + movement provides quieter and more stable printer operation. * Best in class performance. Klipper is able to achieve high stepping - rates on both new and old micro-controllers. Even old 8bit + rates on both new and old micro-controllers. Even old 8-bit micro-controllers can obtain rates over 175K steps per second. On more recent micro-controllers, several million steps per second are possible. Higher stepper rates enable higher print velocities. The @@ -53,6 +53,13 @@ Klipper has several compelling features: types of robots easier and it keeps timing precise even with complex kinematics (no "line segmentation" is needed). +* Klipper is hardware agnostic. One should get the same precise timing + independent of the low-level electronics hardware. The Klipper + micro-controller code is designed to faithfully follow the schedule + provided by the Klipper host software (or prominently alert the user + if it is unable to). This makes it easier to use available hardware, + to upgrade to new hardware, and to have confidence in the hardware. + * Portable code. Klipper works on ARM, AVR, and PRU based micro-controllers. Existing "reprap" style printers can run Klipper without hardware modification - just add a Raspberry Pi. Klipper's @@ -78,9 +85,10 @@ Klipper has several compelling features: Klipper supports many standard 3d printer features: -* Works with Octoprint. This allows the printer to be controlled using +* Several web interfaces available. Works with Mainsail, Fluidd, + OctoPrint and others. This allows the printer to be controlled using a regular web-browser. The same Raspberry Pi that runs Klipper can - also run Octoprint. + also run the web interface. * Standard G-Code support. Common g-code commands that are produced by typical "slicers" (SuperSlicer, Cura, PrusaSlicer, etc.) are @@ -90,7 +98,8 @@ Klipper supports many standard 3d printer features: extruders on independent carriages (IDEX) are also supported. * Support for cartesian, delta, corexy, corexz, hybrid-corexy, - hybrid-corexz, rotary delta, polar, and cable winch style printers. + hybrid-corexz, deltesian, rotary delta, polar, and cable winch style + printers. * Automatic bed leveling support. Klipper can be configured for basic bed tilt detection or full mesh bed leveling. If the bed uses @@ -103,6 +112,9 @@ Klipper supports many standard 3d printer features: dimension calibration. The calibration can be done with a Z height probe or via manual probing. +* Run-time "exclude object" support. When configured, this module may + facilitate canceling of just one object in a multi-part print. + * Support for common temperature sensors (eg, common thermistors, AD595, AD597, AD849x, PT100, PT1000, MAX6675, MAX31855, MAX31856, MAX31865, BME280, HTU21D, DS18B20, and LM75). Custom thermistors and @@ -119,7 +131,7 @@ Klipper supports many standard 3d printer features: * Support for run-time configuration of TMC2130, TMC2208/TMC2224, TMC2209, TMC2660, and TMC5160 stepper motor drivers. There is also support for current control of traditional stepper drivers via - AD5206, MCP4451, MCP4728, MCP4018, and PWM pins. + AD5206, DAC084S085, MCP4451, MCP4728, MCP4018, and PWM pins. * Support for common LCD displays attached directly to the printer. A default menu is also available. The contents of the display and menu @@ -139,8 +151,8 @@ Klipper supports many standard 3d printer features: * Support for filament presence sensors, filament motion sensors, and filament width sensors. -* Support for measuring and recording acceleration using an adxl345 - accelerometer. +* Support for measuring and recording acceleration using an adxl345, + mpu9250, and mpu6050 accelerometers. * Support for limiting the top speed of short "zigzag" moves to reduce printer vibration and noise. See the [kinematics](Kinematics.md) @@ -173,6 +185,7 @@ represent total number of steps per second on the micro-controller. | RP2040 | 2400K | 1636K | | SAM4E8E | 2500K | 1674K | | SAMD51 | 3077K | 1885K | +| AR100 | 3529K | 2507K | | STM32F407 | 3652K | 2459K | | STM32F446 | 3913K | 2634K | | STM32H743 | 9091K | 6061K | diff --git a/docs/G-Codes.md b/docs/G-Codes.md index d9cefd80b715..d89c7df8cd72 100644 --- a/docs/G-Codes.md +++ b/docs/G-Codes.md @@ -146,14 +146,15 @@ The following commands are available when the (also see the [bed mesh guide](Bed_Mesh.md)). #### BED_MESH_CALIBRATE -`BED_MESH_CALIBRATE [METHOD=manual] [=] -[=]`: This command probes the bed using -generated points specified by the parameters in the config. After -probing, a mesh is generated and z-movement is adjusted according to -the mesh. See the PROBE command for details on the optional probe -parameters. If METHOD=manual is specified then the manual probing tool -is activated - see the MANUAL_PROBE command above for details on the -additional commands available while this tool is active. +`BED_MESH_CALIBRATE [METHOD=manual] [HORIZONTAL_MOVE_Z=] +[=] [=]`: This command probes +the bed using generated points specified by the parameters in the config. After +probing, a mesh is generated and z-movement is adjusted according to the mesh. +See the PROBE command for details on the optional probe parameters. If +METHOD=manual is specified then the manual probing tool is activated - see the +MANUAL_PROBE command above for details on the additional commands available +while this tool is active. The optional `HORIZONTAL_MOVE_Z` value overrides the +`horizontal_move_z` option specified in the config file. #### BED_MESH_OUTPUT `BED_MESH_OUTPUT PGP=[<0:1>]`: This command outputs the current probed @@ -207,13 +208,14 @@ The following commands are available when the [bed_tilt config section](Config_Reference.md#bed_tilt) is enabled. #### BED_TILT_CALIBRATE -`BED_TILT_CALIBRATE [METHOD=manual] [=]`: This -command will probe the points specified in the config and then -recommend updated x and y tilt adjustments. See the PROBE command for -details on the optional probe parameters. If METHOD=manual is -specified then the manual probing tool is activated - see the -MANUAL_PROBE command above for details on the additional commands -available while this tool is active. +`BED_TILT_CALIBRATE [METHOD=manual] [HORIZONTAL_MOVE_Z=] +[=]`: This command will probe the points specified in +the config and then recommend updated x and y tilt adjustments. See the PROBE +command for details on the optional probe parameters. If METHOD=manual is +specified then the manual probing tool is activated - see the MANUAL_PROBE +command above for details on the additional commands available while this tool +is active. The optional `HORIZONTAL_MOVE_Z` value overrides the +`horizontal_move_z` option specified in the config file. ### [bltouch] @@ -262,13 +264,14 @@ The following commands are available when the is enabled (also see the [delta calibrate guide](Delta_Calibrate.md)). #### DELTA_CALIBRATE -`DELTA_CALIBRATE [METHOD=manual] [=]`: This -command will probe seven points on the bed and recommend updated -endstop positions, tower angles, and radius. See the PROBE command for -details on the optional probe parameters. If METHOD=manual is -specified then the manual probing tool is activated - see the -MANUAL_PROBE command above for details on the additional commands -available while this tool is active. +`DELTA_CALIBRATE [METHOD=manual] [HORIZONTAL_MOVE_Z=] +[=]`: This command will probe seven points on the bed +and recommend updated endstop positions, tower angles, and radius. See the +PROBE command for details on the optional probe parameters. If METHOD=manual is +specified then the manual probing tool is activated - see the MANUAL_PROBE +command above for details on the additional commands available while this tool +is active. The optional `HORIZONTAL_MOVE_Z` value overrides the +`horizontal_move_z` option specified in the config file. #### DELTA_ANALYZE `DELTA_ANALYZE`: This command is used during enhanced delta @@ -549,8 +552,9 @@ clears any error state from the micro-controller. The following standard G-Code commands are available if a [gcode_arcs config section](Config_Reference.md#gcode_arcs) is enabled: -- Controlled Arc Move (G2 or G3): `G2 [X] [Y] [Z] - [E] [F] I J` +- Arc Move Clockwise (G2), Arc Move Counter-clockwise (G3): `G2|G3 [X] [Y] [Z] + [E] [F] I J|I K|J K` +- Arc Plane Select: G17 (XY plane), G18 (XZ plane), G19 (YZ plane) ### [gcode_macro] @@ -810,9 +814,17 @@ The following command is available when an enabled. #### SET_PIN -`SET_PIN PIN=config_name VALUE= CYCLE_TIME=`: -Note - hardware PWM does not currently support the CYCLE_TIME -parameter and will use the cycle time defined in the config. +`SET_PIN PIN=config_name VALUE= [CYCLE_TIME=]`: Set +the pin to the given output `VALUE`. VALUE should be 0 or 1 for +"digital" output pins. For PWM pins, set to a value between 0.0 and +1.0, or between 0.0 and `scale` if a scale is configured in the +output_pin config section. + +Some pins (currently only "soft PWM" pins) support setting an explicit +cycle time using the CYCLE_TIME parameter (specified in seconds). Note +that the CYCLE_TIME parameter is not stored between SET_PIN commands +(any SET_PIN command without an explicit CYCLE_TIME parameter will use +the `cycle_time` specified in the output_pin config section). ### [palette2] @@ -1069,16 +1081,17 @@ is enabled (also see the #### SCREWS_TILT_CALCULATE `SCREWS_TILT_CALCULATE [DIRECTION=CW|CCW] [MAX_DEVIATION=] -[=]`: This command will invoke the bed screws -adjustment tool. It will command the nozzle to different locations (as -defined in the config file) probing the z height and calculate the -number of knob turns to adjust the bed level. If DIRECTION is -specified, the knob turns will all be in the same direction, clockwise -(CW) or counterclockwise (CCW). See the PROBE command for details on -the optional probe parameters. IMPORTANT: You MUST always do a G28 -before using this command. If MAX_DEVIATION is specified, the command -will raise a gcode error if any difference in the screw height -relative to the base screw height is greater than the value provided. +[HORIZONTAL_MOVE_Z=] [=]`: This command will +invoke the bed screws adjustment tool. It will command the nozzle to different +locations (as defined in the config file) probing the z height and calculate +the number of knob turns to adjust the bed level. If DIRECTION is specified, +the knob turns will all be in the same direction, clockwise (CW) or +counterclockwise (CCW). See the PROBE command for details on the optional probe +parameters. IMPORTANT: You MUST always do a G28 before using this command. If +MAX_DEVIATION is specified, the command will raise a gcode error if any +difference in the screw height relative to the base screw height is greater +than the value provided. The optional `HORIZONTAL_MOVE_Z` value overrides the +`horizontal_move_z` option specified in the config file. ### [sdcard_loop] @@ -1206,8 +1219,9 @@ The following commands are available when any of the are enabled. #### DUMP_TMC -`DUMP_TMC STEPPER=`: This command will read the TMC driver -registers and report their values. +`DUMP_TMC STEPPER= [REGISTER=]`: This command will read all TMC +driver registers and report their values. If a REGISTER is provided, only +the specified register will be dumped. #### INIT_TMC `INIT_TMC STEPPER=`: This command will initialize the TMC @@ -1217,16 +1231,22 @@ turned off then back on. #### SET_TMC_CURRENT `SET_TMC_CURRENT STEPPER= CURRENT= HOLDCURRENT=`: This will adjust the run and hold currents of the TMC driver. -(HOLDCURRENT is not applicable to tmc2660 drivers.) +`HOLDCURRENT` is not applicable to tmc2660 drivers. +When used on a driver which has the `globalscaler` field (tmc5160 and tmc2240), +if StealthChop2 is used, the stepper must be held at standstill for >130ms so +that the driver executes the AT#1 calibration. #### SET_TMC_FIELD -`SET_TMC_FIELD STEPPER= FIELD= VALUE=`: This will -alter the value of the specified register field of the TMC driver. +`SET_TMC_FIELD STEPPER= FIELD= VALUE= VELOCITY=`: +This will alter the value of the specified register field of the TMC driver. This command is intended for low-level diagnostics and debugging only because changing the fields during run-time can lead to undesired and potentially dangerous behavior of your printer. Permanent changes should be made using the printer configuration file instead. No sanity checks are performed for the given values. +A VELOCITY can also be specified instead of a VALUE. This velocity is +converted to the 20bit TSTEP based value representation. Only use the VELOCITY +argument for fields that represent velocities. ### [toolhead] @@ -1317,7 +1337,8 @@ The following commands are available when the [z_tilt config section](Config_Reference.md#z_tilt) is enabled. #### Z_TILT_ADJUST -`Z_TILT_ADJUST [=]`: This command will probe -the points specified in the config and then make independent -adjustments to each Z stepper to compensate for tilt. See the PROBE -command for details on the optional probe parameters. +`Z_TILT_ADJUST [HORIZONTAL_MOVE_Z=] [=]`: This +command will probe the points specified in the config and then make independent +adjustments to each Z stepper to compensate for tilt. See the PROBE command for +details on the optional probe parameters. The optional `HORIZONTAL_MOVE_Z` +value overrides the `horizontal_move_z` option specified in the config file. diff --git a/docs/Hall_Filament_Width_Sensor.md b/docs/Hall_Filament_Width_Sensor.md index 680a1a4f1989..9992ef730401 100644 --- a/docs/Hall_Filament_Width_Sensor.md +++ b/docs/Hall_Filament_Width_Sensor.md @@ -2,7 +2,7 @@ This document describes Filament Width Sensor host module. Hardware used for developing this host module is based on two Hall linear sensors (ss49e for -example). Sensors in the body are located opposite sides. Principle of operation: +example). Sensors in the body are located on opposite sides. Principle of operation: two hall sensors work in differential mode, temperature drift same for sensor. Special temperature compensation not needed. @@ -18,9 +18,9 @@ To use Hall filament width sensor, read Sensor generates two analog output based on calculated filament width. Sum of output voltage always equals to detected filament width. Host module monitors -voltage changes and adjusts extrusion multiplier. I use aux2 connector on -ramps-like board analog11 and analog12 pins. You can use different pins and -differenr boards. +voltage changes and adjusts extrusion multiplier. I use the aux2 connector on +a ramps-like board with the analog11 and analog12 pins. You can use different pins +and different boards. ## Template for menu variables diff --git a/docs/Measuring_Resonances.md b/docs/Measuring_Resonances.md index ba9ad3e9c1d1..17a3756251aa 100644 --- a/docs/Measuring_Resonances.md +++ b/docs/Measuring_Resonances.md @@ -1,35 +1,60 @@ # Measuring Resonances -Klipper has built-in support for ADXL345 accelerometer, which can be used to -measure resonance frequencies of the printer for different axes, and auto-tune -[input shapers](Resonance_Compensation.md) to compensate for resonances. -Note that using ADXL345 requires some soldering and crimping. ADXL345 can be -connected to a Raspberry Pi directly, or to an SPI interface of an MCU -board (it needs to be reasonably fast). - -When sourcing ADXL345, be aware that there is a variety of different PCB -board designs and different clones of them. Make sure that the board supports -SPI mode (small number of boards appear to be hard-configured for I2C by -pulling SDO to GND), and, if it is going to be connected to a 5V printer MCU, -that it has a voltage regulator and a level shifter. - +Klipper has built-in support for the ADXL345 and MPU-9250 compatible +accelerometers which can be used to measure resonance frequencies of the printer +for different axes, and auto-tune [input shapers](Resonance_Compensation.md) to +compensate for resonances. Note that using accelerometers requires some +soldering and crimping. The ADXL345 can be connected to the SPI interface of a +Raspberry Pi or MCU board (it needs to be reasonably fast). The MPU family can +be connected to the I2C interface of a Raspberry Pi directly, or to an I2C +interface of an MCU board that supports 400kbit/s *fast mode* in Klipper. + +When sourcing accelerometers, be aware that there are a variety of different PCB +board designs and different clones of them. If it is going to be connected to a +5V printer MCU ensure it has a voltage regulator and level shifters. + +For ADXL345s, make sure that the board supports SPI mode (a small number of +boards appear to be hard-configured for I2C by pulling SDO to GND). + +For MPU-9250/MPU-9255/MPU-6515/MPU-6050/MPU-6500s there are also a variety of +board designs and clones with different I2C pull-up resistors which will need +supplementing. + +## MCUs with Klipper I2C *fast-mode* Support + +| MCU Family | MCU(s) Tested | MCU(s) with Support | +|:--:|:--|:--| +| Raspberry Pi | 3B+, Pico | 3A, 3A+, 3B, 4 | +| AVR ATmega | ATmega328p | ATmega32u4, ATmega128, ATmega168, ATmega328, ATmega644p, ATmega1280, ATmega1284, ATmega2560 | +| AVR AT90 | - | AT90usb646, AT90usb1286 | ## Installation instructions ### Wiring An ethernet cable with shielded twisted pairs (cat5e or better) is recommended -for signal integrety over a long distance. If you still experience signal integrity -issues (SPI/I2C errors), shorten the cable. - -Connect ethernet cable shielding to the controller board/RPI ground. +for signal integrity over a long distance. If you still experience signal +integrity issues (SPI/I2C errors): + +- Double check the wiring with a digital multimeter for: + - Correct connections when turned off (continuity) + - Correct power and ground voltages +- I2C only: + - Check the SCL and SDA lines' resistances to 3.3V are in the range of 900 + ohms to 1.8K + - For full technical details consult [chapter 7 of the I2C-bus specification + and user manual UM10204](https://www.pololu.com/file/0J435/UM10204.pdf) + for *fast-mode* +- Shorten the cable + +Connect ethernet cable shielding only to the MCU board/Pi ground. ***Double-check your wiring before powering up to prevent damaging your MCU/Raspberry Pi or the accelerometer.*** -#### SPI Accelerometers +### SPI Accelerometers -Suggested twisted pair order: +Suggested twisted pair order for three twisted pairs: ``` GND+MISO @@ -37,11 +62,15 @@ GND+MISO SCLK+CS ``` -##### ADXL345 +Note that unlike a cable shield, GND must be connected at both ends. +#### ADXL345 -**Note: Many MCUs will work with an ADXL345 in SPI mode(eg Pi Pico), wiring and -configuration will vary according to your specific board and avaliable pins.** +##### Direct to Raspberry Pi + +**Note: Many MCUs will work with an ADXL345 in SPI mode (e.g. Pi Pico), wiring +and configuration will vary according to your specific board and available +pins.** You need to connect ADXL345 to your Raspberry Pi via SPI. Note that the I2C connection, which is suggested by ADXL345 documentation, has too low throughput @@ -49,7 +78,7 @@ and **will not work**. The recommended connection scheme: | ADXL345 pin | RPi pin | RPi pin name | |:--:|:--:|:--:| -| 3V3 (or VCC) | 01 | 3.3v DC power | +| 3V3 (or VCC) | 01 | 3.3V DC power | | GND | 06 | Ground | | CS | 24 | GPIO08 (SPI0_CE0_N) | | SDO | 21 | GPIO09 (SPI0_MISO) | @@ -60,20 +89,56 @@ Fritzing wiring diagrams for some of the ADXL345 boards: ![ADXL345-Rpi](img/adxl345-fritzing.png) -#### I2C Accelerometers +##### Using Raspberry Pi Pico + +You may connect the ADXL345 to your Raspberry Pi Pico and then connect the +Pico to your Raspberry Pi via USB. This makes it easy to reuse the +accelerometer on other Klipper devices, as you can connect via USB instead +of GPIO. The Pico does not have much processing power, so make sure it is +only running the accelerometer and not performing any other duties. + +In order to avoid damage to your RPi make sure to connect the ADXL345 to 3.3V +only. Depending on the board's layout, a level shifter may be present, which +makes 5V dangerous for your RPi. + +| ADXL345 pin | Pico pin | Pico pin name | +|:--:|:--:|:--:| +| 3V3 (or VCC) | 36 | 3.3V DC power | +| GND | 38 | Ground | +| CS | 2 | GP1 (SPI0_CSn) | +| SDO | 1 | GP0 (SPI0_RX) | +| SDA | 5 | GP3 (SPI0_TX) | +| SCL | 4 | GP2 (SPI0_SCK) | + +Wiring diagrams for some of the ADXL345 boards: -Suggested twisted pair order: +![ADXL345-Pico](img/adxl345-pico.png) + +### I2C Accelerometers + +Suggested twisted pair order for three pairs (preferred): + +``` +3.3V+GND +SDA+GND +SCL+GND +``` + +or for two pairs: ``` 3.3V+SDA GND+SCL ``` -##### MPU-9250/MPU-9255/MPU-6515/MPU-6050/MPU-6500 +Note that unlike a cable shield, any GND(s) should be connected at both ends. + +#### MPU-9250/MPU-9255/MPU-6515/MPU-6050/MPU-6500 -Alternatives to the ADXL345 are MPU-9250/MPU-9255/MPU-6515/MPU-6050/MPU-6500. -These accelerometers have been tested to work over I2C on the RPi or RP2040(pico) -at 400kbaud. +These accelerometers have been tested to work over I2C on the RPi, RP2040 (Pico) +and AVR at 400kbit/s (*fast mode*). Some MPU accelerometer modules include +pull-ups, but some are too large at 10K and must be changed or supplemented by +smaller parallel resistors. Recommended connection scheme for I2C on the Raspberry Pi: @@ -84,18 +149,34 @@ Recommended connection scheme for I2C on the Raspberry Pi: | SDA | 03 | GPIO02 (SDA1) | | SCL | 05 | GPIO03 (SCL1) | -![MPU-9250 connected to RPI](img/mpu9250-PI-fritzing.png) +The RPi has buit-in 1.8K pull-ups on both SCL and SDA. -Recommended connection scheme for I2C(i2c0a) on the RP2040: +![MPU-9250 connected to Pi](img/mpu9250-PI-fritzing.png) -| MPU-9250 pin | RP2040 pin | RPi pin name | +Recommended connection scheme for I2C (i2c0a) on the RP2040: + +| MPU-9250 pin | RP2040 pin | RP2040 pin name | |:--:|:--:|:--:| -| VCC | 39 | 3v3 | +| VCC | 36 | 3v3 | | GND | 38 | Ground | | SDA | 01 | GP0 (I2C0 SDA) | | SCL | 02 | GP1 (I2C0 SCL) | -![MPU-9250 connected to PICO](img/mpu9250-PICO-fritzing.png) +The Pico does not include any built-in I2C pull-up resistors. + +![MPU-9250 connected to Pico](img/mpu9250-PICO-fritzing.png) + +##### Recommended connection scheme for I2C(TWI) on the AVR ATmega328P Arduino Nano: + +| MPU-9250 pin | Atmega328P TQFP32 pin | Atmega328P pin name | Arduino Nano pin | +|:--:|:--:|:--:|:--:| +| VCC | 39 | - | - | +| GND | 38 | Ground | GND | +| SDA | 27 | SDA | A4 | +| SCL | 28 | SCL | A5 | + +The Arduino Nano does not include any built-in pull-up resistors nor a 3.3V +power pin. ### Mounting the accelerometer @@ -164,6 +245,65 @@ probe_points: It is advised to start with 1 probe point, in the middle of the print bed, slightly above it. +#### Configure ADXL345 With Pi Pico + +##### Flash the Pico Firmware + +On your Raspberry Pi, compile the firmware for the Pico. + +``` +cd ~/klipper +make clean +make menuconfig +``` +![Pico menuconfig](img/klipper_pico_menuconfig.png) + +Now, while holding down the `BOOTSEL` button on the Pico, connect the Pico to +the Raspberry Pi via USB. Compile and flash the firmware. +``` +make flash FLASH_DEVICE=first +``` + +If that fails, you will be told which `FLASH_DEVICE` to use. In this example, +that's ```make flash FLASH_DEVICE=2e8a:0003```. +![Determine flash device](img/flash_rp2040_FLASH_DEVICE.png) + +##### Configure the Connection + +The Pico will now reboot with the new firmware and should show up as a serial +device. Find the pico serial device with `ls /dev/serial/by-id/*`. You can +now add an `adxl.cfg` file with the following settings: + +``` +[mcu adxl] +# Change to whatever you found above. For example, +# usb-Klipper_rp2040_E661640843545B2E-if00 +serial: /dev/serial/by-id/usb-Klipper_rp2040_ + +[adxl345] +cs_pin: adxl:gpio1 +spi_bus: spi0a +axes_map: x,z,y + +[resonance_tester] +accel_chip: adxl345 +probe_points: + # Somewhere slightly above the middle of your print bed + 147,154, 20 + +[output_pin power_mode] # Improve power stability +pin: adxl:gpio23 +``` + +If setting up the ADXL345 configuration in a separate file, as shown above, +you'll also want to modify your `printer.cfg` file to include this: + +``` +[include adxl.cfg] # Comment this out when you disconnect the accelerometer +``` + +Restart Klipper via the `RESTART` command. + #### Configure MPU-6000/9000 series With RPi Make sure the Linux I2C driver is enabled and the baud rate is @@ -184,18 +324,18 @@ probe_points: 100, 100, 20 # an example ``` -#### Configure MPU-6000/9000 series With PICO +#### Configure MPU-9520 Compatibles With Pico -PICO I2C is set to 400000 on default. Simply add the following to the +Pico I2C is set to 400000 on default. Simply add the following to the printer.cfg: ``` [mcu pico] -serial: /dev/serial/by-id/ +serial: /dev/serial/by-id/ [mpu9250] i2c_mcu: pico -i2c_bus: i2c1a +i2c_bus: i2c0a [resonance_tester] accel_chip: mpu9250 @@ -203,7 +343,25 @@ probe_points: 100, 100, 20 # an example [static_digital_output pico_3V3pwm] # Improve power stability -pin: pico:gpio23 +pins: pico:gpio23 +``` + +#### Configure MPU-9520 Compatibles with AVR + +AVR I2C will be set to 400000 by the mpu9250 option. Simply add the following +to the printer.cfg: + +``` +[mcu nano] +serial: /dev/serial/by-id/ + +[mpu9250] +i2c_mcu: nano + +[resonance_tester] +accel_chip: mpu9250 +probe_points: + 100, 100, 20 # an example ``` Restart Klipper via the `RESTART` command. @@ -228,12 +386,14 @@ Recv: // adxl345 values (x, y, z): 470.719200, 941.438400, 9728.196800 ``` If you get an error like `Invalid adxl345 id (got xx vs e5)`, where `xx` -is some other ID, it is indicative of the connection problem with ADXL345, +is some other ID, immediately try again. There's an issue with SPI +initialization. If you still get an error, it is indicative of the connection +problem with ADXL345, or the faulty sensor. Double-check the power, the wiring (that it matches the schematics, no wire is broken or loose, etc.), and soldering quality. -**If you are using MPU-6000/9000 series accelerometer and it show up as `mpu-unknown`, use with -caution! They are probably refurbished chips!** +**If you are using a MPU-9250 compatible accelerometer and it shows up as +`mpu-unknown`, use with caution! They are probably refurbished chips!** Next, try running `MEASURE_AXES_NOISE` in Octoprint, you should get some baseline numbers for the noise of accelerometer on the axes (should be @@ -310,7 +470,7 @@ or you can choose some other configuration yourself based on the generated charts: peaks in the power spectral density on the charts correspond to the resonance frequencies of the printer. -Note that alternatively you can run the input shaper autocalibration +Note that alternatively you can run the input shaper auto-calibration from Klipper [directly](#input-shaper-auto-calibration), which can be convenient, for example, for the input shaper [re-calibration](#input-shaper-re-calibration). @@ -322,10 +482,11 @@ of the accelerometer between the measurements for X and Y axes: measure the resonances of X axis with the accelerometer attached to the toolhead and the resonances of Y axis - to the bed (the usual bed slinger setup). -However, you can also connect two accelerometers simultaneously, though they -must be connected to different boards (say, to an RPi and printer MCU board), or -to two different physical SPI interfaces on the same board (rarely available). -Then they can be configured in the following manner: +However, you can also connect two accelerometers simultaneously, though the +ADXL345 must be connected to different boards (say, to an RPi and printer MCU +board), or to two different physical SPI interfaces on the same board (rarely +available). Then they can be configured in the following manner: + ``` [adxl345 hotend] # Assuming `hotend` chip is connected to an RPi @@ -342,6 +503,30 @@ accel_chip_y: adxl345 bed probe_points: ... ``` +Two MPUs can share one I2C bus, but they **cannot** measure simultaneously as +the 400kbit/s I2C bus is not fast enough. One must have its AD0 pin pulled-down +to 0V (address 104) and the other its AD0 pin pulled-up to 3.3V (address 105): + +``` +[mpu9250 hotend] +i2c_mcu: rpi +i2c_bus: i2c.1 +i2c_address: 104 # This MPU has pin AD0 pulled low + +[mpu9250 bed] +i2c_mcu: rpi +i2c_bus: i2c.1 +i2c_address: 105 # This MPU has pin AD0 pulled high + +[resonance_tester] +# Assuming the typical setup of the bed slinger printer +accel_chip_x: mpu9250 hotend +accel_chip_y: mpu9250 bed +probe_points: ... +``` +[Test with each MPU individually before connecting both to the bus for easy +debugging.] + Then the commands `TEST_RESONANCES AXIS=X` and `TEST_RESONANCES AXIS=Y` will use the correct accelerometer for each axis. @@ -550,9 +735,9 @@ supplying `AXIS=` parameter, like SHAPER_CALIBRATE AXIS=X ``` -**Warning!** It is not advisable to run the shaper autocalibration very +**Warning!** It is not advisable to run the shaper auto-calibration very frequently (e.g. before every print, or every day). In order to determine -resonance frequencies, autocalibration creates intensive vibrations on each of +resonance frequencies, auto-calibration creates intensive vibrations on each of the axes. Generally, 3D printers are not designed to withstand a prolonged exposure to vibrations near the resonance frequencies. Doing so may increase wear of the printer components and reduce their lifespan. There is also an diff --git a/docs/Overview.md b/docs/Overview.md index 6b9a6cd90443..9b94b01ec18c 100644 --- a/docs/Overview.md +++ b/docs/Overview.md @@ -54,7 +54,7 @@ communication with the Klipper developers. perfectly square. - [PWM tools](Using_PWM_Tools.md): Guide on how to use PWM controlled tools such as lasers or spindles. -- [Exclude Object](Exclude_Object.md): The guide to the Exclude Objecs +- [Exclude Object](Exclude_Object.md): The guide to the Exclude Objects implementation. ## Developer Documentation diff --git a/docs/Packaging.md b/docs/Packaging.md index 7aa2c1188995..9e9b1627b7f8 100644 --- a/docs/Packaging.md +++ b/docs/Packaging.md @@ -27,4 +27,4 @@ follows: `python2 scripts/make_version.py YOURDISTRONAME > klippy/.version`. ## Sample packaging script klipper-git is packaged for Arch Linux, and has a PKGBUILD (package build -script) available at [Arch User Repositiory](https://aur.archlinux.org/cgit/aur.git/tree/PKGBUILD?h=klipper-git). +script) available at [Arch User Repository](https://aur.archlinux.org/cgit/aur.git/tree/PKGBUILD?h=klipper-git). diff --git a/docs/RPi_microcontroller.md b/docs/RPi_microcontroller.md index 2e64650c127f..58688d70ea06 100644 --- a/docs/RPi_microcontroller.md +++ b/docs/RPi_microcontroller.md @@ -25,8 +25,8 @@ must run before the klippy process. After installing Klipper, install the script. run: ``` cd ~/klipper/ -sudo cp "./scripts/klipper-mcu-start.sh" /etc/init.d/klipper_mcu -sudo update-rc.d klipper_mcu defaults +sudo cp ./scripts/klipper-mcu.service /etc/systemd/system/ +sudo systemctl enable klipper-mcu.service ``` ## Building the micro-controller code diff --git a/docs/Releases.md b/docs/Releases.md index f92d7a9793e5..7054a0b30e5d 100644 --- a/docs/Releases.md +++ b/docs/Releases.md @@ -3,6 +3,31 @@ History of Klipper releases. Please see [installation](Installation.md) for information on installing Klipper. +## Klipper 0.11.0 + +Available on 20221128. Major changes in this release: +* Trinamic stepper motor driver "step on both edges" optimization. +* Support for Python3. The Klipper host code will run with either + Python2 or Python3. +* Enhanced CAN bus support. Support for CAN bus on rp2040, stm32g0, + stm32h7, same51, and same54 chips. Support for "USB to CAN bus + bridge" mode. +* Support for CanBoot bootloader. +* Support for mpu9250 and mpu6050 accelerometers. +* Improved error handling for max31856, max31855, max31865, and + max6675 temperature sensors. +* It is now possible to configure LEDs to update during long running + G-Code commands using LED "template" support. +* Several micro-controller improvements. New support for stm32h743, + stm32h750, stm32l412, stm32g0b1, same70, same51, and same54 chips. + Support for i2c reads on atsamd and stm32f0. Hardware pwm support on + stm32. Linux mcu signal based event dispatch. New rp2040 support for + "make flash", i2c, and rp2040-e5 USB errata. +* New modules added: angle, dac084S085, exclude_object, led, mpu9250, + pca9632, smart_effector, z_thermal_adjust. New deltesian kinematics + added. New dump_mcu tool added. +* Several bug fixes and code cleanups. + ## Klipper 0.10.0 Available on 20210929. Major changes in this release: diff --git a/docs/SDCard_Updates.md b/docs/SDCard_Updates.md index 1b94a1e28586..77a586157dae 100644 --- a/docs/SDCard_Updates.md +++ b/docs/SDCard_Updates.md @@ -127,13 +127,13 @@ BOARD_DEFS = { ``` The following fields may be specified: -- `mcu`: The mcu type. This can be retrevied after configuring the build +- `mcu`: The mcu type. This can be retrieved after configuring the build via `make menuconfig` by running `cat .config | grep CONFIG_MCU`. This field is required. -- `spi_bus`: The SPI bus connected to the SD Card. This should be retreived +- `spi_bus`: The SPI bus connected to the SD Card. This should be retrieved from the board's schematic. This field is required. - `cs_pin`: The Chip Select Pin connected to the SD Card. This should be - retreived from the board schematic. This field is required. + retrieved from the board schematic. This field is required. - `firmware_path`: The path on the SD Card where firmware should be transferred. The default is `firmware.bin`. - `current_firmware_path`: The path on the SD Card where the renamed firmware diff --git a/docs/Slicers.md b/docs/Slicers.md index 5cc678ec913e..afffe7499994 100644 --- a/docs/Slicers.md +++ b/docs/Slicers.md @@ -87,3 +87,39 @@ Klipper's maximum extrusion cross-section check. In contrast, it is okay (and often helpful) to use a slicer's "retract" setting, "wipe" setting, and/or "wipe on retract" setting. + +## START_PRINT macros + +When using a START_PRINT macro or similar, it is useful to sometimes +pass through parameters from the slicer variables to the macro. + +In Cura, to pass through temperatures, the following start gcode +would be used: + +``` +START_PRINT BED_TEMP={material_bed_temperature_layer_0} EXTRUDER_TEMP={material_print_temperature_layer_0} +``` + +In slic3r derivatives such as PrusaSlicer and SuperSlicer, the +following would be used: + +``` +START_PRINT EXTRUDER_TEMP=[first_layer_temperature] BED_TEMP=[first_layer_bed_temperature] +``` + +Also note that these slicers will insert their own heating codes when +certain conditions are not met. In Cura, the existence of the +`{material_bed_temperature_layer_0}` and `{material_print_temperature_layer_0}` +variables is enough to mitigate this. In slic3r derivatives, +you would use: + +``` +M140 S0 +M104 S0 +``` + +before the macro call. Also note that SuperSlicer has a +"custom gcode only" button option, which achieves the same outcome. + +An example of a START_PRINT macro using these paramaters can +be found in config/sample-macros.cfg diff --git a/docs/Status_Reference.md b/docs/Status_Reference.md index e6595ddbbec0..84b4de73ae00 100644 --- a/docs/Status_Reference.md +++ b/docs/Status_Reference.md @@ -126,6 +126,9 @@ The following information is available for extruder_stepper objects (as well as [extruder](Config_Reference.md#extruder) objects): - `pressure_advance`: The current [pressure advance](Pressure_Advance.md) value. - `smooth_time`: The current pressure advance smooth time. +- `motion_queue`: The name of the extruder that this extruder stepper is + currently synchronized to. This is reported as `None` if the extruder stepper + is not currently associated with an extruder. ## fan @@ -343,6 +346,7 @@ The following information is available in the [probe](Config_Reference.md#probe) object (this object is also available if a [bltouch](Config_Reference.md#bltouch) config section is defined): +- `name`: Returns the name of the probe in use. - `last_query`: Returns True if the probe was reported as "triggered" during the last QUERY_PROBE command. Note, if this is used in a macro, due to the order of template expansion, the QUERY_PROBE @@ -369,6 +373,25 @@ The following information is available in the `query_endstops` object the QUERY_ENDSTOP command must be run prior to the macro containing this reference. +## screws_tilt_adjust + +The following information is available in the `screws_tilt_adjust` +object: +- `error`: Returns True if the most recent `SCREWS_TILT_CALCULATE` + command included the `MAX_DEVIATION` parameter and any of the probed + screw points exceeded the specified `MAX_DEVIATION`. +- `results[""]`: A dictionary containing the following keys: + - `z`: The measured Z height of the screw location. + - `sign`: A string specifying the direction to turn to screw for the + necessary adjustment. Either "CW" for clockwise or "CCW" for + counterclockwise. + - `adjust`: The number of screw turns to adjust the screw, given in + the format "HH:MM," where "HH" is the number of full screw turns + and "MM" is the number of "minutes of a clock face" representing + a partial screw turn. (E.g. "01:15" would mean to turn the screw + one and a quarter revolutions.) + - `is_base`: Returns True if this is the base screw. + ## servo The following information is available in @@ -376,6 +399,12 @@ The following information is available in - `printer["servo "].value`: The last setting of the PWM pin (a value between 0.0 and 1.0) associated with the servo. +## stepper_enable + +The following information is available in the `stepper_enable` object (this +object is available if any stepper is defined): +- `steppers[""]`: Returns True if the given stepper is enabled. + ## system_stats The following information is available in the `system_stats` object @@ -429,6 +458,9 @@ objects (eg, `[tmc2208 stepper_x]`): - `drv_status`: The results of the last driver status query. (Only non-zero fields are reported.) This field will be null if the driver is not enabled (and thus is not periodically queried). +- `temperature`: The internal temperature reported by the driver. This + field will be null if the driver is not enabled or if the driver + does not support temperature reporting. - `run_current`: The currently set run current. - `hold_current`: The currently set hold current. diff --git a/docs/TMC_Drivers.md b/docs/TMC_Drivers.md index b036b57e0aa5..d2a7eaa33aae 100644 --- a/docs/TMC_Drivers.md +++ b/docs/TMC_Drivers.md @@ -544,7 +544,7 @@ hot. Typical solutions are to decrease the stepper motor current, increase cooling on the stepper motor driver, and/or increase cooling on the stepper motor. -#### TMC reports error: `... ShortToGND` OR `LowSideShort` +#### TMC reports error: `... ShortToGND` OR `ShortToSupply` This indicates the driver has disabled itself because it detected very high current passing through the driver. This may indicate a loose or diff --git a/docs/img/adxl345-pico.png b/docs/img/adxl345-pico.png new file mode 100644 index 000000000000..77bce31baebb Binary files /dev/null and b/docs/img/adxl345-pico.png differ diff --git a/docs/img/flash_rp2040_FLASH_DEVICE.png b/docs/img/flash_rp2040_FLASH_DEVICE.png new file mode 100644 index 000000000000..7687811e4514 Binary files /dev/null and b/docs/img/flash_rp2040_FLASH_DEVICE.png differ diff --git a/docs/img/klipper_pico_menuconfig.png b/docs/img/klipper_pico_menuconfig.png new file mode 100644 index 000000000000..478ee4a15437 Binary files /dev/null and b/docs/img/klipper_pico_menuconfig.png differ diff --git a/klippy/chelper/__init__.py b/klippy/chelper/__init__.py index 04119614f8c5..6166363e2581 100644 --- a/klippy/chelper/__init__.py +++ b/klippy/chelper/__init__.py @@ -85,13 +85,13 @@ double x_r, y_r, z_r; }; + struct trapq *trapq_alloc(void); + void trapq_free(struct trapq *tq); void trapq_append(struct trapq *tq, double print_time , double accel_t, double cruise_t, double decel_t , double start_pos_x, double start_pos_y, double start_pos_z , double axes_r_x, double axes_r_y, double axes_r_z , double start_v, double cruise_v, double accel); - struct trapq *trapq_alloc(void); - void trapq_free(struct trapq *tq); void trapq_finalize_moves(struct trapq *tq, double print_time); void trapq_set_position(struct trapq *tq, double print_time , double pos_x, double pos_y, double pos_z); diff --git a/klippy/chelper/serialqueue.c b/klippy/chelper/serialqueue.c index 75d39d2124bc..b6500fe621d5 100644 --- a/klippy/chelper/serialqueue.c +++ b/klippy/chelper/serialqueue.c @@ -30,7 +30,7 @@ #include "serialqueue.h" // struct queue_message struct command_queue { - struct list_head stalled_queue, ready_queue; + struct list_head upcoming_queue, ready_queue; struct list_node node; }; @@ -59,7 +59,7 @@ struct serialqueue { double srtt, rttvar, rto; // Pending transmission message queues struct list_head pending_queues; - int ready_bytes, stalled_bytes, need_ack_bytes, last_ack_bytes; + int ready_bytes, upcoming_bytes, need_ack_bytes, last_ack_bytes; uint64_t need_kick_clock; struct list_head notify_queue; // Received messages @@ -356,6 +356,7 @@ kick_event(struct serialqueue *sq, double eventtime) pollreactor_update_timer(sq->pr, SQPT_COMMAND, PR_NOW); } +// OS write of data to be sent to the mcu static void do_write(struct serialqueue *sq, void *buf, int buflen) { @@ -457,7 +458,7 @@ build_and_send_command(struct serialqueue *sq, uint8_t *buf, int pending if (len + qm->len > MESSAGE_MAX - MESSAGE_TRAILER_SIZE) break; list_del(&qm->node); - if (list_empty(&cq->ready_queue) && list_empty(&cq->stalled_queue)) + if (list_empty(&cq->ready_queue) && list_empty(&cq->upcoming_queue)) list_del(&cq->node); memcpy(&buf[len], qm->msg, qm->len); len += qm->len; @@ -522,10 +523,10 @@ check_send_command(struct serialqueue *sq, int pending, double eventtime) uint64_t min_stalled_clock = MAX_CLOCK, min_ready_clock = MAX_CLOCK; struct command_queue *cq; list_for_each_entry(cq, &sq->pending_queues, node) { - // Move messages from the stalled_queue to the ready_queue - while (!list_empty(&cq->stalled_queue)) { + // Move messages from the upcoming_queue to the ready_queue + while (!list_empty(&cq->upcoming_queue)) { struct queue_message *qm = list_first_entry( - &cq->stalled_queue, struct queue_message, node); + &cq->upcoming_queue, struct queue_message, node); if (ack_clock < qm->min_clock) { if (qm->min_clock < min_stalled_clock) min_stalled_clock = qm->min_clock; @@ -533,7 +534,7 @@ check_send_command(struct serialqueue *sq, int pending, double eventtime) } list_del(&qm->node); list_add_tail(&qm->node, &cq->ready_queue); - sq->stalled_bytes -= qm->len; + sq->upcoming_bytes -= qm->len; sq->ready_bytes += qm->len; } // Update min_ready_clock @@ -713,7 +714,7 @@ serialqueue_free(struct serialqueue *sq) &sq->pending_queues, struct command_queue, node); list_del(&cq->node); message_queue_free(&cq->ready_queue); - message_queue_free(&cq->stalled_queue); + message_queue_free(&cq->upcoming_queue); } pthread_mutex_unlock(&sq->lock); pollreactor_free(sq->pr); @@ -727,7 +728,7 @@ serialqueue_alloc_commandqueue(void) struct command_queue *cq = malloc(sizeof(*cq)); memset(cq, 0, sizeof(*cq)); list_init(&cq->ready_queue); - list_init(&cq->stalled_queue); + list_init(&cq->upcoming_queue); return cq; } @@ -737,7 +738,7 @@ serialqueue_free_commandqueue(struct command_queue *cq) { if (!cq) return; - if (!list_empty(&cq->ready_queue) || !list_empty(&cq->stalled_queue)) { + if (!list_empty(&cq->ready_queue) || !list_empty(&cq->upcoming_queue)) { errorf("Memory leak! Can't free non-empty commandqueue"); return; } @@ -783,12 +784,12 @@ serialqueue_send_batch(struct serialqueue *sq, struct command_queue *cq return; qm = list_first_entry(msgs, struct queue_message, node); - // Add list to cq->stalled_queue + // Add list to cq->upcoming_queue pthread_mutex_lock(&sq->lock); - if (list_empty(&cq->ready_queue) && list_empty(&cq->stalled_queue)) + if (list_empty(&cq->ready_queue) && list_empty(&cq->upcoming_queue)) list_add_tail(&cq->node, &sq->pending_queues); - list_join_tail(msgs, &cq->stalled_queue); - sq->stalled_bytes += len; + list_join_tail(msgs, &cq->upcoming_queue); + sq->upcoming_bytes += len; int mustwake = 0; if (qm->min_clock < sq->need_kick_clock) { sq->need_kick_clock = 0; @@ -924,13 +925,13 @@ serialqueue_get_stats(struct serialqueue *sq, char *buf, int len) " bytes_retransmit=%u bytes_invalid=%u" " send_seq=%u receive_seq=%u retransmit_seq=%u" " srtt=%.3f rttvar=%.3f rto=%.3f" - " ready_bytes=%u stalled_bytes=%u" + " ready_bytes=%u upcoming_bytes=%u" , stats.bytes_write, stats.bytes_read , stats.bytes_retransmit, stats.bytes_invalid , (int)stats.send_seq, (int)stats.receive_seq , (int)stats.retransmit_seq , stats.srtt, stats.rttvar, stats.rto - , stats.ready_bytes, stats.stalled_bytes); + , stats.ready_bytes, stats.upcoming_bytes); } // Extract old messages stored in the debug queues diff --git a/klippy/chelper/trapq.c b/klippy/chelper/trapq.c index dbb72865e78b..9b1b501b422d 100644 --- a/klippy/chelper/trapq.c +++ b/klippy/chelper/trapq.c @@ -20,54 +20,6 @@ move_alloc(void) return m; } -// Fill and add a move to the trapezoid velocity queue -void __visible -trapq_append(struct trapq *tq, double print_time - , double accel_t, double cruise_t, double decel_t - , double start_pos_x, double start_pos_y, double start_pos_z - , double axes_r_x, double axes_r_y, double axes_r_z - , double start_v, double cruise_v, double accel) -{ - struct coord start_pos = { .x=start_pos_x, .y=start_pos_y, .z=start_pos_z }; - struct coord axes_r = { .x=axes_r_x, .y=axes_r_y, .z=axes_r_z }; - if (accel_t) { - struct move *m = move_alloc(); - m->print_time = print_time; - m->move_t = accel_t; - m->start_v = start_v; - m->half_accel = .5 * accel; - m->start_pos = start_pos; - m->axes_r = axes_r; - trapq_add_move(tq, m); - - print_time += accel_t; - start_pos = move_get_coord(m, accel_t); - } - if (cruise_t) { - struct move *m = move_alloc(); - m->print_time = print_time; - m->move_t = cruise_t; - m->start_v = cruise_v; - m->half_accel = 0.; - m->start_pos = start_pos; - m->axes_r = axes_r; - trapq_add_move(tq, m); - - print_time += cruise_t; - start_pos = move_get_coord(m, cruise_t); - } - if (decel_t) { - struct move *m = move_alloc(); - m->print_time = print_time; - m->move_t = decel_t; - m->start_v = cruise_v; - m->half_accel = -.5 * accel; - m->start_pos = start_pos; - m->axes_r = axes_r; - trapq_add_move(tq, m); - } -} - // Return the distance moved given a time in a move inline double move_get_distance(struct move *m, double move_time) @@ -163,6 +115,54 @@ trapq_add_move(struct trapq *tq, struct move *m) tail_sentinel->print_time = 0.; } +// Fill and add a move to the trapezoid velocity queue +void __visible +trapq_append(struct trapq *tq, double print_time + , double accel_t, double cruise_t, double decel_t + , double start_pos_x, double start_pos_y, double start_pos_z + , double axes_r_x, double axes_r_y, double axes_r_z + , double start_v, double cruise_v, double accel) +{ + struct coord start_pos = { .x=start_pos_x, .y=start_pos_y, .z=start_pos_z }; + struct coord axes_r = { .x=axes_r_x, .y=axes_r_y, .z=axes_r_z }; + if (accel_t) { + struct move *m = move_alloc(); + m->print_time = print_time; + m->move_t = accel_t; + m->start_v = start_v; + m->half_accel = .5 * accel; + m->start_pos = start_pos; + m->axes_r = axes_r; + trapq_add_move(tq, m); + + print_time += accel_t; + start_pos = move_get_coord(m, accel_t); + } + if (cruise_t) { + struct move *m = move_alloc(); + m->print_time = print_time; + m->move_t = cruise_t; + m->start_v = cruise_v; + m->half_accel = 0.; + m->start_pos = start_pos; + m->axes_r = axes_r; + trapq_add_move(tq, m); + + print_time += cruise_t; + start_pos = move_get_coord(m, cruise_t); + } + if (decel_t) { + struct move *m = move_alloc(); + m->print_time = print_time; + m->move_t = decel_t; + m->start_v = cruise_v; + m->half_accel = -.5 * accel; + m->start_pos = start_pos; + m->axes_r = axes_r; + trapq_add_move(tq, m); + } +} + #define HISTORY_EXPIRE (30.0) // Expire any moves older than `print_time` from the trapezoid velocity queue diff --git a/klippy/chelper/trapq.h b/klippy/chelper/trapq.h index dbde8d3ea242..bd8f4e8c2f94 100644 --- a/klippy/chelper/trapq.h +++ b/klippy/chelper/trapq.h @@ -32,17 +32,17 @@ struct pull_move { }; struct move *move_alloc(void); -void trapq_append(struct trapq *tq, double print_time - , double accel_t, double cruise_t, double decel_t - , double start_pos_x, double start_pos_y, double start_pos_z - , double axes_r_x, double axes_r_y, double axes_r_z - , double start_v, double cruise_v, double accel); double move_get_distance(struct move *m, double move_time); struct coord move_get_coord(struct move *m, double move_time); struct trapq *trapq_alloc(void); void trapq_free(struct trapq *tq); void trapq_check_sentinels(struct trapq *tq); void trapq_add_move(struct trapq *tq, struct move *m); +void trapq_append(struct trapq *tq, double print_time + , double accel_t, double cruise_t, double decel_t + , double start_pos_x, double start_pos_y, double start_pos_z + , double axes_r_x, double axes_r_y, double axes_r_z + , double start_v, double cruise_v, double accel); void trapq_finalize_moves(struct trapq *tq, double print_time); void trapq_set_position(struct trapq *tq, double print_time , double pos_x, double pos_y, double pos_z); diff --git a/klippy/configfile.py b/klippy/configfile.py index 63dd814969b1..dd32d47fd3c6 100644 --- a/klippy/configfile.py +++ b/klippy/configfile.py @@ -80,11 +80,15 @@ def getchoice(self, option, choices, default=sentinel, note_valid=True): def getlists(self, option, default=sentinel, seps=(',',), count=None, parser=str, note_valid=True): def lparser(value, pos): + if len(value.strip()) == 0: + # Return an empty list instead of [''] for empty string + parts = [] + else: + parts = [p.strip() for p in value.split(seps[pos])] if pos: # Nested list - parts = [p.strip() for p in value.split(seps[pos])] return tuple([lparser(p, pos - 1) for p in parts if p]) - res = [parser(p.strip()) for p in value.split(seps[pos])] + res = [parser(p) for p in parts] if count is not None and len(res) != count: raise error("Option '%s' in section '%s' must have %d elements" % (option, self.section, count)) diff --git a/klippy/console.py b/klippy/console.py index da32e18b034f..0a20e09e357b 100755 --- a/klippy/console.py +++ b/klippy/console.py @@ -5,7 +5,7 @@ # # This file may be distributed under the terms of the GNU GPLv3 license. import sys, optparse, os, re, logging -import util, reactor, serialhdl, pins, msgproto, clocksync +import util, reactor, serialhdl, msgproto, clocksync help_txt = """ This is a debugging console for the Klipper micro-controller. @@ -43,7 +43,6 @@ def __init__(self, reactor, serialport, baud, canbus_iface, canbus_nodeid): self.fd = sys.stdin.fileno() util.set_nonblock(self.fd) self.mcu_freq = 0 - self.pins = pins.PinResolver(validate_aliases=False) self.data = "" reactor.register_fd(self.fd, self.process_kbd) reactor.register_callback(self.connect) @@ -223,11 +222,7 @@ def translate(self, line, eventtime): return None line = ''.join(evalparts) self.output("Eval: %s" % (line,)) - try: - line = self.pins.update_command(line).strip() - except: - self.output("Unable to map pin: %s" % (line,)) - return None + line = line.strip() if line: parts = line.split() if parts[0] in self.local_commands: diff --git a/klippy/extras/aht10.py b/klippy/extras/aht10.py new file mode 100644 index 000000000000..001f7e54d59a --- /dev/null +++ b/klippy/extras/aht10.py @@ -0,0 +1,162 @@ +# AHT10/AHT20/AHT21 I2c-based humiditure sensor support +# +# Copyright (C) 2023 Scott Mudge +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import logging +from . import bus + +###################################################################### +# Compatible Sensors: +# AHT10 - Tested w/ BTT GTR 1.0 MCU on i2c3 +# AHT20 - Untested but should work +# AHT21 - Tested w/ BTT GTR 1.0 MCU on i2c3 +###################################################################### + +AHT10_I2C_ADDR= 0x38 + +AHT10_COMMANDS = { + 'INIT' :[0xE1, 0x08, 0x00], + 'MEASURE' :[0xAC, 0x33, 0x00], + 'RESET' :[0xBA, 0x08, 0x00] +} + +AHT10_MAX_BUSY_CYCLES= 5 + +class AHT10: + def __init__(self, config): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.reactor = self.printer.get_reactor() + self.i2c = bus.MCU_I2C_from_config( + config, default_addr=AHT10_I2C_ADDR, default_speed=100000) + self.report_time = config.getint('aht10_report_time',30,minval=5) + self.temp = self.min_temp = self.max_temp = self.humidity = 0. + self.sample_timer = self.reactor.register_timer(self._sample_aht10) + self.printer.add_object("aht10 " + self.name, self) + self.printer.register_event_handler("klippy:connect", + self.handle_connect) + self.is_calibrated = False + self.init_sent = False + + def handle_connect(self): + self._init_aht10() + self.reactor.update_timer(self.sample_timer, self.reactor.NOW) + + def setup_minmax(self, min_temp, max_temp): + self.min_temp = min_temp + self.max_temp = max_temp + + def setup_callback(self, cb): + self._callback = cb + + def get_report_time_delta(self): + return self.report_time + + def _make_measurement(self): + if not self.init_sent: + return False + + data = None + + is_busy = True + cycles = 0 + + try: + while is_busy: + # Check if we're constantly busy. If so, send soft-reset + # and issue warning. + if is_busy and cycles > AHT10_MAX_BUSY_CYCLES: + logging.warning("aht10: device reported busy after " + + "%d cycles, resetting device"% AHT10_MAX_BUSY_CYCLES) + self._reset_device() + data = None + break + + cycles += 1 + # Write command for updating temperature+status bit + self.i2c.i2c_write(AHT10_COMMANDS['MEASURE']) + # Wait 110ms after first read, 75ms minimum + self.reactor.pause(self.reactor.monotonic() + .110) + + # Read data + read = self.i2c.i2c_read([], 6) + if read is None: + logging.warning("aht10: received data from" + + " i2c_read is None") + continue + data = bytearray(read['response']) + if len(data) < 6: + logging.warning("aht10: received bytes less than" + + " expected 6 [%d]"%len(data)) + continue + + self.is_calibrated = True if (data[0] & 0b00000100) else False + is_busy = True if (data[0] & 0b01000000) else False + + if is_busy: + return False + except Exception as e: + logging.exception("aht10: exception encountered" + + " reading data: %s"%str(e)) + return False + + temp = ((data[3] & 0x0F) << 16) | (data[4] << 8) | data[5] + self.temp = ((temp*200) / 1048576) - 50 + hum = ((data[1] << 16) | (data[2] << 8) | data[3]) >> 4 + self.humidity = int(hum * 100 / 1048576) + + # Clamp humidity + if (self.humidity > 100): + self.humidity = 100 + elif (self.humidity < 0): + self.humidity = 0 + + return True + + def _reset_device(self): + if not self.init_sent: + return + + # Reset device + self.i2c.i2c_write(AHT10_COMMANDS['RESET']) + # Wait 100ms after reset + self.reactor.pause(self.reactor.monotonic() + .10) + + def _init_aht10(self): + # Init device + self.i2c.i2c_write(AHT10_COMMANDS['INIT']) + # Wait 100ms after init + self.reactor.pause(self.reactor.monotonic() + .10) + self.init_sent = True + + if self._make_measurement(): + logging.info("aht10: successfully initialized, initial temp: " + + "%.3f, humidity: %.3f"%(self.temp, self.humidity)) + + def _sample_aht10(self, eventtime): + if not self._make_measurement(): + self.temp = self.humidity = .0 + return self.reactor.NEVER + + if self.temp < self.min_temp or self.temp > self.max_temp: + self.printer.invoke_shutdown( + "AHT10 temperature %0.1f outside range of %0.1f:%.01f" + % (self.temp, self.min_temp, self.max_temp)) + + measured_time = self.reactor.monotonic() + print_time = self.i2c.get_mcu().estimated_print_time(measured_time) + self._callback(print_time, self.temp) + return measured_time + self.report_time + + def get_status(self, eventtime): + return { + 'temperature': round(self.temp, 2), + 'humidity': self.humidity, + } + + +def load_config(config): + # Register sensor + pheater = config.get_printer().lookup_object("heaters") + pheater.add_sensor_factory("AHT10", AHT10) diff --git a/klippy/extras/angle.py b/klippy/extras/angle.py index d61a76343c33..2e17749e90c7 100644 --- a/klippy/extras/angle.py +++ b/klippy/extras/angle.py @@ -9,7 +9,8 @@ MIN_MSG_TIME = 0.100 TCODE_ERROR = 0xff -TRINAMIC_DRIVERS = ["tmc2130", "tmc2208", "tmc2209", "tmc2660", "tmc5160"] +TRINAMIC_DRIVERS = ["tmc2130", "tmc2208", "tmc2209", "tmc2240", "tmc2660", + "tmc5160"] CALIBRATION_BITS = 6 # 64 entries ANGLE_BITS = 16 # angles range from 0..65535 diff --git a/klippy/extras/bed_mesh.py b/klippy/extras/bed_mesh.py index 0618c97071fa..92c3ac540bd8 100644 --- a/klippy/extras/bed_mesh.py +++ b/klippy/extras/bed_mesh.py @@ -129,7 +129,6 @@ def __init__(self, config): def handle_connect(self): self.toolhead = self.printer.lookup_object('toolhead') self.bmc.print_generated_points(logging.info) - self.pmgr.initialize() def set_mesh(self, mesh): if mesh is not None and self.fade_end != self.FADE_DISABLE: self.log_fade_complete = True @@ -315,7 +314,7 @@ def _generate_points(self, error): # floor distances down to next hundredth x_dist = math.floor(x_dist * 100) / 100 y_dist = math.floor(y_dist * 100) / 100 - if x_dist <= 1. or y_dist <= 1.: + if x_dist < 1. or y_dist < 1.: raise error("bed_mesh: min/max points too close together") if self.radius is not None: @@ -1137,10 +1136,6 @@ def __init__(self, config, bedmesh): self.gcode.register_command( 'BED_MESH_PROFILE', self.cmd_BED_MESH_PROFILE, desc=self.cmd_BED_MESH_PROFILE_help) - def initialize(self): - self._check_incompatible_profiles() - if "default" in self.profiles: - self.load_profile("default") def get_profiles(self): return self.profiles def get_current_profile(self): diff --git a/klippy/extras/endstop_phase.py b/klippy/extras/endstop_phase.py index bd34ddbe44e5..feb9e8b8b082 100644 --- a/klippy/extras/endstop_phase.py +++ b/klippy/extras/endstop_phase.py @@ -6,7 +6,8 @@ import math, logging import stepper -TRINAMIC_DRIVERS = ["tmc2130", "tmc2208", "tmc2209", "tmc2660", "tmc5160"] +TRINAMIC_DRIVERS = ["tmc2130", "tmc2208", "tmc2209", "tmc2240", "tmc2660", + "tmc5160"] # Calculate the trigger phase of a stepper motor class PhaseCalc: diff --git a/klippy/extras/gcode_arcs.py b/klippy/extras/gcode_arcs.py index 61fa723413a1..76c165dd5bca 100644 --- a/klippy/extras/gcode_arcs.py +++ b/klippy/extras/gcode_arcs.py @@ -10,9 +10,22 @@ # Coordinates created by this are converted into G1 commands. # -# note: only IJ version available +# supports XY, XZ & YZ planes with remaining axis as helical + +# Enum +ARC_PLANE_X_Y = 0 +ARC_PLANE_X_Z = 1 +ARC_PLANE_Y_Z = 2 + +# Enum +X_AXIS = 0 +Y_AXIS = 1 +Z_AXIS = 2 +E_AXIS = 3 + class ArcSupport: + def __init__(self, config): self.printer = config.get_printer() self.mm_per_arc_segment = config.getfloat('resolution', 1., above=0.0) @@ -22,12 +35,30 @@ def __init__(self, config): self.gcode.register_command("G2", self.cmd_G2) self.gcode.register_command("G3", self.cmd_G3) + self.gcode.register_command("G17", self.cmd_G17) + self.gcode.register_command("G18", self.cmd_G18) + self.gcode.register_command("G19", self.cmd_G19) + + self.Coord = self.gcode.Coord + + # backwards compatibility, prior implementation only supported XY + self.plane = ARC_PLANE_X_Y + def cmd_G2(self, gcmd): self._cmd_inner(gcmd, True) def cmd_G3(self, gcmd): self._cmd_inner(gcmd, False) + def cmd_G17(self, gcmd): + self.plane = ARC_PLANE_X_Y + + def cmd_G18(self, gcmd): + self.plane = ARC_PLANE_X_Z + + def cmd_G19(self, gcmd): + self.plane = ARC_PLANE_Y_Z + def _cmd_inner(self, gcmd, clockwise): gcodestatus = self.gcode_move.get_status() if not gcodestatus['absolute_coordinates']: @@ -35,21 +66,33 @@ def _cmd_inner(self, gcmd, clockwise): currentPos = gcodestatus['gcode_position'] # Parse parameters - asX = gcmd.get_float("X", currentPos[0]) - asY = gcmd.get_float("Y", currentPos[1]) - asZ = gcmd.get_float("Z", currentPos[2]) + asTarget = self.Coord(x=gcmd.get_float("X", currentPos[0]), + y=gcmd.get_float("Y", currentPos[1]), + z=gcmd.get_float("Z", currentPos[2]), + e=None) + if gcmd.get_float("R", None) is not None: raise gcmd.error("G2/G3 does not support R moves") - asI = gcmd.get_float("I", 0.) - asJ = gcmd.get_float("J", 0.) - if not asI and not asJ: - raise gcmd.error("G2/G3 neither I nor J given") + + # determine the plane coordinates and the helical axis + asPlanar = [ gcmd.get_float(a, 0.) for i,a in enumerate('IJ') ] + axes = (X_AXIS, Y_AXIS, Z_AXIS) + if self.plane == ARC_PLANE_X_Z: + asPlanar = [ gcmd.get_float(a, 0.) for i,a in enumerate('IK') ] + axes = (X_AXIS, Z_AXIS, Y_AXIS) + elif self.plane == ARC_PLANE_Y_Z: + asPlanar = [ gcmd.get_float(a, 0.) for i,a in enumerate('JK') ] + axes = (Y_AXIS, Z_AXIS, X_AXIS) + + if not (asPlanar[0] or asPlanar[1]): + raise gcmd.error("G2/G3 requires IJ, IK or JK parameters") + asE = gcmd.get_float("E", None) asF = gcmd.get_float("F", None) - # Build list of linear coordinates to move to - coords = self.planArc(currentPos, [asX, asY, asZ], [asI, asJ], - clockwise) + # Build list of linear coordinates to move + coords = self.planArc(currentPos, asTarget, asPlanar, + clockwise, *axes) e_per_move = e_base = 0. if asE is not None: if gcodestatus['absolute_extrude']: @@ -74,37 +117,37 @@ def _cmd_inner(self, gcmd, clockwise): # The arc is approximated by generating many small linear segments. # The length of each segment is configured in MM_PER_ARC_SEGMENT # Arcs smaller then this value, will be a Line only - def planArc(self, currentPos, targetPos, offset, clockwise): + # + # alpha and beta axes are the current plane, helical axis is linear travel + def planArc(self, currentPos, targetPos, offset, clockwise, + alpha_axis, beta_axis, helical_axis): # todo: sometimes produces full circles - X_AXIS = 0 - Y_AXIS = 1 - Z_AXIS = 2 # Radius vector from center to current location r_P = -offset[0] r_Q = -offset[1] # Determine angular travel - center_P = currentPos[X_AXIS] - r_P - center_Q = currentPos[Y_AXIS] - r_Q - rt_X = targetPos[X_AXIS] - center_P - rt_Y = targetPos[Y_AXIS] - center_Q - angular_travel = math.atan2(r_P * rt_Y - r_Q * rt_X, - r_P * rt_X + r_Q * rt_Y) + center_P = currentPos[alpha_axis] - r_P + center_Q = currentPos[beta_axis] - r_Q + rt_Alpha = targetPos[alpha_axis] - center_P + rt_Beta = targetPos[beta_axis] - center_Q + angular_travel = math.atan2(r_P * rt_Beta - r_Q * rt_Alpha, + r_P * rt_Alpha + r_Q * rt_Beta) if angular_travel < 0.: angular_travel += 2. * math.pi if clockwise: angular_travel -= 2. * math.pi if (angular_travel == 0. - and currentPos[X_AXIS] == targetPos[X_AXIS] - and currentPos[Y_AXIS] == targetPos[Y_AXIS]): + and currentPos[alpha_axis] == targetPos[alpha_axis] + and currentPos[beta_axis] == targetPos[beta_axis]): # Make a circle if the angular rotation is 0 and the # target is current position angular_travel = 2. * math.pi # Determine number of segments - linear_travel = targetPos[Z_AXIS] - currentPos[Z_AXIS] + linear_travel = targetPos[helical_axis] - currentPos[helical_axis] radius = math.hypot(r_P, r_Q) flat_mm = radius * angular_travel if linear_travel: @@ -118,14 +161,18 @@ def planArc(self, currentPos, targetPos, offset, clockwise): linear_per_segment = linear_travel / segments coords = [] for i in range(1, int(segments)): - dist_Z = i * linear_per_segment + dist_Helical = i * linear_per_segment cos_Ti = math.cos(i * theta_per_segment) sin_Ti = math.sin(i * theta_per_segment) r_P = -offset[0] * cos_Ti + offset[1] * sin_Ti r_Q = -offset[0] * sin_Ti - offset[1] * cos_Ti - c = [center_P + r_P, center_Q + r_Q, currentPos[Z_AXIS] + dist_Z] - coords.append(c) + # Coord doesn't support index assignment, create list + c = [None, None, None, None] + c[alpha_axis] = center_P + r_P + c[beta_axis] = center_Q + r_Q + c[helical_axis] = currentPos[helical_axis] + dist_Helical + coords.append(self.Coord(*c)) coords.append(targetPos) return coords diff --git a/klippy/extras/gcode_macro.py b/klippy/extras/gcode_macro.py index 4f50c75ade02..78cdae0eea3c 100644 --- a/klippy/extras/gcode_macro.py +++ b/klippy/extras/gcode_macro.py @@ -3,7 +3,7 @@ # Copyright (C) 2018-2021 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. -import traceback, logging, ast, copy +import traceback, logging, ast, copy, json import jinja2 @@ -144,12 +144,13 @@ def __init__(self, config): prefix = 'variable_' for option in config.get_prefix_options(prefix): try: - self.variables[option[len(prefix):]] = ast.literal_eval( - config.get(option)) - except ValueError as e: + literal = ast.literal_eval(config.get(option)) + json.dumps(literal, separators=(',', ':')) + self.variables[option[len(prefix):]] = literal + except (SyntaxError, TypeError, ValueError) as e: raise config.error( - "Option '%s' in section '%s' is not a valid literal" % ( - option, config.get_name())) + "Option '%s' in section '%s' is not a valid literal: %s" % ( + option, config.get_name(), e)) def handle_connect(self): prev_cmd = self.gcode.register_command(self.alias, None) if prev_cmd is None: @@ -169,8 +170,10 @@ def cmd_SET_GCODE_VARIABLE(self, gcmd): raise gcmd.error("Unknown gcode_macro variable '%s'" % (variable,)) try: literal = ast.literal_eval(value) - except ValueError as e: - raise gcmd.error("Unable to parse '%s' as a literal" % (value,)) + json.dumps(literal, separators=(',', ':')) + except (SyntaxError, TypeError, ValueError) as e: + raise gcmd.error("Unable to parse '%s' as a literal: %s" % + (value, e)) v = dict(self.variables) v[variable] = literal self.variables = v diff --git a/klippy/extras/manual_probe.py b/klippy/extras/manual_probe.py index c6e9dc64f64b..496455fa0d71 100644 --- a/klippy/extras/manual_probe.py +++ b/klippy/extras/manual_probe.py @@ -13,9 +13,25 @@ def __init__(self, config): self.gcode_move = self.printer.load_object(config, "gcode_move") self.gcode.register_command('MANUAL_PROBE', self.cmd_MANUAL_PROBE, desc=self.cmd_MANUAL_PROBE_help) + # Endstop value for cartesian printers with separate Z axis zconfig = config.getsection('stepper_z') self.z_position_endstop = zconfig.getfloat('position_endstop', None, note_valid=False) + # Endstop values for linear delta printers with vertical A,B,C towers + a_tower_config = config.getsection('stepper_a') + self.a_position_endstop = a_tower_config.getfloat('position_endstop', + None, + note_valid=False) + b_tower_config = config.getsection('stepper_b') + self.b_position_endstop = b_tower_config.getfloat('position_endstop', + None, + note_valid=False) + c_tower_config = config.getsection('stepper_c') + self.c_position_endstop = c_tower_config.getfloat('position_endstop', + None, + note_valid=False) + # Conditionally register appropriate commands depending on printer + # Cartestian printers with separate Z Axis if self.z_position_endstop is not None: self.gcode.register_command( 'Z_ENDSTOP_CALIBRATE', self.cmd_Z_ENDSTOP_CALIBRATE, @@ -24,6 +40,12 @@ def __init__(self, config): 'Z_OFFSET_APPLY_ENDSTOP', self.cmd_Z_OFFSET_APPLY_ENDSTOP, desc=self.cmd_Z_OFFSET_APPLY_ENDSTOP_help) + # Linear delta printers with A,B,C towers + if 'delta' == config.getsection('printer').get('kinematics'): + self.gcode.register_command( + 'Z_OFFSET_APPLY_ENDSTOP', + self.cmd_Z_OFFSET_APPLY_DELTA_ENDSTOPS, + desc=self.cmd_Z_OFFSET_APPLY_ENDSTOP_help) self.reset_status() def manual_probe_finalize(self, kin_pos): if kin_pos is not None: @@ -66,6 +88,29 @@ def cmd_Z_OFFSET_APPLY_ENDSTOP(self,gcmd): "with the above and restart the printer." % (new_calibrate)) configfile.set('stepper_z', 'position_endstop', "%.3f" % (new_calibrate,)) + def cmd_Z_OFFSET_APPLY_DELTA_ENDSTOPS(self,gcmd): + offset = self.gcode_move.get_status()['homing_origin'].z + configfile = self.printer.lookup_object('configfile') + if offset == 0: + self.gcode.respond_info("Nothing to do: Z Offset is 0") + else: + new_a_calibrate = self.a_position_endstop - offset + new_b_calibrate = self.b_position_endstop - offset + new_c_calibrate = self.c_position_endstop - offset + self.gcode.respond_info( + "stepper_a: position_endstop: %.3f\n" + "stepper_b: position_endstop: %.3f\n" + "stepper_c: position_endstop: %.3f\n" + "The SAVE_CONFIG command will update the printer config file\n" + "with the above and restart the printer." % (new_a_calibrate, + new_b_calibrate, + new_c_calibrate)) + configfile.set('stepper_a', 'position_endstop', + "%.3f" % (new_a_calibrate,)) + configfile.set('stepper_b', 'position_endstop', + "%.3f" % (new_b_calibrate,)) + configfile.set('stepper_c', 'position_endstop', + "%.3f" % (new_c_calibrate,)) cmd_Z_OFFSET_APPLY_ENDSTOP_help = "Adjust the z endstop_position" # Verify that a manual probe isn't already in progress diff --git a/klippy/extras/mpu9250.py b/klippy/extras/mpu9250.py index 419207fc4384..dc25449bba7b 100644 --- a/klippy/extras/mpu9250.py +++ b/klippy/extras/mpu9250.py @@ -221,7 +221,7 @@ def _start_measurements(self): systime = self.printer.get_reactor().monotonic() print_time = self.mcu.estimated_print_time(systime) + MIN_MSG_TIME reqclock = self.mcu.print_time_to_clock(print_time) - rest_ticks = self.mcu.seconds_to_clock(1. / self.data_rate) + rest_ticks = self.mcu.seconds_to_clock(4. / self.data_rate) self.query_rate = self.data_rate self.query_mpu9250_cmd.send([self.oid, reqclock, rest_ticks], reqclock=reqclock) diff --git a/klippy/extras/palette2.py b/klippy/extras/palette2.py index c3c43ea693c1..ec8631b0a50e 100644 --- a/klippy/extras/palette2.py +++ b/klippy/extras/palette2.py @@ -221,9 +221,9 @@ def cmd_OmegaDefault(self, gcmd): def _wait_for_heartbeat(self): startTs = self.reactor.monotonic() currTs = startTs - while self.heartbeat is None and self.heartbeat < ( - currTs - SETUP_TIMEOUT) and startTs > ( - currTs - SETUP_TIMEOUT): + while self.heartbeat is None or (self.heartbeat < ( + currTs - SETUP_TIMEOUT) and startTs > ( + currTs - SETUP_TIMEOUT)): currTs = self.reactor.pause(currTs + 1.) if self.heartbeat < (currTs - SETUP_TIMEOUT): @@ -401,7 +401,7 @@ def p2cmd_O50(self, params): try: fw = params[0][1:] logging.info( - "Palette 2 firmware version %s detected" % os.fwalk) + "Palette 2 firmware version %s detected" % fw) except (TypeError, IndexError): logging.error("Unable to parse firmware version") @@ -583,7 +583,7 @@ def _run_Heartbeat(self, eventtime): self.write_queue.put(COMMAND_HEARTBEAT) eventtime = self.reactor.pause(eventtime + 5) if self.heartbeat and self.heartbeat < ( - eventtime - HEARTBEAT_TIMEOUT): + eventtime - HEARTBEAT_TIMEOUT): logging.error( "P2 has not responded to heartbeat") if not self.is_printing or self.is_setup_complete: @@ -612,6 +612,7 @@ def _run_Write(self, eventtime): logging.error("Unable to communicate with the Palette 2") self.signal_disconnect = True return self.reactor.NEVER + return eventtime + SERIAL_TIMER return eventtime + SERIAL_TIMER def _run_Smart_Load(self, eventtime): diff --git a/klippy/extras/probe.py b/klippy/extras/probe.py index 4a32a3001e5d..e9f5ef94f04f 100644 --- a/klippy/extras/probe.py +++ b/klippy/extras/probe.py @@ -195,7 +195,8 @@ def cmd_QUERY_PROBE(self, gcmd): self.last_state = res gcmd.respond_info("probe: %s" % (["open", "TRIGGERED"][not not res],)) def get_status(self, eventtime): - return {'last_query': self.last_state, + return {'name': self.name, + 'last_query': self.last_state, 'last_z_result': self.last_z_result} cmd_PROBE_ACCURACY_help = "Probe Z-height accuracy at current XY position" def cmd_PROBE_ACCURACY(self, gcmd): @@ -362,7 +363,8 @@ def __init__(self, config, finalize_callback, default_points=None): if default_points is None or config.get('points', None) is not None: self.probe_points = config.getlists('points', seps=(',', '\n'), parser=float, count=2) - self.horizontal_move_z = config.getfloat('horizontal_move_z', 5.) + def_move_z = config.getfloat('horizontal_move_z', 5.) + self.default_horizontal_move_z = def_move_z self.speed = config.getfloat('speed', 50., above=0.) self.use_offsets = False # Internal probing state @@ -408,6 +410,9 @@ def start_probe(self, gcmd): probe = self.printer.lookup_object('probe', None) method = gcmd.get('METHOD', 'automatic').lower() self.results = [] + def_move_z = self.default_horizontal_move_z + self.horizontal_move_z = gcmd.get_float('HORIZONTAL_MOVE_Z', + def_move_z) if probe is None or method != 'automatic': # Manual probe self.lift_speed = self.speed diff --git a/klippy/extras/replicape.py b/klippy/extras/replicape.py index 0f5bef0eeb1b..4c3762974654 100644 --- a/klippy/extras/replicape.py +++ b/klippy/extras/replicape.py @@ -21,6 +21,7 @@ def __init__(self, replicape, channel, pin_type, pin_params): raise pins.error("Pin type not supported on replicape") self._mcu = replicape.host_mcu self._mcu.register_config_callback(self._build_config) + self._reactor = self._mcu.get_printer().get_reactor() self._bus = REPLICAPE_PCA9685_BUS self._address = REPLICAPE_PCA9685_ADDRESS self._cycle_time = REPLICAPE_PCA9685_CYCLE_TIME @@ -28,6 +29,7 @@ def __init__(self, replicape, channel, pin_type, pin_params): self._oid = None self._invert = pin_params['invert'] self._start_value = self._shutdown_value = float(self._invert) + self._is_enable = not not self._start_value self._is_static = False self._last_clock = 0 self._pwm_max = 0. @@ -53,6 +55,7 @@ def setup_start_value(self, start_value, shutdown_value, is_static=False): self._is_static = is_static self._replicape.note_pwm_start_value( self._channel, self._start_value, self._shutdown_value) + self._is_enable = not not self._start_value def _build_config(self): self._pwm_max = self._mcu.get_constant_float("PCA9685_MAX") cycle_ticks = self._mcu.seconds_to_clock(self._cycle_time) @@ -80,7 +83,12 @@ def set_pwm(self, print_time, value, cycle_time=None): if self._invert: value = 1. - value value = int(max(0., min(1., value)) * self._pwm_max + 0.5) - self._replicape.note_pwm_enable(print_time, self._channel, value) + is_enable = not not value + if is_enable != self._is_enable: + self._is_enable = is_enable + self._reactor.register_async_callback( + (lambda e, s=self, pt=print_time, ie=is_enable: + s._replicape.note_pwm_enable(pt, s._channel, ie))) self._set_cmd.send([self._oid, clock, value], minclock=self._last_clock, reqclock=clock) self._last_clock = clock @@ -148,7 +156,7 @@ def __init__(self, replicape, pin_params): pin_resolver.reserve_pin(resv1, config_name) pin_resolver.reserve_pin(resv2, config_name) def setup_cycle_time(self, cycle_time, hardware_pwm=False): - self.mcu_pwm.setup_cycle_time(cycle_time, True); + self.mcu_pwm.setup_cycle_time(cycle_time, True) ReplicapeStepConfig = { 'disable': None, @@ -171,6 +179,7 @@ def __init__(self, config): self.mcu_pwm_enable = ppins.setup_pin('digital_out', enable_pin) self.mcu_pwm_enable.setup_max_duration(0.) self.mcu_pwm_start_value = self.mcu_pwm_shutdown_value = False + self.last_pwm_enable_time = 0. # Setup power pins self.pins = { "power_e": (pca9685_pwm, 5), "power_h": (pca9685_pwm, 3), @@ -180,7 +189,6 @@ def __init__(self, config): self.servo_pins = { "servo0": 3, "servo1": 2 } # Setup stepper config - self.last_stepper_time = 0. self.stepper_dacs = {} shift_registers = [1, 0, 0, 1, 1] for port, name in enumerate('xyzeh'): @@ -227,18 +235,17 @@ def note_pwm_start_value(self, channel, start_value, shutdown_value): self.mcu_pwm_enable.setup_start_value( self.mcu_pwm_start_value, self.mcu_pwm_shutdown_value) self.enabled_channels[channel] = not not start_value - def note_pwm_enable(self, print_time, channel, value): - is_enable = not not value - if self.enabled_channels[channel] == is_enable: - # Nothing to do - return + def note_pwm_enable(self, print_time, channel, is_enable): self.enabled_channels[channel] = is_enable # Check if need to set the pca9685 enable pin + pe_time = max(print_time, self.last_pwm_enable_time + PIN_MIN_TIME) on_channels = [1 for c, e in self.enabled_channels.items() if e] if not on_channels: - self.mcu_pwm_enable.set_digital(print_time, 0) + self.mcu_pwm_enable.set_digital(pe_time, 0) + self.last_pwm_enable_time = pe_time elif is_enable and len(on_channels) == 1: - self.mcu_pwm_enable.set_digital(print_time, 1) + self.mcu_pwm_enable.set_digital(pe_time, 1) + self.last_pwm_enable_time = pe_time # Check if need to set the stepper enable lines if channel not in self.stepper_dacs: return @@ -250,7 +257,6 @@ def note_pwm_enable(self, print_time, channel, value): sr = self.sr_enabled else: return - print_time = max(print_time, self.last_stepper_time + PIN_MIN_TIME) clock = self.host_mcu.print_time_to_clock(print_time) self.sr_spi.spi_send(sr, minclock=clock, reqclock=clock) def setup_pin(self, pin_type, pin_params): diff --git a/klippy/extras/save_variables.py b/klippy/extras/save_variables.py index 8cb949fe151a..6cedcf4664ce 100644 --- a/klippy/extras/save_variables.py +++ b/klippy/extras/save_variables.py @@ -12,6 +12,8 @@ def __init__(self, config): self.filename = os.path.expanduser(config.get('filename')) self.allVariables = {} try: + if not os.path.exists(self.filename): + open(self.filename, "w").close() self.loadVariables() except self.printer.command_error as e: raise config.error(str(e)) diff --git a/klippy/extras/screws_tilt_adjust.py b/klippy/extras/screws_tilt_adjust.py index 1bb599ed3376..5698f0bd9035 100644 --- a/klippy/extras/screws_tilt_adjust.py +++ b/klippy/extras/screws_tilt_adjust.py @@ -12,7 +12,9 @@ def __init__(self, config): self.config = config self.printer = config.get_printer() self.screws = [] + self.results = [] self.max_diff = None + self.max_diff_error = False # Read config for i in range(99): prefix = "screw%d" % (i + 1,) @@ -57,7 +59,13 @@ def cmd_SCREWS_TILT_CALCULATE(self, gcmd): self.direction = direction self.probe_helper.start_probe(gcmd) + def get_status(self, eventtime): + return {'error': self.max_diff_error, + 'results': self.results} + def probe_finalize(self, offsets, positions): + self.results = {} + self.max_diff_error = False # Factors used for CW-M3, CCW-M3, CW-M4, CCW-M4, CW-M5 and CCW-M5 threads_factor = {0: 0.5, 1: 0.5, 2: 0.7, 3: 0.7, 4: 0.8, 5: 0.8} is_clockwise_thread = (self.thread & 1) == 0 @@ -84,6 +92,9 @@ def probe_finalize(self, offsets, positions): self.gcode.respond_info( "%s : x=%.1f, y=%.1f, z=%.5f" % (name + ' (base)', coord[0], coord[1], z)) + sign = "CW" if is_clockwise_thread else "CCW" + self.results["screw%d" % (i + 1,)] = {'z': z, 'sign': sign, + 'adjust': '00:00', 'is_base': True} else: # Calculate how knob must be adjusted for other positions diff = z_base - z @@ -104,7 +115,11 @@ def probe_finalize(self, offsets, positions): self.gcode.respond_info( "%s : x=%.1f, y=%.1f, z=%.5f : adjust %s %02d:%02d" % (name, coord[0], coord[1], z, sign, full_turns, minutes)) + self.results["screw%d" % (i + 1,)] = {'z': z, 'sign': sign, + 'adjust':"%02d:%02d" % (full_turns, minutes), + 'is_base': False} if self.max_diff and any((d > self.max_diff) for d in screw_diff): + self.max_diff_error = True raise self.gcode.error( "bed level exceeds configured limits ({}mm)! " \ "Adjust screws and restart print.".format(self.max_diff)) diff --git a/klippy/extras/stepper_enable.py b/klippy/extras/stepper_enable.py index e8b41c0afda0..621ff700e2ac 100644 --- a/klippy/extras/stepper_enable.py +++ b/klippy/extras/stepper_enable.py @@ -108,6 +108,10 @@ def motor_debug_enable(self, stepper, enable): el.motor_disable(print_time) logging.info("%s has been manually disabled", stepper) toolhead.dwell(DISABLE_STALL_TIME) + def get_status(self, eventtime): + steppers = { name: et.is_motor_enabled() + for (name, et) in self.enable_lines.items() } + return {'steppers': steppers} def _handle_request_restart(self, print_time): self.motor_off() def cmd_M18(self, gcmd): diff --git a/klippy/extras/temperature_mcu.py b/klippy/extras/temperature_mcu.py index f35e97288bac..585ec4c1d20d 100644 --- a/klippy/extras/temperature_mcu.py +++ b/klippy/extras/temperature_mcu.py @@ -72,7 +72,9 @@ def _mcu_identify(self): ('stm32f070', self.config_stm32f070), ('stm32f072', self.config_stm32f0x2), ('stm32g0', self.config_stm32g0), + ('stm32g4', self.config_stm32g0), ('stm32l4', self.config_stm32g0), + ('stm32h723', self.config_stm32h723), ('stm32h7', self.config_stm32h7), ('', self.config_unknown)] for name, func in cfg_funcs: @@ -145,6 +147,11 @@ def config_stm32g0(self): cal_adc_130 = self.read16(0x1FFF75CA) * 3.0 / (3.3 * 4095.) self.slope = (130. - 30.) / (cal_adc_130 - cal_adc_30) self.base_temperature = self.calc_base(30., cal_adc_30) + def config_stm32h723(self): + cal_adc_30 = self.read16(0x1FF1E820) / 4095. + cal_adc_130 = self.read16(0x1FF1E840) / 4095. + self.slope = (130. - 30.) / (cal_adc_130 - cal_adc_30) + self.base_temperature = self.calc_base(30., cal_adc_30) def config_stm32h7(self): cal_adc_30 = self.read16(0x1FF1E820) / 65535. cal_adc_110 = self.read16(0x1FF1E840) / 65535. diff --git a/klippy/extras/temperature_sensors.cfg b/klippy/extras/temperature_sensors.cfg index ebee3089979d..7e0d918f5b8a 100644 --- a/klippy/extras/temperature_sensors.cfg +++ b/klippy/extras/temperature_sensors.cfg @@ -18,6 +18,9 @@ # Load "SI7013", "SI7020", "SI7021", "SHT21", and "HTU21D" sensors [htu21d] +# Load "AHT10" +[aht10] + # Load "LM75" sensor [lm75] diff --git a/klippy/extras/tmc.py b/klippy/extras/tmc.py index df3c705bd840..28f7be6fc01f 100644 --- a/klippy/extras/tmc.py +++ b/klippy/extras/tmc.py @@ -93,7 +93,7 @@ def __init__(self, config, mcu_tmc): self.mcu_tmc = mcu_tmc self.fields = mcu_tmc.get_fields() self.check_timer = None - self.last_drv_status = self.last_status = None + self.last_drv_status = self.last_drv_fields = None # Setup for GSTAT query reg_name = self.fields.lookup_register("drv_err") if reg_name is not None: @@ -122,6 +122,9 @@ def __init__(self, config, mcu_tmc): if f in err_fields: err_mask |= self.fields.all_fields[reg_name][f] self.drv_status_reg_info = [0, reg_name, mask, err_mask, cs_actual_mask] + # Setup for temperature query + self.adc_temp = None + self.adc_temp_reg = self.fields.lookup_register("adc_temp") def _query_register(self, reg_info, try_clear=False): last_value, reg_name, mask, err_mask, cs_actual_mask = reg_info cleared_flags = 0 @@ -161,11 +164,20 @@ def _query_register(self, reg_info, try_clear=False): cleared_flags |= val & err_mask self.mcu_tmc.set_register(reg_name, val & err_mask) return cleared_flags + def _query_temperature(self): + try: + self.adc_temp = self.mcu_tmc.get_register(self.adc_temp_reg) + except self.printer.command_error as e: + # Ignore comms error for temperature + self.adc_temp = None + return def _do_periodic_check(self, eventtime): try: self._query_register(self.drv_status_reg_info) if self.gstat_reg_info is not None: self._query_register(self.gstat_reg_info) + if self.adc_temp_reg is not None: + self._query_temperature() except self.printer.command_error as e: self.printer.invoke_shutdown(str(e)) return self.printer.get_reactor().NEVER @@ -194,14 +206,16 @@ def start_checks(self): return False def get_status(self, eventtime=None): if self.check_timer is None: - return {'drv_status': None} + return {'drv_status': None, 'temperature': None} + temp = None + if self.adc_temp is not None: + temp = round((self.adc_temp - 2038) / 7.7, 2) last_value, reg_name = self.drv_status_reg_info[:2] if last_value != self.last_drv_status: self.last_drv_status = last_value fields = self.fields.get_reg_fields(reg_name, last_value) - fields = {n: v for n, v in fields.items() if v} - self.last_status = {'drv_status': fields} - return self.last_status + self.last_drv_fields = {n: v for n, v in fields.items() if v} + return {'drv_status': self.last_drv_fields, 'temperature': temp} ###################################################################### @@ -258,7 +272,18 @@ def cmd_SET_TMC_FIELD(self, gcmd): reg_name = self.fields.lookup_register(field_name, None) if reg_name is None: raise gcmd.error("Unknown field name '%s'" % (field_name,)) - value = gcmd.get_int('VALUE') + value = gcmd.get_int('VALUE', None) + velocity = gcmd.get_float('VELOCITY', None, minval=0.) + tmc_frequency = self.mcu_tmc.get_tmc_frequency() + if tmc_frequency is None and velocity is not None: + raise gcmd.error("VELOCITY parameter not supported by this driver") + if (value is None) == (velocity is None): + raise gcmd.error("Specify either VALUE or VELOCITY") + if velocity is not None: + step_dist = self.stepper.get_step_dist() + mres = self.fields.get_field("mres") + value = TMCtstepHelper(step_dist, mres, tmc_frequency, + velocity) reg_val = self.fields.set_field(field_name, value) print_time = self.printer.lookup_object('toolhead').get_last_move_time() self.mcu_tmc.set_register(reg_name, reg_val, print_time) @@ -402,17 +427,32 @@ def setup_register_dump(self, read_registers, read_translate=None): cmd_DUMP_TMC_help = "Read and display TMC stepper driver registers" def cmd_DUMP_TMC(self, gcmd): logging.info("DUMP_TMC %s", self.name) - print_time = self.printer.lookup_object('toolhead').get_last_move_time() - gcmd.respond_info("========== Write-only registers ==========") - for reg_name, val in self.fields.registers.items(): - if reg_name not in self.read_registers: + reg_name = gcmd.get('REGISTER', None) + if reg_name is not None: + reg_name = reg_name.upper() + val = self.fields.registers.get(reg_name) + if (val is not None) and (reg_name not in self.read_registers): + # write-only register + gcmd.respond_info(self.fields.pretty_format(reg_name, val)) + elif reg_name in self.read_registers: + # readable register + val = self.mcu_tmc.get_register(reg_name) + if self.read_translate is not None: + reg_name, val = self.read_translate(reg_name, val) + gcmd.respond_info(self.fields.pretty_format(reg_name, val)) + else: + raise gcmd.error("Unknown register name '%s'" % (reg_name)) + else: + gcmd.respond_info("========== Write-only registers ==========") + for reg_name, val in self.fields.registers.items(): + if reg_name not in self.read_registers: + gcmd.respond_info(self.fields.pretty_format(reg_name, val)) + gcmd.respond_info("========== Queried registers ==========") + for reg_name in self.read_registers: + val = self.mcu_tmc.get_register(reg_name) + if self.read_translate is not None: + reg_name, val = self.read_translate(reg_name, val) gcmd.respond_info(self.fields.pretty_format(reg_name, val)) - gcmd.respond_info("========== Queried registers ==========") - for reg_name in self.read_registers: - val = self.mcu_tmc.get_register(reg_name) - if self.read_translate is not None: - reg_name, val = self.read_translate(reg_name, val) - gcmd.respond_info(self.fields.pretty_format(reg_name, val)) ###################################################################### @@ -437,7 +477,7 @@ def __init__(self, config, mcu_tmc): self.diag_pin_field = None self.mcu_endstop = None self.en_pwm = False - self.pwmthrs = 0 + self.pwmthrs = self.coolthrs = 0 # Register virtual_endstop pin name_parts = config.get_name().split() ppins = self.printer.lookup_object("pins") @@ -452,13 +492,6 @@ def setup_pin(self, pin_type, pin_params): if self.diag_pin is None: raise ppins.error("tmc virtual endstop requires diag pin config") # Setup for sensorless homing - reg = self.fields.lookup_register("en_pwm_mode", None) - if reg is None: - self.en_pwm = not self.fields.get_field("en_spreadcycle") - self.pwmthrs = self.fields.get_field("tpwmthrs") - else: - self.en_pwm = self.fields.get_field("en_pwm_mode") - self.pwmthrs = 0 self.printer.register_event_handler("homing:homing_move_begin", self.handle_homing_move_begin) self.printer.register_event_handler("homing:homing_move_end", @@ -468,19 +501,24 @@ def setup_pin(self, pin_type, pin_params): def handle_homing_move_begin(self, hmove): if self.mcu_endstop not in hmove.get_mcu_endstops(): return + self.pwmthrs = self.fields.get_field("tpwmthrs") + self.coolthrs = self.fields.get_field("tcoolthrs") reg = self.fields.lookup_register("en_pwm_mode", None) if reg is None: # On "stallguard4" drivers, "stealthchop" must be enabled + self.en_pwm = not self.fields.get_field("en_spreadcycle") tp_val = self.fields.set_field("tpwmthrs", 0) self.mcu_tmc.set_register("TPWMTHRS", tp_val) val = self.fields.set_field("en_spreadcycle", 0) else: # On earlier drivers, "stealthchop" must be disabled + self.en_pwm = self.fields.get_field("en_pwm_mode") self.fields.set_field("en_pwm_mode", 0) val = self.fields.set_field(self.diag_pin_field, 1) self.mcu_tmc.set_register("GCONF", val) - tc_val = self.fields.set_field("tcoolthrs", 0xfffff) - self.mcu_tmc.set_register("TCOOLTHRS", tc_val) + if self.coolthrs == 0: + tc_val = self.fields.set_field("tcoolthrs", 0xfffff) + self.mcu_tmc.set_register("TCOOLTHRS", tc_val) def handle_homing_move_end(self, hmove): if self.mcu_endstop not in hmove.get_mcu_endstops(): return @@ -493,7 +531,7 @@ def handle_homing_move_end(self, hmove): self.fields.set_field("en_pwm_mode", self.en_pwm) val = self.fields.set_field(self.diag_pin_field, 0) self.mcu_tmc.set_register("GCONF", val) - tc_val = self.fields.set_field("tcoolthrs", 0) + tc_val = self.fields.set_field("tcoolthrs", self.coolthrs) self.mcu_tmc.set_register("TCOOLTHRS", tc_val) @@ -501,6 +539,27 @@ def handle_homing_move_end(self, hmove): # Config reading helpers ###################################################################### +# Helper to initialize the wave table from config or defaults +def TMCWaveTableHelper(config, mcu_tmc): + set_config_field = mcu_tmc.get_fields().set_config_field + set_config_field(config, "mslut0", 0xAAAAB554) + set_config_field(config, "mslut1", 0x4A9554AA) + set_config_field(config, "mslut2", 0x24492929) + set_config_field(config, "mslut3", 0x10104222) + set_config_field(config, "mslut4", 0xFBFFFFFF) + set_config_field(config, "mslut5", 0xB5BB777D) + set_config_field(config, "mslut6", 0x49295556) + set_config_field(config, "mslut7", 0x00404222) + set_config_field(config, "w0", 2) + set_config_field(config, "w1", 1) + set_config_field(config, "w2", 1) + set_config_field(config, "w3", 1) + set_config_field(config, "x1", 128) + set_config_field(config, "x2", 255) + set_config_field(config, "x3", 255) + set_config_field(config, "start_sin", 0) + set_config_field(config, "start_sin90", 247) + # Helper to configure and query the microstep settings def TMCMicrostepHelper(config, mcu_tmc): fields = mcu_tmc.get_fields() @@ -519,20 +578,33 @@ def TMCMicrostepHelper(config, mcu_tmc): fields.set_field("mres", mres) fields.set_field("intpol", config.getboolean("interpolate", True)) -# Helper to configure "stealthchop" mode +# Helper for calculating TSTEP based values from velocity +def TMCtstepHelper(step_dist, mres, tmc_freq, velocity): + if velocity > 0.: + step_dist_256 = step_dist / (1 << mres) + threshold = int(tmc_freq * step_dist_256 / velocity + .5) + return max(0, min(0xfffff, threshold)) + else: + return 0xfffff + +# Helper to configure stealthChop-spreadCycle transition velocity def TMCStealthchopHelper(config, mcu_tmc, tmc_freq): fields = mcu_tmc.get_fields() en_pwm_mode = False - velocity = config.getfloat('stealthchop_threshold', 0., minval=0.) - if velocity: + velocity = config.getfloat('stealthchop_threshold', None, minval=0.) + tpwmthrs = 0xfffff + + if velocity is not None: + en_pwm_mode = True + stepper_name = " ".join(config.get_name().split()[1:]) sconfig = config.getsection(stepper_name) rotation_dist, steps_per_rotation = stepper.parse_step_distance(sconfig) step_dist = rotation_dist / steps_per_rotation - step_dist_256 = step_dist / (1 << fields.get_field("mres")) - threshold = int(tmc_freq * step_dist_256 / velocity + .5) - fields.set_field("tpwmthrs", max(0, min(0xfffff, threshold))) - en_pwm_mode = True + mres = fields.get_field("mres") + tpwmthrs = TMCtstepHelper(step_dist, mres, tmc_freq, velocity) + fields.set_field("tpwmthrs", tpwmthrs) + reg = fields.lookup_register("en_pwm_mode", None) if reg is not None: fields.set_field("en_pwm_mode", en_pwm_mode) diff --git a/klippy/extras/tmc2130.py b/klippy/extras/tmc2130.py index f2142d26fd0f..62a9abbfe56b 100644 --- a/klippy/extras/tmc2130.py +++ b/klippy/extras/tmc2130.py @@ -11,10 +11,12 @@ Registers = { "GCONF": 0x00, "GSTAT": 0x01, "IOIN": 0x04, "IHOLD_IRUN": 0x10, "TPOWERDOWN": 0x11, "TSTEP": 0x12, "TPWMTHRS": 0x13, "TCOOLTHRS": 0x14, - "THIGH": 0x15, "XDIRECT": 0x2d, "MSLUT0": 0x60, "MSLUTSEL": 0x68, - "MSLUTSTART": 0x69, "MSCNT": 0x6a, "MSCURACT": 0x6b, "CHOPCONF": 0x6c, - "COOLCONF": 0x6d, "DCCTRL": 0x6e, "DRV_STATUS": 0x6f, "PWMCONF": 0x70, - "PWM_SCALE": 0x71, "ENCM_CTRL": 0x72, "LOST_STEPS": 0x73, + "THIGH": 0x15, "XDIRECT": 0x2d, "MSLUT0": 0x60, "MSLUT1": 0x61, + "MSLUT2": 0x62, "MSLUT3": 0x63, "MSLUT4": 0x64, "MSLUT5": 0x65, + "MSLUT6": 0x66, "MSLUT7": 0x67, "MSLUTSEL": 0x68, "MSLUTSTART": 0x69, + "MSCNT": 0x6a, "MSCURACT": 0x6b, "CHOPCONF": 0x6c, "COOLCONF": 0x6d, + "DCCTRL": 0x6e, "DRV_STATUS": 0x6f, "PWMCONF": 0x70, "PWM_SCALE": 0x71, + "ENCM_CTRL": 0x72, "LOST_STEPS": 0x73, } ReadRegisters = [ @@ -45,6 +47,27 @@ Fields["TPWMTHRS"] = { "tpwmthrs": 0xfffff } Fields["TCOOLTHRS"] = { "tcoolthrs": 0xfffff } Fields["THIGH"] = { "thigh": 0xfffff } +Fields["MSLUT0"] = { "mslut0": 0xffffffff } +Fields["MSLUT1"] = { "mslut1": 0xffffffff } +Fields["MSLUT2"] = { "mslut2": 0xffffffff } +Fields["MSLUT3"] = { "mslut3": 0xffffffff } +Fields["MSLUT4"] = { "mslut4": 0xffffffff } +Fields["MSLUT5"] = { "mslut5": 0xffffffff } +Fields["MSLUT6"] = { "mslut6": 0xffffffff } +Fields["MSLUT7"] = { "mslut7": 0xffffffff } +Fields["MSLUTSEL"] = { + "x3": 0xFF << 24, + "x2": 0xFF << 16, + "x1": 0xFF << 8, + "w3": 0x03 << 6, + "w2": 0x03 << 4, + "w1": 0x03 << 2, + "w0": 0x03 << 0, +} +Fields["MSLUTSTART"] = { + "start_sin": 0xFF << 0, + "start_sin90": 0xFF << 16, +} Fields["MSCNT"] = { "mscnt": 0x3ff } Fields["MSCURACT"] = { "cur_a": 0x1ff, "cur_b": 0x1ff << 16 } Fields["CHOPCONF"] = { @@ -225,13 +248,14 @@ def lookup_tmc_spi_chain(config): # Helper code for working with TMC devices via SPI class MCU_TMC_SPI: - def __init__(self, config, name_to_reg, fields): + def __init__(self, config, name_to_reg, fields, tmc_frequency): self.printer = config.get_printer() self.name = config.get_name().split()[-1] self.tmc_spi, self.chain_pos = lookup_tmc_spi_chain(config) self.mutex = self.tmc_spi.mutex self.name_to_reg = name_to_reg self.fields = fields + self.tmc_frequency = tmc_frequency def get_fields(self): return self.fields def get_register(self, reg_name): @@ -248,6 +272,8 @@ def set_register(self, reg_name, val, print_time=None): return raise self.printer.command_error( "Unable to write tmc spi '%s' register %s" % (self.name, reg_name)) + def get_tmc_frequency(self): + return self.tmc_frequency ###################################################################### @@ -258,7 +284,8 @@ class TMC2130: def __init__(self, config): # Setup mcu communication self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = MCU_TMC_SPI(config, Registers, self.fields) + self.mcu_tmc = MCU_TMC_SPI(config, Registers, self.fields, + TMC_FREQUENCY) # Allow virtual pins to be created tmc.TMCVirtualPinHelper(config, self.mcu_tmc) # Register commands @@ -268,20 +295,26 @@ def __init__(self, config): self.get_phase_offset = cmdhelper.get_phase_offset self.get_status = cmdhelper.get_status # Setup basic register values + tmc.TMCWaveTableHelper(config, self.mcu_tmc) tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) # Allow other registers to be set from the config set_config_field = self.fields.set_config_field + # CHOPCONF set_config_field(config, "toff", 4) set_config_field(config, "hstrt", 0) set_config_field(config, "hend", 7) set_config_field(config, "tbl", 1) + # COOLCONF + set_config_field(config, "sgt", 0) + # IHOLDIRUN set_config_field(config, "iholddelay", 8) - set_config_field(config, "tpowerdown", 0) + # PWMCONF set_config_field(config, "pwm_ampl", 128) set_config_field(config, "pwm_grad", 4) set_config_field(config, "pwm_freq", 1) set_config_field(config, "pwm_autoscale", True) - set_config_field(config, "sgt", 0) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 0) def load_config_prefix(config): return TMC2130(config) diff --git a/klippy/extras/tmc2208.py b/klippy/extras/tmc2208.py index 1b5968a91d35..bedf8092c667 100644 --- a/klippy/extras/tmc2208.py +++ b/klippy/extras/tmc2208.py @@ -173,8 +173,8 @@ FieldFormatters = dict(tmc2130.FieldFormatters) FieldFormatters.update({ "sel_a": (lambda v: "%d(%s)" % (v, ["TMC222x", "TMC220x"][v])), - "s2vsa": (lambda v: "1(LowSideShort_A!)" if v else ""), - "s2vsb": (lambda v: "1(LowSideShort_B!)" if v else ""), + "s2vsa": (lambda v: "1(ShortToSupply_A!)" if v else ""), + "s2vsb": (lambda v: "1(ShortToSupply_B!)" if v else ""), }) @@ -186,7 +186,8 @@ class TMC2208: def __init__(self, config): # Setup mcu communication self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields) + self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 0, + TMC_FREQUENCY) self.fields.set_field("pdn_disable", True) # Register commands current_helper = tmc2130.TMCCurrentHelper(config, self.mcu_tmc) @@ -200,12 +201,14 @@ def __init__(self, config): tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) # Allow other registers to be set from the config set_config_field = self.fields.set_config_field + # CHOPCONF set_config_field(config, "toff", 3) set_config_field(config, "hstrt", 5) set_config_field(config, "hend", 0) set_config_field(config, "tbl", 2) + # IHOLDIRUN set_config_field(config, "iholddelay", 8) - set_config_field(config, "tpowerdown", 20) + # PWMCONF set_config_field(config, "pwm_ofs", 36) set_config_field(config, "pwm_grad", 14) set_config_field(config, "pwm_freq", 1) @@ -213,6 +216,8 @@ def __init__(self, config): set_config_field(config, "pwm_autograd", True) set_config_field(config, "pwm_reg", 8) set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 20) def read_translate(self, reg_name, val): if reg_name == "IOIN": drv_type = self.fields.get_field("sel_a", val) diff --git a/klippy/extras/tmc2209.py b/klippy/extras/tmc2209.py index 64bf195be3d2..1afa280ce704 100644 --- a/klippy/extras/tmc2209.py +++ b/klippy/extras/tmc2209.py @@ -58,7 +58,8 @@ def __init__(self, config): # Setup mcu communication self.fields = tmc.FieldHelper(Fields, tmc2208.SignedFields, FieldFormatters) - self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 3) + self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 3, + TMC_FREQUENCY) # Setup fields for UART self.fields.set_field("pdn_disable", True) self.fields.set_field("senddelay", 2) # Avoid tx errors on shared uart @@ -71,18 +72,19 @@ def __init__(self, config): self.get_phase_offset = cmdhelper.get_phase_offset self.get_status = cmdhelper.get_status # Setup basic register values - self.fields.set_field("pdn_disable", True) self.fields.set_field("mstep_reg_select", True) self.fields.set_field("multistep_filt", True) tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) # Allow other registers to be set from the config set_config_field = self.fields.set_config_field + # CHOPCONF set_config_field(config, "toff", 3) set_config_field(config, "hstrt", 5) set_config_field(config, "hend", 0) set_config_field(config, "tbl", 2) + # IHOLDIRUN set_config_field(config, "iholddelay", 8) - set_config_field(config, "tpowerdown", 20) + # PWMCONF set_config_field(config, "pwm_ofs", 36) set_config_field(config, "pwm_grad", 14) set_config_field(config, "pwm_freq", 1) @@ -90,6 +92,9 @@ def __init__(self, config): set_config_field(config, "pwm_autograd", True) set_config_field(config, "pwm_reg", 8) set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 20) + # SGTHRS set_config_field(config, "sgthrs", 0) def load_config_prefix(config): diff --git a/klippy/extras/tmc2240.py b/klippy/extras/tmc2240.py new file mode 100644 index 000000000000..45482509915a --- /dev/null +++ b/klippy/extras/tmc2240.py @@ -0,0 +1,401 @@ +# TMC2240 configuration +# +# Copyright (C) 2018-2023 Kevin O'Connor +# Copyright (C) 2023 Alex Voinea +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import math, logging +from . import bus, tmc, tmc2130 + +TMC_FREQUENCY=12500000. + +Registers = { + "GCONF": 0x00, + "GSTAT": 0x01, + "IFCNT": 0x02, + "NODECONF": 0x03, + "IOIN": 0x04, + "DRV_CONF": 0x0A, + "GLOBALSCALER": 0x0B, + "IHOLD_IRUN": 0x10, + "TPOWERDOWN": 0x11, + "TSTEP": 0x12, + "TPWMTHRS": 0x13, + "TCOOLTHRS": 0x14, + "THIGH": 0x15, + "DIRECT_MODE": 0x2D, + "ENCMODE": 0x38, + "X_ENC": 0x39, + "ENC_CONST": 0x3A, + "ENC_STATUS": 0x3B, + "ENC_LATCH": 0x3C, + "ADC_VSUPPLY_AIN": 0x50, + "ADC_TEMP": 0x51, + "OTW_OV_VTH": 0x52, + "MSLUT0": 0x60, + "MSLUT1": 0x61, + "MSLUT2": 0x62, + "MSLUT3": 0x63, + "MSLUT4": 0x64, + "MSLUT5": 0x65, + "MSLUT6": 0x66, + "MSLUT7": 0x67, + "MSLUTSEL": 0x68, + "MSLUTSTART": 0x69, + "MSCNT": 0x6A, + "MSCURACT": 0x6B, + "CHOPCONF": 0x6C, + "COOLCONF": 0x6D, + "DRV_STATUS": 0x6F, + "PWMCONF": 0x70, + "PWM_SCALE": 0x71, + "PWM_AUTO": 0x72, + "SG4_THRS": 0x74, + "SG4_RESULT": 0x75, + "SG4_IND": 0x76, +} + +ReadRegisters = [ + "GCONF", "GSTAT", "IOIN", "DRV_CONF", "GLOBALSCALER", "IHOLD_IRUN", + "TPOWERDOWN", "TSTEP", "TPWMTHRS", "TCOOLTHRS", "THIGH", "ADC_VSUPPLY_AIN", + "ADC_TEMP", "MSCNT", "MSCURACT", "CHOPCONF", "COOLCONF", "DRV_STATUS", + "PWMCONF", "PWM_SCALE", "PWM_AUTO", "SG4_THRS", "SG4_RESULT", "SG4_IND" +] + +Fields = {} +Fields["COOLCONF"] = { + "semin": 0x0F << 0, + "seup": 0x03 << 5, + "semax": 0x0F << 8, + "sedn": 0x03 << 13, + "seimin": 0x01 << 15, + "sgt": 0x7F << 16, + "sfilt": 0x01 << 24 +} +Fields["CHOPCONF"] = { + "toff": 0x0F << 0, + "hstrt": 0x07 << 4, + "hend": 0x0F << 7, + "fd3": 0x01 << 11, + "disfdcc": 0x01 << 12, + "chm": 0x01 << 14, + "tbl": 0x03 << 15, + "vhighfs": 0x01 << 18, + "vhighchm": 0x01 << 19, + "tpfd": 0x0F << 20, # midrange resonances + "mres": 0x0F << 24, + "intpol": 0x01 << 28, + "dedge": 0x01 << 29, + "diss2g": 0x01 << 30, + "diss2vs": 0x01 << 31 +} +Fields["DRV_STATUS"] = { + "sg_result": 0x3FF << 0, + "s2vsa": 0x01 << 12, + "s2vsb": 0x01 << 13, + "stealth": 0x01 << 14, + "fsactive": 0x01 << 15, + "csactual": 0x1F << 16, + "stallguard": 0x01 << 24, + "ot": 0x01 << 25, + "otpw": 0x01 << 26, + "s2ga": 0x01 << 27, + "s2gb": 0x01 << 28, + "ola": 0x01 << 29, + "olb": 0x01 << 30, + "stst": 0x01 << 31 +} +Fields["GCONF"] = { + "faststandstill": 0x01 << 1, + "en_pwm_mode": 0x01 << 2, + "multistep_filt": 0x01 << 3, + "shaft": 0x01 << 4, + "diag0_error": 0x01 << 5, + "diag0_otpw": 0x01 << 6, + "diag0_stall": 0x01 << 7, + "diag1_stall": 0x01 << 8, + "diag1_index": 0x01 << 9, + "diag1_onstate": 0x01 << 10, + "diag0_pushpull": 0x01 << 12, + "diag1_pushpull": 0x01 << 13, + "small_hysteresis": 0x01 << 14, + "stop_enable": 0x01 << 15, + "direct_mode": 0x01 << 16 +} +Fields["GSTAT"] = { + "reset": 0x01 << 0, + "drv_err": 0x01 << 1, + "uv_cp": 0x01 << 2, + "register_reset": 0x01 << 3, + "vm_uvlo": 0x01 << 4 +} +Fields["GLOBALSCALER"] = { + "globalscaler": 0xFF << 0 +} +Fields["IHOLD_IRUN"] = { + "ihold": 0x1F << 0, + "irun": 0x1F << 8, + "iholddelay": 0x0F << 16, + "irundelay": 0x0F << 24 +} +Fields["IOIN"] = { + "step": 0x01 << 0, + "dir": 0x01 << 1, + "encb": 0x01 << 2, + "enca": 0x01 << 3, + "drv_enn": 0x01 << 4, + "encn": 0x01 << 5, + "uart_en": 0x01 << 6, + "comp_a": 0x01 << 8, + "comp_b": 0x01 << 9, + "comp_a1_a2": 0x01 << 10, + "comp_b1_b2": 0x01 << 11, + "output": 0x01 << 12, + "ext_res_det": 0x01 << 13, + "ext_clk": 0x01 << 14, + "adc_err": 0x01 << 15, + "silicon_rv": 0x07 << 16, + "version": 0xFF << 24 +} +Fields["MSLUT0"] = { "mslut0": 0xffffffff } +Fields["MSLUT1"] = { "mslut1": 0xffffffff } +Fields["MSLUT2"] = { "mslut2": 0xffffffff } +Fields["MSLUT3"] = { "mslut3": 0xffffffff } +Fields["MSLUT4"] = { "mslut4": 0xffffffff } +Fields["MSLUT5"] = { "mslut5": 0xffffffff } +Fields["MSLUT6"] = { "mslut6": 0xffffffff } +Fields["MSLUT7"] = { "mslut7": 0xffffffff } +Fields["MSLUTSEL"] = { + "x3": 0xFF << 24, + "x2": 0xFF << 16, + "x1": 0xFF << 8, + "w3": 0x03 << 6, + "w2": 0x03 << 4, + "w1": 0x03 << 2, + "w0": 0x03 << 0, +} +Fields["MSLUTSTART"] = { + "start_sin": 0xFF << 0, + "start_sin90": 0xFF << 16, + "offset_sin90": 0xFF << 24, +} +Fields["MSCNT"] = { + "mscnt": 0x3ff << 0 +} +Fields["MSCURACT"] = { + "cur_a": 0x1ff << 0, + "cur_b": 0x1ff << 16 +} +Fields["PWM_AUTO"] = { + "pwm_ofs_auto": 0xff << 0, + "pwm_grad_auto": 0xff << 16 +} +Fields["PWMCONF"] = { + "pwm_ofs": 0xFF << 0, + "pwm_grad": 0xFF << 8, + "pwm_freq": 0x03 << 16, + "pwm_autoscale": 0x01 << 18, + "pwm_autograd": 0x01 << 19, + "freewheel": 0x03 << 20, + "pwm_meas_sd_enable": 0x01 << 22, + "pwm_dis_reg_stst": 0x01 << 23, + "pwm_reg": 0x0F << 24, + "pwm_lim": 0x0F << 28 +} +Fields["PWM_SCALE"] = { + "pwm_scale_sum": 0x3ff << 0, + "pwm_scale_auto": 0x1ff << 16 +} +Fields["TPOWERDOWN"] = { + "tpowerdown": 0xff << 0 +} +Fields["TPWMTHRS"] = { + "tpwmthrs": 0xfffff << 0 +} +Fields["TCOOLTHRS"] = { + "tcoolthrs": 0xfffff << 0 +} +Fields["TSTEP"] = { + "tstep": 0xfffff << 0 +} +Fields["THIGH"] = { + "thigh": 0xfffff << 0 +} +Fields["DRV_CONF"] = { + "current_range": 0x03 << 0, + "slope_control": 0x03 << 4 +} +Fields["ADC_VSUPPLY_AIN"] = { + "adc_vsupply": 0x1fff << 0, + "adc_ain": 0x1fff << 16 +} +Fields["ADC_TEMP"] = { + "adc_temp": 0x1fff << 0 +} +Fields["OTW_OV_VTH"] = { + "overvoltage_vth": 0x1fff << 0, + "overtempprewarning_vth": 0x1fff << 16 +} +Fields["SG4_THRS"] = { + "sg4_thrs": 0xFF << 0, + "sg4_filt_en": 0x01 << 8, + "sg4_angle_offset": 0x01 << 9 +} +Fields["SG4_RESULT"] = { + "sg4_result": 0x3FF << 0 +} +Fields["SG4_IND"] = { + "sg4_ind_0": 0xFF << 0, + "sg4_ind_1": 0xFF << 8, + "sg4_ind_2": 0xFF << 16, + "sg4_ind_3": 0xFF << 24 +} + + +SignedFields = ["cur_a", "cur_b", "sgt", "pwm_scale_auto", "offset_sin90"] + +FieldFormatters = dict(tmc2130.FieldFormatters) +FieldFormatters.update({ + "s2vsa": (lambda v: "1(ShortToSupply_A!)" if v else ""), + "s2vsb": (lambda v: "1(ShortToSupply_B!)" if v else ""), + "adc_temp": (lambda v: "0x%04x(%.1fC)" % (v, ((v - 2038) / 7.7))), +}) + + +###################################################################### +# TMC stepper current config helper +###################################################################### + +class TMC2240CurrentHelper: + def __init__(self, config, mcu_tmc): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.mcu_tmc = mcu_tmc + self.fields = mcu_tmc.get_fields() + self.Rref = config.getfloat('rref', 12000., + minval=12000., maxval=60000.) + max_cur = self._get_ifs_rms(3) + run_current = config.getfloat('run_current', above=0., maxval=max_cur) + hold_current = config.getfloat('hold_current', max_cur, + above=0., maxval=max_cur) + self.req_hold_current = hold_current + current_range = self._calc_current_range(run_current) + self.fields.set_field("current_range", current_range) + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + self.fields.set_field("globalscaler", gscaler) + self.fields.set_field("ihold", ihold) + self.fields.set_field("irun", irun) + def _get_ifs_rms(self, current_range=None): + if current_range is None: + current_range = self.fields.get_field("current_range") + KIFS = [11750., 24000., 36000., 36000.] + return (KIFS[current_range] / self.Rref) / math.sqrt(2.) + def _calc_current_range(self, current): + for current_range in range(4): + if current <= self._get_ifs_rms(current_range): + break + return current_range + def _calc_globalscaler(self, current): + ifs_rms = self._get_ifs_rms() + globalscaler = int(((current * 256.) / ifs_rms) + .5) + globalscaler = max(32, globalscaler) + if globalscaler >= 256: + globalscaler = 0 + return globalscaler + def _calc_current_bits(self, current, globalscaler): + ifs_rms = self._get_ifs_rms() + if not globalscaler: + globalscaler = 256 + cs = int((current * 256. * 32.) / (globalscaler * ifs_rms) - 1. + .5) + return max(0, min(31, cs)) + def _calc_current(self, run_current, hold_current): + gscaler = self._calc_globalscaler(run_current) + irun = self._calc_current_bits(run_current, gscaler) + ihold = self._calc_current_bits(min(hold_current, run_current), gscaler) + return gscaler, irun, ihold + def _calc_current_from_field(self, field_name): + ifs_rms = self._get_ifs_rms() + globalscaler = self.fields.get_field("globalscaler") + if not globalscaler: + globalscaler = 256 + bits = self.fields.get_field(field_name) + return globalscaler * (bits + 1) * ifs_rms / (256. * 32.) + def get_current(self): + ifs_rms = self._get_ifs_rms() + run_current = self._calc_current_from_field("irun") + hold_current = self._calc_current_from_field("ihold") + return (run_current, hold_current, self.req_hold_current, ifs_rms) + def set_current(self, run_current, hold_current, print_time): + self.req_hold_current = hold_current + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + val = self.fields.set_field("globalscaler", gscaler) + self.mcu_tmc.set_register("GLOBALSCALER", val, print_time) + self.fields.set_field("ihold", ihold) + val = self.fields.set_field("irun", irun) + self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) + + +###################################################################### +# TMC2240 printer object +###################################################################### + +class TMC2240: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) + self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields, + TMC_FREQUENCY) + # Allow virtual pins to be created + tmc.TMCVirtualPinHelper(config, self.mcu_tmc) + # Register commands + current_helper = TMC2240CurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + # Setup basic register values + self.fields.set_field("multistep_filt", True) + tmc.TMCWaveTableHelper(config, self.mcu_tmc) + self.fields.set_config_field(config, "offset_sin90", 0) + tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) + # CHOPCONF + set_config_field = self.fields.set_config_field + set_config_field(config, "toff", 3) + set_config_field(config, "hstrt", 5) + set_config_field(config, "hend", 2) + set_config_field(config, "fd3", 0) + set_config_field(config, "disfdcc", 0) + set_config_field(config, "chm", 0) + set_config_field(config, "tbl", 2) + set_config_field(config, "vhighfs", 0) + set_config_field(config, "vhighchm", 0) + set_config_field(config, "tpfd", 4) + set_config_field(config, "diss2g", 0) + set_config_field(config, "diss2vs", 0) + # COOLCONF + set_config_field(config, "semin", 0) + set_config_field(config, "seup", 0) + set_config_field(config, "semax", 0) + set_config_field(config, "sedn", 0) + set_config_field(config, "seimin", 0) + set_config_field(config, "sgt", 0) + set_config_field(config, "sfilt", 0) + # IHOLDIRUN + set_config_field(config, "iholddelay", 6) + set_config_field(config, "irundelay", 4) + # PWMCONF + set_config_field(config, "pwm_ofs", 29) + set_config_field(config, "pwm_grad", 0) + set_config_field(config, "pwm_freq", 0) + set_config_field(config, "pwm_autoscale", True) + set_config_field(config, "pwm_autograd", True) + set_config_field(config, "freewheel", 0) + set_config_field(config, "pwm_reg", 4) + set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 10) + # SG4_THRS + set_config_field(config, "sg4_angle_offset", 1) + +def load_config_prefix(config): + return TMC2240(config) diff --git a/klippy/extras/tmc2660.py b/klippy/extras/tmc2660.py index e873c608bffa..dcffac759fbd 100644 --- a/klippy/extras/tmc2660.py +++ b/klippy/extras/tmc2660.py @@ -221,6 +221,8 @@ def set_register(self, reg_name, val, print_time=None): msg = [((val >> 16) | reg) & 0xff, (val >> 8) & 0xff, val & 0xff] with self.mutex: self.spi.spi_send(msg, minclock) + def get_tmc_frequency(self): + return None ###################################################################### diff --git a/klippy/extras/tmc5160.py b/klippy/extras/tmc5160.py index 4d9702711d7b..1e8266b3cf54 100644 --- a/klippy/extras/tmc5160.py +++ b/klippy/extras/tmc5160.py @@ -105,6 +105,13 @@ "diss2g": 0x01 << 30, "diss2vs": 0x01 << 31 } +Fields["DRV_CONF"] = { + "bbmtime": 0x1F << 0, + "bbmclks": 0x0F << 8, + "otselect": 0x03 << 16, + "drvstrength": 0x03 << 18, + "filt_isense": 0x03 << 20, +} Fields["DRV_STATUS"] = { "sg_result": 0x3FF << 0, "s2vsa": 0x01 << 12, @@ -171,6 +178,27 @@ Fields["LOST_STEPS"] = { "lost_steps": 0xfffff << 0 } +Fields["MSLUT0"] = { "mslut0": 0xffffffff } +Fields["MSLUT1"] = { "mslut1": 0xffffffff } +Fields["MSLUT2"] = { "mslut2": 0xffffffff } +Fields["MSLUT3"] = { "mslut3": 0xffffffff } +Fields["MSLUT4"] = { "mslut4": 0xffffffff } +Fields["MSLUT5"] = { "mslut5": 0xffffffff } +Fields["MSLUT6"] = { "mslut6": 0xffffffff } +Fields["MSLUT7"] = { "mslut7": 0xffffffff } +Fields["MSLUTSEL"] = { + "x3": 0xFF << 24, + "x2": 0xFF << 16, + "x1": 0xFF << 8, + "w3": 0x03 << 6, + "w2": 0x03 << 4, + "w1": 0x03 << 2, + "w0": 0x03 << 0, +} +Fields["MSLUTSTART"] = { + "start_sin": 0xFF << 0, + "start_sin90": 0xFF << 16, +} Fields["MSCNT"] = { "mscnt": 0x3ff << 0 } @@ -218,6 +246,10 @@ SignedFields = ["cur_a", "cur_b", "sgt", "xactual", "vactual", "pwm_scale_auto"] FieldFormatters = dict(tmc2130.FieldFormatters) +FieldFormatters.update({ + "s2vsa": (lambda v: "1(ShortToSupply_A!)" if v else ""), + "s2vsb": (lambda v: "1(ShortToSupply_B!)" if v else ""), +}) ###################################################################### @@ -239,19 +271,18 @@ def __init__(self, config, mcu_tmc): above=0., maxval=MAX_CURRENT) self.req_hold_current = hold_current self.sense_resistor = config.getfloat('sense_resistor', 0.075, above=0.) - self._set_globalscaler(run_current) - irun, ihold = self._calc_current(run_current, hold_current) + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + self.fields.set_field("globalscaler", gscaler) self.fields.set_field("ihold", ihold) self.fields.set_field("irun", irun) - def _set_globalscaler(self, current): + def _calc_globalscaler(self, current): globalscaler = int((current * 256. * math.sqrt(2.) * self.sense_resistor / VREF) + .5) globalscaler = max(32, globalscaler) if globalscaler >= 256: globalscaler = 0 - self.fields.set_field("globalscaler", globalscaler) - def _calc_current_bits(self, current): - globalscaler = self.fields.get_field("globalscaler") + return globalscaler + def _calc_current_bits(self, current, globalscaler): if not globalscaler: globalscaler = 256 cs = int((current * 256. * 32. * math.sqrt(2.) * self.sense_resistor) @@ -259,9 +290,10 @@ def _calc_current_bits(self, current): - 1. + .5) return max(0, min(31, cs)) def _calc_current(self, run_current, hold_current): - irun = self._calc_current_bits(run_current) - ihold = self._calc_current_bits(min(hold_current, run_current)) - return irun, ihold + gscaler = self._calc_globalscaler(run_current) + irun = self._calc_current_bits(run_current, gscaler) + ihold = self._calc_current_bits(min(hold_current, run_current), gscaler) + return gscaler, irun, ihold def _calc_current_from_field(self, field_name): globalscaler = self.fields.get_field("globalscaler") if not globalscaler: @@ -275,7 +307,9 @@ def get_current(self): return run_current, hold_current, self.req_hold_current, MAX_CURRENT def set_current(self, run_current, hold_current, print_time): self.req_hold_current = hold_current - irun, ihold = self._calc_current(run_current, hold_current) + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + val = self.fields.set_field("globalscaler", gscaler) + self.mcu_tmc.set_register("GLOBALSCALER", val, print_time) self.fields.set_field("ihold", ihold) val = self.fields.set_field("irun", irun) self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) @@ -289,7 +323,8 @@ class TMC5160: def __init__(self, config): # Setup mcu communication self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields) + self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields, + TMC_FREQUENCY) # Allow virtual pins to be created tmc.TMCVirtualPinHelper(config, self.mcu_tmc) # Register commands @@ -299,9 +334,11 @@ def __init__(self, config): self.get_phase_offset = cmdhelper.get_phase_offset self.get_status = cmdhelper.get_status # Setup basic register values + self.fields.set_field("multistep_filt", True) + tmc.TMCWaveTableHelper(config, self.mcu_tmc) tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - # CHOPCONF set_config_field = self.fields.set_config_field + # CHOPCONF set_config_field(config, "toff", 3) set_config_field(config, "hstrt", 5) set_config_field(config, "hend", 2) @@ -322,6 +359,11 @@ def __init__(self, config): set_config_field(config, "seimin", 0) set_config_field(config, "sgt", 0) set_config_field(config, "sfilt", 0) + # DRV_CONF + set_config_field(config, "drvstrength", 0) + set_config_field(config, "bbmclks", 4) + set_config_field(config, "bbmtime", 0) + set_config_field(config, "filt_isense", 0) # IHOLDIRUN set_config_field(config, "iholddelay", 6) # PWMCONF diff --git a/klippy/extras/tmc_uart.py b/klippy/extras/tmc_uart.py index fe51303eed55..4d5ec1d5a257 100644 --- a/klippy/extras/tmc_uart.py +++ b/klippy/extras/tmc_uart.py @@ -210,7 +210,7 @@ def lookup_tmc_uart_bitbang(config, max_addr): # Helper code for communicating via TMC uart class MCU_TMC_uart: - def __init__(self, config, name_to_reg, fields, max_addr=0): + def __init__(self, config, name_to_reg, fields, max_addr, tmc_frequency): self.printer = config.get_printer() self.name = config.get_name().split()[-1] self.name_to_reg = name_to_reg @@ -219,6 +219,7 @@ def __init__(self, config, name_to_reg, fields, max_addr=0): self.instance_id, self.addr, self.mcu_uart = lookup_tmc_uart_bitbang( config, max_addr) self.mutex = self.mcu_uart.mutex + self.tmc_frequency = tmc_frequency def get_fields(self): return self.fields def _do_get_register(self, reg_name): @@ -250,3 +251,5 @@ def set_register(self, reg_name, val, print_time=None): return raise self.printer.command_error( "Unable to write tmc uart '%s' register %s" % (self.name, reg_name)) + def get_tmc_frequency(self): + return self.tmc_frequency diff --git a/klippy/extras/z_tilt.py b/klippy/extras/z_tilt.py index 72c33831bf07..49bafc4a38b2 100644 --- a/klippy/extras/z_tilt.py +++ b/klippy/extras/z_tilt.py @@ -41,7 +41,7 @@ def adjust_steppers(self, adjustments, speed): s.set_trapq(None) # Move each z stepper (sorted from lowest to highest) until they match positions = [(-a, s) for a, s in zip(adjustments, self.z_steppers)] - positions.sort() + positions.sort(key=(lambda k: k[0])) first_stepper_offset, first_stepper = positions[0] z_low = curpos[2] - first_stepper_offset for i in range(len(positions)-1): diff --git a/klippy/kinematics/corexz.py b/klippy/kinematics/corexz.py index 66e054230b0c..72134c32741b 100644 --- a/klippy/kinematics/corexz.py +++ b/klippy/kinematics/corexz.py @@ -9,13 +9,12 @@ class CoreXZKinematics: def __init__(self, toolhead, config): # Setup axis rails - self.rails = [ stepper.PrinterRail(config.getsection('stepper_x')), - stepper.PrinterRail(config.getsection('stepper_y')), - stepper.PrinterRail(config.getsection('stepper_z')) ] - self.rails[0].get_endstops()[0][0].add_stepper( - self.rails[2].get_steppers()[0]) - self.rails[2].get_endstops()[0][0].add_stepper( - self.rails[0].get_steppers()[0]) + self.rails = [stepper.LookupMultiRail(config.getsection('stepper_' + n)) + for n in 'xyz'] + for s in self.rails[0].get_steppers(): + self.rails[2].get_endstops()[0][0].add_stepper(s) + for s in self.rails[2].get_steppers(): + self.rails[0].get_endstops()[0][0].add_stepper(s) self.rails[0].setup_itersolve('corexz_stepper_alloc', b'+') self.rails[1].setup_itersolve('cartesian_stepper_alloc', b'y') self.rails[2].setup_itersolve('corexz_stepper_alloc', b'-') diff --git a/klippy/kinematics/delta.py b/klippy/kinematics/delta.py index 2278dbca76ae..bb81ab18abeb 100644 --- a/klippy/kinematics/delta.py +++ b/klippy/kinematics/delta.py @@ -65,6 +65,8 @@ def __init__(self, toolhead, config): self.min_z = config.getfloat('minimum_z_position', 0, maxval=self.max_z) self.limit_z = min([ep - arm for ep, arm in zip(self.abs_endstops, arm_lengths)]) + self.min_arm_length = min_arm_length = min(arm_lengths) + self.min_arm2 = min_arm_length**2 logging.info( "Delta max build height %.2fmm (radius tapered above %.2fmm)" % (self.max_z, self.limit_z)) @@ -123,7 +125,11 @@ def check_move(self, move): end_z = end_pos[2] limit_xy2 = self.max_xy2 if end_z > self.limit_z: - limit_xy2 = min(limit_xy2, (self.max_z - end_z)**2) + above_z_limit = end_z - self.limit_z + allowed_radius = self.radius - math.sqrt( + self.min_arm2 - (self.min_arm_length - above_z_limit)**2 + ) + limit_xy2 = min(limit_xy2, allowed_radius**2) if end_xy2 > limit_xy2 or end_z > self.max_z or end_z < self.min_z: # Move out of range - verify not a homing move if (end_pos[:2] != self.home_position[:2] diff --git a/klippy/kinematics/extruder.py b/klippy/kinematics/extruder.py index 62ba0c553e2f..ea422b6ec23e 100644 --- a/klippy/kinematics/extruder.py +++ b/klippy/kinematics/extruder.py @@ -20,6 +20,7 @@ def __init__(self, config): self.sk_extruder = ffi_main.gc(ffi_lib.extruder_stepper_alloc(), ffi_lib.free) self.stepper.set_stepper_kinematics(self.sk_extruder) + self.motion_queue = None # Register commands self.printer.register_event_handler("klippy:connect", self._handle_connect) @@ -49,7 +50,8 @@ def _handle_connect(self): self._set_pressure_advance(self.config_pa, self.config_smooth_time) def get_status(self, eventtime): return {'pressure_advance': self.pressure_advance, - 'smooth_time': self.pressure_advance_smooth_time} + 'smooth_time': self.pressure_advance_smooth_time, + 'motion_queue': self.motion_queue} def find_past_position(self, print_time): mcu_pos = self.stepper.get_past_mcu_position(print_time) return self.stepper.mcu_to_commanded_position(mcu_pos) @@ -58,6 +60,7 @@ def sync_to_extruder(self, extruder_name): toolhead.flush_step_generation() if not extruder_name: self.stepper.set_trapq(None) + self.motion_queue = None return extruder = self.printer.lookup_object(extruder_name, None) if extruder is None or not isinstance(extruder, PrinterExtruder): @@ -65,6 +68,7 @@ def sync_to_extruder(self, extruder_name): % (extruder_name,)) self.stepper.set_position([extruder.last_position, 0., 0.]) self.stepper.set_trapq(extruder.get_trapq()) + self.motion_queue = extruder_name def _set_pressure_advance(self, pressure_advance, smooth_time): old_smooth_time = self.pressure_advance_smooth_time if not self.pressure_advance: @@ -127,7 +131,8 @@ def cmd_SET_E_ROTATION_DISTANCE(self, gcmd): def cmd_SYNC_EXTRUDER_MOTION(self, gcmd): ename = gcmd.get('MOTION_QUEUE') self.sync_to_extruder(ename) - gcmd.respond_info("Extruder stepper now syncing with '%s'" % (ename,)) + gcmd.respond_info("Extruder '%s' now syncing with '%s'" + % (self.name, ename)) cmd_SET_E_STEP_DISTANCE_help = "Set extruder step distance" def cmd_SET_E_STEP_DISTANCE(self, gcmd): step_dist = gcmd.get_float('DISTANCE', None, above=0.) @@ -144,7 +149,8 @@ def cmd_SET_E_STEP_DISTANCE(self, gcmd): def cmd_SYNC_STEPPER_TO_EXTRUDER(self, gcmd): ename = gcmd.get('EXTRUDER') self.sync_to_extruder(ename) - gcmd.respond_info("Extruder stepper now syncing with '%s'" % (ename,)) + gcmd.respond_info("Extruder '%s' now syncing with '%s'" + % (self.name, ename)) # Tracking for hotend heater, extrusion motion queue, and extruder stepper class PrinterExtruder: diff --git a/klippy/mcu.py b/klippy/mcu.py index 4aaf626943cc..76c70506ba4a 100644 --- a/klippy/mcu.py +++ b/klippy/mcu.py @@ -1,6 +1,6 @@ # Interface to Klipper micro-controller code # -# Copyright (C) 2016-2021 Kevin O'Connor +# Copyright (C) 2016-2023 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. import sys, os, zlib, logging, math @@ -9,6 +9,94 @@ class error(Exception): pass + +###################################################################### +# Command transmit helper classes +###################################################################### + +# Class to retry sending of a query command until a given response is received +class RetryAsyncCommand: + TIMEOUT_TIME = 5.0 + RETRY_TIME = 0.500 + def __init__(self, serial, name, oid=None): + self.serial = serial + self.name = name + self.oid = oid + self.reactor = serial.get_reactor() + self.completion = self.reactor.completion() + self.min_query_time = self.reactor.monotonic() + self.serial.register_response(self.handle_callback, name, oid) + def handle_callback(self, params): + if params['#sent_time'] >= self.min_query_time: + self.min_query_time = self.reactor.NEVER + self.reactor.async_complete(self.completion, params) + def get_response(self, cmds, cmd_queue, minclock=0, reqclock=0): + cmd, = cmds + self.serial.raw_send_wait_ack(cmd, minclock, reqclock, cmd_queue) + first_query_time = query_time = self.reactor.monotonic() + while 1: + params = self.completion.wait(query_time + self.RETRY_TIME) + if params is not None: + self.serial.register_response(None, self.name, self.oid) + return params + query_time = self.reactor.monotonic() + if query_time > first_query_time + self.TIMEOUT_TIME: + self.serial.register_response(None, self.name, self.oid) + raise serialhdl.error("Timeout on wait for '%s' response" + % (self.name,)) + self.serial.raw_send(cmd, minclock, minclock, cmd_queue) + +# Wrapper around query commands +class CommandQueryWrapper: + def __init__(self, serial, msgformat, respformat, oid=None, + cmd_queue=None, is_async=False, error=serialhdl.error): + self._serial = serial + self._cmd = serial.get_msgparser().lookup_command(msgformat) + serial.get_msgparser().lookup_command(respformat) + self._response = respformat.split()[0] + self._oid = oid + self._error = error + self._xmit_helper = serialhdl.SerialRetryCommand + if is_async: + self._xmit_helper = RetryAsyncCommand + if cmd_queue is None: + cmd_queue = serial.get_default_command_queue() + self._cmd_queue = cmd_queue + def _do_send(self, cmds, minclock, reqclock): + xh = self._xmit_helper(self._serial, self._response, self._oid) + reqclock = max(minclock, reqclock) + try: + return xh.get_response(cmds, self._cmd_queue, minclock, reqclock) + except serialhdl.error as e: + raise self._error(str(e)) + def send(self, data=(), minclock=0, reqclock=0): + return self._do_send([self._cmd.encode(data)], minclock, reqclock) + def send_with_preface(self, preface_cmd, preface_data=(), data=(), + minclock=0, reqclock=0): + cmds = [preface_cmd._cmd.encode(preface_data), self._cmd.encode(data)] + return self._do_send(cmds, minclock, reqclock) + +# Wrapper around command sending +class CommandWrapper: + def __init__(self, serial, msgformat, cmd_queue=None): + self._serial = serial + msgparser = serial.get_msgparser() + self._cmd = msgparser.lookup_command(msgformat) + if cmd_queue is None: + cmd_queue = serial.get_default_command_queue() + self._cmd_queue = cmd_queue + self._msgtag = msgparser.lookup_msgtag(msgformat) & 0xffffffff + def send(self, data=(), minclock=0, reqclock=0): + cmd = self._cmd.encode(data) + self._serial.raw_send(cmd, minclock, reqclock, self._cmd_queue) + def get_command_tag(self): + return self._msgtag + + +###################################################################### +# Wrapper classes for MCU pins +###################################################################### + class MCU_trsync: REASON_ENDSTOP_HIT = 1 REASON_COMMS_TIMEOUT = 2 @@ -64,14 +152,16 @@ def _build_config(self): self._stepper_stop_cmd = mcu.lookup_command( "stepper_stop_on_trigger oid=%c trsync_oid=%c", cq=self._cmd_queue) # Create trdispatch_mcu object - set_timeout_tag = mcu.lookup_command_tag( - "trsync_set_timeout oid=%c clock=%u") - trigger_tag = mcu.lookup_command_tag("trsync_trigger oid=%c reason=%c") - state_tag = mcu.lookup_command_tag( + set_timeout_tag = mcu.lookup_command( + "trsync_set_timeout oid=%c clock=%u").get_command_tag() + trigger_cmd = mcu.lookup_command("trsync_trigger oid=%c reason=%c") + trigger_tag = trigger_cmd.get_command_tag() + state_cmd = mcu.lookup_command( "trsync_state oid=%c can_trigger=%c trigger_reason=%c clock=%u") + state_tag = state_cmd.get_command_tag() ffi_main, ffi_lib = chelper.get_ffi() self._trdispatch_mcu = ffi_main.gc(ffi_lib.trdispatch_mcu_alloc( - self._trdispatch, mcu._serial.serialqueue, # XXX + self._trdispatch, mcu._serial.get_serialqueue(), # XXX self._cmd_queue, self._oid, set_timeout_tag, trigger_tag, state_tag), ffi_lib.free) def _shutdown(self): @@ -456,79 +546,10 @@ def _handle_analog_in_state(self, params): if self._callback is not None: self._callback(last_read_time, last_value) -# Class to retry sending of a query command until a given response is received -class RetryAsyncCommand: - TIMEOUT_TIME = 5.0 - RETRY_TIME = 0.500 - def __init__(self, serial, name, oid=None): - self.serial = serial - self.name = name - self.oid = oid - self.reactor = serial.get_reactor() - self.completion = self.reactor.completion() - self.min_query_time = self.reactor.monotonic() - self.serial.register_response(self.handle_callback, name, oid) - def handle_callback(self, params): - if params['#sent_time'] >= self.min_query_time: - self.min_query_time = self.reactor.NEVER - self.reactor.async_complete(self.completion, params) - def get_response(self, cmds, cmd_queue, minclock=0, reqclock=0): - cmd, = cmds - self.serial.raw_send_wait_ack(cmd, minclock, reqclock, cmd_queue) - first_query_time = query_time = self.reactor.monotonic() - while 1: - params = self.completion.wait(query_time + self.RETRY_TIME) - if params is not None: - self.serial.register_response(None, self.name, self.oid) - return params - query_time = self.reactor.monotonic() - if query_time > first_query_time + self.TIMEOUT_TIME: - self.serial.register_response(None, self.name, self.oid) - raise serialhdl.error("Timeout on wait for '%s' response" - % (self.name,)) - self.serial.raw_send(cmd, minclock, minclock, cmd_queue) - -# Wrapper around query commands -class CommandQueryWrapper: - def __init__(self, serial, msgformat, respformat, oid=None, - cmd_queue=None, is_async=False, error=serialhdl.error): - self._serial = serial - self._cmd = serial.get_msgparser().lookup_command(msgformat) - serial.get_msgparser().lookup_command(respformat) - self._response = respformat.split()[0] - self._oid = oid - self._error = error - self._xmit_helper = serialhdl.SerialRetryCommand - if is_async: - self._xmit_helper = RetryAsyncCommand - if cmd_queue is None: - cmd_queue = serial.get_default_command_queue() - self._cmd_queue = cmd_queue - def _do_send(self, cmds, minclock, reqclock): - xh = self._xmit_helper(self._serial, self._response, self._oid) - reqclock = max(minclock, reqclock) - try: - return xh.get_response(cmds, self._cmd_queue, minclock, reqclock) - except serialhdl.error as e: - raise self._error(str(e)) - def send(self, data=(), minclock=0, reqclock=0): - return self._do_send([self._cmd.encode(data)], minclock, reqclock) - def send_with_preface(self, preface_cmd, preface_data=(), data=(), - minclock=0, reqclock=0): - cmds = [preface_cmd._cmd.encode(preface_data), self._cmd.encode(data)] - return self._do_send(cmds, minclock, reqclock) -# Wrapper around command sending -class CommandWrapper: - def __init__(self, serial, msgformat, cmd_queue=None): - self._serial = serial - self._cmd = serial.get_msgparser().lookup_command(msgformat) - if cmd_queue is None: - cmd_queue = serial.get_default_command_queue() - self._cmd_queue = cmd_queue - def send(self, data=(), minclock=0, reqclock=0): - cmd = self._cmd.encode(data) - self._serial.raw_send(cmd, minclock, reqclock, self._cmd_queue) +###################################################################### +# Main MCU class +###################################################################### class MCU: error = error @@ -746,7 +767,7 @@ def _connect(self): raise error("Too few moves available on MCU '%s'" % (self._name,)) ffi_main, ffi_lib = chelper.get_ffi() self._steppersync = ffi_main.gc( - ffi_lib.steppersync_alloc(self._serial.serialqueue, + ffi_lib.steppersync_alloc(self._serial.get_serialqueue(), self._stepqueues, len(self._stepqueues), move_count-self._reserved_move_slots), ffi_lib.steppersync_free) @@ -859,9 +880,6 @@ def try_lookup_command(self, msgformat): return self.lookup_command(msgformat) except self._serial.get_msgparser().error as e: return None - def lookup_command_tag(self, msgformat): - all_msgs = self._serial.get_msgparser().get_messages() - return {fmt: msgtag for msgtag, msgtype, fmt in all_msgs}[msgformat] def get_enumerations(self): return self._serial.get_msgparser().get_enumerations() def get_constants(self): diff --git a/klippy/msgproto.py b/klippy/msgproto.py index 5a4233e710dd..f8a12530e67e 100644 --- a/klippy/msgproto.py +++ b/klippy/msgproto.py @@ -21,7 +21,7 @@ MESSAGE_PAYLOAD_MAX = MESSAGE_MAX - MESSAGE_MIN MESSAGE_SEQ_MASK = 0x0f MESSAGE_DEST = 0x10 -MESSAGE_SYNC = '\x7E' +MESSAGE_SYNC = 0x7e class error(Exception): pass @@ -29,12 +29,10 @@ class error(Exception): def crc16_ccitt(buf): crc = 0xffff for data in buf: - data = ord(data) data ^= crc & 0xff data ^= (data & 0x0f) << 4 crc = ((data << 8) | (crc >> 8)) ^ (data >> 4) ^ (data << 3) - crc = chr(crc >> 8) + chr(crc & 0xff) - return crc + return [crc >> 8, crc & 0xff] class PT_uint32: is_int = True @@ -236,6 +234,7 @@ def __init__(self, warn_prefix=""): self.messages = [] self.messages_by_id = {} self.messages_by_name = {} + self.msgtag_by_format = {} self.config = {} self.version = self.build_versions = "" self.raw_identify_data = "" @@ -245,10 +244,10 @@ def _error(self, msg, *params): def check_packet(self, s): if len(s) < MESSAGE_MIN: return 0 - msglen = ord(s[MESSAGE_POS_LEN]) + msglen = s[MESSAGE_POS_LEN] if msglen < MESSAGE_MIN or msglen > MESSAGE_MAX: return -1 - msgseq = ord(s[MESSAGE_POS_SEQ]) + msgseq = s[MESSAGE_POS_SEQ] if (msgseq & ~MESSAGE_SEQ_MASK) != MESSAGE_DEST: return -1 if len(s) < msglen: @@ -258,7 +257,7 @@ def check_packet(self, s): return -1 msgcrc = s[msglen-MESSAGE_TRAILER_CRC:msglen-MESSAGE_TRAILER_CRC+2] crc = crc16_ccitt(s[:msglen-MESSAGE_TRAILER_SIZE]) - if crc != msgcrc: + if crc != list(msgcrc): #logging.debug("got crc %s vs %s", repr(crc), repr(msgcrc)) return -1 return msglen @@ -294,10 +293,10 @@ def parse(self, s): def encode(self, seq, cmd): msglen = MESSAGE_MIN + len(cmd) seq = (seq & MESSAGE_SEQ_MASK) | MESSAGE_DEST - out = [chr(msglen), chr(seq), cmd] - out.append(crc16_ccitt(''.join(out))) + out = [msglen, seq] + cmd + out.append(crc16_ccitt(out)) out.append(MESSAGE_SYNC) - return ''.join(out) + return out def _parse_buffer(self, value): if not value: return [] @@ -318,6 +317,11 @@ def lookup_command(self, msgformat): self._error("Command format mismatch: %s vs %s", msgformat, mp.msgformat) return mp + def lookup_msgtag(self, msgformat): + msgtag = self.msgtag_by_format.get(msgformat) + if msgtag is None: + self._error("Unknown command: %s", msgformat) + return msgtag def create_command(self, msg): parts = msg.strip().split() if not parts: @@ -378,6 +382,7 @@ def _init_messages(self, messages, command_tags=[], output_tags=[]): self.messages.append((msgtag, msgtype, msgformat)) if msgtag < -32 or msgtag > 95: self._error("Multi-byte msgtag not supported") + self.msgtag_by_format[msgformat] = msgtag msgid = msgtag & 0x7f if msgtype == 'output': self.messages_by_id[msgid] = OutputFormat(msgid, msgformat) diff --git a/klippy/parsedump.py b/klippy/parsedump.py index 380446ebefb3..6d4191835889 100755 --- a/klippy/parsedump.py +++ b/klippy/parsedump.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python # Script to parse a serial port data dump # # Copyright (C) 2016 Kevin O'Connor @@ -23,12 +23,12 @@ def main(): f = open(data_filename, 'rb') fd = f.fileno() - data = "" + data = bytearray() while 1: newdata = os.read(fd, 4096) if not newdata: break - data += newdata + data += bytearray(newdata) while 1: l = mp.check_packet(data) if l == 0: @@ -37,7 +37,7 @@ def main(): logging.error("Invalid data") data = data[-l:] continue - msgs = mp.dump(bytearray(data[:l])) + msgs = mp.dump(data[:l]) sys.stdout.write('\n'.join(msgs[1:]) + '\n') data = data[l:] diff --git a/klippy/reactor.py b/klippy/reactor.py index 5b1ec56963c3..412d53edf64f 100644 --- a/klippy/reactor.py +++ b/klippy/reactor.py @@ -240,7 +240,7 @@ def mutex(self, is_locked=False): # File descriptors def register_fd(self, fd, read_callback, write_callback=None): file_handler = ReactorFileHandler(fd, read_callback, write_callback) - self.set_fd_wake(file_handle, True, False) + self.set_fd_wake(file_handler, True, False) return file_handler def unregister_fd(self, file_handler): if file_handler in self._read_fds: @@ -248,12 +248,12 @@ def unregister_fd(self, file_handler): if file_handler in self._write_fds: self._write_fds.pop(self._write_fds.index(file_handler)) def set_fd_wake(self, file_handler, is_readable=True, is_writeable=False): - if file_hander in self._read_fds: + if file_handler in self._read_fds: if not is_readable: self._read_fds.pop(self._read_fds.index(file_handler)) elif is_readable: self._read_fds.append(file_handler) - if file_hander in self._write_fds: + if file_handler in self._write_fds: if not is_writeable: self._write_fds.pop(self._write_fds.index(file_handler)) elif is_writeable: @@ -366,7 +366,7 @@ def __init__(self, gc_checking=False): def register_fd(self, fd, read_callback, write_callback=None): file_handler = ReactorFileHandler(fd, read_callback, write_callback) fds = self._fds.copy() - fds[fd] = callback + fds[fd] = read_callback self._fds = fds self._epoll.register(fd, select.EPOLLIN | select.EPOLLHUP) return file_handler diff --git a/klippy/serialhdl.py b/klippy/serialhdl.py index 15d1cc21d727..0285799385fb 100644 --- a/klippy/serialhdl.py +++ b/klippy/serialhdl.py @@ -226,6 +226,8 @@ def get_reactor(self): return self.reactor def get_msgparser(self): return self.msgparser + def get_serialqueue(self): + return self.serialqueue def get_default_command_queue(self): return self.default_cmd_queue # Serial response callbacks diff --git a/klippy/stepper.py b/klippy/stepper.py index ad7d12829ace..0f8c0275efc8 100644 --- a/klippy/stepper.py +++ b/klippy/stepper.py @@ -89,12 +89,12 @@ def _build_config(self): invert_step, step_pulse_ticks)) self._mcu.add_config_cmd("reset_step_clock oid=%d clock=0" % (self._oid,), on_restart=True) - step_cmd_tag = self._mcu.lookup_command_tag( - "queue_step oid=%c interval=%u count=%hu add=%hi") - dir_cmd_tag = self._mcu.lookup_command_tag( - "set_next_step_dir oid=%c dir=%c") - self._reset_cmd_tag = self._mcu.lookup_command_tag( - "reset_step_clock oid=%c clock=%u") + step_cmd_tag = self._mcu.lookup_command( + "queue_step oid=%c interval=%u count=%hu add=%hi").get_command_tag() + dir_cmd_tag = self._mcu.lookup_command( + "set_next_step_dir oid=%c dir=%c").get_command_tag() + self._reset_cmd_tag = self._mcu.lookup_command( + "reset_step_clock oid=%c clock=%u").get_command_tag() self._get_position_cmd = self._mcu.lookup_query_command( "stepper_get_position oid=%c", "stepper_position oid=%c pos=%i", oid=self._oid) diff --git a/klippy/toolhead.py b/klippy/toolhead.py index 2398d7ca1c5c..d8b9382570b6 100644 --- a/klippy/toolhead.py +++ b/klippy/toolhead.py @@ -240,7 +240,7 @@ def __init__(self, config): # Kinematic step generation scan window time tracking self.kin_flush_delay = SDS_CHECK_TIME self.kin_flush_times = [] - self.last_kin_flush_time = self.last_kin_move_time = 0. + self.force_flush_time = self.last_kin_move_time = 0. # Setup iterative solver ffi_main, ffi_lib = chelper.get_ffi() self.trapq = ffi_main.gc(ffi_lib.trapq_alloc(), ffi_lib.trapq_free) @@ -279,16 +279,16 @@ def __init__(self, config): def _update_move_time(self, next_print_time): batch_time = MOVE_BATCH_TIME kin_flush_delay = self.kin_flush_delay - lkft = self.last_kin_flush_time + fft = self.force_flush_time while 1: self.print_time = min(self.print_time + batch_time, next_print_time) - sg_flush_time = max(lkft, self.print_time - kin_flush_delay) + sg_flush_time = max(fft, self.print_time - kin_flush_delay) for sg in self.step_generators: sg(sg_flush_time) - free_time = max(lkft, sg_flush_time - kin_flush_delay) + free_time = max(fft, sg_flush_time - kin_flush_delay) self.trapq_finalize_moves(self.trapq, free_time) self.extruder.update_move_time(free_time) - mcu_flush_time = max(lkft, sg_flush_time - self.move_flush_time) + mcu_flush_time = max(fft, sg_flush_time - self.move_flush_time) for m in self.all_mcus: m.flush_moves(mcu_flush_time) if self.print_time >= next_print_time: @@ -296,7 +296,7 @@ def _update_move_time(self, next_print_time): def _calc_print_time(self): curtime = self.reactor.monotonic() est_print_time = self.mcu.estimated_print_time(curtime) - kin_time = max(est_print_time + MIN_KIN_TIME, self.last_kin_flush_time) + kin_time = max(est_print_time + MIN_KIN_TIME, self.force_flush_time) kin_time += self.kin_flush_delay min_print_time = max(est_print_time + self.buffer_time_start, kin_time) if min_print_time > self.print_time: @@ -332,7 +332,7 @@ def _process_moves(self, moves): if self.special_queuing_state: self._update_drip_move_time(next_move_time) self._update_move_time(next_move_time) - self.last_kin_move_time = next_move_time + self.last_kin_move_time = max(self.last_kin_move_time, next_move_time) def flush_step_generation(self): # Transition from "Flushed"/"Priming"/main state to "Flushed" state self.move_queue.flush() @@ -341,10 +341,16 @@ def flush_step_generation(self): self.reactor.update_timer(self.flush_timer, self.reactor.NEVER) self.move_queue.set_flush_time(self.buffer_time_high) self.idle_flush_print_time = 0. - flush_time = self.last_kin_move_time + self.kin_flush_delay - flush_time = max(flush_time, self.print_time - self.kin_flush_delay) - self.last_kin_flush_time = max(self.last_kin_flush_time, flush_time) - self._update_move_time(max(self.print_time, self.last_kin_flush_time)) + # Determine actual last "itersolve" flush time + lastf = self.print_time - self.kin_flush_delay + # Calculate flush time that includes kinematic scan windows + flush_time = max(lastf, self.last_kin_move_time + self.kin_flush_delay) + if flush_time > self.print_time: + # Flush in small time chunks + self._update_move_time(flush_time) + # Flush kinematic scan windows and step buffers + self.force_flush_time = max(self.force_flush_time, flush_time) + self._update_move_time(max(self.print_time, self.force_flush_time)) def _flush_lookahead(self): if self.special_queuing_state: return self.flush_step_generation() diff --git a/klippy/webhooks.py b/klippy/webhooks.py index 43ff9a914e62..9188a4f70af4 100644 --- a/klippy/webhooks.py +++ b/klippy/webhooks.py @@ -268,8 +268,14 @@ def _process_request(self, web_request): self.send(result) def send(self, data): - jmsg = json.dumps(data, separators=(',', ':')) - self.send_buffer += jmsg.encode() + b"\x03" + try: + jmsg = json.dumps(data, separators=(',', ':')) + self.send_buffer += jmsg.encode() + b"\x03" + except (TypeError, ValueError) as e: + msg = ("json encoding error: %s" % (str(e),)) + logging.exception(msg) + self.printer.invoke_shutdown(msg) + return if not self.is_blocking: self._do_send() diff --git a/lib/README b/lib/README index a827dc22acb9..ce24bce650ca 100644 --- a/lib/README +++ b/lib/README @@ -78,6 +78,11 @@ The stm32g0 directory contains code from: version v1.4.1 (5cb06333a6a43cefbe145f10a5aa98d3cc4cffee). Contents taken from the Drivers/CMSIS/Device/ST/STM32G0xx/ directory. +The stm32g4 directory contains code from: + https://github.com/STMicroelectronics/STM32CubeG4 +version v1.4.0 (e762fe2ce800cf6c18a1868a3aabc7e9351751bd). Contents +taken from the Drivers/CMSIS/Device/ST/STM32G4xx/ directory. + The stm32l4 directory contains code from: https://github.com/STMicroelectronics/STM32CubeL4 version v1.17.0 (5e1553e07706491bd11f4edd304e093b6e4b83a4). Contents @@ -85,7 +90,7 @@ taken from the Drivers/CMSIS/Device/ST/STM32L4xx/ directory. The stm32h7 directory contains code from: https://github.com/STMicroelectronics/STM32CubeH7 -version v1.7.0 (79196b09acfb720589f58e93ccf956401b18a191). Contents +version v1.9.0 (ccb11556044540590ca6e45056e6b65cdca2deb2). Contents taken from the Drivers/CMSIS/Device/ST/STM32H7xx/ directory. The rp2040 directory contains code from the pico sdk: @@ -120,6 +125,10 @@ from the repo's hc-sr04-range-sensor directory. It has been modified so that the IEP definitions compile correctly. See pru_rpmsg.patch for the modifications. +The ar100 directory contains code from: + https://github.com/crust-firmware/crust +revision 966124af914ce611aadd06fbbcbc4c36c4a0b240 + The fast-hash directory contains code from: https://github.com/ztanml/fast-hash revision ae3bb53c199fe75619e940b5b6a3584ede99c5fc @@ -146,4 +155,12 @@ used to upload firmware to devices flashed with the CanBoot bootloader. The can2040 directory contains code from: https://github.com/KevinOConnor/can2040 -revision 177b0073fe6f19281ee7f7fdbe9599e32d1b4b8b. +revision d1190afcaa6245c20da28199d06e453d2e743099. + +The Huada HC32F460 directory contains code from: + https://www.hdsc.com.cn/Category83-1490 +version 2.2 DDL minus example directory, empty/extra files + +The n32g45x directory contains parts of code from: + https://github.com/RT-Thread/rt-thread/tree/master/bsp/n32g452xx/Libraries/N32_Std_Driver +version v1.0.1 (77638c17877c4b6b0b81e189a36bb08b3384923b) diff --git a/lib/ar100/asm/spr.h b/lib/ar100/asm/spr.h new file mode 100644 index 000000000000..2e7912960dc9 --- /dev/null +++ b/lib/ar100/asm/spr.h @@ -0,0 +1,2667 @@ +/* + * Copyright © 2014 OpenRISC Project Maintainers. All rights reserved. + * SPDX-License-Identifier: BSD-1-Clause + */ + +#ifndef COMMON_ARCH_SPR_H +#define COMMON_ARCH_SPR_H + +#ifdef __ASSEMBLER__ +#define U(n) (n) +#else +#define U(n) (n ## U) +#endif + +#define SPR_GROUP_BITS 5 +#define SPR_GROUP_LSB 11 +#define SPR_GROUP_MSB 15 +#define SPR_INDEX_BITS 11 +#define SPR_INDEX_LSB 0 +#define SPR_INDEX_MSB 10 + +/****************/ +/* System Group */ +/****************/ +#define SPR_SYS_GROUP 0x00 + +/* Version Register */ +#define SPR_SYS_VR_INDEX U(0x000) +#define SPR_SYS_VR_ADDR U(0x0000) + +/* Revision */ +#define SPR_SYS_VR_REV_LSB 0 +#define SPR_SYS_VR_REV_MSB 5 +#define SPR_SYS_VR_REV_BITS 6 +#define SPR_SYS_VR_REV_MASK U(0x0000003f) +#define SPR_SYS_VR_REV_GET(x) (((x) >> 0) & U(0x0000003f)) +#define SPR_SYS_VR_REV_SET(x, y) (((x) & U(0xffffffc0)) | \ + ((y) << 0)) + +/* Updated Version Registers Present */ +#define SPR_SYS_VR_UVRP_OFFSET 6 +#define SPR_SYS_VR_UVRP_MASK 0x00000040 +#define SPR_SYS_VR_UVRP_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_VR_UVRP_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Configuration Template */ +#define SPR_SYS_VR_CFG_LSB 16 +#define SPR_SYS_VR_CFG_MSB 23 +#define SPR_SYS_VR_CFG_BITS 8 +#define SPR_SYS_VR_CFG_MASK U(0x00ff0000) +#define SPR_SYS_VR_CFG_GET(x) (((x) >> 16) & U(0x000000ff)) +#define SPR_SYS_VR_CFG_SET(x, y) (((x) & U(0xff00ffff)) | \ + ((y) << 16)) + +/* Version */ +#define SPR_SYS_VR_VER_LSB 24 +#define SPR_SYS_VR_VER_MSB 31 +#define SPR_SYS_VR_VER_BITS 8 +#define SPR_SYS_VR_VER_MASK U(0xff000000) +#define SPR_SYS_VR_VER_GET(x) (((x) >> 24) & U(0x000000ff)) +#define SPR_SYS_VR_VER_SET(x, y) (((x) & U(0x00ffffff)) | \ + ((y) << 24)) + +/* Unit Present Register */ +#define SPR_SYS_UPR_INDEX U(0x001) +#define SPR_SYS_UPR_ADDR U(0x0001) + +/* UPR Present */ +#define SPR_SYS_UPR_UP_OFFSET 0 +#define SPR_SYS_UPR_UP_MASK 0x00000001 +#define SPR_SYS_UPR_UP_GET(x) (((x) >> 0) & 0x1) +#define SPR_SYS_UPR_UP_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Data Cache Present */ +#define SPR_SYS_UPR_DCP_OFFSET 1 +#define SPR_SYS_UPR_DCP_MASK 0x00000002 +#define SPR_SYS_UPR_DCP_GET(x) (((x) >> 1) & 0x1) +#define SPR_SYS_UPR_DCP_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Instruction Cache Present */ +#define SPR_SYS_UPR_ICP_OFFSET 2 +#define SPR_SYS_UPR_ICP_MASK 0x00000004 +#define SPR_SYS_UPR_ICP_GET(x) (((x) >> 2) & 0x1) +#define SPR_SYS_UPR_ICP_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Data MMU Present */ +#define SPR_SYS_UPR_DMP_OFFSET 3 +#define SPR_SYS_UPR_DMP_MASK 0x00000008 +#define SPR_SYS_UPR_DMP_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_UPR_DMP_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Instruction MMU Present */ +#define SPR_SYS_UPR_IMP_OFFSET 4 +#define SPR_SYS_UPR_IMP_MASK 0x00000010 +#define SPR_SYS_UPR_IMP_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_UPR_IMP_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* MAC Present */ +#define SPR_SYS_UPR_MP_OFFSET 5 +#define SPR_SYS_UPR_MP_MASK 0x00000020 +#define SPR_SYS_UPR_MP_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_UPR_MP_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Debug Unit Present */ +#define SPR_SYS_UPR_DUP_OFFSET 6 +#define SPR_SYS_UPR_DUP_MASK 0x00000040 +#define SPR_SYS_UPR_DUP_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_UPR_DUP_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Performance Counters Unit Present */ +#define SPR_SYS_UPR_PCUP_OFFSET 7 +#define SPR_SYS_UPR_PCUP_MASK 0x00000080 +#define SPR_SYS_UPR_PCUP_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_UPR_PCUP_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Power Management Present */ +#define SPR_SYS_UPR_PICP_OFFSET 8 +#define SPR_SYS_UPR_PICP_MASK 0x00000100 +#define SPR_SYS_UPR_PICP_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_UPR_PICP_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Programmable Interrupt Controller Present */ +#define SPR_SYS_UPR_PMP_OFFSET 9 +#define SPR_SYS_UPR_PMP_MASK 0x00000200 +#define SPR_SYS_UPR_PMP_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_UPR_PMP_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Tick Timer Present */ +#define SPR_SYS_UPR_TTP_OFFSET 10 +#define SPR_SYS_UPR_TTP_MASK 0x00000400 +#define SPR_SYS_UPR_TTP_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_UPR_TTP_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Custom Units Present */ +#define SPR_SYS_UPR_CUP_LSB 24 +#define SPR_SYS_UPR_CUP_MSB 31 +#define SPR_SYS_UPR_CUP_BITS 8 +#define SPR_SYS_UPR_CUP_MASK U(0xff000000) +#define SPR_SYS_UPR_CUP_GET(x) (((x) >> 24) & U(0x000000ff)) +#define SPR_SYS_UPR_CUP_SET(x, y) (((x) & U(0x00ffffff)) | \ + ((y) << 24)) + +/* CPU Configuration Register */ +#define SPR_SYS_CPUCFGR_INDEX U(0x002) +#define SPR_SYS_CPUCFGR_ADDR U(0x0002) + +/* Number of Shadow GPR Files */ +#define SPR_SYS_CPUCFGR_NSGF_LSB 0 +#define SPR_SYS_CPUCFGR_NSGF_MSB 3 +#define SPR_SYS_CPUCFGR_NSGF_BITS 4 +#define SPR_SYS_CPUCFGR_NSGF_MASK U(0x0000000f) +#define SPR_SYS_CPUCFGR_NSGF_GET(x) (((x) >> 0) & U(0x0000000f)) +#define SPR_SYS_CPUCFGR_NSGF_SET(x, y) (((x) & U(0xfffffff0)) | \ + ((y) << 0)) + +/* Custom GPR File */ +#define SPR_SYS_CPUCFGR_CGF_OFFSET 4 +#define SPR_SYS_CPUCFGR_CGF_MASK 0x00000010 +#define SPR_SYS_CPUCFGR_CGF_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_CPUCFGR_CGF_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* ORBIS32 Supported */ +#define SPR_SYS_CPUCFGR_OB32S_OFFSET 5 +#define SPR_SYS_CPUCFGR_OB32S_MASK 0x00000020 +#define SPR_SYS_CPUCFGR_OB32S_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_CPUCFGR_OB32S_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* ORBIS64 Supported */ +#define SPR_SYS_CPUCFGR_OB64S_OFFSET 6 +#define SPR_SYS_CPUCFGR_OB64S_MASK 0x00000040 +#define SPR_SYS_CPUCFGR_OB64S_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_CPUCFGR_OB64S_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* ORFPX32 Supported */ +#define SPR_SYS_CPUCFGR_OF32S_OFFSET 7 +#define SPR_SYS_CPUCFGR_OF32S_MASK 0x00000080 +#define SPR_SYS_CPUCFGR_OF32S_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_CPUCFGR_OF32S_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* ORFPX64 Supported */ +#define SPR_SYS_CPUCFGR_OF64S_OFFSET 8 +#define SPR_SYS_CPUCFGR_OF64S_MASK 0x00000100 +#define SPR_SYS_CPUCFGR_OF64S_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_CPUCFGR_OF64S_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* ORVDX64 Supported */ +#define SPR_SYS_CPUCFGR_OV64S_OFFSET 9 +#define SPR_SYS_CPUCFGR_OV64S_MASK 0x00000200 +#define SPR_SYS_CPUCFGR_OV64S_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_CPUCFGR_OV64S_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* No Delay-Slot */ +#define SPR_SYS_CPUCFGR_ND_OFFSET 10 +#define SPR_SYS_CPUCFGR_ND_MASK 0x00000400 +#define SPR_SYS_CPUCFGR_ND_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_CPUCFGR_ND_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Architecture Version Register Present */ +#define SPR_SYS_CPUCFGR_AVRP_OFFSET 11 +#define SPR_SYS_CPUCFGR_AVRP_MASK 0x00000800 +#define SPR_SYS_CPUCFGR_AVRP_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_CPUCFGR_AVRP_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Exception Vector Base Address Register Present */ +#define SPR_SYS_CPUCFGR_EVBARP_OFFSET 12 +#define SPR_SYS_CPUCFGR_EVBARP_MASK 0x00001000 +#define SPR_SYS_CPUCFGR_EVBARP_GET(x) (((x) >> 12) & 0x1) +#define SPR_SYS_CPUCFGR_EVBARP_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Implementation-Specific Registers (ISR0-7) Present */ +#define SPR_SYS_CPUCFGR_ISRP_OFFSET 13 +#define SPR_SYS_CPUCFGR_ISRP_MASK 0x00002000 +#define SPR_SYS_CPUCFGR_ISRP_GET(x) (((x) >> 13) & 0x1) +#define SPR_SYS_CPUCFGR_ISRP_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* Arithmetic Exception Control/Status Registers Present */ +#define SPR_SYS_CPUCFGR_AECSRP_OFFSET 14 +#define SPR_SYS_CPUCFGR_AECSRP_MASK 0x00004000 +#define SPR_SYS_CPUCFGR_AECSRP_GET(x) (((x) >> 14) & 0x1) +#define SPR_SYS_CPUCFGR_AECSRP_SET(x, y) (((x) & U(0xffffbfff)) | \ + ((!!(y)) << 14)) + +/* Data MMU Configuration Register */ +#define SPR_SYS_DMMUCFGR_INDEX U(0x003) +#define SPR_SYS_DMMUCFGR_ADDR U(0x0003) + +/* Number of TLB Ways */ +#define SPR_SYS_DMMUCFGR_NTW_LSB 0 +#define SPR_SYS_DMMUCFGR_NTW_MSB 1 +#define SPR_SYS_DMMUCFGR_NTW_BITS 2 +#define SPR_SYS_DMMUCFGR_NTW_MASK U(0x00000003) +#define SPR_SYS_DMMUCFGR_NTW_GET(x) (((x) >> 0) & U(0x00000003)) +#define SPR_SYS_DMMUCFGR_NTW_SET(x, y) (((x) & U(0xfffffffc)) | \ + ((y) << 0)) + +/* Number of TLB Sets */ +#define SPR_SYS_DMMUCFGR_NTS_LSB 2 +#define SPR_SYS_DMMUCFGR_NTS_MSB 4 +#define SPR_SYS_DMMUCFGR_NTS_BITS 3 +#define SPR_SYS_DMMUCFGR_NTS_MASK U(0x0000001c) +#define SPR_SYS_DMMUCFGR_NTS_GET(x) (((x) >> 2) & U(0x00000007)) +#define SPR_SYS_DMMUCFGR_NTS_SET(x, y) (((x) & U(0xffffffe3)) | \ + ((y) << 2)) + +/* Number of ATB Entries */ +#define SPR_SYS_DMMUCFGR_NAE_LSB 5 +#define SPR_SYS_DMMUCFGR_NAE_MSB 7 +#define SPR_SYS_DMMUCFGR_NAE_BITS 3 +#define SPR_SYS_DMMUCFGR_NAE_MASK U(0x000000e0) +#define SPR_SYS_DMMUCFGR_NAE_GET(x) (((x) >> 5) & U(0x00000007)) +#define SPR_SYS_DMMUCFGR_NAE_SET(x, y) (((x) & U(0xffffff1f)) | \ + ((y) << 5)) + +/* Control Register Implemented */ +#define SPR_SYS_DMMUCFGR_CRI_OFFSET 8 +#define SPR_SYS_DMMUCFGR_CRI_MASK 0x00000100 +#define SPR_SYS_DMMUCFGR_CRI_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_DMMUCFGR_CRI_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Protection Register Implemented */ +#define SPR_SYS_DMMUCFGR_PRI_OFFSET 9 +#define SPR_SYS_DMMUCFGR_PRI_MASK 0x00000200 +#define SPR_SYS_DMMUCFGR_PRI_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_DMMUCFGR_PRI_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* TLB Entry Invalidate Register Implemented */ +#define SPR_SYS_DMMUCFGR_TEIRI_OFFSET 10 +#define SPR_SYS_DMMUCFGR_TEIRI_MASK 0x00000400 +#define SPR_SYS_DMMUCFGR_TEIRI_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_DMMUCFGR_TEIRI_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Hardware TLB Reload */ +#define SPR_SYS_DMMUCFGR_HTR_OFFSET 11 +#define SPR_SYS_DMMUCFGR_HTR_MASK 0x00000800 +#define SPR_SYS_DMMUCFGR_HTR_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_DMMUCFGR_HTR_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* DTLB reloaded in software */ +#define SPR_SYS_DMMUCFGR_HTR_SW 0 +/* DTLB reloaded in hardware */ +#define SPR_SYS_DMMUCFGR_HTR_HW 1 + +/* Instruction MMU Configuration Register */ +#define SPR_SYS_IMMUCFGR_INDEX U(0x004) +#define SPR_SYS_IMMUCFGR_ADDR U(0x0004) + +/* Number of TLB Ways */ +#define SPR_SYS_IMMUCFGR_NTW_LSB 0 +#define SPR_SYS_IMMUCFGR_NTW_MSB 1 +#define SPR_SYS_IMMUCFGR_NTW_BITS 2 +#define SPR_SYS_IMMUCFGR_NTW_MASK U(0x00000003) +#define SPR_SYS_IMMUCFGR_NTW_GET(x) (((x) >> 0) & U(0x00000003)) +#define SPR_SYS_IMMUCFGR_NTW_SET(x, y) (((x) & U(0xfffffffc)) | \ + ((y) << 0)) + +/* Number of TLB Sets */ +#define SPR_SYS_IMMUCFGR_NTS_LSB 2 +#define SPR_SYS_IMMUCFGR_NTS_MSB 4 +#define SPR_SYS_IMMUCFGR_NTS_BITS 3 +#define SPR_SYS_IMMUCFGR_NTS_MASK U(0x0000001c) +#define SPR_SYS_IMMUCFGR_NTS_GET(x) (((x) >> 2) & U(0x00000007)) +#define SPR_SYS_IMMUCFGR_NTS_SET(x, y) (((x) & U(0xffffffe3)) | \ + ((y) << 2)) + +/* Number of ATB Entries */ +#define SPR_SYS_IMMUCFGR_NAE_LSB 5 +#define SPR_SYS_IMMUCFGR_NAE_MSB 7 +#define SPR_SYS_IMMUCFGR_NAE_BITS 3 +#define SPR_SYS_IMMUCFGR_NAE_MASK U(0x000000e0) +#define SPR_SYS_IMMUCFGR_NAE_GET(x) (((x) >> 5) & U(0x00000007)) +#define SPR_SYS_IMMUCFGR_NAE_SET(x, y) (((x) & U(0xffffff1f)) | \ + ((y) << 5)) + +/* Control Register Implemented */ +#define SPR_SYS_IMMUCFGR_CRI_OFFSET 8 +#define SPR_SYS_IMMUCFGR_CRI_MASK 0x00000100 +#define SPR_SYS_IMMUCFGR_CRI_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_IMMUCFGR_CRI_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Protection Register Implemented */ +#define SPR_SYS_IMMUCFGR_PRI_OFFSET 9 +#define SPR_SYS_IMMUCFGR_PRI_MASK 0x00000200 +#define SPR_SYS_IMMUCFGR_PRI_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_IMMUCFGR_PRI_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* TLB Entry Invalidate Register Implemented */ +#define SPR_SYS_IMMUCFGR_TEIRI_OFFSET 10 +#define SPR_SYS_IMMUCFGR_TEIRI_MASK 0x00000400 +#define SPR_SYS_IMMUCFGR_TEIRI_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_IMMUCFGR_TEIRI_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Hardware TLB Reload */ +#define SPR_SYS_IMMUCFGR_HTR_OFFSET 11 +#define SPR_SYS_IMMUCFGR_HTR_MASK 0x00000800 +#define SPR_SYS_IMMUCFGR_HTR_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_IMMUCFGR_HTR_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* DTLB reloaded in software */ +#define SPR_SYS_IMMUCFGR_HTR_SW 0 +/* DTLB reloaded in hardware */ +#define SPR_SYS_IMMUCFGR_HTR_HW 1 + +/* Data Cache Configuration Register */ +#define SPR_SYS_DCCFGR_INDEX U(0x005) +#define SPR_SYS_DCCFGR_ADDR U(0x0005) + +/* Number of Cache Ways */ +#define SPR_SYS_DCCFGR_NCW_LSB 0 +#define SPR_SYS_DCCFGR_NCW_MSB 2 +#define SPR_SYS_DCCFGR_NCW_BITS 3 +#define SPR_SYS_DCCFGR_NCW_MASK U(0x00000007) +#define SPR_SYS_DCCFGR_NCW_GET(x) (((x) >> 0) & U(0x00000007)) +#define SPR_SYS_DCCFGR_NCW_SET(x, y) (((x) & U(0xfffffff8)) | \ + ((y) << 0)) + +/* Number of Cache Sets */ +#define SPR_SYS_DCCFGR_NCS_LSB 3 +#define SPR_SYS_DCCFGR_NCS_MSB 6 +#define SPR_SYS_DCCFGR_NCS_BITS 4 +#define SPR_SYS_DCCFGR_NCS_MASK U(0x00000078) +#define SPR_SYS_DCCFGR_NCS_GET(x) (((x) >> 3) & U(0x0000000f)) +#define SPR_SYS_DCCFGR_NCS_SET(x, y) (((x) & U(0xffffff87)) | \ + ((y) << 3)) + +/* Cache Block Size */ +#define SPR_SYS_DCCFGR_CBS_OFFSET 7 +#define SPR_SYS_DCCFGR_CBS_MASK 0x00000080 +#define SPR_SYS_DCCFGR_CBS_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_DCCFGR_CBS_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* 16 Bytes */ +#define SPR_SYS_DCCFGR_CBS_16 0 +/* 32 Bytes */ +#define SPR_SYS_DCCFGR_CBS_32 1 + +/* Cache Write Strategy */ +#define SPR_SYS_DCCFGR_CWS_OFFSET 8 +#define SPR_SYS_DCCFGR_CWS_MASK 0x00000100 +#define SPR_SYS_DCCFGR_CWS_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_DCCFGR_CWS_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Write Through */ +#define SPR_SYS_DCCFGR_CWS_WT 0 +/* Write Back */ +#define SPR_SYS_DCCFGR_CWS_WB 1 + +/* Cache Control Register Implemented */ +#define SPR_SYS_DCCFGR_CCRI_OFFSET 9 +#define SPR_SYS_DCCFGR_CCRI_MASK 0x00000200 +#define SPR_SYS_DCCFGR_CCRI_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_DCCFGR_CCRI_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Cache Block Invalidate Register Implemented */ +#define SPR_SYS_DCCFGR_CBIRI_OFFSET 10 +#define SPR_SYS_DCCFGR_CBIRI_MASK 0x00000400 +#define SPR_SYS_DCCFGR_CBIRI_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_DCCFGR_CBIRI_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Cache Block Prefetch Register Implemented */ +#define SPR_SYS_DCCFGR_CBPRI_OFFSET 11 +#define SPR_SYS_DCCFGR_CBPRI_MASK 0x00000800 +#define SPR_SYS_DCCFGR_CBPRI_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_DCCFGR_CBPRI_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Cache Block Lock Register Implemented */ +#define SPR_SYS_DCCFGR_CBLRI_OFFSET 12 +#define SPR_SYS_DCCFGR_CBLRI_MASK 0x00001000 +#define SPR_SYS_DCCFGR_CBLRI_GET(x) (((x) >> 12) & 0x1) +#define SPR_SYS_DCCFGR_CBLRI_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Cache Block Flush Register Implemented */ +#define SPR_SYS_DCCFGR_CBFRI_OFFSET 13 +#define SPR_SYS_DCCFGR_CBFRI_MASK 0x00002000 +#define SPR_SYS_DCCFGR_CBFRI_GET(x) (((x) >> 13) & 0x1) +#define SPR_SYS_DCCFGR_CBFRI_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* Cache Block Write-back Register Implemented */ +#define SPR_SYS_DCCFGR_CBWBRI_OFFSET 14 +#define SPR_SYS_DCCFGR_CBWBRI_MASK 0x00004000 +#define SPR_SYS_DCCFGR_CBWBRI_GET(x) (((x) >> 14) & 0x1) +#define SPR_SYS_DCCFGR_CBWBRI_SET(x, y) (((x) & U(0xffffbfff)) | \ + ((!!(y)) << 14)) + +/* Instruction Cache Configuration Register */ +#define SPR_SYS_ICCFGR_INDEX U(0x006) +#define SPR_SYS_ICCFGR_ADDR U(0x0006) + +/* Number of Cache Ways */ +#define SPR_SYS_ICCFGR_NCW_LSB 0 +#define SPR_SYS_ICCFGR_NCW_MSB 2 +#define SPR_SYS_ICCFGR_NCW_BITS 3 +#define SPR_SYS_ICCFGR_NCW_MASK U(0x00000007) +#define SPR_SYS_ICCFGR_NCW_GET(x) (((x) >> 0) & U(0x00000007)) +#define SPR_SYS_ICCFGR_NCW_SET(x, y) (((x) & U(0xfffffff8)) | \ + ((y) << 0)) + +/* Number of Cache Sets */ +#define SPR_SYS_ICCFGR_NCS_LSB 3 +#define SPR_SYS_ICCFGR_NCS_MSB 6 +#define SPR_SYS_ICCFGR_NCS_BITS 4 +#define SPR_SYS_ICCFGR_NCS_MASK U(0x00000078) +#define SPR_SYS_ICCFGR_NCS_GET(x) (((x) >> 3) & U(0x0000000f)) +#define SPR_SYS_ICCFGR_NCS_SET(x, y) (((x) & U(0xffffff87)) | \ + ((y) << 3)) + +/* Cache Block Size */ +#define SPR_SYS_ICCFGR_CBS_OFFSET 7 +#define SPR_SYS_ICCFGR_CBS_MASK 0x00000080 +#define SPR_SYS_ICCFGR_CBS_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_ICCFGR_CBS_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* 16 Bytes */ +#define SPR_SYS_ICCFGR_CBS_16 0 +/* 32 Bytes */ +#define SPR_SYS_ICCFGR_CBS_32 1 + +/* Cache Control Register Implemented */ +#define SPR_SYS_ICCFGR_CCRI_OFFSET 9 +#define SPR_SYS_ICCFGR_CCRI_MASK 0x00000200 +#define SPR_SYS_ICCFGR_CCRI_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_ICCFGR_CCRI_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Cache Block Invalidate Register Implemented */ +#define SPR_SYS_ICCFGR_CBIRI_OFFSET 10 +#define SPR_SYS_ICCFGR_CBIRI_MASK 0x00000400 +#define SPR_SYS_ICCFGR_CBIRI_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_ICCFGR_CBIRI_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Cache Block Prefetch Register Implemented */ +#define SPR_SYS_ICCFGR_CBPRI_OFFSET 11 +#define SPR_SYS_ICCFGR_CBPRI_MASK 0x00000800 +#define SPR_SYS_ICCFGR_CBPRI_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_ICCFGR_CBPRI_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Cache Block Lock Register Implemented */ +#define SPR_SYS_ICCFGR_CBLRI_OFFSET 12 +#define SPR_SYS_ICCFGR_CBLRI_MASK 0x00001000 +#define SPR_SYS_ICCFGR_CBLRI_GET(x) (((x) >> 12) & 0x1) +#define SPR_SYS_ICCFGR_CBLRI_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Debug Configuration Register */ +#define SPR_SYS_DCFGR_INDEX U(0x007) +#define SPR_SYS_DCFGR_ADDR U(0x0007) + +/* Number of Debug Pairs */ +#define SPR_SYS_DCFGR_NDP_LSB 0 +#define SPR_SYS_DCFGR_NDP_MSB 2 +#define SPR_SYS_DCFGR_NDP_BITS 3 +#define SPR_SYS_DCFGR_NDP_MASK U(0x00000007) +#define SPR_SYS_DCFGR_NDP_GET(x) (((x) >> 0) & U(0x00000007)) +#define SPR_SYS_DCFGR_NDP_SET(x, y) (((x) & U(0xfffffff8)) | \ + ((y) << 0)) + +/* Watchpoint Counters Implemented */ +#define SPR_SYS_DCFGR_WPCI_OFFSET 3 +#define SPR_SYS_DCFGR_WPCI_MASK 0x00000008 +#define SPR_SYS_DCFGR_WPCI_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_DCFGR_WPCI_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Performance Counters Configuration */ +#define SPR_SYS_PCCFGR_INDEX U(0x008) +#define SPR_SYS_PCCFGR_ADDR U(0x0008) + +/* Number of Performance Counters */ +#define SPR_SYS_PCCFGR_NPC_LSB 0 +#define SPR_SYS_PCCFGR_NPC_MSB 2 +#define SPR_SYS_PCCFGR_NPC_BITS 3 +#define SPR_SYS_PCCFGR_NPC_MASK U(0x00000007) +#define SPR_SYS_PCCFGR_NPC_GET(x) (((x) >> 0) & U(0x00000007)) +#define SPR_SYS_PCCFGR_NPC_SET(x, y) (((x) & U(0xfffffff8)) | \ + ((y) << 0)) + +/* Version Register 2 */ +#define SPR_SYS_VR2_INDEX U(0x009) +#define SPR_SYS_VR2_ADDR U(0x0009) + +/* Version */ +#define SPR_SYS_VR2_VER_LSB 0 +#define SPR_SYS_VR2_VER_MSB 23 +#define SPR_SYS_VR2_VER_BITS 24 +#define SPR_SYS_VR2_VER_MASK U(0x00ffffff) +#define SPR_SYS_VR2_VER_GET(x) (((x) >> 0) & U(0x00ffffff)) +#define SPR_SYS_VR2_VER_SET(x, y) (((x) & U(0xff000000)) | \ + ((y) << 0)) + +/* CPU Identification Number */ +#define SPR_SYS_VR2_CPUID_LSB 24 +#define SPR_SYS_VR2_CPUID_MSB 31 +#define SPR_SYS_VR2_CPUID_BITS 8 +#define SPR_SYS_VR2_CPUID_MASK U(0xff000000) +#define SPR_SYS_VR2_CPUID_GET(x) (((x) >> 24) & U(0x000000ff)) +#define SPR_SYS_VR2_CPUID_SET(x, y) (((x) & U(0x00ffffff)) | \ + ((y) << 24)) + +/* Architecture Version Register */ +#define SPR_SYS_AVR_INDEX U(0x00a) +#define SPR_SYS_AVR_ADDR U(0x000a) + +/* Major Architecture Version Number */ +#define SPR_SYS_AVR_REV_LSB 8 +#define SPR_SYS_AVR_REV_MSB 15 +#define SPR_SYS_AVR_REV_BITS 8 +#define SPR_SYS_AVR_REV_MASK U(0x0000ff00) +#define SPR_SYS_AVR_REV_GET(x) (((x) >> 8) & U(0x000000ff)) +#define SPR_SYS_AVR_REV_SET(x, y) (((x) & U(0xffff00ff)) | \ + ((y) << 8)) + +/* Minor Architecture Version Number */ +#define SPR_SYS_AVR_MIN_LSB 16 +#define SPR_SYS_AVR_MIN_MSB 23 +#define SPR_SYS_AVR_MIN_BITS 8 +#define SPR_SYS_AVR_MIN_MASK U(0x00ff0000) +#define SPR_SYS_AVR_MIN_GET(x) (((x) >> 16) & U(0x000000ff)) +#define SPR_SYS_AVR_MIN_SET(x, y) (((x) & U(0xff00ffff)) | \ + ((y) << 16)) + +/* Architecture Revision Number */ +#define SPR_SYS_AVR_MAJ_LSB 24 +#define SPR_SYS_AVR_MAJ_MSB 31 +#define SPR_SYS_AVR_MAJ_BITS 8 +#define SPR_SYS_AVR_MAJ_MASK U(0xff000000) +#define SPR_SYS_AVR_MAJ_GET(x) (((x) >> 24) & U(0x000000ff)) +#define SPR_SYS_AVR_MAJ_SET(x, y) (((x) & U(0x00ffffff)) | \ + ((y) << 24)) + +/* Exception Vector Base Address Register */ +#define SPR_SYS_EVBAR_INDEX U(0x00b) +#define SPR_SYS_EVBAR_ADDR U(0x000b) + +/* Exception Vector Base Address */ +#define SPR_SYS_EVBAR_EVBA_LSB 13 +#define SPR_SYS_EVBAR_EVBA_MSB 31 +#define SPR_SYS_EVBAR_EVBA_BITS 19 +#define SPR_SYS_EVBAR_EVBA_MASK U(0xffffe000) +#define SPR_SYS_EVBAR_EVBA_GET(x) (((x) >> 13) & U(0x0007ffff)) +#define SPR_SYS_EVBAR_EVBA_SET(x, y) (((x) & U(0x00001fff)) | \ + ((y) << 13)) + +/* Arithmetic Exception Control Register */ +#define SPR_SYS_AECR_INDEX U(0x00c) +#define SPR_SYS_AECR_ADDR U(0x000c) + +/* Carry on Add Exception Enabled */ +#define SPR_SYS_AECR_CYADDE_OFFSET 0 +#define SPR_SYS_AECR_CYADDE_MASK 0x00000001 +#define SPR_SYS_AECR_CYADDE_GET(x) (((x) >> 0) & 0x1) +#define SPR_SYS_AECR_CYADDE_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Overflow on Add Exception Enabled */ +#define SPR_SYS_AECR_OVADDE_OFFSET 1 +#define SPR_SYS_AECR_OVADDE_MASK 0x00000002 +#define SPR_SYS_AECR_OVADDE_GET(x) (((x) >> 1) & 0x1) +#define SPR_SYS_AECR_OVADDE_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Carry on Multiply Exception Enabled */ +#define SPR_SYS_AECR_CYMULE_OFFSET 2 +#define SPR_SYS_AECR_CYMULE_MASK 0x00000004 +#define SPR_SYS_AECR_CYMULE_GET(x) (((x) >> 2) & 0x1) +#define SPR_SYS_AECR_CYMULE_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Overflow on Multiply Exception Enabled */ +#define SPR_SYS_AECR_OVMULE_OFFSET 3 +#define SPR_SYS_AECR_OVMULE_MASK 0x00000008 +#define SPR_SYS_AECR_OVMULE_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_AECR_OVMULE_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Divide by Zero Exception Enabled */ +#define SPR_SYS_AECR_DBZE_OFFSET 4 +#define SPR_SYS_AECR_DBZE_MASK 0x00000010 +#define SPR_SYS_AECR_DBZE_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_AECR_DBZE_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Carry on MAC Addition Exception Enabled */ +#define SPR_SYS_AECR_CYMACADDE_OFFSET 5 +#define SPR_SYS_AECR_CYMACADDE_MASK 0x00000020 +#define SPR_SYS_AECR_CYMACADDE_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_AECR_CYMACADDE_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Overflow on MAC Addition Exception Enabled */ +#define SPR_SYS_AECR_OVMACADDE_OFFSET 6 +#define SPR_SYS_AECR_OVMACADDE_MASK 0x00000040 +#define SPR_SYS_AECR_OVMACADDE_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_AECR_OVMACADDE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Arithmetic Exception Status Register */ +#define SPR_SYS_AESR_INDEX U(0x00d) +#define SPR_SYS_AESR_ADDR U(0x000d) + +/* Carry on Add Exception */ +#define SPR_SYS_AESR_CYADDE_OFFSET 0 +#define SPR_SYS_AESR_CYADDE_MASK 0x00000001 +#define SPR_SYS_AESR_CYADDE_GET(x) (((x) >> 0) & 0x1) +#define SPR_SYS_AESR_CYADDE_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Overflow on Add Exception */ +#define SPR_SYS_AESR_OVADDE_OFFSET 1 +#define SPR_SYS_AESR_OVADDE_MASK 0x00000002 +#define SPR_SYS_AESR_OVADDE_GET(x) (((x) >> 1) & 0x1) +#define SPR_SYS_AESR_OVADDE_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Carry on Multiply Exception */ +#define SPR_SYS_AESR_CYMULE_OFFSET 2 +#define SPR_SYS_AESR_CYMULE_MASK 0x00000004 +#define SPR_SYS_AESR_CYMULE_GET(x) (((x) >> 2) & 0x1) +#define SPR_SYS_AESR_CYMULE_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Overflow on Multiply Exception */ +#define SPR_SYS_AESR_OVMULE_OFFSET 3 +#define SPR_SYS_AESR_OVMULE_MASK 0x00000008 +#define SPR_SYS_AESR_OVMULE_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_AESR_OVMULE_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Divide by Zero Exception */ +#define SPR_SYS_AESR_DBZE_OFFSET 4 +#define SPR_SYS_AESR_DBZE_MASK 0x00000010 +#define SPR_SYS_AESR_DBZE_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_AESR_DBZE_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Carry on MAC Addition Exception */ +#define SPR_SYS_AESR_CYMACADDE_OFFSET 5 +#define SPR_SYS_AESR_CYMACADDE_MASK 0x00000020 +#define SPR_SYS_AESR_CYMACADDE_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_AESR_CYMACADDE_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Overflow on MAC Addition Exception */ +#define SPR_SYS_AESR_OVMACADDE_OFFSET 6 +#define SPR_SYS_AESR_OVMACADDE_MASK 0x00000040 +#define SPR_SYS_AESR_OVMACADDE_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_AESR_OVMACADDE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Next Program Counter */ +#define SPR_SYS_NPC_INDEX U(0x010) +#define SPR_SYS_NPC_ADDR U(0x0010) + +/* Supervision Register */ +#define SPR_SYS_SR_INDEX U(0x011) +#define SPR_SYS_SR_ADDR U(0x0011) + +/* Supervisor Mode */ +#define SPR_SYS_SR_SM_OFFSET 0 +#define SPR_SYS_SR_SM_MASK 0x00000001 +#define SPR_SYS_SR_SM_GET(x) (((x) >> 0) & 0x1) +#define SPR_SYS_SR_SM_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Tick Timer Exception Enabled */ +#define SPR_SYS_SR_TEE_OFFSET 1 +#define SPR_SYS_SR_TEE_MASK 0x00000002 +#define SPR_SYS_SR_TEE_GET(x) (((x) >> 1) & 0x1) +#define SPR_SYS_SR_TEE_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Interrupt Exception Enabled */ +#define SPR_SYS_SR_IEE_OFFSET 2 +#define SPR_SYS_SR_IEE_MASK 0x00000004 +#define SPR_SYS_SR_IEE_GET(x) (((x) >> 2) & 0x1) +#define SPR_SYS_SR_IEE_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Data Cache Enabled */ +#define SPR_SYS_SR_DCE_OFFSET 3 +#define SPR_SYS_SR_DCE_MASK 0x00000008 +#define SPR_SYS_SR_DCE_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_SR_DCE_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Instruction Cache Enabled */ +#define SPR_SYS_SR_ICE_OFFSET 4 +#define SPR_SYS_SR_ICE_MASK 0x00000010 +#define SPR_SYS_SR_ICE_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_SR_ICE_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Data MMU Enabled */ +#define SPR_SYS_SR_DME_OFFSET 5 +#define SPR_SYS_SR_DME_MASK 0x00000020 +#define SPR_SYS_SR_DME_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_SR_DME_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Instruction MMU Enabled */ +#define SPR_SYS_SR_IME_OFFSET 6 +#define SPR_SYS_SR_IME_MASK 0x00000040 +#define SPR_SYS_SR_IME_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_SR_IME_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Little Endian Enabled */ +#define SPR_SYS_SR_LEE_OFFSET 7 +#define SPR_SYS_SR_LEE_MASK 0x00000080 +#define SPR_SYS_SR_LEE_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_SR_LEE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* CID Enable */ +#define SPR_SYS_SR_CE_OFFSET 8 +#define SPR_SYS_SR_CE_MASK 0x00000100 +#define SPR_SYS_SR_CE_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_SR_CE_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Flag */ +#define SPR_SYS_SR_F_OFFSET 9 +#define SPR_SYS_SR_F_MASK 0x00000200 +#define SPR_SYS_SR_F_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_SR_F_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Carry */ +#define SPR_SYS_SR_CY_OFFSET 10 +#define SPR_SYS_SR_CY_MASK 0x00000400 +#define SPR_SYS_SR_CY_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_SR_CY_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Overflow */ +#define SPR_SYS_SR_OV_OFFSET 11 +#define SPR_SYS_SR_OV_MASK 0x00000800 +#define SPR_SYS_SR_OV_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_SR_OV_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Overflow Exception Enabled */ +#define SPR_SYS_SR_OVE_OFFSET 12 +#define SPR_SYS_SR_OVE_MASK 0x00001000 +#define SPR_SYS_SR_OVE_GET(x) (((x) >> 12) & 0x1) +#define SPR_SYS_SR_OVE_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Delay-slot Exception */ +#define SPR_SYS_SR_DSX_OFFSET 13 +#define SPR_SYS_SR_DSX_MASK 0x00002000 +#define SPR_SYS_SR_DSX_GET(x) (((x) >> 13) & 0x1) +#define SPR_SYS_SR_DSX_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* Exception Prefix High */ +#define SPR_SYS_SR_EPH_OFFSET 14 +#define SPR_SYS_SR_EPH_MASK 0x00004000 +#define SPR_SYS_SR_EPH_GET(x) (((x) >> 14) & 0x1) +#define SPR_SYS_SR_EPH_SET(x, y) (((x) & U(0xffffbfff)) | \ + ((!!(y)) << 14)) + +/* Fixed One */ +#define SPR_SYS_SR_FO_OFFSET 15 +#define SPR_SYS_SR_FO_MASK 0x00008000 +#define SPR_SYS_SR_FO_GET(x) (((x) >> 15) & 0x1) +#define SPR_SYS_SR_FO_SET(x, y) (((x) & U(0xffff7fff)) | \ + ((!!(y)) << 15)) + +/* SPR User Mode Read Access */ +#define SPR_SYS_SR_SUMRA_OFFSET 16 +#define SPR_SYS_SR_SUMRA_MASK 0x00010000 +#define SPR_SYS_SR_SUMRA_GET(x) (((x) >> 16) & 0x1) +#define SPR_SYS_SR_SUMRA_SET(x, y) (((x) & U(0xfffeffff)) | \ + ((!!(y)) << 16)) + +/* Context ID */ +#define SPR_SYS_SR_CID_LSB 28 +#define SPR_SYS_SR_CID_MSB 31 +#define SPR_SYS_SR_CID_BITS 4 +#define SPR_SYS_SR_CID_MASK U(0xf0000000) +#define SPR_SYS_SR_CID_GET(x) (((x) >> 28) & U(0x0000000f)) +#define SPR_SYS_SR_CID_SET(x, y) (((x) & U(0x0fffffff)) | \ + ((y) << 28)) + +/* Previous Program Counter */ +#define SPR_SYS_PPC_INDEX U(0x012) +#define SPR_SYS_PPC_ADDR U(0x0012) + +/* Floating Point Control Status Register */ +#define SPR_SYS_FPCSR_INDEX U(0x014) +#define SPR_SYS_FPCSR_ADDR U(0x0014) + +/* Floating Point Exception Enabled */ +#define SPR_SYS_FPCSR_FPEE_OFFSET 0 +#define SPR_SYS_FPCSR_FPEE_MASK 0x00000001 +#define SPR_SYS_FPCSR_FPEE_GET(x) (((x) >> 0) & 0x1) +#define SPR_SYS_FPCSR_FPEE_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Rounding Mode */ +#define SPR_SYS_FPCSR_RM_LSB 1 +#define SPR_SYS_FPCSR_RM_MSB 2 +#define SPR_SYS_FPCSR_RM_BITS 2 +#define SPR_SYS_FPCSR_RM_MASK U(0x00000006) +#define SPR_SYS_FPCSR_RM_GET(x) (((x) >> 1) & U(0x00000003)) +#define SPR_SYS_FPCSR_RM_SET(x, y) (((x) & U(0xfffffff9)) | \ + ((y) << 1)) + +/* Round to nearest */ +#define SPR_SYS_FPCSR_RM_NEAREST 0 +/* Round to zero */ +#define SPR_SYS_FPCSR_RM_ZERO 1 +/* Round to infinity+ */ +#define SPR_SYS_FPCSR_RM_INFPLUS 2 +/* Round to infinity- */ +#define SPR_SYS_FPCSR_RM_INFMINUS 3 + +/* Overflow Flag */ +#define SPR_SYS_FPCSR_OVF_OFFSET 3 +#define SPR_SYS_FPCSR_OVF_MASK 0x00000008 +#define SPR_SYS_FPCSR_OVF_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_FPCSR_OVF_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Underflow Flag */ +#define SPR_SYS_FPCSR_UNF_OFFSET 4 +#define SPR_SYS_FPCSR_UNF_MASK 0x00000010 +#define SPR_SYS_FPCSR_UNF_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_FPCSR_UNF_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* SNAN Flag */ +#define SPR_SYS_FPCSR_SNF_OFFSET 5 +#define SPR_SYS_FPCSR_SNF_MASK 0x00000020 +#define SPR_SYS_FPCSR_SNF_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_FPCSR_SNF_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* QNAN Flag */ +#define SPR_SYS_FPCSR_QNF_OFFSET 6 +#define SPR_SYS_FPCSR_QNF_MASK 0x00000040 +#define SPR_SYS_FPCSR_QNF_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_FPCSR_QNF_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Zero Flag */ +#define SPR_SYS_FPCSR_ZF_OFFSET 7 +#define SPR_SYS_FPCSR_ZF_MASK 0x00000080 +#define SPR_SYS_FPCSR_ZF_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_FPCSR_ZF_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Inexact Flag */ +#define SPR_SYS_FPCSR_IXF_OFFSET 8 +#define SPR_SYS_FPCSR_IXF_MASK 0x00000100 +#define SPR_SYS_FPCSR_IXF_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_FPCSR_IXF_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Invalid Flag */ +#define SPR_SYS_FPCSR_IVF_OFFSET 9 +#define SPR_SYS_FPCSR_IVF_MASK 0x00000200 +#define SPR_SYS_FPCSR_IVF_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_FPCSR_IVF_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Infinity Flag */ +#define SPR_SYS_FPCSR_INF_OFFSET 10 +#define SPR_SYS_FPCSR_INF_MASK 0x00000400 +#define SPR_SYS_FPCSR_INF_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_FPCSR_INF_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Divide by Zero Flag */ +#define SPR_SYS_FPCSR_DZF_OFFSET 11 +#define SPR_SYS_FPCSR_DZF_MASK 0x00000800 +#define SPR_SYS_FPCSR_DZF_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_FPCSR_DZF_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Implementation-specific Registers */ +#define SPR_SYS_ISR_BASE U(0x015) +#define SPR_SYS_ISR_COUNT U(0x008) +#define SPR_SYS_ISR_STEP U(0x001) +#define SPR_SYS_ISR_INDEX(N) (SPR_SYS_ISR_BASE + \ + (SPR_SYS_ISR_STEP * (N))) +#define SPR_SYS_ISR_ADDR(N) ((SPR_SYS_GROUP << SPR_GROUP_LSB) | \ + SPR_SYS_ISR_INDEX(N)) + +/* Exception PC Registers */ +#define SPR_SYS_EPCR_BASE U(0x020) +#define SPR_SYS_EPCR_COUNT U(0x010) +#define SPR_SYS_EPCR_STEP U(0x001) +#define SPR_SYS_EPCR_INDEX(N) (SPR_SYS_EPCR_BASE + \ + (SPR_SYS_EPCR_STEP * (N))) +#define SPR_SYS_EPCR_ADDR(N) ((SPR_SYS_GROUP << SPR_GROUP_LSB) | \ + SPR_SYS_EPCR_INDEX(N)) + +/* Exception Effective Address Registers */ +#define SPR_SYS_EEAR_BASE U(0x030) +#define SPR_SYS_EEAR_COUNT U(0x010) +#define SPR_SYS_EEAR_STEP U(0x001) +#define SPR_SYS_EEAR_INDEX(N) (SPR_SYS_EEAR_BASE + \ + (SPR_SYS_EEAR_STEP * (N))) +#define SPR_SYS_EEAR_ADDR(N) ((SPR_SYS_GROUP << SPR_GROUP_LSB) | \ + SPR_SYS_EEAR_INDEX(N)) + +/* Exception Supervision Registers */ +#define SPR_SYS_ESR_BASE U(0x040) +#define SPR_SYS_ESR_COUNT U(0x010) +#define SPR_SYS_ESR_STEP U(0x001) +#define SPR_SYS_ESR_INDEX(N) (SPR_SYS_ESR_BASE + \ + (SPR_SYS_ESR_STEP * (N))) +#define SPR_SYS_ESR_ADDR(N) ((SPR_SYS_GROUP << SPR_GROUP_LSB) | \ + SPR_SYS_ESR_INDEX(N)) + +/* Supervisor Mode */ +#define SPR_SYS_ESR_SM_OFFSET 0 +#define SPR_SYS_ESR_SM_MASK 0x00000001 +#define SPR_SYS_ESR_SM_GET(x) (((x) >> 0) & 0x1) +#define SPR_SYS_ESR_SM_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Tick Timer Exception Enabled */ +#define SPR_SYS_ESR_TEE_OFFSET 1 +#define SPR_SYS_ESR_TEE_MASK 0x00000002 +#define SPR_SYS_ESR_TEE_GET(x) (((x) >> 1) & 0x1) +#define SPR_SYS_ESR_TEE_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Interrupt Exception Enabled */ +#define SPR_SYS_ESR_IEE_OFFSET 2 +#define SPR_SYS_ESR_IEE_MASK 0x00000004 +#define SPR_SYS_ESR_IEE_GET(x) (((x) >> 2) & 0x1) +#define SPR_SYS_ESR_IEE_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Data Cache Enabled */ +#define SPR_SYS_ESR_DCE_OFFSET 3 +#define SPR_SYS_ESR_DCE_MASK 0x00000008 +#define SPR_SYS_ESR_DCE_GET(x) (((x) >> 3) & 0x1) +#define SPR_SYS_ESR_DCE_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Instruction Cache Enabled */ +#define SPR_SYS_ESR_ICE_OFFSET 4 +#define SPR_SYS_ESR_ICE_MASK 0x00000010 +#define SPR_SYS_ESR_ICE_GET(x) (((x) >> 4) & 0x1) +#define SPR_SYS_ESR_ICE_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Data MMU Enabled */ +#define SPR_SYS_ESR_DME_OFFSET 5 +#define SPR_SYS_ESR_DME_MASK 0x00000020 +#define SPR_SYS_ESR_DME_GET(x) (((x) >> 5) & 0x1) +#define SPR_SYS_ESR_DME_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Instruction MMU Enabled */ +#define SPR_SYS_ESR_IME_OFFSET 6 +#define SPR_SYS_ESR_IME_MASK 0x00000040 +#define SPR_SYS_ESR_IME_GET(x) (((x) >> 6) & 0x1) +#define SPR_SYS_ESR_IME_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Little Endian Enabled */ +#define SPR_SYS_ESR_LEE_OFFSET 7 +#define SPR_SYS_ESR_LEE_MASK 0x00000080 +#define SPR_SYS_ESR_LEE_GET(x) (((x) >> 7) & 0x1) +#define SPR_SYS_ESR_LEE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* CID Enable */ +#define SPR_SYS_ESR_CE_OFFSET 8 +#define SPR_SYS_ESR_CE_MASK 0x00000100 +#define SPR_SYS_ESR_CE_GET(x) (((x) >> 8) & 0x1) +#define SPR_SYS_ESR_CE_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Flag */ +#define SPR_SYS_ESR_F_OFFSET 9 +#define SPR_SYS_ESR_F_MASK 0x00000200 +#define SPR_SYS_ESR_F_GET(x) (((x) >> 9) & 0x1) +#define SPR_SYS_ESR_F_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Carry */ +#define SPR_SYS_ESR_CY_OFFSET 10 +#define SPR_SYS_ESR_CY_MASK 0x00000400 +#define SPR_SYS_ESR_CY_GET(x) (((x) >> 10) & 0x1) +#define SPR_SYS_ESR_CY_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* Overflow */ +#define SPR_SYS_ESR_OV_OFFSET 11 +#define SPR_SYS_ESR_OV_MASK 0x00000800 +#define SPR_SYS_ESR_OV_GET(x) (((x) >> 11) & 0x1) +#define SPR_SYS_ESR_OV_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Overflow Exception Enabled */ +#define SPR_SYS_ESR_OVE_OFFSET 12 +#define SPR_SYS_ESR_OVE_MASK 0x00001000 +#define SPR_SYS_ESR_OVE_GET(x) (((x) >> 12) & 0x1) +#define SPR_SYS_ESR_OVE_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Delay-slot Exception */ +#define SPR_SYS_ESR_DSX_OFFSET 13 +#define SPR_SYS_ESR_DSX_MASK 0x00002000 +#define SPR_SYS_ESR_DSX_GET(x) (((x) >> 13) & 0x1) +#define SPR_SYS_ESR_DSX_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* Exception Prefix High */ +#define SPR_SYS_ESR_EPH_OFFSET 14 +#define SPR_SYS_ESR_EPH_MASK 0x00004000 +#define SPR_SYS_ESR_EPH_GET(x) (((x) >> 14) & 0x1) +#define SPR_SYS_ESR_EPH_SET(x, y) (((x) & U(0xffffbfff)) | \ + ((!!(y)) << 14)) + +/* Fixed One */ +#define SPR_SYS_ESR_FO_OFFSET 15 +#define SPR_SYS_ESR_FO_MASK 0x00008000 +#define SPR_SYS_ESR_FO_GET(x) (((x) >> 15) & 0x1) +#define SPR_SYS_ESR_FO_SET(x, y) (((x) & U(0xffff7fff)) | \ + ((!!(y)) << 15)) + +/* SPR User Mode Read Access */ +#define SPR_SYS_ESR_SUMRA_OFFSET 16 +#define SPR_SYS_ESR_SUMRA_MASK 0x00010000 +#define SPR_SYS_ESR_SUMRA_GET(x) (((x) >> 16) & 0x1) +#define SPR_SYS_ESR_SUMRA_SET(x, y) (((x) & U(0xfffeffff)) | \ + ((!!(y)) << 16)) + +/* Context ID */ +#define SPR_SYS_ESR_CID_LSB 28 +#define SPR_SYS_ESR_CID_MSB 31 +#define SPR_SYS_ESR_CID_BITS 4 +#define SPR_SYS_ESR_CID_MASK U(0xf0000000) +#define SPR_SYS_ESR_CID_GET(x) (((x) >> 28) & U(0x0000000f)) +#define SPR_SYS_ESR_CID_SET(x, y) (((x) & U(0x0fffffff)) | \ + ((y) << 28)) + +/* Core identifier (multicore) */ +#define SPR_SYS_COREID_INDEX U(0x080) +#define SPR_SYS_COREID_ADDR U(0x0080) + +/* Number of cores (multicore) */ +#define SPR_SYS_NUMCORES_INDEX U(0x081) +#define SPR_SYS_NUMCORES_ADDR U(0x0081) + +/* General Purpose Registers */ +#define SPR_SYS_GPR_BASE U(0x400) +#define SPR_SYS_GPR_COUNT U(0x100) +#define SPR_SYS_GPR_STEP U(0x001) +#define SPR_SYS_GPR_INDEX(N) (SPR_SYS_GPR_BASE + \ + (SPR_SYS_GPR_STEP * (N))) +#define SPR_SYS_GPR_ADDR(N) ((SPR_SYS_GROUP << SPR_GROUP_LSB) | \ + SPR_SYS_GPR_INDEX(N)) + +/******************/ +/* Data MMU Group */ +/******************/ +#define SPR_DMMU_GROUP 0x01 + +/* Instruction MMU Control Register */ +#define SPR_DMMU_DMMUCR_INDEX U(0x000) +#define SPR_DMMU_DMMUCR_ADDR U(0x0800) + +/* DTLB Flush */ +#define SPR_DMMU_DMMUCR_DTF_OFFSET 0 +#define SPR_DMMU_DMMUCR_DTF_MASK 0x00000001 +#define SPR_DMMU_DMMUCR_DTF_GET(x) (((x) >> 0) & 0x1) +#define SPR_DMMU_DMMUCR_DTF_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Page Table Base Pointer */ +#define SPR_DMMU_DMMUCR_PTBP_LSB 10 +#define SPR_DMMU_DMMUCR_PTBP_MSB 31 +#define SPR_DMMU_DMMUCR_PTBP_BITS 22 +#define SPR_DMMU_DMMUCR_PTBP_MASK U(0xfffffc00) +#define SPR_DMMU_DMMUCR_PTBP_GET(x) (((x) >> 10) & U(0x003fffff)) +#define SPR_DMMU_DMMUCR_PTBP_SET(x, y) (((x) & U(0x000003ff)) | \ + ((y) << 10)) + +/* Data MMU Protection Register */ +#define SPR_DMMU_DMMUPR_INDEX U(0x001) +#define SPR_DMMU_DMMUPR_ADDR U(0x0801) + +/* Supervisor Read Enable 1 */ +#define SPR_DMMU_DMMUPR_SRE1_OFFSET 0 +#define SPR_DMMU_DMMUPR_SRE1_MASK 0x00000001 +#define SPR_DMMU_DMMUPR_SRE1_GET(x) (((x) >> 0) & 0x1) +#define SPR_DMMU_DMMUPR_SRE1_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Supervisor Write Enable 1 */ +#define SPR_DMMU_DMMUPR_SWE1_OFFSET 1 +#define SPR_DMMU_DMMUPR_SWE1_MASK 0x00000002 +#define SPR_DMMU_DMMUPR_SWE1_GET(x) (((x) >> 1) & 0x1) +#define SPR_DMMU_DMMUPR_SWE1_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* User Read Enable 1 */ +#define SPR_DMMU_DMMUPR_URE1_OFFSET 2 +#define SPR_DMMU_DMMUPR_URE1_MASK 0x00000004 +#define SPR_DMMU_DMMUPR_URE1_GET(x) (((x) >> 2) & 0x1) +#define SPR_DMMU_DMMUPR_URE1_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* User Write Enable 1 */ +#define SPR_DMMU_DMMUPR_UWE1_OFFSET 3 +#define SPR_DMMU_DMMUPR_UWE1_MASK 0x00000008 +#define SPR_DMMU_DMMUPR_UWE1_GET(x) (((x) >> 3) & 0x1) +#define SPR_DMMU_DMMUPR_UWE1_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Supervisor Read Enable 2 */ +#define SPR_DMMU_DMMUPR_SRE2_OFFSET 4 +#define SPR_DMMU_DMMUPR_SRE2_MASK 0x00000010 +#define SPR_DMMU_DMMUPR_SRE2_GET(x) (((x) >> 4) & 0x1) +#define SPR_DMMU_DMMUPR_SRE2_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Supervisor Write Enable 2 */ +#define SPR_DMMU_DMMUPR_SWE2_OFFSET 5 +#define SPR_DMMU_DMMUPR_SWE2_MASK 0x00000020 +#define SPR_DMMU_DMMUPR_SWE2_GET(x) (((x) >> 5) & 0x1) +#define SPR_DMMU_DMMUPR_SWE2_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* User Read Enable 2 */ +#define SPR_DMMU_DMMUPR_URE2_OFFSET 6 +#define SPR_DMMU_DMMUPR_URE2_MASK 0x00000040 +#define SPR_DMMU_DMMUPR_URE2_GET(x) (((x) >> 6) & 0x1) +#define SPR_DMMU_DMMUPR_URE2_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* User Write Enable 2 */ +#define SPR_DMMU_DMMUPR_UWE2_OFFSET 7 +#define SPR_DMMU_DMMUPR_UWE2_MASK 0x00000080 +#define SPR_DMMU_DMMUPR_UWE2_GET(x) (((x) >> 7) & 0x1) +#define SPR_DMMU_DMMUPR_UWE2_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Supervisor Read Enable 3 */ +#define SPR_DMMU_DMMUPR_SRE3_OFFSET 8 +#define SPR_DMMU_DMMUPR_SRE3_MASK 0x00000100 +#define SPR_DMMU_DMMUPR_SRE3_GET(x) (((x) >> 8) & 0x1) +#define SPR_DMMU_DMMUPR_SRE3_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Supervisor Write Enable 3 */ +#define SPR_DMMU_DMMUPR_SWE3_OFFSET 9 +#define SPR_DMMU_DMMUPR_SWE3_MASK 0x00000200 +#define SPR_DMMU_DMMUPR_SWE3_GET(x) (((x) >> 9) & 0x1) +#define SPR_DMMU_DMMUPR_SWE3_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* User Read Enable 3 */ +#define SPR_DMMU_DMMUPR_URE3_OFFSET 10 +#define SPR_DMMU_DMMUPR_URE3_MASK 0x00000400 +#define SPR_DMMU_DMMUPR_URE3_GET(x) (((x) >> 10) & 0x1) +#define SPR_DMMU_DMMUPR_URE3_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* User Write Enable 3 */ +#define SPR_DMMU_DMMUPR_UWE3_OFFSET 11 +#define SPR_DMMU_DMMUPR_UWE3_MASK 0x00000800 +#define SPR_DMMU_DMMUPR_UWE3_GET(x) (((x) >> 11) & 0x1) +#define SPR_DMMU_DMMUPR_UWE3_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Supervisor Read Enable 4 */ +#define SPR_DMMU_DMMUPR_SRE4_OFFSET 12 +#define SPR_DMMU_DMMUPR_SRE4_MASK 0x00001000 +#define SPR_DMMU_DMMUPR_SRE4_GET(x) (((x) >> 12) & 0x1) +#define SPR_DMMU_DMMUPR_SRE4_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Supervisor Write Enable 4 */ +#define SPR_DMMU_DMMUPR_SWE4_OFFSET 13 +#define SPR_DMMU_DMMUPR_SWE4_MASK 0x00002000 +#define SPR_DMMU_DMMUPR_SWE4_GET(x) (((x) >> 13) & 0x1) +#define SPR_DMMU_DMMUPR_SWE4_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* User Read Enable 4 */ +#define SPR_DMMU_DMMUPR_URE4_OFFSET 14 +#define SPR_DMMU_DMMUPR_URE4_MASK 0x00004000 +#define SPR_DMMU_DMMUPR_URE4_GET(x) (((x) >> 14) & 0x1) +#define SPR_DMMU_DMMUPR_URE4_SET(x, y) (((x) & U(0xffffbfff)) | \ + ((!!(y)) << 14)) + +/* User Write Enable 4 */ +#define SPR_DMMU_DMMUPR_UWE4_OFFSET 15 +#define SPR_DMMU_DMMUPR_UWE4_MASK 0x00008000 +#define SPR_DMMU_DMMUPR_UWE4_GET(x) (((x) >> 15) & 0x1) +#define SPR_DMMU_DMMUPR_UWE4_SET(x, y) (((x) & U(0xffff7fff)) | \ + ((!!(y)) << 15)) + +/* Supervisor Read Enable 5 */ +#define SPR_DMMU_DMMUPR_SRE5_OFFSET 16 +#define SPR_DMMU_DMMUPR_SRE5_MASK 0x00010000 +#define SPR_DMMU_DMMUPR_SRE5_GET(x) (((x) >> 16) & 0x1) +#define SPR_DMMU_DMMUPR_SRE5_SET(x, y) (((x) & U(0xfffeffff)) | \ + ((!!(y)) << 16)) + +/* Supervisor Write Enable 5 */ +#define SPR_DMMU_DMMUPR_SWE5_OFFSET 17 +#define SPR_DMMU_DMMUPR_SWE5_MASK 0x00020000 +#define SPR_DMMU_DMMUPR_SWE5_GET(x) (((x) >> 17) & 0x1) +#define SPR_DMMU_DMMUPR_SWE5_SET(x, y) (((x) & U(0xfffdffff)) | \ + ((!!(y)) << 17)) + +/* User Read Enable 5 */ +#define SPR_DMMU_DMMUPR_URE5_OFFSET 18 +#define SPR_DMMU_DMMUPR_URE5_MASK 0x00040000 +#define SPR_DMMU_DMMUPR_URE5_GET(x) (((x) >> 18) & 0x1) +#define SPR_DMMU_DMMUPR_URE5_SET(x, y) (((x) & U(0xfffbffff)) | \ + ((!!(y)) << 18)) + +/* User Write Enable 5 */ +#define SPR_DMMU_DMMUPR_UWE5_OFFSET 19 +#define SPR_DMMU_DMMUPR_UWE5_MASK 0x00080000 +#define SPR_DMMU_DMMUPR_UWE5_GET(x) (((x) >> 19) & 0x1) +#define SPR_DMMU_DMMUPR_UWE5_SET(x, y) (((x) & U(0xfff7ffff)) | \ + ((!!(y)) << 19)) + +/* Supervisor Read Enable 6 */ +#define SPR_DMMU_DMMUPR_SRE6_OFFSET 20 +#define SPR_DMMU_DMMUPR_SRE6_MASK 0x00100000 +#define SPR_DMMU_DMMUPR_SRE6_GET(x) (((x) >> 20) & 0x1) +#define SPR_DMMU_DMMUPR_SRE6_SET(x, y) (((x) & U(0xffefffff)) | \ + ((!!(y)) << 20)) + +/* Supervisor Write Enable 6 */ +#define SPR_DMMU_DMMUPR_SWE6_OFFSET 21 +#define SPR_DMMU_DMMUPR_SWE6_MASK 0x00200000 +#define SPR_DMMU_DMMUPR_SWE6_GET(x) (((x) >> 21) & 0x1) +#define SPR_DMMU_DMMUPR_SWE6_SET(x, y) (((x) & U(0xffdfffff)) | \ + ((!!(y)) << 21)) + +/* User Read Enable 6 */ +#define SPR_DMMU_DMMUPR_URE6_OFFSET 22 +#define SPR_DMMU_DMMUPR_URE6_MASK 0x00400000 +#define SPR_DMMU_DMMUPR_URE6_GET(x) (((x) >> 22) & 0x1) +#define SPR_DMMU_DMMUPR_URE6_SET(x, y) (((x) & U(0xffbfffff)) | \ + ((!!(y)) << 22)) + +/* User Write Enable 6 */ +#define SPR_DMMU_DMMUPR_UWE6_OFFSET 23 +#define SPR_DMMU_DMMUPR_UWE6_MASK 0x00800000 +#define SPR_DMMU_DMMUPR_UWE6_GET(x) (((x) >> 23) & 0x1) +#define SPR_DMMU_DMMUPR_UWE6_SET(x, y) (((x) & U(0xff7fffff)) | \ + ((!!(y)) << 23)) + +/* Supervisor Read Enable 7 */ +#define SPR_DMMU_DMMUPR_SRE7_OFFSET 24 +#define SPR_DMMU_DMMUPR_SRE7_MASK 0x01000000 +#define SPR_DMMU_DMMUPR_SRE7_GET(x) (((x) >> 24) & 0x1) +#define SPR_DMMU_DMMUPR_SRE7_SET(x, y) (((x) & U(0xfeffffff)) | \ + ((!!(y)) << 24)) + +/* Supervisor Write Enable 7 */ +#define SPR_DMMU_DMMUPR_SWE7_OFFSET 25 +#define SPR_DMMU_DMMUPR_SWE7_MASK 0x02000000 +#define SPR_DMMU_DMMUPR_SWE7_GET(x) (((x) >> 25) & 0x1) +#define SPR_DMMU_DMMUPR_SWE7_SET(x, y) (((x) & U(0xfdffffff)) | \ + ((!!(y)) << 25)) + +/* User Read Enable 7 */ +#define SPR_DMMU_DMMUPR_URE7_OFFSET 26 +#define SPR_DMMU_DMMUPR_URE7_MASK 0x04000000 +#define SPR_DMMU_DMMUPR_URE7_GET(x) (((x) >> 26) & 0x1) +#define SPR_DMMU_DMMUPR_URE7_SET(x, y) (((x) & U(0xfbffffff)) | \ + ((!!(y)) << 26)) + +/* User Write Enable 7 */ +#define SPR_DMMU_DMMUPR_UWE7_OFFSET 27 +#define SPR_DMMU_DMMUPR_UWE7_MASK 0x08000000 +#define SPR_DMMU_DMMUPR_UWE7_GET(x) (((x) >> 27) & 0x1) +#define SPR_DMMU_DMMUPR_UWE7_SET(x, y) (((x) & U(0xf7ffffff)) | \ + ((!!(y)) << 27)) + +/* Data TLB Entry Invalidate Register */ +#define SPR_DMMU_DTLBEIR_INDEX U(0x002) +#define SPR_DMMU_DTLBEIR_ADDR U(0x0802) + +/* Data ATB Match Registers */ +#define SPR_DMMU_DATBMR_BASE U(0x004) +#define SPR_DMMU_DATBMR_COUNT U(0x004) +#define SPR_DMMU_DATBMR_STEP U(0x001) +#define SPR_DMMU_DATBMR_INDEX(N) (SPR_DMMU_DATBMR_BASE + \ + (SPR_DMMU_DATBMR_STEP * (N))) +#define SPR_DMMU_DATBMR_ADDR(N) ((SPR_DMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_DMMU_DATBMR_INDEX(N)) + +/* Valid */ +#define SPR_DMMU_DATBMR_V_OFFSET 0 +#define SPR_DMMU_DATBMR_V_MASK 0x00000001 +#define SPR_DMMU_DATBMR_V_GET(x) (((x) >> 0) & 0x1) +#define SPR_DMMU_DATBMR_V_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Context ID */ +#define SPR_DMMU_DATBMR_CID_LSB 1 +#define SPR_DMMU_DATBMR_CID_MSB 4 +#define SPR_DMMU_DATBMR_CID_BITS 4 +#define SPR_DMMU_DATBMR_CID_MASK U(0x0000001e) +#define SPR_DMMU_DATBMR_CID_GET(x) (((x) >> 1) & U(0x0000000f)) +#define SPR_DMMU_DATBMR_CID_SET(x, y) (((x) & U(0xffffffe1)) | \ + ((y) << 1)) + +/* Page Size */ +#define SPR_DMMU_DATBMR_PS_OFFSET 5 +#define SPR_DMMU_DATBMR_PS_MASK 0x00000020 +#define SPR_DMMU_DATBMR_PS_GET(x) (((x) >> 5) & 0x1) +#define SPR_DMMU_DATBMR_PS_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Virtual Page Number */ +#define SPR_DMMU_DATBMR_VPN_LSB 10 +#define SPR_DMMU_DATBMR_VPN_MSB 31 +#define SPR_DMMU_DATBMR_VPN_BITS 22 +#define SPR_DMMU_DATBMR_VPN_MASK U(0xfffffc00) +#define SPR_DMMU_DATBMR_VPN_GET(x) (((x) >> 10) & U(0x003fffff)) +#define SPR_DMMU_DATBMR_VPN_SET(x, y) (((x) & U(0x000003ff)) | \ + ((y) << 10)) + +/* Data ATB Translate Registers */ +#define SPR_DMMU_DATBTR_BASE U(0x008) +#define SPR_DMMU_DATBTR_COUNT U(0x004) +#define SPR_DMMU_DATBTR_STEP U(0x001) +#define SPR_DMMU_DATBTR_INDEX(N) (SPR_DMMU_DATBTR_BASE + \ + (SPR_DMMU_DATBTR_STEP * (N))) +#define SPR_DMMU_DATBTR_ADDR(N) ((SPR_DMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_DMMU_DATBTR_INDEX(N)) + +/* Cache Coherency */ +#define SPR_DMMU_DATBTR_CC_OFFSET 0 +#define SPR_DMMU_DATBTR_CC_MASK 0x00000001 +#define SPR_DMMU_DATBTR_CC_GET(x) (((x) >> 0) & 0x1) +#define SPR_DMMU_DATBTR_CC_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Cache Inhibit */ +#define SPR_DMMU_DATBTR_CI_OFFSET 1 +#define SPR_DMMU_DATBTR_CI_MASK 0x00000002 +#define SPR_DMMU_DATBTR_CI_GET(x) (((x) >> 1) & 0x1) +#define SPR_DMMU_DATBTR_CI_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Write-back Cache */ +#define SPR_DMMU_DATBTR_WBC_OFFSET 2 +#define SPR_DMMU_DATBTR_WBC_MASK 0x00000004 +#define SPR_DMMU_DATBTR_WBC_GET(x) (((x) >> 2) & 0x1) +#define SPR_DMMU_DATBTR_WBC_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Weakly-ordered Memory */ +#define SPR_DMMU_DATBTR_WOM_OFFSET 3 +#define SPR_DMMU_DATBTR_WOM_MASK 0x00000008 +#define SPR_DMMU_DATBTR_WOM_GET(x) (((x) >> 3) & 0x1) +#define SPR_DMMU_DATBTR_WOM_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Accessed */ +#define SPR_DMMU_DATBTR_A_OFFSET 4 +#define SPR_DMMU_DATBTR_A_MASK 0x00000010 +#define SPR_DMMU_DATBTR_A_GET(x) (((x) >> 4) & 0x1) +#define SPR_DMMU_DATBTR_A_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Dirty */ +#define SPR_DMMU_DATBTR_D_OFFSET 5 +#define SPR_DMMU_DATBTR_D_MASK 0x00000020 +#define SPR_DMMU_DATBTR_D_GET(x) (((x) >> 5) & 0x1) +#define SPR_DMMU_DATBTR_D_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Supervisor Read Enable */ +#define SPR_DMMU_DATBTR_SRE_OFFSET 6 +#define SPR_DMMU_DATBTR_SRE_MASK 0x00000040 +#define SPR_DMMU_DATBTR_SRE_GET(x) (((x) >> 6) & 0x1) +#define SPR_DMMU_DATBTR_SRE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Supervisor Write Enable */ +#define SPR_DMMU_DATBTR_SWE_OFFSET 7 +#define SPR_DMMU_DATBTR_SWE_MASK 0x00000080 +#define SPR_DMMU_DATBTR_SWE_GET(x) (((x) >> 7) & 0x1) +#define SPR_DMMU_DATBTR_SWE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* User Read Enable */ +#define SPR_DMMU_DATBTR_URE_OFFSET 8 +#define SPR_DMMU_DATBTR_URE_MASK 0x00000100 +#define SPR_DMMU_DATBTR_URE_GET(x) (((x) >> 8) & 0x1) +#define SPR_DMMU_DATBTR_URE_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* User Write Enable */ +#define SPR_DMMU_DATBTR_UWE_OFFSET 9 +#define SPR_DMMU_DATBTR_UWE_MASK 0x00000200 +#define SPR_DMMU_DATBTR_UWE_GET(x) (((x) >> 9) & 0x1) +#define SPR_DMMU_DATBTR_UWE_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Physical Page Number */ +#define SPR_DMMU_DATBTR_PPN_LSB 10 +#define SPR_DMMU_DATBTR_PPN_MSB 31 +#define SPR_DMMU_DATBTR_PPN_BITS 22 +#define SPR_DMMU_DATBTR_PPN_MASK U(0xfffffc00) +#define SPR_DMMU_DATBTR_PPN_GET(x) (((x) >> 10) & U(0x003fffff)) +#define SPR_DMMU_DATBTR_PPN_SET(x, y) (((x) & U(0x000003ff)) | \ + ((y) << 10)) + +/* Data TLB */ +#define SPR_DMMU_DTLBW_BASE U(0x200) +#define SPR_DMMU_DTLBW_COUNT U(0x004) +#define SPR_DMMU_DTLBW_STEP U(0x100) +#define SPR_DMMU_DTLBW_SUBBASE(N0) (SPR_DMMU_DTLBW_BASE + \ + (SPR_DMMU_DTLBW_STEP * (N0))) + +/* Data TLB Match Registers */ +#define SPR_DMMU_DTLBW_MR_BASE U(0x000) +#define SPR_DMMU_DTLBW_MR_COUNT U(0x080) +#define SPR_DMMU_DTLBW_MR_STEP U(0x001) + +#define SPR_DMMU_DTLBW_MR_INDEX(N0, N1) (SPR_DMMU_DTLBW_SUBBASE(N0) + \ + SPR_DMMU_DTLBW_MR_BASE + \ + (SPR_DMMU_DTLBW_MR_STEP * (N1))) +#define SPR_DMMU_DTLBW_MR_ADDR(N0, N1) ((SPR_DMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_DMMU_DTLBW_MR_INDEX(N0, N1)) + +/* Valid */ +#define SPR_DMMU_DTLBW_MR_V_OFFSET 0 +#define SPR_DMMU_DTLBW_MR_V_MASK 0x00000001 +#define SPR_DMMU_DTLBW_MR_V_GET(x) (((x) >> 0) & 0x1) +#define SPR_DMMU_DTLBW_MR_V_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Page Level 1 */ +#define SPR_DMMU_DTLBW_MR_PL1_OFFSET 1 +#define SPR_DMMU_DTLBW_MR_PL1_MASK 0x00000002 +#define SPR_DMMU_DTLBW_MR_PL1_GET(x) (((x) >> 1) & 0x1) +#define SPR_DMMU_DTLBW_MR_PL1_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Context ID */ +#define SPR_DMMU_DTLBW_MR_CID_LSB 2 +#define SPR_DMMU_DTLBW_MR_CID_MSB 5 +#define SPR_DMMU_DTLBW_MR_CID_BITS 4 +#define SPR_DMMU_DTLBW_MR_CID_MASK U(0x0000003c) +#define SPR_DMMU_DTLBW_MR_CID_GET(x) (((x) >> 2) & U(0x0000000f)) +#define SPR_DMMU_DTLBW_MR_CID_SET(x, y) (((x) & U(0xffffffc3)) | \ + ((y) << 2)) + +/* Least Recently Used */ +#define SPR_DMMU_DTLBW_MR_LRU_LSB 6 +#define SPR_DMMU_DTLBW_MR_LRU_MSB 7 +#define SPR_DMMU_DTLBW_MR_LRU_BITS 2 +#define SPR_DMMU_DTLBW_MR_LRU_MASK U(0x000000c0) +#define SPR_DMMU_DTLBW_MR_LRU_GET(x) (((x) >> 6) & U(0x00000003)) +#define SPR_DMMU_DTLBW_MR_LRU_SET(x, y) (((x) & U(0xffffff3f)) | \ + ((y) << 6)) + +/* Virtual Page Number */ +#define SPR_DMMU_DTLBW_MR_VPN_LSB 13 +#define SPR_DMMU_DTLBW_MR_VPN_MSB 31 +#define SPR_DMMU_DTLBW_MR_VPN_BITS 19 +#define SPR_DMMU_DTLBW_MR_VPN_MASK U(0xffffe000) +#define SPR_DMMU_DTLBW_MR_VPN_GET(x) (((x) >> 13) & U(0x0007ffff)) +#define SPR_DMMU_DTLBW_MR_VPN_SET(x, y) (((x) & U(0x00001fff)) | \ + ((y) << 13)) + +/* Data TLB Translate Registers */ +#define SPR_DMMU_DTLBW_TR_BASE U(0x080) +#define SPR_DMMU_DTLBW_TR_COUNT U(0x080) +#define SPR_DMMU_DTLBW_TR_STEP U(0x001) + +#define SPR_DMMU_DTLBW_TR_INDEX(N0, N1) (SPR_DMMU_DTLBW_SUBBASE(N0) + \ + SPR_DMMU_DTLBW_TR_BASE + \ + (SPR_DMMU_DTLBW_TR_STEP * (N1))) +#define SPR_DMMU_DTLBW_TR_ADDR(N0, N1) ((SPR_DMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_DMMU_DTLBW_TR_INDEX(N0, N1)) + +/* Cache Coherency */ +#define SPR_DMMU_DTLBW_TR_CC_OFFSET 0 +#define SPR_DMMU_DTLBW_TR_CC_MASK 0x00000001 +#define SPR_DMMU_DTLBW_TR_CC_GET(x) (((x) >> 0) & 0x1) +#define SPR_DMMU_DTLBW_TR_CC_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Cache Inhibit */ +#define SPR_DMMU_DTLBW_TR_CI_OFFSET 1 +#define SPR_DMMU_DTLBW_TR_CI_MASK 0x00000002 +#define SPR_DMMU_DTLBW_TR_CI_GET(x) (((x) >> 1) & 0x1) +#define SPR_DMMU_DTLBW_TR_CI_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Write-back Cache */ +#define SPR_DMMU_DTLBW_TR_WBC_OFFSET 2 +#define SPR_DMMU_DTLBW_TR_WBC_MASK 0x00000004 +#define SPR_DMMU_DTLBW_TR_WBC_GET(x) (((x) >> 2) & 0x1) +#define SPR_DMMU_DTLBW_TR_WBC_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Weakly-ordered Memory */ +#define SPR_DMMU_DTLBW_TR_WOM_OFFSET 3 +#define SPR_DMMU_DTLBW_TR_WOM_MASK 0x00000008 +#define SPR_DMMU_DTLBW_TR_WOM_GET(x) (((x) >> 3) & 0x1) +#define SPR_DMMU_DTLBW_TR_WOM_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Accessed */ +#define SPR_DMMU_DTLBW_TR_A_OFFSET 4 +#define SPR_DMMU_DTLBW_TR_A_MASK 0x00000010 +#define SPR_DMMU_DTLBW_TR_A_GET(x) (((x) >> 4) & 0x1) +#define SPR_DMMU_DTLBW_TR_A_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Dirty */ +#define SPR_DMMU_DTLBW_TR_D_OFFSET 5 +#define SPR_DMMU_DTLBW_TR_D_MASK 0x00000020 +#define SPR_DMMU_DTLBW_TR_D_GET(x) (((x) >> 5) & 0x1) +#define SPR_DMMU_DTLBW_TR_D_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* User Read Enable */ +#define SPR_DMMU_DTLBW_TR_URE_OFFSET 6 +#define SPR_DMMU_DTLBW_TR_URE_MASK 0x00000040 +#define SPR_DMMU_DTLBW_TR_URE_GET(x) (((x) >> 6) & 0x1) +#define SPR_DMMU_DTLBW_TR_URE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* User Write Enable */ +#define SPR_DMMU_DTLBW_TR_UWE_OFFSET 7 +#define SPR_DMMU_DTLBW_TR_UWE_MASK 0x00000080 +#define SPR_DMMU_DTLBW_TR_UWE_GET(x) (((x) >> 7) & 0x1) +#define SPR_DMMU_DTLBW_TR_UWE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Supervisor Read Enable */ +#define SPR_DMMU_DTLBW_TR_SRE_OFFSET 8 +#define SPR_DMMU_DTLBW_TR_SRE_MASK 0x00000100 +#define SPR_DMMU_DTLBW_TR_SRE_GET(x) (((x) >> 8) & 0x1) +#define SPR_DMMU_DTLBW_TR_SRE_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* Supervisor Write Enable */ +#define SPR_DMMU_DTLBW_TR_SWE_OFFSET 9 +#define SPR_DMMU_DTLBW_TR_SWE_MASK 0x00000200 +#define SPR_DMMU_DTLBW_TR_SWE_GET(x) (((x) >> 9) & 0x1) +#define SPR_DMMU_DTLBW_TR_SWE_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Physical Page Number */ +#define SPR_DMMU_DTLBW_TR_PPN_LSB 13 +#define SPR_DMMU_DTLBW_TR_PPN_MSB 31 +#define SPR_DMMU_DTLBW_TR_PPN_BITS 19 +#define SPR_DMMU_DTLBW_TR_PPN_MASK U(0xffffe000) +#define SPR_DMMU_DTLBW_TR_PPN_GET(x) (((x) >> 13) & U(0x0007ffff)) +#define SPR_DMMU_DTLBW_TR_PPN_SET(x, y) (((x) & U(0x00001fff)) | \ + ((y) << 13)) + +/*************************/ +/* Instruction MMU Group */ +/*************************/ +#define SPR_IMMU_GROUP 0x02 + +/* Instruction MMU Control Register */ +#define SPR_IMMU_IMMUCR_INDEX U(0x000) +#define SPR_IMMU_IMMUCR_ADDR U(0x1000) + +/* ITLB Flush */ +#define SPR_IMMU_IMMUCR_ITF_OFFSET 0 +#define SPR_IMMU_IMMUCR_ITF_MASK 0x00000001 +#define SPR_IMMU_IMMUCR_ITF_GET(x) (((x) >> 0) & 0x1) +#define SPR_IMMU_IMMUCR_ITF_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Page Table Base Pointer */ +#define SPR_IMMU_IMMUCR_PTBP_LSB 10 +#define SPR_IMMU_IMMUCR_PTBP_MSB 31 +#define SPR_IMMU_IMMUCR_PTBP_BITS 22 +#define SPR_IMMU_IMMUCR_PTBP_MASK U(0xfffffc00) +#define SPR_IMMU_IMMUCR_PTBP_GET(x) (((x) >> 10) & U(0x003fffff)) +#define SPR_IMMU_IMMUCR_PTBP_SET(x, y) (((x) & U(0x000003ff)) | \ + ((y) << 10)) + +/* Instruction MMU Protection Register */ +#define SPR_IMMU_IMMUPR_INDEX U(0x001) +#define SPR_IMMU_IMMUPR_ADDR U(0x1001) + +/* Supervisor Execute Enable 1 */ +#define SPR_IMMU_IMMUPR_SXE1_OFFSET 0 +#define SPR_IMMU_IMMUPR_SXE1_MASK 0x00000001 +#define SPR_IMMU_IMMUPR_SXE1_GET(x) (((x) >> 0) & 0x1) +#define SPR_IMMU_IMMUPR_SXE1_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* User Execute Enable 1 */ +#define SPR_IMMU_IMMUPR_UXE1_OFFSET 1 +#define SPR_IMMU_IMMUPR_UXE1_MASK 0x00000002 +#define SPR_IMMU_IMMUPR_UXE1_GET(x) (((x) >> 1) & 0x1) +#define SPR_IMMU_IMMUPR_UXE1_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Supervisor Execute Enable 2 */ +#define SPR_IMMU_IMMUPR_SXE2_OFFSET 2 +#define SPR_IMMU_IMMUPR_SXE2_MASK 0x00000004 +#define SPR_IMMU_IMMUPR_SXE2_GET(x) (((x) >> 2) & 0x1) +#define SPR_IMMU_IMMUPR_SXE2_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* User Execute Enable 2 */ +#define SPR_IMMU_IMMUPR_UXE2_OFFSET 3 +#define SPR_IMMU_IMMUPR_UXE2_MASK 0x00000008 +#define SPR_IMMU_IMMUPR_UXE2_GET(x) (((x) >> 3) & 0x1) +#define SPR_IMMU_IMMUPR_UXE2_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Supervisor Execute Enable 3 */ +#define SPR_IMMU_IMMUPR_SXE3_OFFSET 4 +#define SPR_IMMU_IMMUPR_SXE3_MASK 0x00000010 +#define SPR_IMMU_IMMUPR_SXE3_GET(x) (((x) >> 4) & 0x1) +#define SPR_IMMU_IMMUPR_SXE3_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* User Execute Enable 3 */ +#define SPR_IMMU_IMMUPR_UXE3_OFFSET 5 +#define SPR_IMMU_IMMUPR_UXE3_MASK 0x00000020 +#define SPR_IMMU_IMMUPR_UXE3_GET(x) (((x) >> 5) & 0x1) +#define SPR_IMMU_IMMUPR_UXE3_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Supervisor Execute Enable 4 */ +#define SPR_IMMU_IMMUPR_SXE4_OFFSET 6 +#define SPR_IMMU_IMMUPR_SXE4_MASK 0x00000040 +#define SPR_IMMU_IMMUPR_SXE4_GET(x) (((x) >> 6) & 0x1) +#define SPR_IMMU_IMMUPR_SXE4_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* User Execute Enable 4 */ +#define SPR_IMMU_IMMUPR_UXE4_OFFSET 7 +#define SPR_IMMU_IMMUPR_UXE4_MASK 0x00000080 +#define SPR_IMMU_IMMUPR_UXE4_GET(x) (((x) >> 7) & 0x1) +#define SPR_IMMU_IMMUPR_UXE4_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Supervisor Execute Enable 5 */ +#define SPR_IMMU_IMMUPR_SXE5_OFFSET 8 +#define SPR_IMMU_IMMUPR_SXE5_MASK 0x00000100 +#define SPR_IMMU_IMMUPR_SXE5_GET(x) (((x) >> 8) & 0x1) +#define SPR_IMMU_IMMUPR_SXE5_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* User Execute Enable 5 */ +#define SPR_IMMU_IMMUPR_UXE5_OFFSET 9 +#define SPR_IMMU_IMMUPR_UXE5_MASK 0x00000200 +#define SPR_IMMU_IMMUPR_UXE5_GET(x) (((x) >> 9) & 0x1) +#define SPR_IMMU_IMMUPR_UXE5_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Supervisor Execute Enable 6 */ +#define SPR_IMMU_IMMUPR_SXE6_OFFSET 10 +#define SPR_IMMU_IMMUPR_SXE6_MASK 0x00000400 +#define SPR_IMMU_IMMUPR_SXE6_GET(x) (((x) >> 10) & 0x1) +#define SPR_IMMU_IMMUPR_SXE6_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* User Execute Enable 6 */ +#define SPR_IMMU_IMMUPR_UXE6_OFFSET 11 +#define SPR_IMMU_IMMUPR_UXE6_MASK 0x00000800 +#define SPR_IMMU_IMMUPR_UXE6_GET(x) (((x) >> 11) & 0x1) +#define SPR_IMMU_IMMUPR_UXE6_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Supervisor Execute Enable 7 */ +#define SPR_IMMU_IMMUPR_SXE7_OFFSET 12 +#define SPR_IMMU_IMMUPR_SXE7_MASK 0x00001000 +#define SPR_IMMU_IMMUPR_SXE7_GET(x) (((x) >> 12) & 0x1) +#define SPR_IMMU_IMMUPR_SXE7_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* User Execute Enable 7 */ +#define SPR_IMMU_IMMUPR_UXE7_OFFSET 13 +#define SPR_IMMU_IMMUPR_UXE7_MASK 0x00002000 +#define SPR_IMMU_IMMUPR_UXE7_GET(x) (((x) >> 13) & 0x1) +#define SPR_IMMU_IMMUPR_UXE7_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* Instruction TLB Entry Invalidate Register */ +#define SPR_IMMU_ITLBEIR_INDEX U(0x002) +#define SPR_IMMU_ITLBEIR_ADDR U(0x1002) + +/* Instruction ATB Match Registers */ +#define SPR_IMMU_IATBMR_BASE U(0x004) +#define SPR_IMMU_IATBMR_COUNT U(0x004) +#define SPR_IMMU_IATBMR_STEP U(0x001) +#define SPR_IMMU_IATBMR_INDEX(N) (SPR_IMMU_IATBMR_BASE + \ + (SPR_IMMU_IATBMR_STEP * (N))) +#define SPR_IMMU_IATBMR_ADDR(N) ((SPR_IMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_IMMU_IATBMR_INDEX(N)) + +/* Valid */ +#define SPR_IMMU_IATBMR_V_OFFSET 0 +#define SPR_IMMU_IATBMR_V_MASK 0x00000001 +#define SPR_IMMU_IATBMR_V_GET(x) (((x) >> 0) & 0x1) +#define SPR_IMMU_IATBMR_V_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Context ID */ +#define SPR_IMMU_IATBMR_CID_LSB 1 +#define SPR_IMMU_IATBMR_CID_MSB 4 +#define SPR_IMMU_IATBMR_CID_BITS 4 +#define SPR_IMMU_IATBMR_CID_MASK U(0x0000001e) +#define SPR_IMMU_IATBMR_CID_GET(x) (((x) >> 1) & U(0x0000000f)) +#define SPR_IMMU_IATBMR_CID_SET(x, y) (((x) & U(0xffffffe1)) | \ + ((y) << 1)) + +/* Page Size */ +#define SPR_IMMU_IATBMR_PS_OFFSET 5 +#define SPR_IMMU_IATBMR_PS_MASK 0x00000020 +#define SPR_IMMU_IATBMR_PS_GET(x) (((x) >> 5) & 0x1) +#define SPR_IMMU_IATBMR_PS_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Virtual Page Number */ +#define SPR_IMMU_IATBMR_VPN_LSB 10 +#define SPR_IMMU_IATBMR_VPN_MSB 31 +#define SPR_IMMU_IATBMR_VPN_BITS 22 +#define SPR_IMMU_IATBMR_VPN_MASK U(0xfffffc00) +#define SPR_IMMU_IATBMR_VPN_GET(x) (((x) >> 10) & U(0x003fffff)) +#define SPR_IMMU_IATBMR_VPN_SET(x, y) (((x) & U(0x000003ff)) | \ + ((y) << 10)) + +/* Instruction ATB Translate Registers */ +#define SPR_IMMU_IATBTR_BASE U(0x008) +#define SPR_IMMU_IATBTR_COUNT U(0x004) +#define SPR_IMMU_IATBTR_STEP U(0x001) +#define SPR_IMMU_IATBTR_INDEX(N) (SPR_IMMU_IATBTR_BASE + \ + (SPR_IMMU_IATBTR_STEP * (N))) +#define SPR_IMMU_IATBTR_ADDR(N) ((SPR_IMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_IMMU_IATBTR_INDEX(N)) + +/* Cache Coherency */ +#define SPR_IMMU_IATBTR_CC_OFFSET 0 +#define SPR_IMMU_IATBTR_CC_MASK 0x00000001 +#define SPR_IMMU_IATBTR_CC_GET(x) (((x) >> 0) & 0x1) +#define SPR_IMMU_IATBTR_CC_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Cache Inhibit */ +#define SPR_IMMU_IATBTR_CI_OFFSET 1 +#define SPR_IMMU_IATBTR_CI_MASK 0x00000002 +#define SPR_IMMU_IATBTR_CI_GET(x) (((x) >> 1) & 0x1) +#define SPR_IMMU_IATBTR_CI_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Write-back Cache */ +#define SPR_IMMU_IATBTR_WBC_OFFSET 2 +#define SPR_IMMU_IATBTR_WBC_MASK 0x00000004 +#define SPR_IMMU_IATBTR_WBC_GET(x) (((x) >> 2) & 0x1) +#define SPR_IMMU_IATBTR_WBC_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Weakly-ordered Memory */ +#define SPR_IMMU_IATBTR_WOM_OFFSET 3 +#define SPR_IMMU_IATBTR_WOM_MASK 0x00000008 +#define SPR_IMMU_IATBTR_WOM_GET(x) (((x) >> 3) & 0x1) +#define SPR_IMMU_IATBTR_WOM_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Accessed */ +#define SPR_IMMU_IATBTR_A_OFFSET 4 +#define SPR_IMMU_IATBTR_A_MASK 0x00000010 +#define SPR_IMMU_IATBTR_A_GET(x) (((x) >> 4) & 0x1) +#define SPR_IMMU_IATBTR_A_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Dirty */ +#define SPR_IMMU_IATBTR_D_OFFSET 5 +#define SPR_IMMU_IATBTR_D_MASK 0x00000020 +#define SPR_IMMU_IATBTR_D_GET(x) (((x) >> 5) & 0x1) +#define SPR_IMMU_IATBTR_D_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Supervisor Execute Enable */ +#define SPR_IMMU_IATBTR_SRE_OFFSET 6 +#define SPR_IMMU_IATBTR_SRE_MASK 0x00000040 +#define SPR_IMMU_IATBTR_SRE_GET(x) (((x) >> 6) & 0x1) +#define SPR_IMMU_IATBTR_SRE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* User Execute Enable */ +#define SPR_IMMU_IATBTR_URE_OFFSET 7 +#define SPR_IMMU_IATBTR_URE_MASK 0x00000080 +#define SPR_IMMU_IATBTR_URE_GET(x) (((x) >> 7) & 0x1) +#define SPR_IMMU_IATBTR_URE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Physical Page Number */ +#define SPR_IMMU_IATBTR_PPN_LSB 10 +#define SPR_IMMU_IATBTR_PPN_MSB 31 +#define SPR_IMMU_IATBTR_PPN_BITS 22 +#define SPR_IMMU_IATBTR_PPN_MASK U(0xfffffc00) +#define SPR_IMMU_IATBTR_PPN_GET(x) (((x) >> 10) & U(0x003fffff)) +#define SPR_IMMU_IATBTR_PPN_SET(x, y) (((x) & U(0x000003ff)) | \ + ((y) << 10)) + +/* Instruction TLB */ +#define SPR_IMMU_ITLBW_BASE U(0x200) +#define SPR_IMMU_ITLBW_COUNT U(0x004) +#define SPR_IMMU_ITLBW_STEP U(0x100) +#define SPR_IMMU_ITLBW_SUBBASE(N0) (SPR_IMMU_ITLBW_BASE + \ + (SPR_IMMU_ITLBW_STEP * (N0))) + +/* Instruction TLB Match Registers */ +#define SPR_IMMU_ITLBW_MR_BASE U(0x000) +#define SPR_IMMU_ITLBW_MR_COUNT U(0x080) +#define SPR_IMMU_ITLBW_MR_STEP U(0x001) + +#define SPR_IMMU_ITLBW_MR_INDEX(N0, N1) (SPR_IMMU_ITLBW_SUBBASE(N0) + \ + SPR_IMMU_ITLBW_MR_BASE + \ + (SPR_IMMU_ITLBW_MR_STEP * (N1))) +#define SPR_IMMU_ITLBW_MR_ADDR(N0, N1) ((SPR_IMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_IMMU_ITLBW_MR_INDEX(N0, N1)) + +/* Valid */ +#define SPR_IMMU_ITLBW_MR_V_OFFSET 0 +#define SPR_IMMU_ITLBW_MR_V_MASK 0x00000001 +#define SPR_IMMU_ITLBW_MR_V_GET(x) (((x) >> 0) & 0x1) +#define SPR_IMMU_ITLBW_MR_V_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Page Level 1 */ +#define SPR_IMMU_ITLBW_MR_PL1_OFFSET 1 +#define SPR_IMMU_ITLBW_MR_PL1_MASK 0x00000002 +#define SPR_IMMU_ITLBW_MR_PL1_GET(x) (((x) >> 1) & 0x1) +#define SPR_IMMU_ITLBW_MR_PL1_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Context ID */ +#define SPR_IMMU_ITLBW_MR_CID_LSB 2 +#define SPR_IMMU_ITLBW_MR_CID_MSB 5 +#define SPR_IMMU_ITLBW_MR_CID_BITS 4 +#define SPR_IMMU_ITLBW_MR_CID_MASK U(0x0000003c) +#define SPR_IMMU_ITLBW_MR_CID_GET(x) (((x) >> 2) & U(0x0000000f)) +#define SPR_IMMU_ITLBW_MR_CID_SET(x, y) (((x) & U(0xffffffc3)) | \ + ((y) << 2)) + +/* Least Recently Used */ +#define SPR_IMMU_ITLBW_MR_LRU_LSB 6 +#define SPR_IMMU_ITLBW_MR_LRU_MSB 7 +#define SPR_IMMU_ITLBW_MR_LRU_BITS 2 +#define SPR_IMMU_ITLBW_MR_LRU_MASK U(0x000000c0) +#define SPR_IMMU_ITLBW_MR_LRU_GET(x) (((x) >> 6) & U(0x00000003)) +#define SPR_IMMU_ITLBW_MR_LRU_SET(x, y) (((x) & U(0xffffff3f)) | \ + ((y) << 6)) + +/* Virtual Page Number */ +#define SPR_IMMU_ITLBW_MR_VPN_LSB 13 +#define SPR_IMMU_ITLBW_MR_VPN_MSB 31 +#define SPR_IMMU_ITLBW_MR_VPN_BITS 19 +#define SPR_IMMU_ITLBW_MR_VPN_MASK U(0xffffe000) +#define SPR_IMMU_ITLBW_MR_VPN_GET(x) (((x) >> 13) & U(0x0007ffff)) +#define SPR_IMMU_ITLBW_MR_VPN_SET(x, y) (((x) & U(0x00001fff)) | \ + ((y) << 13)) + +/* Instruction TLB Translate Registers */ +#define SPR_IMMU_ITLBW_TR_BASE U(0x080) +#define SPR_IMMU_ITLBW_TR_COUNT U(0x080) +#define SPR_IMMU_ITLBW_TR_STEP U(0x001) + +#define SPR_IMMU_ITLBW_TR_INDEX(N0, N1) (SPR_IMMU_ITLBW_SUBBASE(N0) + \ + SPR_IMMU_ITLBW_TR_BASE + \ + (SPR_IMMU_ITLBW_TR_STEP * (N1))) +#define SPR_IMMU_ITLBW_TR_ADDR(N0, N1) ((SPR_IMMU_GROUP << SPR_GROUP_LSB) | \ + SPR_IMMU_ITLBW_TR_INDEX(N0, N1)) + +/* Cache Coherency */ +#define SPR_IMMU_ITLBW_TR_CC_OFFSET 0 +#define SPR_IMMU_ITLBW_TR_CC_MASK 0x00000001 +#define SPR_IMMU_ITLBW_TR_CC_GET(x) (((x) >> 0) & 0x1) +#define SPR_IMMU_ITLBW_TR_CC_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Cache Inhibit */ +#define SPR_IMMU_ITLBW_TR_CI_OFFSET 1 +#define SPR_IMMU_ITLBW_TR_CI_MASK 0x00000002 +#define SPR_IMMU_ITLBW_TR_CI_GET(x) (((x) >> 1) & 0x1) +#define SPR_IMMU_ITLBW_TR_CI_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Write-back Cache */ +#define SPR_IMMU_ITLBW_TR_WBC_OFFSET 2 +#define SPR_IMMU_ITLBW_TR_WBC_MASK 0x00000004 +#define SPR_IMMU_ITLBW_TR_WBC_GET(x) (((x) >> 2) & 0x1) +#define SPR_IMMU_ITLBW_TR_WBC_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Weakly-ordered Memory */ +#define SPR_IMMU_ITLBW_TR_WOM_OFFSET 3 +#define SPR_IMMU_ITLBW_TR_WOM_MASK 0x00000008 +#define SPR_IMMU_ITLBW_TR_WOM_GET(x) (((x) >> 3) & 0x1) +#define SPR_IMMU_ITLBW_TR_WOM_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Accessed */ +#define SPR_IMMU_ITLBW_TR_A_OFFSET 4 +#define SPR_IMMU_ITLBW_TR_A_MASK 0x00000010 +#define SPR_IMMU_ITLBW_TR_A_GET(x) (((x) >> 4) & 0x1) +#define SPR_IMMU_ITLBW_TR_A_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Dirty */ +#define SPR_IMMU_ITLBW_TR_D_OFFSET 5 +#define SPR_IMMU_ITLBW_TR_D_MASK 0x00000020 +#define SPR_IMMU_ITLBW_TR_D_GET(x) (((x) >> 5) & 0x1) +#define SPR_IMMU_ITLBW_TR_D_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* User Execute Enable */ +#define SPR_IMMU_ITLBW_TR_UXE_OFFSET 6 +#define SPR_IMMU_ITLBW_TR_UXE_MASK 0x00000040 +#define SPR_IMMU_ITLBW_TR_UXE_GET(x) (((x) >> 6) & 0x1) +#define SPR_IMMU_ITLBW_TR_UXE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Supervisor Execute Enable */ +#define SPR_IMMU_ITLBW_TR_SXE_OFFSET 7 +#define SPR_IMMU_ITLBW_TR_SXE_MASK 0x00000080 +#define SPR_IMMU_ITLBW_TR_SXE_GET(x) (((x) >> 7) & 0x1) +#define SPR_IMMU_ITLBW_TR_SXE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* Physical Page Number */ +#define SPR_IMMU_ITLBW_TR_PPN_LSB 13 +#define SPR_IMMU_ITLBW_TR_PPN_MSB 31 +#define SPR_IMMU_ITLBW_TR_PPN_BITS 19 +#define SPR_IMMU_ITLBW_TR_PPN_MASK U(0xffffe000) +#define SPR_IMMU_ITLBW_TR_PPN_GET(x) (((x) >> 13) & U(0x0007ffff)) +#define SPR_IMMU_ITLBW_TR_PPN_SET(x, y) (((x) & U(0x00001fff)) | \ + ((y) << 13)) + +/********************/ +/* Data Cache Group */ +/********************/ +#define SPR_DCACHE_GROUP 0x03 + +/* Data Cache Control Register */ +#define SPR_DCACHE_DCCR_INDEX U(0x000) +#define SPR_DCACHE_DCCR_ADDR U(0x1800) + +/* Enable Ways */ +#define SPR_DCACHE_DCCR_EW_LSB 0 +#define SPR_DCACHE_DCCR_EW_MSB 7 +#define SPR_DCACHE_DCCR_EW_BITS 8 +#define SPR_DCACHE_DCCR_EW_MASK U(0x000000ff) +#define SPR_DCACHE_DCCR_EW_GET(x) (((x) >> 0) & U(0x000000ff)) +#define SPR_DCACHE_DCCR_EW_SET(x, y) (((x) & U(0xffffff00)) | \ + ((y) << 0)) + +/* Data Cache Block Prefetch Register */ +#define SPR_DCACHE_DCBPR_INDEX U(0x001) +#define SPR_DCACHE_DCBPR_ADDR U(0x1801) + +/* Data Cache Block Flush Register */ +#define SPR_DCACHE_DCBFR_INDEX U(0x002) +#define SPR_DCACHE_DCBFR_ADDR U(0x1802) + +/* Data Cache Block Invalidate Register */ +#define SPR_DCACHE_DCBIR_INDEX U(0x003) +#define SPR_DCACHE_DCBIR_ADDR U(0x1803) + +/* Data Cache Block Write-back Register */ +#define SPR_DCACHE_DCBWR_INDEX U(0x004) +#define SPR_DCACHE_DCBWR_ADDR U(0x1804) + +/* Data Cache Block Lock Register */ +#define SPR_DCACHE_DCBLR_INDEX U(0x005) +#define SPR_DCACHE_DCBLR_ADDR U(0x1805) + +/***************************/ +/* Instruction Cache Group */ +/***************************/ +#define SPR_ICACHE_GROUP 0x04 + +/* Instruction Cache Control Register */ +#define SPR_ICACHE_ICCR_INDEX U(0x000) +#define SPR_ICACHE_ICCR_ADDR U(0x2000) + +/* Enable Ways */ +#define SPR_ICACHE_ICCR_EW_LSB 0 +#define SPR_ICACHE_ICCR_EW_MSB 7 +#define SPR_ICACHE_ICCR_EW_BITS 8 +#define SPR_ICACHE_ICCR_EW_MASK U(0x000000ff) +#define SPR_ICACHE_ICCR_EW_GET(x) (((x) >> 0) & U(0x000000ff)) +#define SPR_ICACHE_ICCR_EW_SET(x, y) (((x) & U(0xffffff00)) | \ + ((y) << 0)) + +/* Instruction Cache Block Prefetch Register */ +#define SPR_ICACHE_ICBPR_INDEX U(0x001) +#define SPR_ICACHE_ICBPR_ADDR U(0x2001) + +/* Instruction Cache Block Invalidate Register */ +#define SPR_ICACHE_ICBIR_INDEX U(0x002) +#define SPR_ICACHE_ICBIR_ADDR U(0x2002) + +/* Instruction Cache Block Lock Register */ +#define SPR_ICACHE_ICBLR_INDEX U(0x003) +#define SPR_ICACHE_ICBLR_ADDR U(0x2003) + +/*********************************/ +/* Multiply and Accumulate Group */ +/*********************************/ +#define SPR_MAC_GROUP 0x05 + +/* MAC Result Low Word */ +#define SPR_MAC_MACLO_INDEX U(0x001) +#define SPR_MAC_MACLO_ADDR U(0x2801) + +/* MAC Result High Word */ +#define SPR_MAC_MACHI_INDEX U(0x002) +#define SPR_MAC_MACHI_ADDR U(0x2802) + +/***************/ +/* Debug Group */ +/***************/ +#define SPR_DEBUG_GROUP 0x06 + +/* Debug Value Registers */ +#define SPR_DEBUG_DVR_BASE U(0x000) +#define SPR_DEBUG_DVR_COUNT U(0x008) +#define SPR_DEBUG_DVR_STEP U(0x001) +#define SPR_DEBUG_DVR_INDEX(N) (SPR_DEBUG_DVR_BASE + \ + (SPR_DEBUG_DVR_STEP * (N))) +#define SPR_DEBUG_DVR_ADDR(N) ((SPR_DEBUG_GROUP << SPR_GROUP_LSB) | \ + SPR_DEBUG_DVR_INDEX(N)) + +/* Debug Control Registers */ +#define SPR_DEBUG_DCR_BASE U(0x008) +#define SPR_DEBUG_DCR_COUNT U(0x008) +#define SPR_DEBUG_DCR_STEP U(0x001) +#define SPR_DEBUG_DCR_INDEX(N) (SPR_DEBUG_DCR_BASE + \ + (SPR_DEBUG_DCR_STEP * (N))) +#define SPR_DEBUG_DCR_ADDR(N) ((SPR_DEBUG_GROUP << SPR_GROUP_LSB) | \ + SPR_DEBUG_DCR_INDEX(N)) + +/* DVR/DCR Present */ +#define SPR_DEBUG_DCR_DP_OFFSET 0 +#define SPR_DEBUG_DCR_DP_MASK 0x00000001 +#define SPR_DEBUG_DCR_DP_GET(x) (((x) >> 0) & 0x1) +#define SPR_DEBUG_DCR_DP_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Compare Condition */ +#define SPR_DEBUG_DCR_CC_LSB 1 +#define SPR_DEBUG_DCR_CC_MSB 3 +#define SPR_DEBUG_DCR_CC_BITS 3 +#define SPR_DEBUG_DCR_CC_MASK U(0x0000000e) +#define SPR_DEBUG_DCR_CC_GET(x) (((x) >> 1) & U(0x00000007)) +#define SPR_DEBUG_DCR_CC_SET(x, y) (((x) & U(0xfffffff1)) | \ + ((y) << 1)) + +/* Masked */ +#define SPR_DEBUG_DCR_CC_MASKED 0 +/* Equal */ +#define SPR_DEBUG_DCR_CC_EQ 1 +/* Less than */ +#define SPR_DEBUG_DCR_CC_LT 2 +/* Less than or equal */ +#define SPR_DEBUG_DCR_CC_LTE 3 +/* Greater than */ +#define SPR_DEBUG_DCR_CC_GT 4 +/* Greater than or equal */ +#define SPR_DEBUG_DCR_CC_GTE 5 +/* Not equal */ +#define SPR_DEBUG_DCR_CC_NEQ 6 + +/* Signed Comparison */ +#define SPR_DEBUG_DCR_SC_OFFSET 4 +#define SPR_DEBUG_DCR_SC_MASK 0x00000010 +#define SPR_DEBUG_DCR_SC_GET(x) (((x) >> 4) & 0x1) +#define SPR_DEBUG_DCR_SC_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Compare To */ +#define SPR_DEBUG_DCR_CT_LSB 5 +#define SPR_DEBUG_DCR_CT_MSB 7 +#define SPR_DEBUG_DCR_CT_BITS 3 +#define SPR_DEBUG_DCR_CT_MASK U(0x000000e0) +#define SPR_DEBUG_DCR_CT_GET(x) (((x) >> 5) & U(0x00000007)) +#define SPR_DEBUG_DCR_CT_SET(x, y) (((x) & U(0xffffff1f)) | \ + ((y) << 5)) + +/* Comparison disabled */ +#define SPR_DEBUG_DCR_CT_DISABLED 0 +/* Instruction fetch EA */ +#define SPR_DEBUG_DCR_CT_FEA 1 +/* Load EA */ +#define SPR_DEBUG_DCR_CT_LEA 2 +/* Store EA */ +#define SPR_DEBUG_DCR_CT_SEA 3 +/* Load data */ +#define SPR_DEBUG_DCR_CT_LD 4 +/* Store data */ +#define SPR_DEBUG_DCR_CT_SD 5 +/* Load/store EA */ +#define SPR_DEBUG_DCR_CT_LSEA 6 +/* Load/store data */ +#define SPR_DEBUG_DCR_CT_LSD 7 + +/* Debug Mode Register 1 */ +#define SPR_DEBUG_DMR1_INDEX U(0x010) +#define SPR_DEBUG_DMR1_ADDR U(0x3010) + +/* Chain Watchpoint 0 */ +#define SPR_DEBUG_DMR1_CW0_LSB 0 +#define SPR_DEBUG_DMR1_CW0_MSB 1 +#define SPR_DEBUG_DMR1_CW0_BITS 2 +#define SPR_DEBUG_DMR1_CW0_MASK U(0x00000003) +#define SPR_DEBUG_DMR1_CW0_GET(x) (((x) >> 0) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW0_SET(x, y) (((x) & U(0xfffffffc)) | \ + ((y) << 0)) + +/* Chain Watchpoint 1 */ +#define SPR_DEBUG_DMR1_CW1_LSB 2 +#define SPR_DEBUG_DMR1_CW1_MSB 3 +#define SPR_DEBUG_DMR1_CW1_BITS 2 +#define SPR_DEBUG_DMR1_CW1_MASK U(0x0000000c) +#define SPR_DEBUG_DMR1_CW1_GET(x) (((x) >> 2) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW1_SET(x, y) (((x) & U(0xfffffff3)) | \ + ((y) << 2)) + +/* Chain Watchpoint 2 */ +#define SPR_DEBUG_DMR1_CW2_LSB 4 +#define SPR_DEBUG_DMR1_CW2_MSB 5 +#define SPR_DEBUG_DMR1_CW2_BITS 2 +#define SPR_DEBUG_DMR1_CW2_MASK U(0x00000030) +#define SPR_DEBUG_DMR1_CW2_GET(x) (((x) >> 4) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW2_SET(x, y) (((x) & U(0xffffffcf)) | \ + ((y) << 4)) + +/* Chain Watchpoint 3 */ +#define SPR_DEBUG_DMR1_CW3_LSB 6 +#define SPR_DEBUG_DMR1_CW3_MSB 7 +#define SPR_DEBUG_DMR1_CW3_BITS 2 +#define SPR_DEBUG_DMR1_CW3_MASK U(0x000000c0) +#define SPR_DEBUG_DMR1_CW3_GET(x) (((x) >> 6) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW3_SET(x, y) (((x) & U(0xffffff3f)) | \ + ((y) << 6)) + +/* Chain Watchpoint 4 */ +#define SPR_DEBUG_DMR1_CW4_LSB 9 +#define SPR_DEBUG_DMR1_CW4_MSB 9 +#define SPR_DEBUG_DMR1_CW4_BITS 1 +#define SPR_DEBUG_DMR1_CW4_MASK U(0x00000200) +#define SPR_DEBUG_DMR1_CW4_GET(x) (((x) >> 9) & U(0x00000001)) +#define SPR_DEBUG_DMR1_CW4_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((y) << 9)) + +/* Chain Watchpoint 5 */ +#define SPR_DEBUG_DMR1_CW5_LSB 10 +#define SPR_DEBUG_DMR1_CW5_MSB 11 +#define SPR_DEBUG_DMR1_CW5_BITS 2 +#define SPR_DEBUG_DMR1_CW5_MASK U(0x00000c00) +#define SPR_DEBUG_DMR1_CW5_GET(x) (((x) >> 10) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW5_SET(x, y) (((x) & U(0xfffff3ff)) | \ + ((y) << 10)) + +/* Chain Watchpoint 6 */ +#define SPR_DEBUG_DMR1_CW6_LSB 12 +#define SPR_DEBUG_DMR1_CW6_MSB 13 +#define SPR_DEBUG_DMR1_CW6_BITS 2 +#define SPR_DEBUG_DMR1_CW6_MASK U(0x00003000) +#define SPR_DEBUG_DMR1_CW6_GET(x) (((x) >> 12) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW6_SET(x, y) (((x) & U(0xffffcfff)) | \ + ((y) << 12)) + +/* Chain Watchpoint 7 */ +#define SPR_DEBUG_DMR1_CW7_LSB 14 +#define SPR_DEBUG_DMR1_CW7_MSB 15 +#define SPR_DEBUG_DMR1_CW7_BITS 2 +#define SPR_DEBUG_DMR1_CW7_MASK U(0x0000c000) +#define SPR_DEBUG_DMR1_CW7_GET(x) (((x) >> 14) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW7_SET(x, y) (((x) & U(0xffff3fff)) | \ + ((y) << 14)) + +/* Chain Watchpoint 8 */ +#define SPR_DEBUG_DMR1_CW8_LSB 16 +#define SPR_DEBUG_DMR1_CW8_MSB 17 +#define SPR_DEBUG_DMR1_CW8_BITS 2 +#define SPR_DEBUG_DMR1_CW8_MASK U(0x00030000) +#define SPR_DEBUG_DMR1_CW8_GET(x) (((x) >> 16) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW8_SET(x, y) (((x) & U(0xfffcffff)) | \ + ((y) << 16)) + +/* Chain Watchpoint 9 */ +#define SPR_DEBUG_DMR1_CW9_LSB 18 +#define SPR_DEBUG_DMR1_CW9_MSB 19 +#define SPR_DEBUG_DMR1_CW9_BITS 2 +#define SPR_DEBUG_DMR1_CW9_MASK U(0x000c0000) +#define SPR_DEBUG_DMR1_CW9_GET(x) (((x) >> 18) & U(0x00000003)) +#define SPR_DEBUG_DMR1_CW9_SET(x, y) (((x) & U(0xfff3ffff)) | \ + ((y) << 18)) + +/* Single-step Trace */ +#define SPR_DEBUG_DMR1_ST_OFFSET 22 +#define SPR_DEBUG_DMR1_ST_MASK 0x00400000 +#define SPR_DEBUG_DMR1_ST_GET(x) (((x) >> 22) & 0x1) +#define SPR_DEBUG_DMR1_ST_SET(x, y) (((x) & U(0xffbfffff)) | \ + ((!!(y)) << 22)) + +/* Branch Trace */ +#define SPR_DEBUG_DMR1_BT_OFFSET 23 +#define SPR_DEBUG_DMR1_BT_MASK 0x00800000 +#define SPR_DEBUG_DMR1_BT_GET(x) (((x) >> 23) & 0x1) +#define SPR_DEBUG_DMR1_BT_SET(x, y) (((x) & U(0xff7fffff)) | \ + ((!!(y)) << 23)) + +/* Debug Mode Register 2 */ +#define SPR_DEBUG_DMR2_INDEX U(0x011) +#define SPR_DEBUG_DMR2_ADDR U(0x3011) + +/* Watchpoint Counter Enable 0 */ +#define SPR_DEBUG_DMR2_WCE0_OFFSET 0 +#define SPR_DEBUG_DMR2_WCE0_MASK 0x00000001 +#define SPR_DEBUG_DMR2_WCE0_GET(x) (((x) >> 0) & 0x1) +#define SPR_DEBUG_DMR2_WCE0_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Watchpoint Counter Enable 1 */ +#define SPR_DEBUG_DMR2_WCE1_OFFSET 1 +#define SPR_DEBUG_DMR2_WCE1_MASK 0x00000002 +#define SPR_DEBUG_DMR2_WCE1_GET(x) (((x) >> 1) & 0x1) +#define SPR_DEBUG_DMR2_WCE1_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Assign Watchpoints to Counter */ +#define SPR_DEBUG_DMR2_AWTC_LSB 2 +#define SPR_DEBUG_DMR2_AWTC_MSB 11 +#define SPR_DEBUG_DMR2_AWTC_BITS 10 +#define SPR_DEBUG_DMR2_AWTC_MASK U(0x00000ffc) +#define SPR_DEBUG_DMR2_AWTC_GET(x) (((x) >> 2) & U(0x000003ff)) +#define SPR_DEBUG_DMR2_AWTC_SET(x, y) (((x) & U(0xfffff003)) | \ + ((y) << 2)) + +/* Watchpoints Generating Breakpoint */ +#define SPR_DEBUG_DMR2_WGB_LSB 12 +#define SPR_DEBUG_DMR2_WGB_MSB 21 +#define SPR_DEBUG_DMR2_WGB_BITS 10 +#define SPR_DEBUG_DMR2_WGB_MASK U(0x003ff000) +#define SPR_DEBUG_DMR2_WGB_GET(x) (((x) >> 12) & U(0x000003ff)) +#define SPR_DEBUG_DMR2_WGB_SET(x, y) (((x) & U(0xffc00fff)) | \ + ((y) << 12)) + +/* Watchpoints Breakpoint Status */ +#define SPR_DEBUG_DMR2_WBS_LSB 22 +#define SPR_DEBUG_DMR2_WBS_MSB 31 +#define SPR_DEBUG_DMR2_WBS_BITS 10 +#define SPR_DEBUG_DMR2_WBS_MASK U(0xffc00000) +#define SPR_DEBUG_DMR2_WBS_GET(x) (((x) >> 22) & U(0x000003ff)) +#define SPR_DEBUG_DMR2_WBS_SET(x, y) (((x) & U(0x003fffff)) | \ + ((y) << 22)) + +/* Debug Watchpoint Counter Registers */ +#define SPR_DEBUG_DCWR_BASE U(0x012) +#define SPR_DEBUG_DCWR_COUNT U(0x002) +#define SPR_DEBUG_DCWR_STEP U(0x001) +#define SPR_DEBUG_DCWR_INDEX(N) (SPR_DEBUG_DCWR_BASE + \ + (SPR_DEBUG_DCWR_STEP * (N))) +#define SPR_DEBUG_DCWR_ADDR(N) ((SPR_DEBUG_GROUP << SPR_GROUP_LSB) | \ + SPR_DEBUG_DCWR_INDEX(N)) + +/* Debug Stop Register */ +#define SPR_DEBUG_DSR_INDEX U(0x014) +#define SPR_DEBUG_DSR_ADDR U(0x3014) + +/* Reset Exception */ +#define SPR_DEBUG_DSR_RSTE_OFFSET 0 +#define SPR_DEBUG_DSR_RSTE_MASK 0x00000001 +#define SPR_DEBUG_DSR_RSTE_GET(x) (((x) >> 0) & 0x1) +#define SPR_DEBUG_DSR_RSTE_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Bus Error Exception */ +#define SPR_DEBUG_DSR_BUSEE_OFFSET 1 +#define SPR_DEBUG_DSR_BUSEE_MASK 0x00000002 +#define SPR_DEBUG_DSR_BUSEE_GET(x) (((x) >> 1) & 0x1) +#define SPR_DEBUG_DSR_BUSEE_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Data Page Fault Exception */ +#define SPR_DEBUG_DSR_DPFE_OFFSET 2 +#define SPR_DEBUG_DSR_DPFE_MASK 0x00000004 +#define SPR_DEBUG_DSR_DPFE_GET(x) (((x) >> 2) & 0x1) +#define SPR_DEBUG_DSR_DPFE_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Instruction Page Fault Exception */ +#define SPR_DEBUG_DSR_IPFE_OFFSET 3 +#define SPR_DEBUG_DSR_IPFE_MASK 0x00000008 +#define SPR_DEBUG_DSR_IPFE_GET(x) (((x) >> 3) & 0x1) +#define SPR_DEBUG_DSR_IPFE_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Tick Timer Exception */ +#define SPR_DEBUG_DSR_TTE_OFFSET 4 +#define SPR_DEBUG_DSR_TTE_MASK 0x00000010 +#define SPR_DEBUG_DSR_TTE_GET(x) (((x) >> 4) & 0x1) +#define SPR_DEBUG_DSR_TTE_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Alignment Exception */ +#define SPR_DEBUG_DSR_AE_OFFSET 5 +#define SPR_DEBUG_DSR_AE_MASK 0x00000020 +#define SPR_DEBUG_DSR_AE_GET(x) (((x) >> 5) & 0x1) +#define SPR_DEBUG_DSR_AE_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Illegal Instruction Exception */ +#define SPR_DEBUG_DSR_IIE_OFFSET 6 +#define SPR_DEBUG_DSR_IIE_MASK 0x00000040 +#define SPR_DEBUG_DSR_IIE_GET(x) (((x) >> 6) & 0x1) +#define SPR_DEBUG_DSR_IIE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Interrupt Exception */ +#define SPR_DEBUG_DSR_INTE_OFFSET 7 +#define SPR_DEBUG_DSR_INTE_MASK 0x00000080 +#define SPR_DEBUG_DSR_INTE_GET(x) (((x) >> 7) & 0x1) +#define SPR_DEBUG_DSR_INTE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* DTLB Miss Exception */ +#define SPR_DEBUG_DSR_DME_OFFSET 8 +#define SPR_DEBUG_DSR_DME_MASK 0x00000100 +#define SPR_DEBUG_DSR_DME_GET(x) (((x) >> 8) & 0x1) +#define SPR_DEBUG_DSR_DME_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* ITLB Miss Exception */ +#define SPR_DEBUG_DSR_IME_OFFSET 9 +#define SPR_DEBUG_DSR_IME_MASK 0x00000200 +#define SPR_DEBUG_DSR_IME_GET(x) (((x) >> 9) & 0x1) +#define SPR_DEBUG_DSR_IME_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Range Exception */ +#define SPR_DEBUG_DSR_RE_OFFSET 10 +#define SPR_DEBUG_DSR_RE_MASK 0x00000400 +#define SPR_DEBUG_DSR_RE_GET(x) (((x) >> 10) & 0x1) +#define SPR_DEBUG_DSR_RE_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* System Call Exception */ +#define SPR_DEBUG_DSR_SCE_OFFSET 11 +#define SPR_DEBUG_DSR_SCE_MASK 0x00000800 +#define SPR_DEBUG_DSR_SCE_GET(x) (((x) >> 11) & 0x1) +#define SPR_DEBUG_DSR_SCE_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Floating Point Exception */ +#define SPR_DEBUG_DSR_FPE_OFFSET 12 +#define SPR_DEBUG_DSR_FPE_MASK 0x00001000 +#define SPR_DEBUG_DSR_FPE_GET(x) (((x) >> 12) & 0x1) +#define SPR_DEBUG_DSR_FPE_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Trap Exception */ +#define SPR_DEBUG_DSR_TE_OFFSET 13 +#define SPR_DEBUG_DSR_TE_MASK 0x00002000 +#define SPR_DEBUG_DSR_TE_GET(x) (((x) >> 13) & 0x1) +#define SPR_DEBUG_DSR_TE_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/* Debug Reason Register */ +#define SPR_DEBUG_DRR_INDEX U(0x015) +#define SPR_DEBUG_DRR_ADDR U(0x3015) + +/* Reset Exception */ +#define SPR_DEBUG_DRR_RSTE_OFFSET 0 +#define SPR_DEBUG_DRR_RSTE_MASK 0x00000001 +#define SPR_DEBUG_DRR_RSTE_GET(x) (((x) >> 0) & 0x1) +#define SPR_DEBUG_DRR_RSTE_SET(x, y) (((x) & U(0xfffffffe)) | \ + ((!!(y)) << 0)) + +/* Bus Error Exception */ +#define SPR_DEBUG_DRR_BUSEE_OFFSET 1 +#define SPR_DEBUG_DRR_BUSEE_MASK 0x00000002 +#define SPR_DEBUG_DRR_BUSEE_GET(x) (((x) >> 1) & 0x1) +#define SPR_DEBUG_DRR_BUSEE_SET(x, y) (((x) & U(0xfffffffd)) | \ + ((!!(y)) << 1)) + +/* Data Page Fault Exception */ +#define SPR_DEBUG_DRR_DPFE_OFFSET 2 +#define SPR_DEBUG_DRR_DPFE_MASK 0x00000004 +#define SPR_DEBUG_DRR_DPFE_GET(x) (((x) >> 2) & 0x1) +#define SPR_DEBUG_DRR_DPFE_SET(x, y) (((x) & U(0xfffffffb)) | \ + ((!!(y)) << 2)) + +/* Instruction Page Fault Exception */ +#define SPR_DEBUG_DRR_IPFE_OFFSET 3 +#define SPR_DEBUG_DRR_IPFE_MASK 0x00000008 +#define SPR_DEBUG_DRR_IPFE_GET(x) (((x) >> 3) & 0x1) +#define SPR_DEBUG_DRR_IPFE_SET(x, y) (((x) & U(0xfffffff7)) | \ + ((!!(y)) << 3)) + +/* Tick Timer Exception */ +#define SPR_DEBUG_DRR_TTE_OFFSET 4 +#define SPR_DEBUG_DRR_TTE_MASK 0x00000010 +#define SPR_DEBUG_DRR_TTE_GET(x) (((x) >> 4) & 0x1) +#define SPR_DEBUG_DRR_TTE_SET(x, y) (((x) & U(0xffffffef)) | \ + ((!!(y)) << 4)) + +/* Alignment Exception */ +#define SPR_DEBUG_DRR_AE_OFFSET 5 +#define SPR_DEBUG_DRR_AE_MASK 0x00000020 +#define SPR_DEBUG_DRR_AE_GET(x) (((x) >> 5) & 0x1) +#define SPR_DEBUG_DRR_AE_SET(x, y) (((x) & U(0xffffffdf)) | \ + ((!!(y)) << 5)) + +/* Illegal Instruction Exception */ +#define SPR_DEBUG_DRR_IIE_OFFSET 6 +#define SPR_DEBUG_DRR_IIE_MASK 0x00000040 +#define SPR_DEBUG_DRR_IIE_GET(x) (((x) >> 6) & 0x1) +#define SPR_DEBUG_DRR_IIE_SET(x, y) (((x) & U(0xffffffbf)) | \ + ((!!(y)) << 6)) + +/* Interrupt Exception */ +#define SPR_DEBUG_DRR_INTE_OFFSET 7 +#define SPR_DEBUG_DRR_INTE_MASK 0x00000080 +#define SPR_DEBUG_DRR_INTE_GET(x) (((x) >> 7) & 0x1) +#define SPR_DEBUG_DRR_INTE_SET(x, y) (((x) & U(0xffffff7f)) | \ + ((!!(y)) << 7)) + +/* DTLB Miss Exception */ +#define SPR_DEBUG_DRR_DME_OFFSET 8 +#define SPR_DEBUG_DRR_DME_MASK 0x00000100 +#define SPR_DEBUG_DRR_DME_GET(x) (((x) >> 8) & 0x1) +#define SPR_DEBUG_DRR_DME_SET(x, y) (((x) & U(0xfffffeff)) | \ + ((!!(y)) << 8)) + +/* ITLB Miss Exception */ +#define SPR_DEBUG_DRR_IME_OFFSET 9 +#define SPR_DEBUG_DRR_IME_MASK 0x00000200 +#define SPR_DEBUG_DRR_IME_GET(x) (((x) >> 9) & 0x1) +#define SPR_DEBUG_DRR_IME_SET(x, y) (((x) & U(0xfffffdff)) | \ + ((!!(y)) << 9)) + +/* Range Exception */ +#define SPR_DEBUG_DRR_RE_OFFSET 10 +#define SPR_DEBUG_DRR_RE_MASK 0x00000400 +#define SPR_DEBUG_DRR_RE_GET(x) (((x) >> 10) & 0x1) +#define SPR_DEBUG_DRR_RE_SET(x, y) (((x) & U(0xfffffbff)) | \ + ((!!(y)) << 10)) + +/* System Call Exception */ +#define SPR_DEBUG_DRR_SCE_OFFSET 11 +#define SPR_DEBUG_DRR_SCE_MASK 0x00000800 +#define SPR_DEBUG_DRR_SCE_GET(x) (((x) >> 11) & 0x1) +#define SPR_DEBUG_DRR_SCE_SET(x, y) (((x) & U(0xfffff7ff)) | \ + ((!!(y)) << 11)) + +/* Floating Point Exception */ +#define SPR_DEBUG_DRR_FPE_OFFSET 12 +#define SPR_DEBUG_DRR_FPE_MASK 0x00001000 +#define SPR_DEBUG_DRR_FPE_GET(x) (((x) >> 12) & 0x1) +#define SPR_DEBUG_DRR_FPE_SET(x, y) (((x) & U(0xffffefff)) | \ + ((!!(y)) << 12)) + +/* Trap Exception */ +#define SPR_DEBUG_DRR_TE_OFFSET 13 +#define SPR_DEBUG_DRR_TE_MASK 0x00002000 +#define SPR_DEBUG_DRR_TE_GET(x) (((x) >> 13) & 0x1) +#define SPR_DEBUG_DRR_TE_SET(x, y) (((x) & U(0xffffdfff)) | \ + ((!!(y)) << 13)) + +/******************************/ +/* Performance Counters Group */ +/******************************/ +#define SPR_PERF_GROUP 0x07 + +/* Performance Counters Count Registers */ +#define SPR_PERF_PCCR_BASE U(0x000) +#define SPR_PERF_PCCR_COUNT U(0x008) +#define SPR_PERF_PCCR_STEP U(0x001) +#define SPR_PERF_PCCR_INDEX(N) (SPR_PERF_PCCR_BASE + \ + (SPR_PERF_PCCR_STEP * (N))) +#define SPR_PERF_PCCR_ADDR(N) ((SPR_PERF_GROUP << SPR_GROUP_LSB) | \ + SPR_PERF_PCCR_INDEX(N)) + +/* Performance Counters Mode Registers */ +#define SPR_PERF_PCMR_BASE U(0x008) +#define SPR_PERF_PCMR_COUNT U(0x008) +#define SPR_PERF_PCMR_STEP U(0x001) +#define SPR_PERF_PCMR_INDEX(N) (SPR_PERF_PCMR_BASE + \ + (SPR_PERF_PCMR_STEP * (N))) +#define SPR_PERF_PCMR_ADDR(N) ((SPR_PERF_GROUP << SPR_GROUP_LSB) | \ + SPR_PERF_PCMR_INDEX(N)) + +/**************************/ +/* Power Management Group */ +/**************************/ +#define SPR_POWER_GROUP 0x08 + +/* Power Management Register */ +#define SPR_POWER_PMR_INDEX U(0x000) +#define SPR_POWER_PMR_ADDR U(0x4000) + +/*******************************************/ +/* Programmable Interrupt Controller Group */ +/*******************************************/ +#define SPR_PIC_GROUP 0x09 + +/* PIC Mask Register */ +#define SPR_PIC_PICMR_INDEX U(0x000) +#define SPR_PIC_PICMR_ADDR U(0x4800) + +/* PIC Status Register */ +#define SPR_PIC_PICSR_INDEX U(0x002) +#define SPR_PIC_PICSR_ADDR U(0x4802) + +/********************/ +/* Tick Timer Group */ +/********************/ +#define SPR_TICK_GROUP 0x0a + +/* Tick Timer Mode Register */ +#define SPR_TICK_TTMR_INDEX U(0x000) +#define SPR_TICK_TTMR_ADDR U(0x5000) + +/* Time Period */ +#define SPR_TICK_TTMR_TP_LSB 0 +#define SPR_TICK_TTMR_TP_MSB 27 +#define SPR_TICK_TTMR_TP_BITS 28 +#define SPR_TICK_TTMR_TP_MASK U(0x0fffffff) +#define SPR_TICK_TTMR_TP_GET(x) (((x) >> 0) & U(0x0fffffff)) +#define SPR_TICK_TTMR_TP_SET(x, y) (((x) & U(0xf0000000)) | \ + ((y) << 0)) + +/* Interrupt Pending */ +#define SPR_TICK_TTMR_IP_OFFSET 28 +#define SPR_TICK_TTMR_IP_MASK 0x10000000 +#define SPR_TICK_TTMR_IP_GET(x) (((x) >> 28) & 0x1) +#define SPR_TICK_TTMR_IP_SET(x, y) (((x) & U(0xefffffff)) | \ + ((!!(y)) << 28)) + +/* Interrupt Enable */ +#define SPR_TICK_TTMR_IE_OFFSET 29 +#define SPR_TICK_TTMR_IE_MASK 0x20000000 +#define SPR_TICK_TTMR_IE_GET(x) (((x) >> 29) & 0x1) +#define SPR_TICK_TTMR_IE_SET(x, y) (((x) & U(0xdfffffff)) | \ + ((!!(y)) << 29)) + +/* Mode */ +#define SPR_TICK_TTMR_MODE_LSB 30 +#define SPR_TICK_TTMR_MODE_MSB 31 +#define SPR_TICK_TTMR_MODE_BITS 2 +#define SPR_TICK_TTMR_MODE_MASK U(0xc0000000) +#define SPR_TICK_TTMR_MODE_GET(x) (((x) >> 30) & U(0x00000003)) +#define SPR_TICK_TTMR_MODE_SET(x, y) (((x) & U(0x3fffffff)) | \ + ((y) << 30)) + +/* Disabled */ +#define SPR_TICK_TTMR_MODE_DISABLE 0 +/* Restart counting when TTMR[TP]==TTCR */ +#define SPR_TICK_TTMR_MODE_RESTART 1 +/* Stop counting when TTMR[TP]==TTCR */ +#define SPR_TICK_TTMR_MODE_STOP 2 +/* Continue counting when TTMR[TP]==TTCR */ +#define SPR_TICK_TTMR_MODE_CONTINUE 3 + +/* Tick Timer Count Register */ +#define SPR_TICK_TTCR_INDEX U(0x001) +#define SPR_TICK_TTCR_ADDR U(0x5001) + +/*****************************/ +/* Floating Point Unit Group */ +/*****************************/ +#define SPR_FPU_GROUP 0x0b + +#endif /* COMMON_ARCH_SPR_H */ diff --git a/lib/ar100/macros.S b/lib/ar100/macros.S new file mode 100644 index 000000000000..734ac0ea59fe --- /dev/null +++ b/lib/ar100/macros.S @@ -0,0 +1,38 @@ +/* + * Copyright © 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright © 2017-2020 The Crust Firmware Authors. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MACROS_S +#define MACROS_S + + /* This macro marks a global data declaration. */ + .macro data name + .section .data.\name, "aw", @progbits + .global \name + .type \name, %object + .align 4 +\name: + .endm + + /* This macro marks the beginning of a function. */ + .macro func name + .section .text.\name, "ax", @progbits + .global \name + .type \name, %function + .func \name + .cfi_sections .debug_frame + .cfi_startproc + .align 4 +\name: + .endm + + /* This macro marks the end of a function. */ + .macro endfunc name + .cfi_endproc + .endfunc + .size \name, . - \name + .endm + +#endif /* MACROS_S */ diff --git a/lib/ar100/runtime.S b/lib/ar100/runtime.S new file mode 100644 index 000000000000..6d6f167593a4 --- /dev/null +++ b/lib/ar100/runtime.S @@ -0,0 +1,117 @@ +/* + * Copyright © 2017-2020 The Crust Firmware Authors. + * SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only + */ + +#include + +func __divsi3 + l.sflts r3, r0 + l.sw -8(r1), r18 + l.bnf 1f + l.ori r18, r0, 0 + l.sub r3, r0, r3 # Negate x if it is negative + l.addi r18, r18, 1 # Increment the flag if x is negative +1: l.sflts r4, r0 + l.bnf 2f + l.sw -4(r1), r9 + l.sub r4, r0, r4 # Negate y if it is negative + l.addi r18, r18, -1 # Decrement the flag if y is negative +2: l.jal __udivsi3 + l.addi r1, r1, -8 + l.sfne r18, r0 + l.bnf 3f + l.addi r1, r1, 8 + l.sub r11, r0, r11 # Negate q if the flag is nonzero +3: l.lwz r9, -4(r1) + l.jr r9 + l.lwz r18, -8(r1) +endfunc __divsi3 + +/* + * Of the three ORBIS32 32-bit multiplication instructions (l.mul, l.muli, and + * l.mulu), only l.mul works. By passing "-msoft-mul" to the compiler, and + * delegating to this function, we can force all multiplication to use l.mul. + */ +func __mulsi3 + l.jr r9 + l.mul r11, r3, r4 +endfunc __mulsi3 + +/* + * Derived from the "best method for counting bits in a 32-bit integer" at + * https://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel. + * + * Signed multiplication is used because l.mulu is broken in hardware. This is + * safe because the previous bit masking ensures neither operand is negative. + */ +func __popcountsi2 + l.movhi r5, 0x5555 # Statement 1: + l.ori r5, r5, 0x5555 # r5 = 0x55555555 + l.srli r4, r3, 1 # r4 = v >> 1 + l.and r4, r4, r5 # r4 = (v >> 1) & 0x55555555 + l.sub r3, r3, r4 # v = v - ((v >> 1) & 0x55555555) + l.movhi r5, 0x3333 # Statement 2: + l.ori r5, r5, 0x3333 # r5 = 0x33333333 + l.srli r4, r3, 2 # r4 = v >> 2 + l.and r4, r4, r5 # r4 = (v >> 2) & 0x33333333 + l.and r3, r3, r5 # v = v & 0x33333333 + l.add r3, r3, r4 # v += ((v >> 2) & 0x33333333) + l.movhi r5, 0x0f0f # Statement 3: + l.ori r5, r5, 0x0f0f # r5 = 0x0f0f0f0f + l.srli r4, r3, 4 # r4 = v >> 4 + l.add r4, r3, r4 # r4 = v + (v >> 4) + l.and r4, r4, r5 # r4 = v + (v >> 4) & 0x0f0f0f0f + l.movhi r5, 0x0101 + l.ori r5, r5, 0x0101 # r5 = 0x01010101 + l.mul r11, r4, r5 # c = r4 * 0x01010101 + l.jr r9 + l.srli r11, r11, 24 # return c >> 24 +endfunc __popcountsi2 + +/* + * Optimized implementation of the "shift divisor method" algorithm from + * T. Rodeheffer. Software Integer Division. Microsoft Research, 2008. + * + * In addition to returning the quotient in r11, this function also returns + * the remainder in r12. __umodsi3 simply copies the remainder into r11. + */ +func __udivsi3 # u32 __udivsi3(u32 x, u32 y) { + l.sfeqi r4, 1 # if (y == 1) + l.bf 5f # goto identity; + l.ori r12, r3, 0 # u32 r = x; + l.ori r5, r4, 0 # u32 y0 = y; + l.addi r11, r0, 0 # u32 q = 0; + l.sfltu r3, r4 # if (x >= y) { + l.bf 2f + l.sub r3, r3, r4 # x = x−y; +1: l.sfltu r3, r4 # while (x >= y) { + l.bf 2f + l.sub r3, r3, r4 # x = x−y; + l.add r4, r4, r4 # y *= 2; + l.j 1b # } +2: l.sfltu r12, r4 # } for (;;) { + l.bf 3f # if (r >= y) { + l.sfeq r4, r5 # [if (y == y0)] + l.sub r12, r12, r4 # r = r−y; + l.addi r11, r11, 1 # q = q + 1; +3: l.bf 4f # } if (y == y0) break; + l.srli r4, r4, 1 # y >>= 1; + l.j 2b # } + l.add r11, r11, r11 # q *= 2; +4: l.jr r9 # return q; + l.nop +5: l.ori r11, r3, 0 # identity: + l.jr r9 # return x; + l.ori r12, r0, 0 # r = 0; +endfunc __udivsi3 # } + +func __umodsi3 + l.sw -4(r1), r9 + l.jal __udivsi3 + l.addi r1, r1, -4 + l.addi r1, r1, 4 + l.lwz r9, -4(r1) + l.jr r9 + l.ori r11, r12, 0 +endfunc __umodsi3 diff --git a/lib/ar100/start.S b/lib/ar100/start.S new file mode 100644 index 000000000000..0ffc8348837c --- /dev/null +++ b/lib/ar100/start.S @@ -0,0 +1,41 @@ +/* + * Copyright © 2017-2020 The Crust Firmware Authors. + * SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only + */ + +#include +#include + +func start + l.mfspr r2, r0, SPR_SYS_PPC_ADDR + l.sfltui r2, 0x4000 # Size of exception vector area + l.bf 1f + l.srli r2, r2, 8 # Vector address → exception number + l.addi r2, r0, 0 # Set to zero if not an exception +1: l.addi r3, r0, 0 # Invalidate instruction cache + l.addi r4, r0, 4096 # Cache lines (256) * block size (16) +2: l.mtspr r0, r3, SPR_ICACHE_ICBIR_ADDR + l.sfltu r3, r4 + l.bf 2b + l.addi r3, r3, 16 # Cache block size + l.psync # Flush CPU pipeline + l.mfspr r3, r0, SPR_SYS_SR_ADDR # Enable instruction cache + l.ori r3, r3, SPR_SYS_SR_ICE_MASK + l.mtspr r0, r3, SPR_SYS_SR_ADDR + l.nop # One cache block of nops + l.nop + l.nop + l.nop + l.movhi r3, hi(__bss_start) # Clear .bss + l.ori r3, r3, lo(__bss_start) + l.movhi r4, hi(__bss_end) + l.ori r4, r4, lo(__bss_end) +3: l.sw 0(r3), r0 + l.sfltu r3, r4 + l.bf 3b + l.addi r3, r3, 4 + l.movhi r1, hi(__stack_end) + l.ori r1, r1, lo(__stack_end) # Initialize stack pointer + l.j main # Jump to C entry point + l.or r3, r2, r2 +endfunc start diff --git a/lib/can2040/can2040.c b/lib/can2040/can2040.c index fb9e3fb62b64..9eef0d43dbe8 100644 --- a/lib/can2040/can2040.c +++ b/lib/can2040/can2040.c @@ -113,7 +113,7 @@ static const uint16_t can2040_program_instructions[] = { 0x20c4, // 28: wait 1 irq, 4 0x00d9, // 29: jmp pin, 25 0x023a, // 30: jmp !x, 26 [2] - 0xc027, // 31: irq wait 7 + 0x001f, // 31: jmp 31 }; // Local names for PIO state machine IRQs @@ -267,7 +267,7 @@ pio_tx_send(struct can2040 *cd, uint32_t *data, uint32_t count) pio_hw_t *pio_hw = cd->pio_hw; pio_tx_reset(cd); pio_hw->instr_mem[can2040_offset_tx_got_recessive] = 0xa242; // nop [2] - int i; + uint32_t i; for (i=0; itxf[3] = data[i]; struct pio_sm_hw *sm = &pio_hw->sm[3]; @@ -351,7 +351,7 @@ pio_sm_setup(struct can2040 *cd) pio_signal_set_txpending(cd); // Load pio program - int i; + uint32_t i; for (i=0; iinstr_mem[i] = can2040_program_instructions[i]; @@ -436,9 +436,9 @@ static inline uint32_t crc_bytes(uint32_t crc, uint32_t data, uint32_t num) { switch (num) { - default: crc = crc_byte(crc, data >> 24); - case 3: crc = crc_byte(crc, data >> 16); - case 2: crc = crc_byte(crc, data >> 8); + default: crc = crc_byte(crc, data >> 24); /* FALLTHRU */ + case 3: crc = crc_byte(crc, data >> 16); /* FALLTHRU */ + case 2: crc = crc_byte(crc, data >> 8); /* FALLTHRU */ case 1: crc = crc_byte(crc, data); } return crc; @@ -647,14 +647,19 @@ tx_schedule_transmit(struct can2040 *cd) if (cd->tx_state == TS_QUEUED && !pio_tx_did_fail(cd)) // Already queued or actively transmitting return 0; - if (cd->tx_push_pos == cd->tx_pull_pos) { + uint32_t tx_pull_pos = cd->tx_pull_pos; + if (readl(&cd->tx_push_pos) == tx_pull_pos) { // No new messages to transmit cd->tx_state = TS_IDLE; pio_signal_clear_txpending(cd); - return SI_TXPENDING; + __DMB(); + if (likely(readl(&cd->tx_push_pos) == tx_pull_pos)) + return SI_TXPENDING; + // Raced with can2040_transmit() - msg is now available for transmit + pio_signal_set_txpending(cd); } cd->tx_state = TS_QUEUED; - struct can2040_transmit *qt = &cd->tx_queue[tx_qpos(cd, cd->tx_pull_pos)]; + struct can2040_transmit *qt = &cd->tx_queue[tx_qpos(cd, tx_pull_pos)]; pio_tx_send(cd, qt->stuffed_data, qt->stuffed_words); return 0; } @@ -717,7 +722,7 @@ report_callback_rx_msg(struct can2040 *cd) static void report_callback_tx_msg(struct can2040 *cd) { - cd->tx_pull_pos++; + writel(&cd->tx_pull_pos, cd->tx_pull_pos + 1); cd->rx_cb(cd, CAN2040_NOTIFY_TX, &cd->parse_msg); } @@ -856,7 +861,9 @@ report_line_maytx(struct can2040 *cd) static void report_line_txpending(struct can2040 *cd) { - if (cd->report_state == RS_NEED_RX_ACK) { + uint32_t pio_irqs = pio_irq_get(cd); + if (pio_irqs == (SI_MAYTX | SI_TXPENDING | SI_RX_DATA) + && cd->report_state == RS_NEED_RX_ACK) { // Ack inject request from report_note_crc_start() uint32_t mk = pio_match_calc_key(cd->parse_crc_bits, cd->parse_crc_pos); tx_inject_ack(cd, mk); @@ -866,7 +873,7 @@ report_line_txpending(struct can2040 *cd) // Tx request from can2040_transmit(), report_note_eof_success(), // or report_note_parse_error(). uint32_t check_txpending = tx_schedule_transmit(cd); - pio_irq_set(cd, (pio_irq_get(cd) & ~SI_TXPENDING) | check_txpending); + pio_irq_set(cd, (pio_irqs & ~SI_TXPENDING) | check_txpending); } @@ -1241,7 +1248,7 @@ can2040_transmit(struct can2040 *cd, struct can2040_msg *msg) crc = crc_bytes(crc, hdr, 3); bs_push(&bs, hdr, 19); } - int i; + uint32_t i; for (i=0; imsg.data[i]; crc = crc_byte(crc, v); @@ -1256,6 +1263,7 @@ can2040_transmit(struct can2040 *cd, struct can2040_msg *msg) writel(&cd->tx_push_pos, tx_push_pos + 1); // Wakeup if in TS_IDLE state + __DMB(); pio_signal_set_txpending(cd); return 0; diff --git a/lib/hc32f460/driver/inc/hc32f460_adc.h b/lib/hc32f460/driver/inc/hc32f460_adc.h new file mode 100644 index 000000000000..25c411bf575c --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_adc.h @@ -0,0 +1,503 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.h + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ +#ifndef __HC32F460_ADC_H__ +#define __HC32F460_ADC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AdcGroup Analog-to-Digital Converter(ADC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC average count. + ** + ******************************************************************************/ +typedef enum en_adc_avcnt +{ + AdcAvcnt_2 = 0x0, ///< Average after 2 conversions. + AdcAvcnt_4 = 0x1, ///< Average after 4 conversions. + AdcAvcnt_8 = 0x2, ///< Average after 8 conversions. + AdcAvcnt_16 = 0x3, ///< Average after 16 conversions. + AdcAvcnt_32 = 0x4, ///< Average after 32 conversions. + AdcAvcnt_64 = 0x5, ///< Average after 64 conversions. + AdcAvcnt_128 = 0x6, ///< Average after 128 conversions. + AdcAvcnt_256 = 0x7, ///< Average after 256 conversions. +} en_adc_avcnt_t; + +/** + ******************************************************************************* + ** \brief ADC data alignment + ** + ******************************************************************************/ +typedef enum en_adc_data_align +{ + AdcDataAlign_Right = 0x0, ///< Data right alignment. + AdcDataAlign_Left = 0x1, ///< Data left alignment. +} en_adc_data_align_t; + +/** + ******************************************************************************* + ** \brief Automatically clear data registers after reading data. + ** The auto clear function is mainly used to detect whether the data register + ** is updated. + ** + ******************************************************************************/ +typedef enum en_adc_clren +{ + AdcClren_Disable = 0x0, ///< Automatic clear function disable. + AdcClren_Enable = 0x1, ///< Automatic clear function enable. +} en_adc_clren_t; + +/** + ******************************************************************************* + ** \brief ADC resolution. + ** + ******************************************************************************/ +typedef enum en_adc_resolution +{ + AdcResolution_12Bit = 0x0, ///< Resolution is 12 bit. + AdcResolution_10Bit = 0x1, ///< Resolution is 10 bit. + AdcResolution_8Bit = 0x2, ///< Resolution is 8 bit. +} en_adc_resolution_t; + +/** + ******************************************************************************* + ** \brief ADC scan mode. + ** + ******************************************************************************/ +typedef enum en_adc_scan_mode +{ + AdcMode_SAOnce = 0x0, ///< Sequence A works once. + AdcMode_SAContinuous = 0x1, ///< Sequence A works always. + AdcMode_SAOnceSBOnce = 0x2, ///< Sequence A and sequence B work once. + AdcMode_SAContinuousSBOnce = 0x3, ///< Sequence A works always, sequence works once. +} en_adc_scan_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sequence A restart position. + ** + ******************************************************************************/ +typedef enum en_adc_rschsel +{ + AdcRschsel_Continue = 0x0, ///< After sequence A is interrupted by sequence B, + ///< sequence A continues to scan from the interrupt + ///< when it restarts. + + AdcRschsel_Restart = 0x1, ///< After sequence A is interrupted by sequence B, + ///< sequence A restarts scanning from the first channel + ///< when it restarts. +} en_adc_rschsel_t; + +/** + ******************************************************************************* + ** \brief ADC external or internal trigger source enable/disable . + ** + ******************************************************************************/ +typedef enum en_adc_trgen +{ + AdcTrgen_Disable = 0x0, ///< External or internal trigger source disable. + AdcTrgen_Enable = 0x1, ///< External or internal trigger source enable. +} en_adc_trgen_t; + +/** + ******************************************************************************* + ** \brief ADC sequence trigger source selection. + ** + ******************************************************************************/ +typedef enum en_adc_trgsel +{ + AdcTrgsel_ADTRGX = 0x0, ///< X = 1(use ADC1) / 2(use ADC2), same as below. + AdcTrgsel_TRGX0 = 0x1, ///< Pin IN_TRG10 / IN_TRG20. + AdcTrgsel_TRGX1 = 0x2, ///< Pin IN_TRG11 / IN_TRG21. + AdcTrgsel_TRGX0_TRGX1 = 0x3, ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21. +} en_adc_trgsel_t; + +/** + ******************************************************************************* + ** \brief Sequence A/B conversion completion interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_eocien +{ + AdcEocien_Disable = 0x0, ///< Conversion completion interrupt disable. + AdcEocien_Enable = 0x1, ///< Conversion completion interrupt enable. +} en_adc_eocien_t; + +/** + ******************************************************************************* + ** \brief ADC sync mode. + ** + ******************************************************************************/ +typedef enum en_adc_sync_mode +{ + AdcSync_SingleSerial = 0x0u, ///< Single: ADC1 and ADC2 only sample and convert once after triggering. + ///< Serial: ADC2 start after ADC1 N PCLK4 cycles. + AdcSync_SingleParallel = 0x2u, ///< Parallel: ADC1 and ADC2 start at the same time. + AdcSync_ContinuousSerial = 0x4u, ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering. + AdcSync_ContinuousParallel = 0x6u, +} en_adc_sync_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sync enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_syncen +{ + AdcSync_Disable = 0x0, ///< Disable sync mode. + AdcSync_Enable = 0x1, ///< Enable sync mode. +} en_adc_syncen_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awdien +{ + AdcAwdInt_Disable = 0x0, ///< Disable AWD interrupt. + AdcAwdInt_Enable = 0x1, ///< Enable AWD interrupt. +} en_adc_awdien_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt event sequence selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdss +{ + AdcAwdSel_SA_SB = 0x0, ///< Sequence A and B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SA = 0x1, ///< Sequence A output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB = 0x2, ///< Sequence B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB_SA = 0x3, ///< Same as AdcAwdSel_SA_SB. +} en_adc_awdss_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog comparison mode selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdmd +{ + AdcAwdCmpMode_0 = 0x0, ///< Upper limit is AWDDR0, lower limit is AWDDR1. + ///< If AWDDR0 > result or result > AWDDR1, + ///< the interrupt will be occur. + + AdcAwdCmpMode_1 = 0x1, ///< The range is [AWDDR0, AWDDR1]. + ///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur. +} en_adc_awdmd_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awden +{ + AdcAwd_Disable = 0x0, ///< Disable AWD. + AdcAwd_Enable = 0x1, ///< Enable AWD. +} en_adc_awden_t; + +/** + ******************************************************************************* + ** \brief PGA control. + ** + ******************************************************************************/ +typedef enum en_adc_pga_ctl +{ + AdcPgaCtl_Invalid = 0x0, ///< Amplifier is invalid. + AdcPgaCtl_Amplify = 0xE, ///< Amplifier effective. +} en_adc_pga_ctl_t; + +/** + ******************************************************************************* + ** \brief The amplification factor of the amplifier is as follows. + ** + ******************************************************************************/ +typedef enum en_adc_pga_factor +{ + AdcPgaFactor_2 = 0x0, ///< PGA magnification 2. + AdcPgaFactor_2P133 = 0x1, ///< PGA magnification 2.133. + AdcPgaFactor_2P286 = 0x2, ///< PGA magnification 2.286. + AdcPgaFactor_2P667 = 0x3, ///< PGA magnification 2.667. + AdcPgaFactor_2P909 = 0x4, ///< PGA magnification 2.909. + AdcPgaFactor_3P2 = 0x5, ///< PGA magnification 3.2. + AdcPgaFactor_3P556 = 0x6, ///< PGA magnification 3.556. + AdcPgaFactor_4 = 0x7, ///< PGA magnification 4. + AdcPgaFactor_4P571 = 0x8, ///< PGA magnification 4.571. + AdcPgaFactor_5P333 = 0x9, ///< PGA magnification 5.333. + AdcPgaFactor_6P4 = 0xA, ///< PGA magnification 6.4. + AdcPgaFactor_8 = 0xB, ///< PGA magnification 8. + AdcPgaFactor_10P667 = 0xC, ///< PGA magnification 10.667. + AdcPgaFactor_16 = 0xD, ///< PGA magnification 16. + AdcPgaFactor_32 = 0xE, ///< PGA magnification 32. +} en_adc_pga_factor_t; + +/** + ******************************************************************************* + ** \brief Negative phase input selection + ** + ******************************************************************************/ +typedef enum en_adc_pga_negative +{ + AdcPgaNegative_PGAVSS = 0x0, ///< Use external port PGAVSS as PGA negative input. + AdcPgaNegative_VSSA = 0x1, ///< Use internal analog ground VSSA as PGA negative input. +} en_adc_pga_negative_t; + +/** + ******************************************************************************* + ** \brief ADC common trigger source select + ** + ******************************************************************************/ +typedef enum en_adc_com_trigger +{ + AdcComTrigger_1 = 0x1, ///< Select common trigger 1. + AdcComTrigger_2 = 0x2, ///< Select common trigger 2. + AdcComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_adc_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Structure definition of ADC + ** + ******************************************************************************/ +typedef struct stc_adc_ch_cfg +{ + uint32_t u32Channel; ///< ADC channels mask. + uint8_t u8Sequence; ///< The sequence which the channel(s) belong to. + uint8_t *pu8SampTime; ///< Pointer to sampling time. +} stc_adc_ch_cfg_t; + +typedef struct stc_adc_awd_cfg +{ + en_adc_awdmd_t enAwdmd; ///< Comparison mode of the values. + en_adc_awdss_t enAwdss; ///< Interrupt output select. + uint16_t u16AwdDr0; ///< Your range DR0. + uint16_t u16AwdDr1; ///< Your range DR1. +} stc_adc_awd_cfg_t; + +typedef struct stc_adc_trg_cfg +{ + uint8_t u8Sequence; ///< The sequence will be configured trigger source. + en_adc_trgsel_t enTrgSel; ///< Trigger source type. + en_event_src_t enInTrg0; ///< Internal trigger 0 source number + ///< (event number @ref en_event_src_t). + en_event_src_t enInTrg1; ///< Internal trigger 1 source number + ///< (event number @ref en_event_src_t). +} stc_adc_trg_cfg_t; + +typedef struct stc_adc_init +{ + en_adc_resolution_t enResolution; ///< ADC resolution 12bit/10bit/8bit. + en_adc_data_align_t enDataAlign; ///< ADC data alignment. + en_adc_clren_t enAutoClear; ///< Automatically clear data register. + ///< after reading data register(enable/disable). + en_adc_scan_mode_t enScanMode; ///< ADC scan mode. + en_adc_rschsel_t enRschsel; ///< Restart or continue. +} stc_adc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC sequence definition. + ** + ******************************************************************************/ +/* ADC sequence definition */ +#define ADC_SEQ_A ((uint8_t)0) +#define ADC_SEQ_B ((uint8_t)1) + +/* ADC pin definition */ +#define ADC1_IN0 ((uint8_t)0) +#define ADC1_IN1 ((uint8_t)1) +#define ADC1_IN2 ((uint8_t)2) +#define ADC1_IN3 ((uint8_t)3) +#define ADC12_IN4 ((uint8_t)4) +#define ADC12_IN5 ((uint8_t)5) +#define ADC12_IN6 ((uint8_t)6) +#define ADC12_IN7 ((uint8_t)7) +#define ADC12_IN8 ((uint8_t)8) +#define ADC12_IN9 ((uint8_t)9) +#define ADC12_IN10 ((uint8_t)10) +#define ADC12_IN11 ((uint8_t)11) +#define ADC1_IN12 ((uint8_t)12) +#define ADC1_IN13 ((uint8_t)13) +#define ADC1_IN14 ((uint8_t)14) +#define ADC1_IN15 ((uint8_t)15) +#define ADC_PIN_INVALID ((uint8_t)0xFF) + +/* ADC channel index definition */ +#define ADC_CH_IDX0 (0u) +#define ADC_CH_IDX1 (1u) +#define ADC_CH_IDX2 (2u) +#define ADC_CH_IDX3 (3u) +#define ADC_CH_IDX4 (4u) +#define ADC_CH_IDX5 (5u) +#define ADC_CH_IDX6 (6u) +#define ADC_CH_IDX7 (7u) +#define ADC_CH_IDX8 (8u) +#define ADC_CH_IDX9 (9u) +#define ADC_CH_IDX10 (10u) +#define ADC_CH_IDX11 (11u) +#define ADC_CH_IDX12 (12u) +#define ADC_CH_IDX13 (13u) +#define ADC_CH_IDX14 (14u) +#define ADC_CH_IDX15 (15u) +#define ADC_CH_IDX16 (16u) + +/* ADC1 channel mask definition */ +#define ADC1_CH0 (0x1ul << 0u) ///< Default mapping pin ADC1_IN0 +#define ADC1_CH1 (0x1ul << 1u) ///< Default mapping pin ADC1_IN1 +#define ADC1_CH2 (0x1ul << 2u) ///< Default mapping pin ADC1_IN2 +#define ADC1_CH3 (0x1ul << 3u) ///< Default mapping pin ADC1_IN3 +#define ADC1_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN4 +#define ADC1_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN5 +#define ADC1_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN6 +#define ADC1_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN7 +#define ADC1_CH8 (0x1ul << 8u) ///< Default mapping pin ADC12_IN8 +#define ADC1_CH9 (0x1ul << 9u) ///< Default mapping pin ADC12_IN9 +#define ADC1_CH10 (0x1ul << 10u) ///< Default mapping pin ADC12_IN10 +#define ADC1_CH11 (0x1ul << 11u) ///< Default mapping pin ADC12_IN11 +#define ADC1_CH12 (0x1ul << 12u) ///< Default mapping pin ADC12_IN12 +#define ADC1_CH13 (0x1ul << 13u) ///< Default mapping pin ADC12_IN13 +#define ADC1_CH14 (0x1ul << 14u) ///< Default mapping pin ADC12_IN14 +#define ADC1_CH15 (0x1ul << 15u) ///< Default mapping pin ADC12_IN15 +#define ADC1_CH16 (0x1ul << 16u) +#define ADC1_CH_INTERNAL (ADC1_CH16) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC1_CH_ALL (0x0001FFFFul) +#define ADC1_PIN_MASK_ALL (ADC1_CH_ALL & ~ADC1_CH_INTERNAL) + +/* ADC2 channel definition */ +#define ADC2_CH0 (0x1ul << 0u) ///< Default mapping pin ADC12_IN4 +#define ADC2_CH1 (0x1ul << 1u) ///< Default mapping pin ADC12_IN5 +#define ADC2_CH2 (0x1ul << 2u) ///< Default mapping pin ADC12_IN6 +#define ADC2_CH3 (0x1ul << 3u) ///< Default mapping pin ADC12_IN7 +#define ADC2_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN8 +#define ADC2_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN9 +#define ADC2_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN10 +#define ADC2_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN11 +#define ADC2_CH8 (0x1ul << 8u) +#define ADC2_CH_INTERNAL (ADC2_CH8) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC2_CH_ALL (0x000001FFul) +#define ADC2_PIN_MASK_ALL (ADC2_CH_ALL & ~ADC2_CH_INTERNAL) + +/* +* PGA channel definition. +* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel. +*/ +#define PGA_CH_NONE (0x0000u) ///< PGA channel none selection. +#define PGA_CH0 (0x0001u) ///< Mapping pin ADC1_IN0 +#define PGA_CH1 (0x0002u) ///< Mapping pin ADC1_IN1 +#define PGA_CH2 (0x0004u) ///< Mapping pin ADC1_IN2 +#define PGA_CH3 (0x0008u) ///< Mapping pin ADC1_IN3 +#define PGA_CH4 (0x0010u) ///< Mapping pin ADC12_IN4 +#define PGA_CH5 (0x0020u) ///< Mapping pin ADC12_IN5 +#define PGA_CH6 (0x0040u) ///< Mapping pin ADC12_IN6 +#define PGA_CH7 (0x0080u) ///< Mapping pin ADC12_IN7 +#define PGA_CH8 (0x0100u) ///< Mapping internal 8bit DAC1 output + +/* ADC1 has up to 17 channels */ +#define ADC1_CH_COUNT (17u) + +/* ADC2 has up to 9 channels */ +#define ADC2_CH_COUNT (9u) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit); +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx); + +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode); +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg); +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg); +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); + +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt); +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg); +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn); +void ADC_PgaCmd(en_functional_state_t enState); +void ADC_PgaSelChannel(uint16_t u16Channel); + +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay); +void ADC_SyncCmd(en_functional_state_t enState); + +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx); +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx); +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout); + +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length); +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh); + +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin); +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +//@} // AdcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_aes.h b/lib/hc32f460/driver/inc/hc32f460_aes.h new file mode 100644 index 000000000000..d9fd7e672e49 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_aes.h @@ -0,0 +1,76 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.h + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ +#ifndef __HC32F460_AES_H__ +#define __HC32F460_AES_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AesGroup Advanced Encryption Standard(AES) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* AES key length in bytes is 16. */ +#define AES_KEYLEN ((uint8_t)16) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext); + +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext); + +//@} // AesGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_can.h b/lib/hc32f460/driver/inc/hc32f460_can.h new file mode 100644 index 000000000000..fa0e0416d631 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_can.h @@ -0,0 +1,513 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.h + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of CAN + ** + ******************************************************************************/ +#ifndef __HC32F460_CAN_H__ +#define __HC32F460_CAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CanGroup Controller Area Network(CAN) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The Can error types. + ******************************************************************************/ +typedef enum +{ + NO_ERROR = 0U, + BIT_ERROR = 1U, + FORM_ERROR = 2U, + STUFF_ERROR = 3U, + ACK_ERROR = 4U, + CRC_ERROR = 5U, + UNKOWN_ERROR = 6U, +}en_can_error_t; + +/** + ******************************************************************************* + ** \brief The Can transmit buffer select.(TCMD) + ******************************************************************************/ +typedef enum +{ + CanPTBSel = 0U, ///< high-priority buffer + CanSTBSel = 1U, ///< secondary buffer +}en_can_buffer_sel_t; + +/** + ******************************************************************************* + ** \brief The Can warning limits.(AFWL) + ******************************************************************************/ +typedef struct stc_can_warning_limit +{ + uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit + uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit +}stc_can_warning_limit_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Frame Format Check.(ACF) + ******************************************************************************/ +typedef enum en_can_acf_format_en +{ + CanStdFrames = 0x02u, ///< Accepts only Standard frames + CanExtFrames = 0x03u, ///< Accepts only Extended frames + CanAllFrames = 0x00u, ///< Accepts both standard or extended frames +}en_can_acf_format_en_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Enable.(ACFEN) + ******************************************************************************/ +typedef enum en_can_filter_sel +{ + CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable + CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable + CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable + CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable + CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable + CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable + CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable + CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable +}en_can_filter_sel_t; + +/** + ******************************************************************************* + ** \brief The can interrupt enable.(IE) + ******************************************************************************/ +typedef enum +{ + //<empty and =almost full, but not full and no overflow + CanRxBufFull = 3, ///< full +}en_can_rx_buf_status_t; + +/** + ******************************************************************************* + ** \brief The Can Transmission secondary Status.(TSSTAT) + ******************************************************************************/ +typedef enum +{ + CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty + ///< TTEN=1 and TTTBM=1: PTB and STB are empty + CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full + ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full + CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full + ///< TTEN=1 and TTTBM=1: None + CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full + ///< TTEN=1 and TTTBM=1: PTB and STB are full +}en_can_tx_buf_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Acceptance Filter Code and Mask. + ******************************************************************************/ +typedef struct stc_can_filter +{ + uint32_t u32CODE; ///< Acceptance CODE + uint32_t u32MASK; ///< Acceptance MASK + en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable + en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check. +}stc_can_filter_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Bit Timing. + ******************************************************************************/ +typedef struct stc_can_bt +{ + uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ) + uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ) + uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ) + uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ) +}stc_can_bt_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Control Frame. + ******************************************************************************/ +typedef struct +{ + uint32_t DLC : 4; ///< Data length code + uint32_t RESERVED0 : 2; ///< Ignore + uint32_t RTR : 1; ///< Remote transmission request + uint32_t IDE : 1; ///< IDentifier extension + uint32_t RESERVED1 : 24; ///< Ignore +}stc_can_txcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Tx Frame. + ******************************************************************************/ +typedef struct stc_can_txframe +{ + union + { + uint32_t TBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t TBUF32_1; ///< Ignore + stc_can_txcontrol_t Control_f; ///< CAN Tx Control + }; + union + { + uint32_t TBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; + en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select +}stc_can_txframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx Ctrl. + ******************************************************************************/ +typedef struct +{ + uint8_t DLC : 4; ///< Data length code + uint8_t RESERVED0 : 2; ///< Ignore + uint8_t RTR : 1; ///< Remote transmission request + uint8_t IDE : 1; ///< IDentifier extension +}stc_can_rxcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN status. + ******************************************************************************/ +typedef struct +{ + uint8_t RESERVED0 : 4; ///< Ignore + uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated + uint8_t KOER : 3; ///< Kind of error +}stc_can_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN control, status and cycletime. + ******************************************************************************/ +typedef struct +{ + stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t + stc_can_status_t Status_f; ///< @ref stc_can_status_t + uint16_t CycleTime; ///< TTCAN cycletime +}stc_can_cst_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_rxframe +{ + union + { + uint32_t RBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t RBUF32_1; ///< Ignore + stc_can_cst_t Cst; ///< @ref stc_can_cst_t + }; + union + { + uint32_t RBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; +}stc_can_rxframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_init_config +{ + en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t + en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t + en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t + en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t + stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t + stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t + stc_can_filter_t *pstcFilter; ///< @ref stc_can_filter_t Pointer to a stc_can_filter_t type array that \ + ///< contains the configuration informations of the acceptance filters. + uint8_t u8FilterCount; ///< Number of filters that to to initialized. +}stc_can_init_config_t; + +/** + ******************************************************************************* + ** \brief CAN TTCAN + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN pointer to a TB message slot + ******************************************************************************/ +typedef enum +{ + CanTTcanPTBSel = 0x00u, ///< PTB + CanTTcanSTB1Sel = 0x01u, ///< STB1 + CanTTcanSTB2Sel = 0x02u, ///< STB2 + CanTTcanSTB3Sel = 0x03u, ///< STB3 + CanTTcanSTB4Sel = 0x04u, ///< STB4 +}en_can_ttcan_tbslot_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Timer prescaler + ******************************************************************************/ +typedef enum +{ + CanTTcanTprescDiv1 = 0x00u, ///< Div1 + CanTTcanTprescDiv2 = 0x01u, ///< Div2 + CanTTcanTprescDiv3 = 0x02u, ///< Div3 + CanTTcanTprescDiv4 = 0x03u, ///< Div4 +}en_can_ttcan_Tpresc_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Trigger type + ******************************************************************************/ +typedef enum +{ + CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission + CanTTcanTime = 0x01, ///< Time trigger for receive trigger + CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows + CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows + CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows +}en_can_ttcan_trigger_type_t; + +typedef enum +{ + CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt + CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt +}en_can_ttcan_irq_type_t; + + +typedef struct stc_can_ttcan_ref_msg +{ + uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard; + union ///< Reference message ID + { + uint32_t RefStdID; ///< Reference standard ID + uint32_t RefExtID; ///< Reference Extended ID + }; +}stc_can_ttcan_ref_msg_t; + +typedef struct stc_can_ttcan_trigger_config +{ + en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer + en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type + en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler + uint8_t u8Tew; ///< Transmit enable window + uint16_t u16TrigTime; ///< TTCAN trigger time + uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register +}stc_can_ttcan_trigger_config_t; + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg); +void CAN_DeInit(void); +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState); +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState); +en_can_error_t CAN_ErrorStatusGet(void); +bool CAN_StatusGet(en_can_status_t enCanStatus); + +void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount); +void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState); + +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame); +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd); +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame); + +uint8_t CAN_ArbitrationLostCap(void); +uint8_t CAN_RxErrorCntGet(void); +uint8_t CAN_TxErrorCntGet(void); + + +//<< void CAN_TTCAN_Enable(void); +//<< void CAN_TTCAN_Disable(void); +//<< void CAN_TTCAN_IrqCmd(void); +//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg); +//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg); + +//@} // CanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/lib/hc32f460/driver/inc/hc32f460_clk.h b/lib/hc32f460/driver/inc/hc32f460_clk.h new file mode 100644 index 000000000000..b0de3fcbb9b0 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_clk.h @@ -0,0 +1,642 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.h + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ +#ifndef __HC32F460_CLK_H__ +#define __HC32F460_CLK_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmuGroup Clock Manage Unit(CMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The system clock source. + ** + ******************************************************************************/ + typedef enum en_clk_sys_source + { + ClkSysSrcHRC = 0u, ///< The system clock source is HRC. + ClkSysSrcMRC = 1u, ///< The system clock source is MRC. + ClkSysSrcLRC = 2u, ///< The system clock source is LRC. + ClkSysSrcXTAL = 3u, ///< The system clock source is XTAL. + ClkSysSrcXTAL32 = 4u, ///< The system clock source is XTAL32. + CLKSysSrcMPLL = 5u, ///< The system clock source is MPLL. + }en_clk_sys_source_t; + +/** + ******************************************************************************* + ** \brief The pll clock source. + ** + ******************************************************************************/ + typedef enum en_clk_pll_source + { + ClkPllSrcXTAL = 0u, ///< The pll clock source is XTAL. + ClkPllSrcHRC = 1u, ///< The pll clock source is HRC. + }en_clk_pll_source_t; + +/** + ******************************************************************************* + ** \brief The usb clock source. + ** + ******************************************************************************/ +typedef enum en_clk_usb_source +{ + ClkUsbSrcSysDiv2 = 2u, ///< The usb clock source is 1/2 system clock. + ClkUsbSrcSysDiv3 = 3u, ///< The usb clock source is 1/3 system clock. + ClkUsbSrcSysDiv4 = 4u, ///< The usb clock source is 1/4 system clock. + ClkUsbSrcMpllp = 8u, ///< The usb clock source is MPLLP. + ClkUsbSrcMpllq = 9u, ///< The usb clock source is MPLLQ. + ClkUsbSrcMpllr = 10u, ///< The usb clock source is MPLLR. + ClkUsbSrcUpllp = 11u, ///< The usb clock source is UPLLP. + ClkUsbSrcUpllq = 12u, ///< The usb clock source is UPLLQ. + ClkUsbSrcUpllr = 13u, ///< The usb clock source is UPLLR. +}en_clk_usb_source_t; + +/** + ******************************************************************************* + ** \brief The peripheral(adc/trng/I2S) clock source. + ** + ******************************************************************************/ +typedef enum en_clk_peri_source +{ + ClkPeriSrcPclk = 0u, ///< The peripheral(adc/trng/I2S) clock source is division from system clock. + ClkPeriSrcMpllp = 8u, ///< The peripheral(adc/trng/I2S) clock source is MPLLP. + ClkPeriSrcMpllq = 9u, ///< The peripheral(adc/trng/I2S) clock source is MPLLQ. + ClkPeriSrcMpllr = 10u, ///< The peripheral(adc/trng/I2S) clock source is MPLLR. + ClkPeriSrcUpllp = 11u, ///< The peripheral(adc/trng/I2S) clock source is UPLLP. + ClkPeriSrcUpllq = 12u, ///< The peripheral(adc/trng/I2S) clock source is UPLLQ. + ClkPeriSrcUpllr = 13u, ///< The peripheral(adc/trng/I2S) clock source is UPLLR. +}en_clk_peri_source_t; + +/** + ******************************************************************************* + ** \brief The clock output source. + ** + ******************************************************************************/ +typedef enum en_clk_output_source +{ + ClkOutputSrcHrc = 0u, ///< The clock output source is HRC + ClkOutputSrcMrc = 1u, ///< The clock output source is MRC. + ClkOutputSrcLrc = 2u, ///< The clock output source is LRC. + ClkOutputSrcXtal = 3u, ///< The clock output source is XTAL. + ClkOutputSrcXtal32 = 4u, ///< The clock output source is XTAL32 + ClkOutputSrcMpllp = 6u, ///< The clock output source is MPLLP. + ClkOutputSrcUpllp = 7u, ///< The clock output source is UPLLP. + ClkOutputSrcMpllq = 8u, ///< The clock output source is MPLLQ. + ClkOutputSrcUpllq = 9u, ///< The clock output source is UPLLQ. + ClkOutputSrcSysclk = 11u, ///< The clock output source is system clock. +}en_clk_output_source_t; + +/** + ******************************************************************************* + ** \brief The clock frequency source for measure or reference. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_source +{ + ClkFcmSrcXtal = 0u, ///< The clock frequency measure or reference source is XTAL + ClkFcmSrcXtal32 = 1u, ///< The clock frequency measure or reference source is XTAL32. + ClkFcmSrcHrc = 2u, ///< The clock frequency measure or reference source is HRC. + ClkFcmSrcLrc = 3u, ///< The clock frequency measure or reference source is LRC. + ClkFcmSrcSwdtrc = 4u, ///< The clock frequency measure or reference source is SWDTRC + ClkFcmSrcPclk1 = 5u, ///< The clock frequency measure or reference source is PCLK1. + ClkFcmSrcUpllp = 6u, ///< The clock frequency measure or reference source is UPLLP. + ClkFcmSrcMrc = 7u, ///< The clock frequency measure or reference source is MRC. + ClkFcmSrcMpllp = 8u, ///< The clock frequency measure or reference source is MPLLP. + ClkFcmSrcRtcLrc = 9u, ///< The clock frequency measure or reference source is RTCLRC. +}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t; + +/** + ******************************************************************************* + ** \brief The clock flag status. + ** + ******************************************************************************/ +typedef enum en_clk_flag +{ + ClkFlagHRCRdy = 0u, ///< The clock flag is HRC ready. + ClkFlagXTALRdy = 1u, ///< The clock flag is XTAL ready. + ClkFlagMPLLRdy = 2u, ///< The clock flag is MPLL ready. + ClkFlagUPLLRdy = 3u, ///< The clock flag is UPLL ready. + ClkFlagXTALStoppage = 4u, ///< The clock flag is XTAL stoppage. +}en_clk_flag_t; + +/** + ******************************************************************************* + ** \brief The clock frequency measure flag status. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_flag +{ + ClkFcmFlagErrf = 0u, ///< The clock frequency flag is frequency abnormal. + ClkFcmFlagMendf = 1u, ///< The clock frequency flag is end of measurement. + ClkFcmFlagOvf = 2u, ///< The clock frequency flag is counter overflow. +}en_clk_fcm_flag_t; + +/** + ******************************************************************************* + ** \brief The source of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_mode +{ + ClkXtalModeOsc = 0u, ///< Use external high speed osc as source. + ClkXtalModeExtClk = 1u, ///< Use external clk as source. +}en_clk_xtal_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_drv +{ + ClkXtalHighDrv = 0u, ///< High drive capability.20MHz~24MHz. + ClkXtalMidDrv = 1u, ///< Middle drive capability.16MHz~20MHz. + ClkXtalLowDrv = 2u, ///< Low drive capability.8MHz~16MHz. + ClkXtalTinyDrv = 3u, ///< Tiny drive capability.8MHz. +}en_clk_xtal_drv_t; + +/** + ******************************************************************************* + ** \brief The stable time of XTAL. + ** + ** \note It depends on SUPDRV bit. + ******************************************************************************/ +typedef enum en_clk_xtal_stb_cycle +{ + ClkXtalStbCycle35 = 1u, ///< stable time is 35(36) cycle. + ClkXtalStbCycle67 = 2u, ///< stable time is 67(68) cycle. + ClkXtalStbCycle131 = 3u, ///< stable time is 131(132) cycle. + ClkXtalStbCycle259 = 4u, ///< stable time is 259(260) cycle. + ClkXtalStbCycle547 = 5u, ///< stable time is 547(548) cycle. + ClkXtalStbCycle1059 = 6u, ///< stable time is 1059(1060) cycle. + ClkXtalStbCycle2147 = 7u, ///< stable time is 2147(2148) cycle. + ClkXtalStbCycle4291 = 8u, ///< stable time is 4291(4292) cycle. + ClkXtalStbCycle8163 = 9u, ///< stable time is 8163(8164) cycle. +}en_clk_xtal_stb_cycle_t; + +/** + ******************************************************************************* + ** \brief The handle of xtal stoppage. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_stp_mode +{ + ClkXtalStpModeInt = 0u, ///< The handle of stoppage is interrupt. + ClkXtalStpModeReset = 1u, ///< The handle of stoppage is reset. +}en_clk_xtal_stp_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_drv +{ + ClkXtal32MidDrv = 0u, ///< Middle drive capability.32.768KHz. + ClkXtal32HighDrv = 1u, ///< High drive capability.32.768KHz. +}en_clk_xtal32_drv_t; + +/** + ******************************************************************************* + ** \brief The filter mode of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_filter_mode +{ + ClkXtal32FilterModeFull = 0u, ///< Valid in run,stop,power down mode. + ClkXtal32FilterModePart = 2u, ///< Valid in run mode. + ClkXtal32FilterModeNone = 3u, ///< Invalid in run,stop,power down mode. +}en_clk_xtal32_filter_mode_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock. + ** + ******************************************************************************/ +typedef enum en_clk_sysclk_div_factor +{ + ClkSysclkDiv1 = 0u, ///< 1 division. + ClkSysclkDiv2 = 1u, ///< 2 division. + ClkSysclkDiv4 = 2u, ///< 4 division. + ClkSysclkDiv8 = 3u, ///< 8 division. + ClkSysclkDiv16 = 4u, ///< 16 division. + ClkSysclkDiv32 = 5u, ///< 32 division. + ClkSysclkDiv64 = 6u, ///< 64 division. +}en_clk_sysclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock.It will be used for debug clock. + ** + ******************************************************************************/ +typedef enum en_clk_tpiuclk_div_factor +{ + ClkTpiuclkDiv1 = 0u, ///< 1 division. + ClkTpiuclkDiv2 = 1u, ///< 2 division. + ClkTpiuclkDiv4 = 2u, ///< 4 division. +}en_clk_tpiuclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_div_factor +{ + ClkOutputDiv1 = 0u, ///< 1 division. + ClkOutputDiv2 = 1u, ///< 2 division. + ClkOutputDiv4 = 2u, ///< 4 division. + ClkOutputDiv8 = 3u, ///< 8 division. + ClkOutputDiv16 = 4u, ///< 16 division. + ClkOutputDiv32 = 5u, ///< 32 division. + ClkOutputDiv64 = 6u, ///< 64 division. + ClkOutputDiv128 = 7u, ///< 128 division. +}en_clk_output_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm measure source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_measure_div_factor +{ + ClkFcmMeaDiv1 = 0u, ///< 1 division. + ClkFcmMeaDiv4 = 1u, ///< 4 division. + ClkFcmMeaDiv8 = 2u, ///< 8 division. + ClkFcmMeaDiv32 = 3u, ///< 32 division. +}en_clk_fcm_measure_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_intref_div_factor +{ + ClkFcmIntrefDiv32 = 0u, ///< 32 division. + ClkFcmIntrefDiv128 = 1u, ///< 128 division. + ClkFcmIntrefDiv1024 = 2u, ///< 1024 division. + ClkFcmIntrefDiv8192 = 3u, ///< 8192 division. +}en_clk_fcm_intref_div_factor_t; + +/** + ******************************************************************************* + ** \brief The edge of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_edge +{ + ClkFcmEdgeRising = 0u, ///< Rising edge. + ClkFcmEdgeFalling = 1u, ///< Falling edge. + ClkFcmEdgeBoth = 2u, ///< Both edge. +}en_clk_fcm_edge_t; + +/** + ******************************************************************************* + ** \brief The filter clock of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_filter_clk +{ + ClkFcmFilterClkNone = 0u, ///< None filter. + ClkFcmFilterClkFcmSrc = 1u, ///< Use fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv4 = 2u, ///< Use 1/4 fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv16 = 3u, ///< Use 1/16 fcm measurement source as filter clock. +}en_clk_fcm_filter_clk_t; + +/** + ******************************************************************************* + ** \brief The fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_refer +{ + ClkFcmExtRef = 0u, ///< Use external reference. + ClkFcmInterRef = 1u, ///< Use internal reference. +}en_clk_fcm_refer_t; + +/** + ******************************************************************************* + ** \brief The handle of fcm abnormal. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_abnormal_handle +{ + ClkFcmHandleInterrupt = 0u, ///< The handle of fcm abnormal is interrupt. + ClkFcmHandleReset = 1u, ///< The handle of fcm abnormal is reset. +}en_clk_fcm_abnormal_handle_t; + +/** + ******************************************************************************* + ** \brief The channel of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_ch +{ + ClkOutputCh1 = 1u, ///< The output of clk is MCO_1. + ClkOutputCh2 = 2u, ///< The output of clk is MCO_2. +}en_clk_output_ch_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL. + ** + ** \note Configures the XTAL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_cfg +{ + en_functional_state_t enFastStartup; ///< Enable fast start up or not. + en_clk_xtal_mode_t enMode; ///< Select xtal mode. + en_clk_xtal_drv_t enDrv; ///< Select xtal drive capability. +}stc_clk_xtal_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL stoppage. + ** + ** \note Configures the XTAL stoppage if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_stp_cfg +{ + en_functional_state_t enDetect; ///< Enable detect stoppage or not. + en_clk_xtal_stp_mode_t enMode; ///< Select the handle of xtal stoppage. + en_functional_state_t enModeReset; ///< Enable reset for handle the xtal stoppage. + en_functional_state_t enModeInt; ///< Enable interrupt for handle the xtal stoppage. +}stc_clk_xtal_stp_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL32. + ** + ** \note Configures the XTAL32 if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal32_cfg +{ + en_clk_xtal32_drv_t enDrv; ///< Select xtal32 drive capability. + en_clk_xtal32_filter_mode_t enFilterMode; ///< The filter mode of xtal32. +}stc_clk_xtal32_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of PLL. + ** + ** \note Configures the PLL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_pll_cfg +{ + uint32_t PllpDiv; ///< Pllp clk, division factor of VCO out. + uint32_t PllqDiv; ///< Pllq clk, division factor of VCO out. + uint32_t PllrDiv; ///< Pllr clk, division factor of VCO out. + uint32_t plln; ///< Multiplication factor of vco out, ensure between 240M~480M + uint32_t pllmDiv; ///< Division factor of VCO in, ensure between 1M~12M. +}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of system clock. + ** + ** \note Configures the system clock if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_sysclk_cfg +{ + en_clk_sysclk_div_factor_t enHclkDiv; ///< Division for hclk. + en_clk_sysclk_div_factor_t enExclkDiv; ///< Division for exclk. + en_clk_sysclk_div_factor_t enPclk0Div; ///< Division for pclk0. + en_clk_sysclk_div_factor_t enPclk1Div; ///< Division for pclk1. + en_clk_sysclk_div_factor_t enPclk2Div; ///< Division for pclk2. + en_clk_sysclk_div_factor_t enPclk3Div; ///< Division for pclk3. + en_clk_sysclk_div_factor_t enPclk4Div; ///< Division for pclk4. +}stc_clk_sysclk_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of clock output. + ** + ** \note Configures the clock output if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_output_cfg +{ + en_clk_output_source_t enOutputSrc; ///< The clock output source. + en_clk_output_div_factor_t enOutputDiv; ///< The division factor of clock output source. +}stc_clk_output_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm window. + ** + ** \note Configures the fcm window if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_window_cfg +{ + uint16_t windowLower; ///< The lower value of the window. + uint16_t windowUpper; ///< The upper value of the window. +}stc_clk_fcm_window_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm measurement. + ** + ** \note Configures the fcm measurement if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_measure_cfg +{ + en_clk_fcm_measure_source_t enSrc; ///< The measurement source. + en_clk_fcm_measure_div_factor_t enSrcDiv; ///< The division factor of measurement source. +}stc_clk_fcm_measure_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm reference. + ** + ** \note Configures the fcm reference if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_reference_cfg +{ + en_functional_state_t enExtRef; ///< Enable external reference or not. + en_clk_fcm_edge_t enEdge; ///< The edge of internal reference. + en_clk_fcm_filter_clk_t enFilterClk; ///< The filter clock of internal reference. + en_clk_fcm_refer_t enRefSel; ///< Select reference. + en_clk_fcm_intref_source_t enIntRefSrc; ///< Select internal reference. + en_clk_fcm_intref_div_factor_t enIntRefDiv; ///< The division factor of internal reference. +}stc_clk_fcm_reference_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm interrupt. + ** + ** \note Configures the fcm interrupt if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_interrupt_cfg +{ + en_clk_fcm_abnormal_handle_t enHandleSel; ///< Use interrupt or reset. + en_functional_state_t enHandleReset; ///< Enable reset or not. + en_functional_state_t enHandleInterrupt; ///< Enable interrupt or not. + en_functional_state_t enOvfInterrupt; ///< Enable overflow interrupt or not. + en_functional_state_t enEndInterrupt; ///< Enable measurement end interrupt or not. +}stc_clk_fcm_interrupt_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm. + ** + ** \note Configures the fcm if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_cfg +{ + stc_clk_fcm_window_cfg_t *pstcFcmWindowCfg; ///< Window configuration struct. + stc_clk_fcm_measure_cfg_t *pstcFcmMeaCfg; ///< Measurement configuration struct. + stc_clk_fcm_reference_cfg_t *pstcFcmRefCfg; ///< Reference configuration struct. + stc_clk_fcm_interrupt_cfg_t *pstcFcmIntCfg; ///< Interrupt configuration struct. +}stc_clk_fcm_cfg_t; + +/** + ******************************************************************************* + ** \brief Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_clk_freq +{ + uint32_t sysclkFreq; ///< System clock frequency. + uint32_t hclkFreq; ///< Hclk frequency. + uint32_t exckFreq; ///< Exclk frequency. + uint32_t pclk0Freq; ///< Pclk0 frequency. + uint32_t pclk1Freq; ///< Pclk1 frequency. + uint32_t pclk2Freq; ///< Pclk2 frequency. + uint32_t pclk3Freq; ///< Pclk3 frequency. + uint32_t pclk4Freq; ///< Pclk4 frequency. +}stc_clk_freq_t; + +/** + ******************************************************************************* + ** \brief PLL Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_pll_clk_freq +{ + uint32_t mpllp; ///< mpllp clock frequency. + uint32_t mpllq; ///< mpllq clock frequency. + uint32_t mpllr; ///< mpllr clock frequency. + uint32_t upllp; ///< upllp clock frequency. + uint32_t upllq; ///< upllq clock frequency. + uint32_t upllr; ///< upllr clock frequency. +}stc_pll_clk_freq_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg); +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb); +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg); +en_result_t CLK_XtalCmd(en_functional_state_t enNewState); + +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg); +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t trimValue); +en_result_t CLK_HrcCmd(en_functional_state_t enNewState); + +void CLK_MrcTrim(int8_t trimValue); +en_result_t CLK_MrcCmd(en_functional_state_t enNewState); + +void CLK_LrcTrim(int8_t trimValue); +en_result_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc); +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg); +en_result_t CLK_MpllCmd(en_functional_state_t enNewState); + +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg); +en_result_t CLK_UpllCmd(en_functional_state_t enNewState); + +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc); +en_clk_sys_source_t CLK_GetSysClkSource(void); + +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg); +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq); +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq); + +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc); +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc); +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc); +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg); + +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv); +void CLK_TpiuClkCmd(en_functional_state_t enNewState); + +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg); +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState); +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag); + +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg); +void CLK_FcmCmd(en_functional_state_t enNewState); + +uint16_t CLK_GetFcmCounter(void); +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag); +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag); + +void CLK_ClearXtalStdFlag(void); + +//@} // CmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_cmp.h b/lib/hc32f460/driver/inc/hc32f460_cmp.h new file mode 100644 index 000000000000..3915ca7f1074 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_cmp.h @@ -0,0 +1,274 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.h + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ +#ifndef __HC32F460_CMP_H__ +#define __HC32F460_CMP_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmpGroup Comparator(CMP) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief CMP function enumeration + ******************************************************************************/ +typedef enum en_cmp_func +{ + CmpVcoutOutput = (1u << 12), ///< CMP vcout output enable function + CmpOutpuInv = (1u << 13), ///< CMP output invert enable function + CmpOutput = (1u << 14), ///< CMP output enable function +} en_cmp_func_t; + +/** + ******************************************************************************* + ** \brief CMP edge selection enumeration + ******************************************************************************/ +typedef enum en_cmp_edge_sel +{ + CmpNoneEdge = 0u, ///< None edge detection + CmpRisingEdge = 1u, ///< Rising edge detection + CmpFaillingEdge = 2u, ///< Falling edge detection + CmpBothEdge = 3u, ///< Falling or Rising edge detection +} en_cmp_edge_sel_t; + +/** + ******************************************************************************* + ** \brief CMP filter sample clock division enumeration + ******************************************************************************/ +typedef enum en_cmp_fltclk_div +{ + CmpNoneFlt = 0u, ///< Unuse filter + CmpFltPclk3Div1 = 1u, ///< PCLK3/1 + CmpFltPclk3Div2 = 2u, ///< PCLK3/2 + CmpFltPclk3Div4 = 3u, ///< PCLK3/4 + CmpFltPclk3Div8 = 4u, ///< PCLK3/8 + CmpFltPclk3Div16 = 5u, ///< PCLK3/16 + CmpFltPclk3Div32 = 6u, ///< PCLK3/32 + CmpFltPclk3Div64 = 7u, ///< PCLK3/64 +} en_cmp_fltclk_div_t; + +/** + ******************************************************************************* + ** \brief CMP INP4 input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp4_sel +{ + CmpInp4None = 0u, ///< None input + CmpInp4PGAO = 1u, ///< PGAO output + CmpInp4PGAO_BP = 2u, ///< PGAO_BP output + CmpInp4CMP1_INP4 = 4u, ///< CMP1_INP4 +} en_cmp_inp4_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp_sel +{ + CmpInpNone = 0u, ///< None input + CmpInp1 = 1u, ///< INP1 input + CmpInp2 = 2u, ///< INP2 input + CmpInp1_Inp2 = 3u, ///< INP1 INP2 input + CmpInp3 = 4u, ///< INP3 input + CmpInp1_Inp3 = 5u, ///< INP1 INP3 input + CmpInp2_Inp3 = 6u, ///< INP2 INP3 input + CmpInp1_Inp2_Inp3 = 7u, ///< INP1 INP2 INP3 input + CmpInp4 = 8u, ///< INP4 input + CmpInp1_Inp4 = 9u, ///< INP1 INP4 input + CmpInp2_Inp4 = 10u, ///< INP2 INP4 input + CmpInp1_Inp2_Inp4 = 11u, ///< INP1 INP2 INP4 input + CmpInp3_Inp4 = 12u, ///< INP3 INP4 input + CmpInp1_Inp3_Inp4 = 13u, ///< INP1 INP3 INP4 input + CmpInp2_Inp3_Inp4 = 14u, ///< INP2 INP3 INP4 input + CmpInp1_Inp2_Inp3_Inp4 = 15u, ///< INP1 INP2 INP3 INP4 input +} en_cmp_inp_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INM input enumeration + ******************************************************************************/ +typedef enum en_cmp_inm_sel +{ + CmpInmNone = 0u, ///< None input + CmpInm1 = 1u, ///< INM1 input + CmpInm2 = 2u, ///< INM2 input + CmpInm3 = 4u, ///< INM3 input + CmpInm4 = 8u, ///< INM4 input +} en_cmp_inm_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_inp_state +{ + CmpInpNoneState = 0u, ///< none input state + CmpInp1State = 1u, ///< INP1 input state + CmpInp2State = 2u, ///< INP2 input state + CmpInp3State = 4u, ///< INP3 input state + CmpInp4State = 8u, ///< INP4 input state +} en_cmp_inp_state_t; + +/** + ******************************************************************************* + ** \brief CMP Output State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_output_state +{ + CmpOutputLow = 0u, ///< Compare output Low "0" + CmpOutputHigh = 1u, ///< Compare output High "1" +} en_cmp_output_state_t; + +/** + ******************************************************************************* + ** \brief CMP input selection + ******************************************************************************/ +typedef struct stc_cmp_input_sel +{ + en_cmp_inm_sel_t enInmSel; ///< CMP INM sel + + en_cmp_inp_sel_t enInpSel; ///< CMP INP sel + + en_cmp_inp4_sel_t enInp4Sel; ///< CMP INP4 sel +} stc_cmp_input_sel_t; + +/** + ****************************************************************************** + ** \brief DAC channel + ******************************************************************************/ +typedef enum en_cmp_dac_ch +{ + CmpDac1 = 0u, ///< DAC1 + CmpDac2 = 1u, ///< DAC2 +} en_cmp_dac_ch_t; + +/** + ****************************************************************************** + ** \brief ADC internal reference voltage path + ******************************************************************************/ +typedef enum en_cmp_adc_int_ref_volt_path +{ + CmpAdcRefVoltPathDac1 = (1u << 0u), ///< ADC internal reference voltage path: DAC1 + CmpAdcRefVoltPathDac2 = (1u << 1u), ///< ADC internal reference voltage path: DAC2 + CmpAdcRefVoltPathVref = (1u << 4u), ///< ADC internal reference voltage path: VREF +} en_cmp_adc_int_ref_volt_path_t; + +/** + ******************************************************************************* + ** \brief CMP initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_init +{ + en_cmp_edge_sel_t enEdgeSel; ///< CMP edge sel + + en_cmp_fltclk_div_t enFltClkDiv; ///< CMP FLTclock division + + en_functional_state_t enCmpOutputEn; ///< CMP Output enable + + en_functional_state_t enCmpVcoutOutputEn; ///< CMP output result enable + + en_functional_state_t enCmpInvEn; ///< CMP INV sel for output + + en_functional_state_t enCmpIntEN; ///< CMP interrupt enable +} stc_cmp_init_t; + +/** + ******************************************************************************* + ** \brief CMP DAC initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_dac_init +{ + uint8_t u8DacData; ///< CMP DAC Data register value + + en_functional_state_t enCmpDacEN; ///< CMP DAC enable +} stc_cmp_dac_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg); +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx); +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod); +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd); +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv); +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel); +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx); +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel); +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel); +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel); +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel); +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx); +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx); +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx); +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg); +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh); +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd); +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData); +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh); +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath); + +//@} // CmpGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_crc.h b/lib/hc32f460/driver/inc/hc32f460_crc.h new file mode 100644 index 000000000000..57066550ecd1 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_crc.h @@ -0,0 +1,113 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.h + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ +#ifndef __HC32F460_CRC_H__ +#define __HC32F460_CRC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CrcGroup Cyclic Redundancy Check(CRC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Bits definitions of CRC control register(CRC_CR). */ +/* + * Definitions of CRC protocol. + * NOTE: CRC16 polynomial is X16 + X12 + X5 + 1 + * CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \ + * X8 + X7 + X5 + X4 + X2 + X + 1 + */ +#define CRC_SEL_16B ((uint32_t)0x0) +#define CRC_SEL_32B ((uint32_t)(0x1ul << 1u)) + +/* + * Identifies the transpose configuration of the source data. + * If this function is enabled, the source data's bits in bytes are transposed. + * e.g. There's a source data 0x1234 which will be calculated checksum and this + * function is enabled, the final data be calculated is 0x482C. + * 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48. + * 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C. + * The same to 32 bit data while using CRC32. + */ +#define CRC_REFIN_DISABLE ((uint32_t)0x0) +#define CRC_REFIN_ENABLE ((uint32_t)(0x1ul << 2u)) + +/* + * Identifies the transpose configuration of the checksum. + * If this function is enabled, bits of the checksum will be transposed. + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then + * this function is enabled, the checksum will be 0x1E6A. + * 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_REFOUT_DISABLE ((uint32_t)0x0) +#define CRC_REFOUT_ENABLE ((uint32_t)(0x1ul << 3u)) + +/* + * XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32). + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled. + * If this function enabled, the checksum will be 0xA987. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_XOROUT_DISABLE ((uint32_t)0x0) +#define CRC_XOROUT_ENABLE ((uint32_t)(0x1ul << 4u)) + +#define CRC_CONFIG_MASK ((uint32_t)(0x1Eu)) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CRC_Init(uint32_t u32Config); +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length); +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length); +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length); +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length); + +//@} // CrcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_dcu.h b/lib/hc32f460/driver/inc/hc32f460_dcu.h new file mode 100644 index 000000000000..f4dcc3d4ddbf --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_dcu.h @@ -0,0 +1,211 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.h + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ +#ifndef __HC32F460_DCU_H__ +#define __HC32F460_DCU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DcuGroup Data Computing Unit(DCU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief DCU register data enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_register +{ + DcuRegisterData0 = 0u, ///< DCU DATA0 + DcuRegisterData1 = 1u, ///< DCU DATA1 + DcuRegisterData2 = 2u, ///< DCU DATA2 +} en_dcu_data_register_t; + +/** + ******************************************************************************* + ** \brief DCU operation enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_operation_mode +{ + DcuInvalid = 0u, ///< DCU Invalid + DcuOpAdd = 1u, ///< DCU operation: Add + DcuOpSub = 2u, ///< DCU operation: Sub + DcuHwTrigOpAdd = 3u, ///< DCU operation: Hardware trigger Add + DcuHwTrigOpSub = 4u, ///< DCU operation: Hardware trigger Sub + DcuOpCompare = 5u, ///< DCU operation: Compare +} en_dcu_operation_mode_t; + +/** + ******************************************************************************* + ** \brief DCU data size enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_size +{ + DcuDataBit8 = 0u, ///< DCU data size: 8 bit + DcuDataBit16 = 1u, ///< DCU data size: 16 bit + DcuDataBit32 = 2u, ///< DCU data size: 32 bit +} en_dcu_data_size_t; + +/** + ******************************************************************************* + ** \brief DCU compare operation trigger mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_cmp_trigger_mode +{ + DcuCmpTrigbyData0 = 0u, ///< DCU compare triggered by DATA0 + DcuCmpTrigbyData012 = 1u, ///< DCU compare triggered by DATA0 or DATA1 or DATA2 +} en_dcu_cmp_trigger_mode_t; + +/** + ******************************************************************************* + ** \brief DCU interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_sel +{ + DcuIntOp = (1ul << 0), ///< DCU overflow or underflow interrupt + DcuIntLs2 = (1ul << 1), ///< DCU DATA0 < DATA2 interrupt + DcuIntEq2 = (1ul << 2), ///< DCU DATA0 = DATA2 interrupt + DcuIntGt2 = (1ul << 3), ///< DCU DATA0 > DATA2 interrupt + DcuIntLs1 = (1ul << 4), ///< DCU DATA0 < DATA1 interrupt + DcuIntEq1 = (1ul << 5), ///< DCU DATA0 = DATA1 interrupt + DcuIntGt1 = (1ul << 6), ///< DCU DATA0 > DATA1 interrupt +} en_dcu_int_sel_t, en_dcu_flag_t; + +/** + ******************************************************************************* + ** \brief DCU window interrupt mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_win_mode +{ + DcuIntInvalid = 0u, ///< DCU don't occur interrupt + DcuWinIntInvalid = 1u, ///< DCU window interrupt is invalid. + DcuInsideWinCmpInt = 2u, ///< DCU occur interrupt when DATA2 �� DATA0 �� DATA2 + DcuOutsideWinCmpInt = 3u, ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 +} en_dcu_int_win_mode_t; + +/* DCU common trigger source select */ +typedef enum en_dcu_com_trigger +{ + DcuComTrigger_1 = 1u, ///< Select common trigger 1. + DcuComTrigger_2 = 2u, ///< Select common trigger 2. + DcuComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_dcu_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DCU initialization configuration + ** + ******************************************************************************/ +typedef struct stc_dcu_init +{ + uint32_t u32IntSel; ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t + + en_functional_state_t enIntCmd; ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function + + en_dcu_int_win_mode_t enIntWinMode; ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t + + en_dcu_data_size_t enDataSize; ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t + + en_dcu_operation_mode_t enOperation; ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t + + en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t + +} stc_dcu_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg); +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode); +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize); +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode); +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode); +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx); +en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx); +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd); +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, uint8_t u8Data); +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data); +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data); +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc); +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState); + +//@} // DcuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_dmac.h b/lib/hc32f460/driver/inc/hc32f460_dmac.h new file mode 100644 index 000000000000..9c7d7332fe57 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_dmac.h @@ -0,0 +1,383 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.h + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ +#ifndef __HC32F460_DMAC_H__ +#define __HC32F460_DMAC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief DMA Channel + ** + ******************************************************************************/ +typedef enum en_dma_channel +{ + DmaCh0 = 0u, ///< DMA channel 0 + DmaCh1 = 1u, ///< DMA channel 1 + DmaCh2 = 2u, ///< DMA channel 2 + DmaCh3 = 3u, ///< DMA channel 3 + DmaChMax = 4u ///< DMA channel max +}en_dma_channel_t; + +/** + ******************************************************************************* + ** \brief DMA transfer data width + ** + ******************************************************************************/ +typedef enum en_dma_transfer_width +{ + Dma8Bit = 0u, ///< 8 bit transfer via DMA + Dma16Bit = 1u, ///< 16 bit transfer via DMA + Dma32Bit = 2u ///< 32 bit transfer via DMA +}en_dma_transfer_width_t; + +/** + ******************************************************************************* + ** \brief DMA flag + ** + ******************************************************************************/ +typedef enum en_dma_flag +{ + DmaTransferComplete = 0u, ///< DMA transfer complete + DmaBlockComplete = 1u, ///< DMA block transfer complete + DmaTransferErr = 2u, ///< DMA transfer error + DmaReqErr = 3u, ///< DMA transfer request error + DmaFlagMax = 4u +}en_dma_flag_t; + +/** + ******************************************************************************* + ** \brief DMA address mode + ** + ******************************************************************************/ +typedef enum en_dma_address_mode +{ + AddressFix = 0u, ///< Address fixed + AddressIncrease = 1u, ///< Address increased + AddressDecrease = 2u, ///< Address decreased +}en_dma_address_mode_t; + +/** + ******************************************************************************* + ** \brief DMA link list pointer mode + ** + ******************************************************************************/ +typedef enum en_dma_llp_mode +{ + LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request + LlpRunNow = 1u, ///< DMA trigger transfer now +}en_dma_llp_mode_t; + +/** + ******************************************************************************* + ** \brief DMA interrupt selection + ** + ******************************************************************************/ +typedef enum en_dma_irq_sel +{ + TrnErrIrq = 0u, ///< Select DMA transfer error interrupt + TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt + TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt + BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt + DmaIrqSelMax = 4u +}en_dma_irq_sel_t; + +/** + ******************************************************************************* + ** \brief DMA re_config count mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_cnt_mode +{ + CntFix = 0u, ///< Fix + CntSrcAddr = 1u, ///< Source address mode + CntDesAddr = 2u, ///< Destination address mode +}en_dma_recfg_cnt_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config destination address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_daddr_mode +{ + DaddrFix = 0u, ///< Fix + DaddrNseq = 1u, ///< No_sequence address + DaddrRep = 2u, ///< Repeat address +}en_dma_recfg_daddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config source address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_saddr_mode +{ + SaddrFix = 0u, ///< Fix + SaddrNseq = 1u, ///< No_sequence address + SaddrRep = 2u, ///< Repeat address +}en_dma_recfg_saddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA channel status + ** + ******************************************************************************/ +typedef enum en_dma_ch_flag +{ + DmaSta = 0u, ///< DMA status. + ReCfgSta = 1u, ///< DMA re_configuration status. + DmaCh0Sta = 2u, ///< DMA channel 0 status. + DmaCh1Sta = 3u, ///< DMA channel 1 status. + DmaCh2Sta = 4u, ///< DMA channel 2 status. + DmaCh3Sta = 5u, ///< DMA channel 3 status. +}en_dma_ch_flag_t; + +/** + ******************************************************************************* + ** \brief DMA request status + ** + ******************************************************************************/ +typedef enum en_dma_req_status +{ + ReCfgReqSta = 0u, ///< DMA re_configuration request. + DmaCh0ReqSta = 1u, ///< DMA channel 0 transfer request status. + DmaCh1ReqSta = 2u, ///< DMA channel 1 transfer request status. + DmaCh2ReqSta = 3u, ///< DMA channel 2 transfer request status. + DmaCh3ReqSta = 4u, ///< DMA channel 3 transfer request status. +}en_dma_req_status_t; + +/** + ******************************************************************************* + ** \brief DMA common trigger source select + ** + ******************************************************************************/ +typedef enum en_dma_com_trigger +{ + DmaComTrigger_1 = 0x1, ///< Select common trigger 1. + DmaComTrigger_2 = 0x2, ///< Select common trigger 2. + DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_dma_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DMA llp descriptor + ** + ******************************************************************************/ +typedef struct stc_dma_llp_descriptor +{ + uint32_t SARx; ///< DMA source address register + uint32_t DARx; ///< DMA destination address register + union + { + uint32_t DTCTLx; + stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register + }; + union + { + uint32_t RPTx; + stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register + }; + union + { + uint32_t SNSEQCTLx; + stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register + }; + union + { + __IO uint32_t DNSEQCTLx; + stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register + }; + union + { + uint32_t LLPx; + stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register + }; + union + { + uint32_t CHxCTL; + stc_dma_chctl_field_t CHxCTL_f; ///< DMA channel control register + }; +}stc_dma_llp_descriptor_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseq_cfg +{ + uint32_t u32Offset; ///< DMA no-sequence offset. + uint16_t u16Cnt; ///< DMA no-sequence count. +}stc_dma_nseq_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseqb_cfg +{ + uint32_t u32NseqDist; ///< DMA no-sequence district interval. + uint16_t u16CntB; ///< DMA no-sequence count. +}stc_dma_nseqb_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA re_config configuration + ** + ******************************************************************************/ +typedef struct stc_dma_recfg_ctl +{ + uint16_t u16SrcRptBSize; ///< The source repeat size. + uint16_t u16DesRptBSize; ///< The destination repeat size. + en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode. + en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode. + en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode. + stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config. + stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config. +}stc_dma_recfg_ctl_t; + +/** + ******************************************************************************* + ** \brief DMA channel configuration + ** + ******************************************************************************/ +typedef struct stc_dma_ch_cfg +{ + en_dma_address_mode_t enSrcInc; ///< DMA source address update mode. + en_dma_address_mode_t enDesInc; ///< DMA destination address update mode. + en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not. + en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not. + en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not. + en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not. + en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width. + en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not. + en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode. + en_functional_state_t enIntEn; ///< Enable interrupt function or not. +}stc_dma_ch_cfg_t; + + +/** + ******************************************************************************* + ** \brief DMA configuration + ** + ******************************************************************************/ +typedef struct stc_dma_config +{ + uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set. + uint16_t u16TransferCnt; ///< Transfer counter. + uint32_t u32SrcAddr; ///< The source address. + uint32_t u32DesAddr; ///< The destination address. + uint16_t u16SrcRptSize; ///< The source repeat size. + uint16_t u16DesRptSize; ///< The destination repeat size. + uint32_t u32DmaLlp; ///< The Dma linked list pointer address + stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration. + stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration. + stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration. +}stc_dma_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState); +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState); +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg); +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState); +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag); +en_flag_status_t DMA_GetReqStatus(M4_DMA_TypeDef* pstcDmaReg, en_dma_req_status_t enDmaReqStatus); + +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize); +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt); +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg); +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg); +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg); +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg); +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer); + +uint32_t DMA_GetSrcAddr(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetDesAddr(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetTransferCnt(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetBlockSize(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetSrcRptSize(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetDesRptSize(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetSrcNSeqCount(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetDesNSeqCount(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetSrcNSeqOffset(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); +uint32_t DMA_GetDesNSeqOffset(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); + +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc); +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc); +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); + +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg); +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg); +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); + + + +//@} // DmacGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_DMAC_H__*/ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_efm.h b/lib/hc32f460/driver/inc/hc32f460_efm.h new file mode 100644 index 000000000000..9da454e1e8f6 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_efm.h @@ -0,0 +1,204 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.h + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ +#ifndef __HC32F460_EFM_H__ +#define __HC32F460_EFM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EfmGroup Embedded Flash Management unit(EFM) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The flash status. + ** + ******************************************************************************/ +typedef enum en_efm_flash_status +{ + FlashReady = 1u, ///< The flash ready flag. + FlashRWErr = 2u, ///< The flash read/write error flag. + FlashEOP = 3u, ///< The flash end of operation flag. + FlashPgMissMatch = 4u, ///< The flash program miss match flag. + FlashPgSizeErr = 5u, ///< The flash program size error flag. + FlashPgareaPErr = 6u, ///< The flash program protect area error flag. + FlashWRPErr = 7u, ///< The flash write protect error flag. +}en_efm_flash_status_t; + +/** + ******************************************************************************* + ** \brief The flash read mode. + ** + ******************************************************************************/ +typedef enum en_efm_read_md +{ + NormalRead = 0u, ///< The flash normal read mode. + UltraPowerRead = 1u, ///< The flash ultra power read mode. +}en_efm_read_md_t; + +/** + ******************************************************************************* + ** \brief The flash interrupt select. + ** + ******************************************************************************/ +typedef enum en_efm_int_sel +{ + PgmErsErrInt = 0u, ///< The flash program / erase error interrupt. + EndPgmInt = 1u, ///< The flash end of program interrupt. + ColErrInt = 2u, ///< The flash read collided error interrupt. +}en_efm_int_sel_t; + +/** + ******************************************************************************* + ** \brief The bus state while flash program & erase. + ** + ******************************************************************************/ +typedef enum en_efm_bus_sta +{ + BusBusy = 0u, ///< The bus busy while flash program & erase. + BusRelease = 1u, ///< The bus release while flash program & erase. +}en_efm_bus_sta_t; + +/** + ******************************************************************************* + ** \brief Structure of windows protect address. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_win_protect_addr +{ + uint32_t StartAddr; ///< The protect start address. + uint32_t EndAddr; ///< The protect end address. +}stc_efm_win_protect_addr_t; + +/** + ******************************************************************************* + ** \brief Structure of unique ID. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_unique_id +{ + uint32_t uniqueID1; ///< unique ID 1. + uint32_t uniqueID2; ///< unique ID 2. + uint32_t uniqueID3; ///< unique ID 3. +}stc_efm_unique_id_t; +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* Flach latency cycle (0~15) */ +#define EFM_LATENCY_0 (0ul) +#define EFM_LATENCY_1 (1ul) +#define EFM_LATENCY_2 (2ul) +#define EFM_LATENCY_3 (3ul) +#define EFM_LATENCY_4 (4ul) +#define EFM_LATENCY_5 (5ul) +#define EFM_LATENCY_6 (6ul) +#define EFM_LATENCY_7 (7ul) +#define EFM_LATENCY_8 (8ul) +#define EFM_LATENCY_9 (9ul) +#define EFM_LATENCY_10 (10ul) +#define EFM_LATENCY_11 (11ul) +#define EFM_LATENCY_12 (12ul) +#define EFM_LATENCY_13 (13ul) +#define EFM_LATENCY_14 (14ul) +#define EFM_LATENCY_15 (15ul) + +/* Flash flag */ +#define EFM_FLAG_WRPERR (0x00000001ul) +#define EFM_FLAG_PEPRTERR (0x00000002ul) +#define EFM_FLAG_PGSZERR (0x00000004ul) +#define EFM_FLAG_PGMISMTCH (0x00000008ul) +#define EFM_FLAG_EOP (0x00000010ul) +#define EFM_FLAG_COLERR (0x00000020ul) +#define EFM_FLAG_RDY (0x00000100ul) + +/* Flash operate mode */ +#define EFM_MODE_READONLY (0ul) +#define EFM_MODE_SINGLEPROGRAM (1ul) +#define EFM_MODE_SINGLEPROGRAMRB (2ul) +#define EFM_MODE_SEQUENCEPROGRAM (3ul) +#define EFM_MODE_SECTORERASE (4ul) +#define EFM_MODE_CHIPERASE (5ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void EFM_Unlock(void); +void EFM_Lock(void); + +void EFM_FlashCmd(en_functional_state_t enNewState); +void EFM_SetLatency(uint32_t u32Latency); +void EFM_InstructionCacheCmd(en_functional_state_t enNewState); +void EFM_DataCacheRstCmd(en_functional_state_t enNewState); +void EFM_SetReadMode(en_efm_read_md_t enReadMD); +void EFM_ErasePgmCmd(en_functional_state_t enNewState); +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode); +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState); + +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag); +en_flag_status_t EFM_GetSwitchStatus(void); +void EFM_ClearFlag(uint32_t u32flag); +en_efm_flash_status_t EFM_GetStatus(void); +void EFM_SetBusState(en_efm_bus_sta_t enState); + +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr); + +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf); +en_result_t EFM_SectorErase(uint32_t u32Addr); +en_result_t EFM_MassErase(uint32_t u32Addr); + +en_result_t EFM_OtpLock(uint32_t u32Addr); +stc_efm_unique_id_t EFM_ReadUID(void); + + +//@} // EfmGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/lib/hc32f460/driver/inc/hc32f460_emb.h b/lib/hc32f460/driver/inc/hc32f460_emb.h new file mode 100644 index 000000000000..773377b206b9 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_emb.h @@ -0,0 +1,200 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.h + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ +#ifndef __HC32F460_EMB_H__ +#define __HC32F460_EMB_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup EMBGroup Emergency Brake(EMB) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief EMB status enumeration + ******************************************************************************/ +typedef enum en_emb_status +{ + EMBFlagPortIn = 0u, ///< EMB port in brake flag + EMBFlagPWMSame = 1u, ///< EMB PWM same brake flag + EMBFlagCmp = 2u, ///< EMB CMP brake flag + EMBFlagOSCFail = 3u, ///< EMB oscillator fail brake flag + EMBPortInState = 4u, ///< EMB port in state + EMBPWMState = 5u, ///< EMB PWM same state +} en_emb_status_t; + +/** + ******************************************************************************* + ** \brief EMB status clear(recover) enumeration + ******************************************************************************/ +typedef enum en_emb_status_clr +{ + EMBPortInFlagClr = 0u, ///< EMB port in brake flag clear + EMBPWMSameFlagCLr = 1u, ///< EMB PWM same brake flag clear + EMBCmpFlagClr = 2u, ///< EMB CMP brake flag clear + EMBOSCFailFlagCLr = 3u, ///< EMB oscillator fail brake flag clear +} en_emb_status_clr_t; + +/** + ******************************************************************************* + ** \brief EMB irq enumeration + ******************************************************************************/ +typedef enum en_emb_irq_type +{ + PORTBrkIrq = 0u, ///< EMB port brake interrupt + PWMSmBrkIrq = 1u, ///< EMB PWM same brake interrupt + CMPBrkIrq = 2u, ///< EMB CMP brake interrupt + OSCFailBrkIrq = 3u, ///< EMB oscillator fail brake interrupt +} en_emb_irq_type_t; + +/** + ******************************************************************************* + ** \brief EMB port in filter enumeration + ******************************************************************************/ +typedef enum en_emb_port_filter +{ + EMBPortFltDiv0 = 0u, ///< EMB port in filter with PCLK clock + EMBPortFltDiv8 = 1u, ///< EMB port in filter with PCLK/8 clock + EMBPortFltDiv32 = 2u, ///< EMB port in filter with PCLK/32 clock + EMBPortFltDiv128 = 3u, ///< EMB port in filter with PCLK/128 clock +} en_emb_port_filter_t; + +/** + ******************************************************************************* + ** \brief EMB CR0 for timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer6 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OSC fail brake + bool bEnTimer61PWMSBrake; ///< Enable tiemr61 PWM same brake + bool bEnTimer62PWMSBrake; ///< Enable tiemr62 PWM same brake + bool bEnTimer63PWMSBrake; ///< Enable tiemr63 PWM same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB CR1~3 for timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer4 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OS fail brake + bool bEnTimer4xWHLSammeBrake; ///< Enable tiemr4x PWM WH WL same brake + bool bEnTimer4xVHLSammeBrake; ///< Enable tiemr4x PWM VH VL same brake + bool bEnTimer4xUHLSammeBrake; ///< Enable tiemr4x PWM UH UL same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer4_t; + + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer6 +{ + bool bEnTimer61HighLevelDect; ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer62HighLevelDect; ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer63HighLevelDect; ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer4 +{ + bool bEnUHLPhaseHighLevelDect; ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel + bool bEnVHLPhaseHighLevelDect; ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel + bool bEnWHLphaseHighLevelDect; ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer4_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn); +/* Get status(flag) */ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus); +/* Status(flag) clear (recover) */ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr); +/* Control Register(CTL) config for timer6 */ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR); +/* Control Register(CTL) config for timer4 */ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR); +/* PWM level detect (short detection) selection config for timer6 */ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv); +/* PWM level detect (short detection) selection config for timer4 */ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv); +/* Software brake */ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn); + +//@} // EMBGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_event_port.h b/lib/hc32f460/driver/inc/hc32f460_event_port.h new file mode 100644 index 000000000000..4bfadb0617b2 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_event_port.h @@ -0,0 +1,171 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.h + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EVENT_PORT_H__ +#define __HC32F460_EVENT_PORT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EventPortGroup Event Port (EventPort) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port Index enumeration + ** + ******************************************************************************/ +typedef enum en_event_port +{ + EventPort1 = 0, ///< Event port 1 + EventPort2 = 1, ///< Event port 2 + EventPort3 = 2, ///< Event port 3 + EventPort4 = 3, ///< Event port 4 +}en_event_port_t; + +/** + ******************************************************************************* + ** \brief Event Port Pin enumeration + ** + ******************************************************************************/ +typedef enum en_event_pin +{ + EventPin00 = 1u << 0, ///< Event port Pin 00 + EventPin01 = 1u << 1, ///< Event port Pin 01 + EventPin02 = 1u << 2, ///< Event port Pin 02 + EventPin03 = 1u << 3, ///< Event port Pin 03 + EventPin04 = 1u << 4, ///< Event port Pin 04 + EventPin05 = 1u << 5, ///< Event port Pin 05 + EventPin06 = 1u << 6, ///< Event port Pin 06 + EventPin07 = 1u << 7, ///< Event port Pin 07 + EventPin08 = 1u << 8, ///< Event port Pin 08 + EventPin09 = 1u << 9, ///< Event port Pin 09 + EventPin10 = 1u << 10, ///< Event port Pin 10 + EventPin11 = 1u << 11, ///< Event port Pin 11 + EventPin12 = 1u << 12, ///< Event port Pin 12 + EventPin13 = 1u << 13, ///< Event port Pin 13 + EventPin14 = 1u << 14, ///< Event port Pin 14 + EventPin15 = 1u << 15, ///< Event port Pin 15 + EventPinAll= 0xFFFF, ///< All event pins are selected +}en_event_pin_t; + +/** + ******************************************************************************* + ** \brief Event Port common trigger source select + ** + ******************************************************************************/ +typedef enum en_event_port_com_trigger +{ + EpComTrigger_1 = 0x1, ///< Select common trigger 1. + EpComTrigger_2 = 0x2, ///< Select common trigger 2. + EpComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_event_port_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Event Port direction enumeration + ** + ******************************************************************************/ +typedef enum en_event_port_dir +{ + EventPortIn = 0, ///< Event Port direction 'IN' + EventPortOut = 1, ///< Event Port direction 'OUT' +}en_event_port_dir_t; + +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for Event port detect + ** + ** \note + ******************************************************************************/ +typedef enum en_ep_flt_clk +{ + Pclk1Div1 = 0u, ///< PCLK1 as EP filter clock source + Pclk1Div8 = 1u, ///< PCLK1 div8 as EP filter clock source + Pclk1Div32 = 2u, ///< PCLK1 div32 as EP filter clock source + Pclk1Div64 = 3u, ///< PCLK1 div64 as EP filter clock source +}en_ep_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Event port init structure definition + ******************************************************************************/ +typedef struct stc_event_port_init +{ + en_event_port_dir_t enDirection; ///< Input/Output setting + en_functional_state_t enReset; ///< Corresponding pin reset after triggered + en_functional_state_t enSet; ///< Corresponding pin set after triggered + en_functional_state_t enRisingDetect; ///< Rising edge detect enable + en_functional_state_t enFallingDetect;///< Falling edge detect enable + en_functional_state_t enFilter; ///< Filter clock source select + en_ep_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_ep_flt_clk_t for details +}stc_event_port_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort, \ + uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit); +extern en_result_t EVENTPORT_DeInit(void); +extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc); +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState); +extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort); +extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, \ + en_event_pin_t enEventPin); +extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); +extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); + +//@} // EventPortGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_exint_nmi_swi.h b/lib/hc32f460/driver/inc/hc32f460_exint_nmi_swi.h new file mode 100644 index 000000000000..c8fda4494c5e --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_exint_nmi_swi.h @@ -0,0 +1,252 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.h + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EXINT_NMI_SWI_H__ +#define __HC32F460_EXINT_NMI_SWI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup ExintNmiSwiGroup External Interrupts (External Interrupt), \ + ** NMI (Non-Maskable Interrupt), SWI (Software Interrupt) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for EXINT and NMI + ** + ** \note + ******************************************************************************/ +typedef enum en_ei_flt_clk +{ + Pclk3Div1 = 0u, ///< PCLK3 as EP filter clock source + Pclk3Div8 = 1u, ///< PCLK3 div8 as EP filter clock source + Pclk3Div32 = 2u, ///< PCLK3 div32 as EP filter clock source + Pclk3Div64 = 3u, ///< PCLK3 div64 as EP filter clock source +}en_ei_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_lvl +{ + NmiFallingEdge = 0u, ///< Falling edge detection + NmiRisingEdge = 1u, ///< Rising edge detection +}en_nmi_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to EXTI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_exti_lvl +{ + ExIntFallingEdge = 0u, ///< Falling edge detection + ExIntRisingEdge = 1u, ///< Rising edge detection + ExIntBothEdge = 2u, ///< Falling or Rising edge detection + ExIntLowLevel = 3u, ///< "L" level detection +}en_exti_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define an index for EXINT + ******************************************************************************/ +typedef enum en_exti_ch +{ + ExtiCh00 = 0u, + ExtiCh01 = 1u, + ExtiCh02 = 2u, + ExtiCh03 = 3u, + ExtiCh04 = 4u, + ExtiCh05 = 5u, + ExtiCh06 = 6u, + ExtiCh07 = 7u, + ExtiCh08 = 8u, + ExtiCh09 = 9u, + ExtiCh10 = 10u, + ExtiCh11 = 11u, + ExtiCh12 = 12u, + ExtiCh13 = 13u, + ExtiCh14 = 14u, + ExtiCh15 = 15u, +}en_exti_ch_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define the SWI channel + ******************************************************************************/ +typedef enum en_swi_ch +{ + SwiCh00 = 1u << 0, + SwiCh01 = 1u << 1, + SwiCh02 = 1u << 2, + SwiCh03 = 1u << 3, + SwiCh04 = 1u << 4, + SwiCh05 = 1u << 5, + SwiCh06 = 1u << 6, + SwiCh07 = 1u << 7, + SwiCh08 = 1u << 8, + SwiCh09 = 1u << 9, + SwiCh10 = 1u << 10, + SwiCh11 = 1u << 11, + SwiCh12 = 1u << 12, + SwiCh13 = 1u << 13, + SwiCh14 = 1u << 14, + SwiCh15 = 1u << 15, + SwiCh16 = 1u << 16, + SwiCh17 = 1u << 17, + SwiCh18 = 1u << 18, + SwiCh19 = 1u << 19, + SwiCh20 = 1u << 20, + SwiCh21 = 1u << 21, + SwiCh22 = 1u << 22, + SwiCh23 = 1u << 23, + SwiCh24 = 1u << 24, + SwiCh25 = 1u << 25, + SwiCh26 = 1u << 26, + SwiCh27 = 1u << 27, + SwiCh28 = 1u << 28, + SwiCh29 = 1u << 29, + SwiCh30 = 1u << 30, + SwiCh31 = 1u << 31, +}en_swi_ch_t; + +/** + ******************************************************************************* + ** \brief External Interrupt configuration + ** + ** \note The EXINT configuration + ******************************************************************************/ +typedef struct stc_exint_config +{ + en_exti_ch_t enExitCh; ///< External Int CH.0~15 ref@ en_exti_ch_t + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFltClk; ///< Filter clock, ref@ en_ei_flt_clk_t for details + en_exti_lvl_t enExtiLvl; ///< Detection level, ref@ en_exti_lvl_t for details +}stc_exint_config_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI Trigger source + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_src +{ + NmiSrcNmi = 1u << 0, ///< NMI pin + NmiSrcSwdt = 1u << 1, ///< Special watch dog timer + NmiSrcVdu1 = 1u << 2, ///< Voltage detect 1 + NmiSrcVdu2 = 1u << 3, ///< Voltage detect 2 + NmiSrcXtalStop = 1u << 5, ///< Xtal stop + NmiSrcSramPE = 1u << 8, ///< SRAM1/2/HS/Ret parity error + NmiSrcSramDE = 1u << 9, ///< SRAM3 ECC error + NmiSrcMpu = 1u << 10, ///< MPU error + NmiSrcWdt = 1u << 11, ///< Watch dog timer +}en_nmi_src_t; + +/** + ******************************************************************************* + ** \brief Enumeration to software interrupt or event + ** + ** \note + ******************************************************************************/ +typedef enum en_swi_type +{ + SwEvent = 0u, ///< software event + SwInt = 1u, ///< software interrupt +}en_swi_type_t; + + +/** + ******************************************************************************* + ** \brief NMI configuration + ** + ** \note The NMI configuration + ******************************************************************************/ +typedef struct stc_nmi_config +{ + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_flt_clk_t for details + en_nmi_lvl_t enNmiLvl; ///< Detection level, ref@ en_nmi_lvl_t for details + uint16_t u16NmiSrc; ///< NMI trigger source, ref@ en_nmi_src_t for details + func_ptr_t pfnNmiCallback; ///< Callback pointers +}stc_nmi_config_t; + +/** + ******************************************************************************* + ** \brief SWI configuration + ** + ** \note The SWI configuration + ******************************************************************************/ +typedef struct stc_swi_config +{ + en_swi_ch_t enSwiCh; ///< SWI channel + en_swi_type_t enSwiType; ///< Select software interrupt or event + func_ptr_t pfnSwiCallback; ///< Callback pointers +}stc_swi_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig); +extern en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint); +extern en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint); +extern en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig); +extern en_result_t NMI_DeInit(void); +extern en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc); +extern en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc); +extern en_result_t SWI_Enable(uint32_t u32SwiCh); +extern en_result_t SWI_Disable(uint32_t u32SwiCh); + +//@} // ExintNmiSwiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_EXINT_NMI_SWI_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_gpio.h b/lib/hc32f460/driver/inc/hc32f460_gpio.h new file mode 100644 index 000000000000..076b904adc16 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_gpio.h @@ -0,0 +1,290 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.h + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +#ifndef __HC32F460_GPIO_H__ +#define __HC32F460_GPIO_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup GpioGroup General Purpose Input/Output(GPIO) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief GPIO Configuration Mode enumeration + ** + ******************************************************************************/ +typedef enum en_pin_mode +{ + Pin_Mode_In = 0, ///< GPIO Input mode + Pin_Mode_Out = 1, ///< GPIO Output mode + Pin_Mode_Ana = 2, ///< GPIO Analog mode +}en_pin_mode_t; + +/** + ******************************************************************************* + ** \brief GPIO Drive Capacity enumeration + ** + ******************************************************************************/ +typedef enum en_pin_drv +{ + Pin_Drv_L = 0, ///< Low Drive Capacity + Pin_Drv_M = 1, ///< Middle Drive Capacity + Pin_Drv_H = 2, ///< High Drive Capacity +}en_pin_drv_t; + +/** + ******************************************************************************* + ** \brief GPIO Output Type enumeration + ******************************************************************************/ +typedef enum en_pin_o_type +{ + Pin_OType_Cmos = 0, ///< CMOS + Pin_OType_Od = 1, ///< Open Drain +}en_pin_o_type_t; + + +typedef enum en_debug_port +{ + TCK_SWCLK = 1 << 0, ///< TCK or SWCLK + TMS_SWDIO = 1 << 1, ///< TMS or SWDIO + TDO_SWO = 1 << 2, ///< TOD or SWD + TDI = 1 << 3, ///< TDI + TRST = 1 << 4, ///< TRest + ALL_DBG_PIN = 0x1Fu ///< All above +}en_debug_port_t; +/** + ******************************************************************************* + ** \brief GPIO Port Index enumeration + ****************************************************************PORTC**************/ +typedef enum en_port +{ + PortA = 0, ///< port group A + PortB = 1, ///< port group B + PortC = 2, ///< port group C + PortD = 3, ///< port group D + PortE = 4, ///< port group E + PortH = 5, ///< port group H +}en_port_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin Index enumeration + ******************************************************************************/ +typedef enum en_pin +{ + Pin00 = (1 << 0), ///< Pin index 00 of each port group + Pin01 = (1 << 1), ///< Pin index 01 of each port group + Pin02 = (1 << 2), ///< Pin index 02 of each port group + Pin03 = (1 << 3), ///< Pin index 03 of each port group + Pin04 = (1 << 4), ///< Pin index 04 of each port group + Pin05 = (1 << 5), ///< Pin index 05 of each port group + Pin06 = (1 << 6), ///< Pin index 06 of each port group + Pin07 = (1 << 7), ///< Pin index 07 of each port group + Pin08 = (1 << 8), ///< Pin index 08 of each port group + Pin09 = (1 << 9), ///< Pin index 09 of each port group + Pin10 = (1 << 10), ///< Pin index 10 of each port group + Pin11 = (1 << 11), ///< Pin index 11 of each port group + Pin12 = (1 << 12), ///< Pin index 12 of each port group + Pin13 = (1 << 13), ///< Pin index 13 of each port group + Pin14 = (1 << 14), ///< Pin index 14 of each port group + Pin15 = (1 << 15), ///< Pin index 15 of each port group + PinAll= 0xFFFF, ///< All pins selected +}en_pin_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin read wait cycle enumeration + ******************************************************************************/ +typedef enum en_read_wait +{ + WaitCycle0 = 0, ///< no wait cycle, operation freq. lower than 42MHz + WaitCycle1 = 1, ///< one wait cycle, operation freq. @[42~84)MHz + WaitCycle2 = 2, ///< two wait cycles, operation freq. @[84~126)MHz + WaitCycle3 = 3, ///< three wait cycles, operation freq. @[126~200)MHz +}en_read_wait_t; + +/** + ******************************************************************************* + ** \brief GPIO Function enumeration + ******************************************************************************/ +typedef enum en_port_func +{ + Func_Gpio = 0u, ///< function set to gpio + Func_Fcmref = 1u, ///< function set to fcm reference + Func_Rtcout = 1u, ///< function set to rtc output + Func_Vcout = 1u, ///< function set to vc output + Func_Adtrg = 1u, ///< function set to adc trigger + Func_Mclkout = 1u, ///< function set to mclk output + Func_Tim4 = 2u, ///< function set to timer4 + Func_Tim6 = 3u, ///< function set to timer6 + Func_Tima0 = 4u, ///< function set to timerA + Func_Tima1 = 5u, ///< function set to timerA + Func_Tima2 = 6u, ///< function set to timerA + Func_Emb = 6u, ///< function set to emb + Func_Usart_Ck = 7u, ///< function set to usart clk + Func_Spi_Nss = 7u, ///< function set to spi nss + Func_Qspi = 7u, ///< function set to qspi + Func_Key = 8u, ///< function set to key + Func_Sdio = 9u, ///< function set to sdio + Func_I2s = 10u, ///< function set to i2s + Func_UsbF = 10u, ///< function set to usb full speed + Func_Evnpt = 14u, ///< function set to event port + Func_Eventout = 15u, ///< function set to event out + Func_Usart1_Tx = 32u, ///< function set to usart tx of ch.1 + Func_Usart3_Tx = 32u, ///< function set to usart tx of ch.3 + Func_Usart1_Rx = 33u, ///< function set to usart rx of ch.1 + Func_Usart3_Rx = 33u, ///< function set to usart rx of ch.3 + Func_Usart1_Rts = 34u, ///< function set to usart rts of ch.1 + Func_Usart3_Rts = 34u, ///< function set to usart rts of ch.3 + Func_Usart1_Cts = 35u, ///< function set to usart cts of ch.1 + Func_Usart3_Cts = 35u, ///< function set to usart cts of ch.3 + Func_Usart2_Tx = 36u, ///< function set to usart tx of ch.2 + Func_Usart4_Tx = 36u, ///< function set to usart tx of ch.4 + Func_Usart2_Rx = 37u, ///< function set to usart rx of ch.2 + Func_Usart4_Rx = 37u, ///< function set to usart rx of ch.4 + Func_Usart2_Rts = 38u, ///< function set to usart rts of ch.2 + Func_Usart4_Rts = 38u, ///< function set to usart rts of ch.4 + Func_Usart2_Cts = 39u, ///< function set to usart cts of ch.2 + Func_Usart4_Cts = 39u, ///< function set to usart cts of ch.4 + Func_Spi1_Mosi = 40u, ///< function set to spi mosi of ch.1 + Func_Spi3_Mosi = 40u, ///< function set to spi mosi of ch.3 + Func_Spi1_Miso = 41u, ///< function set to spi miso of ch.1 + Func_Spi3_Miso = 41u, ///< function set to spi miso of ch.3 + Func_Spi1_Nss0 = 42u, ///< function set to spi nss0 of ch.1 + Func_Spi3_Nss0 = 42u, ///< function set to spi nss0 of ch.3 + Func_Spi1_Sck = 43u, ///< function set to spi sck of ch.1 + Func_Spi3_Sck = 43u, ///< function set to spi sck of ch.3 + Func_Spi2_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi4_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi2_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi4_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi2_Nss0 = 46u, ///< function set to spi nss0 of ch.2 + Func_Spi4_Nss0 = 46u, ///< function set to spi nss0 of ch.4 + Func_Spi2_Sck = 47u, ///< function set to spi sck of ch.2 + Func_Spi4_Sck = 47u, ///< function set to spi sck of ch.4 + Func_I2c1_Sda = 48u, ///< function set to i2c sda of ch.1 + Func_I2c3_Sda = 48u, ///< function set to i2c sda of ch.3 + Func_I2c1_Scl = 49u, ///< function set to i2c scl of ch.1 + Func_I2c3_Scl = 49u, ///< function set to i2c scl of ch.3 + Func_I2c2_Sda = 50u, ///< function set to i2c sda of ch.2 + Func_Can1_Tx = 50u, ///< function set to can tx of ch.1 + Func_I2c2_Scl = 51u, ///< function set to i2c scl of ch.2 + Func_Can1_Rx = 51u, ///< function set to can rx of ch.1 + Func_I2s1_Sd = 52u, ///< function set to i2s sd of ch.1 + Func_I2s3_Sd = 52u, ///< function set to i2s sd of ch.3 + Func_I2s1_Sdin = 53u, ///< function set to i2s sdin of ch.1 + Func_I2s3_Sdin = 53u, ///< function set to i2s sdin of ch.3 + Func_I2s1_Ws = 54u, ///< function set to i2s ws of ch.1 + Func_I2s3_Ws = 54u, ///< function set to i2s ws of ch.3 + Func_I2s1_Ck = 55u, ///< function set to i2s ck of ch.1 + Func_I2s3_Ck = 55u, ///< function set to i2s ck of ch.3 + Func_I2s2_Sd = 56u, ///< function set to i2s sd of ch.2 + Func_I2s4_Sd = 56u, ///< function set to i2s sd of ch.4 + Func_I2s2_Sdin = 57u, ///< function set to i2s sdin of ch.2 + Func_I2s4_Sdin = 57u, ///< function set to i2s sdin of ch.4 + Func_I2s2_Ws = 58u, ///< function set to i2s ws of ch.2 + Func_I2s4_Ws = 58u, ///< function set to i2s ws of ch.4 + Func_I2s2_Ck = 59u, ///< function set to i2s ck of ch.2 + Func_I2s4_Ck = 59u, ///< function set to i2s ck of ch.4 +}en_port_func_t; + +/** + ******************************************************************************* + ** \brief GPIO init structure definition + ******************************************************************************/ +typedef struct stc_port_init +{ + en_pin_mode_t enPinMode; ///< Set pin mode @ref en_pin_mode_t + en_functional_state_t enLatch; ///< Pin output latch enable + en_functional_state_t enExInt; ///< External int enable + en_functional_state_t enInvert; ///< Pin input/output invert enable + en_functional_state_t enPullUp; ///< Internal pull-up resistor enable + en_pin_drv_t enPinDrv; ///< Drive capacity setting @ref en_pin_drv_t + en_pin_o_type_t enPinOType; ///< Output mode setting @ref en_pin_o_type_t + en_functional_state_t enPinSubFunc; ///< Pin sub-function enable +}stc_port_init_t; + +/** + ******************************************************************************* + ** \brief GPIO public setting structure definition + ******************************************************************************/ +typedef struct stc_port_pub_set +{ + en_port_func_t enSubFuncSel; ///< Sub-function setting @ref en_port_func_t + en_read_wait_t enReadWait; ///< Read wait cycle setting @ref en_read_wait_t +}stc_port_pub_set_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, \ + const stc_port_init_t *pstcPortInit); +extern en_result_t PORT_DeInit(void); +extern void PORT_Unlock(void); +extern void PORT_Lock(void); +extern en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc); +extern en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet); +extern uint16_t PORT_GetData(en_port_t enPort); +extern en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin); +extern en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState); +extern en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_AlwaysOn(en_port_t enPort, en_functional_state_t enNewState); +extern en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, \ + en_port_func_t enFuncSel, en_functional_state_t enSubFunc); +extern en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel); + +//@} // GpioGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_hash.h b/lib/hc32f460/driver/inc/hc32f460_hash.h new file mode 100644 index 000000000000..9828a031efdb --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_hash.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.h + ** + ** A detailed description is available at + ** @link HashGroup Hash description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of Hash. + ** + ******************************************************************************/ +#ifndef __HC32F460_HASH_H__ +#define __HC32F460_HASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup HashGroup Hash(HASH) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void HASH_Init(void); +void HASH_DeInit(void); +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout); + +//@} // HashGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_i2c.h b/lib/hc32f460/driver/inc/hc32f460_i2c.h new file mode 100644 index 000000000000..bc9d482e4f58 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_i2c.h @@ -0,0 +1,265 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.h + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2C_H__ +#define __HC32F460_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2cGroup Inter-Integrated Circuit (I2C) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2c configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_init +{ + uint32_t u32ClockDiv; ///< I2C clock division for i2c source clock + uint32_t u32Baudrate; ///< I2C baudrate config + uint32_t u32SclTime; ///< The SCL rising and falling time, count of T(i2c source clock after frequency divider) +}stc_i2c_init_t; + +/** + ******************************************************************************* + ** \brief I2c SMBUS configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_smbus_init +{ + en_functional_state_t enHostAdrMatchFunc; ///< SMBUS host address matching function + en_functional_state_t enDefaultAdrMatchFunc; ///< SMBUS default address matching function + en_functional_state_t enAlarmAdrMatchFunc; ///< SMBUS Alarm address matching function +}stc_i2c_smbus_init_t; + +/** + ******************************************************************************* + ** \brief I2c digital filter mode enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_digital_filter_mode +{ + Filter1BaseCycle = 0u, ///< I2C digital filter ability 1 base cycle + Filter2BaseCycle = 1u, ///< I2C digital filter ability 2 base cycle + Filter3BaseCycle = 2u, ///< I2C digital filter ability 3 base cycle + Filter4BaseCycle = 3u, ///< I2C digital filter ability 4 base cycle +}en_i2c_digital_filter_mode_t; + +/** + ******************************************************************************* + ** \brief I2c address bit enumeration + ** + ******************************************************************************/ +typedef enum en_address_bit +{ + Adr7bit = 0u, ///< I2C address length is 7 bits + Adr10bit = 1u, ///< I2C address length is 10 bits +}en_address_bit_t; + +/** + ******************************************************************************* + ** \brief I2c transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_trans_direction +{ + I2CDirTrans = 0u, + I2CDirReceive = 1u, +}en_trans_direction_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout switch enumeration + ** + ******************************************************************************/ +typedef enum en_clock_timeout_switch +{ + TimeoutFunOff = 0u, ///< I2C SCL pin time out function off + LowTimerOutOn = 3u, ///< I2C SCL pin high level time out function on + HighTimeOutOn = 5u, ///< I2C SCL pin low level time out function on + BothTimeOutOn = 7u, ///< I2C SCL pin both(low and high) level time out function on +}en_clock_timeout_switch_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout initialize structure + ** + ******************************************************************************/ +typedef struct stc_clock_timeout_init +{ + en_clock_timeout_switch_t enClkTimeOutSwitch; ///< I2C clock timeout function switch + uint16_t u16TimeOutHigh; ///< I2C clock timeout period for High level + uint16_t u16TimeOutLow; ///< I2C clock timeout period for Low level +}stc_clock_timeout_init_t; + +/** + ******************************************************************************* + ** \brief I2c ACK config enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_ack_config +{ + I2c_ACK = 0u, + I2c_NACK = 1u, +}en_i2c_ack_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define interrupt enable bit for I2C_CR2 register */ +#define I2C_CR2_STARTIE (0x00000001ul) +#define I2C_CR2_SLADDR0EN (0x00000002ul) +#define I2C_CR2_SLADDR1EN (0x00000004ul) +#define I2C_CR2_TENDIE (0x00000008ul) +#define I2C_CR2_STOPIE (0x00000010ul) +#define I2C_CR2_RFULLIE (0x00000040ul) +#define I2C_CR2_TEMPTYIE (0x00000080ul) +#define I2C_CR2_ARLOIE (0x00000200ul) +#define I2C_CR2_NACKIE (0x00001000ul) +#define I2C_CR2_TMOURIE (0x00004000ul) +#define I2C_CR2_GENCALLIE (0x00100000ul) +#define I2C_CR2_SMBDEFAULTIE (0x00200000ul) +#define I2C_CR2_SMBHOSTIE (0x00400000ul) +#define I2C_CR2_SMBALRTIE (0x00800000ul) + +/* define status bit for I2C_SR register */ +#define I2C_SR_STARTF (0x00000001ul) +#define I2C_SR_SLADDR0F (0x00000002ul) +#define I2C_SR_SLADDR1F (0x00000004ul) +#define I2C_SR_TENDF (0x00000008ul) +#define I2C_SR_STOPF (0x00000010ul) +#define I2C_SR_RFULLF (0x00000040ul) +#define I2C_SR_TEMPTYF (0x00000080ul) +#define I2C_SR_ARLOF (0x00000200ul) +#define I2C_SR_ACKRF (0x00000400ul) +#define I2C_SR_NACKF (0x00001000ul) +#define I2C_SR_TMOUTF (0x00004000ul) +#define I2C_SR_MSL (0x00010000ul) +#define I2C_SR_BUSY (0x00020000ul) +#define I2C_SR_TRA (0x00040000ul) +#define I2C_SR_GENCALLF (0x00100000ul) +#define I2C_SR_SMBDEFAULTF (0x00200000ul) +#define I2C_SR_SMBHOSTF (0x00400000ul) +#define I2C_SR_SMBALRTF (0x00800000ul) + +/* define status clear bit for I2C_CLR register*/ +#define I2C_CLR_STARTFCLR (0x00000001ul) +#define I2C_CLR_SLADDR0FCLR (0x00000002ul) +#define I2C_CLR_SLADDR1FCLR (0x00000004ul) +#define I2C_CLR_TENDFCLR (0x00000008ul) +#define I2C_CLR_STOPFCLR (0x00000010ul) +#define I2C_CLR_RFULLFCLR (0x00000040ul) +#define I2C_CLR_TEMPTYFCLR (0x00000080ul) +#define I2C_CLR_ARLOFCLR (0x00000200ul) +#define I2C_CLR_NACKFCLR (0x00001000ul) +#define I2C_CLR_TMOUTFCLR (0x00004000ul) +#define I2C_CLR_GENCALLFCLR (0x00100000ul) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000ul) +#define I2C_CLR_SMBHOSTFCLR (0x00400000ul) +#define I2C_CLR_SMBALRTFCLR (0x00800000ul) +#define I2C_CLR_MASK (0x00F056DFul) + +/* I2C_Clock_Division I2C clock division */ +#define I2C_CLK_DIV1 (0ul) /* I2c source clock/1 */ +#define I2C_CLK_DIV2 (1ul) /* I2c source clock/2 */ +#define I2C_CLK_DIV4 (2ul) /* I2c source clock/4 */ +#define I2C_CLK_DIV8 (3ul) /* I2c source clock/8 */ +#define I2C_CLK_DIV16 (4ul) /* I2c source clock/16 */ +#define I2C_CLK_DIV32 (5ul) /* I2c source clock/32 */ +#define I2C_CLK_DIV64 (6ul) /* I2c source clock/64 */ +#define I2C_CLK_DIV128 (7ul) /* I2c source clock/128 */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx); +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct); +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +//////////////////////////////////////////////////////////////////////////////////////// +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode); +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit); +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState); +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +/////////////////////////////////////////////////////////////////////////////////////// +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx); +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig); +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); + +/* High level functions for reference ********************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); + +//@} // I2cGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_i2s.h b/lib/hc32f460/driver/inc/hc32f460_i2s.h new file mode 100644 index 000000000000..fc277ad0a619 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_i2s.h @@ -0,0 +1,201 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.h + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2S_H__ +#define __HC32F460_I2S_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2sGroup Inter-IC Sound(I2S) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2S function + ******************************************************************************/ +typedef enum en_i2s_func +{ + TxEn = 0u, ///< Transfer enable function + TxIntEn = 1u, ///< Transfer interrupt enable function + RxEn = 2u, ///< receive enable function + RxIntEn = 3u, ///< receive interrupt enable function + ErrIntEn = 4u, ///< error interrupt enable function +}en_i2s_func_t; + + +/** + ******************************************************************************* + ** \brief I2S status flag + ******************************************************************************/ +typedef enum en_i2s_std +{ + TxBufAlarmFlag = 0u, + RxBufAlarmFlag = 1u, + TxBufEmptFlag = 2u, + TxBufFullFlag = 3u, + RxBufEmptFlag = 4u, + RxBufFullFlag = 5u, +}en_i2s_std_t; + +/** + ******************************************************************************* + ** \brief I2S clr flag + ******************************************************************************/ +typedef enum en_i2s_err_flag +{ + ClrTxErrFlag = 0u, + ClrRxErrFlag = 1u, +}en_i2s_err_flag_t; +/** + ******************************************************************************* + ** \brief I2S mode + ******************************************************************************/ +typedef enum en_i2s_mode +{ + I2sMaster = 0u, ///< I2S Master mode + I2sSlave = 1u, ///< I2S Slave mode +}en_i2s_mode_t; + +/** + ******************************************************************************* + ** \brief I2S full duplex mode + ******************************************************************************/ +typedef enum en_i2s_full_duplex_mode +{ + I2s_HalfDuplex = 0u, ///< I2S half duplex + I2s_FullDuplex = 1u, ///< I2S full duplex +}en_i2s_full_duplex_mode_t; + +/** + ******************************************************************************* + ** \brief I2S standard + ******************************************************************************/ +typedef enum en_i2s_standard +{ + Std_Philips = 0u, ///< I2S Philips standard + Std_MSBJust = 1u, ///< I2S MSB justified standart + Std_LSBJust = 2u, ///< I2S LSB justified standart + Std_PCM = 3u, ///< I2S PCM standart +}en_i2s_standard_t; + +/** + ******************************************************************************* + ** \brief I2S channel data length + ******************************************************************************/ +typedef enum en_i2s_ch_len +{ + I2s_ChLen_16Bit = 0u, + I2s_ChLen_32Bit = 1u, +}en_i2s_ch_len_t; + +/** + ******************************************************************************* + ** \brief I2S data length + ******************************************************************************/ +typedef enum en_i2s_data_len +{ + I2s_DataLen_16Bit = 0u, + I2s_DataLen_24Bit = 1u, + I2s_DataLen_32Bit = 2u, +}en_i2s_data_len_t; + +/** + ******************************************************************************* + ** \brief I2S configuration structure + ******************************************************************************/ +typedef struct stc_i2s_config +{ + en_i2s_mode_t enMode; ///< I2S mode + en_i2s_full_duplex_mode_t enFullDuplexMode; ///< I2S full duplex mode + uint32_t u32I2sInterClkFreq; ///< I2S internal clock frequency + en_i2s_standard_t enStandrad; ///< I2S standard + en_i2s_data_len_t enDataBits; ///< I2S data format, data bits + en_i2s_ch_len_t enChanelLen; ///< I2S channel length + en_functional_state_t enMcoOutEn; ///< I2S MCK output config + en_functional_state_t enExckEn; ///< I2S EXCK function config + uint32_t u32AudioFreq; ///< I2S audio frequecy +}stc_i2s_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define audio frequency */ +#define I2S_AudioFreq_192k (192000ul) +#define I2S_AudioFreq_96k (96000ul) +#define I2S_AudioFreq_48k (48000ul) +#define I2S_AudioFreq_44k (44100ul) +#define I2S_AudioFreq_32k (32000ul) +#define I2S_AudioFreq_22k (22050ul) +#define I2S_AudioFreq_16k (16000ul) +#define I2S_AudioFreq_11k (11025ul) +#define I2S_AudioFreq_8k (8000ul) +#define I2S_AudioFreq_Default (2ul) + +/* if use external clock open this define */ +#define I2S_EXTERNAL_CLOCK_VAL (12288000ul) + +/* 0,1 or 2 config for tx or tx buffer interrupt warning level */ +#define RXBUF_IRQ_WL (1ul) +#define TXBUF_IRQ_WL (1ul) + +/* 0: Short frame synchronization; 1: Long frame synchronization */ +#define PCM_SYNC_FRAME (0ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg); +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data); +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg); +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd); +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg); + +//@} // I2sGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_icg.h b/lib/hc32f460/driver/inc/hc32f460_icg.h new file mode 100644 index 000000000000..d70fcd320ce0 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_icg.h @@ -0,0 +1,395 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.h + ** + ** A detailed description is available at + ** @link IcgGroup Initialize configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ +#ifndef __HC32F460_ICG_H__ +#define __HC32F460_ICG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup IcgGroup Initialize Configure(ICG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT running state after reset + ******************************************************************************/ +#define SWDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< SWDT Auto Start after reset +#define SWDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< SWDT stop after reset + +/** + ******************************************************************************* + ** \brief SWDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define SWDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define SWDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief SWDT count underflow cycle + ******************************************************************************/ +#define SWDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief SWDT count clock division + ******************************************************************************/ +#define SWDT_COUNT_SWDTCLK_DIV1 ((uint16_t)0x0000) ///< SWDTCLK +#define SWDT_COUNT_SWDTCLK_DIV16 ((uint16_t)0x0040) ///< SWDTCLK/16 +#define SWDT_COUNT_SWDTCLK_DIV32 ((uint16_t)0x0050) ///< SWDTCLK/32 +#define SWDT_COUNT_SWDTCLK_DIV64 ((uint16_t)0x0060) ///< SWDTCLK/64 +#define SWDT_COUNT_SWDTCLK_DIV128 ((uint16_t)0x0070) ///< SWDTCLK/128 +#define SWDT_COUNT_SWDTCLK_DIV256 ((uint16_t)0x0080) ///< SWDTCLK/256 +#define SWDT_COUNT_SWDTCLK_DIV2048 ((uint16_t)0x00B0) ///< SWDTCLK/2048 + +/** + ******************************************************************************* + ** \brief SWDT allow refresh percent range + ******************************************************************************/ +#define SWDT_100PCT ((uint16_t)0x0000) ///< 100% +#define SWDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define SWDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define SWDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define SWDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define SWDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define SWDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define SWDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define SWDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define SWDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define SWDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define SWDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define SWDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define SWDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define SWDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define SWDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief SWDT count control in the sleep/stop mode + ******************************************************************************/ +#define SWDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< SWDT count continue in the sleep/stop mode +#define SWDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< SWDT count stop in the sleep/stop mode + +/** + ******************************************************************************* + ** \brief WDT running state after reset + ******************************************************************************/ +#define WDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< WDT Auto Start after reset +#define WDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< WDT stop after reset + +/** + ******************************************************************************* + ** \brief WDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define WDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define WDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief WDT count underflow cycle + ******************************************************************************/ +#define WDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief WDT count clock division + ******************************************************************************/ +#define WDT_COUNT_PCLK3_DIV4 ((uint16_t)0x0020) ///< PCLK3/4 +#define WDT_COUNT_PCLK3_DIV64 ((uint16_t)0x0060) ///< PCLK3/64 +#define WDT_COUNT_PCLK3_DIV128 ((uint16_t)0x0070) ///< PCLK3/128 +#define WDT_COUNT_PCLK3_DIV256 ((uint16_t)0x0080) ///< PCLK3/256 +#define WDT_COUNT_PCLK3_DIV512 ((uint16_t)0x0090) ///< PCLK3/512 +#define WDT_COUNT_PCLK3_DIV1024 ((uint16_t)0x00A0) ///< PCLK3/1024 +#define WDT_COUNT_PCLK3_DIV2048 ((uint16_t)0x00B0) ///< PCLK3/2048 +#define WDT_COUNT_PCLK3_DIV8192 ((uint16_t)0x00D0) ///< PCLK3/8192 + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range + ******************************************************************************/ +#define WDT_100PCT ((uint16_t)0x0000) ///< 100% +#define WDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define WDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define WDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define WDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define WDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define WDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define WDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define WDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define WDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define WDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define WDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define WDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define WDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define WDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define WDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief WDT count control in the sleep mode + ******************************************************************************/ +#define WDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< WDT count continue in the sleep mode +#define WDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< WDT count stop in the sleep mode + +/** + ******************************************************************************* + ** \brief HRC frequency select + ******************************************************************************/ +#define HRC_FREQUENCY_20MHZ ((uint16_t)0x0000) ///< HRC frequency 20MHZ +#define HRC_FREQUENCY_16MHZ ((uint16_t)0x0001) ///< HRC frequency 16MHZ + +/** + ******************************************************************************* + ** \brief HRC oscillation state control + ******************************************************************************/ +#define HRC_OSCILLATION_START ((uint16_t)0x0000) ///< HRC oscillation start +#define HRC_OSCILLATION_STOP ((uint16_t)0x0100) ///< HRC oscillation stop + +/** + ******************************************************************************* + ** \brief VDU0 threshold voltage select + ******************************************************************************/ +#define VDU0_VOLTAGE_THRESHOLD_1P5 ((uint8_t)0x00) ///< VDU0 voltage threshold 1.9V +#define VDU0_VOLTAGE_THRESHOLD_2P0 ((uint8_t)0x01) ///< VDU0 voltage threshold 2.0V +#define VDU0_VOLTAGE_THRESHOLD_2P1 ((uint8_t)0x02) ///< VDU0 voltage threshold 2.1V +#define VDU0_VOLTAGE_THRESHOLD_2P3 ((uint8_t)0x03) ///< VDU0 voltage threshold 2.3V + +/** + ******************************************************************************* + ** \brief VDU0 running state after reset + ******************************************************************************/ +#define VDU0_START_AFTER_RESET ((uint8_t)0x00) ///< VDU0 start after reset +#define VDU0_STOP_AFTER_RESET ((uint8_t)0x04) ///< VDU0 stop after reset + +/** + ******************************************************************************* + ** \brief NMI pin filter sample clock division + ******************************************************************************/ +#define NMI_PIN_FILTER_PCLK3_DIV1 ((uint8_t)0x00) ///< PCLK3 +#define NMI_PIN_FILTER_PCLK3_DIV8 ((uint8_t)0x04) ///< PCLK3/8 +#define NMI_PIN_FILTER_PCLK3_DIV32 ((uint8_t)0x08) ///< PCLK3/32 +#define NMI_PIN_FILTER_PCLK3_DIV64 ((uint8_t)0x0C) ///< PCLK3/64 + +/** + ******************************************************************************* + ** \brief NMI pin trigger edge type + ******************************************************************************/ +#define NMI_PIN_TRIGGER_EDGE_FALLING ((uint8_t)0x00) ///< Falling edge trigger +#define NMI_PIN_TRIGGER_EDGE_RISING ((uint8_t)0x10) ///< Rising edge trigger + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin interrupt request + ******************************************************************************/ +#define NMI_PIN_IRQ_DISABLE ((uint8_t)0x00) ///< Disable NMI pin interrupt request +#define NMI_PIN_IRQ_ENABLE ((uint8_t)0x20) ///< Enable NMI pin interrupt request + +/** + ******************************************************************************* + ** \brief Enable or disable NMI digital filter function + ******************************************************************************/ +#define NMI_DIGITAL_FILTER_DISABLE ((uint8_t)0x00) ///< Disable NMI digital filter +#define NMI_DIGITAL_FILTER_ENABLE ((uint8_t)0x40) ///< Enable NMI digital filter + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin ICG function + ******************************************************************************/ +#define NMI_PIN_ICG_FUNCTION_DISABLE ((uint8_t)0x80) ///< Disable NMI pin ICG function +#define NMI_PIN_ICG_FUNCTION_ENABLE ((uint8_t)0x00) ///< Enable NMI pin ICG function + +/** + ******************************************************************************* + ** \brief ICG start configure function on/off + ******************************************************************************/ +#ifndef ICG_FUNCTION_ON +#define ICG_FUNCTION_ON (1u) +#endif + +#ifndef ICG_FUNCTION_OFF +#define ICG_FUNCTION_OFF (0u) +#endif + +/** + ******************************************************************************* + ** \brief SWDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable SWDT hardware start */ +#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< SWDT register config */ +#define ICG0_SWDT_AUTS (SWDT_STOP_AFTER_RESET) +#define ICG0_SWDT_ITS (SWDT_RESET_REQUEST) +#define ICG0_SWDT_PERI (SWDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_SWDT_CKS (SWDT_COUNT_SWDTCLK_DIV2048) +#define ICG0_SWDT_WDPT (SWDT_0To100PCT) +#define ICG0_SWDT_SLTPOFF (SWDT_SPECIAL_MODE_COUNT_STOP) + +/*!< SWDT register config value */ +#if ICG0_SWDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_SWDT_REG_CONFIG (ICG0_SWDT_AUTS | ICG0_SWDT_ITS | ICG0_SWDT_PERI | \ + ICG0_SWDT_CKS | ICG0_SWDT_WDPT | ICG0_SWDT_SLTPOFF) +#else +#define ICG0_SWDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief WDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable WDT hardware start */ +#define ICG0_WDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< WDT register config */ +#define ICG0_WDT_AUTS (WDT_STOP_AFTER_RESET) +#define ICG0_WDT_ITS (WDT_RESET_REQUEST) +#define ICG0_WDT_PERI (WDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_WDT_CKS (WDT_COUNT_PCLK3_DIV8192) +#define ICG0_WDT_WDPT (WDT_0To100PCT) +#define ICG0_WDT_SLPOFF (WDT_SPECIAL_MODE_COUNT_STOP) + +/*!< WDT register config value */ +#if ICG0_WDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_WDT_REG_CONFIG (ICG0_WDT_AUTS | ICG0_WDT_ITS | ICG0_WDT_PERI | \ + ICG0_WDT_CKS | ICG0_WDT_WDPT | ICG0_WDT_SLPOFF) +#else +#define ICG0_WDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief HRC hardware start configuration + ******************************************************************************/ +/*!< Enable or disable HRC hardware start */ +#define ICG1_HRC_HARDWARE_START (ICG_FUNCTION_ON) + +/*!< HRC register config */ +#define ICG1_HRC_FREQSEL (HRC_FREQUENCY_16MHZ) +#define ICG1_HRC_STOP (HRC_OSCILLATION_START) + +/*!< HRC register config value */ +#if ICG1_HRC_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_HRC_REG_CONFIG (ICG1_HRC_FREQSEL | ICG1_HRC_STOP) +#else +#define ICG1_HRC_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief VDU0 hardware start configuration + ******************************************************************************/ +/*!< Enable or disable VDU0 hardware start */ +#define ICG1_VDU0_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< VDU0 register config */ +#define ICG1_VDU0_BOR_LEV (VDU0_VOLTAGE_THRESHOLD_2P3) +#define ICG1_VDU0_BORDIS (VDU0_STOP_AFTER_RESET) + +/*!< VDU0 register config value */ +#if ICG1_VDU0_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_VDU0_REG_CONFIG (ICG1_VDU0_BOR_LEV | ICG1_VDU0_BORDIS) +#else +#define ICG1_VDU0_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief NMI hardware start configuration + ******************************************************************************/ +/*!< Enable or disable NMI hardware start */ +#define ICG1_NMI_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< NMI register config */ +#define ICG1_NMI_SMPCLK (NMI_PIN_FILTER_PCLK3_DIV1) +#define ICG1_NMI_TRG (NMI_PIN_TRIGGER_EDGE_RISING) +#define ICG1_NMI_IMR (NMI_PIN_IRQ_DISABLE) +#define ICG1_NMI_NFEN (NMI_DIGITAL_FILTER_DISABLE) +#define ICG1_NMI_ICGENA (NMI_PIN_ICG_FUNCTION_DISABLE) + +/*!< NMI register config value */ +#if ICG1_NMI_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_NMI_REG_CONFIG (ICG1_NMI_SMPCLK | ICG1_NMI_TRG | \ + ICG1_NMI_IMR | ICG1_NMI_NFEN | ICG1_NMI_ICGENA) +#else +#define ICG1_NMI_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief ICG registers configuration + ******************************************************************************/ +/*!< ICG0 register value */ +#define ICG0_REGISTER_CONSTANT (((uint32_t)ICG0_WDT_REG_CONFIG << 16) | \ + ((uint32_t)ICG0_SWDT_REG_CONFIG) | \ + ((uint32_t)0xE000E000ul)) +/*!< ICG1 register value */ +#define ICG1_REGISTER_CONSTANT (((uint32_t)ICG1_NMI_REG_CONFIG << 24) | \ + ((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \ + ((uint32_t)ICG1_HRC_REG_CONFIG) | \ + ((uint32_t)0x03F8FEFEul)) +/*!< ICG2~7 register reserved value */ +#define ICG2_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG3_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG4_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG5_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG6_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG7_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // IcgGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_interrupts.h b/lib/hc32f460/driver/inc/hc32f460_interrupts.h new file mode 100644 index 000000000000..bb8ed8c5aa68 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_interrupts.h @@ -0,0 +1,537 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_interrupts.h + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ +#ifndef __HC32F460_INTERRUPTS_H___ +#define __HC32F460_INTERRUPTS_H___ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup InterruptGroup Interrupt + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief IRQ registration structure definition + ******************************************************************************/ +typedef struct stc_irq_regi_conf +{ + en_int_src_t enIntSrc; + IRQn_Type enIRQn; + func_ptr_t pfnCallback; +}stc_irq_regi_conf_t; + +/** + ******************************************************************************* + ** \brief stop mode interrupt wakeup source enumeration + ******************************************************************************/ +typedef enum en_int_wkup_src +{ + Extint0WU = 1u << 0, + Extint1WU = 1u << 1, + Extint2WU = 1u << 2, + Extint3WU = 1u << 3, + Extint4WU = 1u << 4, + Extint5WU = 1u << 5, + Extint6WU = 1u << 6, + Extint7WU = 1u << 7, + Extint8WU = 1u << 8, + Extint9WU = 1u << 9, + Extint10WU = 1u << 10, + Extint11WU = 1u << 11, + Extint12WU = 1u << 12, + Extint13WU = 1u << 13, + Extint14WU = 1u << 14, + Extint15WU = 1u << 15, + SwdtWU = 1u << 16, + Vdu1WU = 1u << 17, + Vdu2WU = 1u << 18, + CmpWU = 1u << 19, + WakeupTimerWU = 1u << 20, + RtcAlarmWU = 1u << 21, + RtcPeriodWU = 1u << 22, + Timer0WU = 1u << 23, + Usart1RxWU = 1u << 25, +}en_int_wkup_src_t; + +/** + ******************************************************************************* + ** \brief event enumeration + ******************************************************************************/ +typedef enum en_evt +{ + Event0 = 1u << 0, + Event1 = 1u << 1, + Event2 = 1u << 2, + Event3 = 1u << 3, + Event4 = 1u << 4, + Event5 = 1u << 5, + Event6 = 1u << 6, + Event7 = 1u << 7, + Event8 = 1u << 8, + Event9 = 1u << 9, + Event10 = 1u << 10, + Event11 = 1u << 11, + Event12 = 1u << 12, + Event13 = 1u << 13, + Event14 = 1u << 14, + Event15 = 1u << 15, + Event16 = 1u << 16, + Event17 = 1u << 17, + Event18 = 1u << 18, + Event19 = 1u << 19, + Event20 = 1u << 20, + Event21 = 1u << 21, + Event22 = 1u << 22, + Event23 = 1u << 23, + Event24 = 1u << 24, + Event25 = 1u << 25, + Event26 = 1u << 26, + Event27 = 1u << 27, + Event28 = 1u << 28, + Event29 = 1u << 29, + Event30 = 1u << 30, + Event31 = 1u << 31, +}en_evt_t; + +/** + ******************************************************************************* + ** \brief interrupt enumeration + ******************************************************************************/ +typedef enum en_int +{ + Int0 = 1u << 0, + Int1 = 1u << 1, + Int2 = 1u << 2, + Int3 = 1u << 3, + Int4 = 1u << 4, + Int5 = 1u << 5, + Int6 = 1u << 6, + Int7 = 1u << 7, + Int8 = 1u << 8, + Int9 = 1u << 9, + Int10 = 1u << 10, + Int11 = 1u << 11, + Int12 = 1u << 12, + Int13 = 1u << 13, + Int14 = 1u << 14, + Int15 = 1u << 15, + Int16 = 1u << 16, + Int17 = 1u << 17, + Int18 = 1u << 18, + Int19 = 1u << 19, + Int20 = 1u << 20, + Int21 = 1u << 21, + Int22 = 1u << 22, + Int23 = 1u << 23, + Int24 = 1u << 24, + Int25 = 1u << 25, + Int26 = 1u << 26, + Int27 = 1u << 27, + Int28 = 1u << 28, + Int29 = 1u << 29, + Int30 = 1u << 30, + Int31 = 1u << 31, +}en_int_t; + + +/*! Bit mask definition*/ +#define BIT_MASK_00 (1ul << 0) +#define BIT_MASK_01 (1ul << 1) +#define BIT_MASK_02 (1ul << 2) +#define BIT_MASK_03 (1ul << 3) +#define BIT_MASK_04 (1ul << 4) +#define BIT_MASK_05 (1ul << 5) +#define BIT_MASK_06 (1ul << 6) +#define BIT_MASK_07 (1ul << 7) +#define BIT_MASK_08 (1ul << 8) +#define BIT_MASK_09 (1ul << 9) +#define BIT_MASK_10 (1ul << 10) +#define BIT_MASK_11 (1ul << 11) +#define BIT_MASK_12 (1ul << 12) +#define BIT_MASK_13 (1ul << 13) +#define BIT_MASK_14 (1ul << 14) +#define BIT_MASK_15 (1ul << 15) +#define BIT_MASK_16 (1ul << 16) +#define BIT_MASK_17 (1ul << 17) +#define BIT_MASK_18 (1ul << 18) +#define BIT_MASK_19 (1ul << 19) +#define BIT_MASK_20 (1ul << 20) +#define BIT_MASK_21 (1ul << 21) +#define BIT_MASK_22 (1ul << 22) +#define BIT_MASK_23 (1ul << 23) +#define BIT_MASK_24 (1ul << 24) +#define BIT_MASK_25 (1ul << 25) +#define BIT_MASK_26 (1ul << 26) +#define BIT_MASK_27 (1ul << 27) +#define BIT_MASK_28 (1ul << 28) +#define BIT_MASK_29 (1ul << 29) +#define BIT_MASK_30 (1ul << 30) +#define BIT_MASK_31 (1ul << 31) + +/*! Default Priority for IRQ, Possible values are 0 (high priority) to 15 (low priority) */ +#define DDL_IRQ_PRIORITY_DEFAULT 15u + +/*! Interrupt priority level 00 ~ 15*/ +#define DDL_IRQ_PRIORITY_00 (0u) +#define DDL_IRQ_PRIORITY_01 (1u) +#define DDL_IRQ_PRIORITY_02 (2u) +#define DDL_IRQ_PRIORITY_03 (3u) +#define DDL_IRQ_PRIORITY_04 (4u) +#define DDL_IRQ_PRIORITY_05 (5u) +#define DDL_IRQ_PRIORITY_06 (6u) +#define DDL_IRQ_PRIORITY_07 (7u) +#define DDL_IRQ_PRIORITY_08 (8u) +#define DDL_IRQ_PRIORITY_09 (9u) +#define DDL_IRQ_PRIORITY_10 (10u) +#define DDL_IRQ_PRIORITY_11 (11u) +#define DDL_IRQ_PRIORITY_12 (12u) +#define DDL_IRQ_PRIORITY_13 (13u) +#define DDL_IRQ_PRIORITY_14 (14u) +#define DDL_IRQ_PRIORITY_15 (15u) + +/** + ******************************************************************************* + ** \brief AOS software trigger function + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + bM4_AOS_INT_SFTTRG_STRG = 1u; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 1 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig) +{ + M4_AOS->COMTRG1 = enTrig; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 2 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig) +{ + M4_AOS->COMTRG2 = enTrig; +} + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf); +extern en_result_t enIrqResign(IRQn_Type enIRQn); +extern en_result_t enShareIrqEnable(en_int_src_t enIntSrc); +extern en_result_t enShareIrqDisable(en_int_src_t enIntSrc); +extern en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc); +extern en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc); +extern en_result_t enEventEnable(uint32_t u32Event); +extern en_result_t enEventDisable(uint32_t u32Event); +extern en_result_t enIntEnable(uint32_t u32Int); +extern en_result_t enIntDisable(uint32_t u32Int); + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +__WEAKDEF void NMI_IrqHandler(void); +__WEAKDEF void HardFault_IrqHandler(void); +__WEAKDEF void MemManage_IrqHandler(void); +__WEAKDEF void BusFault_IrqHandler(void); +__WEAKDEF void UsageFault_IrqHandler(void); +__WEAKDEF void SVC_IrqHandler(void); +__WEAKDEF void DebugMon_IrqHandler(void); +__WEAKDEF void PendSV_IrqHandler(void); +__WEAKDEF void SysTick_IrqHandler(void); + +__WEAKDEF void Extint00_IrqHandler(void); +__WEAKDEF void Extint01_IrqHandler(void); +__WEAKDEF void Extint02_IrqHandler(void); +__WEAKDEF void Extint03_IrqHandler(void); +__WEAKDEF void Extint04_IrqHandler(void); +__WEAKDEF void Extint05_IrqHandler(void); +__WEAKDEF void Extint06_IrqHandler(void); +__WEAKDEF void Extint07_IrqHandler(void); +__WEAKDEF void Extint08_IrqHandler(void); +__WEAKDEF void Extint09_IrqHandler(void); +__WEAKDEF void Extint10_IrqHandler(void); +__WEAKDEF void Extint11_IrqHandler(void); +__WEAKDEF void Extint12_IrqHandler(void); +__WEAKDEF void Extint13_IrqHandler(void); +__WEAKDEF void Extint14_IrqHandler(void); +__WEAKDEF void Extint15_IrqHandler(void); + +__WEAKDEF void Dma1Tc0_IrqHandler(void); +__WEAKDEF void Dma1Tc1_IrqHandler(void); +__WEAKDEF void Dma1Tc2_IrqHandler(void); +__WEAKDEF void Dma1Tc3_IrqHandler(void); +__WEAKDEF void Dma2Tc0_IrqHandler(void); +__WEAKDEF void Dma2Tc1_IrqHandler(void); +__WEAKDEF void Dma2Tc2_IrqHandler(void); +__WEAKDEF void Dma2Tc3_IrqHandler(void); +__WEAKDEF void Dma1Btc0_IrqHandler(void); +__WEAKDEF void Dma1Btc1_IrqHandler(void); +__WEAKDEF void Dma1Btc2_IrqHandler(void); +__WEAKDEF void Dma1Btc3_IrqHandler(void); +__WEAKDEF void Dma2Btc0_IrqHandler(void); +__WEAKDEF void Dma2Btc1_IrqHandler(void); +__WEAKDEF void Dma2Btc2_IrqHandler(void); +__WEAKDEF void Dma2Btc3_IrqHandler(void); +__WEAKDEF void Dma1Err0_IrqHandler(void); +__WEAKDEF void Dma1Err1_IrqHandler(void); +__WEAKDEF void Dma1Err2_IrqHandler(void); +__WEAKDEF void Dma1Err3_IrqHandler(void); +__WEAKDEF void Dma2Err0_IrqHandler(void); +__WEAKDEF void Dma2Err1_IrqHandler(void); +__WEAKDEF void Dma2Err2_IrqHandler(void); +__WEAKDEF void Dma2Err3_IrqHandler(void); + +__WEAKDEF void EfmPgmEraseErr_IrqHandler(void); +__WEAKDEF void EfmColErr_IrqHandler(void); +__WEAKDEF void EfmOpEnd_IrqHandler(void); +__WEAKDEF void QspiInt_IrqHandler(void); +__WEAKDEF void Dcu1_IrqHandler(void); +__WEAKDEF void Dcu2_IrqHandler(void); +__WEAKDEF void Dcu3_IrqHandler(void); +__WEAKDEF void Dcu4_IrqHandler(void); + +__WEAKDEF void Timer01GCMA_IrqHandler(void); +__WEAKDEF void Timer01GCMB_IrqHandler(void); +__WEAKDEF void Timer02GCMA_IrqHandler(void); +__WEAKDEF void Timer02GCMB_IrqHandler(void); + +__WEAKDEF void MainOscStop_IrqHandler(void); +__WEAKDEF void WakeupTimer_IrqHandler(void); +__WEAKDEF void Swdt_IrqHandler(void); + +__WEAKDEF void Timer61GCMA_IrqHandler(void); +__WEAKDEF void Timer61GCMB_IrqHandler(void); +__WEAKDEF void Timer61GCMC_IrqHandler(void); +__WEAKDEF void Timer61GCMD_IrqHandler(void); +__WEAKDEF void Timer61GCME_IrqHandler(void); +__WEAKDEF void Timer61GCMF_IrqHandler(void); +__WEAKDEF void Timer61GOV_IrqHandler(void); +__WEAKDEF void Timer61GUD_IrqHandler(void); +__WEAKDEF void Timer61GDT_IrqHandler(void); +__WEAKDEF void Timer61SCMA_IrqHandler(void); +__WEAKDEF void Timer61SCMB_IrqHandler(void); + +__WEAKDEF void Timer62GCMA_IrqHandler(void); +__WEAKDEF void Timer62GCMB_IrqHandler(void); +__WEAKDEF void Timer62GCMC_IrqHandler(void); +__WEAKDEF void Timer62GCMD_IrqHandler(void); +__WEAKDEF void Timer62GCME_IrqHandler(void); +__WEAKDEF void Timer62GCMF_IrqHandler(void); +__WEAKDEF void Timer62GOV_IrqHandler(void); +__WEAKDEF void Timer62GUD_IrqHandler(void); +__WEAKDEF void Timer62GDT_IrqHandler(void); +__WEAKDEF void Timer62SCMA_IrqHandler(void); +__WEAKDEF void Timer62SCMB_IrqHandler(void); + +__WEAKDEF void Timer63GCMA_IrqHandler(void); +__WEAKDEF void Timer63GCMB_IrqHandler(void); +__WEAKDEF void Timer63GCMC_IrqHandler(void); +__WEAKDEF void Timer63GCMD_IrqHandler(void); +__WEAKDEF void Timer63GCME_IrqHandler(void); +__WEAKDEF void Timer63GCMF_IrqHandler(void); +__WEAKDEF void Timer63GOV_IrqHandler(void); +__WEAKDEF void Timer63GUD_IrqHandler(void); +__WEAKDEF void Timer63GDT_IrqHandler(void); +__WEAKDEF void Timer63SCMA_IrqHandler(void); +__WEAKDEF void Timer63SCMB_IrqHandler(void); + +__WEAKDEF void TimerA1OV_IrqHandler(void); +__WEAKDEF void TimerA1UD_IrqHandler(void); +__WEAKDEF void TimerA1CMP_IrqHandler(void); +__WEAKDEF void TimerA2OV_IrqHandler(void); +__WEAKDEF void TimerA2UD_IrqHandler(void); +__WEAKDEF void TimerA2CMP_IrqHandler(void); +__WEAKDEF void TimerA3OV_IrqHandler(void); +__WEAKDEF void TimerA3UD_IrqHandler(void); +__WEAKDEF void TimerA3CMP_IrqHandler(void); +__WEAKDEF void TimerA4OV_IrqHandler(void); +__WEAKDEF void TimerA4UD_IrqHandler(void); +__WEAKDEF void TimerA4CMP_IrqHandler(void); +__WEAKDEF void TimerA5OV_IrqHandler(void); +__WEAKDEF void TimerA5UD_IrqHandler(void); +__WEAKDEF void TimerA5CMP_IrqHandler(void); +__WEAKDEF void TimerA6OV_IrqHandler(void); +__WEAKDEF void TimerA6UD_IrqHandler(void); +__WEAKDEF void TimerA6CMP_IrqHandler(void); + +__WEAKDEF void UsbGlobal_IrqHandler(void); + +__WEAKDEF void Usart1RxErr_IrqHandler(void); +__WEAKDEF void Usart1RxEnd_IrqHandler(void); +__WEAKDEF void Usart1TxEmpty_IrqHandler(void); +__WEAKDEF void Usart1TxEnd_IrqHandler(void); +__WEAKDEF void Usart1RxTO_IrqHandler(void); +__WEAKDEF void Usart2RxErr_IrqHandler(void); +__WEAKDEF void Usart2RxEnd_IrqHandler(void); +__WEAKDEF void Usart2TxEmpty_IrqHandler(void); +__WEAKDEF void Usart2TxEnd_IrqHandler(void); +__WEAKDEF void Usart2RxTO_IrqHandler(void); +__WEAKDEF void Usart3RxErr_IrqHandler(void); +__WEAKDEF void Usart3RxEnd_IrqHandler(void); +__WEAKDEF void Usart3TxEmpty_IrqHandler(void); +__WEAKDEF void Usart3TxEnd_IrqHandler(void); +__WEAKDEF void Usart3RxTO_IrqHandler(void); +__WEAKDEF void Usart4RxErr_IrqHandler(void); +__WEAKDEF void Usart4RxEnd_IrqHandler(void); +__WEAKDEF void Usart4TxEmpty_IrqHandler(void); +__WEAKDEF void Usart4TxEnd_IrqHandler(void); +__WEAKDEF void Usart4RxTO_IrqHandler(void); + +__WEAKDEF void Spi1RxEnd_IrqHandler(void); +__WEAKDEF void Spi1TxEmpty_IrqHandler(void); +__WEAKDEF void Spi1Err_IrqHandler(void); +__WEAKDEF void Spi1Idle_IrqHandler(void); +__WEAKDEF void Spi2RxEnd_IrqHandler(void); +__WEAKDEF void Spi2TxEmpty_IrqHandler(void); +__WEAKDEF void Spi2Err_IrqHandler(void); +__WEAKDEF void Spi2Idle_IrqHandler(void); +__WEAKDEF void Spi3RxEnd_IrqHandler(void); +__WEAKDEF void Spi3TxEmpty_IrqHandler(void); +__WEAKDEF void Spi3Err_IrqHandler(void); +__WEAKDEF void Spi3Idle_IrqHandler(void); +__WEAKDEF void Spi4RxEnd_IrqHandler(void); +__WEAKDEF void Spi4TxEmpty_IrqHandler(void); +__WEAKDEF void Spi4Err_IrqHandler(void); +__WEAKDEF void Spi4Idle_IrqHandler(void); + +__WEAKDEF void Timer41GCMUH_IrqHandler(void); +__WEAKDEF void Timer41GCMUL_IrqHandler(void); +__WEAKDEF void Timer41GCMVH_IrqHandler(void); +__WEAKDEF void Timer41GCMVL_IrqHandler(void); +__WEAKDEF void Timer41GCMWH_IrqHandler(void); +__WEAKDEF void Timer41GCMWL_IrqHandler(void); +__WEAKDEF void Timer41GOV_IrqHandler(void); +__WEAKDEF void Timer41GUD_IrqHandler(void); +__WEAKDEF void Timer41ReloadU_IrqHandler(void); +__WEAKDEF void Timer41ReloadV_IrqHandler(void); +__WEAKDEF void Timer41ReloadW_IrqHandler(void); +__WEAKDEF void Timer42GCMUH_IrqHandler(void); +__WEAKDEF void Timer42GCMUL_IrqHandler(void); +__WEAKDEF void Timer42GCMVH_IrqHandler(void); +__WEAKDEF void Timer42GCMVL_IrqHandler(void); +__WEAKDEF void Timer42GCMWH_IrqHandler(void); +__WEAKDEF void Timer42GCMWL_IrqHandler(void); +__WEAKDEF void Timer42GOV_IrqHandler(void); +__WEAKDEF void Timer42GUD_IrqHandler(void); +__WEAKDEF void Timer42ReloadU_IrqHandler(void); +__WEAKDEF void Timer42ReloadV_IrqHandler(void); +__WEAKDEF void Timer42ReloadW_IrqHandler(void); +__WEAKDEF void Timer43GCMUH_IrqHandler(void); +__WEAKDEF void Timer43GCMUL_IrqHandler(void); +__WEAKDEF void Timer43GCMVH_IrqHandler(void); +__WEAKDEF void Timer43GCMVL_IrqHandler(void); +__WEAKDEF void Timer43GCMWH_IrqHandler(void); +__WEAKDEF void Timer43GCMWL_IrqHandler(void); +__WEAKDEF void Timer43GOV_IrqHandler(void); +__WEAKDEF void Timer43GUD_IrqHandler(void); +__WEAKDEF void Timer43ReloadU_IrqHandler(void); +__WEAKDEF void Timer43ReloadV_IrqHandler(void); +__WEAKDEF void Timer43ReloadW_IrqHandler(void); + +__WEAKDEF void Emb1_IrqHandler(void); +__WEAKDEF void Emb2_IrqHandler(void); +__WEAKDEF void Emb3_IrqHandler(void); +__WEAKDEF void Emb4_IrqHandler(void); + +__WEAKDEF void I2s1Tx_IrqHandler(void); +__WEAKDEF void I2s1Rx_IrqHandler(void); +__WEAKDEF void I2s1Err_IrqHandler(void); +__WEAKDEF void I2s2Tx_IrqHandler(void); +__WEAKDEF void I2s2Rx_IrqHandler(void); +__WEAKDEF void I2s2Err_IrqHandler(void); +__WEAKDEF void I2s3Tx_IrqHandler(void); +__WEAKDEF void I2s3Rx_IrqHandler(void); +__WEAKDEF void I2s3Err_IrqHandler(void); +__WEAKDEF void I2s4Tx_IrqHandler(void); +__WEAKDEF void I2s4Rx_IrqHandler(void); +__WEAKDEF void I2s4Err_IrqHandler(void); + +__WEAKDEF void I2c1RxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEmpty_IrqHandler(void); +__WEAKDEF void I2c1Err_IrqHandler(void); +__WEAKDEF void I2c2RxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEmpty_IrqHandler(void); +__WEAKDEF void I2c2Err_IrqHandler(void); +__WEAKDEF void I2c3RxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEmpty_IrqHandler(void); +__WEAKDEF void I2c3Err_IrqHandler(void); + +__WEAKDEF void Pvd1_IrqHandler(void); +__WEAKDEF void Pvd2_IrqHandler(void); + +__WEAKDEF void FcmErr_IrqHandler(void); +__WEAKDEF void FcmEnd_IrqHandler(void); +__WEAKDEF void FcmOV_IrqHandler(void); + +__WEAKDEF void Wdt_IrqHandler(void); + +__WEAKDEF void ADC1A_IrqHandler(void); +__WEAKDEF void ADC1B_IrqHandler(void); +__WEAKDEF void ADC1ChCmp_IrqHandler(void); +__WEAKDEF void ADC1SeqCmp_IrqHandler(void); +__WEAKDEF void ADC2A_IrqHandler(void); +__WEAKDEF void ADC2B_IrqHandler(void); +__WEAKDEF void ADC2ChCmp_IrqHandler(void); +__WEAKDEF void ADC2SeqCmp_IrqHandler(void); + +__WEAKDEF void Sdio1_IrqHandler(void); +__WEAKDEF void Sdio2_IrqHandler(void); + +__WEAKDEF void Can_IrqHandler(void); + +//@} // InterruptGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_INTERRUPTS_H___ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_keyscan.h b/lib/hc32f460/driver/inc/hc32f460_keyscan.h new file mode 100644 index 000000000000..a06ecbc8e2c8 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_keyscan.h @@ -0,0 +1,186 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.h + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +#ifndef __HC32F460_KEYSCAN_H__ +#define __HC32F460_KEYSCAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup KeyscanGroup Matrix Key Scan Module (KeyScan) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to hi-z state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_hiz_cycle +{ + Hiz4 = 0u, + Hiz8 = 1u, + Hiz16 = 2u, + Hiz32 = 3u, + Hiz64 = 4u, + Hiz256 = 5u, + Hiz512 = 6u, + Hiz1K = 7u, +}en_hiz_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to low state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_low_cycle +{ + Low8 = 3u, + Low16 = 4u, + Low32 = 5u, + Low64 = 6u, + Low128 = 7u, + Low256 = 8u, + Low512 = 9u, + Low1K = 10u, + Low2K = 11u, + Low4K = 12u, + Low8K = 13u, + Low16K = 14u, + Low32K = 15u, + Low64K = 16u, + Low128K = 17u, + Low256K = 18u, + Low512K = 19u, + Low1M = 20u, + Low2M = 21u, + Low4M = 22u, + Low8M = 23u, + Low16M = 24u, +}en_low_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to key scan clock + ** + ** \note + ******************************************************************************/ +typedef enum en_keyscan_clk +{ + KeyscanHclk = 0u, ///< use HCLK as scan clock + KeyscanLrc = 1u, ///< use internal Low RC as scan clock + KeyscanXtal32 = 2u, ///< use external XTAL32 as scan clock +}en_keyscan_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYOUT combination + ******************************************************************************/ +typedef enum en_keyout_sel +{ + Keyout0To1 = 1u, ///< KEYOUT 0 to 1 are selected + Keyout0To2 = 2u, ///< KEYOUT 0 to 2 are selected + Keyout0To3 = 3u, ///< KEYOUT 0 to 3 are selected + Keyout0To4 = 4u, ///< KEYOUT 0 to 4 are selected + Keyout0To5 = 5u, ///< KEYOUT 0 to 5 are selected + Keyout0To6 = 6u, ///< KEYOUT 0 to 6 are selected + Keyout0To7 = 7u, ///< KEYOUT 0 to 7 are selected +}en_keyout_sel_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYIN combination + ******************************************************************************/ +typedef enum en_keyin_sel +{ + Keyin00 = 1u << 0, ///< KEYIN 0 is selected + Keyin01 = 1u << 1, ///< KEYIN 1 is selected + Keyin02 = 1u << 2, ///< KEYIN 2 is selected + Keyin03 = 1u << 3, ///< KEYIN 3 is selected + Keyin04 = 1u << 4, ///< KEYIN 4 is selected + Keyin05 = 1u << 5, ///< KEYIN 5 is selected + Keyin06 = 1u << 6, ///< KEYIN 6 is selected + Keyin07 = 1u << 7, ///< KEYIN 7 is selected + Keyin08 = 1u << 8, ///< KEYIN 8 is selected + Keyin09 = 1u << 9, ///< KEYIN 9 is selected + Keyin10 = 1u << 10, ///< KEYIN 10 is selected + Keyin11 = 1u << 11, ///< KEYIN 11 is selected + Keyin12 = 1u << 12, ///< KEYIN 12 is selected + Keyin13 = 1u << 13, ///< KEYIN 13 is selected + Keyin14 = 1u << 14, ///< KEYIN 14 is selected + Keyin15 = 1u << 15, ///< KEYIN 15 is selected +}en_keyin_sel_t; + +/** + ******************************************************************************* + ** \brief Keyscan configuration + ** + ** \note The Keyscan configuration structure + ******************************************************************************/ +typedef struct stc_keyscan_config +{ + en_hiz_cycle_t enHizCycle; ///< KEYOUT Hiz state cycles, ref @ en_hiz_cycle_t for details + en_low_cycle_t enLowCycle; ///< KEYOUT Low state cycles, ref @ en_low_cycle_t for details + en_keyscan_clk_t enKeyscanClk; ///< Key scan clock, ref @ en_keyscan_clk_t for details + en_keyout_sel_t enKeyoutSel; ///< KEYOUT selection, ref @ en_keyout_sel_t for details + uint16_t u16KeyinSel; ///< KEYIN selection, ref @ en_keyin_sel_t for details +}stc_keyscan_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig); +extern en_result_t KEYSCAN_DeInit(void); +extern en_result_t KEYSCAN_Start(void); +extern en_result_t KEYSCAN_Stop(void); +extern uint8_t KEYSCAN_GetColIdx(void); + +//@} // KeyscanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_KEYSCAN_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_mpu.h b/lib/hc32f460/driver/inc/hc32f460_mpu.h new file mode 100644 index 000000000000..6657571ed5f2 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_mpu.h @@ -0,0 +1,288 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.h + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ +#ifndef __HC32F460_MPU_H__ +#define __HC32F460_MPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup MpuGroup Memory Protection Unit(MPU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief MPU region number enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_num +{ + MpuRegionNum0 = 0u, ///< MPU region number 0 + MpuRegionNum1 = 1u, ///< MPU region number 1 + MpuRegionNum2 = 2u, ///< MPU region number 2 + MpuRegionNum3 = 3u, ///< MPU region number 3 + MpuRegionNum4 = 4u, ///< MPU region number 4 + MpuRegionNum5 = 5u, ///< MPU region number 5 + MpuRegionNum6 = 6u, ///< MPU region number 6 + MpuRegionNum7 = 7u, ///< MPU region number 7 + MpuRegionNum8 = 8u, ///< MPU region number 8 + MpuRegionNum9 = 9u, ///< MPU region number 9 + MpuRegionNum10 = 10u, ///< MPU region number 10 + MpuRegionNum11 = 11u, ///< MPU region number 11 + MpuRegionNum12 = 12u, ///< MPU region number 12 + MpuRegionNum13 = 13u, ///< MPU region number 13 + MpuRegionNum14 = 14u, ///< MPU region number 14 + MpuRegionNum15 = 15u, ///< MPU region number 15 +} en_mpu_region_num_t; + +/** + ******************************************************************************* + ** \brief MPU region size enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_size +{ + MpuRegionSize32Byte = 4u, ///< 32 Byte + MpuRegionSize64Byte = 5u, ///< 64 Byte + MpuRegionSize128Byte = 6u, ///< 126 Byte + MpuRegionSize256Byte = 7u, ///< 256 Byte + MpuRegionSize512Byte = 8u, ///< 512 Byte + MpuRegionSize1KByte = 9u, ///< 1K Byte + MpuRegionSize2KByte = 10u, ///< 2K Byte + MpuRegionSize4KByte = 11u, ///< 4K Byte + MpuRegionSize8KByte = 12u, ///< 8K Byte + MpuRegionSize16KByte = 13u, ///< 16K Byte + MpuRegionSize32KByte = 14u, ///< 32K Byte + MpuRegionSize64KByte = 15u, ///< 64K Byte + MpuRegionSize128KByte = 16u, ///< 128K Byte + MpuRegionSize256KByte = 17u, ///< 256K Byte + MpuRegionSize512KByte = 18u, ///< 512K Byte + MpuRegionSize1MByte = 19u, ///< 1M Byte + MpuRegionSize2MByte = 20u, ///< 2M Byte + MpuRegionSize4MByte = 21u, ///< 4M Byte + MpuRegionSize8MByte = 22u, ///< 8M Byte + MpuRegionSize16MByte = 23u, ///< 16M Byte + MpuRegionSize32MByte = 24u, ///< 32M Byte + MpuRegionSize64MByte = 25u, ///< 64M Byte + MpuRegionSize128MByte = 26u, ///< 128M Byte + MpuRegionSize256MByte = 27u, ///< 256M Byte + MpuRegionSize512MByte = 28u, ///< 512M Byte + MpuRegionSize1GByte = 29u, ///< 1G Byte + MpuRegionSize2GByte = 30u, ///< 2G Byte + MpuRegionSize4GByte = 31u, ///< 4G Byte +} en_mpu_region_size_t; + +/** + ******************************************************************************* + ** \brief MPU region enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_type +{ + SMPU1Region = 0u, ///< System DMA_1 MPU + SMPU2Region = 1u, ///< System DMA_2 MPU + FMPURegion = 2u, ///< System USBFS_DMA MPU +} en_mpu_region_type_t; + +/** + ******************************************************************************* + ** \brief MPU action selection enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_action_sel +{ + MpuNoneAction = 0u, ///< MPU don't action. + MpuTrigBusError = 1u, ///< MPU trigger bus error + MpuTrigNmi = 2u, ///< MPU trigger bus NMI interrupt + MpuTrigReset = 3u, ///< MPU trigger reset +} en_mpu_action_sel_t; + +/** + ******************************************************************************* + ** \brief MPU IP protection mode enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_ip_prot_mode +{ + AesReadProt = (1ul << 0), ///< AES read protection + AesWriteProt = (1ul << 1), ///< AES write protection + HashReadProt = (1ul << 2), ///< HASH read protection + HashWriteProt = (1ul << 3), ///< HASH write protection + TrngReadProt = (1ul << 4), ///< TRNG read protection + TrngWriteProt = (1ul << 5), ///< TRNG write protection + CrcReadProt = (1ul << 6), ///< CRC read protection + CrcWriteProt = (1ul << 7), ///< CRC write protection + FmcReadProt = (1ul << 8), ///< FMC read protection + FmcWriteProt = (1ul << 9), ///< FMC write protection + WdtReadProt = (1ul << 12), ///< WDT read protection + WdtWriteProt = (1ul << 13), ///< WDT write protection + SwdtReadProt = (1ul << 14), ///< WDT read protection + SwdtWriteProt = (1ul << 15), ///< WDT write protection + BksramReadProt = (1ul << 16), ///< BKSRAM read protection + BksramWriteProt = (1ul << 17), ///< BKSRAM write protection + RtcReadProt = (1ul << 18), ///< RTC read protection + RtcWriteProt = (1ul << 19), ///< RTC write protection + DmpuReadProt = (1ul << 20), ///< DMPU read protection + DmpuWriteProt = (1ul << 21), ///< DMPU write protection + SramcReadProt = (1ul << 22), ///< SRAMC read protection + SramcWriteProt = (1ul << 23), ///< SRAMC write protection + IntcReadProt = (1ul << 24), ///< INTC read protection + IntcWriteProt = (1ul << 25), ///< INTC write protection + SyscReadProt = (1ul << 26), ///< SYSC read protection + SyscWriteProt = (1ul << 27), ///< SYSC write protection + MstpReadProt = (1ul << 28), ///< MSTP read protection + MstpWriteProt = (1ul << 29), ///< MSTP write protection + BusErrProt = (1ul << 31), ///< BUSERR write protection +} en_mpu_ip_prot_mode_t; + +/** + ******************************************************************************* + ** \brief MPU protection region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_permission +{ + en_mpu_action_sel_t enAction; ///< Specifies MPU action + + en_functional_state_t enRegionEnable; ///< Disable: Disable region protection; Enable:Enable region protection + + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read + +} stc_mpu_prot_region_permission_t; + +/** + ******************************************************************************* + ** \brief MPU background region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_permission +{ + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read +} stc_mpu_bkgd_region_permission_t_t; + +/** + ******************************************************************************* + ** \brief MPU background region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_init +{ + stc_mpu_bkgd_region_permission_t_t stcSMPU1BkgdPermission; ///< Specifies SMPU1 background permission and this stuctrue detail refer of @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcSMPU2BkgdPermission; ///< Specifies SMPU2 background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcFMPUBkgdPermission; ///< Specifies FMPU background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t +} stc_mpu_bkgd_region_init_t; + +/** + ******************************************************************************* + ** \brief MPU protect region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_init +{ + uint32_t u32RegionBaseAddress; ///< Specifies region base address + + en_mpu_region_size_t enRegionSize; ///< Specifies region size and This parameter can be a value of @ref en_mpu_region_size_t + + stc_mpu_prot_region_permission_t stcSMPU1Permission; ///< Specifies DMA1 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcSMPU2Permission; ///< Specifies DMA2 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcFMPUPermission; ///< Specifies USBFS-DMA MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t +} stc_mpu_prot_region_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg); +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg); +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize); +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr); +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel); +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_WriteProtCmd(en_functional_state_t enState); +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState); + +//@} // MpuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_ots.h b/lib/hc32f460/driver/inc/hc32f460_ots.h new file mode 100644 index 000000000000..af1b3163dd70 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_ots.h @@ -0,0 +1,134 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.h + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ +#ifndef __HC32F460_OTS_H__ +#define __HC32F460_OTS_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup OtsGroup On-chip Temperature Sensor(OTS) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Automatically turn off the analog temperature sensor after the temperature + measurement is over. */ +typedef enum en_ots_auto_off +{ + OtsAutoOff_Disable = 0x0, ///< Disable automatically turn off OTS. + OtsAutoOff_Enable = 0x1, ///< Enable automatically turn off OTS. +} en_ots_auto_off_t; + +/* Temperature measurement end interrupt request. */ +typedef enum en_ots_ie +{ + OtsInt_Disable = 0x0, ///< Disable OTS interrupt. + OtsInt_Enable = 0x1, ///< Enable OTS interrupt. +} en_ots_ie_t; + +/* OTS clock selection. */ +typedef enum en_ots_clk_sel +{ + OtsClkSel_Xtal = 0x0, ///< Select XTAL as OTS clock. + OtsClkSel_Hrc = 0x1, ///< Select HRC as OTS clock. +} en_ots_clk_sel_t; + +/* OTS OTS initialization structure definition. */ +typedef struct stc_ots_init +{ + en_ots_auto_off_t enAutoOff; ///< @ref en_ots_auto_off_t. + en_ots_clk_sel_t enClkSel; ///< @ref en_ots_clk_sel_t. + float32_t f32SlopeK; ///< K: Temperature slope (calculated by calibration experiment). */ + float32_t f32OffsetM; ///< M: Temperature offset (calculated by calibration experiment). */ +} stc_ots_init_t; + +/* OTS common trigger source select */ +typedef enum en_ots_com_trigger +{ + OtsComTrigger_1 = 0x1, ///< Select common trigger 1. + OtsComTrigger_2 = 0x2, ///< Select common trigger 2. + OtsComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_ots_com_trigger_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)1u; +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)0u; +} + +en_result_t OTS_Init(const stc_ots_init_t *pstcInit); +void OTS_DeInit(void); + +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); +void OTS_SetTriggerSrc(en_event_src_t enEvent); +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout); + +float OTS_CalculateTemp(void); + +//@} // OtsGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_pwc.h b/lib/hc32f460/driver/inc/hc32f460_pwc.h new file mode 100644 index 000000000000..eba43f353700 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_pwc.h @@ -0,0 +1,562 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.h + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ +#ifndef __HC32F460_PWC_H__ +#define __HC32F460_PWC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup PwcGroup Power Control(PWC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_powerdown_md +{ + PowerDownMd1 = 0u, ///< Power down mode 1. + PowerDownMd2 = 1u, ///< Power down mode 2. + PowerDownMd3 = 2u, ///< Power down mode 3. + PowerDownMd4 = 3u, ///< Power down mode 4. +}en_pwc_powerdown_md_t; + +/** + ******************************************************************************* + ** \brief The IO retain status under power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_iortn +{ + IoPwrDownRetain = 0u, ///< Io keep under power down mode. + IoPwrRstRetain = 1u, ///< Io keep after power reset. + IoHighImp = 2u, ///< IO high impedance either power down or power reset. +}en_pwc_iortn_t; + +/** + ******************************************************************************* + ** \brief The driver ability while different speed mode enter stop mode. + ** + ******************************************************************************/ +typedef enum en_pwc_stopdas +{ + StopHighspeed = 0u, ///< The driver ability while high speed mode enter stop mode. + StopUlowspeed = 3u, ///< The driver ability while ultra_low speed mode enter stop mode. +}en_pwc_stopdas_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver voltage select. + ** + ******************************************************************************/ +typedef enum en_pwc_rundrvs +{ + RunUHighspeed = 0u, ///< The ultra_high speed. + RunUlowspeed = 2u, ///< The ultra_low speed. + RunHighspeed = 3u, ///< The high speed. +}en_pwc_rundrvs_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver ability scaling. + ** + ******************************************************************************/ +typedef enum en_pwc_drvability_sca +{ + Ulowspeed = 8u, ///< The ultra_low speed. + HighSpeed = 15u, ///< The high speed. +}en_pwc_drvability_sca_t; + +/** + ******************************************************************************* + ** \brief The power down wake up time select. + ** + ******************************************************************************/ +typedef enum en_pwc_waketime_sel +{ + Vcap01 = 0u, ///< Wake up while vcap capacitance 2*0.1uf. + Vcap0047 = 1u, ///< Wake up while vcap capacitance 2*0.047uf. +}en_pwc_waketime_sel_t; + +/** + ******************************************************************************* + ** \brief The wait or not wait flash stable while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_flash_sel +{ + Wait = 0u, ///< wait flash stable. + NotWait = 1u, ///< Not Wait flash stable. +}en_pwc_stop_flash_sel_t; + +/** + ******************************************************************************* + ** \brief The clk value while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_clk_sel +{ + ClkFix = 0u, ///< clock fix. + ClkMrc = 1u, ///< clock source is MRC, only ram code. +}en_pwc_stop_clk_sel_t; + +/** + ******************************************************************************* + ** \brief The power down wake up event edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_edge_sel +{ + EdgeFalling = 0u, ///< Falling edge. + EdgeRising = 1u, ///< Rising edge. +}en_pwc_edge_sel_t; + +/** + ******************************************************************************* + ** \brief The voltage detect edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdedge_sel +{ + OverVcc = 0u, ///< PVD > VCC. + BelowVcc = 1u, ///< PVD < VCC. +}en_pwc_pvdedge_sel_t; + +/** + ******************************************************************************* + ** \brief The flag of wake_up timer compare result. + ** + ******************************************************************************/ +typedef enum en_pwc_wkover_flag +{ + UnEqual = 0u, ///< Timer value unequal with the wake_up compare value whitch set. + Equal = 1u, ///< Timer value equal with the wake_up compare value whitch set.. +}en_pwc_wkover_flag_t; + +/** + ******************************************************************************* + ** \brief The RAM operating mode. + ** + ******************************************************************************/ +typedef enum en_pwc_ram_op_md +{ + HighSpeedMd = 0x8043, ///< Work at high speed. + UlowSpeedMd = 0x9062, ///< Work at ultra low speed. +}en_pwc_ram_op_md_t; + +/** + ******************************************************************************* + ** \brief The wake up clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_wkclk_sel +{ + Wk64hz = 0u, ///< 64Hz. + WkXtal32 = 1u, ///< Xtal32. + WkLrc = 2u, ///< Lrc. +}en_pwc_wkclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd digital filtering sampling clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdfiltclk_sel +{ + PvdLrc025 = 0u, ///< 0.25 LRC cycle. + PvdLrc05 = 1u, ///< 0.5 LRC cycle. + PvdLrc1 = 2u, ///< LRC 1 div. + PvdLrc2 = 3u, ///< LRC 2 div. +}en_pwc_pvdfiltclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd2 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd2level_sel +{ + Pvd2Level0 = 0u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd2Level1 = 1u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd2Level2 = 2u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd2Level3 = 3u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd2Level4 = 4u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd2Level5 = 5u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd2Level6 = 6u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. + Pvd2Level7 = 7u, ///< 1.1V.while high_speed & ultra_low speed mode, 1.15V.while ultra_high speed mode. +}en_pwc_pvd2level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd1 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd1level_sel +{ + Pvd1Level0 = 0u, ///< 2.0V.while high_speed & ultra_low speed mode, 2.09V.while ultra_high speed mode. + Pvd1Level1 = 1u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd1Level2 = 2u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd1Level3 = 3u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd1Level4 = 4u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd1Level5 = 5u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd1Level6 = 6u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd1Level7 = 7u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. +}en_pwc_pvd1level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd interrupt select. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_int_sel +{ + NonMskInt = 0u, ///< Non-maskable Interrupt. + MskInt = 1u, ///< Maskable Interrupt. +}en_pwc_pvd_int_sel_t; + +/** + ******************************************************************************* + ** \brief The handle of pvd mode. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_md +{ + PvdInt = 0u, ///< The handle of pvd is interrupt. + PvdReset = 1u, ///< The handle of pvd is reset. +}en_pwc_pvd_md_t; + +/** + ******************************************************************************* + ** \brief The unit of pvd detect. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd +{ + PvdU1 = 0u, ///< The uint1 of pvd detect. + PvdU2 = 1u, ///< The unit2 of pvd detect. +}en_pwc_pvd_t; + +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pwr_mode_cfg +{ + en_pwc_powerdown_md_t enPwrDownMd; ///< Power down mode. + en_functional_state_t enRLdo; ///< Enable or disable RLDO. + en_functional_state_t enRetSram; ///< Enable or disable Ret_Sram. + en_pwc_iortn_t enIoRetain; ///< IO retain. + en_pwc_waketime_sel_t enPwrDWkupTm; ///< The power down wake up time select. +}stc_pwc_pwr_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_stop_mode_cfg +{ + en_pwc_stopdas_t enStpDrvAbi; ///< Driver ability while enter stop mode. + en_pwc_stop_flash_sel_t enStopFlash; ///< Flash mode while stop mode awake. + en_pwc_stop_clk_sel_t enStopClk; ///< Clock value while stop mode awake. + en_functional_state_t enPll; ///< Whether the PLL enable or disable while enter stop mode. +}stc_pwc_stop_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up timer control. + ** + ******************************************************************************/ +typedef struct stc_pwc_wktm_ctl +{ + uint16_t u16WktmCmp; ///< The wake_up timer compare value. + en_pwc_wkover_flag_t enWkOverFlag; ///< The flag of compare result. + en_pwc_wkclk_sel_t enWkclk; ///< The clock of wake_up timer. + en_functional_state_t enWktmEn; ///< Enable or disable wake_up timer. +}stc_pwc_wktm_ctl_t; + +/** + ******************************************************************************* + ** \brief The pvd control. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_ctl +{ + en_functional_state_t enPvdIREn; ///< Enable or disable pvd interrupt(reset). + en_pwc_pvd_md_t enPvdMode; ///< The handle of pvd is interrupt or reset. + en_functional_state_t enPvdCmpOutEn; ///< Enable or disable pvd output compare result . +}stc_pwc_pvd_ctl_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up event configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_cfg +{ + stc_pwc_pvd_ctl_t stcPvd1Ctl; ///< Pvd1 control configuration. + stc_pwc_pvd_ctl_t stcPvd2Ctl; ///< Pvd2 control configuration. + en_functional_state_t enPvd1FilterEn; ///< Pvd1 filtering enable or disable. + en_functional_state_t enPvd2FilterEn; ///< Pvd2 filtering enable or disable. + en_pwc_pvdfiltclk_sel_t enPvd1Filtclk; ///< Pvd1 filtering sampling clock. + en_pwc_pvdfiltclk_sel_t enPvd2Filtclk; ///< Pvd2 filtering sampling clock. + en_pwc_pvd1level_sel_t enPvd1Level; ///< Pvd1 voltage. + en_pwc_pvd2level_sel_t enPvd2Level; ///< Pvd2 voltage. + en_pwc_pvd_int_sel_t enPvd1Int; ///< Pvd1 interrupt. + en_pwc_pvd_int_sel_t enPvd2Int; ///< Pvd2 interrupt. +}stc_pwc_pvd_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define PWC_PDWKEN0_WKUP00 ((uint8_t)0x01) +#define PWC_PDWKEN0_WKUP01 ((uint8_t)0x02) +#define PWC_PDWKEN0_WKUP02 ((uint8_t)0x04) +#define PWC_PDWKEN0_WKUP03 ((uint8_t)0x08) +#define PWC_PDWKEN0_WKUP10 ((uint8_t)0x10) +#define PWC_PDWKEN0_WKUP11 ((uint8_t)0x20) +#define PWC_PDWKEN0_WKUP12 ((uint8_t)0x40) +#define PWC_PDWKEN0_WKUP13 ((uint8_t)0x80) + +#define PWC_PDWKEN1_WKUP20 ((uint8_t)0x01) +#define PWC_PDWKEN1_WKUP21 ((uint8_t)0x02) +#define PWC_PDWKEN1_WKUP22 ((uint8_t)0x04) +#define PWC_PDWKEN1_WKUP23 ((uint8_t)0x08) +#define PWC_PDWKEN1_WKUP30 ((uint8_t)0x10) +#define PWC_PDWKEN1_WKUP31 ((uint8_t)0x20) +#define PWC_PDWKEN1_WKUP32 ((uint8_t)0x40) +#define PWC_PDWKEN1_WKUP33 ((uint8_t)0x80) + +#define PWC_PDWKEN2_PVD1 ((uint8_t)0x01) +#define PWC_PDWKEN2_PVD2 ((uint8_t)0x02) +#define PWC_PDWKEN2_NMI ((uint8_t)0x04) +#define PWC_PDWKEN2_RTCPRD ((uint8_t)0x10) +#define PWC_PDWKEN2_RTCAL ((uint8_t)0x20) +#define PWC_PDWKEN2_WKTM ((uint8_t)0x80) + +#define PWC_PDWKUP_EDGE_WKP0 ((uint8_t)0x01) +#define PWC_PDWKUP_EDGE_WKP1 ((uint8_t)0x02) +#define PWC_PDWKUP_EDGE_WKP2 ((uint8_t)0x04) +#define PWC_PDWKUP_EDGE_WKP3 ((uint8_t)0x08) +#define PWC_PDWKUP_EDGE_PVD1 ((uint8_t)0x10) +#define PWC_PDWKUP_EDGE_PVD2 ((uint8_t)0x20) +#define PWC_PDWKUP_EDGE_NMI ((uint8_t)0x40) + +#define PWC_RAMPWRDOWN_SRAM1 ((uint32_t)0x00000001) +#define PWC_RAMPWRDOWN_SRAM2 ((uint32_t)0x00000002) +#define PWC_RAMPWRDOWN_SRAM3 ((uint32_t)0x00000004) +#define PWC_RAMPWRDOWN_SRAMH ((uint32_t)0x00000008) +#define PWC_RAMPWRDOWN_USBFS ((uint32_t)0x00000010) +#define PWC_RAMPWRDOWN_SDIOC0 ((uint32_t)0x00000020) +#define PWC_RAMPWRDOWN_SDIOC1 ((uint32_t)0x00000040) +#define PWC_RAMPWRDOWN_CAN ((uint32_t)0x00000080) +#define PWC_RAMPWRDOWN_CACHE ((uint32_t)0x00000100) +#define PWC_RAMPWRDOWN_FULL ((uint32_t)0x000001FF) + +#define PWC_STOPWKUPEN_EIRQ0 ((uint32_t)0x00000001) +#define PWC_STOPWKUPEN_EIRQ1 ((uint32_t)0x00000002) +#define PWC_STOPWKUPEN_EIRQ2 ((uint32_t)0x00000004) +#define PWC_STOPWKUPEN_EIRQ3 ((uint32_t)0x00000008) +#define PWC_STOPWKUPEN_EIRQ4 ((uint32_t)0x00000010) +#define PWC_STOPWKUPEN_EIRQ5 ((uint32_t)0x00000020) +#define PWC_STOPWKUPEN_EIRQ6 ((uint32_t)0x00000040) +#define PWC_STOPWKUPEN_EIRQ7 ((uint32_t)0x00000080) +#define PWC_STOPWKUPEN_EIRQ8 ((uint32_t)0x00000100) +#define PWC_STOPWKUPEN_EIRQ9 ((uint32_t)0x00000200) +#define PWC_STOPWKUPEN_EIRQ10 ((uint32_t)0x00000400) +#define PWC_STOPWKUPEN_EIRQ11 ((uint32_t)0x00000800) +#define PWC_STOPWKUPEN_EIRQ12 ((uint32_t)0x00001000) +#define PWC_STOPWKUPEN_EIRQ13 ((uint32_t)0x00002000) +#define PWC_STOPWKUPEN_EIRQ14 ((uint32_t)0x00004000) +#define PWC_STOPWKUPEN_EIRQ15 ((uint32_t)0x00008000) +#define PWC_STOPWKUPEN_SWDT ((uint32_t)0x00010000) +#define PWC_STOPWKUPEN_VDU1 ((uint32_t)0x00020000) +#define PWC_STOPWKUPEN_VDU2 ((uint32_t)0x00040000) +#define PWC_STOPWKUPEN_CMPI0 ((uint32_t)0x00080000) +#define PWC_STOPWKUPEN_WKTM ((uint32_t)0x00100000) +#define PWC_STOPWKUPEN_RTCAL ((uint32_t)0x00200000) +#define PWC_STOPWKUPEN_RTCPRD ((uint32_t)0x00400000) +#define PWC_STOPWKUPEN_TMR0 ((uint32_t)0x00800000) +#define PWC_STOPWKUPEN_USARTRXD ((uint32_t)0x02000000) + +#define PWC_PTWK0_WKUPFLAG ((uint8_t)0x01) +#define PWC_PTWK1_WKUPFLAG ((uint8_t)0x02) +#define PWC_PTWK2_WKUPFLAG ((uint8_t)0x04) +#define PWC_PTWK3_WKUPFLAG ((uint8_t)0x08) +#define PWC_PVD1_WKUPFLAG ((uint8_t)0x10) +#define PWC_PVD2_WKUPFLAG ((uint8_t)0x20) +#define PWC_NMI_WKUPFLAG ((uint8_t)0x40) + +#define PWC_RTCPRD_WKUPFALG ((uint8_t)0x10) +#define PWC_RTCAL_WKUPFLAG ((uint8_t)0x20) +#define PWC_WKTM_WKUPFLAG ((uint8_t)0x80) + +#define PWC_WKTMCMP_MSK ((uint16_t)0x0FFF) + +#define PWC_FCG0_PERIPH_SRAMH ((uint32_t)0x00000001) +#define PWC_FCG0_PERIPH_SRAM12 ((uint32_t)0x00000010) +#define PWC_FCG0_PERIPH_SRAM3 ((uint32_t)0x00000100) +#define PWC_FCG0_PERIPH_SRAMRET ((uint32_t)0x00000400) +#define PWC_FCG0_PERIPH_DMA1 ((uint32_t)0x00004000) +#define PWC_FCG0_PERIPH_DMA2 ((uint32_t)0x00008000) +#define PWC_FCG0_PERIPH_FCM ((uint32_t)0x00010000) +#define PWC_FCG0_PERIPH_AOS ((uint32_t)0x00020000) +#define PWC_FCG0_PERIPH_AES ((uint32_t)0x00100000) +#define PWC_FCG0_PERIPH_HASH ((uint32_t)0x00200000) +#define PWC_FCG0_PERIPH_TRNG ((uint32_t)0x00400000) +#define PWC_FCG0_PERIPH_CRC ((uint32_t)0x00800000) +#define PWC_FCG0_PERIPH_DCU1 ((uint32_t)0x01000000) +#define PWC_FCG0_PERIPH_DCU2 ((uint32_t)0x02000000) +#define PWC_FCG0_PERIPH_DCU3 ((uint32_t)0x04000000) +#define PWC_FCG0_PERIPH_DCU4 ((uint32_t)0x08000000) +#define PWC_FCG0_PERIPH_KEY ((uint32_t)0x80000000) + + +#define PWC_FCG1_PERIPH_CAN ((uint32_t)0x00000001) +#define PWC_FCG1_PERIPH_QSPI ((uint32_t)0x00000008) +#define PWC_FCG1_PERIPH_I2C1 ((uint32_t)0x00000010) +#define PWC_FCG1_PERIPH_I2C2 ((uint32_t)0x00000020) +#define PWC_FCG1_PERIPH_I2C3 ((uint32_t)0x00000040) +#define PWC_FCG1_PERIPH_USBFS ((uint32_t)0x00000100) +#define PWC_FCG1_PERIPH_SDIOC1 ((uint32_t)0x00000400) +#define PWC_FCG1_PERIPH_SDIOC2 ((uint32_t)0x00000800) +#define PWC_FCG1_PERIPH_I2S1 ((uint32_t)0x00001000) +#define PWC_FCG1_PERIPH_I2S2 ((uint32_t)0x00002000) +#define PWC_FCG1_PERIPH_I2S3 ((uint32_t)0x00004000) +#define PWC_FCG1_PERIPH_I2S4 ((uint32_t)0x00008000) +#define PWC_FCG1_PERIPH_SPI1 ((uint32_t)0x00010000) +#define PWC_FCG1_PERIPH_SPI2 ((uint32_t)0x00020000) +#define PWC_FCG1_PERIPH_SPI3 ((uint32_t)0x00040000) +#define PWC_FCG1_PERIPH_SPI4 ((uint32_t)0x00080000) +#define PWC_FCG1_PERIPH_USART1 ((uint32_t)0x01000000) +#define PWC_FCG1_PERIPH_USART2 ((uint32_t)0x02000000) +#define PWC_FCG1_PERIPH_USART3 ((uint32_t)0x04000000) +#define PWC_FCG1_PERIPH_USART4 ((uint32_t)0x08000000) + +#define PWC_FCG2_PERIPH_TIM01 ((uint32_t)0x00000001) +#define PWC_FCG2_PERIPH_TIM02 ((uint32_t)0x00000002) +#define PWC_FCG2_PERIPH_TIMA1 ((uint32_t)0x00000004) +#define PWC_FCG2_PERIPH_TIMA2 ((uint32_t)0x00000008) +#define PWC_FCG2_PERIPH_TIMA3 ((uint32_t)0x00000010) +#define PWC_FCG2_PERIPH_TIMA4 ((uint32_t)0x00000020) +#define PWC_FCG2_PERIPH_TIMA5 ((uint32_t)0x00000040) +#define PWC_FCG2_PERIPH_TIMA6 ((uint32_t)0x00000080) +#define PWC_FCG2_PERIPH_TIM41 ((uint32_t)0x00000100) +#define PWC_FCG2_PERIPH_TIM42 ((uint32_t)0x00000200) +#define PWC_FCG2_PERIPH_TIM43 ((uint32_t)0x00000400) +#define PWC_FCG2_PERIPH_EMB ((uint32_t)0x00008000) +#define PWC_FCG2_PERIPH_TIM61 ((uint32_t)0x00010000) +#define PWC_FCG2_PERIPH_TIM62 ((uint32_t)0x00020000) +#define PWC_FCG2_PERIPH_TIM63 ((uint32_t)0x00040000) + +#define PWC_FCG3_PERIPH_ADC1 ((uint32_t)0x00000001) +#define PWC_FCG3_PERIPH_ADC2 ((uint32_t)0x00000002) +#define PWC_FCG3_PERIPH_CMP ((uint32_t)0x00000100) +#define PWC_FCG3_PERIPH_OTS ((uint32_t)0x00001000) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg); +void PWC_EnterPowerDownMd(void); + +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState); +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState); +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge); + +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag); +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag); +void PWC_PwrMonitorCmd(en_functional_state_t enNewState); + +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg); +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); + +void PWC_EnterStopMd(void); +void PWC_EnterSleepMd(void); + +void PWC_Xtal32CsCmd(en_functional_state_t enNewState); +void PWC_HrcPwrCmd(en_functional_state_t enNewState); +void PWC_PllPwrCmd(en_functional_state_t enNewState); +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState); +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd); + +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl); + +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg); +void PWC_Pvd1Cmd(en_functional_state_t enNewState); +void PWC_Pvd2Cmd(en_functional_state_t enNewState); +void PWC_ExVccCmd(en_functional_state_t enNewState); +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd); + +void PWC_enNvicBackup(void); +void PWC_enNvicRecover(void); +void PWC_ClkBackup(void); +void PWC_ClkRecover(void); +void PWC_IrqClkBackup(void); +void PWC_IrqClkRecover(void); + +en_result_t PWC_HS2LS(void); +en_result_t PWC_LS2HS(void); +en_result_t PWC_HS2HP(void); +en_result_t PWC_HP2HS(void); +en_result_t PWC_LS2HP(void); +en_result_t PWC_HP2LS(void); + +//@} // PwcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_qspi.h b/lib/hc32f460/driver/inc/hc32f460_qspi.h new file mode 100644 index 000000000000..a4cef3611d3b --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_qspi.h @@ -0,0 +1,397 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.h + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ +#ifndef __HC32F460_QSPI_H__ +#define __HC32F460_QSPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup QspiGroup Queued SPI(QSPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief QSPI spi protocol enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_protocol +{ + QspiProtocolExtendSpi = 0u, ///< Extend spi protocol + QspiProtocolTwoWiresSpi = 1u, ///< Two wires spi protocol + QspiProtocolFourWiresSpi = 2u, ///< Four wires spi protocol +} en_qspi_spi_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI spi Mode enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_mode +{ + QspiSpiMode0 = 0u, ///< Spi mode 0(QSCK normalcy is Low level) + QspiSpiMode3 = 1u, ///< Spi mode 3(QSCK normalcy is High level) +} en_qspi_spi_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI bus communication mode enumeration + ******************************************************************************/ +typedef enum en_qspi_bus_mode +{ + QspiBusModeRomAccess = 0u, ///< Rom access mode + QspiBusModeDirectAccess = 1u, ///< Direct communication mode +} en_qspi_bus_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI prefetch data stop config enumeration + ******************************************************************************/ +typedef enum en_qspi_prefetch_config +{ + QspiPrefetchStopComplete = 0u, ///< Stop after prefetch data complete + QspiPrefetchStopImmediately = 1u, ///< Immediately stop prefetch +} en_qspi_prefetch_config_t; + +/** + ******************************************************************************* + ** \brief QSPI read mode enumeration + ******************************************************************************/ +typedef enum en_qspi_read_mode +{ + QspiReadModeStandard = 0u, ///< Standard read + QspiReadModeFast = 1u, ///< Fast read + QspiReadModeTwoWiresOutput = 2u, ///< Two wires output fast read + QspiReadModeTwoWiresIO = 3u, ///< Two wires input/output fast read + QspiReadModeFourWiresOutput = 4u, ///< Four wires output fast read + QspiReadModeFourWiresIO = 5u, ///< Four wires input/output fast read + QspiReadModeCustomStandard = 6u, ///< Custom standard read + QspiReadModeCustomFast = 7u, ///< Custom fast read +} en_qspi_read_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN valid extend time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_valid_extend_time +{ + QspiQssnValidExtendNot = 0u, ///< Don't extend QSSN valid time + QspiQssnValidExtendSck32 = 1u, ///< QSSN valid time extend 32 QSCK cycles + QspiQssnValidExtendSck128 = 2u, ///< QSSN valid time extend 138 QSCK cycles + QspiQssnValidExtendSckEver = 3u, ///< QSSN valid time extend to ever +} en_qspi_qssn_valid_extend_time_t; + +/** + ******************************************************************************* + ** \brief QSPI QSCK duty cycle correction enumeration + ******************************************************************************/ +typedef enum en_qspi_qsck_duty_correction +{ + QspiQsckDutyCorrNot = 0u, ///< Don't correction duty cycle + QspiQsckDutyCorrHalfHclk = 1u, ///< QSCK's rising edge delay 0.5 HCLK cycle when Qsck select HCLK is odd +} en_qspi_qsck_duty_correction_t; + +/** + ******************************************************************************* + ** \brief QSPI WP Pin output level enumeration + ******************************************************************************/ +typedef enum en_qspi_wp_pin_level +{ + QspiWpPinOutputLow = 0u, ///< WP pin(QIO2) output low level + QspiWpPinOutputHigh = 1u, ///< WP pin(QIO2) output high level +} en_qspi_wp_pin_level_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN setup delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_setup_delay +{ + QspiQssnSetupDelayHalfQsck = 0u, ///< QSSN setup delay 0.5 QSCK output than QSCK first rising edge + QspiQssnSetupDelay1Dot5Qsck = 1u, ///< QSSN setup delay 1.5 QSCK output than QSCK first rising edge +} en_qspi_qssn_setup_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN hold delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_hold_delay +{ + QspiQssnHoldDelayHalfQsck = 0u, ///< QSSN hold delay 0.5 QSCK release than QSCK last rising edge + QspiQssnHoldDelay1Dot5Qsck = 1u, ///< QSSN hold delay 1.5 QSCK release than QSCK last rising edge +} en_qspi_qssn_hold_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI address width enumeration + ******************************************************************************/ +typedef enum en_qspi_addr_width +{ + QspiAddressByteOne = 0u, ///< One byte address + QspiAddressByteTwo = 1u, ///< Two byte address + QspiAddressByteThree = 2u, ///< Three byte address + QspiAddressByteFour = 3u, ///< Four byte address +} en_qspi_addr_width_t; + +/** + ******************************************************************************* + ** \brief QSPI flag type enumeration + ******************************************************************************/ +typedef enum en_qspi_flag_type +{ + QspiFlagBusBusy = 0u, ///< QSPI bus work status flag in direct communication mode + QspiFlagXipMode = 1u, ///< XIP mode status signal + QspiFlagRomAccessError = 2u, ///< Trigger rom access error flag in direct communication mode + QspiFlagPrefetchBufferFull = 3u, ///< Prefetch buffer area status signal + QspiFlagPrefetchStop = 4u, ///< Prefetch action status signal +} en_qspi_flag_type_t; + +/** + ******************************************************************************* + ** \brief QSPI clock division enumeration + ******************************************************************************/ +typedef enum en_qspi_clk_div +{ + QspiHclkDiv2 = 0u, ///< Clock source: HCLK/2 + QspiHclkDiv3 = 2u, ///< Clock source: HCLK/3 + QspiHclkDiv4 = 3u, ///< Clock source: HCLK/4 + QspiHclkDiv5 = 4u, ///< Clock source: HCLK/5 + QspiHclkDiv6 = 5u, ///< Clock source: HCLK/6 + QspiHclkDiv7 = 6u, ///< Clock source: HCLK/7 + QspiHclkDiv8 = 7u, ///< Clock source: HCLK/8 + QspiHclkDiv9 = 8u, ///< Clock source: HCLK/9 + QspiHclkDiv10 = 9u, ///< Clock source: HCLK/10 + QspiHclkDiv11 = 10u, ///< Clock source: HCLK/11 + QspiHclkDiv12 = 11u, ///< Clock source: HCLK/12 + QspiHclkDiv13 = 12u, ///< Clock source: HCLK/13 + QspiHclkDiv14 = 13u, ///< Clock source: HCLK/14 + QspiHclkDiv15 = 14u, ///< Clock source: HCLK/15 + QspiHclkDiv16 = 15u, ///< Clock source: HCLK/16 + QspiHclkDiv17 = 16u, ///< Clock source: HCLK/17 + QspiHclkDiv18 = 17u, ///< Clock source: HCLK/18 + QspiHclkDiv19 = 18u, ///< Clock source: HCLK/19 + QspiHclkDiv20 = 19u, ///< Clock source: HCLK/20 + QspiHclkDiv21 = 20u, ///< Clock source: HCLK/21 + QspiHclkDiv22 = 21u, ///< Clock source: HCLK/22 + QspiHclkDiv23 = 22u, ///< Clock source: HCLK/23 + QspiHclkDiv24 = 23u, ///< Clock source: HCLK/24 + QspiHclkDiv25 = 24u, ///< Clock source: HCLK/25 + QspiHclkDiv26 = 25u, ///< Clock source: HCLK/26 + QspiHclkDiv27 = 26u, ///< Clock source: HCLK/27 + QspiHclkDiv28 = 27u, ///< Clock source: HCLK/28 + QspiHclkDiv29 = 28u, ///< Clock source: HCLK/29 + QspiHclkDiv30 = 29u, ///< Clock source: HCLK/30 + QspiHclkDiv31 = 30u, ///< Clock source: HCLK/31 + QspiHclkDiv32 = 31u, ///< Clock source: HCLK/32 + QspiHclkDiv33 = 32u, ///< Clock source: HCLK/33 + QspiHclkDiv34 = 33u, ///< Clock source: HCLK/34 + QspiHclkDiv35 = 34u, ///< Clock source: HCLK/35 + QspiHclkDiv36 = 35u, ///< Clock source: HCLK/36 + QspiHclkDiv37 = 36u, ///< Clock source: HCLK/37 + QspiHclkDiv38 = 37u, ///< Clock source: HCLK/38 + QspiHclkDiv39 = 38u, ///< Clock source: HCLK/39 + QspiHclkDiv40 = 39u, ///< Clock source: HCLK/40 + QspiHclkDiv41 = 40u, ///< Clock source: HCLK/41 + QspiHclkDiv42 = 41u, ///< Clock source: HCLK/42 + QspiHclkDiv43 = 42u, ///< Clock source: HCLK/43 + QspiHclkDiv44 = 43u, ///< Clock source: HCLK/44 + QspiHclkDiv45 = 44u, ///< Clock source: HCLK/45 + QspiHclkDiv46 = 45u, ///< Clock source: HCLK/46 + QspiHclkDiv47 = 46u, ///< Clock source: HCLK/47 + QspiHclkDiv48 = 47u, ///< Clock source: HCLK/48 + QspiHclkDiv49 = 48u, ///< Clock source: HCLK/49 + QspiHclkDiv50 = 49u, ///< Clock source: HCLK/50 + QspiHclkDiv51 = 50u, ///< Clock source: HCLK/51 + QspiHclkDiv52 = 51u, ///< Clock source: HCLK/52 + QspiHclkDiv53 = 52u, ///< Clock source: HCLK/53 + QspiHclkDiv54 = 53u, ///< Clock source: HCLK/54 + QspiHclkDiv55 = 54u, ///< Clock source: HCLK/55 + QspiHclkDiv56 = 55u, ///< Clock source: HCLK/56 + QspiHclkDiv57 = 56u, ///< Clock source: HCLK/57 + QspiHclkDiv58 = 57u, ///< Clock source: HCLK/58 + QspiHclkDiv59 = 58u, ///< Clock source: HCLK/59 + QspiHclkDiv60 = 59u, ///< Clock source: HCLK/60 + QspiHclkDiv61 = 60u, ///< Clock source: HCLK/61 + QspiHclkDiv62 = 61u, ///< Clock source: HCLK/62 + QspiHclkDiv63 = 62u, ///< Clock source: HCLK/63 + QspiHclkDiv64 = 63u, ///< Clock source: HCLK/64 +} en_qspi_clk_div_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN minimum interval time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_interval_time +{ + QspiQssnIntervalQsck1 = 0u, ///< QSSN signal min interval time 1 QSCK + QspiQssnIntervalQsck2 = 1u, ///< QSSN signal min interval time 2 QSCK + QspiQssnIntervalQsck3 = 2u, ///< QSSN signal min interval time 3 QSCK + QspiQssnIntervalQsck4 = 3u, ///< QSSN signal min interval time 4 QSCK + QspiQssnIntervalQsck5 = 4u, ///< QSSN signal min interval time 5 QSCK + QspiQssnIntervalQsck6 = 5u, ///< QSSN signal min interval time 6 QSCK + QspiQssnIntervalQsck7 = 6u, ///< QSSN signal min interval time 7 QSCK + QspiQssnIntervalQsck8 = 7u, ///< QSSN signal min interval time 8 QSCK + QspiQssnIntervalQsck9 = 8u, ///< QSSN signal min interval time 9 QSCK + QspiQssnIntervalQsck10 = 9u, ///< QSSN signal min interval time 10 QSCK + QspiQssnIntervalQsck11 = 10u, ///< QSSN signal min interval time 11 QSCK + QspiQssnIntervalQsck12 = 11u, ///< QSSN signal min interval time 12 QSCK + QspiQssnIntervalQsck13 = 12u, ///< QSSN signal min interval time 13 QSCK + QspiQssnIntervalQsck14 = 13u, ///< QSSN signal min interval time 14 QSCK + QspiQssnIntervalQsck15 = 14u, ///< QSSN signal min interval time 15 QSCK + QspiQssnIntervalQsck16 = 15u, ///< QSSN signal min interval time 16 QSCK +} en_qspi_qssn_interval_time_t; + +/** + ******************************************************************************* + ** \brief QSPI virtual period enumeration + ******************************************************************************/ +typedef enum en_qspi_virtual_period +{ + QspiVirtualPeriodQsck3 = 0u, ///< Virtual period select 3 QSCK + QspiVirtualPeriodQsck4 = 1u, ///< Virtual period select 4 QSCK + QspiVirtualPeriodQsck5 = 2u, ///< Virtual period select 5 QSCK + QspiVirtualPeriodQsck6 = 3u, ///< Virtual period select 6 QSCK + QspiVirtualPeriodQsck7 = 4u, ///< Virtual period select 7 QSCK + QspiVirtualPeriodQsck8 = 5u, ///< Virtual period select 8 QSCK + QspiVirtualPeriodQsck9 = 6u, ///< Virtual period select 9 QSCK + QspiVirtualPeriodQsck10 = 7u, ///< Virtual period select 10 QSCK + QspiVirtualPeriodQsck11 = 8u, ///< Virtual period select 11 QSCK + QspiVirtualPeriodQsck12 = 9u, ///< Virtual period select 12 QSCK + QspiVirtualPeriodQsck13 = 10u, ///< Virtual period select 13 QSCK + QspiVirtualPeriodQsck14 = 11u, ///< Virtual period select 14 QSCK + QspiVirtualPeriodQsck15 = 12u, ///< Virtual period select 15 QSCK + QspiVirtualPeriodQsck16 = 13u, ///< Virtual period select 16 QSCK + QspiVirtualPeriodQsck17 = 14u, ///< Virtual period select 17 QSCK + QspiVirtualPeriodQsck18 = 15u, ///< Virtual period select 18 QSCK +} en_qspi_virtual_period_t; + +/** + ******************************************************************************* + ** \brief QSPI communication protocol structure definition + ******************************************************************************/ +typedef struct stc_qspi_comm_protocol +{ + en_qspi_spi_protocol_t enReceProtocol; ///< Receive data stage SPI protocol + en_qspi_spi_protocol_t enTransAddrProtocol; ///< Transmit address stage SPI protocol + en_qspi_spi_protocol_t enTransInstrProtocol; ///< Transmit instruction stage SPI protocol + en_qspi_read_mode_t enReadMode; ///< Serial interface read mode +} stc_qspi_comm_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI init structure definition + ******************************************************************************/ +typedef struct stc_qspi_init +{ + en_qspi_clk_div_t enClkDiv; ///< Clock division + en_qspi_spi_mode_t enSpiMode; ///< Specifies SPI mode + en_qspi_bus_mode_t enBusCommMode; ///< Bus communication mode + en_qspi_prefetch_config_t enPrefetchMode; ///< Config prefetch stop location + en_functional_state_t enPrefetchFuncEn; ///< Disable: disable prefetch function, Enable: enable prefetch function + stc_qspi_comm_protocol_t stcCommProtocol; ///< Qspi communication protocol config + en_qspi_qssn_valid_extend_time_t enQssnValidExtendTime; ///< QSSN valid extend time function select after QSPI access bus + en_qspi_qssn_interval_time_t enQssnIntervalTime; ///< QSSN minimum interval time + en_qspi_qsck_duty_correction_t enQsckDutyCorr; ///< QSCK output duty cycles correction + en_qspi_virtual_period_t enVirtualPeriod; ///< Virtual period config + en_qspi_wp_pin_level_t enWpPinLevel; ///< WP pin(QIO2) level select + en_qspi_qssn_setup_delay_t enQssnSetupDelayTime; ///< QSSN setup delay time choose + en_qspi_qssn_hold_delay_t enQssnHoldDelayTime; ///< QSSN hold delay time choose + en_functional_state_t enFourByteAddrReadEn; ///< Read instruction code select when set address width is four bytes + en_qspi_addr_width_t enAddrWidth; ///< Serial interface address width choose + uint8_t u8RomAccessInstr; ///< Rom access mode instruction +} stc_qspi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< 4-byte instruction mode using instruction set */ +#define QSPI_4BINSTR_STANDARD_READ 0x13u +#define QSPI_4BINSTR_FAST_READ 0x0Cu +#define QSPI_4BINSTR_TWO_WIRES_OUTPUT_READ 0x3Cu +#define QSPI_4BINSTR_TWO_WIRES_IO_READ 0xBCu +#define QSPI_4BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Cu +#define QSPI_4BINSTR_FOUR_WIRES_IO_READ 0xECu +#define QSPI_4BINSTR_EXIT_4BINSTR_MODE 0xB7u + +/*!< 3-byte instruction mode using instruction set */ +#define QSPI_3BINSTR_STANDARD_READ 0x03u +#define QSPI_3BINSTR_FAST_READ 0x0Bu +#define QSPI_3BINSTR_TWO_WIRES_OUTPUT_READ 0x3Bu +#define QSPI_3BINSTR_TWO_WIRES_IO_READ 0xBBu +#define QSPI_3BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Bu +#define QSPI_3BINSTR_FOUR_WIRES_IO_READ 0xEBu +#define QSPI_3BINSTR_ENTER_4BINSTR_MODE 0xE9u + +/*!< General instruction set */ +#define QSPI_WRITE_MODE_ENABLE 0x06u + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t QSPI_DeInit(void); +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg); +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth); +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr); +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol); +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta); +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv); +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel); + +/* Rom access mode functions */ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr); +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta); + +/* Direct communication mode functions */ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val); +uint8_t QSPI_ReadDirectCommValue(void); +en_result_t QSPI_EnterDirectCommMode(void); +en_result_t QSPI_ExitDirectCommMode(void); + +/* Flags and get buffer functions */ +uint8_t QSPI_GetPrefetchBufferNum(void); +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag); +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag); + +//@} // QspiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_rmu.h b/lib/hc32f460/driver/inc/hc32f460_rmu.h new file mode 100644 index 000000000000..0bba03ca8a41 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_rmu.h @@ -0,0 +1,91 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.h + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU + ** + ******************************************************************************/ +#ifndef __HC32F460_RMU_H__ +#define __HC32F460_RMU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RmuGroup Reset Management Unit(RMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief system reset cause flag + ** + ******************************************************************************/ +typedef struct stc_rmu_rstcause +{ + en_flag_status_t enMultiRst; ///< Multiply reset cause + en_flag_status_t enXtalErr; ///< Xtal error reset + en_flag_status_t enClkFreqErr; ///< Clk freqence error reset + en_flag_status_t enRamEcc; ///< Ram ECC reset + en_flag_status_t enRamParityErr; ///< Ram parity error reset + en_flag_status_t enMpuErr; ///< Mpu error reset + en_flag_status_t enSoftware; ///< Software reset + en_flag_status_t enPowerDown; ///< Power down reset + en_flag_status_t enSwdt; ///< Special watchdog timer reset + en_flag_status_t enWdt; ///< Watchdog timer reset + en_flag_status_t enPvd2; ///< Program voltage Dectection 2 reset + en_flag_status_t enPvd1; ///< Program voltage Dectection 1 reset + en_flag_status_t enBrownOut; ///< Brown out reset + en_flag_status_t enRstPin; ///< Reset pin reset + en_flag_status_t enPowerOn; ///< Power on reset +}stc_rmu_rstcause_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData); +en_result_t RMU_ClrResetFlag(void); + +//@} // RmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/lib/hc32f460/driver/inc/hc32f460_rtc.h b/lib/hc32f460/driver/inc/hc32f460_rtc.h new file mode 100644 index 000000000000..8047e49d1206 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_rtc.h @@ -0,0 +1,269 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.h + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ +#ifndef __HC32F460_RTC_H__ +#define __HC32F460_RTC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RtcGroup Real-Time Clock(RTC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief RTC period interrupt type enumeration + ******************************************************************************/ +typedef enum en_rtc_period_int_type +{ + RtcPeriodIntInvalid = 0u, ///< Period interrupt invalid + RtcPeriodIntHalfSec = 1u, ///< 0.5 second period interrupt + RtcPeriodIntOneSec = 2u, ///< 1 second period interrupt + RtcPeriodIntOneMin = 3u, ///< 1 minute period interrupt + RtcPeriodIntOneHour = 4u, ///< 1 hour period interrupt + RtcPeriodIntOneDay = 5u, ///< 1 day period interrupt + RtcPeriodIntOneMon = 6u ///< 1 month period interrupt +} en_rtc_period_int_type_t; + +/** + ******************************************************************************* + ** \brief RTC time format enumeration + ******************************************************************************/ +typedef enum en_rtc_time_format +{ + RtcTimeFormat12Hour = 0u, ///< 12 hours mode + RtcTimeFormat24Hour = 1u, ///< 24 hours mode +} en_rtc_time_format_t; + +/** + ******************************************************************************* + ** \brief RTC 1Hz output compensation way enumeration + ******************************************************************************/ +typedef enum en_rtc_output_compen +{ + RtcOutputCompenDistributed = 0u, ///< Distributed compensation 1hz output + RtcOutputCompenUniform = 1u, ///< Uniform Compensation 1hz output +} en_rtc_output_compen_t; + +/** + ******************************************************************************* + ** \brief RTC work mode enumeration + ******************************************************************************/ +typedef enum en_rtc_work_mode +{ + RtcModeNormalCount = 0u, ///< Normal count mode + RtcModeReadOrWrite = 1u, ///< Read or write mode +} en_rtc_work_mode_t; + +/** + ******************************************************************************* + ** \brief RTC count clock source enumeration + ******************************************************************************/ +typedef enum en_rtc_clk_source +{ + RtcClkXtal32 = 0u, ///< XTAL32 as clock source + RtcClkLrc = 1u, ///< LRC as clock source +} en_rtc_clk_source_t; + +/** + ******************************************************************************* + ** \brief RTC data format enumeration + ******************************************************************************/ +typedef enum en_rtc_data_format +{ + RtcDataFormatDec = 0u, ///< Decimal format + RtcDataFormatBcd = 1u, ///< BCD format +} en_rtc_data_format_t; + +/** + ******************************************************************************* + ** \brief RTC 12 hour AM/PM enumeration + ******************************************************************************/ +typedef enum en_rtc_hour12_ampm +{ + RtcHour12Am = 0u, ///< Ante meridiem + RtcHour12Pm = 1u, ///< Post meridiem +} en_rtc_hour12_ampm_t; + +/** + ******************************************************************************* + ** \brief RTC month enumeration + ******************************************************************************/ +typedef enum en_rtc_month +{ + RtcMonthJanuary = 1u, ///< January + RtcMonthFebruary = 2u, ///< February + RtcMonthMarch = 3u, ///< March + RtcMonthApril = 4u, ///< April + RtcMonthMay = 5u, ///< May + RtcMonthJune = 6u, ///< June + RtcMonthJuly = 7u, ///< July + RtcMonthAugust = 8u, ///< August + RtcMonthSeptember = 9u, ///< September + RtcMonthOctober = 10u, ///< October + RtcMonthNovember = 11u, ///< November + RtcMonthDecember = 12u, ///< December +} en_rtc_month_t; + +/** + ******************************************************************************* + ** \brief RTC weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_weekday +{ + RtcWeekdaySunday = 0u, ///< Sunday + RtcWeekdayMonday = 1u, ///< Monday + RtcWeekdayTuesday = 2u, ///< Tuesday + RtcWeekdayWednesday = 3u, ///< Wednesday + RtcWeekdayThursday = 4u, ///< Thursday + RtcWeekdayFriday = 5u, ///< Friday + RtcWeekdaySaturday = 6u ///< Saturday +} en_rtc_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC alarm weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_alarm_weekday +{ + RtcAlarmWeekdaySunday = 0x01u, ///< Sunday + RtcAlarmWeekdayMonday = 0x02u, ///< Monday + RtcAlarmWeekdayTuesday = 0x04u, ///< Tuesday + RtcAlarmWeekdayWednesday = 0x08u, ///< Wednesday + RtcAlarmWeekdayThursday = 0x10u, ///< Thursday + RtcAlarmWeekdayFriday = 0x20u, ///< Friday + RtcAlarmWeekdaySaturday = 0x40u, ///< Saturday +} en_rtc_alarm_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC interrupt request type enumeration + ******************************************************************************/ +typedef enum en_rtc_irq_type_ +{ + RtcIrqPeriod = 0u, ///< Period count interrupt request + RtcIrqAlarm = 1u, ///< Alarm interrupt request +} en_rtc_irq_type_t; + +/** + ******************************************************************************* + ** \brief RTC date and time structure definition + ******************************************************************************/ +typedef struct stc_rtc_date_time +{ + uint8_t u8Year; ///< Year (range 0-99) + uint8_t u8Month; ///< Month (range 1-12) + uint8_t u8Day; ///< Day (range 1-31) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Second; ///< Seconds (range 0-59) + uint8_t u8Weekday; ///< Weekday (range 0-6) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_date_time_t; + +/** + ******************************************************************************* + ** \brief RTC alarm time structure definition + ******************************************************************************/ +typedef struct stc_rtc_alarm_time +{ + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Weekday; ///< Weekday (range RtcAlarmWeekdaySunday to RtcAlarmWeekdaySaturday) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_alarm_time_t; + +/** + ******************************************************************************* + ** \brief RTC init structure definition + ******************************************************************************/ +typedef struct stc_rtc_init +{ + en_rtc_clk_source_t enClkSource; ///< Clock source + en_rtc_period_int_type_t enPeriodInt; ///< Period interrupt condition + en_rtc_time_format_t enTimeFormat; ///< RTC time format + en_rtc_output_compen_t enCompenWay; ///< 1HZ output compensation way + uint16_t u16CompenVal; ///< Clock error compensation value + en_functional_state_t enCompenEn; ///< Enable/Disable clock error compensation +} stc_rtc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t RTC_DeInit(void); +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +en_result_t RTC_Cmd(en_functional_state_t enNewSta); +en_result_t RTC_EnterRwMode(void); +en_result_t RTC_ExitRwMode(void); + +/* Extend functions */ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType); +en_result_t RTC_LowPowerSwitch(void); +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal); +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta); +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta); + +/* Date and time functions */ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn); +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime); + +/* Alarm functions */ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta); + +/* Interrupt and flags management functions ******************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta); +en_flag_status_t RTC_GetAlarmFlag(void); +en_result_t RTC_ClearAlarmFlag(void); + +//@} // RtcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_sdioc.h b/lib/hc32f460/driver/inc/hc32f460_sdioc.h new file mode 100644 index 000000000000..5a1b3cc29dd9 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_sdioc.h @@ -0,0 +1,554 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.h + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ +#ifndef __HC32F460_SDIOC_H__ +#define __HC32F460_SDIOC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SDIOC mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_mode +{ + SdiocModeSD = 0u, ///< The SD mode + SdiocModeMMC = 1u, ///< The MMC mode +} en_sdioc_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC transfer bus width enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_bus_width +{ + SdiocBusWidth4Bit = 0u, ///< The SDIOC bus width 4 bit + SdiocBusWidth8Bit = 1u, ///< The SDIOC bus width 8 bit + SdiocBusWidth1Bit = 2u, ///< The SDIOC bus width 1 bit +} en_sdioc_bus_width_t; + +/** + ******************************************************************************* + ** \brief SDIOC clock division enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_div +{ + SdiocClkDiv_1 = 0x00u, ///< EXCLK/1 + SdiocClkDiv_2 = 0x01u, ///< EXCLK/2 + SdiocClkDiv_4 = 0x02u, ///< EXCLK/4 + SdiocClkDiv_8 = 0x04u, ///< EXCLK/8 + SdiocClkDiv_16 = 0x08u, ///< EXCLK/16 + SdiocClkDiv_32 = 0x10u, ///< EXCLK/32 + SdiocClkDiv_64 = 0x20u, ///< EXCLK/64 + SdiocClkDiv_128 = 0x40u, ///< EXCLK/128 + SdiocClkDiv_256 = 0x80u, ///< EXCLK/256 +} en_sdioc_clk_div_t; + +/** + ******************************************************************************* + ** \brief SDIOC response type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_type +{ + SdiocResponseNoneBit = 0u, ///< No Response + SdiocResponse136Bit = 1u, ///< Response Length 136 + SdiocResponse48Bit = 2u, ///< Response Length 48 + SdiocResponse48BitCheckBusy = 3u, ///< Response Length 48 check Busy after response +} en_sdioc_response_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC response index enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_index +{ + SdiocCmdNoRsp = 0u, ///< No Response + SdiocCmdRspR1 = 1u, ///< Command Response 1 + SdiocCmdRspR1b = 2u, ///< Command Response 1 with busy + SdiocCmdRspR2 = 3u, ///< Command Response 2 + SdiocCmdRspR3 = 4u, ///< Command Response 3 + SdiocCmdRspR4 = 5u, ///< Command Response 4 + SdiocCmdRspR5 = 6u, ///< Command Response 5 + SdiocCmdRspR5b = 7u, ///< Command Response 5 with busy + SdiocCmdRspR6 = 8u, ///< Command Response 6 + SdiocCmdRspR7 = 9u, ///< Command Response 7 +} en_sdioc_response_index_t; + +/** + ******************************************************************************* + ** \brief SDIOC command type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_cmd_type +{ + SdiocCmdNormal = 0u, ///< Other commands + SdiocCmdSuspend = 1u, ///< CMD52 for writing "Bus Suspend" in CCCR + SdiocCmdResume = 2u, ///< CMD52 for writing "Function Select" in CCCR + SdiocCmdAbort = 3u, ///< CMD12, CMD52 for writing "I/O Abort" in CCCR +} en_sdioc_cmd_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_dir +{ + SdiocTransferToCard = 0u, ///< Write (Host to Card) + SdiocTransferToHost = 1u, ///< Read (Card to Host) +} en_sdioc_transfer_dir_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_mode +{ + SdiocTransferSingle = 0u, ///< Single Block transfer + SdiocTransferInfinite = 1u, ///< Infinite Block transfer + SdiocTransferMultiple = 2u, ///< Multiple Block transfer + SdiocTransferStopMultiple = 3u, ///< Stop Multiple Block transfer +} en_sdioc_transfer_mode_t; + +/** + ******************************************************************************* + ** \brief SD data timeout time enumeration + ** + ******************************************************************************/ +typedef enum en_sd_data_timeout +{ + SdiocDtoSdclk_2_13 = 0u, ///< Timeout time: SDCLK*2^13 + SdiocDtoSdclk_2_14 = 1u, ///< Timeout time: SDCLK*2^14 + SdiocDtoSdclk_2_15 = 2u, ///< Timeout time: SDCLK*2^15 + SdiocDtoSdclk_2_16 = 3u, ///< Timeout time: SDCLK*2^16 + SdiocDtoSdclk_2_17 = 4u, ///< Timeout time: SDCLK*2^17 + SdiocDtoSdclk_2_18 = 5u, ///< Timeout time: SDCLK*2^18 + SdiocDtoSdclk_2_19 = 6u, ///< Timeout time: SDCLK*2^19 + SdiocDtoSdclk_2_20 = 7u, ///< Timeout time: SDCLK*2^20 + SdiocDtoSdclk_2_21 = 8u, ///< Timeout time: SDCLK*2^21 + SdiocDtoSdclk_2_22 = 9u, ///< Timeout time: SDCLK*2^22 + SdiocDtoSdclk_2_23 = 10u, ///< Timeout time: SDCLK*2^23 + SdiocDtoSdclk_2_24 = 11u, ///< Timeout time: SDCLK*2^24 + SdiocDtoSdclk_2_25 = 12u, ///< Timeout time: SDCLK*2^25 + SdiocDtoSdclk_2_26 = 13u, ///< Timeout time: SDCLK*2^26 + SdiocDtoSdclk_2_27 = 14u, ///< Timeout time: SDCLK*2^27 +} en_sdioc_data_timeout_t; + +/** + ******************************************************************************* + ** \brief SDIOC dat line type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_dat_line_type +{ + SdiocDat0Line = 0u, ///< DAT0 Line + SdiocDat1Line = 1u, ///< DAT1 Line + SdiocDat2Line = 2u, ///< DAT2 Line + SdiocDat3Line = 3u, ///< DAT3 Line +} en_sdioc_dat_line_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC software reset type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_sw_reset +{ + SdiocSwResetDatLine = 0u, ///< Only part of data circuit is reset. + SdiocSwResetCmdLine = 1u, ///< Only part of command circuit is reset. + SdiocSwResetAll = 2u, ///< Reset the entire Host Controller except for the card detection circuit. +} en_sdioc_sw_reset_t; + +/** + ******************************************************************************* + ** \brief SDIOC host status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_host_status +{ + SdiocCommandInhibitCmd = (1u << 0), ///< Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + SdiocCommandInhibitData = (1u << 1), ///< Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + SdiocDataLineActive = (1u << 2), ///< 1: DAT Line Active; 0: DAT Line Inactive + SdiocWriteTransferActive = (1u << 8), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocReadTransferActive = (1u << 9), ///< Read Transfer Active.1: Transferring data; 0: No valid data + SdiocBufferWriteEnble = (1u << 10), ///< 1: Write enable; 0: Write Disable + SdiocBufferReadEnble = (1u << 11), ///< 1: Read enable; 0: Read Disable + SdiocCardInserted = (1u << 16), ///< 1: Card Inserted; 0: Reset or Debouncing or No Card + SdiocCardStateStable = (1u << 17), ///< 1: No Card or Inserted; 0: Reset or Debouncing + SdiocCardDetectPinLvl = (1u << 18), ///< 1: Card present; 0: No card present + SdiocWriteProtectPinLvl = (1u << 19), ///< 1: Write enabled; 0: Write protected + SdiocData0PinLvl = (1u << 20), ///< 1: DAT0 line signal level high; 0: DAT0 line signal level low + SdiocData1PinLvl = (1u << 21), ///< 1: DAT1 line signal level high; 0: DAT1 line signal level low + SdiocData2PinLvl = (1u << 22), ///< 1: DAT2 line signal level high; 0: DAT2 line signal level low + SdiocData3PinLvl = (1u << 23), ///< 1: DAT3 line signal level high; 0: DAT3 line signal level low + SdiocCmdPinLvl = (1u << 24), ///< 1: CMD line signal level high; 0: CMD line signal level low +} en_sdioc_host_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_nor_int_sel +{ + SdiocCommandComplete = (1u << 0), ///< Command Complete. 1: Command complete; 0:No command complete + SdiocTransferComplete = (1u << 1), ///< Transfer Complete. 1: Data transfer complete; 0:No transfer complete + SdiocBlockGapEvent = (1u << 2), ///< Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + SdiocBufferWriteReady = (1u << 4), ///< Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + SdiocBufferReadReady = (1u << 5), ///< Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + SdiocCardInsertedInt = (1u << 6), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocCardRemoval = (1u << 7), ///< Card Removal. 1: Card removed; 0: Card state stable or Debouncing + SdiocCardInt = (1u << 8), ///< Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + SdiocErrorInt = (1u << 15), ///< Error Interrupt. 1: Error; 0: No Error +} en_sdioc_nor_int_sel_t, en_sdioc_nor_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC error interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_err_int_sel +{ + SdiocCmdTimeoutErr = (1u << 0), ///< Command Timeout Error. 1: Timer out; 0:No Error + SdiocCmdCrcErr = (1u << 1), ///< Command CRC Error. 1: Command CRC Error Generated; 0:No Error + SdiocCmdEndBitErr = (1u << 2), ///< Command End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocCmdIndexErr = (1u << 3), ///< Command Index Error. 1: Command Index Error Generatedr; 0:No Error + SdiocDataTimeoutErr = (1u << 4), ///< Data Timeout Error. 1: Timer out; 0:No Error + SdiocDataCrcErr = (1u << 5), ///< Data CRC Error. 1: Data CRC Error Generated; 0:No Error + SdiocDataEndBitErr = (1u << 6), ///< Data End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocAutoCmd12Err = (1u << 8), ///< Auto CMD12 Error. 1: Error; 0:No Error +} en_sdioc_err_int_sel_t, en_sdioc_err_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC auto CMD12 error status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_atuo_cmd_err_status +{ + SdiocAutoCmd12NotExecuted = (1u << 0), ///< Auto CMD12 Not Executed. 1: Not executed; 0:Executed + SdiocAutoCmd12Timeout = (1u << 1), ///< Auto CMD12 Timeout Error. 1: Time out; 0:No error + SdiocAutoCmd12CrcErr = (1u << 2), ///< Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + SdiocAutoCmd12EndBitErr = (1u << 3), ///< Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + SdiocAutoCmd12IndexErr = (1u << 4), ///< Auto CMD12 Index Error. 1: Error; 0: No error + SdiocCmdNotIssuedErr = (1u << 7), ///< Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error +} en_sdioc_atuo_cmd_err_sel_t, en_sdioc_atuo_cmd_err_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC speed mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_speed_mode +{ + SdiocNormalSpeedMode = 0u, ///< Normal speed mode + SdiocHighSpeedMode = 1u, ///< High speed mode +} en_sdioc_speed_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC response register enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_reg +{ + SdiocRegResp01 = 0x00u, ///< Response 0/1 Register + SdiocRegResp23 = 0x04u, ///< Response 2/3 Register + SdiocRegResp45 = 0x08u, ///< Response 4/5 Register + SdiocRegResp67 = 0x0Cu, ///< Response 5/6 Register +} en_sdioc_response_reg_t; + +/** + ****************************************************************************** + ** \brief SDIOC output clock frequency enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_freq +{ + SdiocClk400K = 400000u, ///< SDIOC clock: 40KHz + SdiocClk20M = 20000000u, ///< SDIOC clock: 20MHz + SdiocClk25M = 25000000u, ///< SDIOC clock: 25MHz + SdiocClk40M = 40000000u, ///< SDIOC clock: 40MHz + SdiocClk50M = 50000000u, ///< SDIOC clock: 50MHz +} en_sdioc_clk_freq_t; + +/** + ****************************************************************************** + ** \brief SDIOC detect the source of card enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_detect_signal +{ + SdiocSdcdPinLevel = 0u, ///< SDCD# is selected (for normal use) + SdiocCardDetectTestLevel = 1u, ///< The Card Detect Test Level is selected(for test purpose) +} en_sdioc_detect_signal_t; + +/** + ******************************************************************************* + ** \brief SDIOC Command configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_cmd_cfg +{ + uint8_t u8CmdIndex; ///< Command index + + uint32_t u32Argument; ///< The argument of command + + en_sdioc_cmd_type_t enCmdType; ///< Command type + + en_sdioc_response_index_t enRspIndex; ///< Response index, refer @ref en_sdioc_response_index_t for details + + en_functional_state_t enDataPresentEnable; ///< Enable: Data is present and shall be transferred using the DAT line, Disable: Commands using only CMD line +} stc_sdioc_cmd_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC Data configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_data_cfg +{ + uint16_t u16BlkSize; ///< Block size + + uint16_t u16BlkCnt; ///< Block count + + en_functional_state_t enAutoCmd12Enable; ///< Enable: Auto CMD12 enable, Disable: Auto CMD12 disable + + en_sdioc_transfer_dir_t enTransferDir; ///< Specifies the data transfer direction of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_dir_t. + + en_sdioc_data_timeout_t enDataTimeOut; ///< Specifies the data timeout period in card bus clock periods. + ///< This parameter can be a value of @ref en_sdioc_data_timeout_t. + + en_sdioc_transfer_mode_t enTransferMode; ///< Specifies the data transfer mode of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_mode_t. +} stc_sdioc_data_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_en +{ + union + { + uint16_t u16NormalIntsgEn; ///< SDIOC normal interrupt enable + stc_sdioc_errintsgen_field_t stcNormalIntsgEn; ///< SDIOC normal interrupt enable bit-field structure + }; +} stc_sdioc_normal_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_en +{ + union + { + uint16_t u16ErrorIntsgEn; ///< SDIOC error interrupt enable + stc_sdioc_errintsgen_field_t stcErrorIntsgEn; ///< SDIOC error interrupt enable bit-field structure + }; +} stc_sdioc_error_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_cb +{ + func_ptr_t pfnCommandCompleteIrqCb; ///< Pointer to command complete callback function + + func_ptr_t pfnTransferCompleteIrqCb; ///< Pointer to transfer complete callback function + + func_ptr_t pfnBlockGapIrqCb; ///< Pointer to Block gap callback function + + func_ptr_t pfnBufferWriteReadyIrqCb; ///< Pointer to buffer write ready callback function + + func_ptr_t pfnBufferReadReadyIrqCb; ///< Pointer to buffer read ready callback function + + func_ptr_t pfnCardInsertIrqCb; ///< Pointer to card insertion callback function + + func_ptr_t pfnCardRemovalIrqCb; ///< Pointer to card removal callback function + + func_ptr_t pfnCardIrqCb; ///< Pointer to card interrupt callback function +} stc_sdioc_normal_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_cb +{ + func_ptr_t pfnCmdTimeoutErrIrqCb; ///< Pointer to command timeout error interrupt callback function + + func_ptr_t pfnCmdCrcErrIrqCb; ///< Pointer to command CRC error interrupt callback function + + func_ptr_t pfnCmdEndBitErrIrqCb; ///< Pointer to command end bit error interrupt callback function + + func_ptr_t pfnCmdIndexErrIrqCb; ///< Pointer to command index error interrupt callback function + + func_ptr_t pfnDataTimeoutErrIrqCb; ///< Pointer to data timeout error interrupt callback function + + func_ptr_t pfnDataCrcErrIrqCb; ///< Pointer to data CRC error interrupt callback function + + func_ptr_t pfnDataEndBitErrIrqCb; ///< Pointer to data end bit error interrupt callback function + + func_ptr_t pfnAutoCmdErrIrqCb; ///< Pointer to command error interrupt callback function +} stc_sdioc_error_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC initialization configuration + ** + ******************************************************************************/ +typedef struct stc_sdioc_init +{ + stc_sdioc_normal_irq_en_t *pstcNormalIrqEn; ///< Pointer to normal interrupt enable structure + + stc_sdioc_normal_irq_cb_t *pstcNormalIrqCb; ///< Pointer to normal interrupt callback function structure + + stc_sdioc_error_irq_en_t *pstcErrorIrqEn; ///< Pointer to error interrupt enable structure + + stc_sdioc_error_irq_cb_t *pstcErrorIrqCb; ///< Pointer to error interrupt callback structure +} stc_sdioc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg); +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode); +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg); +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg); +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg); +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv); +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq); +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth); +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode); +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout); +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal); +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType); +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus); +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt); +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr); +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr); + +//@} // SdiocGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_spi.h b/lib/hc32f460/driver/inc/hc32f460_spi.h new file mode 100644 index 000000000000..b7e57d7f1e4b --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_spi.h @@ -0,0 +1,421 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.h + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ +#ifndef __HC32F460_SPI_H__ +#define __HC32F460_SPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SpiGroup Serial Peripheral Interface(SPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SPI parity enumeration + ******************************************************************************/ +typedef enum en_spi_parity +{ + SpiParityEven = 0u, ///< Select even parity send and receive + SpiParityOdd = 1u, ///< Select odd parity send and receive +} en_spi_parity_t; + +/** + ******************************************************************************* + ** \brief SPI master/slave mode enumeration + ******************************************************************************/ +typedef enum en_spi_master_slave_mode +{ + SpiModeSlave = 0u, ///< Spi slave mode + SpiModeMaster = 1u, ///< Spi master mode +} en_spi_master_slave_mode_t; + +/** + ******************************************************************************* + ** \brief SPI transmission mode enumeration + ******************************************************************************/ +typedef enum en_spi_trans_mode +{ + SpiTransFullDuplex = 0u, ///< Full duplex sync serial communication + SpiTransOnlySend = 1u, ///< Only send serial communication +} en_spi_trans_mode_t; + +/** + ******************************************************************************* + ** \brief SPI work mode enumeration + ******************************************************************************/ +typedef enum en_spi_work_mode +{ + SpiWorkMode4Line = 0u, ///< 4 lines spi work mode + SpiWorkMode3Line = 1u, ///< 3 lines spi work mode(clock sync running) +} en_spi_work_mode_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time +{ + SpiSsIntervalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalSck2PlusPck2 = 1u, ///< Spi SS interval time 2 SCK plus 2 PCLK1 + SpiSsIntervalSck3PlusPck2 = 2u, ///< Spi SS interval time 3 SCK plus 2 PCLK1 + SpiSsIntervalSck4PlusPck2 = 3u, ///< Spi SS interval time 4 SCK plus 2 PCLK1 + SpiSsIntervalSck5PlusPck2 = 4u, ///< Spi SS interval time 5 SCK plus 2 PCLK1 + SpiSsIntervalSck6PlusPck2 = 5u, ///< Spi SS interval time 6 SCK plus 2 PCLK1 + SpiSsIntervalSck7PlusPck2 = 6u, ///< Spi SS interval time 7 SCK plus 2 PCLK1 + SpiSsIntervalSck8PlusPck2 = 7u, ///< Spi SS interval time 8 SCK plus 2 PCLK1 +} en_spi_ss_interval_time_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay +{ + SpiSsSetupDelaySck1 = 0u, ///< Spi SS setup delay 1 SCK + SpiSsSetupDelaySck2 = 1u, ///< Spi SS setup delay 2 SCK + SpiSsSetupDelaySck3 = 2u, ///< Spi SS setup delay 3 SCK + SpiSsSetupDelaySck4 = 3u, ///< Spi SS setup delay 4 SCK + SpiSsSetupDelaySck5 = 4u, ///< Spi SS setup delay 5 SCK + SpiSsSetupDelaySck6 = 5u, ///< Spi SS setup delay 6 SCK + SpiSsSetupDelaySck7 = 6u, ///< Spi SS setup delay 7 SCK + SpiSsSetupDelaySck8 = 7u, ///< Spi SS setup delay 8 SCK +} en_spi_ss_setup_delay_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay +{ + SpiSsHoldDelaySck1 = 0u, ///< Spi SS hold delay 1 SCK + SpiSsHoldDelaySck2 = 1u, ///< Spi SS hold delay 2 SCK + SpiSsHoldDelaySck3 = 2u, ///< Spi SS hold delay 3 SCK + SpiSsHoldDelaySck4 = 3u, ///< Spi SS hold delay 4 SCK + SpiSsHoldDelaySck5 = 4u, ///< Spi SS hold delay 5 SCK + SpiSsHoldDelaySck6 = 5u, ///< Spi SS hold delay 6 SCK + SpiSsHoldDelaySck7 = 6u, ///< Spi SS hold delay 7 SCK + SpiSsHoldDelaySck8 = 7u, ///< Spi SS hold delay 8 SCK +} en_spi_ss_hold_delay_t; + +/** + ******************************************************************************* + ** \brief SPI slave select polarity enumeration + ******************************************************************************/ +typedef enum en_spi_ss_polarity +{ + SpiSsLowValid = 0u, ///< SS0~3 signal low level valid + SpiSsHighValid = 1u, ///< SS0~3 signal high level valid +} en_spi_ss_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI data register read object enumeration + ******************************************************************************/ +typedef enum en_spi_read_object +{ + SpiReadReceiverBuffer = 0u, ///< Read receive buffer + SpiReadSendBuffer = 1u, ///< Read send buffer(must be read when TDEF=1) +} en_spi_read_object_t; + +/** + ******************************************************************************* + ** \brief SPI frame number enumeration + ******************************************************************************/ +typedef enum en_spi_frame_number +{ + SpiFrameNumber1 = 0u, ///< 1 frame data + SpiFrameNumber2 = 1u, ///< 2 frame data + SpiFrameNumber3 = 2u, ///< 3 frame data + SpiFrameNumber4 = 3u, ///< 4 frame data +} en_spi_frame_number_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay_option +{ + SpiSsSetupDelayTypicalSck1 = 0u, ///< SS setup delay 1 SCK + SpiSsSetupDelayCustomValue = 1u, ///< SS setup delay SCKDL register set value +} en_spi_ss_setup_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay_option +{ + SpiSsHoldDelayTypicalSck1 = 0u, ///< SS hold delay 1 SCK + SpiSsHoldDelayCustomValue = 1u, ///< SS hold delay SSDL register set value +} en_spi_ss_hold_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time_option +{ + SpiSsIntervalTypicalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalCustomValue = 1u, ///< Spi SS interval time NXTDL register set value +} en_spi_ss_interval_time_option_t; + +/** + ******************************************************************************* + ** \brief SPI first bit position enumeration + ******************************************************************************/ +typedef enum en_spi_first_bit_position +{ + SpiFirstBitPositionMSB = 0u, ///< Spi first bit to MSB + SpiFirstBitPositionLSB = 1u, ///< Spi first bit to LSB +} en_spi_first_bit_position_t; + +/** + ******************************************************************************* + ** \brief SPI data length enumeration + ******************************************************************************/ +typedef enum en_spi_data_length +{ + SpiDataLengthBit4 = 0u, ///< 4 bits + SpiDataLengthBit5 = 1u, ///< 5 bits + SpiDataLengthBit6 = 2u, ///< 6 bits + SpiDataLengthBit7 = 3u, ///< 7 bits + SpiDataLengthBit8 = 4u, ///< 8 bits + SpiDataLengthBit9 = 5u, ///< 9 bits + SpiDataLengthBit10 = 6u, ///< 10 bits + SpiDataLengthBit11 = 7u, ///< 11 bits + SpiDataLengthBit12 = 8u, ///< 12 bits + SpiDataLengthBit13 = 9u, ///< 13 bits + SpiDataLengthBit14 = 10u, ///< 14 bits + SpiDataLengthBit15 = 11u, ///< 15 bits + SpiDataLengthBit16 = 12u, ///< 16 bits + SpiDataLengthBit20 = 13u, ///< 20 bits + SpiDataLengthBit24 = 14u, ///< 24 bits + SpiDataLengthBit32 = 15u, ///< 32 bits +} en_spi_data_length_t; + +/** + ******************************************************************************* + ** \brief SPI SS valid channel select enumeration + ******************************************************************************/ +typedef enum en_spi_ss_valid_channel +{ + SpiSsValidChannel0 = 0u, ///< Select SS0 valid + SpiSsValidChannel1 = 1u, ///< Select SS1 valid + SpiSsValidChannel2 = 2u, ///< Select SS2 valid + SpiSsValidChannel3 = 3u, ///< Select SS3 valid +} en_spi_ss_valid_channel_t; + +/** + ******************************************************************************* + ** \brief SPI clock division enumeration + ******************************************************************************/ +typedef enum en_spi_clk_div +{ + SpiClkDiv2 = 0u, ///< Spi pclk1 division 2 + SpiClkDiv4 = 1u, ///< Spi pclk1 division 4 + SpiClkDiv8 = 2u, ///< Spi pclk1 division 8 + SpiClkDiv16 = 3u, ///< Spi pclk1 division 16 + SpiClkDiv32 = 4u, ///< Spi pclk1 division 32 + SpiClkDiv64 = 5u, ///< Spi pclk1 division 64 + SpiClkDiv128 = 6u, ///< Spi pclk1 division 128 + SpiClkDiv256 = 7u, ///< Spi pclk1 division 256 +} en_spi_clk_div_t; + +/** + ******************************************************************************* + ** \brief SPI SCK polarity enumeration + ******************************************************************************/ +typedef enum en_spi_sck_polarity +{ + SpiSckIdleLevelLow = 0u, ///< SCK is low level when SCK idle + SpiSckIdleLevelHigh = 1u, ///< SCK is high level when SCK idle +} en_spi_sck_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI SCK phase enumeration + ******************************************************************************/ +typedef enum en_spi_sck_phase +{ + SpiSckOddSampleEvenChange = 0u, ///< SCK Odd edge data sample,even edge data change + SpiSckOddChangeEvenSample = 1u, ///< SCK Odd edge data change,even edge data sample +} en_spi_sck_phase_t; + +/** + ******************************************************************************* + ** \brief SPI interrupt request type enumeration + ******************************************************************************/ +typedef enum en_spi_irq_type +{ + SpiIrqIdle = 0u, ///< Spi idle interrupt request + SpiIrqReceive = 1u, ///< Spi receive interrupt request + SpiIrqSend = 2u, ///< Spi send interrupt request + SpiIrqError = 3u, ///< Spi error interrupt request +} en_spi_irq_type_t; + +/** + ******************************************************************************* + ** \brief SPI flag type enumeration + ******************************************************************************/ +typedef enum en_spi_flag_type +{ + SpiFlagReceiveBufferFull = 0u, ///< Receive buffer full flag + SpiFlagSendBufferEmpty = 1u, ///< Send buffer empty flag + SpiFlagUnderloadError = 2u, ///< Underload error flag + SpiFlagParityError = 3u, ///< Parity error flag + SpiFlagModeFaultError = 4u, ///< Mode fault error flag + SpiFlagSpiIdle = 5u, ///< SPI idle flag + SpiFlagOverloadError = 6u, ///< Overload error flag +} en_spi_flag_type_t; + +/** + ******************************************************************************* + ** \brief SPI SS channel enumeration + ******************************************************************************/ +typedef enum en_spi_ss_channel +{ + SpiSsChannel0 = 0u, ///< SS0 channel + SpiSsChannel1 = 1u, ///< SS1 channel + SpiSsChannel2 = 2u, ///< SS2 channel + SpiSsChannel3 = 3u, ///< SS3 channel +} en_spi_ss_channel_t; + +/** + ******************************************************************************* + ** \brief SPI bus delay structure definition + ** + ** \note Slave mode stc_spi_delay_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_delay_config +{ + en_spi_ss_setup_delay_option_t enSsSetupDelayOption; ///< SS setup delay time option + en_spi_ss_setup_delay_t enSsSetupDelayTime; ///< SS setup delay time(the value valid when enSsSetupDelayOption is custom) + en_spi_ss_hold_delay_option_t enSsHoldDelayOption; ///< SS hold delay time option + en_spi_ss_hold_delay_t enSsHoldDelayTime; ///< SS hold delay time(the value valid when enSsHoldDelayOption is custom) + en_spi_ss_interval_time_option_t enSsIntervalTimeOption; ///< SS interval time option + en_spi_ss_interval_time_t enSsIntervalTime; ///< SS interval time(the value valid when enSsIntervalTimeOption is custom) +} stc_spi_delay_config_t; + +/** + ******************************************************************************* + ** \brief SPI SS config structure definition + ** + ** \note 3 lines mode stc_spi_ss_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_ss_config +{ + en_spi_ss_valid_channel_t enSsValidBit; ///< SS valid channel select + en_spi_ss_polarity_t enSs0Polarity; ///< SS0 signal polarity + en_spi_ss_polarity_t enSs1Polarity; ///< SS1 signal polarity + en_spi_ss_polarity_t enSs2Polarity; ///< SS2 signal polarity + en_spi_ss_polarity_t enSs3Polarity; ///< SS3 signal polarity +} stc_spi_ss_config_t; + +/** + ******************************************************************************* + ** \brief SPI init structure definition + ******************************************************************************/ +typedef struct stc_spi_init_t +{ + stc_spi_delay_config_t stcDelayConfig; ///< SPI delay structure(Slave mode is invalid) + stc_spi_ss_config_t stcSsConfig; ///< SS polarity and channel structure(3 lines mode invalid) + en_spi_read_object_t enReadBufferObject; ///< Data register read object select(must be read when TDEF=1) + en_spi_sck_polarity_t enSckPolarity; ///< Sck polarity + en_spi_sck_phase_t enSckPhase; ///< Sck phase(This value must be SpiSckOddChangeEvenSample in 3-line mode) + en_spi_clk_div_t enClkDiv; ///< SPI clock division + en_spi_data_length_t enDataLength; ///< Data length + en_spi_first_bit_position_t enFirstBitPosition; ///< Data first bit position + en_spi_frame_number_t enFrameNumber; ///< Data frame number + en_spi_work_mode_t enWorkMode; ///< Spi work mode + en_spi_trans_mode_t enTransMode; ///< transmission mode + en_spi_master_slave_mode_t enMasterSlaveMode; ///< Spi master/slave mode + en_functional_state_t enCommAutoSuspendEn; ///< Enable/disable Communication auto suspend + en_functional_state_t enModeFaultErrorDetectEn; ///< Enable/disable Mode fault error detect + en_functional_state_t enParitySelfDetectEn; ///< Enable/disable Parity self detect + en_functional_state_t enParityEn; ///< Enable/disable Parity(if enable parity and SPI_CR1.TXMDS=1, receive data don't parity) + en_spi_parity_t enParity; ///< Parity mode select +} stc_spi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx); +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg); +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); + +/* Send and receive data functions */ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data); +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data); +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data); +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx); +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx); +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx); + +/* Communication configure functions */ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity); +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel); +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject); +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum); +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength); +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition); +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv); + +/* Interrupt and flags functions */ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); + +//@} // SpiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_sram.h b/lib/hc32f460/driver/inc/hc32f460_sram.h new file mode 100644 index 000000000000..41750a132dc8 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_sram.h @@ -0,0 +1,186 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.h + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +#ifndef __HC32F460_SRAM_H__ +#define __HC32F460_SRAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup SramGroup Internal SRAM + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +///< SRAM wait cycle register, parity/ECC check register protect code definition +#define SRAM_PROTECT_CODE (0x0000003Bu) + +/******************************************************************************* + Start addr. End addr. Size Function + SRAM1 0x20000000 0x2000FFFF 64KB Even Parity Check + SRAM2 0x20010000 0x2001FFFF 64KB Even Parity Check + SRAM3 0x20020000 0x20026FFF 28KB ECC Check + SRAM_Ret 0x200F0000 0x200F0FFF 4KB Even Parity Check + SRAM_HS 0x1FFF8000 0x1FFFFFFF 32KB Even Parity Check + ******************************************************************************/ +///< SRAM1 base address definition +#define SRAM1_BASE_ADDR (*((volatile unsigned int*)(0x20000000UL))) + +///< SRAM2 base address definition +#define SRAM2_BASE_ADDR (*((volatile unsigned int*)(0x20010000UL))) + +///< SRAM3 base address definition +#define SRAM3_BASE_ADDR (*((volatile unsigned int*)(0x20020000UL))) + +///< Retention SRAM base address definition +#define SRAMRET_BASE_ADDR (*((volatile unsigned int*)(0x200F0000UL))) + +///< High speed SRAM base address definition +#define SRAMHS_BASE_ADDR (*((volatile unsigned int*)(0x1FFF8000UL))) + + +typedef enum en_sram_index +{ + Sram12Idx = 1u << 0, + Sram3Idx = 1u << 1, + SramHsIdx = 1u << 2, + SramRetIdx = 1u << 3, +}en_sram_index_t; +/** + ******************************************************************************* + ** \brief Enumeration to the write/read cycles of SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_rw_cycle +{ + SramCycle1 = 0u, + SramCycle2 = 1u, + SramCycle3 = 2u, + SramCycle4 = 3u, + SramCycle5 = 4u, + SramCycle6 = 5u, + SramCycle7 = 6u, + SramCycle8 = 7u, +}en_sram_rw_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to ECC check mode + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_mode +{ + EccMode0 = 0u, ///< disable ECC check function + EccMode1 = 1u, ///< no 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode2 = 2u, ///< generate 1 bit ECC flag, but no interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode3 = 3u, ///< generate 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected +}en_ecc_mode_t; + +/** + ******************************************************************************* + ** \brief Enumeration to operation after ECC/Parity error + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_py_err_op +{ + SramNmi = 0u, ///< Generate NMI after ECC/Parity error detected + SramReset = 1u, ///< Generate Reset after ECC/Parity error detected +}en_ecc_py_err_op_t; + +/** + ******************************************************************************* + ** \brief Enumeration to the ECC/Parity error status of each SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_err_status +{ + Sram3EccErr1 = 1u << 0, ///< SRAM3 1 bit ECC error + Sram3EccErr2 = 1u << 1, ///< SRAM3 2 bit ECC error + Sram12ParityErr = 1u << 2, ///< SRAM1/2 parity error + SramHSParityErr = 1u << 3, ///< High speed SRAM parity error + SramRetParityErr = 1u << 4, ///< Retention SRAM parity error +}en_sram_err_status_t; + +/** + ******************************************************************************* + ** \brief SRAM configuration + ** + ** \note The SRAM configuration structure + ******************************************************************************/ +typedef struct stc_sram_config +{ + uint8_t u8SramIdx; ///< SRAM index, ref @ en_sram_index_t for details + en_sram_rw_cycle_t enSramRC; ///< SRAM read wait cycle setting + en_sram_rw_cycle_t enSramWC; ///< SRAM write wait cycle setting + en_ecc_mode_t enSramEccMode; ///< SRAM ECC mode setting + en_ecc_py_err_op_t enSramEccOp; ///< SRAM3 ECC error handling setting + en_ecc_py_err_op_t enSramPyOp; ///< SRAM1/2/HS/Ret Parity error handling setting + +}stc_sram_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig); +extern en_result_t SRAM_DeInit(void); +extern en_result_t SRAM_WT_Disable(void); +extern en_result_t SRAM_WT_Enable(void); +extern en_result_t SRAM_CK_Disable(void); +extern en_result_t SRAM_CK_Enable(void); +extern en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus); +extern en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus); + +//@} // SramGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_SRAM_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_swdt.h b/lib/hc32f460/driver/inc/hc32f460_swdt.h new file mode 100644 index 000000000000..6add27c02c85 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_swdt.h @@ -0,0 +1,81 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.h + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_SWDT_H__ +#define __HC32F460_SWDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SwdtGroup Special Watchdog Counter(SWDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT flag type enumeration + ******************************************************************************/ +typedef enum en_swdt_flag_type +{ + SwdtFlagCountUnderflow = 0u, ///< Count underflow flag + SwdtFlagRefreshError = 1u, ///< Refresh error flag +} en_swdt_flag_type_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SWDT_RefreshCounter(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag); +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag); + +//@} // SwdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_timer0.h b/lib/hc32f460/driver/inc/hc32f460_timer0.h new file mode 100644 index 000000000000..16744a5bd8cf --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_timer0.h @@ -0,0 +1,204 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.h + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +#ifndef __HC32F460_TIMER0_H__ +#define __HC32F460_TIMER0_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Timer0Group Timer0 + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timer0 channel enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_channel +{ + Tim0_ChannelA = 0x00u, + Tim0_ChannelB = 0x01u +}en_tim0_channel_t; + +/** + ******************************************************************************* + ** \brief Timer0 Async Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_async_clock_src +{ + Tim0_LRC = 0x00u, + Tim0_XTAL32 = 0x01u +}en_tim0_async_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 Sync Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_sync_clock_src +{ + Tim0_Pclk1 = 0x00u, + Tim0_InsideHardTrig = 0x01u +}en_tim0_sync_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 counter mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_counter_mode +{ + Tim0_Sync = 0x00u, + Tim0_Async = 0x01u +}en_tim0_counter_mode_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger event mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_function +{ + Tim0_OutputCapare = 0x00u, + Tim0_InputCaptrue = 0x01u +}en_tim0_function_t; + +/** + ******************************************************************************* + ** \brief Timer0 clock division enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_clock_div +{ + Tim0_ClkDiv0 = 0u, + Tim0_ClkDiv2, + Tim0_ClkDiv4, + Tim0_ClkDiv8, + Tim0_ClkDiv16, + Tim0_ClkDiv32, + Tim0_ClkDiv64, + Tim0_ClkDiv128, + Tim0_ClkDiv256, + Tim0_ClkDiv512, + Tim0_ClkDiv1024 +}en_tim0_clock_div_t; + +/** + ******************************************************************************* + ** \brief Timer0 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_com_trigger +{ + Tim0ComTrigger_1 = 1u, ///< Select common trigger 1. + Tim0ComTrigger_2 = 2u, ///< Select common trigger 2. + Tim0ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_tim0_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger function init structrue definition + ** + ******************************************************************************/ +typedef struct stc_tim0_trigger_init +{ + en_tim0_function_t Tim0_OCMode; ///GCMAR / GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR / GCMDR-->GCMBR + ** Double buffer stransfer: Compare Ouput: GCMER-->GCMCR-->GCMAR / GCMFR-->GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR-->GCMER /GCMFR-->GCMDR-->GCMBR + ** For Period register: + ** Single buffer stransfer: PERBR-->PERAR + ** Double buffer stransfer: PERCR-->PERBR-->PERAR + ******************************************************************************/ +typedef enum en_timer6_buf_gcmp_prd +{ + Timer6GcmpPrdSingleBuf = 0u, ///< Single buffer stransfer + Timer6GcmpPrdDoubleBuf = 1u, ///< Double buffer stransfer +}en_timer6_buf_gcmp_prd_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer function selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_cmp +{ + Timer6SpclSingleBuf = 0u, ///< Single buffer stransfer: Compare Ouput: SCMCR-->SCMAR / SCMDR-->SCMBR + Timer6SpclDoubleBuf = 1u, ///< Double buffer stransfer: Compare Ouput: SCMER-->SCMCR-->SCMAR / SCMFR-->SCMDR-->SCMBR +}en_timer6_buf_spcl_cmp_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer opportunity selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_opt +{ + Timer6SplcOptNone = 0u, ///< No transfer + Timer6SplcOptOverFlow = 1u, ///< Transfer when over flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptUnderFlow = 2u, ///< Transfer when under flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptBoth = 3u, ///< Transfer when over flow or under flow (About sawtooth mode,accord to the count direction) +}en_timer6_buf_spcl_opt_t; + +/** + ****************************************************************************** + ** \brief ADT dead timer control - PWMx dead timer separate set + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_dconr_sepa +{ + Timer6PWMxDtSeparate = 0u, ///< The dead timer of up count and down count separate set by DTUAR and DTDAR + Timer6PWMxDtEqual = 1u, ///< the values of DTUAR and DTDAR are equal automatically +}en_timer6_dconr_sepa_t; + +/** + ****************************************************************************** + ** \brief ADT filter control- TRIx/PWMx port filter sample clock selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_fconr_fltclk +{ + Timer6FltClkPclk0Div1 = 0u, ///< PCLK0 + Timer6FltClkPclk0Div4 = 1u, ///< PCLK0/4 + Timer6FltClkPclk0Div16 = 2u, ///< PCLK0/16 + Timer6FltClkPclk0Div64 = 3u, ///< PCLK0/64 +}en_timer6_fconr_fltclk_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- TIMx valid period repeat function selection(trigger interrupt or AOS event) + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnts +{ + Timer6PeriodCnts0 = 0u, ///< Valid period repeat function disable + Timer6PeriodCnts1 = 1u, ///< Enable every other one period + Timer6PeriodCnts2 = 2u, ///< Enable every other two periods + Timer6PeriodCnts3 = 3u, ///< Enable every other three periods + Timer6PeriodCnts4 = 4u, ///< Enable every other four periods + Timer6PeriodCnts5 = 5u, ///< Enable every other five periods + Timer6PeriodCnts6 = 6u, ///< Enable every other six periods + Timer6PeriodCnts7 = 7u, ///< Enable every other seven periods +}en_timer6_vperr_pcnts_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- Count condition select + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnte +{ + Timer6PeriodCnteDisable = 0u, ///< Valid period repeat function disable + Timer6PeriodCnteMin = 1u, ///< Over flow and under flow point of Sawtooth wave mode, or under flow point of Triangular wave mode + Timer6PeriodCnteMax = 2u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow point of Triangular wave mode + Timer6PeriodCnteBoth = 3u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow and under flow point of Triangular wave mode +}en_timer6_vperr_pcnte_t; + +/** + ****************************************************************************** + ** \brief Timer6 Hardware(Start/Stop/Clear/Capture) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_trig +{ + Timer6HwTrigAos0 = 0u, ///< Hardware trigger event from AOS0(HTSSR0) + Timer6HwTrigAos1 = 1u, ///< Hardware trigger event from AOS1(HTSSR1) + Timer6HwTrigPWMARise = 4u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMAFall = 5u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigPWMBRise = 6u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMBFall = 7u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigTimTriARise = 8u, ///< Hardware trigger event from TRIGA rising + Timer6HwTrigTimTriAFall = 9u, ///< Hardware trigger event from TRIGA falling + Timer6HwTrigTimTriBRise = 10u, ///< Hardware trigger event from TRIGB rising + Timer6HwTrigTimTriBFall = 11u, ///< Hardware trigger event from TRIGB falling + Timer6HwTrigEnd = 16u, +}en_timer6_hw_trig_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware (up count/down count) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_cnt +{ + Timer6HwCntPWMALowPWMBRise = 0u, ///< PWMB Rising trigger when PWMA is low level + Timer6HwCntPWMALowPWMBFall = 1u, ///< PWMB falling trigger when PWMA is low level + Timer6HwCntPWMAHighPWMBRise = 2u, ///< PWMB Rising trigger when PWMA is high level + Timer6HwCntPWMAHighPWMBFall = 3u, ///< PWMB falling trigger when PWMA is high level + Timer6HwCntPWMBLowPWMARise = 4u, ///< PWMA Rising trigger when PWMB is low level + Timer6HwCntPWMBLowPWMAFall = 5u, ///< PWMA falling trigger when PWMB is low level + Timer6HwCntPWMBHighPWMARise = 6u, ///< PWMA Rising trigger when PWMB is high level + Timer6HwCntPWMBHighPWMAFall = 7u, ///< PWMA falling trigger when PWMB is high level + Timer6HwCntTRIGARise = 8u, ///< TRIGA rising trigger + Timer6HwCntTRIGAFall = 9u, ///< TRIGA falling trigger + Timer6HwCntTRIGBRise = 10u, ///< TRIGB rising trigger + Timer6HwCntTRIGBFall = 11u, ///< TRIGB falling trigger + Timer6HwCntAos0 = 16u, ///< AOS0 trigger + Timer6HwCntAos1 = 17u, ///< AOS1 trigger + Timer6HwCntMax = 18u, +}en_timer6_hw_cnt_t; + + +/** + ****************************************************************************** + ** \brief Timer6 interrupt type + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_irq_type +{ + Timer6INTENA = 0u, ///< Interrupt of count equal to GCMA (or capture input A) + Timer6INTENB = 1u, ///< Interrupt of count equal to GCMB (or capture input B) + Timer6INTENC = 2u, ///< Interrupt of count equal to GCMC + Timer6INTEND = 3u, ///< Interrupt of count equal to GCMD + Timer6INTENE = 4u, ///< Interrupt of count equal to GCME + Timer6INTENF = 5u, ///< Interrupt of count equal to GCMF + Timer6INTENOVF = 6u, ///< Interrupt of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6INTENUDF = 7u, ///< Interrupt of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6INTENDTE = 8u, ///< Interrupt of dead timer error + Timer6INTENSAU = 16u, ///< Interrupt of count up equally compared with SCMA + Timer6INTENSAD = 17u, ///< Interrupt of count down equally compared with SCMA + Timer6INTENSBU = 18u, ///< Interrupt of count up equally compared with SCMB + Timer6INTENSBD = 19u, ///< Interrupt of count down equally compared with SCMB +}en_timer6_irq_type_t; + + +/** + ****************************************************************************** + ** \brief Timer6 status flag + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_status +{ + Timer6CMAF = 0u, ///< Status flag of count equal to GCMA (or capture input A) + Timer6CMBF = 1u, ///< Status flag of count equal to GCMB (or capture input B) + Timer6CMCF = 2u, ///< Status flag of count equal to GCMC + Timer6CMDF = 3u, ///< Status flag of count equal to GCMD + Timer6CMEF = 4u, ///< Status flag of count equal to GCME + Timer6CMFF = 5u, ///< Status flag of count equal to GCMF + Timer6OVFF = 6u, ///< Status flag of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6UDFF = 7u, ///< Status flag of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6DTEF = 8u, ///< Status flag of dead timer error + Timer6CMSAUF = 9u, ///< Status flag of count up equally compared with SCMA + Timer6CMSADF = 10u, ///< Status flag of count down equally compared with SCMA + Timer6CMSBUF = 11u, ///< Status flag of count up equally compared with SCMB + Timer6CMSBDF = 12u, ///< Status flag of count down equally compared with SCMB + Timer6VPERNUM = 21, ///< Number of valid period + Timer6DIRF = 31, ///< Count direction +}en_timer6_status_t; + +/** + ******************************************************************************* + ** \brief Timer6 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_timer6_com_trigger +{ + Timer6ComTrigger_1 = 1u, ///< Select common trigger 1. + Timer6ComTrigger_2 = 2u, ///< Select common trigger 2. + Timer6ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timer6_com_trigger_t; + +/** + ****************************************************************************** + ** \brief Timer6 software synchronous config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_sw_sync +{ + bool bTimer61; ///< Timer6 unit1 + bool bTimer62; ///< Timer6 unit2 + bool bTimer63; ///< Timer6 unit3 +}stc_timer6_sw_sync_t; + +/** + ****************************************************************************** + ** \brief Timer6 base init structure definition + ** \note + ******************************************************************************/ +typedef struct stc_timer6_basecnt_cfg +{ + en_timer6_count_mode_t enCntMode; ///< Count mode + en_timer6_count_dir_t enCntDir; ///< Count direction + en_timer6_clk_div_t enCntClkDiv; ///< Count clock division select +}stc_timer6_basecnt_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Trig port config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_port_trig_cfg +{ + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_tiemr6_port_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 port output config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_output_cfg +{ + bool bOutEn; ///< Output enable / disable + en_timer6_pconr_cmpc_t enPerc; ///< Port state when counter match the period + en_timer6_pconr_cmpc_t enCmpc; ///< Port state when counter match GCMAR(GCMBR) + en_timer6_pconr_stastps_t enStaStp; ///< Post state selection when count start/stop + en_timer6_pconr_port_out_t enStaOut; ///< Port state when count start + en_timer6_pconr_port_out_t enStpOut; ///< port stop when count stop + en_timer6_pconr_disval_t enDisVal; ///< Port output state when brake +}stc_timer6_port_output_cfg_t; + + +/** + ****************************************************************************** + ** \brief Timer6 port input config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_input_cfg +{ + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_timer6_port_input_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware dead time function config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_deadtime_cfg +{ + bool bEnDeadtime; ///< Enable hardware dead time function + bool bEnDtBufUp; ///< Enable buffer transfer for up count dead time register(DTUBR-->DTUAR) + bool bEnDtBufDwn; ///< Enable buffer transfer for down count dead time register(DTDBR-->DTDAR) + bool bEnDtEqualUpDwn; ///< Enable down count dead time register equal to up count DT register +}stc_timer6_deadtime_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_validper_cfg +{ + en_timer6_vperr_pcnts_t enValidCntNum; ///< Valid period selection + en_timer6_vperr_pcnte_t enValidCdtEn; ///< Count condition of valid period + bool bPeriodSCMA; ///< Sepcial signal A valid period selection enable + bool bPeriodSCMB; ///< Sepcial signal A valid period selection enable +}stc_timer6_validper_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 general compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_gcmp_buf_cfg +{ + bool bEnGcmpTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enGcmpBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_gcmp_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 period register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_period_buf_cfg +{ + bool bEnPeriodTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enPeriodBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_period_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Specila compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_spcl_buf_cfg +{ + bool bEnSpclTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_spcl_cmp_t enSpclBufTransType; ///< Sigle or double buffer transfer + en_timer6_buf_spcl_opt_t enSpclBufOptType; ///< Buffer transfer opportunity +}stc_timer6_spcl_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Z phase input mask config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_zmask_cfg +{ + en_timer6_gconr_zmsk_t enZMaskCycle; ///< Z phase input mask periods selection + bool bFltPosCntMaksEn; ///< As position count timer, position counter clear function enable(TRUE) or disable(FALSE) during the time of Z phase input mask + bool bFltRevCntMaksEn; ///< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) during the time of Z phase input mask +}stc_timer6_zmask_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn); +/* Get status(flag) */ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus); + +/* Base functions */ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x); +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg); +/* Timer6 unit start count*/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit stop count*/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Set Count Value*/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value); +/* Timer6 unit Get Count Value*/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Clear Count Value*/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x); + +/* Timer6 unit Set Period and buffer Value*/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period); +/* Timer6 unit set general compare register value*/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare); +/* Timer6 unit set specoal compare register value*/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp); +/* Timer6 unit get general compare register value*/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare); + +/* Timer6 unit set period buffer transfer function*/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg); +/* Timer6 unit set general compare buffer transfer function*/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg); +/* Timer6 unit set special compare buffer transfer function*/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg); + +/* Timer6 unit Set valid period Value*/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg); + +/* Config channel mode, capture or output */ +void Timer6_SetFunc(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, en_timer6_func_mode_t enMode); +/* Config Input prot and filter function */ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_input_port_t enTimer6InputPort, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg); +/* Config output prot function */ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg); + +/* Set dead time register value */ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue); +/* Config dead time function */ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg); + +/* Config Software Synchrony Stop */ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart); +/* Config Software Synchrony Start */ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop); +/* Config Software Synchrony Clear */ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear); +/* Get Software Synchrony Status */ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState); + +/* Config Hardware up count event */ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp); +/* Clear Hardware up count event */ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware down count event */ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn); +/* Clear Hardware down count event */ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware start event */ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart); +/* Clear Hardware start event */ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware start event */ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware start event */ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware stop event */ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop); +/* Clear Hardware stop event */ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware stop event */ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x); +/* Disable Hardware stop event */ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware clear event */ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear); +/* Clear Hardware clear event */ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware clear event */ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware clear event */ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware capture event A */ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA); +/* Clear Hardware capture event A */ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware capture event B */ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB); +/* Clear Hardware capture event B */ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x); + + +/* Set trigger source 0 of hardware event */ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc); +/* Set trigger source 1 of hardware event */ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc); +/* Enable or disable Timer6 common trigger for Hardware trigger source 0 */ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); +/* Enable or disable Timer6 common trigger for Hardware trigger source 1 */ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); + +/* Z phase input mask config */ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg); + +//@} // Timer6Group + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_TIMER6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_timera.h b/lib/hc32f460/driver/inc/hc32f460_timera.h new file mode 100644 index 000000000000..4bd002be08f6 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_timera.h @@ -0,0 +1,488 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.h + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ +#ifndef __HC32F460_TIMERA_H__ +#define __HC32F460_TIMERA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TimeraGroup Timer A(Timera) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timera channel enumeration + ******************************************************************************/ +typedef enum en_timera_channel +{ + TimeraCh1 = 0u, ///< Timera channel 1 + TimeraCh2 = 1u, ///< Timera channel 2 + TimeraCh3 = 2u, ///< Timera channel 3 + TimeraCh4 = 3u, ///< Timera channel 4 + TimeraCh5 = 4u, ///< Timera channel 5 + TimeraCh6 = 5u, ///< Timera channel 6 + TimeraCh7 = 6u, ///< Timera channel 7 + TimeraCh8 = 7u, ///< Timera channel 8 +} en_timera_channel_t; + +/** + ******************************************************************************* + ** \brief Clock division enumeration + ******************************************************************************/ +typedef enum en_timera_clk_div +{ + TimeraPclkDiv1 = 0u, ///< Count clock: pclk + TimeraPclkDiv2 = 1u, ///< Count clock: pclk/2 + TimeraPclkDiv4 = 2u, ///< Count clock: pclk/4 + TimeraPclkDiv8 = 3u, ///< Count clock: pclk/8 + TimeraPclkDiv16 = 4u, ///< Count clock: pclk/16 + TimeraPclkDiv32 = 5u, ///< Count clock: pclk/32 + TimeraPclkDiv64 = 6u, ///< Count clock: pclk/64 + TimeraPclkDiv128 = 7u, ///< Count clock: pclk/128 + TimeraPclkDiv256 = 8u, ///< Count clock: pclk/256 + TimeraPclkDiv512 = 9u, ///< Count clock: pclk/512 + TimeraPclkDiv1024 = 10u, ///< Count clock: pclk/1024 +} en_timera_clk_div_t; + +/** + ******************************************************************************* + ** \brief Count mode enumeration + ******************************************************************************/ +typedef enum en_timera_count_mode +{ + TimeraCountModeSawtoothWave = 0u, ///< Sawtooth wave mode + TimeraCountModeTriangularWave = 1u, ///< Triangular wave mode +} en_timera_count_mode_t; + +/** + ******************************************************************************* + ** \brief Count direction enumeration + ******************************************************************************/ +typedef enum en_timera_count_dir +{ + TimeraCountDirDown = 0u, ///< Counter counting down + TimeraCountDirUp = 1u, ///< Counter counting up +} en_timera_count_dir_t; + +/** + ******************************************************************************* + ** \brief Input port filter clock division enumeration + ******************************************************************************/ +typedef enum en_timera_filter_clk_div +{ + TimeraFilterPclkDiv1 = 0u, ///< Filter clock: pclk + TimeraFilterPclkDiv4 = 1u, ///< Filter clock: pclk/4 + TimeraFilterPclkDiv16 = 2u, ///< Filter clock: pclk/16 + TimeraFilterPclkDiv64 = 3u, ///< Filter clock: pclk/64 +} en_timera_filter_clk_div_t; + +/** + ******************************************************************************* + ** \brief Input port filter source enumeration + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef enum en_timera_filter_source +{ + TimeraFilterSourceCh1 = 0u, ///< TIMA__PWM1 input port + TimeraFilterSourceCh2 = 1u, ///< TIMA__PWM2 input port + TimeraFilterSourceCh3 = 2u, ///< TIMA__PWM3 input port + TimeraFilterSourceCh4 = 3u, ///< TIMA__PWM4 input port + TimeraFilterSourceCh5 = 4u, ///< TIMA__PWM5 input port + TimeraFilterSourceCh6 = 5u, ///< TIMA__PWM6 input port + TimeraFilterSourceCh7 = 6u, ///< TIMA__PWM7 input port + TimeraFilterSourceCh8 = 7u, ///< TIMA__PWM8 input port + TimeraFilterSourceClkA = 8u, ///< TIMA__CLKA input port + TimeraFilterSourceClkB = 9u, ///< TIMA__CLKB input port + TimeraFilterSourceTrig = 10u, ///< TIMA__TRIG input port +} en_timera_filter_source_t; + +/** + ******************************************************************************* + ** \brief Timera interrupt request type enumeration + ******************************************************************************/ +typedef enum en_timera_irq_type +{ + TimeraIrqCaptureOrCompareCh1 = 0u, ///< Interrupt request when channel 1 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh2 = 1u, ///< Interrupt request when channel 2 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh3 = 2u, ///< Interrupt request when channel 3 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh4 = 3u, ///< Interrupt request when channel 4 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh5 = 4u, ///< Interrupt request when channel 5 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh6 = 5u, ///< Interrupt request when channel 6 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh7 = 6u, ///< Interrupt request when channel 7 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh8 = 7u, ///< Interrupt request when channel 8 trigger capture event or compare value equal count value + TimeraIrqOverflow = 8u, ///< Count overflow interrupt request + TimeraIrqUnderflow = 9u, ///< Count underflow interrupt request +} en_timera_irq_type_t; + +/** + ******************************************************************************* + ** \brief Timera flag type enumeration + ******************************************************************************/ +typedef enum en_timera_flag_type +{ + TimeraFlagCaptureOrCompareCh1 = 0u, ///< Match flag when channel 1 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh2 = 1u, ///< Match flag when channel 2 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh3 = 2u, ///< Match flag when channel 3 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh4 = 3u, ///< Match flag when channel 4 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh5 = 4u, ///< Match flag when channel 5 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh6 = 5u, ///< Match flag when channel 6 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh7 = 6u, ///< Match flag when channel 7 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh8 = 7u, ///< Match flag when channel 8 trigger capture complete or compare value equal count value + TimeraFlagOverflow = 8u, ///< Count overflow flag + TimeraFlagUnderflow = 9u, ///< Count underflow flag +} en_timera_flag_type_t; + +/** + ******************************************************************************* + ** \brief Timera function mode selection enumeration + ******************************************************************************/ +typedef enum en_timera_func_mode +{ + TimeraModeCompareOutput = 0u, ///< Compare output function + TimeraModeCaptureInput = 1u, ///< Capture input function +} en_timera_func_mode_t; + +/** + ******************************************************************************* + ** \brief Timera count start port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_start_output +{ + TimeraCountStartOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStartOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStartOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_start_output_t; + +/** + ******************************************************************************* + ** \brief Timera count stop port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_stop_output +{ + TimeraCountStopOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStopOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStopOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_stop_output_t; + +/** + ******************************************************************************* + ** \brief Timera compare value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_compare_match_output +{ + TimeraCompareMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCompareMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCompareMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraCompareMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_compare_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera period value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_period_match_output +{ + TimeraPeriodMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraPeriodMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraPeriodMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraPeriodMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_period_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera specify output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_specify_output +{ + TimeraSpecifyOutputInvalid = 0u, ///< TIMA__PWMn port output invalid + TimeraSpecifyOutputLow = 2u, ///< TIMA__PWMn port output low level from next period + TimeraSpecifyOutputHigh = 3u, ///< TIMA__PWMn port output high level from next period +} en_timera_specify_output_t; + +/** + ******************************************************************************* + ** \brief Timera common trigger source enumeration + ******************************************************************************/ +typedef enum en_timera_com_trigger +{ + TimeraComTrigger_1 = 1u, ///< Select common trigger 1. + TimeraComTrigger_2 = 2u, ///< Select common trigger 2. + TimeraComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timera_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timera base init structure definition + ******************************************************************************/ +typedef struct stc_timera_base_init +{ + en_timera_clk_div_t enClkDiv; ///< Count clock division select,This is invalid when counting internal or external event + en_timera_count_mode_t enCntMode; ///< Timera count mode + en_timera_count_dir_t enCntDir; ///< Timera count direction + en_functional_state_t enSyncStartupEn; ///< Enable/disable synchronization startup when unit 1 startup,unit 1 set bit invalid + uint16_t u16PeriodVal; ///< Period value +} stc_timera_base_init_t; + +/** + ******************************************************************************* + ** \brief Timera compare output init structure definition + ******************************************************************************/ +typedef struct stc_timera_compare_init +{ + uint16_t u16CompareVal; ///< Compare value + en_timera_count_start_output_t enStartCountOutput; ///< Port status set when count start + en_timera_count_stop_output_t enStopCountOutput; ///< Port status set when count stop + en_timera_compare_match_output_t enCompareMatchOutput; ///< Port status set when compare value match + en_timera_period_match_output_t enPeriodMatchOutput; ///< Port status set when period value match + en_timera_specify_output_t enSpecifyOutput; ///< Specify port status,next period valid,priority more than other port status set + en_functional_state_t enCacheEn; ///< Enable/Disable cache，Only unit 1、3、5、7 valid + en_functional_state_t enTriangularTroughTransEn; ///< Enable/Disable triangular wave trough transmit cache value，Only unit 1、3、5、7 valid + en_functional_state_t enTriangularCrestTransEn; ///< Enable/Disable triangular wave crest transmit cache value，Only unit 1、3、5、7 valid + uint16_t u16CompareCacheVal; ///< Compare cache value,Only unit 1、3、5、7 valid +} stc_timera_compare_init_t; + +/** + ******************************************************************************* + ** \brief Timera capture input init structure definition + ******************************************************************************/ +typedef struct stc_timera_capture_init +{ + en_functional_state_t enCapturePwmRisingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample rising + en_functional_state_t enCapturePwmFallingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample falling + en_functional_state_t enCaptureSpecifyEventEn; ///< Enable/Disable capture channel n active when specify event trigger,event value is TMRA_HTSSR1 + en_timera_filter_clk_div_t enPwmClkDiv; ///< TIMA__PWMn filter clock select + en_functional_state_t enPwmFilterEn; ///< Enable/Disable TIMA__PWMn filter functions + en_functional_state_t enCaptureTrigRisingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample rising, only CCONR4 valid + en_functional_state_t enCaptureTrigFallingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample falling, only CCONR4 valid + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select, only CCONR4 valid + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions , only CCONR4 valid +} stc_timera_capture_init_t; + +/** + ******************************************************************************* + ** \brief Timera Orthogonal coding init structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6 + ******************************************************************************/ +typedef struct stc_timera_orthogonal_coding_init +{ + en_functional_state_t enIncClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enIncTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enIncSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enIncAnotherUnitOverflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enIncAnotherUnitUnderflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_functional_state_t enDecClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enDecTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enDecSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enDecAnotherUnitUnderflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enDecAnotherUnitOverflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_timera_filter_clk_div_t enClkAClkDiv; ///< TIMA__CLKA filter clock select + en_functional_state_t enClkAFilterEn; ///< Enable/Disable TIMA__CLKA filter functions + en_timera_filter_clk_div_t enClkBClkDiv; ///< TIMA__CLKB filter clock select + en_functional_state_t enClkBFilterEn; ///< Enable/Disable TIMA__CLKB filter functions + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions +} stc_timera_orthogonal_coding_init_t; + +/** + ******************************************************************************* + ** \brief Timera hardware startup config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note TMRA_HTSSR0 trigger startup only when unit 2~6 valid,unit 1 is invalid + ******************************************************************************/ +typedef struct stc_timera_hw_startup_config +{ + en_functional_state_t enTrigRisingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample rising edge(sync start valid) + en_functional_state_t enTrigFallingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample falling edge(sync start valid) + en_functional_state_t enSpecifyEventStartupEn; ///< Hardware startup TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_startup_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware stop config structure definition + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef struct stc_timera_hw_stop_config +{ + en_functional_state_t enTrigRisingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventStopEn; ///< Hardware stop TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_stop_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware clear config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6 + ******************************************************************************/ +typedef struct stc_timera_hw_clear_config +{ + en_functional_state_t enTrigRisingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventClearEn; ///< Hardware clear TIMA_ when TIMA_HTSSR0 register Specify event trigger + en_functional_state_t enAnotherUnitTrigRisingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample rising when current unit is m. + en_functional_state_t enAnotherUnitTrigFallingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample falling when current unit is m. + en_functional_state_t enChannel3RisingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample rising edge + en_functional_state_t enChannel3FallingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample falling edge +} stc_timera_hw_clear_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware trigger init structure definition + ******************************************************************************/ +typedef struct stc_timera_hw_trigger_init +{ + stc_timera_hw_startup_config_t stcHwStartup; ///< Hardware startup condition config + stc_timera_hw_stop_config_t stcHwStop; ///< Hardware stop condition config + stc_timera_hw_clear_config_t stcHwClear; ///< Hardware clear condition config +} stc_timera_hw_trigger_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit); +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt); +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period); +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); + +/* Compare output functions */ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit); +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal); +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache); +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta); +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); + +/* Capture input functions */ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit); +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); + +/* Orthogonal coding functions */ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit); +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt); +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); + +/* Hardware control functions */ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit); +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup); +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop); +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear); + +/* interrupt and flags functions */ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); + +/* Event config functions */ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); + +//@} // TimeraGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_TIMERA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_trng.h b/lib/hc32f460/driver/inc/hc32f460_trng.h new file mode 100644 index 000000000000..b34f37c32a0f --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_trng.h @@ -0,0 +1,95 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.h + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ +#ifndef __HC32F460_TRNG_H__ +#define __HC32F460_TRNG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TrngGroup True Random Number Generator(TRNG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* The data register loads the new initial value from the random number + generator before the random number is generated. */ +typedef enum en_trng_load_ctrl +{ + TrngLoadNewInitValue_Disable = 0x0, ///< Disable load new initial values. + TrngLoadNewInitValue_Enable = 0x1, ///< Enable load new initial values. +} en_trng_load_ctrl_t; + +/* Shift n times when capturing random noise. */ +typedef enum en_trng_shift_cnt +{ + TrngShiftCount_32 = 0x3, ///< Shift 32 times when capturing random noise. + TrngShiftCount_64 = 0x4, ///< Shift 64 times when capturing random noise. + TrngShiftCount_128 = 0x5, ///< Shift 128 times when capturing random noise. + TrngShiftCount_256 = 0x6, ///< Shift 256 times when capturing random noise. +} en_trng_shift_cnt_t; + +/* TRNG initialization structure definition. */ +typedef struct stc_trng_init +{ + en_trng_load_ctrl_t enLoadCtrl; ///< @ref en_trng_load_ctrl_t. + en_trng_shift_cnt_t enShiftCount; ///< @ref en_trng_shift_cnt_t. +} stc_trng_init_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit); +void TRNG_DeInit(void); +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout); + +void TRNG_StartIT(void); +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length); + +//@} // TrngGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_usart.h b/lib/hc32f460/driver/inc/hc32f460_usart.h new file mode 100644 index 000000000000..ce5bd684d246 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_usart.h @@ -0,0 +1,354 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.h + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ +#ifndef __HC32F460_USART_H__ +#define __HC32F460_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup UsartGroup Universal Synchronous Asynchronous Receiver \ + ** Transmitter(USART) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief USART tx mode in multiple processor mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_mp_tx_mode +{ + UsartMpTxData = 0u, ///< USART Send data in multiple-processor mode + UsartMpTxId = 1u, ///< USART Send ID in multiple-processor mode +} en_usart_mp_tx_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock prescale enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_div +{ + UsartClkDiv_1 = 0u, ///< PCLK/1 + UsartClkDiv_4 = 1u, ///< PCLK/4 + UsartClkDiv_16 = 2u, ///< PCLK/16 + UsartClkDiv_64 = 3u, ///< PCLK/64 +} en_usart_clk_div_t; + +/** + ****************************************************************************** + ** \brief USART mode + ** + ******************************************************************************/ +typedef enum en_usart_mode +{ + UsartUartMode = 0u, ///< UART mode + UsartClkSyncMode = 1u, ///< Clock sync mode + UsartSmartCardMode = 2u, ///< Smart card mode +} en_usart_mode_t; + +/** + ****************************************************************************** + ** \brief USART data direction + ** + ******************************************************************************/ +typedef enum en_usart_data_dir +{ + UsartDataLsbFirst = 0u, ///< LSB first + UsartDataMsbFirst = 1u, ///< MSB first +} en_usart_data_dir_t; + +/** + ****************************************************************************** + ** \brief USART sample mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sample_mode +{ + UsartSampleBit16 = 0u, ///< 16 Bit + UsartSampleBit8 = 1u, ///< 8 Bit +} en_usart_sample_mode_t; + +/** + ****************************************************************************** + ** \brief USART data length enumeration + ** + ******************************************************************************/ +typedef enum en_usart_data_len +{ + UsartDataBits8 = 0u, ///< 8 Bit + UsartDataBits9 = 1u, ///< 9 Bit +} en_usart_data_len_t; + +/** + ****************************************************************************** + ** \brief USART parity format enumeration + ** + ******************************************************************************/ +typedef enum en_usart_parity +{ + UsartParityNone = 0u, ///< No parity bit is used. + UsartParityEven = 1u, ///< Even parity bit is used. + UsartParityOdd = 2u, ///< Odd parity bit is used. +} en_usart_parity_t; + +/** + ****************************************************************************** + ** \brief USART functions enumeration + ** + ******************************************************************************/ +typedef enum en_usart_func +{ + UsartRx = 0u, ///< UART RX function + UsartRxInt = 1u, ///< USART RX interrupt function + UsartTx = 2u, ///< UART TX function + UsartTxEmptyInt = 3u, ///< USART TX empty interrupt function + UsartTimeOut = 4u, ///< UART RX timeout function + UsartTimeOutInt = 5u, ///< UART RX timeout interrupt function + UsartSilentMode = 6u, ///< USART silent function + UsartTxCmpltInt = 7u, ///< USART TX complete interrupt function + UsartTxAndTxEmptyInt = 8u, ///< USART TX function and USART TX empty interrupt function + UsartParityCheck = 9u, ///< USART Parity check function + UsartNoiseFilter = 10u, ///< USART noise filter function + UsartFracBaudrate = 11u, ///< USART fractional baudrate function + UsartMulProcessor = 12u, ///< USART multiple processor function + UsartSmartCard = 13u, ///< USART smart card mode function + UsartCts = 14u, ///< USART CTS function +} en_usart_func_t; + +/** + ******************************************************************************* + ** \brief USART status type enumeration + ** + ******************************************************************************/ +typedef enum en_usart_status +{ + UsartParityErr = (1u << 0), ///< USART parity error + UsartFrameErr = (1u << 1), ///< USART receive frame error + UsartOverrunErr = (1u << 3), ///< USART receive over-run error + UsartRxNoEmpty = (1u << 5), ///< USART data receive register is not empty + UsartTxComplete = (1u << 6), ///< USART transfer completely + UsartTxEmpty = (1u << 7), ///< USART data transfer register is empty + UsartRxTimeOut = (1u << 8), ///< USART data receive timeout + UsartRxMpb = (1u << 16), ///< USART multiple processor id or normal data, 0: receive date; 1: received ID +} en_usart_status_t; + +/** + ******************************************************************************* + ** \brief USART Stop bit length select enumeration + ** + ******************************************************************************/ +typedef enum en_usart_stop_bit +{ + UsartOneStopBit = 0u, ///< 1 Stop Bit + UsartTwoStopBit = 1u, ///< 2 Stop Bit +} en_usart_stop_bit_t; + +/** + ******************************************************************************* + ** \brief USART start bit detect mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sb_detect_mode +{ + UsartStartBitLowLvl = 0u, ///< Start bit: RD pin low level + UsartStartBitFallEdge = 1u, ///< Start bit: RD pin falling edge +} en_usart_sb_detect_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_mode +{ + UsartIntClkCkNoOutput = 0u, ///< Select internal clock source and don't output clock. + UsartIntClkCkOutput = 1u, ///< Select internal clock source and output clock. + UsartExtClk = 2u, ///< Select external clock source. +} en_usart_clk_mode_t; + +/** + ******************************************************************************* + ** \brief USART smart-card mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_hw_flow_ctrl +{ + UsartRtsEnable = 0u, ///< Enable RTS function. + UsartCtsEnable = 1u, ///< Enable CTS function. +} en_usart_hw_flow_ctrl_t; + +/** + ****************************************************************************** + ** \brief USART etu clocks of smart card enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sc_etu_clk +{ + UsartScEtuClk32 = 0u, ///< 1 etu = 32/f + UsartScEtuClk64 = 1u, ///< 1 etu = 64/f + UsartScEtuClk128 = 3u, ///< 1 etu = 128/f + UsartScEtuClk256 = 5u, ///< 1 etu = 256/f + UsartScEtuClk372 = 6u, ///< 1 etu = 372/f +} en_usart_sc_etu_clk_t; + +/** + ******************************************************************************* + ** \brief Uart mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_uart_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_len_t enDataLength; ///< 8/9 Bit character length and this parameter can be a value of @ref en_usart_data_len_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_stop_bit_t enStopBit; ///< Stop bit and this parameter can be a value of @ref en_usart_stop_bit_t + + en_usart_parity_t enParity; ///< Parity format and this parameter can be a value of @ref en_usart_parity_t + + en_usart_sample_mode_t enSampleMode; ///< USART sample mode, and this parameter can be a value of @ref en_usart_sample_mode_t + + en_usart_sb_detect_mode_t enDetectMode; ///< USART start bit detect mode and this parameter can be a value of @ref en_usart_sb_detect_mode_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_uart_init_t; + +/** + ******************************************************************************* + ** \brief Clock sync mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_clksync_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_clksync_init_t; + +/** + ******************************************************************************* + ** \brief Smart card mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_sc_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t +} stc_usart_sc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg); +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg); +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg); +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx); +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd); +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity); +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx); +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode); +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir); +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen); +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode); +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode); +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit); +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode); +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl); +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale); +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx); +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk); +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx); +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data); +uint16_t USART_RecData(M4_USART_TypeDef *USARTx); +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +//@} // UsartGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_utility.h b/lib/hc32f460/driver/inc/hc32f460_utility.h new file mode 100644 index 000000000000..37ec19932821 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_utility.h @@ -0,0 +1,104 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.h + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ +#ifndef __HC32F460_UTILITY_H__ +#define __HC32F460_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlUtilityGroup Device Driver Library Utility(DDLUTILITY) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/* A approximate delay */ +void Ddl_Delay1ms(uint32_t u32Cnt); +void Ddl_Delay1us(uint32_t u32Cnt); + +/* Systick functions */ +en_result_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +/*! Ddl assert, you can add your own assert functions by implement the function +Ddl_AssertHook definition follow the function Ddl_AssertHook declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do{ \ + ((x) ? (void)0 : Ddl_AssertHandler((uint8_t *)__FILE__, __LINE__)); \ +}while(0) +/* Exported function */ +void Ddl_AssertHandler(uint8_t *file, int16_t line); +#else +#define DDL_ASSERT(x) (void)(0) +#endif /* __DEBUG */ + +#if defined(DDL_PRINT_ENABLE) +#include + +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)); + +#define DDL_PrintfInit (void)UART_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(x, y, z) +#define DDL_Printf(fmt, ...) +#endif + +//@} // DdlUtilityGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/inc/hc32f460_wdt.h b/lib/hc32f460/driver/inc/hc32f460_wdt.h new file mode 100644 index 000000000000..f958639dd0d7 --- /dev/null +++ b/lib/hc32f460/driver/inc/hc32f460_wdt.h @@ -0,0 +1,157 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.h + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_WDT_H__ +#define __HC32F460_WDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup WdtGroup WatchDog Counter(WDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief WDT count cycle enumeration + ******************************************************************************/ +typedef enum en_wdt_count_cycle +{ + WdtCountCycle256 = 0u, ///< 256 cycle + WdtCountCycle4096 = 1u, ///< 4096 cycle + WdtCountCycle16384 = 2u, ///< 16384 cycle + WdtCountCycle65536 = 3u, ///< 65536 cycle +} en_wdt_count_cycle_t; + +/** + ******************************************************************************* + ** \brief WDT count clock division enumeration + ******************************************************************************/ +typedef enum en_wdt_clk_div +{ + WdtPclk3Div4 = 2u, ///< PCLK3/4 + WdtPclk3Div64 = 6u, ///< PCLK3/64 + WdtPclk3Div128 = 7u, ///< PCLK3/128 + WdtPclk3Div256 = 8u, ///< PCLK3/256 + WdtPclk3Div512 = 9u, ///< PCLK3/512 + WdtPclk3Div1024 = 10u, ///< PCLK3/1024 + WdtPclk3Div2048 = 11u, ///< PCLK3/2048 + WdtPclk3Div8192 = 13u, ///< PCLK3/8192 +} en_wdt_clk_div_t; + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range enumeration + ******************************************************************************/ +typedef enum en_wdt_refresh_range +{ + WdtRefresh100Pct = 0u, ///< 100% + WdtRefresh0To25Pct = 1u, ///< 0%~25% + WdtRefresh25To50Pct = 2u, ///< 25%~50% + WdtRefresh0To50Pct = 3u, ///< 0%~50% + WdtRefresh50To75Pct = 4u, ///< 50%~75% + WdtRefresh0To25PctAnd50To75Pct = 5u, ///< 0%~25% & 50%~75% + WdtRefresh25To75Pct = 6u, ///< 25%~75% + WdtRefresh0To75Pct = 7u, ///< 0%~75% + WdtRefresh75To100Pct = 8u, ///< 75%~100% + WdtRefresh0To25PctAnd75To100Pct = 9u, ///< 0%~25% & 75%~100% + WdtRefresh25To50PctAnd75To100Pct = 10u, ///< 25%~50% & 75%~100% + WdtRefresh0To50PctAnd75To100Pct = 11u, ///< 0%~50% & 75%~100% + WdtRefresh50To100Pct = 12u, ///< 50%~100% + WdtRefresh0To25PctAnd50To100Pct = 13u, ///< 0%~25% & 50%~100% + WdtRefresh25To100Pct = 14u, ///< 25%~100% + WdtRefresh0To100Pct = 15u, ///< 0%~100% +} en_wdt_refresh_range_t; + +/** + ******************************************************************************* + ** \brief WDT refresh error or count underflow trigger event type enumeration + ******************************************************************************/ +typedef enum en_wdt_event_request_type +{ + WdtTriggerInterruptRequest = 0u, ///< Interrupt request + WdtTriggerResetRequest = 1u, ///< Reset request +} en_wdt_event_request_type_t; + +/** + ******************************************************************************* + ** \brief WDT flag type enumeration + ******************************************************************************/ +typedef enum en_wdt_flag_type +{ + WdtFlagCountUnderflow = 0u, ///< Count underflow flag + WdtFlagRefreshError = 1u, ///< Refresh error flag +} en_wdt_flag_type_t; + +/** + ******************************************************************************* + ** \brief WDT init structure definition + ******************************************************************************/ +typedef struct stc_wdt_init +{ + en_wdt_count_cycle_t enCountCycle; ///< Count cycle + en_wdt_clk_div_t enClkDiv; ///< Count clock division + en_wdt_refresh_range_t enRefreshRange; ///< Allow refresh percent range + en_functional_state_t enSleepModeCountEn; ///< Enable/disable count in the sleep mode + en_wdt_event_request_type_t enRequestType; ///< Refresh error or count underflow trigger event type +} stc_wdt_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +en_result_t WDT_RefreshCounter(void); +uint16_t WDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag); +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag); + +//@} // WdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_adc.c b/lib/hc32f460/driver/src/hc32f460_adc.c new file mode 100644 index 000000000000..08f406bbc48a --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_adc.c @@ -0,0 +1,1742 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.c + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_adc.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ADC peripherals. */ +#define IS_ADC_PERIPH(ADCx) \ +( ((ADCx) == M4_ADC1) || \ + ((ADCx) == M4_ADC2)) + +/*! Parameter validity check for ADC1 channel index. */ +#define IS_ADC1_CH_INDEX(x) \ +( ((x) < ADC1_CH_COUNT)) + +/*! Parameter validity check for ADC2 channel index. */ +#define IS_ADC2_CH_INDEX(x) \ +( ((x) < ADC2_CH_COUNT)) + +/*! Parameter validity check for ADC average count. */ +#define IS_ADC_AVCNT(AVCNT) \ +( ((AVCNT) == AdcAvcnt_2) || \ + (((AVCNT) >= AdcAvcnt_4) && ((AVCNT) <= AdcAvcnt_256))) + +/*! Parameter validity check for ADC data alignment. */ +#define IS_ADC_DATA_ALIGN(ALIGN) \ +( ((ALIGN) == AdcDataAlign_Right) || \ + ((ALIGN) == AdcDataAlign_Left)) + +/*! Parameter validity check for ADC auto clear DR. */ +#define IS_ADC_CLREN(EN) \ +( ((EN) == AdcClren_Enable) || \ + ((EN) == AdcClren_Disable)) + +/*! Parameter validity check for ADC resolution. */ +#define IS_ADC_RESOLUTION(RESOLUTION) \ +( ((RESOLUTION) == AdcResolution_8Bit) || \ + ((RESOLUTION) == AdcResolution_10Bit) || \ + ((RESOLUTION) == AdcResolution_12Bit)) + +/*! Parameter validity check for ADC scan convert mode. */ +#define IS_ADC_SCAN_MODE(MODE) \ +( ((MODE) == AdcMode_SAOnce) || \ + ((MODE) == AdcMode_SAContinuous) || \ + ((MODE) == AdcMode_SAOnceSBOnce) || \ + ((MODE) == AdcMode_SAContinuousSBOnce)) + +/*! Parameter validity check for ADC RSCHSEL. */ +#define IS_ADC_RSCHSEL(SEL) \ +( ((SEL) == AdcRschsel_Continue) || \ + ((SEL) == AdcRschsel_Restart)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGEN(EN) \ +( ((EN) == AdcTrgen_Enable) || \ + ((EN) == AdcTrgen_Disable)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGSEL(SEL) \ +( ((SEL) == AdcTrgsel_ADTRGX) || \ + ((SEL) == AdcTrgsel_TRGX0) || \ + ((SEL) == AdcTrgsel_TRGX1) || \ + ((SEL) == AdcTrgsel_TRGX0_TRGX1)) + +/*! Parameter validity check for ADC common trigger. */ +#define IS_ADC_COM_TRIGGER(x) \ +( ((x) == AdcComTrigger_1) || \ + ((x) == AdcComTrigger_2) || \ + ((x) == AdcComTrigger_1_2)) + +/*! Parameter validity check for ADC EOCAIEN/ENCBIEN. */ +#define IS_ADC_EOCIEN(EN) \ +( ((EN) == AdcEocien_Disable) || \ + ((EN) == AdcEocien_Enable)) + +/*! Parameter validity check for ADC sampling time. */ +#define IS_ADC_SAMPLE_TIME(TIME) \ +( ((TIME) == 255u) || \ + (((TIME) >= 5u) && ((TIME) <= 254u))) + +/*! Parameter validity check for ADC sync trigger mode. */ +#define IS_ADC_SYNC_MODE(MODE) \ +( ((MODE) == AdcSync_SingleSerial) || \ + ((MODE) == AdcSync_SingleParallel) || \ + ((MODE) == AdcSync_ContinuousSerial) || \ + ((MODE) == AdcSync_ContinuousParallel)) + +/*! Parameter validity check for ADC sync able. */ +#define IS_ADC_SYNC_ENABLE(EN) \ +( ((EN) == AdcSync_Disable) || \ + ((EN) == AdcSync_Enable)) + +/*! Parameter validity check for ADC ADWIEN */ +#define IS_ADC_AWDIEN(EN) \ +( ((EN) == AdcAwdInt_Disable) || \ + ((EN) == AdcAwdInt_Enable)) + +/*! Parameter validity check for ADC AWDSS */ +#define IS_ADC_AWDSS(SS) \ +( ((SS) == AdcAwdSel_SA_SB) || \ + ((SS) == AdcAwdSel_SA) || \ + ((SS) == AdcAwdSel_SB) || \ + ((SS) == AdcAwdSel_SB_SA)) + +/*! Parameter validity check for ADC AWDMD */ +#define IS_ADC_AWDMD(MD) \ +( ((MD) == AdcAwdCmpMode_0) || \ + ((MD) == AdcAwdCmpMode_1)) + +/*! Parameter validity check for ADC AWDEN */ +#define IS_ADC_AWDEN(EN) \ +( ((EN) == AdcAwd_Disable) || \ + ((EN) == AdcAwd_Enable)) + +/*! Parameter validity check for ADC PGA control */ +#define IS_ADC_PGA_CTL(CTL) \ +( ((CTL) == AdcPgaCtl_Invalid) || \ + ((CTL) == AdcPgaCtl_Amplify)) + +/*! Parameter validity check for ADC gain factor. */ +#define IS_ADC_PGA_FACTOR(FACTOR) \ +( ((FACTOR) == AdcPgaFactor_2) || \ + (((FACTOR) >= AdcPgaFactor_2P133) && ((FACTOR) <= AdcPgaFactor_32))) + +/*! Parameter validity check for ADC PGA negative. */ +#define IS_ADC_PGA_NEGATIVE(N) \ +( ((N) == AdcPgaNegative_VSSA) || \ + ((N) == AdcPgaNegative_PGAVSS)) + +/*! Parameter validity check for ADC PGA channel. */ +#define IS_ADC_PGA_CH(ch) \ +( ((ch) == PGA_CH_NONE) || \ + ((ch) == PGA_CH0) || \ + ((ch) == PGA_CH1) || \ + ((ch) == PGA_CH2) || \ + ((ch) == PGA_CH3) || \ + ((ch) == PGA_CH4) || \ + ((ch) == PGA_CH5) || \ + ((ch) == PGA_CH6) || \ + ((ch) == PGA_CH7) || \ + ((ch) == PGA_CH8)) + +/*! Parameter validity check for ADC trigger source event . */ +#define IS_ADC_TRIG_SRC_EVENT(x) \ +( ((x) == EVT_PORT_EIRQ0) || \ + (((x) > EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcInit Pointer to ADC initialization structure. + ** See @ref stc_adc_init_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcInit)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcInit->enResolution)); + DDL_ASSERT(IS_ADC_DATA_ALIGN(pstcInit->enDataAlign)); + DDL_ASSERT(IS_ADC_CLREN(pstcInit->enAutoClear)); + DDL_ASSERT(IS_ADC_SCAN_MODE(pstcInit->enScanMode)); + DDL_ASSERT(IS_ADC_RSCHSEL(pstcInit->enRschsel)); + + /* Stop ADC conversion. */ + ADCx->STR = 0u; + + ADCx->CR0_f.ACCSEL = pstcInit->enResolution; + ADCx->CR0_f.DFMT = pstcInit->enDataAlign; + ADCx->CR0_f.CLREN = pstcInit->enAutoClear; + ADCx->CR0_f.MS = pstcInit->enScanMode; + ADCx->CR1_f.RSCHSEL = pstcInit->enRschsel; + + /* Disable EOC(End Of Conversion) interrupts default. */ + ADCx->ICR = (uint8_t)0x0; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx) +{ + uint8_t i; + uint8_t u8SstrNum; + uint32_t u32SSTRAddr; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + /* Set the value of all registers to the reset value. */ + /* Stop ADC conversion. */ + ADCx->STR = 0u; + ADCx->CR0 = 0u; + ADCx->CR1 = 0u; + ADCx->TRGSR = 0u; + ADCx->CHSELRA0 = 0u; + ADCx->CHSELRB0 = 0u; + ADCx->AVCHSELR0 = 0u; + ADCx->CHMUXR0 = (uint16_t)0x3210; + ADCx->CHMUXR1 = (uint16_t)0x7654; + ADCx->ISR = 0u; + ADCx->ICR = (uint8_t)0x03; + ADCx->AWDCR = 0u; + ADCx->AWDDR0 = 0u; + ADCx->AWDDR1 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->AWDSR0 = 0u; + + u32SSTRAddr = (uint32_t)&ADCx->SSTR0; + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 = 0u; + ADCx->CHSELRB1 = 0u; + ADCx->AVCHSELR1 = 0u; + ADCx->CHMUXR2 = (uint16_t)0xBA98; + ADCx->CHMUXR3 = (uint16_t)0xFEDC; + ADCx->SYNCCR = (uint16_t)0x0C00; + ADCx->AWDCHSR1 = 0u; + ADCx->AWDSR1 = 0u; + ADCx->PGACR = 0u; + ADCx->PGAGSR = 0u; + ADCx->PGAINSR0 = 0u; + ADCx->PGAINSR1 = 0u; + ADCx->SSTRL = 0x0Bu; + u8SstrNum = 16u; + } + else + { + u8SstrNum = 9u; + } + + for (i=0u; iCR0_f.MS = enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcTrgCfg Pointer to ADC trigger source configuration structure. + ** \arg u8Sequence The sequence which you want to set it's trigger source. + ** \arg enTrgEnable Enable or disable trigger source. + ** \arg enTrgSel The type of trigger source. + ** \arg enInTrg0 Event number @ref en_event_src_t. + ** \arg enInTrg1 Event number @ref en_event_src_t. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same trigger source. + ** + ******************************************************************************/ +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, + const stc_adc_trg_cfg_t *pstcTrgCfg) +{ + uint32_t u32TrgSelR; + __IO uint32_t *io32AdcxTrgSelR0; + __IO uint32_t *io32AdcxTrgSelR1; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && + (NULL != pstcTrgCfg) && + (pstcTrgCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(pstcTrgCfg->enTrgSel)); + + if (ADC_SEQ_A == pstcTrgCfg->u8Sequence) + { + ADCx->TRGSR_f.TRGSELA = pstcTrgCfg->enTrgSel; + } + else + { + ADCx->TRGSR_f.TRGSELB = pstcTrgCfg->enTrgSel; + } + + if (AdcTrgsel_ADTRGX != pstcTrgCfg->enTrgSel) + { + if (M4_ADC1 == ADCx) + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC1_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC1_ITRGSELR1); + } + else + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC2_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC2_ITRGSELR1); + } + + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg0)); + + u32TrgSelR = *io32AdcxTrgSelR0; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg0; + *io32AdcxTrgSelR0 = u32TrgSelR; + } + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg1)); + + u32TrgSelR = *io32AdcxTrgSelR1; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg1; + *io32AdcxTrgSelR1 = u32TrgSelR; + } + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to set it's trigger source. + ** + ** \param [in] enState Enable or disable trigger source. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (ADC_SEQ_A == u8Seq) + { + ADCx->TRGSR_f.TRGENA = enState; + } + else + { + ADCx->TRGSR_f.TRGENB = enState; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC common trigger. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enTrgSel ADC trigger source type. See @ref en_adc_trgsel_t for details. + ** + ** \param [in] enComTrigger ADC common trigger selection. See @ref en_adc_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + uint32_t u32ITRGSELRAddr; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(enTrgSel) && (enTrgSel != AdcTrgsel_ADTRGX)); + DDL_ASSERT(IS_ADC_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (M4_ADC1 == ADCx) + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC1_ITRGSELR0; + } + else + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC2_ITRGSELR0; + } + + u32ComTrig <<= 30u; + + if ((enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } + + if ((enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + u32ITRGSELRAddr += 4ul; + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } +} + +/** + ******************************************************************************* + ** \brief Add ADC channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcChCfg Pointer to ADC channel configuration structure. + ** \arg u32Channel The channel(s) you want to configure. + ** \arg u8Sequence The sequence which the channel(s) belong(s) to. + ** \arg pu8SampTime Pointer to sampling time. + ** eg. u32Channel = 1001b + ** pu8SampTime[0] = channel 0's time + ** pu8SampTime[1] = channel 3's time + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same channel!!! + ** + ******************************************************************************/ +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32ChannelSel; + __IO uint8_t *io8Sstr; + + if ((NULL != ADCx) && + (NULL != pstcChCfg) && + (pstcChCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32ChannelSel = pstcChCfg->u32Channel & ADC1_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRA1 |= (uint16_t)(u32ChannelSel >> 16u); + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRB1 |= (uint16_t)(u32ChannelSel >> 16u); + } + } + else + { + u32ChannelSel = pstcChCfg->u32Channel & ADC2_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + } + } + + /* Set sampling time */ + i = 0u; + j = 0u; + io8Sstr = &(ADCx->SSTR0); + while (0u != u32ChannelSel) + { + if (u32ChannelSel & 0x1ul) + { + io8Sstr[i] = pstcChCfg->pu8SampTime[j++]; + } + u32ChannelSel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete ADC channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s) you want to delete. + ** \arg ADC1_CH0 ~ ADC1_CH16 Channels of ADC unit 1. + ** \arg ADC2_CH0 ~ ADC2_CH8 Channels of ADC unit 2. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note You can use this function to delete ADC channel(s) + ** and then set the corresponding pin(s) of the channel(s) + ** to the other mode you need in your application. + ** + ******************************************************************************/ +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->CHSELRA0 &= (uint16_t)(~u16ChSelR0); + ADCx->CHSELRB0 &= (uint16_t)(~u16ChSelR0); + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 &= (uint16_t)(~u16ChSelR1); + ADCx->CHSELRB1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC interrupt configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence to be configured. + ** + ** \param [in] enState Enable or Disable sequence conversion done interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8Msk = 0u; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u8Msk = (uint8_t)(0x1ul << u8Seq); + ADCx->ISR &= (uint8_t)(~u8Msk); + + if (Enable == enState) + { + ADCx->ICR |= u8Msk; + } + else + { + ADCx->ICR &= (uint8_t)(~u8Msk); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC average conversion configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enAvgCnt Average after enAvgCnt conversions. + ** See @ref en_adc_avcnt_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AVCNT(enAvgCnt)); + + ADCx->CR0_f.AVCNT = enAvgCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as average channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 |= u16AvgChR0; + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 |= u16AvgChR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The average channel(s) which you want to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 &= (uint16_t)(~u16AvgChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 &= (uint16_t)(~u16AvgChR1); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC AWD(analog watch dog) configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcAwdCfg Pointer to the configuration structure. + ** See @ref stc_adc_awd_cfg_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcAwdCfg)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AWDMD(pstcAwdCfg->enAwdmd)); + DDL_ASSERT(IS_ADC_AWDSS(pstcAwdCfg->enAwdss)); + + ADCx->AWDCR_f.AWDEN = AdcAwd_Disable; + ADCx->AWDCR_f.AWDIEN = AdcAwdInt_Disable; + ADCx->AWDCR_f.AWDMD = pstcAwdCfg->enAwdmd; + ADCx->AWDCR_f.AWDSS = pstcAwdCfg->enAwdss; + + ADCx->AWDDR0 = pstcAwdCfg->u16AwdDr0; + ADCx->AWDDR1 = pstcAwdCfg->u16AwdDr1; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog) interrupt. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDIEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as AWD channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 |= u16ChSelR0; + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 |= u16ChSelR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The AWD channel(s) which you are going to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 &= (uint16_t)(~u16ChSelR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC programmable gain amplifier(PGA) configuration. + ** + ** \param [in] enFactor PGA gain factor. + ** \param [in] enNegativeIn PGA negative input select. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. + ** + ******************************************************************************/ +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn) +{ + DDL_ASSERT(IS_ADC_PGA_FACTOR(enFactor)); + DDL_ASSERT(IS_ADC_PGA_NEGATIVE(enNegativeIn)); + + M4_ADC1->PGAGSR_f.GAIN = enFactor; + M4_ADC1->PGAINSR1_f.PGAVSSEN = enNegativeIn; +} + +/** + ******************************************************************************* + ** \brief Enable or disable PGA. + ** + ** \param [in] enState Enable or disable PGA. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_PgaCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (Enable == enState) + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Amplify; + } + else + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Invalid; + } +} + +/** + ******************************************************************************* + ** \brief Select PGA channel. + ** + ** \param[in] u16Channel The channel, which you want to gain. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. The channel must first + ** be configured as an analog channel + ** by function ADC_AddAdcChannel + ** + ******************************************************************************/ +void ADC_PgaSelChannel(uint16_t u16Channel) +{ + DDL_ASSERT(IS_ADC_PGA_CH(u16Channel)); + M4_ADC1->PGAINSR0 = u16Channel; +} + +/** + ******************************************************************************* + ** \brief ADC sync mode configuration. + ** + ** \param [in] enMode Synchronous mode types. + ** \param [in] u8TrgDelay ADC2 trigger delay time. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay) +{ + DDL_ASSERT(IS_ADC_SYNC_MODE(enMode)); + + /* Disable synchronous mode first. */ + M4_ADC1->SYNCCR_f.SYNCEN = AdcSync_Disable; + + M4_ADC1->SYNCCR_f.SYNCMD = enMode; + M4_ADC1->SYNCCR_f.SYNCDLY = u8TrgDelay; +} + +/** + ******************************************************************************* + ** \brief Enable or disable sync mode. + ** + ** \param [in] enState Enable or disable sync mode. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_SyncCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_ADC1->SYNCCR_f.SYNCEN = enState; +} + +/** + ******************************************************************************* + ** \brief Start an ADC conversion. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note Software startup only support sequence A. + ** + ******************************************************************************/ +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->STR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop an ADC conversion and clear flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32TimeCount = 0u; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + /* Make sure the ADC is really stopped. */ + while (ADCx->STR == 1u) + { + /* Stop ADC conversion. */ + ADCx->STR = 0u; + if (++u32TimeCount > 10000u) + { + enRet = ErrorTimeout; + break; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the conversion status flag. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to get + ** it's conversion status flag. + ** + ** \retval Set ADC converted done. + ** \retval Reset ADC is converting or parameter error. + ** + ******************************************************************************/ +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (ADCx->ISR & ((uint8_t)(0x1ul << u8Seq))) + { + enFlag = Set; + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear conversion status flag of sequence A or sequence B. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to clear + ** it's conversion status flag. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->ISR &= (uint8_t)(~(0x1ul << u8Seq)); + } +} + +/** + ******************************************************************************* + ** \brief ADC start sequence A, check it's EOC status and get the data. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address to store ADC value. + ** The location of the data store depends on + ** the parameter u8Length. + ** u8Length >= ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** all of the ADC data regs will be read: + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** u8Length < ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** only the data of the enabled channles will be read: + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval OperationInProgress ADC is converting. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, + uint16_t *pu16AdcData, + uint8_t u8Length, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8AllDataLength = 0u; + uint32_t u32Channel = 0u; + uint32_t u32AdcTimeout = 0u; + __IO uint32_t u32TimeCount = 0u; + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + if (u8Length >= ADC1_CH_COUNT) + { + u8AllDataLength = ADC1_CH_COUNT; + } + else + { + u32Channel = (uint32_t)ADCx->CHSELRA1; + u32Channel <<= 16u; + u32Channel |= (uint32_t)ADCx->CHSELRA0; + } + } + else + { + if (u8Length >= ADC2_CH_COUNT) + { + u8AllDataLength = ADC2_CH_COUNT; + } + else + { + u32Channel = (uint32_t)M4_ADC2->CHSELRA0; + } + } + + /* Start ADC conversion. */ + ADCx->STR = (uint8_t)0x01; + + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32AdcTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32AdcTimeout) + { + if (ADCx->ISR_f.EOCAF) + { + /* Get ADC data. */ + if (u8AllDataLength) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8AllDataLength); + } + else + { + ADC_GetChData(ADCx, u32Channel, pu16AdcData, u8Length); + } + + /* Clear sequence A flag. */ + ADCx->ISR_f.EOCAF = 0u; + enRet = Ok; + break; + } + u32TimeCount++; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading all data regs of an ADC. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + if (((M4_ADC1 == ADCx) && (u8Length >= ADC1_CH_COUNT)) || + ((M4_ADC2 == ADCx) && (u8Length >= ADC2_CH_COUNT))) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8Length); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading the data of the specified channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u32TargetCh The specified channel(s) + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** eg. u32TargetCh = 1001b + ** pu16AdcData[0] = Channel 0's data, + ** pu16AdcData[1] = Channel 3's data, + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, + uint32_t u32TargetCh, + uint16_t *pu16AdcData, + uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32Channel; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel = u32TargetCh & ADC1_CH_ALL; + } + else + { + u32Channel = u32TargetCh & ADC2_CH_ALL; + } + + i = 0u; + j = 0u; + while ((0u != u32Channel) && (0u != u8Length)) + { + if (0u != (u32Channel & 0x1ul)) + { + pu16AdcData[j] = pu16DataReg[i]; + j++; + u8Length--; + } + + u32Channel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the value of a specified channel via channel index. + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u8ChIndex The index of the specified channel. + ** u8ChIndex < ADC1_CH_COUNT while ADCx == M4_ADC1; + ** u8ChIndex < ADC2_CH_COUNT while ADCx == M4_ADC2. + ** + ** \retval An uint16_t value -- the ADC value of the specified channel. + ** + ******************************************************************************/ +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + return pu16DataReg[u8ChIndex]; +} + +/** + ******************************************************************************* + ** \brief Get all AWD channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval u32AwdFlag 0 -- No ADC channel meets AWD comparison conditions. + ** !0 -- The bit value of the channel that satisfies the + ** AWD condition is 1. + ** + ******************************************************************************/ +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx) +{ + uint32_t u32AwdFlag; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32AwdFlag = ADCx->AWDSR1; + u32AwdFlag <<= 16u; + u32AwdFlag |= ADCx->AWDSR0; + } + else + { + u32AwdFlag = ADCx->AWDSR0; + } + + return u32AwdFlag; +} + +/** + ******************************************************************************* + ** \brief Clear all AWD channels status flags + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->AWDSR0 = 0u; + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR0 = 0u; + ADCx->AWDSR1 = 0u; + } + } +} + +/** + ******************************************************************************* + ** \brief Clear AWD specified channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32AwdCh The channel(s) which you want to clear it's flag(s). + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh) +{ + uint16_t u16ChR0; + uint16_t u16ChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChR0 = (uint16_t)u32AwdCh; + u16ChR1 = (uint16_t)(u32AwdCh >> 16u); + + ADCx->AWDSR0 &= (uint16_t)(~u16ChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR1 &= (uint16_t)(~u16ChR1); + } + } +} + +/** + ******************************************************************************* + ** \brief Remap an ADC pin to channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32DestChannel Destination channel(s). + ** + ** \param [in] u8AdcPin ADC pin number. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, + uint32_t u32DestChannel, + uint8_t u8AdcPin) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint16_t u16AdcPin = u8AdcPin; + __IO uint16_t *io16Chmuxr = NULL; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + if (M4_ADC1 == ADCx) + { + if (u16AdcPin <= ADC1_IN15) + { + u32DestChannel &= ADC1_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + else + { + if ((u16AdcPin >= ADC12_IN4) && (u16AdcPin <= ADC12_IN11)) + { + u16AdcPin -= 4u; + u32DestChannel &= ADC2_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + i = 0u; + while (0u != u32DestChannel) + { + if (u32DestChannel & 0x1ul) + { + u8OffsetReg = i / 4u; + u8ChPos = (i % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + *io16Chmuxr &= (uint16_t)(~(0xFul << u8ChPos)); + *io16Chmuxr |= (uint16_t)(u16AdcPin << u8ChPos); + } + + u32DestChannel >>= 1u; + i++; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the number of the pin corresponding to the specified channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8ChIndex This channel that you want to get its pin number. + ** + ** \retval [0, 15] The correct ADC pin number. + ** \retval [0xFF] The invalid ADC pin number. + ** + ******************************************************************************/ +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + uint8_t u8OffsetPin; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint8_t u8AdcPin = ADC_PIN_INVALID; + __IO const uint16_t *io16Chmuxr = NULL; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + DDL_ASSERT(IS_ADC1_CH_INDEX(u8ChIndex)); + u8OffsetPin = 0u; + } + else + { + DDL_ASSERT(IS_ADC2_CH_INDEX(u8ChIndex)); + u8OffsetPin = 4u; + } + + u8OffsetReg = u8ChIndex / 4u; + u8ChPos = (u8ChIndex % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + u8AdcPin = (uint8_t)((*io16Chmuxr >> u8ChPos) & ((uint16_t)0xF)); + u8AdcPin += u8OffsetPin; + + return u8AdcPin; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Read all data of an ADC. pu16AdcData[0] = DR0, pu16AdcData[1] = DR1, ... + ** + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + uint8_t i; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + for (i = 0u; i < u8Length; i++) + { + pu16AdcData[i] = pu16DataReg[i]; + } +} + +//@} // AdcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_aes.c b/lib/hc32f460/driver/src/hc32f460_aes.c new file mode 100644 index 000000000000..84a0b9c5347e --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_aes.c @@ -0,0 +1,307 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.c + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_aes.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup AesGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* AES block length in bytes is 16. */ +#define AES_BLOCK_LEN ((uint8_t)16) + +/* Each encryption operation takes 440 system clock cycles. */ +#define AES_ENCRYPT_TIMEOUT (440u) + +/* Each decryption operation takes 580 system clock cycles. */ +#define AES_DECRYPT_TIMEOUT (580u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData); +static void AES_ReadData(uint8_t *pu8Dest); +static void AES_WriteKey(const uint8_t *pu8Key); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief AES128 encryption(ECB mode). + ** + ** \param [in] pu8Plaintext Pointer to plaintext(the source data which will be encrypted) + ** + ** \param [in] u32PlaintextSize Length of plaintext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Ciphertext The destination address to store the result of the encryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Plaintext) && + (0u != u32PlaintextSize) && + (NULL != pu8Key) && + (NULL != pu8Ciphertext) && + (0u == (u32PlaintextSize & 0xFu)) && /* u32PlaintextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Plaintext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32PlaintextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Plaintext[u32Index]); + + /* Set AES encrypt. */ + bM4_AES_CR_MODE = 0u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_ENCRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Ciphertext[u32Index]); + u32PlaintextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief AES128 decryption(ECB mode). + ** + ** \param [in] pu8Ciphertext Pointer to ciphertext(the source data which will be decrypted) + ** + ** \param [in] u32CiphertextSize Length of ciphertext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Plaintext The destination address to store the result of the decryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Ciphertext) && + (0u != u32CiphertextSize) && + (NULL != pu8Key) && + (NULL != pu8Plaintext) && + (0u == (u32CiphertextSize & 0xFu)) && /* u32CiphertextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Plaintext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32CiphertextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Ciphertext[u32Index]); + + /* Set AES decrypt. */ + bM4_AES_CR_MODE = 1u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_DECRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Plaintext[u32Index]); + u32CiphertextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint32_t u32SrcAddr = (uint32_t)pu8SrcData; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32DrAddr = *(uint32_t*)u32SrcAddr; + u32SrcAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Reads the from data register. + ** + ** \param [out] pu8Dest Pointer to the destination buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_ReadData(uint8_t *pu8Dest) +{ + uint8_t i; + uint32_t u32DestAddr = (uint32_t)pu8Dest; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(uint32_t*)u32DestAddr = *(__IO uint32_t *)u32DrAddr; + u32DestAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Writes the input buffer in key register. + ** + ** \param [in] pu8Key Pointer to AES key. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteKey(const uint8_t *pu8Key) +{ + uint8_t i; + uint32_t u32SrcKeyAddr = (uint32_t)pu8Key; + uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32KeyAddr = *(uint32_t*)u32SrcKeyAddr; + u32SrcKeyAddr += 4u; + u32KeyAddr += 4u; + } +} + +//@} // AesGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_can.c b/lib/hc32f460/driver/src/hc32f460_can.c new file mode 100644 index 000000000000..54ffe3662913 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_can.c @@ -0,0 +1,558 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.c + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-12-13 CDT First version for Device Driver Library of CAN. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_can.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup CanGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u) +#define CAN_RESET_DISABLE() \ +do{ \ + do{ \ + M4_CAN->CFG_STAT_f.RESET = 0u; \ +}while(M4_CAN->CFG_STAT_f.RESET); \ +}while(0) + +#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr)) + +#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u) +#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u) + + +/*! Parameter validity check for CAN Mode \a CanMode. */ +#define IS_CAN_MODE_VALID(CanMode) \ +( (CanExternalLoopBackMode == (CanMode)) || \ + (CanInternalLoopBackMode == (CanMode)) || \ + (CanTxSignalPrimaryMode == (CanMode)) || \ + (CanTxSignalSecondaryMode == (CanMode)) || \ + (CanListenOnlyMode == (CanMode)) \ +) + +/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */ +#define IS_TX_CMD_VALID(TxCmd) \ +( (CanPTBTxCmd == (TxCmd)) || \ + (CanPTBTxAbortCmd == (TxCmd)) || \ + (CanSTBTxOneCmd == (TxCmd)) || \ + (CanSTBTxAllCmd == (TxCmd)) || \ + (CanSTBTxAbortCmd == (TxCmd)) \ +) + +/*! Parameter validity check for CAN status \a enCanStatus. */ +#define IS_CAN_STATUS_VALID(enCanStatus) \ +( (CanRxActive == (enCanStatus)) || \ + (CanTxActive == (enCanStatus)) || \ + (CanBusoff == (enCanStatus)) \ +) + +/*! Parameter validity check for CAN Irq type \a enCanIrqType. */ +#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \ +( (CanRxIrqEn == (enCanIrqType)) || \ + (CanRxOverIrqEn == (enCanIrqType)) || \ + (CanRxBufFullIrqEn == (enCanIrqType)) || \ + (CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \ + (CanTxPrimaryIrqEn == (enCanIrqType)) || \ + (CanTxSecondaryIrqEn == (enCanIrqType)) || \ + (CanErrorIrqEn == (enCanIrqType)) || \ + (CanErrorPassiveIrqEn == (enCanIrqType)) || \ + (CanArbiLostIrqEn == (enCanIrqType)) || \ + (CanBusErrorIrqEn == (enCanIrqType)) \ +) + +/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */ +#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \ +( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxIrqFlg == (enCanIrqFLg)) || \ + (CanRxOverIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \ + (CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \ + (CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \ + (CanErrorIrqFlg == (enCanIrqFLg)) || \ + (CanAbortIrqFlg == (enCanIrqFLg)) || \ + (CanErrorWarningIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \ + (CanArbiLostIrqFlg == (enCanIrqFLg)) || \ + (CanBusErrorIrqFlg == (enCanIrqFLg)) \ +) + +/*! Parameter validity check for CAN filter \a enCanFilter. */ +#define IS_CAN_FILTER_VALID(enCanFilter) \ +( (enCanFilter) <= CanFilterSel8) + +/*! Parameter validity check for CAN filter count \a u8Count. */ +#define IS_CAN_FILTER_COUNT_VALID(u8Count) \ +( (u8Count) <= 8u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the can base functions + ** + ** \param [in] pstcCanInitCfg The can initial config struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg) +{ + uint8_t i; + if (NULL != pstcCanInitCfg) + { + DDL_ASSERT(IS_CAN_FILTER_COUNT_VALID(pstcCanInitCfg->u8FilterCount)); + + CAN_RESET_ENABLE(); + M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC; + M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1; + M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2; + M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW; + M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode; + CAN_FilterConfig(pstcCanInitCfg->pstcFilter, pstcCanInitCfg->u8FilterCount); + + CAN_RESET_DISABLE(); + M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll; + M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode; + M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck; + M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal; + M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal; + + // Enable filters. + for (i=0u; iu8FilterCount; i++) + { + CAN_FilterCmd(pstcCanInitCfg->pstcFilter[i].enFilterSel, Enable); + } + } +} + +/** + ******************************************************************************* + ** \brief De-Init (RESET CAN register) + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_DeInit(void) +{ + CAN_RESET_ENABLE(); +} + +/** + ******************************************************************************* + ** \brief Configures the can Mode + ** + ** \param [in] enMode The can mode enum. @ref en_can_mode_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_MODE_VALID(enMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(CanListenOnlyMode == enMode) + { + M4_CAN->TCMD_f.LOM = enNewState; + }else + { + if(Enable == enNewState) + { + M4_CAN->CFG_STAT |= enMode; + }else + { + M4_CAN->CFG_STAT &= ~enMode; + } + } +} + + +/** + ******************************************************************************* + ** \brief Configures the can acceptance filter + ** + ** \param [in] pstcFilter Pointer to a stc_can_filter_t type array. + ** @ref stc_can_filter_t + ** \param [in] u8FilterCount Number of filters that to be configured. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount) +{ + uint8_t i; + + if(NULL != pstcFilter) + { + DDL_ASSERT(IS_CAN_FILTER_COUNT_VALID(u8FilterCount)); + + for (i=0u; iACFCTRL_f.ACFADR = pstcFilter[i].enFilterSel; + //<ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL; + M4_CAN->ACF = pstcFilter[i].u32CODE; + //<ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL; + M4_CAN->ACF = pstcFilter[i].u32MASK; + //<ACF_f.AIDEE = ((pstcFilter[i].enAcfFormat >> 1ul) & 0x01u); + M4_CAN->ACF_f.AIDE = (pstcFilter[i].enAcfFormat & 0x01ul); + } + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified can acceptance filter. + ** + ** \param [in] enFilter Specifies a filter. + ** @ref en_can_filter_sel_t + ** \param [in] enNewState The new state of the specified filter. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState) +{ + uint8_t u8FilterSel; + + DDL_ASSERT(IS_CAN_FILTER_VALID(enFilter)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8FilterSel = (uint8_t)(1ul << enFilter); + + if(Enable == enNewState) + { + M4_CAN->ACFEN |= u8FilterSel; + }else + { + M4_CAN->ACFEN &= (uint8_t)(~u8FilterSel); + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx frame set + ** + ** \param [in] pstcTxFrame The can Tx frame struct. + ** @ref stc_can_txframe_t + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame) +{ + uint32_t u32TBUFAddr; + + if(NULL != pstcTxFrame) + { + u32TBUFAddr = (uint32_t)&M4_CAN->TBUF; + M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel; + CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0; + CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1; + CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0]; + CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1]; + + if(CanSTBSel == pstcTxFrame->enBufferSel) + { + M4_CAN->TCTRL_f.TSNEXT = Enable; + } + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx Command + ** + ** \param [in] enTxCmd The can Tx Command. + ** + ** \retval Can Tx buffer status @ref en_can_tx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd) +{ + DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd)); + + M4_CAN->TCMD |= enTxCmd; + + return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT; +} + +/** + ******************************************************************************* + ** \brief Configures the can Rx frame + ** + ** \param [in] pstcRxFrame The can Rx frame. + ** @ref stc_can_rxframe_t + ** \retval Can rx buffer status @ref en_can_rx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame) +{ + uint32_t u32RBUFAddr; + + if(NULL != pstcRxFrame) + { + u32RBUFAddr = (uint32_t)&M4_CAN->RBUF; + pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr); + pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4); + pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8); + pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12); + + M4_CAN->RCTRL_f.RREL = 1u; + } + return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSTAT; +} + + +/** + ******************************************************************************* + ** \brief Get the can Error Status + ** + ** \param None + ** + ** \retval en_can_error_t The can error status + ** + ** \note None + ** + ******************************************************************************/ +en_can_error_t CAN_ErrorStatusGet(void) +{ + en_can_error_t enRet = UNKOWN_ERROR; + + if(6u > M4_CAN->EALCAP_f.KOER) + { + enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the can Status + ** + ** \param enCanStatus The can status + ** \arg true + ** \arg false + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_StatusGet(en_can_status_t enCanStatus) +{ + bool bRet = false; + DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus)); + + if(M4_CAN->CFG_STAT & enCanStatus) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Configures the can Interrupt enable + ** + ** \param [in] enCanIrqType The can interrupt type. + ** \param [in] enNewState The new state of the can interrupt. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState) +{ + volatile uint32_t *u32pIE; + + DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if(Enable == enNewState) + { + *u32pIE |= enCanIrqType; + }else + { + *u32pIE &= ~((uint32_t)enCanIrqType); + } +} + +/** + ******************************************************************************* + ** \brief Get the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt Flag. + ** + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + bool bRet = false; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if( *u32pIE & enCanIrqFlgType) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Clear the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt type. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + uint32_t u32IETempMsk = 0xFF2A00FF; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + *u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType); +} + + +/** + ******************************************************************************* + ** \brief Get the can Rx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_RxErrorCntGet(void) +{ + return M4_CAN->RECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Tx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_TxErrorCntGet(void) +{ + return M4_CAN->TECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Arbitration lost captrue + ** + ** \param None + ** + ** \retval address(0~31) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_ArbitrationLostCap(void) +{ + return M4_CAN->EALCAP_f.ALC; +} + + +//@} // CanGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/lib/hc32f460/driver/src/hc32f460_clk.c b/lib/hc32f460/driver/src/hc32f460_clk.c new file mode 100644 index 000000000000..53055e8377f1 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_clk.c @@ -0,0 +1,1839 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.c + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_clk.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup CmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_XTAL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_XTAL32_TIMEOUT ((uint8_t)0x05u) +#define CLK_HRC_TIMEOUT ((uint16_t)0x1000u) +#define CLK_MRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_LRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_MPLL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_UPLL_TIMEOUT ((uint16_t)0x1000u) + +/* TBDs 30us based 200M frequency. */ +#define CLK_FCG_STABLE ((uint16_t)0x200u) +#define CLK_SYSCLK_STABLE ((uint16_t)0x200u) +#define CLK_USBCLK_STABLE ((uint16_t)0x200u) + +#define CLK_PLL_DIV_MIN (2u) +#define CLK_PLL_DIV_MAX (16u) + +#define CLK_PLLQ_DIV_MIN (1u) +#define CLK_PLLQ_DIV_MAX (16u) + +#define CLK_PLLN_MIN (20u) +#define CLK_PLLN_MAX (480u) + +#define CLK_PLLM_MIN (1u) +#define CLK_PLLM_MAX (24u) + +#define CLK_UPLLM_MIN (2u) +#define CLK_UPLLM_MAX (24u) + +#define CLK_PLL_VCO_IN_MIN (1u*1000u*1000u) +#define CLK_PLL_VCO_IN_MAX (24u*1000u*1000u) + +#define CLK_PLL_VCO_OUT_MIN (240u*1000u*1000u) +#define CLK_PLL_VCO_OUT_MAX (480u*1000u*1000u) + +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa501u) +#define DISABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~1u)))) + +#define ENABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + + +#define DEFAULT_FCG0 (0xFFFFFAEEul) +#define DEFAULT_FCG1 (0xFFFFFFFFul) +#define DEFAULT_FCG2 (0xFFFFFFFFul) +#define DEFAULT_FCG3 (0xFFFFFFFFul) +#define FCG2_WITHOUT_EMB (0xFFFF7FFFul) + +#define FCG0_OFFSET_FCM (16ul) +#define FCG1_OFFSET_CAN (0ul) +#define FCG1_OFFSET_QSPI (3ul) +#define FCG1_OFFSET_USBFS (8ul) +#define FCG1_OFFSET_SPI1 (16ul) +#define FCG1_OFFSET_SPI2 (17ul) +#define FCG1_OFFSET_SPI3 (18ul) +#define FCG1_OFFSET_SPI4 (19ul) +#define FCG3_OFFSET_ADC1 (0ul) +#define FCG3_OFFSET_ADC2 (1ul) +#define FCG3_OFFSET_DAC (4ul) + +/*! Parameter validity check for XTAL stablization time \a stb. */ +#define IS_XTAL_STB_VALID(stb) \ +( (ClkXtalStbCycle35 <= (stb)) && \ + (ClkXtalStbCycle8163 >= (stb))) + +/*! Parameter validity check for pll source \a src. */ +#define IS_PLL_SOURCE(src) \ +( (ClkPllSrcXTAL == (src)) || \ + (ClkPllSrcHRC == (src))) + +/*! Parameter validity check for mpll div \a pllp, pllr, upll div \a pllp, pllq, pllr*/ +#define IS_PLL_DIV_VALID(pllx) \ +( (CLK_PLL_DIV_MIN <= (pllx)) && \ + (CLK_PLL_DIV_MAX >= (pllx))) + +/*! Parameter validity check for pll div \a pllq. */ +#define IS_PLLQ_DIV_VALID(pllx) \ +( (CLK_PLLQ_DIV_MIN <= (pllx)) && \ + (CLK_PLLQ_DIV_MAX >= (pllx))) + +/*! Parameter validity check for plln \a plln. */ +#define IS_PLLN_VALID(plln) \ +( (CLK_PLLN_MIN <= (plln)) && \ + (CLK_PLLN_MAX >= (plln))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_PLLM_VALID(pllm) \ +( (CLK_PLLM_MIN <= (pllm)) && \ + (CLK_PLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_UPLLM_VALID(pllm) \ +( (CLK_UPLLM_MIN <= (pllm)) && \ + (CLK_UPLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllsource/pllm \a vco_in. */ +#define IS_PLL_VCO_IN_VALID(vco_in) \ +( (CLK_PLL_VCO_IN_MIN <= (vco_in)) && \ + (CLK_PLL_VCO_IN_MAX >= (vco_in))) + +/*! Parameter validity check for pllsource/pllm*plln \a vco_out. */ +#define IS_PLL_VCO_OUT_VALID(vco_out) \ +( (CLK_PLL_VCO_OUT_MIN <= (vco_out)) && \ + (CLK_PLL_VCO_OUT_MAX >= (vco_out))) + +/*! Parameter validity check for system clock source \a syssrc. */ +#define IS_SYSCLK_SOURCE(syssrc) \ +( (ClkSysSrcHRC == (syssrc)) || \ + ((ClkSysSrcMRC <= (syssrc)) && \ + (CLKSysSrcMPLL >= (syssrc)))) + +/*! Parameter validity check for usb clock source \a usbsrc. */ +#define IS_USBCLK_SOURCE(usbsrc) \ +( ((ClkUsbSrcSysDiv2 <= (usbsrc)) && \ + (ClkUsbSrcSysDiv4 >= (usbsrc))) || \ + ((ClkUsbSrcMpllp <= (usbsrc)) && \ + (ClkUsbSrcUpllr >= (usbsrc)))) + +/*! Parameter validity check for peripheral(adc/trng/I2S) clock source \a adcsrc. */ +#define IS_PERICLK_SOURCE(adcsrc) \ +( (ClkPeriSrcPclk == (adcsrc)) || \ + ((ClkPeriSrcMpllp <= (adcsrc)) && \ + (ClkPeriSrcUpllr >= (adcsrc)))) + +/*! Parameter validity check for output clock source \a outsrc. */ +#define IS_OUTPUTCLK_SOURCE(outsrc) \ +( (ClkOutputSrcHrc == (outsrc)) || \ + (ClkOutputSrcMrc == (outsrc)) || \ + (ClkOutputSrcLrc == (outsrc)) || \ + (ClkOutputSrcXtal == (outsrc)) || \ + (ClkOutputSrcXtal32 == (outsrc)) || \ + (ClkOutputSrcMpllp == (outsrc)) || \ + (ClkOutputSrcUpllp == (outsrc)) || \ + (ClkOutputSrcMpllq == (outsrc)) || \ + (ClkOutputSrcUpllq == (outsrc)) || \ + (ClkOutputSrcSysclk == (outsrc))) + +/*! Parameter validity check for fcm source \a fcmsrc. */ +#define IS_FCM_SOURCE(fcmsrc) \ +( (ClkFcmSrcXtal == (fcmsrc)) || \ + ((ClkFcmSrcXtal32 <= (fcmsrc)) && \ + (ClkFcmSrcRtcLrc >= (fcmsrc)))) + +/*! Parameter validity check for output clock channel \a outch. */ +#define IS_OUTPUTCLK_CHANNEL(outch) \ +( (ClkOutputCh1 == (outch)) || \ + (ClkOutputCh2 == (outch))) + +/*! Parameter validity check for fcm reference \a ref. */ +#define IS_FCM_REF(ref) \ +( (ClkFcmExtRef == (ref)) || \ + (ClkFcmInterRef == (ref))) + +/*! Parameter validity check for fcm edge \a edge. */ +#define IS_FCM_EDGE(edge) \ +( (ClkFcmEdgeRising == (edge)) || \ + (ClkFcmEdgeFalling == (edge)) || \ + (ClkFcmEdgeBoth == (edge))) + +/*! Parameter validity check for fcm filter clock \a clk. */ +#define IS_FCM_FILTER_CLK(clk) \ +( (ClkFcmFilterClkNone == (clk)) || \ + (ClkFcmFilterClkFcmSrc == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv4 == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv16 == (clk))) + +/*! Parameter validity check for fcm abnormal handle \a handle. */ +#define IS_FCM_HANDLE(handle) \ +( (ClkFcmHandleInterrupt == (handle)) || \ + (ClkFcmHandleReset == (handle))) + +/*! Parameter validity check for debug clock division \a div. */ +#define IS_TPIUCLK_DIV_VALID(div) \ +( (ClkTpiuclkDiv1 == (div)) || \ + (ClkTpiuclkDiv2 == (div)) || \ + (ClkTpiuclkDiv4 == (div))) + +/*! Parameter validity check for output clock division \a div. */ +#define IS_OUTPUTCLK_DIV_VALID(div) \ +( (ClkOutputDiv1 == (div)) || \ + ((ClkOutputDiv2 <= (div)) && \ + (ClkOutputDiv128 >= (div)))) + +/*! Parameter validity check for fcm measurement source division \a div. */ +#define IS_FCM_MEASRC_DIV_VALID(div) \ +( (ClkFcmMeaDiv1 == (div)) || \ + (ClkFcmMeaDiv4 == (div)) || \ + (ClkFcmMeaDiv8 == (div)) || \ + (ClkFcmMeaDiv32 == (div))) + +/*! Parameter validity check for internal reference source division \a div. */ +#define IS_FCM_INTREF_DIV_VALID(div) \ +( (ClkFcmIntrefDiv32 == (div)) || \ + (ClkFcmIntrefDiv128 == (div)) || \ + (ClkFcmIntrefDiv1024 == (div)) || \ + (ClkFcmIntrefDiv8192 == (div))) + +/*! Parameter validity check for system clock config \a cfg. */ +#define IS_SYSCLK_CONFIG_VALID(cfg) \ +( ((cfg)->enHclkDiv <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk3Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk4Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk3Div)) && \ + (((cfg)->enPclk2Div-(cfg)->enPclk4Div == 3) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 2) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 1) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 0) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 1) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 2) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 3))) + + +/*! Parameter validity check for clock status \a flag. */ +#define IS_CLK_FLAG(flag) \ +( (ClkFlagHRCRdy == (flag)) || \ + (ClkFlagXTALRdy == (flag)) || \ + (ClkFlagMPLLRdy == (flag)) || \ + (ClkFlagUPLLRdy == (flag)) || \ + (ClkFlagXTALStoppage == (flag))) +/*! Parameter validity check for fcm status \a flag. */ +#define IS_FCM_FLAG(flag) \ +( (ClkFcmFlagOvf == (flag)) || \ + (ClkFcmFlagMendf == (flag)) || \ + (ClkFcmFlagErrf == (flag))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the external high speed oscillator(XTAL). + ** + ** \param [in] pstcXtalCfg The XTAL configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg) +{ + if(NULL != pstcXtalCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALCFGR_f.SUPDRV = pstcXtalCfg->enFastStartup; + M4_SYSREG->CMU_XTALCFGR_f.XTALMS = pstcXtalCfg->enMode; + M4_SYSREG->CMU_XTALCFGR_f.XTALDRV = pstcXtalCfg->enDrv; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stable time. + ** + ** \param [in] enXtalStb The XTAL stable time. + ** + ** \retval None + ** + ** \note One of the stable clock is 1/8 LRC clock. + ** + ******************************************************************************/ +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb) +{ + DDL_ASSERT(IS_XTAL_STB_VALID(enXtalStb)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTBCR_f.XTALSTB = enXtalStb; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stoppage. + ** + ** \param [in] pstcXtalStpCfg The XTAL stoppage configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg) +{ + if(NULL != pstcXtalStpCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDE = pstcXtalStpCfg->enDetect; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRIS = pstcXtalStpCfg->enMode; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRE = pstcXtalStpCfg->enModeReset; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDIE = pstcXtalStpCfg->enModeInt; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL. + ** + ** \param [in] enNewState The new state of the XTAL. + ** \arg Enable Enable XTAL. + ** \arg Disable Disable XTAL. + ** + ** \retval en_result_t + ** + ** \note XTAL can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 0u; + enRet = ErrorTimeout; + while (timeout < CLK_XTAL_TIMEOUT) + { + if (Set == CLK_GetFlagStatus(ClkFlagXTALRdy)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the external low speed oscillator(XTAL32). + ** + ** \param [in] pstcXtal32Cfg The XTAL32 configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg) +{ + if(NULL != pstcXtal32Cfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTAL32CFGR_f.XTAL32DRV = pstcXtal32Cfg->enDrv; + M4_SYSREG->CMU_XTAL32NFR_f.XTAL32NF = pstcXtal32Cfg->enFilterMode; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL32. + ** + ** \param [in] enNewState The new state of the XTAL32. + ** \arg Enable Enable XTAL32. + ** \arg Disable Disable XTAL32. + ** + ** \retval en_result_t + ** + ** \note XTAL32 can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL32 == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 0u; + do + { + timeout++; + }while(timeout < CLK_XTAL32_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal high speed oscillator(HRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_HrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_HRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the HRC. + ** + ** \param [in] enNewState The new state of the HRC. + ** \arg Enable Enable HRC. + ** \arg Disable Disable HRC. + ** + ** \retval en_result_t + ** + ** \note HRC can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + ENABLE_CLOCK_REG_WRITE(); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if(Disable == enNewState) + { + if(ClkSysSrcHRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcHRC == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 0u; + enRet = ErrorTimeout; + while (timeout < CLK_HRC_TIMEOUT) + { + if (Set == CLK_GetFlagStatus(ClkFlagHRCRdy)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal middle speed oscillator(MRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_MrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_MRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MRC. + ** + ** \param [in] enNewState The new state of the MRC. + ** \arg Enable Enable MRC. + ** \arg Disable Disable MRC. + ** + ** \retval en_result_t + ** + ** \note MRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcMRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_MRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal low speed oscillator(LRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_LrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_LRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the LRC. + ** + ** \param [in] enNewState The new state of the LRC. + ** \arg Enable Enable LRC. + ** \arg Disable Disable LRC. + ** + ** \retval en_result_t + ** + ** \note LRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcLRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_LRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select pll clock source. + ** + ** \param [in] enPllSrc The pll clock source. + ** \arg ClkPllSrcXTAL Select XTAL as pll clock source. + ** \arg ClkPllSrcHRC Select HRC as pll clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc) +{ + DDL_ASSERT(IS_PLL_SOURCE(enPllSrc)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.PLLSRC = enPllSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the MPLL. + ** + ** \param [in] pstcMpllCfg The MPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcMpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLLQ_DIV_VALID(pstcMpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcMpllCfg->plln)); + DDL_ASSERT(IS_PLLM_VALID(pstcMpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcMpllCfg->pllmDiv); + vcoOut = vcoIn * pstcMpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.MPLLP = pstcMpllCfg->PllpDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLQ = pstcMpllCfg->PllqDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLR = pstcMpllCfg->PllrDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLN = pstcMpllCfg->plln - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLM = pstcMpllCfg->pllmDiv - 1ul; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MPLL. + ** + ** \param [in] enNewState The new state of the MPLL. + ** \arg Enable Enable MPLL. + ** \arg Disable Disable MPLL. + ** + ** \retval en_result_t + ** + ** \note MPLL can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 0u; + enRet = ErrorTimeout; + while (timeout < CLK_MPLL_TIMEOUT) + { + if (Set == CLK_GetFlagStatus(ClkFlagMPLLRdy)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the UPLL. + ** + ** \param [in] pstcUpllCfg The UPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcUpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcUpllCfg->plln)); + DDL_ASSERT(IS_UPLLM_VALID(pstcUpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcUpllCfg->pllmDiv); + vcoOut = vcoIn * pstcUpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCFGR_f.UPLLP = pstcUpllCfg->PllpDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ = pstcUpllCfg->PllqDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLR = pstcUpllCfg->PllrDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLN = pstcUpllCfg->plln - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLM = pstcUpllCfg->pllmDiv - 1u; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the UPLL. + ** + ** \param [in] enNewState The new state of the UPLL. + ** \arg Enable Enable UPLL. + ** \arg Disable Disable UPLL. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t CLK_UpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCR_f.UPLLOFF = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_CLOCK_REG_WRITE(); + + if (Disable == enNewState) + { + timeout = 0ul; + while (Reset != CLK_GetFlagStatus(ClkFlagUPLLRdy)) + { + timeout++; + if (timeout > CLK_UPLL_TIMEOUT) + { + return ErrorTimeout; + } + } + } + else + { + timeout = 0ul; + while (Set != CLK_GetFlagStatus(ClkFlagUPLLRdy)) + { + timeout++; + if (timeout > CLK_UPLL_TIMEOUT) + { + return ErrorTimeout; + } + } + } + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] enTargetSysSrc The system clock source. + ** \arg ClkSysSrcHRC Select HRC as system clock source. + ** \arg ClkSysSrcMRC Select MRC as system clock source. + ** \arg ClkSysSrcLRC Select LRC as system clock source. + ** \arg ClkSysSrcXTAL Select XTAL as system clock source. + ** \arg ClkSysSrcXTAL32 Select XTAL32 as system clock source. + ** \arg CLKSysSrcMPLL Select MPLL as system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** + ******************************************************************************/ +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + DDL_ASSERT(IS_SYSCLK_SOURCE(enTargetSysSrc)); + + ENABLE_FCG0_REG_WRITE(); + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) || + (CLKSysSrcMPLL == enTargetSysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = enTargetSysSrc; + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + + SystemCoreClockUpdate(); +} + +/** + ******************************************************************************* + ** \brief Get system clock source. + ** + ** \param None + ** + ** \retval The system clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_sys_source_t CLK_GetSysClkSource(void) +{ + return (en_clk_sys_source_t)M4_SYSREG->CMU_CKSWR_f.CKSW; +} + + +/** + ******************************************************************************* + ** \brief Configures the division factor for hclk,exck,pclk0,pclk1,pclk2,pclk3, + ** pclk4 from system clock. + ** + ** \param [in] pstcSysclkCfg The system clock configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + ENABLE_FCG0_REG_WRITE(); + + if(NULL != pstcSysclkCfg) + { + DDL_ASSERT(IS_SYSCLK_CONFIG_VALID(pstcSysclkCfg)); + + /* Only current system clock source is MPLL need to close fcg0~fcg3 and + open fcg0~fcg3 during switch system clock division. + We need to backup fcg0~fcg3 before close them. */ + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock division. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_SCFGR = ( (uint32_t)pstcSysclkCfg->enPclk0Div | + ((uint32_t)pstcSysclkCfg->enPclk1Div << 4u) | + ((uint32_t)pstcSysclkCfg->enPclk2Div << 8u) | + ((uint32_t)pstcSysclkCfg->enPclk3Div << 12u) | + ((uint32_t)pstcSysclkCfg->enPclk4Div << 16u) | + ((uint32_t)pstcSysclkCfg->enExclkDiv << 20u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 24u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 28u)); + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + else + { + /* code */ + } +} + + +/** + ******************************************************************************* + ** \brief Get clock frequency. + ** + ** \param [in] pstcClkFreq The clock source struct. + ** + ** \retval The clock frequency include system clock,hclk,exck,pclk0,pclk1,pclk2 + ** pclk3,pclk4. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq) +{ + uint32_t plln = 0u, pllp = 0u, pllm = 0u, pllsource = 0u; + + if(NULL != pstcClkFreq) + { + /* Get system clock. */ + switch(M4_SYSREG->CMU_CKSWR_f.CKSW) + { + case ClkSysSrcHRC: + /* HRC used as system clock. */ + pstcClkFreq->sysclkFreq = HRC_VALUE; + break; + case ClkSysSrcMRC: + /* MRC used as system clock. */ + pstcClkFreq->sysclkFreq = MRC_VALUE; + break; + case ClkSysSrcLRC: + /* LRC used as system clock. */ + pstcClkFreq->sysclkFreq = LRC_VALUE; + break; + case ClkSysSrcXTAL: + /* XTAL used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL_VALUE; + break; + case ClkSysSrcXTAL32: + /* XTAL32 used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL32_VALUE; + break; + default: + /* MPLLP used as system clock. */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + if (ClkPllSrcXTAL == pllsource) + { + pstcClkFreq->sysclkFreq = (XTAL_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcClkFreq->sysclkFreq = (HRC_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else + { + //else + } + break; + } + + /* Get hclk. */ + pstcClkFreq->hclkFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.HCLKS; + + /* Get exck. */ + pstcClkFreq->exckFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.EXCKS; + + /* Get pclk0. */ + pstcClkFreq->pclk0Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK0S; + + /* Get pclk1. */ + pstcClkFreq->pclk1Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK1S; + + /* Get pclk2. */ + pstcClkFreq->pclk2Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK2S; + + /* Get pclk3. */ + pstcClkFreq->pclk3Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK3S; + + /* Get pclk4. */ + pstcClkFreq->pclk4Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK4S; + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Get PLL clock frequency. + ** + ** \param [in] pstcPllClkFreq The PLL clock source struct. + ** + ** \retval The clock frequency include mpllp, mpllq, mpllr, upllp, upllq, upllr. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq) +{ + uint32_t pllsource; + uint32_t mplln = 0u, mpllp = 0u, mpllq = 0u, mpllr = 0u, mpllm = 0u; + uint32_t uplln = 0u, upllp = 0u, upllq = 0u, upllr = 0u, upllm = 0u; + + /* Get pll clock source */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + + /* Get Mpll parameter value */ + mpllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + mpllq = M4_SYSREG->CMU_PLLCFGR_f.MPLLQ; + mpllr = M4_SYSREG->CMU_PLLCFGR_f.MPLLR; + mplln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + mpllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* Get Upll paramter value */ + upllp = M4_SYSREG->CMU_UPLLCFGR_f.UPLLP; + upllq = M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ; + upllr = M4_SYSREG->CMU_UPLLCFGR_f.UPLLR; + uplln = M4_SYSREG->CMU_UPLLCFGR_f.UPLLN; + upllm = M4_SYSREG->CMU_UPLLCFGR_f.UPLLM; + + /* Get mpllp ,mpllr, mpllq, upllp, upllq, upllr clock frequency */ + if (ClkPllSrcXTAL == pllsource) + { + pstcPllClkFreq->mpllp = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcPllClkFreq->mpllp = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Select usb clock source. + ** + ** \param [in] enTargetUsbSrc The usb clock source. + ** \arg ClkUsbSrcSysDiv2 Select 1/2 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv3 Select 1/3 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv4 Select 1/4 system clock as usb clock source. + ** \arg ClkUsbSrcMpllp Select MPLLP as usb clock source. + ** \arg ClkUsbSrcMpllq Select MPLLQ as usb clock source. + ** \arg ClkUsbSrcMpllr Select MPLLR as usb clock source. + ** \arg ClkUsbSrcUpllp Select UPLLP as usb clock source. + ** \arg ClkUsbSrcUpllq Select UPLLQ as usb clock source. + ** \arg ClkUsbSrcUpllr Select UPLLR as usb clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc) +{ + + DDL_ASSERT(IS_USBCLK_SOURCE(enTargetUsbSrc)); + + /* Switch to target usb clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UFSCKCFGR_f.USBCKS = enTargetUsbSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select peripheral(adc/trng) clock source. + ** + ** \param [in] enTargetPeriSrc The peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcPclk Select PCLK2 as adc analog clok, PCLK4 as adc digital clock. Select PCLK4 as trng clock. + ** \arg ClkPeriSrcMpllp Select MPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as peripheral(adc/trng) clock source. + ** + ** \retval None + ** + ******************************************************************************/ +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + /* Switch to target adc clock source. */ + M4_SYSREG->CMU_PERICKSEL_f.PERICKSEL = enTargetPeriSrc; + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] enTargetPeriSrc The I2S clock source. + ** \arg ClkPeriSrcPclk Select PCLK3 as I2S clock source. + ** \arg ClkPeriSrcMpllp Select MPLLP as I2S clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as I2S clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as I2S clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as I2S clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as I2S clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as I2S clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + if(M4_I2S1 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL = enTargetPeriSrc; + } + else if(M4_I2S2 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL = enTargetPeriSrc; + } + else if(M4_I2S3 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL = enTargetPeriSrc; + } + else if(M4_I2S4 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL = enTargetPeriSrc; + } + else + { + /* code */ + } + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval en_clk_peri_source_t The I2S clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg) +{ + en_clk_peri_source_t enI2sClkSource = ClkPeriSrcPclk; + + if(M4_I2S1 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL; + } + else if(M4_I2S2 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL; + } + else if(M4_I2S3 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL; + } + else if(M4_I2S4 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL; + } + else + { + /* code */ + } + + return enI2sClkSource; +} + +/** + ******************************************************************************* + ** \brief Configures the debug clock. + ** + ** \param [in] enTpiuDiv The division of debug clock from system + ** clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv) +{ + DDL_ASSERT(IS_TPIUCLK_DIV_VALID(enTpiuDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKS = enTpiuDiv; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the debug clock. + ** + ** \param [in] enNewState The new state of the debug clock. + ** \arg Enable Enable debug clock. + ** \arg Disable Disable debug clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKOE = enNewState; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the output clock. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] pstcOutputCfg The clock output configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg) +{ + if(NULL != pstcOutputCfg) + { + DDL_ASSERT(IS_OUTPUTCLK_CHANNEL(enCh)); + DDL_ASSERT(IS_OUTPUTCLK_SOURCE(pstcOutputCfg->enOutputSrc)); + DDL_ASSERT(IS_OUTPUTCLK_DIV_VALID(pstcOutputCfg->enOutputDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO1CFGR_f.MCO1DIV = pstcOutputCfg->enOutputDiv; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO2CFGR_f.MCO2DIV = pstcOutputCfg->enOutputDiv; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock output. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1EN = enNewState; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2EN = enNewState; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); +} + + +/** + ******************************************************************************* + ** \brief Get the specified clock flag status. + ** + ** \param [in] enClkFlag The specified clock flag. + ** \arg ClkFlagHRCRdy HRC is ready or not. + ** \arg ClkFlagXTALRdy XTAL is ready or not. + ** \arg ClkFlagMPLLRdy MPLL is ready or not. + ** \arg ClkFlagUPLLRdy UPLL is ready or not. + ** \arg ClkFlagXTALStoppage XTAL is detected stoppage or not. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag) +{ + en_flag_status_t status; + + DDL_ASSERT(IS_CLK_FLAG(enClkFlag)); + + switch(enClkFlag) + { + case ClkFlagHRCRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF) ? Set : Reset); + break; + case ClkFlagXTALRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.XTALSTBF) ? Set : Reset); + break; + case ClkFlagMPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.MPLLSTBF) ? Set : Reset); + break; + case ClkFlagUPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.UPLLSTBF) ? Set : Reset); + break; + default: + status = ((1u == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) ? Set : Reset); + break; + } + + return status; +} + + +/** + ******************************************************************************* + ** \brief Configures the clock frequency measurement. + ** + ** \param [in] pstcClkFcmCfg The clock frequency measurement configures + ** struct. + ** + ** \retval None + ** + ** \note Configures the window,measurement,reference and interrupt independently. + ** + ******************************************************************************/ +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg) +{ + if(NULL != pstcClkFcmCfg) + { + /* Window config. */ + if(pstcClkFcmCfg->pstcFcmWindowCfg) + { + /* Set window lower. */ + M4_FCM->LVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowLower; + /* Set window upper. */ + M4_FCM->UVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowUpper; + } + + /* Measure config. */ + if(pstcClkFcmCfg->pstcFcmMeaCfg) + { + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmMeaCfg->enSrc)); + DDL_ASSERT(IS_FCM_MEASRC_DIV_VALID(pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv)); + + /* Measure source. */ + M4_FCM->MCCR_f.MCKS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrc; + /* Measure source division. */ + M4_FCM->MCCR_f.MDIVS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv; + } + + /* Reference config. */ + if(pstcClkFcmCfg->pstcFcmRefCfg) + { + DDL_ASSERT(IS_FCM_REF(pstcClkFcmCfg->pstcFcmRefCfg->enRefSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmRefCfg->enExtRef)); + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc)); + DDL_ASSERT(IS_FCM_INTREF_DIV_VALID(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv)); + DDL_ASSERT(IS_FCM_EDGE(pstcClkFcmCfg->pstcFcmRefCfg->enEdge)); + DDL_ASSERT(IS_FCM_FILTER_CLK(pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk)); + + M4_FCM->RCCR_f.INEXS = pstcClkFcmCfg->pstcFcmRefCfg->enRefSel; + M4_FCM->RCCR_f.EXREFE = pstcClkFcmCfg->pstcFcmRefCfg->enExtRef; + M4_FCM->RCCR_f.RCKS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc; + M4_FCM->RCCR_f.RDIVS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv; + M4_FCM->RCCR_f.EDGES = pstcClkFcmCfg->pstcFcmRefCfg->enEdge; + M4_FCM->RCCR_f.DNFS = pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk; + } + + /* Interrupt config. */ + if(pstcClkFcmCfg->pstcFcmIntCfg) + { + DDL_ASSERT(IS_FCM_HANDLE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt)); + + M4_FCM->RIER_f.ERRINTRS = pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel; + M4_FCM->RIER_f.ERRE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset; + M4_FCM->RIER_f.ERRIE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt; + M4_FCM->RIER_f.MENDIE = pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt; + M4_FCM->RIER_f.OVFIE = pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt; + } + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock frequency measurement. + ** + ** \param [in] enNewState The new state of the clock frequency + ** measurement. + ** \arg Enable Enable clock frequency measurement. + ** \arg Disable Disable clock frequency measurement. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_FcmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_FCM->STR = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get fcm counter value. + ** + ** \param None + ** + ** \retval The fcm counter value. + ** + ** \note None + ** + ******************************************************************************/ +uint16_t CLK_GetFcmCounter(void) +{ + return (uint16_t)(M4_FCM->CNTR & 0xFFFFu); +} + +/** + ******************************************************************************* + ** \brief Get the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf The fcm counter overflow or not. + ** \arg ClkFcmFlagMendf The end of the measurement or not. + ** \arg ClkFcmFlagErrf Whether the frequency is abnormal or not. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + en_flag_status_t status = Reset; + + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + status = (en_flag_status_t)M4_FCM->SR_f.OVF; + break; + case ClkFcmFlagMendf: + status = (en_flag_status_t)M4_FCM->SR_f.MENDF; + break; + case ClkFcmFlagErrf: + status = (en_flag_status_t)M4_FCM->SR_f.ERRF; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief Clear the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf Clear the fcm counter overflow flag. + ** \arg ClkFcmFlagMendf Clear the end of the measurement flag. + ** \arg ClkFcmFlagErrf Clear the frequency abnormal flag. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + M4_FCM->CLR_f.OVFCLR = Set; + break; + case ClkFcmFlagMendf: + M4_FCM->CLR_f.MENDFCLR = Set; + break; + case ClkFcmFlagErrf: + M4_FCM->CLR_f.ERRFCLR = Set; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Clear the XTAL error flag. + ** + ** \param None + ** + ** \retval None + ** + ** \note The system clock should not be XTAL before call this function. + ** + ******************************************************************************/ +void CLK_ClearXtalStdFlag(void) +{ + /* Enable register write. */ + ENABLE_CLOCK_REG_WRITE(); + + if(Set == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) + { + /* Clear the XTAL STD flag */ + M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF = Reset; + } + + /* Disbale register write. */ + DISABLE_CLOCK_REG_WRITE(); +} + + +//@} // CmuGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_cmp.c b/lib/hc32f460/driver/src/hc32f460_cmp.c new file mode 100644 index 000000000000..ef87ccd922f4 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_cmp.c @@ -0,0 +1,1042 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.c + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_cmp.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup CmpGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for CMP Instances. */ +#define IS_VALID_CMP(__CMPx__) \ +( (M4_CMP1 == (__CMPx__)) || \ + (M4_CMP2 == (__CMPx__)) || \ + (M4_CMP3 == (__CMPx__))) + +/*!< Parameter valid check for CMP function */ +#define IS_VALID_CMP_FUNCTION(x) \ +( (CmpOutput == (x)) || \ + (CmpOutpuInv == (x)) || \ + (CmpVcoutOutput == (x))) + +/*! Parameter validity check for edge sel. */ +#define IS_VALID_EDGESEL(x) \ +( (CmpNoneEdge == (x)) || \ + (CmpBothEdge == (x)) || \ + (CmpRisingEdge == (x)) || \ + (CmpFaillingEdge == (x))) + +/*!< Parameter CMP FLT validity check for clock division. */ +#define IS_VALID_FLTCLK_DIVISION(x) \ +( (CmpNoneFlt == (x)) || \ + (CmpFltPclk3Div1 == (x)) || \ + (CmpFltPclk3Div2 == (x)) || \ + (CmpFltPclk3Div4 == (x)) || \ + (CmpFltPclk3Div8 == (x)) || \ + (CmpFltPclk3Div16 == (x)) || \ + (CmpFltPclk3Div32 == (x)) || \ + (CmpFltPclk3Div64 == (x))) + +/*!< Parameter validity check for INP4 SEL. */ +#define IS_VALID_INP4SEL(x) \ +( (CmpInp4None == (x)) || \ + (CmpInp4PGAO == (x)) || \ + (CmpInp4PGAO_BP == (x)) || \ + (CmpInp4CMP1_INP4 == (x))) + +/*!< Parameter validity check for INP INPUT SEL. */ +#define IS_VALID_INPSEL(x) \ +( (CmpInpNone == (x)) || \ + (CmpInp1 == (x)) || \ + (CmpInp2 == (x)) || \ + (CmpInp3 == (x)) || \ + (CmpInp4 == (x)) || \ + (CmpInp1_Inp2 == (x)) || \ + (CmpInp1_Inp3 == (x)) || \ + (CmpInp2_Inp3 == (x)) || \ + (CmpInp1_Inp4 == (x)) || \ + (CmpInp2_Inp4 == (x)) || \ + (CmpInp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3 == (x)) || \ + (CmpInp1_Inp2_Inp4 == (x)) || \ + (CmpInp1_Inp3_Inp4 == (x)) || \ + (CmpInp2_Inp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3_Inp4 == (x))) + +/*!< Parameter validity check for INM INPUT SEL. */ +#define IS_VALID_INMSEL(x) \ +( (CmpInm1 == (x)) || \ + (CmpInm2 == (x)) || \ + (CmpInm3 == (x)) || \ + (CmpInm4 == (x)) || \ + (CmpInmNone == (x))) + +/*!< Parameter validity check for CMP_CR channel. */ +#define IS_VALID_CMP_CR_CH(x) \ +( (CmpDac1 == (x)) || \ + (CmpDac2 == (x))) + +/*!< Parameter validity check for ADC internal reference voltage path. */ +#define IS_VALID_ADC_REF_VOLT_PATH(x) \ +( (CmpAdcRefVoltPathDac1 == (x)) || \ + (CmpAdcRefVoltPathDac2 == (x)) || \ + (CmpAdcRefVoltPathVref == (x))) + +/*!< RVADC Write Protection Key. */ +#define RVADC_WRITE_PROT_KEY (0x5500u) + +/*!< Timer4x ECER register address. */ +#define CMP_CR_DADRx(__DACx__) \ +( (CmpDac1 == (__DACx__)) ? &M4_CMP_CR->DADR1 : &M4_CMP_CR->DADR2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the specified CMP. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CMP configure structure + ** \arg This parameter detail refer @ref stc_cmp_init_t + ** + ** \retval Ok CMP is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - CMPx is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInitCfg pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInitCfg)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(pstcInitCfg->enEdgeSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpIntEN)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpInvEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpOutputEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpVcoutOutputEn)); + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(pstcInitCfg->enFltClkDiv)); + + /* De-Initialize CMP */ + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + + CMPx->CTRL_f.IEN = (uint16_t)pstcInitCfg->enCmpIntEN; + CMPx->CTRL_f.INV = (uint16_t)pstcInitCfg->enCmpInvEn; + CMPx->CTRL_f.EDGSL = (uint16_t)pstcInitCfg->enEdgeSel; + CMPx->CTRL_f.FLTSL = (uint16_t)pstcInitCfg->enFltClkDiv; + CMPx->CTRL_f.CMPOE = (uint16_t)pstcInitCfg->enCmpOutputEn; + CMPx->CTRL_f.OUTEN = (uint16_t)pstcInitCfg->enCmpVcoutOutputEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP working + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP function state + ** \arg Disable Disable CMP working + ** \arg Enable Enable CMP working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + CMPx->CTRL_f.CMPON = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP interrupt request + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP interrupt function state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.IEN = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan time(scan stable&&period) + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] u8ScanStable CMP scan stable value + ** \arg u8ScanStable < 16 + ** \param [in] u8ScanPeriod CMP scan period value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ** \note u8ScanStable && u8ScanPeriod value must meet following condition: + ** u8ScanPeriod > u8ScanStable + FLTSL_DIV*4 + 5 + ** FLTSL_DIV is filter sample period division(refer CMPx->CTRL_f.FLTSL) + ** + ******************************************************************************/ +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod) +{ + uint16_t u16Flts; + uint16_t u16FltslDiv; + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if ((!IS_VALID_CMP(CMPx)) || (u8ScanStable & 0xF0u)) + { + enRet = ErrorInvalidParameter; + } + else + { + u16Flts = CMPx->CTRL_f.FLTSL; + u16FltslDiv = ((uint16_t)1u << (u16Flts - 1u)); + + if ((0u != u16Flts) && + (u8ScanPeriod <= (u8ScanStable + u16FltslDiv * 4u + 5u))) + { + enRet = ErrorInvalidParameter; + } + else + { + CMPx->CVSSTB_f.STB = u8ScanStable; + CMPx->CVSPRD_f.PRD = u8ScanPeriod; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified CMP function. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFunc CMP function selection + ** \arg CmpVcoutOutput CMP Vcout output enable function + ** \arg CmpOutpuInv CMP output invert enable function + ** \arg CmpOutput CMP output enable function + ** \param [in] enCmd CMP functional state + ** \arg Enable Enable the specified CMP function + ** \arg Disable Disable the specified CMP function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CMP_FUNCTION(enFunc)); + + if (Enable == enCmd) + { + CMPx->CTRL |= (uint16_t)enFunc; + } + else + { + CMPx->CTRL &= (uint16_t)(~((uint16_t)enFunc)); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Start successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Stop successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFltClkDiv The CMP filter sample clock division selection + ** \arg CmpNoneFlt Unuse filter + ** \arg CmpFltPclk3Div1 PCLK3/1 + ** \arg CmpFltPclk3Div2 PCLK3/2 + ** \arg CmpFltPclk3Div4 PCLK3/4 + ** \arg CmpFltPclk3Div8 PCLK3/8 + ** \arg CmpFltPclk3Div16 PCLK3/16 + ** \arg CmpFltPclk3Div32 PCLK3/32 + ** \arg CmpFltPclk3Div64 PCLK3/64 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(enFltClkDiv)); + CMPx->CTRL_f.FLTSL = (uint16_t)enFltClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneFlt Unuse filter + ** \retval CmpFltPclk3Div1 PCLK3/1 + ** \retval CmpFltPclk3Div2 PCLK3/2 + ** \retval CmpFltPclk3Div4 PCLK3/4 + ** \retval CmpFltPclk3Div8 PCLK3/8 + ** \retval CmpFltPclk3Div16 PCLK3/16 + ** \retval CmpFltPclk3Div32 PCLK3/32 + ** \retval CmpFltPclk3Div64 PCLK3/64 + ** + ******************************************************************************/ +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_fltclk_div_t)CMPx->CTRL_f.FLTSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enEdgeSel The CMP detection edge selection + ** \arg CmpNoneEdge None edge detection + ** \arg CmpRisingEdge Rising edge detection + ** \arg CmpFaillingEdge Falling edge detection + ** \arg CmpBothEdge Falling or Rising edge detection + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(enEdgeSel)); + CMPx->CTRL_f.EDGSL = (uint16_t)enEdgeSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneEdge None edge detection + ** \retval CmpRisingEdge Rising edge detection + ** \retval CmpFaillingEdge Falling edge detection + ** \retval CmpBothEdge Falling or Rising edge detection + ** + ******************************************************************************/ +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_edge_sel_t)CMPx->CTRL_f.EDGSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP input sel + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInputSel The CMP input selection structure + ** \arg This parameter detail refer @ref stc_cmp_input_sel_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInputSel pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInputSel)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(pstcInputSel->enInmSel)); + DDL_ASSERT(IS_VALID_INPSEL(pstcInputSel->enInpSel)); + DDL_ASSERT(IS_VALID_INP4SEL(pstcInputSel->enInp4Sel)); + + if ((CmpInp4PGAO == pstcInputSel->enInp4Sel) || + (CmpInp4PGAO_BP == pstcInputSel->enInp4Sel)) + { + if (M4_CMP3 != CMPx) + { + enRet = Ok; + } + } + else if (CmpInp4CMP1_INP4 == pstcInputSel->enInp4Sel) + { + if (M4_CMP1 == CMPx) + { + enRet = Ok; + } + } + else + { + enRet = Ok; + } + + if (enRet == Ok) + { + CMPx->VLTSEL_f.CVSL = (uint16_t)pstcInputSel->enInpSel; + CMPx->VLTSEL_f.RVSL = (uint16_t)pstcInputSel->enInmSel; + CMPx->VLTSEL_f.C4SL = (uint16_t)pstcInputSel->enInp4Sel; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInpNone None input + ** \arg CmpInp1 INP1 input + ** \arg CmpInp2 INP2 input + ** \arg CmpInp1_Inp2 INP1 INP2 input + ** \arg CmpInp3 INP3 input + ** \arg CmpInp1_Inp3 INP1 INP3 input + ** \arg CmpInp2_Inp3 INP2 INP3 input + ** \arg CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \arg CmpInp4 INP4 input + ** \arg CmpInp1_Inp4 INP1 INP4 input + ** \arg CmpInp2_Inp4 INP2 INP4 input + ** \arg CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \arg CmpInp3_Inp4 INP3 INP4 input + ** \arg CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \arg CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \arg CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INPSEL(enInputSel)); + CMPx->VLTSEL_f.CVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInpNone None input + ** \retval CmpInp1 INP1 input + ** \retval CmpInp2 INP2 input + ** \retval CmpInp1_Inp2 INP1 INP2 input + ** \retval CmpInp3 INP3 input + ** \retval CmpInp1_Inp3 INP1 INP3 input + ** \retval CmpInp2_Inp3 INP2 INP3 input + ** \retval CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \retval CmpInp4 INP4 input + ** \retval CmpInp1_Inp4 INP1 INP4 input + ** \retval CmpInp2_Inp4 INP2 INP4 input + ** \retval CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \retval CmpInp3_Inp4 INP3 INP4 input + ** \retval CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \retval CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \retval CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ******************************************************************************/ +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_sel_t)CMPx->VLTSEL_f.CVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInmNone None input + ** \arg CmpInm1 INM1 input + ** \arg CmpInm2 INM2 input + ** \arg CmpInm3 INM3 input + ** \arg CmpInm4 INM4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(enInputSel)); + CMPx->VLTSEL_f.RVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInmNone None input + ** \retval CmpInm1 INM1 input + ** \retval CmpInm2 INM2 input + ** \retval CmpInm3 INM3 input + ** \retval CmpInm4 INM4 input + ** + ******************************************************************************/ +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inm_sel_t)CMPx->VLTSEL_f.RVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInp4None None input + ** \arg CmpInp4PGAO PGAO output + ** \arg CmpInp4PGAO_BP PGAO_BP output + ** \arg CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + DDL_ASSERT(M4_CMP3 != CMPx); + DDL_ASSERT(IS_VALID_INP4SEL(enInputSel)); + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->VLTSEL_f.C4SL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInp4None None input + ** \retval CmpInp4PGAO PGAO output + ** \retval CmpInp4PGAO_BP PGAO_BP output + ** \retval CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp4_sel_t)CMPx->VLTSEL_f.C4SL; +} + +/** + ******************************************************************************* + ** \brief Get CMP output state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_output_state_t)(CMPx->OUTMON_f.OMON); +} + +/** + ******************************************************************************* + ** \brief Get CMP INP state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_state_t)(CMPx->OUTMON_f.CVST); +} + +/** + ******************************************************************************* + ** \brief Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] pstcInitCfg Pointer to CMP DAC configure structure + ** \arg This parameter detail refer @ref stc_cmp_dac_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_CMP_CR_CH(enCh)) && (pstcInitCfg != NULL)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpDacEN)); + + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); /* Disable DAC */ + + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = pstcInitCfg->u8DacData; /* Set DAC data */ + + if (Enable == pstcInitCfg->enCmpDacEN) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); /* Enable DAC */ + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP DAC working + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP DAC channel: DAC1 + ** \arg CmpDac2 CMP DAC channel: DAC2 + ** \param [in] enCmd The CMP DAC function state + ** \arg Disable Disable CMP DAC working + ** \arg Enable Enable CMP DAC working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + if(Enable == enCmd) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); + } + else + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] u8DacData DAC data register value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = u8DacData; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval DAC data register value + ** + ******************************************************************************/ +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP_CR_CH(enCh)); + + return *(__IO uint8_t *)CMP_CR_DADRx(enCh); +} + +/** + ******************************************************************************* + ** \brief Set ADC internal reference voltage path + ** + ** \param [in] enRefVoltPath ADC internal reference voltage path + ** \arg CmpAdcRefVoltPathDac1 ADC internal reference voltage path: DAC1 + ** \arg CmpAdcRefVoltPathDac2 ADC internal reference voltage path: DAC2 + ** \arg CmpAdcRefVoltPathVref ADC internal reference voltage path: VREF + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enRefVoltPath is invalid. + ** + ******************************************************************************/ +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_ADC_REF_VOLT_PATH(enRefVoltPath)) + { + M4_CMP_CR->RVADC = RVADC_WRITE_PROT_KEY; /* Release write protection */ + M4_CMP_CR->RVADC = enRefVoltPath; /* Set reference voltage path */ + enRet = Ok; + } + + return enRet; +} + +//@} // CmpGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_crc.c b/lib/hc32f460/driver/src/hc32f460_crc.c new file mode 100644 index 000000000000..c5d4f2be6523 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_crc.c @@ -0,0 +1,323 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.c + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_crc.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Definition of CRC16 data register. */ +#define M4_CRC16_DAT (*((__IO uint16_t *)&M4_CRC->DAT0)) + +/* Definition of CRC16 checksum register. */ +#define M4_CRC16_RSLT (*((__IO uint16_t *)&M4_CRC->RESLT)) + +/* Definition of CRC16 initial value register. */ +#define M4_CRC16_INIT (M4_CRC16_RSLT) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum); +static uint32_t CRC_ReverseBits(uint32_t u32Data); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the CRC. + ** + ** \param [in] u32Config Bit[1]: CRC_SEL_16B or CRC_SEL_32B. + ** Bit[2]: CRC_REFIN_DISABLE or CRC_REFIN_ENABLE. + ** Bit[3]: CRC_REFOUT_DISABLE or CRC_REFOUT_ENABLE. + ** Bit[4]: CRC_XOROUT_DISABLE or CRC_XOROUT_ENABLE. + ** See the definitions for details. + ** + ** \retval None + ** + ******************************************************************************/ +void CRC_Init(uint32_t u32Config) +{ + u32Config &= CRC_CONFIG_MASK; + + M4_CRC->CR = u32Config; +} + +/** + ******************************************************************************* + ** \brief CRC16 calculation. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 16-bit CRC checksum. + ** + ******************************************************************************/ +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length) +{ + uint16_t u16Ret = 0u; + uint32_t u32Count; + + if (NULL != pu16Data) + { + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + u16Ret = M4_CRC16_RSLT; + } + + return u16Ret; +} + +/** + ******************************************************************************* + ** \brief CRC32 calculation. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 32-bit CRC checksum. + ** + ******************************************************************************/ +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length) +{ + uint32_t u32Ret = 0u; + uint32_t u32Count; + + M4_CRC->RESLT = u32InitVal; + + if (NULL != pu32Data) + { + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + u32Ret = M4_CRC->RESLT; + } + + return u32Ret; +} + +/** + ******************************************************************************* + ** \brief CRC16 check. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] u16Checksum CRC16 checksum of the source data. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC16 checks successfully. + ** \retval false CRC16 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16Checksum, const uint16_t *pu16Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint16_t u16CrcChecksum; + + if (NULL != pu16Data) + { + u16CrcChecksum = (uint16_t)CRC_ProcChecksum((uint32_t)u16Checksum); + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + M4_CRC16_DAT = u16CrcChecksum; + + if (bM4_CRC_RESLT_CRCFLAG_16) + { + bRet = true; + } + } + + return bRet; +} + +/** + ******************************************************************************* + ** \brief CRC32 check. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] u32Checksum CRC32 checksum of the source data. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC32 checks successfully. + ** \retval false CRC32 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32Checksum, const uint32_t *pu32Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint32_t u32CrcChecksum; + + if (NULL != pu32Data) + { + u32CrcChecksum = CRC_ProcChecksum(u32Checksum); + M4_CRC->RESLT = u32InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + M4_CRC->DAT0 = u32CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Processes the checksum of CRC. + ** + ** \param [in] u32Checksum The checksum of CRC16 or CRC32. + ** + ** \retval 32-bit new checksum will be used by CRC checking. + ** + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum) +{ + uint8_t i; + uint8_t u8Size = 16u; + uint8_t u8Offset; + uint32_t u32Config; + uint32_t u32FinalChecksum; + uint32_t u32Temp; + + u32Config = M4_CRC->CR; + u32FinalChecksum = u32Checksum; + + if ((u32Config & CRC_SEL_32B) == CRC_SEL_32B) + { + u8Size = 32u; + } + + if ((u32Config & CRC_REFOUT_ENABLE) == CRC_REFOUT_DISABLE) + { + /* Bits reversing. */ + u32FinalChecksum = CRC_ReverseBits(u32Checksum); + if (u8Size == 16u) + { + u32FinalChecksum >>= 16u; + u32FinalChecksum &= 0xFFFFu; + } + } + + if ((u32Config & CRC_XOROUT_ENABLE) == CRC_XOROUT_DISABLE) + { + /* Bits NOT. */ + u32FinalChecksum = ~u32FinalChecksum; + } + + if ((u32Config & CRC_REFIN_ENABLE) == CRC_REFIN_DISABLE) + { + u8Size /= 8u; + /* Bits reversing in bytes. */ + for (i = 0u; i < u8Size; i++) + { + u8Offset = i * 8u; + u32Temp = (u32FinalChecksum >> u8Offset) & 0xFFul; + u32Temp = CRC_ReverseBits(u32Temp); + u32Temp = u32Temp >> (24u - u8Offset); + u32FinalChecksum &= ~((uint32_t)0xFF << u8Offset); + u32FinalChecksum |= u32Temp; + } + } + + return u32FinalChecksum; +} + +/** + ******************************************************************************* + ** \brief Reverse bits. + ** + ** \param [in] u32Data The data to be reversed bits. + ** + ** \retval 32-bit new data. + ** + ******************************************************************************/ +static uint32_t CRC_ReverseBits(uint32_t u32Data) +{ + u32Data = (((u32Data & 0xAAAAAAAAul) >> 1u) | ((u32Data & 0x55555555ul) << 1u)); + u32Data = (((u32Data & 0xCCCCCCCCul) >> 2u) | ((u32Data & 0x33333333ul) << 2u)); + u32Data = (((u32Data & 0xF0F0F0F0ul) >> 4u) | ((u32Data & 0x0F0F0F0Ful) << 4u)); + u32Data = (((u32Data & 0xFF00FF00ul) >> 8u) | ((u32Data & 0x00FF00FFul) << 8u)); + + return ((u32Data >> 16u) | (u32Data << 16u)); +} + +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_dcu.c b/lib/hc32f460/driver/src/hc32f460_dcu.c new file mode 100644 index 000000000000..aaf7b25e5635 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_dcu.c @@ -0,0 +1,971 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.c + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dcu.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup DcuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for DCU Instances. */ +#define IS_VALID_DCU(__DCUx__) \ +( (M4_DCU1 == (__DCUx__)) || \ + (M4_DCU2 == (__DCUx__)) || \ + (M4_DCU3 == (__DCUx__)) || \ + (M4_DCU4 == (__DCUx__))) + +/*!< Parameter valid check for DCU DATA register. */ +#define IS_VALID_DCU_DATA_REG(x) \ +( (DcuRegisterData0 == (x)) || \ + (DcuRegisterData1 == (x)) || \ + (DcuRegisterData2 == (x))) + +/*!< Parameter valid check for DCU operation mode. */ +#define IS_VALID_DCU_OPERATION(x) \ +( (DcuOpAdd == (x)) || \ + (DcuOpSub == (x)) || \ + (DcuInvalid == (x)) || \ + (DcuOpCompare == (x)) || \ + (DcuHwTrigOpAdd == (x)) || \ + (DcuHwTrigOpSub == (x))) + +/*!< Parameter valid check for DCU data size. */ +#define IS_VALID_DCU_DATAZ_SIZE(x) \ +( (DcuDataBit8 == (x)) || \ + (DcuDataBit16 == (x)) || \ + (DcuDataBit32 == (x))) + +/*!< Parameter valid check for DCU compare trigger mode type. */ +#define IS_VALID_DCU_CMP_TRIG_MODE(x) \ +( (DcuCmpTrigbyData0 == (x)) || \ + (DcuCmpTrigbyData012 == (x))) + +/*!< Parameter valid check for DCU interrupt. */ +#define IS_VALID_DCU_INT(x) \ +( (DcuIntOp == (x)) || \ + (DcuIntLs2 == (x)) || \ + (DcuIntEq2 == (x)) || \ + (DcuIntGt2 == (x)) || \ + (DcuIntLs1 == (x)) || \ + (DcuIntEq1 == (x)) || \ + (DcuIntGt1 == (x))) + +/*!< Parameter valid check for DCU interrupt mode. */ +#define IS_VALID_DCU_INT_WIN_MODE(x) \ +( (DcuIntInvalid == (x)) || \ + (DcuWinIntInvalid == (x)) || \ + (DcuInsideWinCmpInt == (x)) || \ + (DcuOutsideWinCmpInt == (x))) + +/*!< Parameter valid check for external trigger event. */ +#define IS_VALID_TRG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter valid check for DCU common trigger. */ +#define IS_DCU_COM_TRIGGER(x) \ +( ((x) == DcuComTrigger_1) || \ + ((x) == DcuComTrigger_2) || \ + ((x) == DcuComTrigger_1_2)) + +/*!< Get the specified DATA register address of the specified DCU unit */ +#define DCU_DATAx(__DCUx__, __DATAx__) ((uint32_t)(&(__DCUx__)->DATA0) + ((uint32_t)(__DATAx__)) * 4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to DCU configure structure + ** \arg This parameter detail refer @ref stc_dcu_init_t + ** + ** \retval Ok DCU is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx && pstcInitCfg pointer */ + if ((IS_VALID_DCU(DCUx)) && (NULL != pstcInitCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enIntCmd)); + DDL_ASSERT(IS_VALID_DCU_OPERATION(pstcInitCfg->enOperation)); + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(pstcInitCfg->enDataSize)); + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(pstcInitCfg->enIntWinMode)); + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(pstcInitCfg->enCmpTriggerMode)); + + /* De-initialize dcu register value */ + DCUx->CTL = 0ul; + DCUx->INTSEL = 0ul; + DCUx->FLAGCLR = 0x7Ful; + + /* Set dcu operation mode */ + DCUx->CTL_f.MODE = (uint32_t)pstcInitCfg->enOperation; + + /* Set dcu data sieze */ + DCUx->CTL_f.DATASIZE = (uint32_t)pstcInitCfg->enDataSize; + + /* Set dcu compare trigger mode */ + DCUx->CTL_f.COMP_TRG = (uint32_t)pstcInitCfg->enCmpTriggerMode; + + /* Set dcu interrupt window mode */ + DCUx->INTSEL_f.INT_WIN = (uint32_t)pstcInitCfg->enIntWinMode; + + DCUx->INTSEL = pstcInitCfg->u32IntSel; + DCUx->CTL_f.INTEN = (uint32_t)(pstcInitCfg->enIntCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval Ok De-Initialized successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* De-initialize dcu register value */ + DCUx->CTL = 0u; + DCUx->INTSEL = 0u; + DCUx->FLAGCLR = 0x7Fu; + *TRGSELx = EVT_MAX; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enMode DCU operation mode + ** \arg DcuInvalid Invalid + ** \arg DcuOpAdd Operation: Add + ** \arg DcuOpSub Operation: Sub + ** \arg DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \arg DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \arg DcuOpCompare Operation: Compare + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_OPERATION(enMode)); + + DCUx->CTL_f.MODE = (uint32_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuInvalid Invalid + ** \retval DcuOpAdd Operation: Add + ** \retval DcuOpSub Operation: Sub + ** \retval DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \retval DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \retval DcuOpCompare Operation: Compare + ** + ******************************************************************************/ +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_operation_mode_t)DCUx->CTL_f.MODE; +} + +/** + ******************************************************************************* + ** \brief Set DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enSize DCU data size + ** \arg DcuDataBit8 8 bit + ** \arg DcuDataBit16 16 bit + ** \arg DcuDataBit32 32 bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(enSize)); + + DCUx->CTL_f.DATASIZE = (uint32_t)enSize; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuDataBit8 8 bit + ** \retval DcuDataBit16 16 bit + ** \retval DcuDataBit32 32 bit + ** + ******************************************************************************/ +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_data_size_t)(DCUx->CTL_f.DATASIZE); +} + +/** + ******************************************************************************* + ** \brief Set DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntWinMode Interrupt window mode + ** \arg DcuIntInvalid DCU don't occur interrupt + ** \arg DcuWinIntInvalid DCU window interrupt is invalid. + ** \arg DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \arg DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(enIntWinMode)); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + DCUx->INTSEL_f.INT_WIN = (uint32_t)enIntWinMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuIntInvalid DCU don't occur interrupt + ** \retval DcuWinIntInvalid DCU window interrupt is invalid. + ** \retval DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \retval DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ******************************************************************************/ +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_int_win_mode_t)(DCUx->INTSEL_f.INT_WIN); +} + +/** + ******************************************************************************* + ** \brief Set DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerMode DCU compare trigger mode + ** \arg DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \arg DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(enTriggerMode)); + + DCUx->CTL_f.COMP_TRG = (uint32_t)enTriggerMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \retval DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ******************************************************************************/ +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_cmp_trigger_mode_t)(DCUx->CTL_f.COMP_TRG); +} + +/** + ******************************************************************************* + ** \brief Enable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enCmd DCU interrupt state + ** \arg Enable Enable the DCU interrupt function + ** \arg Disable Disable the DCU interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + DCUx->CTL_f.INTEN = (uint32_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag The specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + + return ((DCUx->FLAG & enFlag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag the specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + DCUx->FLAGCLR = (uint32_t)enFlag; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntSel DCU interrupt selection + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified DCU interrupt function + ** \arg Disable Disable the specified DCU interrupt function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - enIntSel is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enIntSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + enRet = Ok; + switch(enIntSel) + { + case DcuIntOp: + DCUx->INTSEL_f.INT_OP = (uint32_t)enCmd; + break; + case DcuIntLs2: + DCUx->INTSEL_f.INT_LS2 = (uint32_t)enCmd; + break; + case DcuIntEq2: + DCUx->INTSEL_f.INT_EQ2 = (uint32_t)enCmd; + break; + case DcuIntGt2: + DCUx->INTSEL_f.INT_GT2 = (uint32_t)enCmd; + break; + case DcuIntLs1: + DCUx->INTSEL_f.INT_LS1 = (uint32_t)enCmd; + break; + case DcuIntEq1: + DCUx->INTSEL_f.INT_EQ1 = (uint32_t)enCmd; + break; + case DcuIntGt1: + DCUx->INTSEL_f.INT_GT1 = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint8_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u8Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint8_t *)DCU_DATAx(DCUx, enDataReg) = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint16_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u16Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint16_t *)DCU_DATAx(DCUx, enDataReg) = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint32_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u32Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint32_t *)DCU_DATAx(DCUx, enDataReg) = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU trigger source number + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerSrc The trigger source. + ** \arg This parameter can be any value of @ref en_event_src_t + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_TRG_SRC_EVENT(enTriggerSrc)); + + *TRGSELx = (*TRGSELx & (~((uint32_t)EVT_MAX))) | (uint32_t)enTriggerSrc; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable DCU common trigger. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enComTrigger DCU common trigger selection. See @ref en_dcu_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_DCU_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Get DCU trigger source register address + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DCUx_TRGSEL address DCUx is valid + ** \retval NULL DCUx is invalid + ** + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx) +{ + __IO uint32_t *TRGSELx = NULL; + + if (M4_DCU1 == DCUx) + { + TRGSELx = &M4_AOS->DCU1_TRGSEL; + } + else if (M4_DCU2 == DCUx) + { + TRGSELx = &M4_AOS->DCU2_TRGSEL; + } + else if (M4_DCU3 == DCUx) + { + TRGSELx = &M4_AOS->DCU3_TRGSEL; + } + else if (M4_DCU4 == DCUx) + { + TRGSELx = &M4_AOS->DCU4_TRGSEL; + } + else + { + TRGSELx = NULL; + } + + return TRGSELx; +} + +//@} // DcuGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_dmac.c b/lib/hc32f460/driver/src/hc32f460_dmac.c new file mode 100644 index 000000000000..0e613491b89b --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_dmac.c @@ -0,0 +1,2125 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.c + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dmac.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup DmacGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define DMA_CNT (10u) +#define DMA_IDLE (0u) +#define DMA_BUSY (1u) + +#define DMACH0 (0x01u) +#define DMACH1 (0x02u) +#define DMACH2 (0x04u) +#define DMACH3 (0x08u) + +#define DMATIMEOUT1 (0x5000u) +#define DMATIMEOUT2 (0x1000u) + +#define DMA_CHCTL_DEFAULT (0x00001000ul) +#define DMA_DTCTL_DEFAULT (0x00000001ul) +#define DMA_DAR_DEFAULT (0x00000000ul) +#define DMA_SAR_DEFAULT (0x00000000ul) +#define DMA_RPT_DEFAULT (0x00000000ul) +#define DMA_LLP_DEFAULT (0x00000000ul) +#define DMA_SNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_DNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_RCFGCTL_DEFAULT (0x00000000ul) + +/***************** Bits definition for DMA_INTSTAT0 register ****************/ +#define DMA_INTSTAT0_TRNERR_Pos (0U) /*!< DMA_INTSTAT0: TRNERR Position */ +#define DMA_INTSTAT0_REQERR_Pos (16U) /*!< DMA_INTSTAT0: REQERR Position */ + +/***************** Bits definition for DMA_INTSTAT1 register ****************/ +#define DMA_INTSTAT1_TC_Pos (0U) /*!< DMA_INTSTAT1: TC Position */ +#define DMA_INTSTAT1_BTC_Pos (16U) /*!< DMA_INTSTAT1: BTC Position */ + +/***************** Bits definition for DMA_INTMASK0 register ****************/ +#define DMA_INTMASK0_MSKTRNERR_Pos (0U) /*!< DMA_INTMASK0: MSKTRNERR Position */ +#define DMA_INTMASK0_MSKREQERR_Pos (16U) /*!< DMA_INTMASK0: MSKREQERR Position */ + +/***************** Bits definition for DMA_INTMASK1 register ****************/ +#define DMA_INTMASK1_MSKTC_Pos (0U) /*!< DMA_INTMASK1: MSKTC Position */ +#define DMA_INTMASK1_MSKBTC_Pos (16U) /*!< DMA_INTMASK1: MSKBTC Position */ + +/***************** Bits definition for DMA_INTCLR0 register *****************/ +#define DMA_INTCLR0_CLRTRNERR_Pos (0U) /*!< DMA_INTCLR0: CLRTRNERR Position */ +#define DMA_INTCLR0_CLRREQERR_Pos (16U) /*!< DMA_INTCLR0: CLRREQERR Position */ + +/***************** Bits definition for DMA_INTCLR1 register *****************/ +#define DMA_INTCLR1_CLRTC_Pos (0U) /*!< DMA_INTCLR1: CLRTC Position */ +#define DMA_INTCLR1_CLRBTC_Pos (16U) /*!< DMA_INTCLR1: CLRBTC Position */ + +/******************* Bits definition for DMA_CHEN register ******************/ +#define DMA_CHEN_CHEN_Pos (0U) /*!< DMA_CHEN: CHEN Position */ + +/************** Bits definition for DMA_DTCTLx(x=0~3) register **************/ +#define DMA_DTCTL_BLKSIZE_Pos (0ul) /*!< DMA_DTCTLx: BLKSIZE Position */ +#define DMA_DTCTL_BLKSIZE_Msk (0x3FFul << DMA_DTCTL_BLKSIZE_Pos) /*!< DMA_DTCTLx: BLKSIZE Mask 0x000003FF */ +#define DMA_DTCTL_BLKSIZE (DMA_DTCTL_BLKSIZE_Msk) + +#define DMA_DTCTL_CNT_Pos (16ul) /*!< DMA_DTCTLx: CNT Position */ +#define DMA_DTCTL_CNT_Msk (0xFFFFul << DMA_DTCTL_CNT_Pos) /*!< DMA_DTCTLx: CNT Mask 0xFFFF0000 */ +#define DMA_DTCTL_CNT (DMA_DTCTL_CNT_Msk) + +/*************** Bits definition for DMA_RPTx(x=0~3) register ***************/ +#define DMA_RPT_SRPT_Pos (0ul) /*!< DMA_RPTx: SRPT Position */ +#define DMA_RPT_SRPT_Msk (0x3FFul << DMA_RPT_SRPT_Pos) /*!< DMA_RPTx: SRPT Mask 0x000003FF */ +#define DMA_RPT_SRPT (DMA_RPT_SRPT_Msk) + +#define DMA_RPT_DRPT_Pos (16ul) /*!< DMA_RPTx: DRPT Position */ +#define DMA_RPT_DRPT_Msk (0x3FFul << DMA_RPT_DRPT_Pos) /*!< DMA_RPTx: DRPT Mask 0x03FF0000 */ +#define DMA_RPT_DRPT (DMA_RPT_DRPT_Msk) + +/*************** Bits definition for DMA_RPTBx(x=0~3) register ***************/ +#define DMA_RPTB_SRPTB_Pos (0ul) /*!< DMA_RPTBx: SRPTB Position */ +#define DMA_RPTB_SRPTB_Msk (0x3FFul << DMA_RPTB_SRPTB_Pos) /*!< DMA_RPTBx: SRPTB Mask 0x000003FF */ +#define DMA_RPTB_SRPTB (DMA_RPTB_SRPTB_Msk) + +#define DMA_RPTB_DRPTB_Pos (16ul) /*!< DMA_RPTBx: DRPTB Position */ +#define DMA_RPTB_DRPTB_Msk (0x3FFul << DMA_RPTB_DRPTB_Pos) /*!< DMA_RPTBx: DRPTB Mask 0x03FF0000 */ +#define DMA_RPTB_DRPTB (DMA_RPTB_DRPTB_Msk) + +/************* Bits definition for DMA_SNSEQCTLx(x=0~3) register ************/ +#define DMA_SNSEQCTL_SOFFSET_Pos (0ul) /*!< DMA_SNSEQCTLx: SOFFSET Position */ +#define DMA_SNSEQCTL_SOFFSET_Msk (0xFFFFFul << DMA_SNSEQCTL_SOFFSET_Pos) /*!< DMA_SNSEQCTLx: SOFFSET Mask 0x000FFFFF */ +#define DMA_SNSEQCTL_SOFFSET (DMA_SNSEQCTL_SOFFSET_Msk) + +#define DMA_SNSEQCTL_SNSCNT_Pos (20ul) /*!< DMA_SNSEQCTLx: SNSCNT Position */ +#define DMA_SNSEQCTL_SNSCNT_Msk (0xFFFul << DMA_SNSEQCTL_SNSCNT_Pos) /*!< DMA_SNSEQCTLx: SNSCNT Mask 0xFFF00000 */ +#define DMA_SNSEQCTL_SNSCNT (DMA_SNSEQCTL_SNSCNT_Msk) + +/************* Bits definition for DMA_SNSEQCTLBx(x=0~3) register ************/ +#define DMA_SNSEQCTLB_SNSDIST_Pos (0ul) /*!< DMA_SNSEQCTLBx: SNSDIST Position */ +#define DMA_SNSEQCTLB_SNSDIST_Msk (0xFFFFFul << DMA_SNSEQCTLB_SNSDIST_Pos) /*!< DMA_SNSEQCTLBx: SNSDIST Mask 0x000FFFFF */ +#define DMA_SNSEQCTLB_SNSDIST (DMA_SNSEQCTLB_SNSDIST_Msk) + +#define DMA_SNSEQCTLB_SNSCNTB_Pos (20ul) /*!< DMA_SNSEQCTLBx: SNSCNTB Position */ +#define DMA_SNSEQCTLB_SNSCNTB_Msk (0xFFFul << DMA_SNSEQCTLB_SNSCNTB_Pos) /*!< DMA_SNSEQCTLBx: SNSCNTB Mask 0xFFF00000 */ +#define DMA_SNSEQCTLB_SNSCNTB (DMA_SNSEQCTLB_SNSCNTB_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTL_DOFFSET_Pos (0ul) /*!< DMA_DNSEQCTLx: DOFFSET Position */ +#define DMA_DNSEQCTL_DOFFSET_Msk (0xFFFFFul << DMA_DNSEQCTL_DOFFSET_Pos) /*!< DMA_DNSEQCTLx: DOFFSET Mask 0x000FFFFF */ +#define DMA_DNSEQCTL_DOFFSET (DMA_DNSEQCTL_DOFFSET_Msk) + +#define DMA_DNSEQCTL_DNSCNT_Pos (20ul) /*!< DMA_DNSEQCTLx: DNSCNT Position */ +#define DMA_DNSEQCTL_DNSCNT_Msk (0xFFFul << DMA_DNSEQCTL_DNSCNT_Pos) /*!< DMA_DNSEQCTLx: DNSCNT Mask 0xFFF00000 */ +#define DMA_DNSEQCTL_DNSCNT (DMA_DNSEQCTL_DNSCNT_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTLB_DNSDIST_Pos (0ul) /*!< DMA_DNSEQCTLBx: DNSDIST Position */ +#define DMA_DNSEQCTLB_DNSDIST_Msk (0xFFFFFul << DMA_DNSEQCTLB_DNSDIST_Pos) /*!< DMA_DNSEQCTLBx: DNSDIST Mask 0x000FFFFF */ +#define DMA_DNSEQCTLB_DNSDIST (DMA_DNSEQCTLB_DNSDIST_Msk) + +#define DMA_DNSEQCTLB_DNSCNTB_Pos (20ul) /*!< DMA_DNSEQCTLBx: DNSCNTB Position */ +#define DMA_DNSEQCTLB_DNSCNTB_Msk (0xFFFul << DMA_DNSEQCTLB_DNSCNTB_Pos) /*!< DMA_DNSEQCTLBx: DNSCNTB Mask 0xFFF00000 */ +#define DMA_DNSEQCTLB_DNSCNTB (DMA_DNSEQCTLB_DNSCNTB_Msk) + +/**************** Bits definition for DMA_LLPx(x=0~7) register **************/ +#define DMA_LLP_LLP_Pos (2ul) /*!< DMA_LLPx: LLP Position */ +#define DMA_LLP_LLP_Msk (0x3FFFFFFFul << DMA_LLP_LLP_Pos) /*!< DMA_LLPx: LLP Mask 0xFFFFFFC */ +#define DMA_LLP_LLP (DMA_LLP_LLP_Msk) + +/*************** Bits definition for DMA_CHxCTL(x=0~3) register *************/ +#define DMA_CHCTL_SINC_Pos (0ul) /*!< DMA_CHxCTL: SINC Position */ +#define DMA_CHCTL_SINC_Msk (0x3ul << DMA_CHCTL_SINC_Pos) /*!< DMA_CHxCTL: SINC Mask 0x00000003 */ +#define DMA_CHCTL_SINC (DMA_CHCTL_SINC_Msk) + +#define DMA_CHCTL_DINC_Pos (2ul) /*!< DMA_CHxCTL: DINC Position */ +#define DMA_CHCTL_DINC_Msk (0x3ul << DMA_CHCTL_DINC_Pos) /*!< DMA_CHxCTL: DINC Mask 0x0000000C */ +#define DMA_CHCTL_DINC (DMA_CHCTL_DINC_Msk) + +#define DMA_CHCTL_SRPTEN_Pos (4ul) /*!< DMA_CHxCTL: SRPTEN Position */ +#define DMA_CHCTL_SRPTEN_Msk (0x1ul << DMA_CHCTL_SRPTEN_Pos) /*!< DMA_CHxCTL: SRPTEN Mask 0x00000010 */ +#define DMA_CHCTL_SRPTEN (DMA_CHCTL_SRPTEN_Msk) + +#define DMA_CHCTL_DRPTEN_Pos (5ul) /*!< DMA_CHxCTL: DRPTEN Position */ +#define DMA_CHCTL_DRPTEN_Msk (0x1ul << DMA_CHCTL_DRPTEN_Pos) /*!< DMA_CHxCTL: DRPTEN Mask 0x00000020 */ +#define DMA_CHCTL_DRPTEN (DMA_CHCTL_DRPTEN_Msk) + +#define DMA_CHCTL_SNSEQEN_Pos (6ul) /*!< DMA_CHxCTL: SNSEQEN Position */ +#define DMA_CHCTL_SNSEQEN_Msk (0x1ul << DMA_CHCTL_SNSEQEN_Pos) /*!< DMA_CHxCTL: SNSEQEN Mask 0x00000040 */ +#define DMA_CHCTL_SNSEQEN (DMA_CHCTL_SNSEQEN_Msk) + +#define DMA_CHCTL_DNSEQEN_Pos (7ul) /*!< DMA_CHxCTL: DNSEQEN Position */ +#define DMA_CHCTL_DNSEQEN_Msk (0x1ul << DMA_CHCTL_DNSEQEN_Pos) /*!< DMA_CHxCTL: DNSEQEN Mask 0x00000080 */ +#define DMA_CHCTL_DNSEQEN (DMA_CHCTL_DNSEQEN_Msk) + +#define DMA_CHCTL_HSIZE_Pos (8ul) /*!< DMA_CHxCTL: HSIZE Position */ +#define DMA_CHCTL_HSIZE_Msk (0x3ul << DMA_CHCTL_HSIZE_Pos) /*!< DMA_CHxCTL: HSIZE Mask 0x00000300 */ +#define DMA_CHCTL_HSIZE (DMA_CHCTL_HSIZE_Msk) + +#define DMA_CHCTL_LLPEN_Pos (10ul) /*!< DMA_CHxCTL: LLPEN Position */ +#define DMA_CHCTL_LLPEN_Msk (0x1ul << DMA_CHCTL_LLPEN_Pos) /*!< DMA_CHxCTL: LLPEN Mask 0x00000400 */ +#define DMA_CHCTL_LLPEN (DMA_CHCTL_LLPEN_Msk) + +#define DMA_CHCTL_LLPRUN_Pos (11ul) /*!< DMA_CHxCTL: LLPRUN Position */ +#define DMA_CHCTL_LLPRUN_Msk (0x1ul << DMA_CHCTL_LLPRUN_Pos) /*!< DMA_CHxCTL: LLPRUN Mask 0x00000800 */ +#define DMA_CHCTL_LLPRUN (DMA_CHCTL_LLPRUN_Msk) + +#define DMA_CHCTL_IE_Pos (12ul) /*!< DMA_CHxCTL: IE Position */ +#define DMA_CHCTL_IE_Msk (0x1ul << DMA_CHCTL_IE_Pos) /*!< DMA_CHxCTL: IE Mask 0x00001000 */ +#define DMA_CHCTL_IE (DMA_CHCTL_IE_Msk) + +/*********************** DMA REGISTERx(x=0~3) register **********************/ +#define _DMA_CH_REG_OFFSET(ch) ((ch) * 0x40ul) +#define _DMA_CH_REG(reg_base, ch) (*(volatile uint32_t *)((uint32_t)(reg_base) + _DMA_CH_REG_OFFSET(ch))) + +#define WRITE_DMA_CH_REG(reg_base, ch, val) (_DMA_CH_REG((reg_base), (ch)) = (val)) +#define READ_DMA_CH_REG(reg_base, ch) (_DMA_CH_REG((reg_base), (ch))) + +#define SET_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) |= (1ul << (pos))) +#define CLR_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) &= (~(1ul << (pos)))) + +#define WRITE_DMA_CH_TRGSEL(reg_base, ch, val) ((*(volatile uint32_t *)((uint32_t)(reg_base) + (ch) * 4ul)) = (val)) + +#define MODIFY_DMA_CH_REG(reg_base, ch, msk, val) {do { \ + WRITE_DMA_CH_REG((reg_base), (ch), ((READ_DMA_CH_REG((reg_base), (ch)) & (~(msk))) | ((val) << (msk##_Pos)))); \ +} while(0);} + +/*! Parameter valid check for Dmac register pointer. */ +#define IS_VALID_DMA_REG(x) \ +( (M4_DMA1 == (x)) || \ + (M4_DMA2 == (x))) + +/*! Parameter valid check for Dmac Channel. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x)) || \ + (DmaCh2 == (x)) || \ + (DmaCh3 == (x))) + +/*! Parameter valid check for Dmac irq selection. */ +#define IS_VALID_IRQ_SEL(x) \ +( (TrnErrIrq == (x)) || \ + (TrnReqErrIrq == (x)) || \ + (TrnCpltIrq == (x)) || \ + (BlkTrnCpltIrq == (x))) + +/*! Parameter valid check for Dmac re_config count mode. */ +#define IS_VALID_CNT_MODE(x) \ +( (CntFix == (x)) || \ + (CntSrcAddr == (x)) || \ + (CntDesAddr == (x))) + +/*! Parameter valid check for Dmac re_config source address mode. */ +#define IS_VALID_SADDR_MODE(x) \ +( (SaddrFix == (x)) || \ + (SaddrNseq == (x)) || \ + (SaddrRep == (x))) + +/*! Parameter valid check for Dmac re_config destination address mode. */ +#define IS_VALID_DADDR_MODE(x) \ +( (DaddrFix == (x)) || \ + (DaddrNseq == (x)) || \ + (DaddrRep == (x))) + +/*! Parameter valid check for Dmac status. */ +#define IS_VALID_DMA_STA(x) \ +( (DmaSta == (x)) || \ + (ReCfgSta == (x)) || \ + (DmaCh0Sta == (x)) || \ + (DmaCh1Sta == (x)) || \ + (DmaCh2Sta == (x)) || \ + (DmaCh3Sta == (x))) + +/*! Parameter valid check for Dmac status. */ +#define IS_VALID_DMA_REQ_STA(x) \ +( (ReCfgReqSta == (x)) || \ + (DmaCh0ReqSta == (x)) || \ + (DmaCh1ReqSta == (x)) || \ + (DmaCh2ReqSta == (x)) || \ + (DmaCh3ReqSta == (x))) + +/*! Parameter valid check for Dmac transfer data width. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (Dma8Bit == (x)) || \ + (Dma16Bit == (x)) || \ + (Dma32Bit == (x))) + +/*! Parameter valid check for Dmac address mode. */ +#define IS_VALID_ADDR_MODE(x) \ +( (AddressFix == (x)) || \ + (AddressIncrease == (x)) || \ + (AddressDecrease == (x))) + +/*! Parameter valid check for Dmac link-list-pointer mode. */ +#define IS_VALID_LLP_MODE(x) \ +( (LlpWaitNextReq == (x)) || \ + (LlpRunNow == (x))) + +/*! Parameter validity check for DMA common trigger. */ +#define IS_DMA_COM_TRIGGER(x) \ +( ((x) == DmaComTrigger_1) || \ + ((x) == DmaComTrigger_2) || \ + ((x) == DmaComTrigger_1_2)) + +/*! Parameter valid check for Dmac transfer block size. */ +#define IS_VALID_BLKSIZE(x) \ +( !((x) & (uint16_t)(~(DMA_DTCTL_BLKSIZE_Msk >> DMA_DTCTL_BLKSIZE_Pos)))) + +/*! Parameter valid check for Dmac transfer count. */ +#define IS_VALID_TRNCNT(x) \ +( !((x) & ~(DMA_DTCTL_CNT_Msk >> DMA_DTCTL_CNT_Pos))) + +/*! Parameter valid check for Dmac source repeat size. */ +#define IS_VALID_SRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_SRPT_Msk >> DMA_RPT_SRPT_Pos))) + +/*! Parameter valid check for Dmac destination repeat size. */ +#define IS_VALID_DRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_DRPT_Msk >> DMA_RPT_DRPT_Pos))) + +/*! Parameter valid check for Dmac source repeatB size. */ +#define IS_VALID_SRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_SRPTB_Msk >> DMA_RPTB_SRPTB_Pos))) + +/*! Parameter valid check for Dmac destinationB repeat size. */ +#define IS_VALID_DRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_DRPTB_Msk >> DMA_RPTB_DRPTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence count. */ +#define IS_VALID_SNSCNT(x) \ +( !((x) & ~(DMA_SNSEQCTL_SNSCNT_Msk >> DMA_SNSEQCTL_SNSCNT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence offset. */ +#define IS_VALID_SNSOFFSET(x) \ +( !((x) & ~(DMA_SNSEQCTL_SOFFSET_Msk >> DMA_SNSEQCTL_SOFFSET_Pos))) + +/*! Parameter valid check for Dmac source no-sequence countB. */ +#define IS_VALID_SNSCNTB(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSCNTB_Msk >> DMA_SNSEQCTLB_SNSCNTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence distance. */ +#define IS_VALID_SNSDIST(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSDIST_Msk >> DMA_SNSEQCTLB_SNSDIST_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence count. */ +#define IS_VALID_DNSCNT(x) \ +( !((x) & ~(DMA_DNSEQCTL_DNSCNT_Msk >> DMA_DNSEQCTL_DNSCNT_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence offset. */ +#define IS_VALID_DNSOFFSET(x) \ +( !((x) & ~(DMA_DNSEQCTL_DOFFSET_Msk >> DMA_DNSEQCTL_DOFFSET_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence countB. */ +#define IS_VALID_DNSCNTB(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSCNTB_Msk >> DMA_DNSEQCTLB_DNSCNTB_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence distance. */ +#define IS_VALID_DNSDIST(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSDIST_Msk >> DMA_DNSEQCTLB_DNSDIST_Pos))) + +/*! Parameter valid check for Dmac link-list-pointer. */ +#define IS_VALID_LLP(x) (!((x) & ~DMA_LLP_LLP_Msk)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static volatile uint8_t DmaChEnState = DMA_IDLE; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Enable or disable the dma. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->EN_f.EN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt enabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt disabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma interrupt flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + switch(enIrqSel) + { + case TrnErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_TRNERR_Pos))); + break; + case TrnReqErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_REQERR_Pos))); + break; + case TrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_TC_Pos))); + break; + case BlkTrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_BTC_Pos))); + break; + default: + break; + } + + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint16_t u16Timeout = 0u; + uint32_t u32Temp = 0u; + uint32_t u32Cnt; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(DMA_IDLE == DmaChEnState) + { + DmaChEnState = DMA_BUSY; + + /* Read back channel enable register except current channel */ + u32Temp = (pstcDmaReg->CHEN & (~(1ul << u8Ch))); + if(0ul != u32Temp) + { + if(((pstcDmaReg->CHEN & 0x01ul) == 0x01ul) && (u8Ch != DmaCh0)) + { + u32Cnt = pstcDmaReg->DTCTL0_f.CNT; + if(pstcDmaReg->MONDTCTL0_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL0_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x01ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x02ul) == 0x02ul) && (u8Ch != DmaCh1)) + { + u32Cnt = pstcDmaReg->DTCTL1_f.CNT; + if(pstcDmaReg->MONDTCTL1_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL1_f.CNT < u32Cnt) + { + u16Timeout = 0u; + while(Reset != (pstcDmaReg->CHEN & 0x02ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x04ul) == 0x04ul) && (u8Ch != DmaCh2)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL2_f.CNT; + if(pstcDmaReg->MONDTCTL2_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL2_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x04ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x08ul) == 0x08ul) && (u8Ch != DmaCh3)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL3_f.CNT; + if(pstcDmaReg->MONDTCTL3_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL3_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x08ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + } + + switch(enNewState) + { + case Enable: + pstcDmaReg->CHEN |= (1ul << (u8Ch + DMA_CHEN_CHEN_Pos)) & 0x0fu; + break; + case Disable: + pstcDmaReg->CHEN &= (~(1ul << (u8Ch + DMA_CHEN_CHEN_Pos))) & 0x0fu; + break; + } + + DmaChEnState = DMA_IDLE; + return Ok; + } + + return Error; +} + +/** + ******************************************************************************* + ** \brief DMA repeat & non_sequence Re_Config control configuration. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaReCfg The configuration struct of DMA. + ** \arg u16SrcRptBSize The source repeat size. + ** \arg u16SrcRptBSize; The source repeat size. + ** \arg u16DesRptBSize; The destination repeat size. + ** \arg enSaddrMd; DMA re_config source address mode. + ** \arg enDaddrMd; DMA re_config destination address mode. + ** \arg enCntMd; DMA re_config count mode. + ** \arg stcSrcNseqBCfg; The source no_sequence re_config. + ** \arg stcDesNseqBCfg; The destination no_sequence re_config. + ** + ** \retval None + ** + ** \note This function should be used while DMA disable. + ** + ******************************************************************************/ +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_recfg_ctl_t* pstcDmaReCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcDmaReCfg->enCntMd)); + DDL_ASSERT(IS_VALID_DADDR_MODE(pstcDmaReCfg->enDaddrMd)); + DDL_ASSERT(IS_VALID_SADDR_MODE(pstcDmaReCfg->enSaddrMd)); + + pstcDmaReg->RCFGCTL_f.SARMD = pstcDmaReCfg->enSaddrMd; + pstcDmaReg->RCFGCTL_f.DARMD = pstcDmaReCfg->enDaddrMd; + pstcDmaReg->RCFGCTL_f.CNTMD = pstcDmaReCfg->enCntMd; + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + + if(SaddrRep == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaReCfg->u16SrcRptBSize); + } + else if(SaddrNseq == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaReCfg->stcSrcNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaReCfg->stcSrcNseqBCfg.u16Cnt); + } + else + { + /* */ + } + + if(DaddrRep == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaReCfg->u16DesRptBSize); + } + else if(DaddrNseq == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaReCfg->stcDesNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaReCfg->stcDesNseqBCfg.u16Cnt); + } + else + { + /* */ + } +} + +/** + ******************************************************************************* + ** \brief Disable or enable DMA Re_Config. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Configure DMA Re_Config LLP. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgLlp(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + pstcDmaReg->RCFGCTL_f.RCFGLLP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enDmaChFlag The specified dma flag. + ** \arg DmaSta The DMA status. + ** \arg ReCfgSta The DMA re_config stauts. + ** \arg DmaCh0Sta The DMA channel 0 status. + ** \arg DmaCh1Sta The DMA channel 1 status. + ** \arg DmaCh2Sta The DMA channel 2 status. + ** \arg DmaCh3Sta The DMA channel 3 status. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_DMA_STA(enDmaChFlag)); + + switch(enDmaChFlag) + { + case DmaSta: + u32IntStat = pstcDmaReg->CHSTAT_f.DMAACT; + break; + case ReCfgSta: + u32IntStat = pstcDmaReg->CHSTAT_f.RCFGACT; + break; + case DmaCh0Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH0); + break; + case DmaCh1Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH1); + break; + case DmaCh2Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH2); + break; + case DmaCh3Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH3); + break; + default: + break; + } + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Get the specified dma request status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enDmaReqStatus The specified dma requst status. + ** \arg ReCfgReqSta The DMA re_config requst status. + ** \arg DmaCh0ReqSta The DMA channel 0 transfer requst status. + ** \arg DmaCh1ReqSta The DMA channel 1 transfer requst status. + ** \arg DmaCh2ReqSta The DMA channel 2 transfer requst status. + ** \arg DmaCh3ReqSta The DMA channel 3 transfer requst status. + ** + ** \retval the specified dma requst status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetReqStatus(M4_DMA_TypeDef* pstcDmaReg, en_dma_req_status_t enDmaReqStatus) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_DMA_REQ_STA(enDmaReqStatus)); + + switch(enDmaReqStatus) + { + case ReCfgReqSta: + u32IntStat = pstcDmaReg->REQSTAT_f.RCFGREQ; + break; + case DmaCh0ReqSta: + u32IntStat = (pstcDmaReg->REQSTAT_f.CHREQ & DMACH0); + break; + case DmaCh1ReqSta: + u32IntStat = (pstcDmaReg->REQSTAT_f.CHREQ & DMACH1); + break; + case DmaCh2ReqSta: + u32IntStat = (pstcDmaReg->REQSTAT_f.CHREQ & DMACH2); + break; + case DmaCh3ReqSta: + u32IntStat = (pstcDmaReg->REQSTAT_f.CHREQ & DMACH3); + break; + default: + break; + } + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Set the source address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The source address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONSAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get current source address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The current source address. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetSrcAddr(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + return READ_DMA_CH_REG(&pstcDmaReg->MONSAR0, u8Ch); +} + +/** + ******************************************************************************* + ** \brief Set the destination address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The destination address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONDAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + } + } + + return enRet; + +} + +/** + ******************************************************************************* + ** \brief Get current destination address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The current destination address. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetDesAddr(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + return READ_DMA_CH_REG(&pstcDmaReg->MONDAR0, u8Ch); +} + +/** + ******************************************************************************* + ** \brief Set the block size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16BlkSize The block size. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(u16BlkSize)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + + /* Ensure the block size has been writed */ + while(u16BlkSize != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_BLKSIZE)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the block size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The current block size. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetBlockSize(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + return (READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_BLKSIZE); +} + +/** + ******************************************************************************* + ** \brief Set the transfer count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16TrnCnt The transfer count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_TRNCNT(u16TrnCnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + + /* Ensure the transfer count has been writed */ + while(u16TrnCnt != ((READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the remain transfer count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The remain transfer count. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetTransferCnt(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + uint32_t u32Count; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + u32Count = READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_CNT; + + return (u32Count >> DMA_DTCTL_CNT_Pos); +} + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_SRPT)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The source repeat size. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetSrcRptSize(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + return (READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_SRPT); +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_DRPT) >> DMA_RPT_DRPT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The destination repeat size. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetDesRptSize(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + uint32_t u32Size; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + u32Size = READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_DRPT; + + return (u32Size >> DMA_RPT_DRPT_Pos); +} + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_SRPTB)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptBSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_DRPTB) >> DMA_RPTB_DRPTB_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqCfg + ** \arg u32offset The source no-sequence offset. + ** \arg u16cnt The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcSrcNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSOFFSET(pstcSrcNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_SNSCNT(pstcSrcNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqCfg->u32Offset | ((uint32_t)pstcSrcNseqCfg->u16Cnt << DMA_SNSEQCTL_SNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONSNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqBCfg + ** \arg u32NseqDist The source no-sequence distance. + ** \arg u16cntB The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSDIST(pstcSrcNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_SNSCNTB(pstcSrcNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqBCfg->u32NseqDist | ((uint32_t)pstcSrcNseqBCfg->u16CntB << DMA_SNSEQCTLB_SNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcDesNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSOFFSET(pstcDesNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_DNSCNT(pstcDesNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqCfg->u32Offset | ((uint32_t)pstcDesNseqCfg->u16Cnt << DMA_DNSEQCTL_DNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONDNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqBCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcDesNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSDIST(pstcDesNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_DNSCNTB(pstcDesNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqBCfg->u32NseqDist | ((uint32_t)pstcDesNseqBCfg->u16CntB << DMA_DNSEQCTLB_DNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the source no-sequence count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The source no-sequence count. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetSrcNSeqCount(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + uint32_t u32Count; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + u32Count = READ_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch) & DMA_SNSEQCTL_SNSCNT; + + return (u32Count >> DMA_SNSEQCTL_SNSCNT_Pos); +} + +/** + ******************************************************************************* + ** \brief Get the destination no-sequence count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The destination no-sequence count. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetDesNSeqCount(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + uint32_t u32Count; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + u32Count = READ_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch) & DMA_DNSEQCTL_DNSCNT; + + return (u32Count >> DMA_DNSEQCTL_DNSCNT_Pos); +} + +/** + ******************************************************************************* + ** \brief Get the source no-sequence offset of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The source no-sequence offset. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetSrcNSeqOffset(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + return (READ_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch) & DMA_SNSEQCTL_SOFFSET); +} + +/** + ******************************************************************************* + ** \brief Get the destination no-sequence offset of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \retval uint32_t The destination no-sequence offset. + ** + ** \note None + ** + ******************************************************************************/ +uint32_t DMA_GetDesNSeqOffset(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + return (READ_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch) & DMA_DNSEQCTL_DOFFSET); +} + +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Pointer The decriptor pointer. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_LLP(u32Pointer)); + + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + + /* Ensure the destination repeat size has been writed */ + while(u32Pointer != ((READ_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch) & DMA_LLP_LLP) >> DMA_LLP_LLP_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set The DMA trigger source. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, shoud ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + + if(M4_DMA1 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA1_TRGSEL0,u8Ch,enSrc); + } + else if(M4_DMA2 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA2_TRGSEL0,u8Ch,enSrc); + } + else + { + //else + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA common trigger.. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + __IO uint32_t *TRGSELx; + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (M4_DMA1 == pstcDmaReg) + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA1_TRGSEL0) + u8Ch*4UL); + } + else + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA2_TRGSEL0) + u8Ch*4UL); + } + + if (Enable == enNewState) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA re-config common trigger.. + ** + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + + if (Enable == enNewState) + { + M4_AOS->DMA_TRGSELRC |= (u32ComTrig << 30u); + } + else + { + M4_AOS->DMA_TRGSELRC &= ~(u32ComTrig << 30u); + } +} +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, should ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc) +{ + + M4_AOS->DMA_TRGSELRC_f.TRGSEL = enSrc; + +} +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcChCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_ch_cfg_t* pstcChCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enSrcInc)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enDesInc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcNseqEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesNseqEn)); + DDL_ASSERT(IS_VALID_TRN_WIDTH(pstcChCfg->enTrnWidth)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enLlpEn)); + DDL_ASSERT(IS_VALID_LLP_MODE(pstcChCfg->enLlpMd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enIntEn)); + + /* Set the source address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_SINC, pstcChCfg->enSrcInc); + /* Set the destination address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_DINC, pstcChCfg->enDesInc); + /* Enable or disable source repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_SRPTEN, pstcChCfg->enSrcRptEn); + /* Enable or disable destination repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_DRPTEN, pstcChCfg->enDesRptEn); + /* Enable or disable source no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_SNSEQEN, pstcChCfg->enSrcNseqEn); + /* Enable or disable destination no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_DNSEQEN, pstcChCfg->enDesNseqEn); + /* Set the transfer data width. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_HSIZE, pstcChCfg->enTrnWidth); + /* Enable or disable linked list pointer no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_LLPEN, pstcChCfg->enLlpEn); + /* Set the linked list pointer mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_LLPRUN, pstcChCfg->enLlpMd); + /* Enable or disable channel interrupt function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_IE, pstcChCfg->enIntEn); +} + +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note This function should be used after enable DMAx clk(PWC_Fcg0PeriphClockCmd) + ** and before channel enable. + ** + ******************************************************************************/ +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_config_t* pstcDmaCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(pstcDmaCfg->u16BlockSize)); + DDL_ASSERT(IS_VALID_TRNCNT(pstcDmaCfg->u16TransferCnt)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(pstcDmaCfg->u16SrcRptSize)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(pstcDmaCfg->u16DesRptSize)); + + /* Enable DMA. */ + DMA_Cmd(pstcDmaReg, Enable); + /* Disable DMA interrupt */ + CLR_DMA_CH_REG_BIT(&pstcDmaReg->CHCTL0 , u8Ch, DMA_CHCTL_IE_Pos); + /* Set DMA source address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, pstcDmaCfg->u32SrcAddr); + /* Set DMA destination address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, pstcDmaCfg->u32DesAddr); + /* Set DMA transfer block size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)pstcDmaCfg->u16BlockSize); + /* Set DMA transfer count. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)pstcDmaCfg->u16TransferCnt); + /* Set DMA source repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaCfg->u16SrcRptSize); + /* Set DMA destination repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaCfg->u16DesRptSize); + /* Set DMA source no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaCfg->stcSrcNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaCfg->stcSrcNseqCfg.u16Cnt); + /* Set DMA destination no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaCfg->stcDesNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaCfg->stcDesNseqCfg.u16Cnt); + /* Set DMA linked list pointer. */ + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, pstcDmaCfg->u32DmaLlp); + /* Set DMA channel parameter. */ + DMA_ChannelCfg(pstcDmaReg, u8Ch, &pstcDmaCfg->stcDmaChCfg); +} + +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + /* reset dma channel */ + WRITE_DMA_CH_REG(&pstcDmaReg->CHCTL0, u8Ch, DMA_CHCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, DMA_DAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, DMA_SAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, DMA_LLP_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RCFGCTL, u8Ch, DMA_RCFGCTL_DEFAULT); + + /* Set trigger source event max */ + DMA_SetTriggerSrc(pstcDmaReg, u8Ch, EVT_MAX); + /* disable channel */ + DMA_ChannelCmd(pstcDmaReg, u8Ch, Disable); +} + +//@} // DmacGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_efm.c b/lib/hc32f460/driver/src/hc32f460_efm.c new file mode 100644 index 000000000000..d8583efe1899 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_efm.c @@ -0,0 +1,938 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.c + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_efm.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup EfmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EFM_LOCK (0x00000000u) +#define EFM_UNLOCK (0x00000001u) +#define EFM_KEY1 (0x0123ul) +#define EFM_KEY2 (0x3210ul) + +#define EFM_PROTECT_ADDR_MSK (0x000FFFFFu) + +/* Parameter validity check for pointer. */ +#define IS_VALID_POINTER(x) (NULL != (x)) + +/* Parameter validity check for flash latency. */ +#define IS_VALID_FLASH_LATENCY(x) \ +( ((x) == EFM_LATENCY_0) || \ + ((x) == EFM_LATENCY_1) || \ + ((x) == EFM_LATENCY_2) || \ + ((x) == EFM_LATENCY_3) || \ + ((x) == EFM_LATENCY_4) || \ + ((x) == EFM_LATENCY_5) || \ + ((x) == EFM_LATENCY_6) || \ + ((x) == EFM_LATENCY_7) || \ + ((x) == EFM_LATENCY_8) || \ + ((x) == EFM_LATENCY_9) || \ + ((x) == EFM_LATENCY_10) || \ + ((x) == EFM_LATENCY_11) || \ + ((x) == EFM_LATENCY_12) || \ + ((x) == EFM_LATENCY_13) || \ + ((x) == EFM_LATENCY_14) || \ + ((x) == EFM_LATENCY_15)) + +/* Parameter validity check for read mode. */ +#define IS_VALID_READ_MD(MD) \ +( ((MD) == NormalRead) || \ + ((MD) == UltraPowerRead)) + +/* Parameter validity check for erase/program mode. */ +#define IS_VALID_ERASE_PGM_MD(MD) \ +( ((MD) == EFM_MODE_READONLY) || \ + ((MD) == EFM_MODE_SINGLEPROGRAM) || \ + ((MD) == EFM_MODE_SINGLEPROGRAMRB) || \ + ((MD) == EFM_MODE_SEQUENCEPROGRAM) || \ + ((MD) == EFM_MODE_SECTORERASE) || \ + ((MD) == EFM_MODE_CHIPERASE)) + +/* Parameter validity check for flash flag. */ +#define IS_VALID_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR) || \ + ((flag) == EFM_FLAG_RDY)) + +/* Parameter validity check for flash clear flag. */ +#define IS_VALID_CLEAR_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR)) + +/* Parameter validity check for flash interrupt. */ +#define IS_VALID_EFM_INT_SEL(int) \ +( ((int) == PgmErsErrInt) || \ + ((int) == EndPgmInt) || \ + ((int) == ColErrInt)) + +/* Parameter validity check for flash address. */ +#define IS_VALID_FLASH_ADDR(addr) \ +( ((addr) == 0x00000000u) || \ + (((addr) >= 0x00000001u) && \ + ((addr) <= 0x0007FFDFu))) + +/* Parameter validity check for flash address. */ +#define IS_VALID_OTP_LOCK_ADDR(addr) \ +( ((addr) >= 0x03000FC0u) || \ + ((addr) <= 0x03000FF8u)) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Unlock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Unlock(void) +{ + M4_EFM->FAPRT = EFM_KEY1; + M4_EFM->FAPRT = EFM_KEY2; +} + +/** + ******************************************************************************* + ** \brief Lock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Lock(void) +{ + if(EFM_UNLOCK == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = EFM_KEY2; + M4_EFM->FAPRT = EFM_KEY2; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash. + ** + ** \param [in] enNewState The new state of the flash. + ** \arg Enable Enable flash. + ** \arg Disable Stop flash. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_FlashCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FSTP_f.FSTP = ((Enable == enNewState) ? 0ul : 1ul); +} +/** + ******************************************************************************* + ** \brief Sets the code latency value.. + ** + ** \param [in] u32Latency specifies the FLASH Latency value. + ** \arg EFM_LATENCY_0 FLASH 0 Latency cycle + ** \arg EFM_LATENCY_1 FLASH 1 Latency cycle + ** \arg EFM_LATENCY_2 FLASH 2 Latency cycles + ** \arg EFM_LATENCY_3 FLASH 3 Latency cycles + ** \arg EFM_LATENCY_4 FLASH 4 Latency cycles + ** \arg EFM_LATENCY_5 FLASH 5 Latency cycles + ** \arg EFM_LATENCY_6 FLASH 6 Latency cycles + ** \arg EFM_LATENCY_7 FLASH 7 Latency cycles + ** \arg EFM_LATENCY_8 FLASH 8 Latency cycles + ** \arg EFM_LATENCY_9 FLASH 9 Latency cycles + ** \arg EFM_LATENCY_10 FLASH 10 Latency cycles + ** \arg EFM_LATENCY_11 FLASH 11 Latency cycles + ** \arg EFM_LATENCY_12 FLASH 12 Latency cycles + ** \arg EFM_LATENCY_13 FLASH 13 Latency cycles + ** \arg EFM_LATENCY_14 FLASH 14 Latency cycles + ** \arg EFM_LATENCY_15 FLASH 15 Latency cycles + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetLatency(uint32_t u32Latency) +{ + DDL_ASSERT(IS_VALID_FLASH_LATENCY(u32Latency)); + + M4_EFM->FRMC_f.FLWT = u32Latency; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash instruction cache. + ** + ** \param [in] enNewState The new state of the flash instruction cache. + ** \arg Enable Enable flash instruction cache. + ** \arg Disable Disable flash instruction cache. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InstructionCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CACHE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the data cache reset. + ** + ** \param [in] enNewState The new state of the data cache reset. + ** \arg Enable Enable data cache reset. + ** \arg Disable Disable data cache reset. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_DataCacheRstCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash read mode. + ** + ** \param [in] enReadMD The flash read mode. + ** \arg NormalRead Normal read mode. + ** \arg UltraPowerRead Ultra_Low power read mode. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetReadMode(en_efm_read_md_t enReadMD) +{ + DDL_ASSERT(IS_VALID_READ_MD(enReadMD)); + M4_EFM->FRMC_f.SLPMD = enReadMD; +} + +/** + ******************************************************************************* + ** \brief Enable or disable erase / program. + ** + ** \param [in] enNewState The new state of the erase / program. + ** \arg Enable Enable erase / program. + ** \arg Disable Disable erase / program. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ErasePgmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FWMC_f.PEMODE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash erase program mode. + ** + ** \param [in] u32Mode The flash erase program mode. + ** \arg EFM_MODE_READONLY The flash read only. + ** \arg EFM_MODE_SINGLEPROGRAM The flash single program. + ** \arg EFM_MODE_SINGLEPROGRAMRB The flash single program with read back. + ** \arg EFM_MODE_SEQUENCEPROGRAM The flash sequence program. + ** \arg EFM_MODE_SECTORERASE The flash sector erase. + ** \arg EFM_MODE_CHIPERASE The flash mass erase. + ** + ** \retval en_result_t. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode) +{ + en_result_t enRet = Ok; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_ERASE_PGM_MD(u32Mode)); + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + break; + } + } + if(Ok == enRet) + { + M4_EFM->FWMC_f.PEMODE = Enable; + M4_EFM->FWMC_f.PEMOD = u32Mode; + M4_EFM->FWMC_f.PEMODE = Disable; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable the specified interrupt. + ** + ** \param [in] enInt The specified interrupt. + ** \arg PgmErsErrInt Program erase error interrupt. + ** \arg EndPgmInt End of Program interrupt. + ** \arg ReadErrInt Read collided error flag. + ** + ** \param [in] enNewState The new state of the specified interrupt. + ** \arg Enable Enable the specified interrupt. + ** \arg Disable Disable the specified interrupt. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_INT_SEL(enInt)); + + switch(enInt) + { + case PgmErsErrInt: + M4_EFM->FITE_f.PEERRITE = enNewState; + break; + case EndPgmInt: + M4_EFM->FITE_f.OPTENDITE = enNewState; + break; + case ColErrInt: + M4_EFM->FITE_f.COLERRITE = enNewState; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to check. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** \arg EFM_FLAG_RDY Flash ready flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag) +{ + DDL_ASSERT(IS_VALID_FLASH_FLAG(u32flag)); + + return ((0ul == (M4_EFM->FSR & u32flag)) ? Reset :Set); +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to clear. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ClearFlag(uint32_t u32flag) +{ + //DDL_ASSERT(IS_VALID_CLEAR_FLASH_FLAG(u32flag)); + + M4_EFM->FSCLR = u32flag; +} +/** + ******************************************************************************* + ** \brief Get the flash status. + ** + ** \param None + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_efm_flash_status_t EFM_GetStatus(void) +{ + en_efm_flash_status_t enFlashStatus = FlashEOP; + + if(1ul == M4_EFM->FSR_f.RDY ) + { + enFlashStatus = FlashReady; + } + else if(1ul == M4_EFM->FSR_f.COLERR) + { + enFlashStatus = FlashRWErr; + } + else if(1ul == M4_EFM->FSR_f.OPTEND) + { + enFlashStatus = FlashEOP; + } + else if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enFlashStatus = FlashPgMissMatch; + } + else if(1ul == M4_EFM->FSR_f.PGSZERR) + { + enFlashStatus = FlashPgSizeErr; + } + else if(1ul == M4_EFM->FSR_f.PEPRTERR) + { + enFlashStatus = FlashPgareaPErr; + } + else if(1ul == M4_EFM->FSR_f.PEWERR) + { + enFlashStatus = FlashWRPErr; + } + else + { + //else + } + + return enFlashStatus; +} + +/** + ******************************************************************************* + ** \brief Set flash the windows protect address. + ** + ** \param [in] stcAddr The specified windows protect address. + ** \arg StartAddr The start of windows protect address. + ** \arg EndAddr The end of windows protect address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr) +{ + M4_EFM->FPMTSW_f.FPMTSW = (stcAddr.StartAddr & EFM_PROTECT_ADDR_MSK); + M4_EFM->FPMTEW_f.FPMTEW = (stcAddr.EndAddr & EFM_PROTECT_ADDR_MSK); +} + +/** + ******************************************************************************* + ** \brief Set bus state while flash program & erase. + ** + ** \param [in] enState The specified bus state while flash program & erase. + ** \arg BusBusy The bus busy. + ** \arg BusRelease The bus release. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetBusState(en_efm_bus_sta_t enState) +{ + M4_EFM->FWMC_f.BUSHLDCTL = enState; +} + +/** + ******************************************************************************* + ** \brief Flash single program without read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(u32Data != *(uint32_t*)u32Addr) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash single program with read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp = 0u; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program with read back mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAMRB; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +static void *EFM_Memcpy(void *pvDst, void *pvSrc, uint32_t u32Count) +{ + uint8_t *u8TmpDst = (uint8_t *)pvDst; + uint8_t *u8TmpSrc = (uint8_t *)pvSrc; + + DDL_ASSERT(IS_VALID_POINTER(pvDst)); + DDL_ASSERT(IS_VALID_POINTER(pvSrc)); + + while (u32Count--) + { + *u8TmpDst++ = *u8TmpSrc++; + } + + return pvDst; +} +/** + ******************************************************************************* + ** \brief Flash sequence program. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Len The len of specified program data. + ** \param [in] *pBuf The pointer of specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint32_t i; + uint16_t u16Timeout = 0u; + uint32_t u32Tmp = 0xFFFFFFFFul; + uint32_t *u32pSrc = pBuf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LoopWords = u32Len >> 2ul; + uint32_t u32RemainBytes = u32Len % 4ul; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_POINTER(pBuf)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set sequence program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SEQUENCEPROGRAM; + /* clear read collided error flag.*/ + EFM_ClearFlag(EFM_FLAG_COLERR); + EFM_ClearFlag(EFM_FLAG_WRPERR); + + /* program data. */ + for(i = 0ul; i < u32LoopWords; i++) + { + *u32pDest++ = *u32pSrc++; + /* wait operate end. */ + while(1ul != M4_EFM->FSR_f.OPTEND) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + /* clear end flag. */ + EFM_ClearFlag(EFM_FLAG_EOP); + } + if(u32RemainBytes) + { + EFM_Memcpy(&u32Tmp, u32pSrc, u32RemainBytes); + *u32pDest++ = u32Tmp; + } + + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + + u16Timeout = 0u; + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash sector erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the specified sector. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_SectorErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SECTORERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash mass erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the flash. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_MassErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_CHIPERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flash switch status. + ** + ** \param None. + ** + ** \retval en_flag_status_t + ** \arg Set The flash has switched, the start address is sector1. + ** \arg Reset The flash did not switch, the start address is sector0. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetSwitchStatus(void) +{ + return ((0u == M4_EFM->FSWP_f.FSWP) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Lock OTP data block. + ** + ** \param u32Addr The addr to lock. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_OtpLock(uint32_t u32Addr) +{ + DDL_ASSERT(IS_VALID_OTP_LOCK_ADDR(u32Addr)); + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + + /* Lock the otp block. */ + *(uint32_t*)u32Addr = 0ul; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + return enRet; +} +/** + ******************************************************************************* + ** \brief read unique ID. + ** + ** \param None + ** + ** \retval uint32_t + ** + ** \note None + ** + ******************************************************************************/ +stc_efm_unique_id_t EFM_ReadUID(void) +{ + stc_efm_unique_id_t stcUID; + + stcUID.uniqueID1 = M4_EFM->UQID1; + stcUID.uniqueID2 = M4_EFM->UQID2; + stcUID.uniqueID3 = M4_EFM->UQID3; + + return stcUID; +} + +//@} // EfmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_emb.c b/lib/hc32f460/driver/src/hc32f460_emb.c new file mode 100644 index 000000000000..5e50088e6f0a --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_emb.c @@ -0,0 +1,483 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.c + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_emb.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup EMBGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for emb unit */ +#define IS_VALID_EMB_UNIT(__EMBx__) \ +( (M4_EMB1 == (__EMBx__)) || \ + (M4_EMB2 == (__EMBx__)) || \ + (M4_EMB3 == (__EMBx__)) || \ + (M4_EMB4 == (__EMBx__))) + +/*!< Parameter valid check for emb status*/ +#define IS_VALID_EMB_STATUS_TYPE(x) \ +( (EMBFlagPortIn == (x)) || \ + (EMBFlagPWMSame == (x)) || \ + (EMBFlagCmp == (x)) || \ + (EMBFlagOSCFail == (x)) || \ + (EMBPortInState == (x)) || \ + (EMBPWMState == (x))) + +/*!< Parameter valid check for emb status clear*/ +#define IS_VALID_EMB_STATUS_CLR(x) \ +( (EMBPortInFlagClr == (x)) || \ + (EMBPWMSameFlagCLr == (x)) || \ + (EMBCmpFlagClr == (x)) || \ + (EMBOSCFailFlagCLr == (x))) + +/*!< Parameter valid check for emb irq enable*/ +#define IS_VALID_EMB_IRQ(x) \ +( (PORTBrkIrq == (x)) || \ + (PWMSmBrkIrq == (x)) || \ + (CMPBrkIrq == (x)) || \ + (OSCFailBrkIrq == (x))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief EMB interrupt request enable or disable + * + * \param [in] EMBx EMB unit + * \param [in] enEMBIrq Irq type + * \param [in] bEn true/false + * + * \retval en_result_t Ok: config success + ******************************************************************************/ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_IRQ(enEMBIrq)); + + enRet = Ok; + switch (enEMBIrq) + { + case PORTBrkIrq: + EMBx->INTEN_f.PORTINTEN = (uint32_t)bEn; + break; + case PWMSmBrkIrq: + EMBx->INTEN_f.PWMINTEN = (uint32_t)bEn; + break; + case CMPBrkIrq: + EMBx->INTEN_f.CMPINTEN = (uint32_t)bEn; + break; + case OSCFailBrkIrq: + EMBx->INTEN_f.OSINTEN = (uint32_t)bEn; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get EMB status + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatus EMB status type + ** + ** \retval EMB status + ** + ******************************************************************************/ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus) +{ + bool status = false; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + DDL_ASSERT(IS_VALID_EMB_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case EMBFlagPortIn: + status = EMBx->STAT_f.PORTINF; + break; + case EMBFlagPWMSame: + status = EMBx->STAT_f.PWMSF; + break; + case EMBFlagCmp: + status = EMBx->STAT_f.CMPF; + break; + case EMBFlagOSCFail: + status = EMBx->STAT_f.OSF; + break; + case EMBPortInState: + status = EMBx->STAT_f.PORTINST; + break; + case EMBPWMState: + status = EMBx->STAT_f.PWMST; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief EMB clear status(Recover from protection state) + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatusClr EMB status clear type + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATUS_CLR(enStatusClr)); + + enRet = Ok; + switch (enStatusClr) + { + case EMBPortInFlagClr: + EMBx->STATCLR_f.PORTINFCLR = 1ul; + break; + case EMBPWMSameFlagCLr: + EMBx->STATCLR_f.PWMSFCLR = 1ul; + break; + case EMBCmpFlagClr: + EMBx->STATCLR_f.CMPFCLR = 1ul; + break; + case EMBOSCFailFlagCLr: + EMBx->STATCLR_f.OSFCLR = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBConfigCR) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer61PWMSBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer62PWMSBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer63PWMSBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + M4_EMB1->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((M4_EMB1 != EMBx) && \ + (IS_VALID_EMB_UNIT(EMBx)) && \ + (NULL != pstcEMBConfigCR)) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer4xWHLSammeBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer4xVHLSammeBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer4xUHLSammeBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + EMBx->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBPWMlv) + { + if (pstcEMBPWMlv->bEnTimer61HighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnTimer62HighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnTimer63HighLevelDect) + { + u32Val |= 0x4ul; + } + + M4_EMB1->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_EMB_UNIT(EMBx)) && \ + (M4_EMB1 != EMBx) && \ + (NULL != pstcEMBPWMlv)) + { + if (pstcEMBPWMlv->bEnWHLphaseHighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnVHLPhaseHighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnUHLPhaseHighLevelDect) + { + u32Val |= 0x4ul; + } + + EMBx->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief EMB Software brake + ** + ** \param [in] EMBx EMB unit + ** +** \param [in] bEn true: Software Brake Enable / false: Software Brake Disable + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + + EMBx->SOE_f.SOE = (uint32_t)bEn; + + return Ok; +} + +//@} // EMBGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_event_port.c b/lib/hc32f460/driver/src/hc32f460_event_port.c new file mode 100644 index 000000000000..4141d630bcba --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_event_port.c @@ -0,0 +1,464 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.c + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_event_port.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup EventPortGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EP1_BASE 0x40010800ul + 0x0100ul +#define EP2_BASE 0x40010800ul + 0x011Cul +#define EP3_BASE 0x40010800ul + 0x0138ul +#define EP4_BASE 0x40010800ul + 0x0154ul +#define EP1_DIR_BASE 0x00ul +#define EP1_IDR_BASE 0x04ul +#define EP1_ODR_BASE 0x08ul +#define EP1_ORR_BASE 0x0Cul +#define EP1_OSR_BASE 0x10ul +#define EP1_RISR_BASE 0x14ul +#define EP1_FAL_BASE 0x18ul +#define EP_NFCR_BASE 0x40010800ul + 0x0170ul + + +/*! Parameter validity check for port group. */ +#define IS_VALID_EVENT_PORT(x) \ +( ((x) == EventPort1) || \ + ((x) == EventPort2) || \ + ((x) == EventPort3) || \ + ((x) == EventPort4)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_EVENT_PIN(x) \ +( ((x) == EventPin00) || \ + ((x) == EventPin01) || \ + ((x) == EventPin02) || \ + ((x) == EventPin03) || \ + ((x) == EventPin04) || \ + ((x) == EventPin05) || \ + ((x) == EventPin06) || \ + ((x) == EventPin07) || \ + ((x) == EventPin08) || \ + ((x) == EventPin09) || \ + ((x) == EventPin10) || \ + ((x) == EventPin11) || \ + ((x) == EventPin12) || \ + ((x) == EventPin13) || \ + ((x) == EventPin14) || \ + ((x) == EventPin15)) + +/*! Parameter valid check for Event Port common trigger. */ +#define IS_EP_COM_TRIGGER(x) \ +( ((x) == EpComTrigger_1) || \ + ((x) == EpComTrigger_2) || \ + ((x) == EpComTrigger_1_2)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port init + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \param [in] pstcEventPortInit Structure pointer of event port configuration + ** + ** \retval Ok Init successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_Init(en_event_port_t enEventPort, uint16_t u16EventPin, \ + const stc_event_port_init_t *pstcEventPortInit) +{ + en_result_t enRet = Ok; + + uint32_t *EPDIRx; ///< Direction register + uint32_t *EPORRx; ///< Reset after trigger enable register + uint32_t *EPOSRx; ///< Set after trigger enable register + uint32_t *EPRISRx; ///< Rising edge detect enable register + uint32_t *EPFALx; ///< Falling edge detect enable register + + EPDIRx = (uint32_t *)(EP1_BASE + EP1_DIR_BASE + (0x1C * enEventPort)); + EPORRx = (uint32_t *)(EP1_BASE + EP1_ORR_BASE + (0x1C * enEventPort)); + EPOSRx = (uint32_t *)(EP1_BASE + EP1_OSR_BASE + (0x1C * enEventPort)); + EPRISRx= (uint32_t *)(EP1_BASE + EP1_RISR_BASE+ (0x1C * enEventPort)); + EPFALx = (uint32_t *)(EP1_BASE + EP1_FAL_BASE + (0x1C * enEventPort)); + + /* Direction configure */ + if (EventPortOut == pstcEventPortInit->enDirection) + { + *EPDIRx |= u16EventPin; + } + else + { + *EPDIRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Reset if be triggered */ + if (Enable == pstcEventPortInit->enReset) + { + *EPORRx |= u16EventPin; + } + else + { + *EPORRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Set if be triggered */ + if (Enable == pstcEventPortInit->enSet) + { + *EPOSRx |= u16EventPin; + } + else + { + *EPOSRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Rising edge detect setting */ + if (Enable == pstcEventPortInit->enRisingDetect) + { + *EPRISRx |= u16EventPin; + } + else + { + *EPRISRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Falling edge detect setting */ + if (Enable == pstcEventPortInit->enFallingDetect) + { + *EPFALx |= u16EventPin; + } + else + { + *EPFALx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Noise filter setting */ + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTNFCR_f.NFEN1 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS1 = pstcEventPortInit->enFilterClk; + break; + case EventPort2: + M4_AOS->PEVNTNFCR_f.NFEN2 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS2 = pstcEventPortInit->enFilterClk; + break; + case EventPort3: + M4_AOS->PEVNTNFCR_f.NFEN3 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS3 = pstcEventPortInit->enFilterClk; + break; + case EventPort4: + M4_AOS->PEVNTNFCR_f.NFEN4 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS4 = pstcEventPortInit->enFilterClk; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event Port de-init, restore all registers to default value + ** + ** \param None + ** + ** \retval Ok De-init successful + ** + ******************************************************************************/ +en_result_t EVENTPORT_DeInit(void) +{ + uint32_t EPDIRx ; + uint32_t EPODRx ; + uint32_t EPORRx ; + uint32_t EPOSRx ; + uint32_t EPRISRx; + uint32_t EPFALx ; + uint8_t u8EPCnt; + + EPDIRx = (uint32_t)(EP1_BASE + EP1_DIR_BASE); + EPODRx = (uint32_t)(EP1_BASE + EP1_ODR_BASE); + EPORRx = (uint32_t)(EP1_BASE + EP1_ORR_BASE); + EPOSRx = (uint32_t)(EP1_BASE + EP1_OSR_BASE); + EPRISRx = (uint32_t)(EP1_BASE + EP1_RISR_BASE); + EPFALx = (uint32_t)(EP1_BASE + EP1_FAL_BASE); + + /* Restore all registers to default value */ + M4_AOS->PEVNTTRGSR12 = 0x1FFul; + M4_AOS->PEVNTTRGSR34 = 0x1FFul; + M4_AOS->PEVNTNFCR = 0ul; + for (u8EPCnt = 0u; u8EPCnt < 4u; u8EPCnt++) + { + *(uint32_t *)(EPDIRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPODRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPORRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPOSRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPRISRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPFALx + 0x1Cul * u8EPCnt) = 0ul; + } + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event Port trigger source select + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enTriggerSrc Event port trigger source. This parameter + ** can be any value of @ref en_event_src_t + ** \retval Ok Trigger source is set + ** ErrorInvalidParameter Invalid event port enum + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + if ((EventPort1 == enEventPort) || (EventPort2 == enEventPort)) + { + M4_AOS->PEVNTTRGSR12 = enTriggerSrc; + } + else if ((EventPort3 == enEventPort) || (EventPort4 == enEventPort)) + { + M4_AOS->PEVNTTRGSR34 = enTriggerSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Event Port common trigger. + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enComTrigger Event port common trigger selection. + ** See @ref en_event_port_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx; + + TRGSELx = (__IO uint32_t *)((uint32_t)&M4_AOS->PEVNTTRGSR12 + (4UL * ((uint32_t)enEventPort/2UL))); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_EP_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Read Event Port value after be triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t EVENTPORT_GetData(en_event_port_t enEventPort) +{ + uint16_t u16Data = 0u; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + switch (enEventPort) + { + case EventPort1: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR1 & 0xFFFFul); + break; + case EventPort2: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR2 & 0xFFFFul); + break; + case EventPort3: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR3 & 0xFFFFul); + break; + case EventPort4: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR4 & 0xFFFFul); + break; + } + return u16Data; +} + +/** + ******************************************************************************* + ** \brief Read Event Pin value after triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enEventPin GPIO pin index, This parameter can be + ** any value of @ref en_event_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, en_event_pin_t enEventPin) +{ + bool bBitValue = false; + + switch (enEventPort) + { + case EventPort1: + bBitValue = M4_AOS->PEVNTIDR1 & enEventPin; + break; + case EventPort2: + bBitValue = M4_AOS->PEVNTIDR2 & enEventPin; + break; + case EventPort3: + bBitValue = M4_AOS->PEVNTIDR3 & enEventPin; + break; + case EventPort4: + bBitValue = M4_AOS->PEVNTIDR4 & enEventPin; + break; + } + return (en_flag_status_t)(bool)((!!bBitValue)); +} + +/** + ******************************************************************************* + ** \brief Set Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Set successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 |= u16EventPin; + break; + case EventPort2: + M4_AOS->PEVNTODR2 |= u16EventPin; + break; + case EventPort3: + M4_AOS->PEVNTODR3 |= u16EventPin; + break; + case EventPort4: + M4_AOS->PEVNTODR4 |= u16EventPin; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reset Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Reset successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort2: + M4_AOS->PEVNTODR2 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort3: + M4_AOS->PEVNTODR3 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort4: + M4_AOS->PEVNTODR4 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +//@} // EventPortGroup + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_exint_nmi_swi.c b/lib/hc32f460/driver/src/hc32f460_exint_nmi_swi.c new file mode 100644 index 000000000000..71111b253769 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_exint_nmi_swi.c @@ -0,0 +1,333 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.c + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_exint_nmi_swi.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup ExintNmiSwiGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + /*! Parameter validity check for external interrupt channel. */ +#define IS_VALID_CH(x) \ +( ((x) == ExtiCh00) || \ + ((x) == ExtiCh01) || \ + ((x) == ExtiCh02) || \ + ((x) == ExtiCh03) || \ + ((x) == ExtiCh04) || \ + ((x) == ExtiCh05) || \ + ((x) == ExtiCh06) || \ + ((x) == ExtiCh07) || \ + ((x) == ExtiCh08) || \ + ((x) == ExtiCh09) || \ + ((x) == ExtiCh10) || \ + ((x) == ExtiCh11) || \ + ((x) == ExtiCh12) || \ + ((x) == ExtiCh13) || \ + ((x) == ExtiCh14) || \ + ((x) == ExtiCh15)) + +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Parameter validity check for external interrupt trigger method. */ +#define IS_VALID_LEVEL(x) \ +( ((x) == ExIntLowLevel) || \ + ((x) == ExIntBothEdge) || \ + ((x) == ExIntRisingEdge) || \ + ((x) == ExIntFallingEdge)) + +/*! Parameter validity check for NMI interrupt source. */ +#define IS_VALID_NMI_SRC(x) \ +( ((x) == NmiSrcNmi) || \ + ((x) == NmiSrcSwdt) || \ + ((x) == NmiSrcVdu1) || \ + ((x) == NmiSrcVdu2) || \ + ((x) == NmiSrcXtalStop) || \ + ((x) == NmiSrcSramPE) || \ + ((x) == NmiSrcSramDE) || \ + ((x) == NmiSrcMpu) || \ + ((x) == NmiSrcWdt)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnNmiCallback; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief External Int initialization + ** + ** \param [in] pstcExtiConfig EXTI configure structure + ** + ** \retval Ok EXTI initialized + ** + ******************************************************************************/ +en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig) +{ + stc_intc_eirqcr_field_t *EIRQCRx; + + DDL_ASSERT(IS_VALID_CH(pstcExtiConfig->enExitCh)); + + EIRQCRx = (stc_intc_eirqcr_field_t *)((uint32_t)(&M4_INTC->EIRQCR0) + \ + (uint32_t)(4ul * (uint32_t)(pstcExtiConfig->enExitCh))); + + /* Set filter function */ + EIRQCRx->EFEN = pstcExtiConfig->enFilterEn; + EIRQCRx->EISMPCLK = pstcExtiConfig->enFltClk; + + /* Set detection level */ + EIRQCRx->EIRQTRG = pstcExtiConfig->enExtiLvl; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get External interrupt request flag + ** + ** \param [in] enExint NMI Int source, This parameter can be + ** any value of @ref en_exti_ch_t + ** + ** \retval Set Corresponding Ex.Int request flag be set + ** Reset Corresponding Ex.Int request flag not be set + ** + ******************************************************************************/ +en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint) +{ + en_int_status_t enRet; + DDL_ASSERT(IS_VALID_CH(enExint)); + + enRet = (1u == !!(M4_INTC->EIFR & (1ul<EICFR |= (uint32_t)(1ul << enExint); + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI initialization + ** + ** \param [in] pstcNmiConfig NMI configure structure + ** + ** \retval Ok NMI initialized + ** ErrorInvalidParameter NMI configuration pointer is null + ** + ******************************************************************************/ +en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcNmiConfig) + { + /* NMI callback function */ + pfnNmiCallback = pstcNmiConfig->pfnNmiCallback; + /* Set filter function */ + M4_INTC->NMICR_f.NFEN = pstcNmiConfig->enFilterEn; + /* Set filter clock */ + M4_INTC->NMICR_f.NSMPCLK = pstcNmiConfig->enFilterClk; + /* Set detection level */ + M4_INTC->NMICR_f.NMITRG = pstcNmiConfig->enNmiLvl; + /* Set NMI source */ + M4_INTC->NMIENR = (uint32_t)pstcNmiConfig->u16NmiSrc; + enRet = Ok; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Init Non-Maskable Interrupt (NMI) + ** + ** \param None + ** + ** \retval Ok NMI De-initialized + ** + ******************************************************************************/ +en_result_t NMI_DeInit(void) +{ + /* Set internal data */ + pfnNmiCallback = NULL; + + /* clear NMI control register */ + M4_INTC->NMICR = 0u; + + /* clear NMI enable register */ + M4_INTC->NMIENR = 0u; + + /* clear all NMI flags */ + M4_INTC->NMIFR = 0u; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get NMI interrupt request flag + ** + ** \param [in] enNmiSrc NMI Int source, This parameter can be + ** any value of @ref en_nmi_src_t + ** + ** \retval Set Corresponding NMI flag be set + ** Reset Corresponding NMI flag not be set + ** + ******************************************************************************/ +en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc) +{ + DDL_ASSERT(IS_VALID_NMI_SRC(enNmiSrc)); + + en_int_status_t enRet = Reset; + switch (enNmiSrc) + { + case NmiSrcNmi: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.NMIFR); + break; + case NmiSrcSwdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.SWDTFR); + break; + case NmiSrcVdu1: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD1FR); + break; + case NmiSrcVdu2: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD2FR); + break; + case NmiSrcXtalStop: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.XTALSTPFR); + break; + case NmiSrcSramPE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.REPFR); + break; + case NmiSrcSramDE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.RECCFR); + break; + case NmiSrcMpu: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.BUSMFR); + break; + case NmiSrcWdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.WDTFR); + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear NMI interrupt request flag + ** + ** \param [in] u16NmiSrc NMI Int source, This parameter can be + ** any composited value of @ref en_nmi_src_t + ** + ** \retval Ok Interrupt source be cleared + ** + ******************************************************************************/ +en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc) +{ + M4_INTC->NMICFR |= u16NmiSrc; + return Ok; +} + +/** + ******************************************************************************* + ** \brief ISR for NMI + ** + ******************************************************************************/ +void NMI_IrqHandler(void) +{ + DDL_ASSERT(IS_NULL_POINT(pfnNmiCallback)); + + pfnNmiCallback(); +} + +/** + ******************************************************************************* + ** \brief Enable Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI initialized + ** + ******************************************************************************/ +en_result_t SWI_Enable(uint32_t u32SwiCh) +{ + M4_INTC->SWIER |= u32SwiCh; + return Ok; +} + +/** + ******************************************************************************* + ** \brief De-Init Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI de-initialized + ** + ******************************************************************************/ +en_result_t SWI_Disable(uint32_t u32SwiCh) +{ + /* clear software interrupt enable register */ + M4_INTC->SWIER &= ~u32SwiCh; + + return Ok; +} + +//@} // ExintNmiSwiGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_gpio.c b/lib/hc32f460/driver/src/hc32f460_gpio.c new file mode 100644 index 000000000000..d9b31e5e9d6c --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_gpio.c @@ -0,0 +1,667 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.c + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_gpio.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define GPIO_BASE (0x40053800ul) +#define PODR_BASE (0x0004ul) +#define POER_BASE (0x0006ul) +#define POSR_BASE (0x0008ul) +#define PORR_BASE (0x000Aul) +#define PCR_BASE (0x0400ul) +#define PFSR_BASE (0x0402ul) + +/*! Parameter validity check for port group. */ +#define IS_VALID_PORT(x) \ +( ((x) == PortA) || \ + ((x) == PortB) || \ + ((x) == PortC) || \ + ((x) == PortD) || \ + ((x) == PortE) || \ + ((x) == PortH)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_PIN(x) \ +( ((x) == Pin00) || \ + ((x) == Pin01) || \ + ((x) == Pin02) || \ + ((x) == Pin03) || \ + ((x) == Pin04) || \ + ((x) == Pin05) || \ + ((x) == Pin06) || \ + ((x) == Pin07) || \ + ((x) == Pin08) || \ + ((x) == Pin09) || \ + ((x) == Pin10) || \ + ((x) == Pin11) || \ + ((x) == Pin12) || \ + ((x) == Pin13) || \ + ((x) == Pin14) || \ + ((x) == Pin15)) + +/*! Parameter validity check for debug pins. */ +#define IS_VALID_DEBUGPIN(x) ((x) <= 0x1Fu) + +/*! Parameter validity check for pin mode. */ +#define IS_VALID_PINMODE(x) \ +( ((x) == Pin_Mode_In) || \ + ((x) == Pin_Mode_Out) || \ + ((x) == Pin_Mode_Ana)) + +/*! Parameter validity check for pin drive capacity. */ +#define IS_VALID_PINDRV(x) \ +( ((x) == Pin_Drv_L) || \ + ((x) == Pin_Drv_M) || \ + ((x) == Pin_Drv_H)) + +/*! Parameter validity check for pin output type. */ +#define IS_VALID_PINTYPE(x) \ +( ((x) == Pin_OType_Cmos) || \ + ((x) == Pin_OType_Od)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_VALID_READWAIT(x) \ +( ((x) == WaitCycle0) || \ + ((x) == WaitCycle1) || \ + ((x) == WaitCycle2) || \ + ((x) == WaitCycle3)) + +/*! Parameter validity check for pin function */ +#define IS_VALID_FUNC(x) \ +( ((x) == Func_Gpio) || \ + (((x) >= Func_Fcmref) && \ + ((x) <= Func_I2s)) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout) || \ + (((x) >= Func_Usart1_Tx) && \ + ((x) <= Func_I2s2_Ck))) + +/*! Parameter validity check for pin sub-function */ +#define IS_VALID_SUBFUNC(x) \ +( ((x) == Func_Gpio) || \ + ((x) == Func_Fcmref) || \ + ((x) == Func_Rtcout) || \ + ((x) == Func_Vcout) || \ + ((x) == Func_Adtrg) || \ + ((x) == Func_Mclkout) || \ + ((x) == Func_Tim4) || \ + ((x) == Func_Tim6) || \ + ((x) == Func_Tima0) || \ + ((x) == Func_Tima1) || \ + ((x) == Func_Tima2) || \ + ((x) == Func_Emb) || \ + ((x) == Func_Usart_Ck) || \ + ((x) == Func_Spi_Nss) || \ + ((x) == Func_Qspi) || \ + ((x) == Func_Key) || \ + ((x) == Func_Sdio) || \ + ((x) == Func_I2s) || \ + ((x) == Func_UsbF) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Port init + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] pstcPortInit Structure pointer of port configuration + ** + ** \retval Ok Port initial successful + ** + ******************************************************************************/ +en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, const stc_port_init_t *pstcPortInit) +{ + stc_port_pcr_field_t *PCRx; + stc_port_pfsr_field_t * PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + DDL_ASSERT(IS_VALID_PINMODE(pstcPortInit->enPinMode)); + DDL_ASSERT(IS_VALID_PINDRV(pstcPortInit->enPinDrv)); + DDL_ASSERT(IS_VALID_PINTYPE(pstcPortInit->enPinOType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enLatch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enExInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enInvert)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPullUp)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPinSubFunc)); + + PORT_Unlock(); + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (1ul<PCRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + + /* Input latch function setting */ + PCRx->LTE = pstcPortInit->enLatch; + + /* External interrupt input enable setting */ + PCRx->INTE = pstcPortInit->enExInt; + + /* In_Out invert setting */ + PCRx->INVE = pstcPortInit->enInvert; + + /* Pin pull-up setting */ + PCRx->PUU = pstcPortInit->enPullUp; + + /* CMOS/OD output setting */ + PCRx->NOD = pstcPortInit->enPinOType; + + /* Pin drive mode setting */ + PCRx->DRV = pstcPortInit->enPinDrv; + + /* Pin mode setting */ + switch (pstcPortInit->enPinMode) + { + case Pin_Mode_In: + PCRx->DDIS = 0u; + PCRx->POUTE = 0u; + break; + case Pin_Mode_Out: + PCRx->DDIS = 0u; + PCRx->POUTE = 1u; + break; + case Pin_Mode_Ana: + PCRx->DDIS = 1u; + break; + default: + break; + } + /* Sub function enable setting */ + PFSRx->BFE = pstcPortInit->enPinSubFunc; + } + } + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port de-init + ** + ** \param None + ** + ** \retval Ok GPIO de-initial successful + ** + ******************************************************************************/ +en_result_t PORT_DeInit(void) +{ + uint8_t u8PortIdx, u8PinIdx; + PORT_Unlock(); + + for (u8PortIdx = (uint8_t)PortA; u8PortIdx <= (uint8_t)PortH; u8PortIdx++) + { + *(uint16_t *)(GPIO_BASE + PODR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POER_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POSR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + PORR_BASE + u8PortIdx * 0x10ul) = 0u; + for (u8PinIdx = 0u; u8PinIdx < 16u; u8PinIdx++) + { + if (((uint8_t)PortH == u8PortIdx) && (3u == u8PinIdx)) + { + break; + } + *(uint16_t *)(GPIO_BASE + PCR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + *(uint16_t *)(GPIO_BASE + PFSR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + } + } + M4_PORT->PCCR = 0u; + M4_PORT->PINAER = 0u; + M4_PORT->PSPCR = 0x1Fu; + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Special control register Setting + ** + ** \param [in] u8DebugPort Debug port setting register, This parameter + ** can be any composed value of @ref en_debug_port_t + ** + ** \param [in] enFunc The new state of the debug ports. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Debug port set successful + ** + ******************************************************************************/ +en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_DEBUGPIN(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enFunc)); + + PORT_Unlock(); + + if (Enable == enFunc) + { + M4_PORT->PSPCR |= (uint16_t)(u8DebugPort & 0x1Ful); + } + else + { + M4_PORT->PSPCR &= (uint16_t)(~(u8DebugPort & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Public Setting + ** + ** \param [in] pstcPortPubSet Structure pointer of public setting (PCCR) + ** + ** \retval Ok Port public register set successful + ** + ******************************************************************************/ +en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet) +{ + DDL_ASSERT(IS_VALID_FUNC(pstcPortPubSet->enSubFuncSel)); + DDL_ASSERT(IS_VALID_READWAIT(pstcPortPubSet->enReadWait)); + PORT_Unlock(); + + /* PCCR setting */ + /* Sub function setting */ + M4_PORT->PCCR_f.BFSEL = pstcPortPubSet->enSubFuncSel; + + /* PIDRx, PCRxy read wait cycle setting */ + M4_PORT->PCCR_f.RDWT = pstcPortPubSet->enReadWait; + + PORT_Lock(); + return Ok; +} + + +/** + ******************************************************************************* + ** \brief PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Unlock(void) +{ + M4_PORT->PWPR = 0xA501u; +} + +/** + ******************************************************************************* + ** \brief SPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Lock(void) +{ + M4_PORT->PWPR = 0xA500u; +} + +/** + ******************************************************************************* + ** \brief Read Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t PORT_GetData(en_port_t enPort) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + uint32_t *PIDRx; + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (uint16_t)(*PIDRx); +} + +/** + ******************************************************************************* + ** \brief Read Pin value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enPin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin) +{ + uint32_t *PIDRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_PIN(enPin)); + + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (en_flag_status_t)((bool)(!!(*PIDRx & (enPin)))); +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be set to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be reset to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx &= (uint16_t)(~u16Pin); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Pin Output enable + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] enNewState The new state of pin direction setting + ** \retval Ok Set successful to corresponding port/pin + ** + ******************************************************************************/ +en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint16_t *POERx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POERx = (uint16_t *)((uint32_t)(&M4_PORT->POERA) + 0x10ul * enPort); + if (Enable == enNewState) + { + *POERx |= u16Pin; + } + else + { + *POERx &= (uint16_t)(~u16Pin); + } + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Set Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POSRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POSRx = (uint16_t *)((uint32_t)(&M4_PORT->POSRA) + 0x10u * enPort); + *POSRx |= u16Pin; + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Reset Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PORRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PORRx = (uint16_t *)((uint32_t)(&M4_PORT->PORRA) + 0x10u * enPort); + *PORRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Toggle Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POTRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POTRx = (uint16_t *)((uint32_t)(&M4_PORT->POTRA) + 0x10u * enPort); + *POTRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set port always ON + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enNewState The new state of the port always ON function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_AlwaysOn(en_port_t enPort, en_functional_state_t enNewState) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + PORT_Unlock(); + + if (Enable == enNewState) + { + M4_PORT->PINAER |= Enable << (uint8_t)enPort; + } + else + { + M4_PORT->PINAER &= (uint16_t)(~(((1ul << (uint8_t)enPort)) & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port Pin function + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \param [in] enFuncSel Function selection, This parameter can be + ** any value of @ref en_port_func_t + ** + ** \param [in] enSubFunc The new state of the gpio sub-function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, en_port_func_t enFuncSel, \ + en_functional_state_t enSubFunc) +{ + stc_port_pfsr_field_t *PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_FUNC(enFuncSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enSubFunc)); + + PORT_Unlock(); + + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (uint16_t)(1ul<PFSRA0) \ + + 0x40ul * enPort + 0x4ul * u8PinPos); + + /* main function setting */ + PFSRx->FSEL = enFuncSel; + + /* sub function enable setting */ + PFSRx->BFE = (Enable == enSubFunc ? Enable : Disable); + } + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set global sub-function + ** + ** \param [in] enFuncSel Function selection, This parameter can be + ** some values of @ref en_port_func_t, cannot + ** large than 15u + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_SUBFUNC(enFuncSel)); + + PORT_Unlock(); + + M4_PORT->PCCR_f.BFSEL = enFuncSel; + + PORT_Lock(); + return Ok; +} + +//@} // GpioGroup + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_hash.c b/lib/hc32f460/driver/src/hc32f460_hash.c new file mode 100644 index 000000000000..4ae8173dd269 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_hash.c @@ -0,0 +1,297 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.c + ** + ** A detailed description is available at + ** @link HashGroup HASH description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of HASH. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_hash.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup HashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Constants definitions. */ +#define HASH_GROUP_LEN (64u) +#define LAST_GROUP_MAX_LEN (56u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData); +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_Init(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; +} + +/** + ******************************************************************************* + ** \brief DeInitialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_DeInit(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; + + /* Reset register CR. */ + M4_HASH->CR = 0u; +} + +/** + ******************************************************************************* + ** \brief HASH(SHA256) processes pu8SrcData. + ** + ** \param [in] pu8SrcData Pointer to the source data buffer (buffer to + ** be hashed). + ** + ** \param [in] u32SrcDataSize Length of the input buffer in bytes. + ** + ** \param [out] pu8MsgDigest Pointer to the computed digest. Its size + ** must be 32 bytes. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout HASH works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8FillBuffer[HASH_GROUP_LEN]; + uint8_t u8FirstGroup = 0u; + uint8_t u8HashEnd = 0u; + uint8_t u8DataEndMark = 0u; + uint32_t u32Index = 0u; + uint32_t u32BitLenHi; + uint32_t u32BitLenLo; + uint32_t u32HashTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8SrcData) && + (0u != u32SrcDataSize) && + (NULL != pu8MsgDigest) && + (0u != u32Timeout)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32HashTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32BitLenHi = (u32SrcDataSize >> 29u) & 0x7u; + u32BitLenLo = (u32SrcDataSize << 3u); + + while (1u) + { + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + + if (u32SrcDataSize >= HASH_GROUP_LEN) + { + HASH_WriteData(&pu8SrcData[u32Index]); + u32SrcDataSize -= HASH_GROUP_LEN; + u32Index += HASH_GROUP_LEN; + } + else if (u32SrcDataSize >= LAST_GROUP_MAX_LEN) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + u8FillBuffer[u32SrcDataSize] = 0x80u; + u8DataEndMark = 1u; + HASH_WriteData(u8FillBuffer); + u32SrcDataSize = 0u; + } + else + { + u8HashEnd = 1u; + } + + if (u8HashEnd != 0u) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + if (u32SrcDataSize > 0u) + { + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + } + if (u8DataEndMark == 0u) + { + u8FillBuffer[u32SrcDataSize] = 0x80u; + } + u8FillBuffer[63u] = (uint8_t)(u32BitLenLo); + u8FillBuffer[62u] = (uint8_t)(u32BitLenLo >> 8u); + u8FillBuffer[61u] = (uint8_t)(u32BitLenLo >> 16u); + u8FillBuffer[60u] = (uint8_t)(u32BitLenLo >> 24u); + u8FillBuffer[59u] = (uint8_t)(u32BitLenHi); + u8FillBuffer[58u] = (uint8_t)(u32BitLenHi >> 8u); + u8FillBuffer[57u] = (uint8_t)(u32BitLenHi >> 16u); + u8FillBuffer[56u] = (uint8_t)(u32BitLenHi >> 24u); + HASH_WriteData(u8FillBuffer); + } + + /* check if first group */ + if (0u == u8FirstGroup) + { + u8FirstGroup = 1u; + /* Set first group. */ + bM4_HASH_CR_FST_GRP = 1u; + } + else + { + /* Set continuous group. */ + bM4_HASH_CR_FST_GRP = 0u; + } + + /* Start hash calculating. */ + bM4_HASH_CR_START = 1u; + + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32HashTimeout) + { + if (bM4_HASH_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if ((ErrorTimeout == enRet) || (u8HashEnd != 0u)) + { + break; + } + } + + if (Ok == enRet) + { + /* HASH calculated done */ + HASH_GetMsgDigest(pu8MsgDigest); + } + + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashDr = &(M4_HASH->DR15); + + for (i = 0u; i < 16u; i++) + { + j = i * 4u + 3u; + u32Temp = (uint32_t)pu8SrcData[j]; + u32Temp |= ((uint32_t)pu8SrcData[j-1u]) << 8u; + u32Temp |= ((uint32_t)pu8SrcData[j-2u]) << 16u; + u32Temp |= ((uint32_t)pu8SrcData[j-3u]) << 24u; + + *io32HashDr = u32Temp; + io32HashDr++; + } +} + +/** + ******************************************************************************* + ** \brief Provides the message digest result. + ** + ** \param [out] pu8MsgDigest Pointer to the message digest. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashHr = &(M4_HASH->HR7); + + for (i = 0u; i < 8u; i++) + { + j = i * 4u + 3u; + u32Temp = *io32HashHr; + + pu8MsgDigest[j] = (uint8_t)u32Temp; + pu8MsgDigest[j-1u] = (uint8_t)(u32Temp >> 8u); + pu8MsgDigest[j-2u] = (uint8_t)(u32Temp >> 16u); + pu8MsgDigest[j-3u] = (uint8_t)(u32Temp >> 24u); + + io32HashHr++; + } +} + +//@} // HashGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_i2c.c b/lib/hc32f460/driver/src/hc32f460_i2c.c new file mode 100644 index 000000000000..d7728ae91906 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_i2c.c @@ -0,0 +1,1314 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.c + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2c.h" +#include "hc32f460_utility.h" +#include + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Config I2C peripheral */ +#define I2C_SRC_CLK (SystemCoreClock >> M4_SYSREG->CMU_SCFGR_f.PCLK3S) +#define I2C_ANA_FILTER_VALID (1U) +#define I2C_CLK_TIMEOUT_VALID (1U) + +#define I2C_BAUDRATE_MAX (400000ul) + +/*! Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_I2C1) || \ + ((x) == M4_I2C2) || \ + ((x) == M4_I2C3)) + +/*! Parameter check for I2C baudrate value !*/ +#define IS_VALID_SPEED(speed) ((speed) <= (I2C_BAUDRATE_MAX)) + +/*! Parameter check for I2C baudrate calculate prccess !*/ +#define IS_VALID_FDIV(x) \ +( ((x) == I2C_CLK_DIV1) || \ + ((x) == I2C_CLK_DIV2) || \ + ((x) == I2C_CLK_DIV4) || \ + ((x) == I2C_CLK_DIV8) || \ + ((x) == I2C_CLK_DIV16) || \ + ((x) == I2C_CLK_DIV32) || \ + ((x) == I2C_CLK_DIV64) || \ + ((x) == I2C_CLK_DIV128)) + +#define IS_VALID_BAUDWIDTH(result) ((result) == true) + +/*! Parameter check for Digital filter config !*/ +#define IS_VALID_DIGITAL_FILTER(x) \ +( ((x) == Filter1BaseCycle) || \ + ((x) == Filter2BaseCycle) || \ + ((x) == Filter3BaseCycle) || \ + ((x) == Filter4BaseCycle)) + +/*! Parameter check for address mode !*/ +#define IS_VALID_ADRMODE(x) \ +( ((x) == Adr7bit) || \ + ((x) == Adr10bit)) + +/*! Parameter check for I2C transfer direction !*/ +#define IS_VALID_TRANS_DIR(x) \ +( ((x) == I2CDirReceive) || \ + ((x) == I2CDirTrans)) + +/*! Parameter check for Time out control switch !*/ +#define IS_VALID_TIMOUT_SWITCH(x) \ +( ((x) == TimeoutFunOff) || \ + ((x) == LowTimerOutOn) || \ + ((x) == HighTimeOutOn) || \ + ((x) == BothTimeOutOn)) + +/*! Parameter check for I2C 7 bit address range !*/ +#define IS_VALID_7BIT_ADR(x) ((x) <= 0x7F) + +/*! Parameter check for I2C 10 bit address range !*/ +#define IS_VALID_10BIT_ADR(x) ((x) <= 0x3FF) + +/*! Parameter check for readable I2C status bit !*/ +#define IS_VALID_RD_STATUS_BIT(x) \ +( ((x) == I2C_SR_STARTF) || \ + ((x) == I2C_SR_SLADDR0F) || \ + ((x) == I2C_SR_SLADDR1F) || \ + ((x) == I2C_SR_TENDF) || \ + ((x) == I2C_SR_STOPF) || \ + ((x) == I2C_SR_RFULLF) || \ + ((x) == I2C_SR_TEMPTYF) || \ + ((x) == I2C_SR_ARLOF) || \ + ((x) == I2C_SR_ACKRF) || \ + ((x) == I2C_SR_NACKF) || \ + ((x) == I2C_SR_TMOUTF) || \ + ((x) == I2C_SR_MSL) || \ + ((x) == I2C_SR_BUSY) || \ + ((x) == I2C_SR_TRA) || \ + ((x) == I2C_SR_GENCALLF) || \ + ((x) == I2C_SR_SMBDEFAULTF) || \ + ((x) == I2C_SR_SMBHOSTF) || \ + ((x) == I2C_SR_SMBALRTF)) + +#define IS_VALID_ACK_CONFIG(x) \ +( ((x) == I2c_ACK) || \ + ((x) == I2c_NACK)) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1F * (float32_t)2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Try to wait a status of specified flags + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Flag specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \param [in] enStatus Expected status, This parameter can be one of + ** the following values: + ** Set + ** Reset + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Successfully gotten the expected status of the specified flags + ** \retval ErrorTimeout Failed to get expected status of specified flags. + ******************************************************************************/ +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorTimeout; + uint32_t u32RegStatusBit; + + for(;;) + { + u32RegStatusBit = (pstcI2Cx->SR & u32Flag); + if(((enStatus == Set) && (u32Flag == u32RegStatusBit)) + || ((enStatus == Reset) && (0UL == u32RegStatusBit))) + { + enRet = Ok; + } + + if((Ok == enRet) || (0UL == u32Timeout)) + { + break; + } + else + { + u32Timeout--; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C generate start condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState new state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.START = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C generate restart condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.RESTART = enNewState; + +} + +/** + ******************************************************************************* + ** \brief I2C generate stop condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.STOP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the baudrate for I2C peripheral. + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div, + ** from I2C_Clock_Division in i2c driver head file. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRet = Ok; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1ul << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if(1u == pstcI2Cx->FLTR_f.DNFEN) + { + dnfsum = pstcI2Cx->FLTR_f.DNF+1ul; + } + + /* Judge if clock divider on*/ + if(I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) + { + divsum = 3ul; + } + + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F*(float32_t)divsum) + (2.0F*(float32_t)dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) + { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } + else + { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if(WidthTotal <= SumTotal) + { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + if(WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) + { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + + /* Write register */ + pstcI2Cx->CCR_f.FREQ = pstcI2cInit->u32ClockDiv; + pstcI2Cx->CCR_f.SLOWW = (uint32_t)WidthHL/2u; + pstcI2Cx->CCR_f.SHIGHW = (uint32_t)WidthHL - ((uint32_t)WidthHL)/2u; + } + } + } + + if((NULL != pf32Error) && (Ok == enRet)) + { + *pf32Error = fErr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize I2C unit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval Ok Process finished. + ******************************************************************************/ +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Reset peripheral register and internal status*/ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Initialize I2C peripheral according to the structure + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div, + ** from I2C_Clock_Division in i2c driver head file. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRes = Ok; + if((NULL == pstcI2cInit) || (NULL == pstcI2Cx)) + { + enRes = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + + pstcI2Cx->CR1_f.PE = 1u; + + enRes = I2C_BaudrateConfig(pstcI2Cx, pstcI2cInit, pf32Error); + + pstcI2Cx->CR1_f.ENGC = 0u; + pstcI2Cx->CR1_f.SWRST = 0u; + pstcI2Cx->CR1_f.PE = 0u; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief I2C slave address0 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR0_f.SLADDR0EN = enNewState; + pstcI2Cx->SLR0_f.ADDRMOD0 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C slave address1 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR1_f.SLADDR1EN = enNewState; + pstcI2Cx->SLR1_f.ADDRMOD1 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.PE = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C fast ACK function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR3_f.FACKEN = 0ul; + } + else + { + pstcI2Cx->CR3_f.FACKEN = 1ul; + } +} + +/** + ******************************************************************************* + ** \brief I2C bus wait function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR4_f.BUSWAIT = 1ul; + } + else + { + pstcI2Cx->CR4_f.BUSWAIT = 0ul; + } +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2C_SmbusInitStruct + ** Pointer to I2C SMBUS configuration structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct) +{ + en_result_t enRet = Ok; + if(NULL != pstcI2C_SmbusInitStruct) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enHostAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc)); + + pstcI2Cx->CR1_f.SMBHOSTEN = pstcI2C_SmbusInitStruct->enHostAdrMatchFunc; + pstcI2Cx->CR1_f.SMBDEFAULTEN = pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc; + pstcI2Cx->CR1_f.SMBALRTEN = pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SMBUS = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enDigiFilterMode Chose the digital filter mode, This parameter + ** can be one of the following values: + ** Filter1BaseCycle + ** Filter2BaseCycle + ** Filter3BaseCycle + ** Filter4BaseCycle + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_DIGITAL_FILTER(enDigiFilterMode)); + + pstcI2Cx->FLTR_f.DNF = enDigiFilterMode; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.DNFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C analog filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.ANFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C general call function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.ENGC = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C status bit get + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \retval en_flag_status_t The status of the I2C status flag, may be Set or Reset. + ******************************************************************************/ +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + en_flag_status_t enRet = Reset; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_RD_STATUS_BIT(u32StatusBit)); + + if(0ul != (pstcI2Cx->SR & u32StatusBit)) + { + enRet = Set; + } + else + { + enRet = Reset; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2C status flag + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to clear, + ** This parameter can be any combination of the following values: + ** I2C_CLR_STARTFCLR + ** I2C_CLR_SLADDR0FCLR + ** I2C_CLR_SLADDR1FCLR + ** I2C_CLR_TENDFCLR + ** I2C_CLR_STOPFCLR + ** I2C_CLR_RFULLFCLR + ** I2C_CLR_TEMPTYFCLR + ** I2C_CLR_ARLOFCLR + ** I2C_CLR_NACKFCLR + ** I2C_CLR_TMOUTFCLR + ** I2C_CLR_GENCALLFCLR + ** I2C_CLR_SMBDEFAULTFCLR + ** I2C_CLR_SMBHOSTFCLR + ** I2C_CLR_SMBALRTFCLR + ** \retval None + ******************************************************************************/ +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->CLR |= (u32StatusBit & I2C_CLR_MASK); +} + +/** + ******************************************************************************* + ** \brief I2C software reset function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SWRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C interrupt function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32IntEn Specifies the I2C interrupts sources to be configuration + ** This parameter can be any combination of the following values: + ** I2C_CR2_STARTIE + ** I2C_CR2_SLADDR0EN + ** I2C_CR2_SLADDR1EN + ** I2C_CR2_TENDIE + ** I2C_CR2_STOPIE + ** I2C_CR2_RFULLIE + ** I2C_CR2_TEMPTYIE + ** I2C_CR2_ARLOIE + ** I2C_CR2_NACKIE + ** I2C_CR2_TMOURIE + ** I2C_CR2_GENCALLIE + ** I2C_CR2_SMBDEFAULTIE + ** I2C_CR2_SMBHOSTIE + ** I2C_CR2_SMBALRTIE + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR2 |= u32IntEn; + } + else + { + pstcI2Cx->CR2 &= ~u32IntEn; + } +} + +/** + ******************************************************************************* + ** \brief I2C write data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Data The data to be send + ** \retval None + ******************************************************************************/ +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->DTR = u8Data; +} + +/** + ******************************************************************************* + ** \brief I2C read data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval uint8_t The value of the received data + ******************************************************************************/ +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + return pstcI2Cx->DRR; +} + +/** + ******************************************************************************* + ** \brief I2C ACK status configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32AckConfig I2C ACK configurate. + ** I2c_ACK: Send ACK after date received. + ** I2c_NACK: Send NACK after date received. + ** \retval None + ******************************************************************************/ +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_ACK_CONFIG(u32AckConfig)); + + pstcI2Cx->CR1_f.ACK = u32AckConfig; +} + +/** + ******************************************************************************* + ** \brief I2C clock timer out function config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcTimoutInit Pointer to I2C timeout function structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit) +{ + en_result_t enRet = Ok; + if(NULL != pstcTimoutInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_TIMOUT_SWITCH(pstcTimoutInit->enClkTimeOutSwitch)); + + pstcI2Cx->SLTR_f.TOUTHIGH = pstcTimoutInit->u16TimeOutHigh; + pstcI2Cx->SLTR_f.TOUTLOW = pstcTimoutInit->u16TimeOutLow; + + pstcI2Cx->CR3 &= ~0x00000007ul; + pstcI2Cx->CR3 |= pstcTimoutInit->enClkTimeOutSwitch; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx start + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Start success + ** \retval ErrorTimeout Start time out + ******************************************************************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_BUSY, Reset, u32Timeout); + + if(Ok == enRet) + { + /* generate start signal */ + I2C_GenerateStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx restart + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Restart successfully + ** \retval ErrorTimeout Restart time out + ******************************************************************************/ +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + /* Send restart condition */ + I2C_GenerateReStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_7BIT_ADR(u8Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Send I2C address */ + I2C_WriteData(pstcI2Cx, (u8Addr << 1u) | (uint8_t)enDir); + + if(I2CDirTrans == enDir) + { + /* If in master transfer process, Need wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + } + else + { + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + } + + if(enRet == Ok) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Set) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address 10 bit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u16Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_10BIT_ADR(u16Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirTrans); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + /* If receive ACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Reset) + { + /* Write SLA(bit7:0)*/ + I2C_WriteData(pstcI2Cx, (uint8_t)(u16Addr & 0xFFu)); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + else + { + enRet = Error; + } + } + } + + if((I2CDirReceive == enDir) && (Ok == enRet)) + { + /* Restart */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + I2C_GenerateReStart(pstcI2Cx, Enable); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STARTF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirReceive); + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + + if(Ok == enRet) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] au8TxData The data array to be sent + ** \param [in] u32Size Number of data in array pau8TxData + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval ErrorTimeout: Send data time out + ** \retval ErrorInvalidParameter: au8TxData is NULL + ******************************************************************************/ +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + en_result_t enRet = Ok; + __IO uint32_t u32Cnt = 0ul; + + if(au8TxData != NULL) + { + while((u32Cnt != u32Size) && (enRet == Ok)) + { + /* Wait tx buffer empty */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(enRet == Ok) + { + /* Send one byte data */ + I2C_WriteData(pstcI2Cx, au8TxData[u32Cnt]); + + /* Wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + /* If receive NACK in slave tx mode */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_NACKF) == Set) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_NACKFCLR); + /* Exit data transfer */ + break; + } + + u32Cnt++; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx receive data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx master receive data and stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* Stop before read last data */ + if(i == (u32Size - 1ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + I2C_GenerateStop(pstcI2Cx, Enable); + } + + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + + /* Wait stop flag after DRR read */ + if(i == (u32Size - 1ul)) + { + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + } + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ******************************************************************************/ +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear stop flag */ + while((Set == I2C_GetStatus(pstcI2Cx, I2C_SR_STOPF)) && (u32Timeout > 0ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + u32Timeout--; + } + I2C_GenerateStop(pstcI2Cx, Enable); + /* Wait stop flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + + return enRet; +} + +//@} // I2cGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_i2s.c b/lib/hc32f460/driver/src/hc32f460_i2s.c new file mode 100644 index 000000000000..ece22529c6af --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_i2s.c @@ -0,0 +1,433 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.c + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2s.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup I2sGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for I2S register pointer */ +#define IS_VALID_I2S_REG(x) \ +( (M4_I2S1 == (x)) || \ + (M4_I2S2 == (x)) || \ + (M4_I2S3 == (x)) || \ + (M4_I2S4 == (x))) + +/*!< Parameter valid check for I2S function */ +#define IS_VALID_I2S_FUNCTION(x) \ +( (TxEn == (x)) || \ + (TxIntEn == (x)) || \ + (RxEn == (x)) || \ + (RxIntEn == (x)) || \ + (ErrIntEn == (x))) + +/*!< Parameter valid check for I2S status bits */ +#define IS_VALID_I2S_STATUS(x) \ +( (TxBufAlarmFlag == (x)) || \ + (RxBufAlarmFlag == (x)) || \ + (TxBufEmptFlag == (x)) || \ + (TxBufFullFlag == (x)) || \ + (RxBufEmptFlag == (x)) || \ + (RxBufFullFlag == (x))) + +/*!< Parameter valid check for I2S error flag */ +#define IS_VALID_I2S_ERR_FLAG(x) \ +( (ClrTxErrFlag == (x)) || \ + (ClrRxErrFlag == (x))) + +/*!< Parameter valid check for I2S mode */ +#define IS_VALID_I2S_MODE(x) \ +( (I2sMaster == (x)) || \ + (I2sSlave == (x))) + +/*!< Parameter valid check for I2S full duplex mode */ +#define IS_VALID_I2S_DUPLEX_MODE(x) \ +( (I2s_HalfDuplex == (x)) || \ + (I2s_FullDuplex == (x))) + +/*!< Parameter valid check for I2S standard */ +#define IS_VALID_I2S_STANDARD(x) \ +( (Std_Philips == (x)) || \ + (Std_MSBJust == (x)) || \ + (Std_LSBJust == (x)) || \ + (Std_PCM == (x))) + +/*!< Parameter valid check for I2S data length */ +#define IS_VALID_I2S_DATA_LEN(x) \ +( (I2s_DataLen_16Bit == (x)) || \ + (I2s_DataLen_24Bit == (x)) || \ + (I2s_DataLen_32Bit == (x))) + +/*!< Parameter valid check for I2S channel data length */ +#define IS_VALID_I2S_CHANNEL_LEN(x) \ +( (I2s_ChLen_16Bit == (x)) || \ + (I2s_ChLen_32Bit == (x))) + +/*!< Parameter valid check for I2S MCK output config */ +#define IS_VALID_I2S_MCKOUT(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S EXCK config */ +#define IS_VALID_I2S_EXCK(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S audio frequecy */ +#define IS_I2S_AUDIO_FREQ(FREQ) \ +( (((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) + +/*! I2S registers reset value */ +#define I2S_REG_CTRL_RESET_VALUE (0x00002200ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief I2S function command + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enFunc I2S function + ** \arg Refer @ref en_i2s_func_t + ** \param [in] enNewState New status + ** \arg Refer @ref en_functional_state_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_FUNCTION(enFunc)); + + if(Enable == enNewState) + { + if(0ul == (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL |= (1ul << enFunc); + } + } + else + { + if(0ul != (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL &= ~(1ul << (uint8_t)enFunc); + } + } +} + +/** + ******************************************************************************* + ** \brief Get I2S status bit + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enStd I2S status bit + ** \arg Refer @ref en_i2s_std_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd) +{ + en_flag_status_t enRet = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_STATUS(enStd)); + + if (0ul != ((uint32_t)(pstcI2sReg->SR & (1ul << (uint8_t)enStd)))) + { + enRet = Set; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + pstcI2sReg->ER |= (1ul << (uint8_t)enErrFlag); +} + +/** + ******************************************************************************* + ** \brief Get I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, + en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + return (en_flag_status_t)((uint32_t)(pstcI2sReg->ER | (1ul << (uint8_t)enErrFlag))); +} + +/** + ******************************************************************************* + ** \brief Write data to I2s data send register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] u32Data Data to be send + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + pstcI2sReg->TXBUF = u32Data; +} + +/** + ******************************************************************************* + ** \brief Read data from I2s data receive register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** + ** \retval uint32_t The data read out + ** + ******************************************************************************/ +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + return pstcI2sReg->RXBUF; +} + +/** + ******************************************************************************* + ** \brief Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] pstcI2sCfg Pointer to I2S configuration structure + ** + ** \retval Ok Initialize successfully done + ** + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg) +{ + uint32_t i2sclk = 0ul, tmp=0ul; + uint8_t u8ChanelDataBit,u8ChanMul; + uint16_t i2sdiv, i2sodd; + stc_i2s_cfgr_field_t stcCFGR_Tmp = {0}; + stc_i2s_ctrl_field_t stcCTRL_Tmp = {0}; + en_result_t enRes = Ok; + uint32_t u32AdrTmp = 0ul; + + if((NULL == pstcI2sReg)||(NULL == pstcI2sCfg)) + { + enRes = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_MODE(pstcI2sCfg->enMode)); + DDL_ASSERT(IS_VALID_I2S_DUPLEX_MODE(pstcI2sCfg->enFullDuplexMode)); + DDL_ASSERT(IS_VALID_I2S_STANDARD(pstcI2sCfg->enStandrad)); + DDL_ASSERT(IS_VALID_I2S_DATA_LEN(pstcI2sCfg->enDataBits)); + DDL_ASSERT(IS_VALID_I2S_CHANNEL_LEN(pstcI2sCfg->enChanelLen)); + DDL_ASSERT(IS_VALID_I2S_MCKOUT(pstcI2sCfg->enMcoOutEn)); + DDL_ASSERT(IS_VALID_I2S_EXCK(pstcI2sCfg->enExckEn)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sCfg->u32AudioFreq)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1ul; + pstcI2sReg->ER_f.RXERR = 1ul; + + //*(uint32_t*)&stcCTRL_Tmp = pstcI2sReg->CTRL; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + *(uint32_t*)u32AdrTmp = pstcI2sReg->CTRL; + + /* ---- config I2s clock source---- */ + if(Enable == pstcI2sCfg->enExckEn) + { + /* Set external clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 1ul; + stcCTRL_Tmp.I2SPLLSEL = 0ul; + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + } + else + { + /* Set internal clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 0ul; + stcCTRL_Tmp.I2SPLLSEL = 1ul; + /* Get i2s clock internal frequency */ + i2sclk = pstcI2sCfg->u32I2sInterClkFreq; + } + /* config audio sampple rate */ + if(I2s_ChLen_16Bit == pstcI2sCfg->enChanelLen) + { + u8ChanelDataBit = 16u; + u8ChanMul = 8u; + } + else + { + u8ChanelDataBit = 32u; + u8ChanMul = 4u; + } + + /*config I2S clock*/ + if(true == pstcI2sCfg->enMcoOutEn) + { + /* MCLK output is enabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul * u8ChanMul); + } + else + { + /* MCLK output is disabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul); + } + i2sodd = (uint16_t)(tmp & 0x0001ul); + i2sdiv = (uint16_t)((tmp - (uint32_t)i2sodd) / 2ul); + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2u) || (i2sdiv > 0xFFu)) + { + /* Set the default values */ + i2sdiv = 2u; + i2sodd = 0u; + } + + /* Write I2SPR register */ + pstcI2sReg->PR_f.I2SDIV = (uint8_t)i2sdiv; + + /* Config and write I2S_CFGR */ + stcCFGR_Tmp.CHLEN = pstcI2sCfg->enChanelLen; + stcCFGR_Tmp.DATLEN = pstcI2sCfg->enDataBits; + stcCFGR_Tmp.I2SSTD = pstcI2sCfg->enStandrad; + stcCFGR_Tmp.PCMSYNC = PCM_SYNC_FRAME; + pstcI2sReg->CFGR_f = stcCFGR_Tmp; + + /* Config CTRL register */ + stcCTRL_Tmp.WMS = pstcI2sCfg->enMode; + stcCTRL_Tmp.DUPLEX = pstcI2sCfg->enFullDuplexMode; + if(I2sMaster == pstcI2sCfg->enMode) + { + stcCTRL_Tmp.CKOE = 1u; + stcCTRL_Tmp.LRCKOE = 1u; + } + stcCTRL_Tmp.SDOE = 1u; + stcCTRL_Tmp.MCKOE = pstcI2sCfg->enMcoOutEn; + stcCTRL_Tmp.ODD = (uint8_t)i2sodd; + stcCTRL_Tmp.RXBIRQWL = RXBUF_IRQ_WL; + stcCTRL_Tmp.TXBIRQWL = TXBUF_IRQ_WL; + //pstcI2sReg->CTRL = *(uint32_t*)&stcCTRL_Tmp; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + pstcI2sReg->CTRL = *(uint32_t*)u32AdrTmp; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief De-Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1u; + pstcI2sReg->ER_f.RXERR = 1u; + + return Ok; +} + +//@} // I2sGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_icg.c b/lib/hc32f460/driver/src/hc32f460_icg.c new file mode 100644 index 000000000000..fc8bd8ad9ace --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_icg.c @@ -0,0 +1,79 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.c + ** + ** A detailed description is available at + ** @link IcgGroup Initialize Configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_icg.h" + +/** + ******************************************************************************* + ** \addtogroup IcgGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICG[] __attribute__((at(0x400))) = +#elif defined (__ICCARM__) +__root const uint32_t u32ICG[] @ 0x400 = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~ 3 */ + ICG0_REGISTER_CONSTANT, + ICG1_REGISTER_CONSTANT, + ICG2_REGISTER_CONSTANT, + ICG3_REGISTER_CONSTANT, + /* ICG 4~ 7 */ + ICG4_REGISTER_CONSTANT, + ICG5_REGISTER_CONSTANT, + ICG6_REGISTER_CONSTANT, + ICG7_REGISTER_CONSTANT, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +//@} // IcgGroup + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_interrupts.c b/lib/hc32f460/driver/src/hc32f460_interrupts.c new file mode 100644 index 000000000000..fb6174a3c44a --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_interrupts.c @@ -0,0 +1,3779 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/*****************************************************************************/ +/** \file hc32f460_interrupts.c + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_interrupts.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup InterruptGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Max IRQ Handler. */ +#define IRQ_NUM_MAX (128u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +func_ptr_t IrqHandler[IRQ_NUM_MAX] = {NULL}; + +/** + ******************************************************************************* + ** \brief IRQ Registration + ** + ** param [in] pstcIrqRegiConf, IRQ registration + ** configure structure + ** + ** retval Ok, IRQ register successfully. + ** ErrorInvalidParameter, IRQ No. and + ** Vector No. are not match. + ** ErrorUninitialized, Make sure the + ** Interrupt select register (INTSEL) is + ** default value (0x1FFu) before setting. + ** + *****************************************************************************/ +en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf) +{ + // todo, assert ... + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + //DDL_ASSERT(NULL != pstcIrqRegiConf->pfnCallback); + DDL_ASSERT(IS_NULL_POINT(pstcIrqRegiConf->pfnCallback)); + + /* IRQ032~127 whether out of range */ + if (((((pstcIrqRegiConf->enIntSrc/32)*6 + 32) > pstcIrqRegiConf->enIRQn) || \ + (((pstcIrqRegiConf->enIntSrc/32)*6 + 37) < pstcIrqRegiConf->enIRQn)) && \ + (pstcIrqRegiConf->enIRQn >= 32)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + \ + (4u * pstcIrqRegiConf->enIRQn)); + if (0x1FFu == stcIntSel->INTSEL) + { + stcIntSel->INTSEL = pstcIrqRegiConf->enIntSrc; + IrqHandler[pstcIrqRegiConf->enIRQn] = pstcIrqRegiConf->pfnCallback; + } + else + { + enRet = ErrorUninitialized; + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief IRQ Resign + ** + ** param [in] enIRQn, IRQ enumunation (Int000_IRQn ~ + ** Int127_IRQn + ** + ** retval Ok, IRQ resign sucessfully. + ** ErrorInvalidParameter, IRQ No. is out + ** of range + ** + *****************************************************************************/ +en_result_t enIrqResign(IRQn_Type enIRQn) +{ + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + if ((enIRQn < Int000_IRQn) || (enIRQn > Int127_IRQn)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * enIRQn)); + stcIntSel->INTSEL = 0x1FFu; + IrqHandler[enIRQn] = NULL; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler enable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqEnable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx |= (uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler disable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqDisable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx &= ~(uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be enabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000ul)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN |= u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Disable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be disabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000u)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN &= ~u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be enabled + ** + ******************************************************************************/ +en_result_t enEventEnable(uint32_t u32Event) +{ + M4_INTC->EVTER |= u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be disabled + ** + ******************************************************************************/ +en_result_t enEventDisable(uint32_t u32Event) +{ + M4_INTC->EVTER &= ~u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt enable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be enabled + ** + ******************************************************************************/ +en_result_t enIntEnable(uint32_t u32Int) +{ + M4_INTC->IER |= u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt disable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be disabled + ** + ******************************************************************************/ +en_result_t enIntDisable(uint32_t u32Int) +{ + M4_INTC->IER &= ~u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI IRQ handler + ** + ******************************************************************************/ +void NMI_Handler(void) +{ + NMI_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Hard Fault IRQ handler + ** + ******************************************************************************/ +void HardFault_Handler(void) +{ + HardFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief MPU Fault IRQ handler + ** + ******************************************************************************/ +void MemManage_Handler(void) +{ + MemManage_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Bus Fault IRQ handler + ** + ******************************************************************************/ +void BusFault_Handler(void) +{ + BusFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Usage Fault IRQ handler + ** + ******************************************************************************/ +void UsageFault_Handler(void) +{ + UsageFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief SVCall IRQ handler + ** + ******************************************************************************/ +void SVC_Handler(void) +{ + SVC_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief DebugMon IRQ handler + ** + ******************************************************************************/ +void DebugMon_Handler(void) +{ + DebugMon_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief PendSV IRQ handler + ** + ******************************************************************************/ +void PendSV_Handler(void) +{ + PendSV_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Systick IRQ handler + ** + ******************************************************************************/ +void SysTick_Handler(void) +{ + SysTick_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Int No.000 IRQ handler + ** + ******************************************************************************/ +void IRQ000_Handler(void) +{ + if (NULL != IrqHandler[Int000_IRQn]) + { + IrqHandler[Int000_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.001 IRQ handler + ** + ******************************************************************************/ +void IRQ001_Handler(void) +{ + if (NULL != IrqHandler[Int001_IRQn]) + { + IrqHandler[Int001_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.002 IRQ handler + ** + ******************************************************************************/ +void IRQ002_Handler(void) +{ + if (NULL != IrqHandler[Int002_IRQn]) + { + IrqHandler[Int002_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.003 IRQ handler + ** + ******************************************************************************/ +void IRQ003_Handler(void) +{ + if (NULL != IrqHandler[Int003_IRQn]) + { + IrqHandler[Int003_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.004 IRQ handler + ** + ******************************************************************************/ +void IRQ004_Handler(void) +{ + if (NULL != IrqHandler[Int004_IRQn]) + { + IrqHandler[Int004_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.005 IRQ handler + ** + ******************************************************************************/ +void IRQ005_Handler(void) +{ + if (NULL != IrqHandler[Int005_IRQn]) + { + IrqHandler[Int005_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.006 IRQ handler + ** + ******************************************************************************/ +void IRQ006_Handler(void) +{ + if (NULL != IrqHandler[Int006_IRQn]) + { + IrqHandler[Int006_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.007 IRQ handler + ** + ******************************************************************************/ +void IRQ007_Handler(void) +{ + if (NULL != IrqHandler[Int007_IRQn]) + { + IrqHandler[Int007_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.008 IRQ handler + ** + ******************************************************************************/ +void IRQ008_Handler(void) +{ + if (NULL != IrqHandler[Int008_IRQn]) + { + IrqHandler[Int008_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.009 IRQ handler + ** + ******************************************************************************/ +void IRQ009_Handler(void) +{ + if (NULL != IrqHandler[Int009_IRQn]) + { + IrqHandler[Int009_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.010 IRQ handler + ** + ******************************************************************************/ +void IRQ010_Handler(void) +{ + if (NULL != IrqHandler[Int010_IRQn]) + { + IrqHandler[Int010_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.011 IRQ handler + ** + ******************************************************************************/ +void IRQ011_Handler(void) +{ + if (NULL != IrqHandler[Int011_IRQn]) + { + IrqHandler[Int011_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.012 IRQ handler + ** + ******************************************************************************/ +void IRQ012_Handler(void) +{ + if (NULL != IrqHandler[Int012_IRQn]) + { + IrqHandler[Int012_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.013 IRQ handler + ** + ******************************************************************************/ +void IRQ013_Handler(void) +{ + if (NULL != IrqHandler[Int013_IRQn]) + { + IrqHandler[Int013_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.014 IRQ handler + ** + ******************************************************************************/ +void IRQ014_Handler(void) +{ + if (NULL != IrqHandler[Int014_IRQn]) + { + IrqHandler[Int014_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.015 IRQ handler + ** + ******************************************************************************/ +void IRQ015_Handler(void) +{ + if (NULL != IrqHandler[Int015_IRQn]) + { + IrqHandler[Int015_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.016 IRQ handler + ** + ******************************************************************************/ +void IRQ016_Handler(void) +{ + if (NULL != IrqHandler[Int016_IRQn]) + { + IrqHandler[Int016_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.017 IRQ handler + ** + ******************************************************************************/ +void IRQ017_Handler(void) +{ + if (NULL != IrqHandler[Int017_IRQn]) + { + IrqHandler[Int017_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.018 IRQ handler + ** + ******************************************************************************/ +void IRQ018_Handler(void) +{ + if (NULL != IrqHandler[Int018_IRQn]) + { + IrqHandler[Int018_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.019 IRQ handler + ** + ******************************************************************************/ +void IRQ019_Handler(void) +{ + if (NULL != IrqHandler[Int019_IRQn]) + { + IrqHandler[Int019_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.020 IRQ handler + ** + ******************************************************************************/ +void IRQ020_Handler(void) +{ + if (NULL != IrqHandler[Int020_IRQn]) + { + IrqHandler[Int020_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.021 IRQ handler + ** + ******************************************************************************/ +void IRQ021_Handler(void) +{ + if (NULL != IrqHandler[Int021_IRQn]) + { + IrqHandler[Int021_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.022 IRQ handler + ** + ******************************************************************************/ +void IRQ022_Handler(void) +{ + if (NULL != IrqHandler[Int022_IRQn]) + { + IrqHandler[Int022_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.023 IRQ handler + ** + ******************************************************************************/ +void IRQ023_Handler(void) +{ + if (NULL != IrqHandler[Int023_IRQn]) + { + IrqHandler[Int023_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.024 IRQ handler + ** + ******************************************************************************/ +void IRQ024_Handler(void) +{ + if (NULL != IrqHandler[Int024_IRQn]) + { + IrqHandler[Int024_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.025 IRQ handler + ** + ******************************************************************************/ +void IRQ025_Handler(void) +{ + if (NULL != IrqHandler[Int025_IRQn]) + { + IrqHandler[Int025_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.026 IRQ handler + ** + ******************************************************************************/ +void IRQ026_Handler(void) +{ + if (NULL != IrqHandler[Int026_IRQn]) + { + IrqHandler[Int026_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.027 IRQ handler + ** + ******************************************************************************/ +void IRQ027_Handler(void) +{ + if (NULL != IrqHandler[Int027_IRQn]) + { + IrqHandler[Int027_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.028 IRQ handler + ** + ******************************************************************************/ +void IRQ028_Handler(void) +{ + if (NULL != IrqHandler[Int028_IRQn]) + { + IrqHandler[Int028_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.029 IRQ handler + ** + ******************************************************************************/ +void IRQ029_Handler(void) +{ + if (NULL != IrqHandler[Int029_IRQn]) + { + IrqHandler[Int029_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.030 IRQ handler + ** + ******************************************************************************/ +void IRQ030_Handler(void) +{ + if (NULL != IrqHandler[Int030_IRQn]) + { + IrqHandler[Int030_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.031 IRQ handler + ** + ******************************************************************************/ +void IRQ031_Handler(void) +{ + if (NULL != IrqHandler[Int031_IRQn]) + { + IrqHandler[Int031_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.032 IRQ handler + ** + ******************************************************************************/ +void IRQ032_Handler(void) +{ + if (NULL != IrqHandler[Int032_IRQn]) + { + IrqHandler[Int032_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.033 IRQ handler + ** + ******************************************************************************/ +void IRQ033_Handler(void) +{ + if (NULL != IrqHandler[Int033_IRQn]) + { + IrqHandler[Int033_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.034 IRQ handler + ** + ******************************************************************************/ +void IRQ034_Handler(void) +{ + if (NULL != IrqHandler[Int034_IRQn]) + { + IrqHandler[Int034_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.035 IRQ handler + ** + ******************************************************************************/ +void IRQ035_Handler(void) +{ + if (NULL != IrqHandler[Int035_IRQn]) + { + IrqHandler[Int035_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.036 IRQ handler + ** + ******************************************************************************/ +void IRQ036_Handler(void) +{ + if (NULL != IrqHandler[Int036_IRQn]) + { + IrqHandler[Int036_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.037 IRQ handler + ** + ******************************************************************************/ +void IRQ037_Handler(void) +{ + if (NULL != IrqHandler[Int037_IRQn]) + { + IrqHandler[Int037_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.038 IRQ handler + ** + ******************************************************************************/ +void IRQ038_Handler(void) +{ + if (NULL != IrqHandler[Int038_IRQn]) + { + IrqHandler[Int038_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.039 IRQ handler + ** + ******************************************************************************/ +void IRQ039_Handler(void) +{ + if (NULL != IrqHandler[Int039_IRQn]) + { + IrqHandler[Int039_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.040 IRQ handler + ** + ******************************************************************************/ +void IRQ040_Handler(void) +{ + if (NULL != IrqHandler[Int040_IRQn]) + { + IrqHandler[Int040_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.041 IRQ handler + ** + ******************************************************************************/ +void IRQ041_Handler(void) +{ + if (NULL != IrqHandler[Int041_IRQn]) + { + IrqHandler[Int041_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.042 IRQ handler + ** + ******************************************************************************/ +void IRQ042_Handler(void) +{ + if (NULL != IrqHandler[Int042_IRQn]) + { + IrqHandler[Int042_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.043 IRQ handler + ** + ******************************************************************************/ +void IRQ043_Handler(void) +{ + if (NULL != IrqHandler[Int043_IRQn]) + { + IrqHandler[Int043_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.044 IRQ handler + ** + ******************************************************************************/ +void IRQ044_Handler(void) +{ + if (NULL != IrqHandler[Int044_IRQn]) + { + IrqHandler[Int044_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.045 IRQ handler + ** + ******************************************************************************/ +void IRQ045_Handler(void) +{ + if (NULL != IrqHandler[Int045_IRQn]) + { + IrqHandler[Int045_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.046 IRQ handler + ** + ******************************************************************************/ +void IRQ046_Handler(void) +{ + if (NULL != IrqHandler[Int046_IRQn]) + { + IrqHandler[Int046_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.047 IRQ handler + ** + ******************************************************************************/ +void IRQ047_Handler(void) +{ + if (NULL != IrqHandler[Int047_IRQn]) + { + IrqHandler[Int047_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.048 IRQ handler + ** + ******************************************************************************/ +void IRQ048_Handler(void) +{ + if (NULL != IrqHandler[Int048_IRQn]) + { + IrqHandler[Int048_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.049 IRQ handler + ** + ******************************************************************************/ +void IRQ049_Handler(void) +{ + if (NULL != IrqHandler[Int049_IRQn]) + { + IrqHandler[Int049_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.050 IRQ handler + ** + ******************************************************************************/ +void IRQ050_Handler(void) +{ + if (NULL != IrqHandler[Int050_IRQn]) + { + IrqHandler[Int050_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.051 IRQ handler + ** + ******************************************************************************/ +void IRQ051_Handler(void) +{ + if (NULL != IrqHandler[Int051_IRQn]) + { + IrqHandler[Int051_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.052 IRQ handler + ** + ******************************************************************************/ +void IRQ052_Handler(void) +{ + if (NULL != IrqHandler[Int052_IRQn]) + { + IrqHandler[Int052_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.053 IRQ handler + ** + ******************************************************************************/ +void IRQ053_Handler(void) +{ + if (NULL != IrqHandler[Int053_IRQn]) + { + IrqHandler[Int053_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.054 IRQ handler + ** + ******************************************************************************/ +void IRQ054_Handler(void) +{ + if (NULL != IrqHandler[Int054_IRQn]) + { + IrqHandler[Int054_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.055 IRQ handler + ** + ******************************************************************************/ +void IRQ055_Handler(void) +{ + if (NULL != IrqHandler[Int055_IRQn]) + { + IrqHandler[Int055_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.056 IRQ handler + ** + ******************************************************************************/ +void IRQ056_Handler(void) +{ + if (NULL != IrqHandler[Int056_IRQn]) + { + IrqHandler[Int056_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.057 IRQ handler + ** + ******************************************************************************/ +void IRQ057_Handler(void) +{ + if (NULL != IrqHandler[Int057_IRQn]) + { + IrqHandler[Int057_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.058 IRQ handler + ** + ******************************************************************************/ +void IRQ058_Handler(void) +{ + if (NULL != IrqHandler[Int058_IRQn]) + { + IrqHandler[Int058_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.059 IRQ handler + ** + ******************************************************************************/ +void IRQ059_Handler(void) +{ + if (NULL != IrqHandler[Int059_IRQn]) + { + IrqHandler[Int059_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.060 IRQ handler + ** + ******************************************************************************/ +void IRQ060_Handler(void) +{ + if (NULL != IrqHandler[Int060_IRQn]) + { + IrqHandler[Int060_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.061 IRQ handler + ** + ******************************************************************************/ +void IRQ061_Handler(void) +{ + if (NULL != IrqHandler[Int061_IRQn]) + { + IrqHandler[Int061_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.062 IRQ handler + ** + ******************************************************************************/ +void IRQ062_Handler(void) +{ + if (NULL != IrqHandler[Int062_IRQn]) + { + IrqHandler[Int062_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.063 IRQ handler + ** + ******************************************************************************/ +void IRQ063_Handler(void) +{ + if (NULL != IrqHandler[Int063_IRQn]) + { + IrqHandler[Int063_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.064 IRQ handler + ** + ******************************************************************************/ +void IRQ064_Handler(void) +{ + if (NULL != IrqHandler[Int064_IRQn]) + { + IrqHandler[Int064_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.065 IRQ handler + ** + ******************************************************************************/ +void IRQ065_Handler(void) +{ + if (NULL != IrqHandler[Int065_IRQn]) + { + IrqHandler[Int065_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.066 IRQ handler + ** + ******************************************************************************/ +void IRQ066_Handler(void) +{ + if (NULL != IrqHandler[Int066_IRQn]) + { + IrqHandler[Int066_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.067 IRQ handler + ** + ******************************************************************************/ +void IRQ067_Handler(void) +{ + if (NULL != IrqHandler[Int067_IRQn]) + { + IrqHandler[Int067_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.068 IRQ handler + ** + ******************************************************************************/ +void IRQ068_Handler(void) +{ + if (NULL != IrqHandler[Int068_IRQn]) + { + IrqHandler[Int068_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.069 IRQ handler + ** + ******************************************************************************/ +void IRQ069_Handler(void) +{ + if (NULL != IrqHandler[Int069_IRQn]) + { + IrqHandler[Int069_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.070 IRQ handler + ** + ******************************************************************************/ +void IRQ070_Handler(void) +{ + if (NULL != IrqHandler[Int070_IRQn]) + { + IrqHandler[Int070_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.071 IRQ handler + ** + ******************************************************************************/ +void IRQ071_Handler(void) +{ + if (NULL != IrqHandler[Int071_IRQn]) + { + IrqHandler[Int071_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.072 IRQ handler + ** + ******************************************************************************/ +void IRQ072_Handler(void) +{ + if (NULL != IrqHandler[Int072_IRQn]) + { + IrqHandler[Int072_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.073 IRQ handler + ** + ******************************************************************************/ +void IRQ073_Handler(void) +{ + if (NULL != IrqHandler[Int073_IRQn]) + { + IrqHandler[Int073_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.074 IRQ handler + ** + ******************************************************************************/ +void IRQ074_Handler(void) +{ + if (NULL != IrqHandler[Int074_IRQn]) + { + IrqHandler[Int074_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.075 IRQ handler + ** + ******************************************************************************/ +void IRQ075_Handler(void) +{ + if (NULL != IrqHandler[Int075_IRQn]) + { + IrqHandler[Int075_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.076 IRQ handler + ** + ******************************************************************************/ +void IRQ076_Handler(void) +{ + if (NULL != IrqHandler[Int076_IRQn]) + { + IrqHandler[Int076_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.077 IRQ handler + ** + ******************************************************************************/ +void IRQ077_Handler(void) +{ + if (NULL != IrqHandler[Int077_IRQn]) + { + IrqHandler[Int077_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.078 IRQ handler + ** + ******************************************************************************/ +void IRQ078_Handler(void) +{ + if (NULL != IrqHandler[Int078_IRQn]) + { + IrqHandler[Int078_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.079 IRQ handler + ** + ******************************************************************************/ +void IRQ079_Handler(void) +{ + if (NULL != IrqHandler[Int079_IRQn]) + { + IrqHandler[Int079_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.080 IRQ handler + ** + ******************************************************************************/ +void IRQ080_Handler(void) +{ + if (NULL != IrqHandler[Int080_IRQn]) + { + IrqHandler[Int080_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.081 IRQ handler + ** + ******************************************************************************/ +void IRQ081_Handler(void) +{ + if (NULL != IrqHandler[Int081_IRQn]) + { + IrqHandler[Int081_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.082 IRQ handler + ** + ******************************************************************************/ +void IRQ082_Handler(void) +{ + if (NULL != IrqHandler[Int082_IRQn]) + { + IrqHandler[Int082_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.083 IRQ handler + ** + ******************************************************************************/ +void IRQ083_Handler(void) +{ + if (NULL != IrqHandler[Int083_IRQn]) + { + IrqHandler[Int083_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.084 IRQ handler + ** + ******************************************************************************/ +void IRQ084_Handler(void) +{ + if (NULL != IrqHandler[Int084_IRQn]) + { + IrqHandler[Int084_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.085 IRQ handler + ** + ******************************************************************************/ +void IRQ085_Handler(void) +{ + if (NULL != IrqHandler[Int085_IRQn]) + { + IrqHandler[Int085_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.086 IRQ handler + ** + ******************************************************************************/ +void IRQ086_Handler(void) +{ + if (NULL != IrqHandler[Int086_IRQn]) + { + IrqHandler[Int086_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.087 IRQ handler + ** + ******************************************************************************/ +void IRQ087_Handler(void) +{ + if (NULL != IrqHandler[Int087_IRQn]) + { + IrqHandler[Int087_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.088 IRQ handler + ** + ******************************************************************************/ +void IRQ088_Handler(void) +{ + if (NULL != IrqHandler[Int088_IRQn]) + { + IrqHandler[Int088_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.089 IRQ handler + ** + ******************************************************************************/ +void IRQ089_Handler(void) +{ + if (NULL != IrqHandler[Int089_IRQn]) + { + IrqHandler[Int089_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.090 IRQ handler + ** + ******************************************************************************/ +void IRQ090_Handler(void) +{ + if (NULL != IrqHandler[Int090_IRQn]) + { + IrqHandler[Int090_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.091 IRQ handler + ** + ******************************************************************************/ +void IRQ091_Handler(void) +{ + if (NULL != IrqHandler[Int091_IRQn]) + { + IrqHandler[Int091_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.092 IRQ handler + ** + ******************************************************************************/ +void IRQ092_Handler(void) +{ + if (NULL != IrqHandler[Int092_IRQn]) + { + IrqHandler[Int092_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.093 IRQ handler + ** + ******************************************************************************/ +void IRQ093_Handler(void) +{ + if (NULL != IrqHandler[Int093_IRQn]) + { + IrqHandler[Int093_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.094 IRQ handler + ** + ******************************************************************************/ +void IRQ094_Handler(void) +{ + if (NULL != IrqHandler[Int094_IRQn]) + { + IrqHandler[Int094_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.095 IRQ handler + ** + ******************************************************************************/ +void IRQ095_Handler(void) +{ + if (NULL != IrqHandler[Int095_IRQn]) + { + IrqHandler[Int095_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.096 IRQ handler + ** + ******************************************************************************/ +void IRQ096_Handler(void) +{ + if (NULL != IrqHandler[Int096_IRQn]) + { + IrqHandler[Int096_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.097 IRQ handler + ** + ******************************************************************************/ +void IRQ097_Handler(void) +{ + if (NULL != IrqHandler[Int097_IRQn]) + { + IrqHandler[Int097_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.098 IRQ handler + ** + ******************************************************************************/ +void IRQ098_Handler(void) +{ + if (NULL != IrqHandler[Int098_IRQn]) + { + IrqHandler[Int098_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.099 IRQ handler + ** + ******************************************************************************/ +void IRQ099_Handler(void) +{ + if (NULL != IrqHandler[Int099_IRQn]) + { + IrqHandler[Int099_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.100 IRQ handler + ** + ******************************************************************************/ +void IRQ100_Handler(void) +{ + if (NULL != IrqHandler[Int100_IRQn]) + { + IrqHandler[Int100_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.101 IRQ handler + ** + ******************************************************************************/ +void IRQ101_Handler(void) +{ + if (NULL != IrqHandler[Int101_IRQn]) + { + IrqHandler[Int101_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.102 IRQ handler + ** + ******************************************************************************/ +void IRQ102_Handler(void) +{ + if (NULL != IrqHandler[Int102_IRQn]) + { + IrqHandler[Int102_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.103 IRQ handler + ** + ******************************************************************************/ +void IRQ103_Handler(void) +{ + if (NULL != IrqHandler[Int103_IRQn]) + { + IrqHandler[Int103_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.104 IRQ handler + ** + ******************************************************************************/ +void IRQ104_Handler(void) +{ + if (NULL != IrqHandler[Int104_IRQn]) + { + IrqHandler[Int104_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.105 IRQ handler + ** + ******************************************************************************/ +void IRQ105_Handler(void) +{ + if (NULL != IrqHandler[Int105_IRQn]) + { + IrqHandler[Int105_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.106 IRQ handler + ** + ******************************************************************************/ +void IRQ106_Handler(void) +{ + if (NULL != IrqHandler[Int106_IRQn]) + { + IrqHandler[Int106_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.107 IRQ handler + ** + ******************************************************************************/ +void IRQ107_Handler(void) +{ + if (NULL != IrqHandler[Int107_IRQn]) + { + IrqHandler[Int107_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.108 IRQ handler + ** + ******************************************************************************/ +void IRQ108_Handler(void) +{ + if (NULL != IrqHandler[Int108_IRQn]) + { + IrqHandler[Int108_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.109 IRQ handler + ** + ******************************************************************************/ +void IRQ109_Handler(void) +{ + if (NULL != IrqHandler[Int109_IRQn]) + { + IrqHandler[Int109_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.110 IRQ handler + ** + ******************************************************************************/ +void IRQ110_Handler(void) +{ + if (NULL != IrqHandler[Int110_IRQn]) + { + IrqHandler[Int110_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.111 IRQ handler + ** + ******************************************************************************/ +void IRQ111_Handler(void) +{ + if (NULL != IrqHandler[Int111_IRQn]) + { + IrqHandler[Int111_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.112 IRQ handler + ** + ******************************************************************************/ +void IRQ112_Handler(void) +{ + if (NULL != IrqHandler[Int112_IRQn]) + { + IrqHandler[Int112_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.113 IRQ handler + ** + ******************************************************************************/ +void IRQ113_Handler(void) +{ + if (NULL != IrqHandler[Int113_IRQn]) + { + IrqHandler[Int113_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.114 IRQ handler + ** + ******************************************************************************/ +void IRQ114_Handler(void) +{ + if (NULL != IrqHandler[Int114_IRQn]) + { + IrqHandler[Int114_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.115 IRQ handler + ** + ******************************************************************************/ +void IRQ115_Handler(void) +{ + if (NULL != IrqHandler[Int115_IRQn]) + { + IrqHandler[Int115_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.116 IRQ handler + ** + ******************************************************************************/ +void IRQ116_Handler(void) +{ + if (NULL != IrqHandler[Int116_IRQn]) + { + IrqHandler[Int116_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.117 IRQ handler + ** + ******************************************************************************/ +void IRQ117_Handler(void) +{ + if (NULL != IrqHandler[Int117_IRQn]) + { + IrqHandler[Int117_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.118 IRQ handler + ** + ******************************************************************************/ +void IRQ118_Handler(void) +{ + if (NULL != IrqHandler[Int118_IRQn]) + { + IrqHandler[Int118_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.119 IRQ handler + ** + ******************************************************************************/ +void IRQ119_Handler(void) +{ + if (NULL != IrqHandler[Int119_IRQn]) + { + IrqHandler[Int119_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.120 IRQ handler + ** + ******************************************************************************/ +void IRQ120_Handler(void) +{ + if (NULL != IrqHandler[Int120_IRQn]) + { + IrqHandler[Int120_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.121 IRQ handler + ** + ******************************************************************************/ +void IRQ121_Handler(void) +{ + if (NULL != IrqHandler[Int121_IRQn]) + { + IrqHandler[Int121_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.122 IRQ handler + ** + ******************************************************************************/ +void IRQ122_Handler(void) +{ + if (NULL != IrqHandler[Int122_IRQn]) + { + IrqHandler[Int122_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.123 IRQ handler + ** + ******************************************************************************/ +void IRQ123_Handler(void) +{ + if (NULL != IrqHandler[Int123_IRQn]) + { + IrqHandler[Int123_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.124 IRQ handler + ** + ******************************************************************************/ +void IRQ124_Handler(void) +{ + if (NULL != IrqHandler[Int124_IRQn]) + { + IrqHandler[Int124_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.125 IRQ handler + ** + ******************************************************************************/ +void IRQ125_Handler(void) +{ + if (NULL != IrqHandler[Int125_IRQn]) + { + IrqHandler[Int125_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.126 IRQ handler + ** + ******************************************************************************/ +void IRQ126_Handler(void) +{ + if (NULL != IrqHandler[Int126_IRQn]) + { + IrqHandler[Int126_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.127 IRQ handler + ** + ******************************************************************************/ +void IRQ127_Handler(void) +{ + if (NULL != IrqHandler[Int127_IRQn]) + { + IrqHandler[Int127_IRQn](); + } +} + +#if defined(INTERRUPTS_SHARE_ENABLE) +/** + ******************************************************************************* + ** \brief Int No.128 share IRQ handler + ** + ******************************************************************************/ +void IRQ128_Handler(void) +{ + uint32_t VSSEL128 = M4_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1ul == bM4_INTC_EIFR_EIFR0) && (VSSEL128 & BIT_MASK_00)) + { + Extint00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1ul == bM4_INTC_EIFR_EIFR1) && (VSSEL128 & BIT_MASK_01)) + { + Extint01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1ul == bM4_INTC_EIFR_EIFR2) && (VSSEL128 & BIT_MASK_02)) + { + Extint02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1ul == bM4_INTC_EIFR_EIFR3) && (VSSEL128 & BIT_MASK_03)) + { + Extint03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1ul == bM4_INTC_EIFR_EIFR4) && (VSSEL128 & BIT_MASK_04)) + { + Extint04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1ul == bM4_INTC_EIFR_EIFR5) && (VSSEL128 & BIT_MASK_05)) + { + Extint05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1ul == bM4_INTC_EIFR_EIFR6) && (VSSEL128 & BIT_MASK_06)) + { + Extint06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1ul == bM4_INTC_EIFR_EIFR7) && (VSSEL128 & BIT_MASK_07)) + { + Extint07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1ul == bM4_INTC_EIFR_EIFR8) && (VSSEL128 & BIT_MASK_08)) + { + Extint08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1ul == bM4_INTC_EIFR_EIFR9) && (VSSEL128 & BIT_MASK_09)) + { + Extint09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1ul == bM4_INTC_EIFR_EIFR10) && (VSSEL128 & BIT_MASK_10)) + { + Extint10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1ul == bM4_INTC_EIFR_EIFR11) && (VSSEL128 & BIT_MASK_11)) + { + Extint11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1ul == bM4_INTC_EIFR_EIFR12) && (VSSEL128 & BIT_MASK_12)) + { + Extint12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1ul == bM4_INTC_EIFR_EIFR13) && (VSSEL128 & BIT_MASK_13)) + { + Extint13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1ul == bM4_INTC_EIFR_EIFR14) && (VSSEL128 & BIT_MASK_14)) + { + Extint14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1ul == bM4_INTC_EIFR_EIFR15) && (VSSEL128 & BIT_MASK_15)) + { + Extint15_IrqHandler(); + } +} + + +/** + ******************************************************************************* + ** \brief Int No.129 share IRQ handler + ** + ******************************************************************************/ +void IRQ129_Handler(void) +{ + uint32_t VSSEL129 =M4_INTC->VSSEL129; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + + if (1ul == bM4_DMA1_CHCTL0_IE) + { + /* DMA1 ch.0 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_00)) + { + Dma1Tc0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_08)) + { + Dma1Btc0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CHCTL1_IE) + { + /* DMA1 ch.1 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_01)) + { + Dma1Tc1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_09)) + { + Dma1Btc1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CHCTL2_IE) + { + /* DMA1 ch.2 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_02)) + { + Dma1Tc2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_10)) + { + Dma1Btc2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CHCTL3_IE) + { + /* DMA1 ch.3 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_03)) + { + Dma1Tc3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_11)) + { + Dma1Btc3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err3_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CHCTL0_IE) + { + /* DMA2 ch.0 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_04)) + { + Dma2Tc0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_12)) + { + Dma2Btc0_IrqHandler(); + } + } + /* DMA2 Ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CHCTL1_IE) + { + /* DMA2 ch.1 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_05)) + { + Dma2Tc1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_13)) + { + Dma2Btc1_IrqHandler(); + } + } + /* DMA2 Ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CHCTL2_IE) + { + /* DMA2 ch.2 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_06)) + { + Dma2Tc2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_14)) + { + Dma2Btc2_IrqHandler(); + } + } + /* DMA2 Ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CHCTL3_IE) + { + /* DMA2 ch.3 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_07)) + { + Dma2Tc3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_15)) + { + Dma2Btc3_IrqHandler(); + } + } + /* DMA2 Ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err3_IrqHandler(); + } + } + /* EFM program/erase Error */ + if (1ul == bM4_EFM_FITE_PEERRITE) + { + if ((M4_EFM->FSR & 0x0Fu) && (VSSEL129 & BIT_MASK_18)) + { + EfmPgmEraseErr_IrqHandler(); + } + } + /* EFM collision Error */ + if (1ul == bM4_EFM_FITE_COLERRITE) + { + if ((1ul == bM4_EFM_FSR_COLERR) && (VSSEL129 & BIT_MASK_19)) + { + EfmColErr_IrqHandler(); + } + } + /* EFM operate end */ + if (1ul == bM4_EFM_FITE_OPTENDITE) + { + if ((1ul == bM4_EFM_FSR_OPTEND) && (VSSEL129 & BIT_MASK_20)) + { + EfmOpEnd_IrqHandler(); + } + } + /* QSPI interrupt */ + if ((1ul == M4_QSPI->SR_f.RAER) && (VSSEL129 & BIT_MASK_22)) + { + QspiInt_IrqHandler(); + } + /* DCU ch.1 */ + u32Tmp1 = M4_DCU1->INTSEL; + u32Tmp2 = M4_DCU1->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_23)) + { + Dcu1_IrqHandler(); + } + /* DCU ch.2 */ + u32Tmp1 = M4_DCU2->INTSEL; + u32Tmp2 = M4_DCU2->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_24)) + { + Dcu2_IrqHandler(); + } + /* DCU ch.3 */ + u32Tmp1 = M4_DCU3->INTSEL; + u32Tmp2 = M4_DCU3->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_25)) + { + Dcu3_IrqHandler(); + } + /* DCU ch.4 */ + u32Tmp1 = M4_DCU4->INTSEL; + u32Tmp2 = M4_DCU4->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_26)) + { + Dcu4_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.130 share IRQ handler + ** + ******************************************************************************/ +void IRQ130_Handler(void) +{ + uint32_t VSSEL130 = M4_INTC->VSSEL130; + /* Timer0 Ch. 1 A compare match */ + if (1ul == bM4_TMR01_BCONR_INTENA) + { + if ((1ul == bM4_TMR01_STFLR_CMAF) && (VSSEL130 & BIT_MASK_00)) + { + Timer01GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 1 B compare match */ + if (1ul == bM4_TMR01_BCONR_INTENB) + { + if ((1ul == bM4_TMR01_STFLR_CMBF) && (VSSEL130 & BIT_MASK_01)) + { + Timer01GCMB_IrqHandler(); + } + } + /* Timer0 Ch. 2 A compare match */ + if (1ul == bM4_TMR02_BCONR_INTENA) + { + if ((1ul == bM4_TMR02_STFLR_CMAF) && (VSSEL130 & BIT_MASK_02)) + { + Timer02GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 2 B compare match */ + if (1ul == bM4_TMR02_BCONR_INTENB) + { + if ((1ul == bM4_TMR02_STFLR_CMBF) && (VSSEL130 & BIT_MASK_03)) + { + Timer02GCMB_IrqHandler(); + } + } + /* Main-OSC stop */ + if (1ul == bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE) + { + if ((1ul == bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF) && (VSSEL130 & BIT_MASK_21)) + { + MainOscStop_IrqHandler(); + } + } + /* Wakeup timer */ + if ((1ul == bM4_WKTM_CR_WKOVF) && (VSSEL130 & BIT_MASK_22)) + { + WakeupTimer_IrqHandler(); + } + /* SWDT */ + if ((M4_SWDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL130 & BIT_MASK_23)) + { + Swdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.131 share IRQ handler + ** + ******************************************************************************/ +void IRQ131_Handler(void) +{ + uint32_t VSSEL131 = M4_INTC->VSSEL131; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.1 A compare match */ + if (1ul == bM4_TMR61_ICONR_INTENA) + { + if ((1ul == bM4_TMR61_STFLR_CMAF) && (VSSEL131 & BIT_MASK_00)) + { + Timer61GCMA_IrqHandler(); + } + } + /* Timer6 Ch.1 B compare match */ + if (1ul == bM4_TMR61_ICONR_INTENB) + { + if ((1ul == bM4_TMR61_STFLR_CMBF) && (VSSEL131 & BIT_MASK_01)) + { + Timer61GCMB_IrqHandler(); + } + } + /* Timer6 Ch.1 C compare match */ + if (1ul == bM4_TMR61_ICONR_INTENC) + { + if ((1ul == bM4_TMR61_STFLR_CMCF) && (VSSEL131 & BIT_MASK_02)) + { + Timer61GCMC_IrqHandler(); + } + } + /* Timer6 Ch.1 D compare match */ + if (1ul == bM4_TMR61_ICONR_INTEND) + { + if ((1ul == bM4_TMR61_STFLR_CMDF) && (VSSEL131 & BIT_MASK_03)) + { + Timer61GCMD_IrqHandler(); + } + } + /* Timer6 Ch.1 E compare match */ + if (1ul == bM4_TMR61_ICONR_INTENE) + { + if ((1ul == bM4_TMR61_STFLR_CMEF) && (VSSEL131 & BIT_MASK_04)) + { + Timer61GCME_IrqHandler(); + } + } + /* Timer6 Ch.1 F compare match */ + if (1ul == bM4_TMR61_ICONR_INTENF) + { + if ((1ul == bM4_TMR61_STFLR_CMFF) && (VSSEL131 & BIT_MASK_05)) + { + Timer61GCMF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow */ + if (1ul == bM4_TMR61_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR61_STFLR_OVFF) && (VSSEL131 & BIT_MASK_06)) + { + Timer61GOV_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow */ + if (1ul == bM4_TMR61_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR61_STFLR_UDFF) && (VSSEL131 & BIT_MASK_07)) + { + Timer61GUD_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1ul == bM4_TMR61_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR61_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_08)) + { + Timer61GDT_IrqHandler(); + } + } + /* Timer6 Ch.1 A up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_11)) + { + Timer61SCMA_IrqHandler(); + } + /* Timer6 Ch.1 B up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_12)) + { + Timer61SCMB_IrqHandler(); + } + /* Timer6 Ch.2 A compare match */ + if (1ul == bM4_TMR62_ICONR_INTENA) + { + if ((1ul == bM4_TMR62_STFLR_CMAF) && (VSSEL131 & BIT_MASK_16)) + { + Timer62GCMA_IrqHandler(); + } + } + /* Timer6 Ch.2 B compare match */ + if (1ul == bM4_TMR62_ICONR_INTENB) + { + if ((1ul == bM4_TMR62_STFLR_CMBF) && (VSSEL131 & BIT_MASK_17)) + { + Timer62GCMB_IrqHandler(); + } + } + /* Timer6 Ch.2 C compare match */ + if (1ul == bM4_TMR62_ICONR_INTENC) + { + if ((1ul == bM4_TMR62_STFLR_CMCF) && (VSSEL131 & BIT_MASK_18)) + { + Timer62GCMC_IrqHandler(); + } + } + /* Timer6 Ch.2 D compare match */ + if (1ul == bM4_TMR62_ICONR_INTEND) + { + if ((1ul == bM4_TMR62_STFLR_CMDF) && (VSSEL131 & BIT_MASK_19)) + { + Timer62GCMD_IrqHandler(); + } + } + /* Timer6 Ch.2 E compare match */ + if (1ul == bM4_TMR62_ICONR_INTENE) + { + if ((1ul == bM4_TMR62_STFLR_CMEF) && (VSSEL131 & BIT_MASK_20)) + { + Timer62GCME_IrqHandler(); + } + } + /* Timer6 Ch.2 F compare match */ + if (1ul == bM4_TMR62_ICONR_INTENF) + { + if ((1ul == bM4_TMR62_STFLR_CMFF) && (VSSEL131 & BIT_MASK_21)) + { + Timer62GCMF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow */ + if (1ul == bM4_TMR62_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR62_STFLR_OVFF) && (VSSEL131 & BIT_MASK_22)) + { + Timer62GOV_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow */ + if (1ul == bM4_TMR62_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR62_STFLR_UDFF) && (VSSEL131 & BIT_MASK_23)) + { + Timer62GUD_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1ul == bM4_TMR62_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR62_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_24)) + { + Timer62GDT_IrqHandler(); + } + } + /* Timer6 Ch.2 A up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_27)) + { + Timer62SCMA_IrqHandler(); + } + /* Timer6 Ch.2 B up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_28)) + { + Timer62SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.132 share IRQ handler + ** + ******************************************************************************/ +void IRQ132_Handler(void) +{ + uint32_t VSSEL132 = M4_INTC->VSSEL132; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.3 A compare match */ + if (1ul == bM4_TMR63_ICONR_INTENA) + { + if ((1ul == bM4_TMR63_STFLR_CMAF) && (VSSEL132 & BIT_MASK_00)) + { + Timer63GCMA_IrqHandler(); + } + } + /* Timer6 Ch.3 B compare match */ + if (1ul == bM4_TMR63_ICONR_INTENB) + { + if ((1ul == bM4_TMR63_STFLR_CMBF) && (VSSEL132 & BIT_MASK_01)) + { + Timer63GCMB_IrqHandler(); + } + } + /* Timer6 Ch.3 C compare match */ + if (1ul == bM4_TMR63_ICONR_INTENC) + { + if ((1ul == bM4_TMR63_STFLR_CMCF) && (VSSEL132 & BIT_MASK_02)) + { + Timer63GCMC_IrqHandler(); + } + } + /* Timer6 Ch.3 D compare match */ + if (1ul == bM4_TMR63_ICONR_INTEND) + { + if ((1ul == bM4_TMR63_STFLR_CMDF) && (VSSEL132 & BIT_MASK_03)) + { + Timer63GCMD_IrqHandler(); + } + } + /* Timer6 Ch.3 E compare match */ + if (1ul == bM4_TMR63_ICONR_INTENE) + { + if ((1ul == bM4_TMR63_STFLR_CMEF) && (VSSEL132 & BIT_MASK_04)) + { + Timer63GCME_IrqHandler(); + } + } + /* Timer6 Ch.3 F compare match */ + if (1ul == bM4_TMR63_ICONR_INTENF) + { + if ((1ul == bM4_TMR63_STFLR_CMFF) && (VSSEL132 & BIT_MASK_05)) + { + Timer63GCMF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow */ + if (1ul == bM4_TMR63_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR63_STFLR_OVFF) && (VSSEL132 & BIT_MASK_06)) + { + Timer63GOV_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow */ + if (1ul == bM4_TMR63_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR63_STFLR_UDFF) && (VSSEL132 & BIT_MASK_07)) + { + Timer63GUD_IrqHandler(); + } + } + /* Timer6 Ch.3 dead time */ + if (1ul == bM4_TMR63_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR63_STFLR_DTEF)) && (VSSEL132 & BIT_MASK_08)) + { + Timer63GDT_IrqHandler(); + } + } + /* Timer6 Ch.3 A up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_11)) + { + Timer63SCMA_IrqHandler(); + } + /* Timer6 Ch.3 B up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_12)) + { + Timer63SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.136 share IRQ handler + ** + ******************************************************************************/ +void IRQ136_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL136 = M4_INTC->VSSEL136; + + u32Tmp1 = M4_TMRA1->BCSTR; + /* TimerA Ch.1 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_00)) + { + TimerA1OV_IrqHandler(); + } + /* TimerA Ch.1 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_01)) + { + TimerA1UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA1->ICONR; + u32Tmp2 = M4_TMRA1->STFLR; + /* TimerA Ch.1 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_02)) + { + TimerA1CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA2->BCSTR; + /* TimerA Ch.2 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_03)) + { + TimerA2OV_IrqHandler(); + } + /* TimerA Ch.2 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_04)) + { + TimerA2UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA2->ICONR; + u32Tmp2 = M4_TMRA2->STFLR; + /* TimerA Ch.2 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_05)) + { + TimerA2CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA3->BCSTR; + /* TimerA Ch.3 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_06)) + { + TimerA3OV_IrqHandler(); + } + /* TimerA Ch.3 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_07)) + { + TimerA3UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA3->ICONR; + u32Tmp2 = M4_TMRA3->STFLR; + /* TimerA Ch.3 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_08)) + { + TimerA3CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA4->BCSTR; + /* TimerA Ch.4 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_09)) + { + TimerA4OV_IrqHandler(); + } + /* TimerA Ch.4 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_10)) + { + TimerA4UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA4->ICONR; + u32Tmp2 = M4_TMRA4->STFLR; + /* TimerA Ch.4 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_11)) + { + TimerA4CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA5->BCSTR; + /* TimerA Ch.5 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_12)) + { + TimerA5OV_IrqHandler(); + } + /* TimerA Ch.5 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_13)) + { + TimerA5UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA5->ICONR; + u32Tmp2 = M4_TMRA5->STFLR; + /* TimerA Ch.5 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_14)) + { + TimerA5CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA6->BCSTR; + /* TimerA Ch.6 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_16)) + { + TimerA6OV_IrqHandler(); + } + /* TimerA Ch.6 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_17)) + { + TimerA6UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA6->ICONR; + u32Tmp2 = M4_TMRA6->STFLR; + /* TimerA Ch.6 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_18)) + { + TimerA6CMP_IrqHandler(); + } + /* USBFS global interrupt */ + if(1ul == bM4_USBFS_GAHBCFG_GINTMSK) + { + u32Tmp1 = M4_USBFS->GINTMSK & 0xF77CFCFBul; + u32Tmp2 = M4_USBFS->GINTSTS & 0xF77CFCFBul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL136 & BIT_MASK_19)) + { + UsbGlobal_IrqHandler(); + } + } + + u32Tmp1 = M4_USART1->SR; + u32Tmp2 = M4_USART1->CR1; + /* USART Ch.1 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_22)) + { + Usart1RxErr_IrqHandler(); + } + /* USART Ch.1 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_23)) + { + Usart1RxEnd_IrqHandler(); + } + /* USART Ch.1 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_24)) + { + Usart1TxEmpty_IrqHandler(); + } + /* USART Ch.1 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_25)) + { + Usart1TxEnd_IrqHandler(); + } + /* USART Ch.1 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_26)) + { + Usart1RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART2->SR; + u32Tmp2 = M4_USART2->CR1; + /* USART Ch.2 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_27)) + { + Usart2RxErr_IrqHandler(); + } + /* USART Ch.2 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_28)) + { + Usart2RxEnd_IrqHandler(); + } + /* USART Ch.2 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_29)) + { + Usart2TxEmpty_IrqHandler(); + } + /* USART Ch.2 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_30)) + { + Usart2TxEnd_IrqHandler(); + } + /* USART Ch.2 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_31)) + { + Usart2RxTO_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.137 share IRQ handler + ** + ******************************************************************************/ +void IRQ137_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL137 = M4_INTC->VSSEL137; + + u32Tmp1 = M4_USART3->SR; + u32Tmp2 = M4_USART3->CR1; + /* USART Ch.3 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_00)) + { + Usart3RxErr_IrqHandler(); + } + /* USART Ch.3 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_01)) + { + Usart3RxEnd_IrqHandler(); + } + /* USART Ch.3 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_02)) + { + Usart3TxEmpty_IrqHandler(); + } + /* USART Ch.3 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_03)) + { + Usart3TxEnd_IrqHandler(); + } + /* USART Ch.3 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_04)) + { + Usart3RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART4->SR; + u32Tmp2 = M4_USART4->CR1; + /* USART Ch.4 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_05)) + { + Usart4RxErr_IrqHandler(); + } + /* USART Ch.4 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_06)) + { + Usart4RxEnd_IrqHandler(); + } + /* USART Ch.4 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_07)) + { + Usart4TxEmpty_IrqHandler(); + } + /* USART Ch.4 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_08)) + { + Usart4TxEnd_IrqHandler(); + } + /* USART Ch.4 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_09)) + { + Usart4RxTO_IrqHandler(); + } + + u32Tmp1 = M4_SPI1->CR1; + u32Tmp2 = M4_SPI1->SR; + /* SPI Ch.1 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_11)) + { + Spi1RxEnd_IrqHandler(); + } + /* SPI Ch.1 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_12)) + { + Spi1TxEmpty_IrqHandler(); + } + /* SPI Ch.1 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_13)) + { + Spi1Idle_IrqHandler(); + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_14)) + { + Spi1Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI2->CR1; + u32Tmp2 = M4_SPI2->SR; + /* SPI Ch.2 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_16)) + { + Spi2RxEnd_IrqHandler(); + } + /* SPI Ch.2 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_17)) + { + Spi2TxEmpty_IrqHandler(); + } + /* SPI Ch.2 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_18)) + { + Spi2Idle_IrqHandler(); + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_19)) + { + Spi2Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI3->CR1; + u32Tmp2 = M4_SPI3->SR; + /* SPI Ch.3 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_21)) + { + Spi3RxEnd_IrqHandler(); + } + /* SPI Ch.3 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_22)) + { + Spi3TxEmpty_IrqHandler(); + } + /* SPI Ch.3 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_23)) + { + Spi3Idle_IrqHandler(); + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_24)) + { + Spi3Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI4->CR1; + u32Tmp2 = M4_SPI4->SR; + /* SPI Ch.4 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_26)) + { + Spi4RxEnd_IrqHandler(); + } + /* SPI Ch.4 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_27)) + { + Spi4TxEmpty_IrqHandler(); + } + /* SPI Ch.4 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_28)) + { + Spi4Idle_IrqHandler(); + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_29)) + { + Spi4Err_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.138 share IRQ handler + ** + ******************************************************************************/ +void IRQ138_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL138 = M4_INTC->VSSEL138; + + u32Tmp1 = M4_TMR41->OCSRU; + /* Timer4 Ch.1 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.1 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRV; + /* Timer4 Ch.1 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMVH_IrqHandler(); + } + /* Timer4 Ch.1 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRW; + /* Timer4 Ch.1 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMWH_IrqHandler(); + } + /* Timer4 Ch.1 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->CCSR; + /* Timer4 Ch.1 overflow */ + if ((VSSEL138 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer41GOV_IrqHandler(); + } + /* Timer4 Ch.1 underflow */ + if ((VSSEL138 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer41GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->RCSR; + /* Timer4 Ch.1 U phase reload */ + if ((VSSEL138 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.1 V phase reload */ + if ((VSSEL138 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer41ReloadV_IrqHandler(); + } + /* Timer4 Ch.1 W phase reload */ + if ((VSSEL138 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer41ReloadW_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRU; + /* Timer4 Ch.2 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_16) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.2 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_17) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRV; + /* Timer4 Ch.2 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_18) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMVH_IrqHandler(); + } + /* Timer4 Ch.2 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_19) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRW; + /* Timer4 Ch.2 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_20) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMWH_IrqHandler(); + } + /* Timer4 Ch.2 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_21) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->CCSR; + /* Timer4 Ch.2 overflow */ + if ((VSSEL138 & BIT_MASK_22) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer42GOV_IrqHandler(); + } + /* Timer4 Ch.2 underflow */ + if ((VSSEL138 & BIT_MASK_23) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer42GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->RCSR; + /* Timer4 Ch.2 U phase reload */ + if ((VSSEL138 & BIT_MASK_24) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer42ReloadU_IrqHandler(); + } + /* Timer4 Ch.2 V phase reload */ + if ((VSSEL138 & BIT_MASK_25) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer42ReloadV_IrqHandler(); + } + /* Timer4 Ch.2 W phase reload */ + if ((VSSEL138 & BIT_MASK_26) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer42ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.139 share IRQ handler + ** + ******************************************************************************/ +void IRQ139_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL139 = M4_INTC->VSSEL139; + + u32Tmp1 = M4_TMR43->OCSRU; + /* Timer4 Ch.3 U phase higher compare match */ + if ((VSSEL139 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMUH_IrqHandler(); + } + /* Timer4 Ch.3 U phase lower compare match */ + if ((VSSEL139 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRV; + /* Timer4 Ch.3 V phase higher compare match */ + if ((VSSEL139 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMVH_IrqHandler(); + } + /* Timer4 Ch.3 V phase lower compare match */ + if ((VSSEL139 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRW; + /* Timer4 Ch.3 W phase higher compare match */ + if ((VSSEL139 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMWH_IrqHandler(); + } + /* Timer4 Ch.3 W phase lower compare match */ + if ((VSSEL139 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->CCSR; + /* Timer4 Ch.3 overflow */ + if ((VSSEL139 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer43GOV_IrqHandler(); + } + /* Timer4 Ch.3 underflow */ + if ((VSSEL139 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer43GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->RCSR; + /* Timer4 Ch.3 U phase reload */ + if ((VSSEL139 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.3 V phase reload */ + if ((VSSEL139 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer43ReloadV_IrqHandler(); + } + /* Timer4 Ch.3 W phase reload */ + if ((VSSEL139 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer43ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.140 share IRQ handler + ** + ******************************************************************************/ +void IRQ140_Handler(void) +{ + uint32_t VSSEL140 = M4_INTC->VSSEL140; + uint32_t u32Tmp1 = 0u; + uint32_t u32Tmp2 = 0u; + /* EMB1 */ + u32Tmp1 = M4_EMB1->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB1->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_06)) + { + Emb1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = M4_EMB2->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB2->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_07)) + { + Emb2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = M4_EMB3->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB3->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_08)) + { + Emb3_IrqHandler(); + } + /* EMB4*/ + u32Tmp1 = M4_EMB4->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB4->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_09)) + { + Emb4_IrqHandler(); + } + + /* I2S Ch.1 Transmit */ + if(1ul == bM4_I2S1_CTRL_TXIE) + { + if ((1ul == bM4_I2S1_SR_TXBA) && (VSSEL140 & BIT_MASK_16)) + { + I2s1Tx_IrqHandler(); + } + } + /* I2S Ch.1 Receive */ + if(1ul == bM4_I2S1_CTRL_RXIE) + { + if ((1ul == bM4_I2S1_SR_RXBA) && (VSSEL140 & BIT_MASK_17)) + { + I2s1Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if(1ul == bM4_I2S1_CTRL_EIE) + { + if ((M4_I2S1->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_18)) + { + I2s1Err_IrqHandler(); + } + } + /* I2S Ch.2 Transmit */ + if(1ul == bM4_I2S2_CTRL_TXIE) + { + if ((1ul == bM4_I2S2_SR_TXBA) && (VSSEL140 & BIT_MASK_19)) + { + I2s2Tx_IrqHandler(); + } + } + /* I2S Ch.2 Receive */ + if(1ul == bM4_I2S2_CTRL_RXIE) + { + if ((1ul == bM4_I2S2_SR_RXBA) && (VSSEL140 & BIT_MASK_20)) + { + I2s2Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if(1ul == bM4_I2S2_CTRL_EIE) + { + if ((M4_I2S2->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_21)) + { + I2s2Err_IrqHandler(); + } + } + /* I2S Ch.3 Transmit */ + if(1ul == bM4_I2S3_CTRL_TXIE) + { + if ((1ul == bM4_I2S3_SR_TXBA) && (VSSEL140 & BIT_MASK_22)) + { + I2s3Tx_IrqHandler(); + } + } + /* I2S Ch.3 Receive */ + if(1ul == bM4_I2S3_CTRL_RXIE) + { + if ((1ul == bM4_I2S3_SR_RXBA) && (VSSEL140 & BIT_MASK_23)) + { + I2s3Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if(1ul == bM4_I2S3_CTRL_EIE) + { + if ((M4_I2S3->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_24)) + { + I2s3Err_IrqHandler(); + } + } + /* I2S Ch.4 Transmit */ + if(1ul == bM4_I2S4_CTRL_TXIE) + { + if ((1ul == bM4_I2S4_SR_TXBA) && (VSSEL140 & BIT_MASK_25)) + { + I2s4Tx_IrqHandler(); + } + } + /* I2S Ch.4 Receive */ + if(1ul == bM4_I2S4_CTRL_RXIE) + { + if ((1ul == bM4_I2S4_SR_RXBA) && (VSSEL140 & BIT_MASK_26)) + { + I2s4Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if(1ul == bM4_I2S4_CTRL_EIE) + { + if ((M4_I2S4->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_27)) + { + I2s4Err_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.141 share IRQ handler + ** + ******************************************************************************/ +void IRQ141_Handler(void) +{ + uint32_t VSSEL141 = M4_INTC->VSSEL141; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* I2C Ch.1 Receive completed */ + if(1ul == bM4_I2C1_CR2_RFULLIE) + { + if ((1ul == bM4_I2C1_SR_RFULLF) && (VSSEL141 & BIT_MASK_04)) + { + I2c1RxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Transmit data empty */ + if(1ul == bM4_I2C1_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C1_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_05)) + { + I2c1TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Transmit completed */ + if(1ul == bM4_I2C1_CR2_TENDIE) + { + if ((1ul == bM4_I2C1_SR_TENDF) && (VSSEL141 & BIT_MASK_06)) + { + I2c1TxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = M4_I2C1->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C1->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_07)) + { + I2c1Err_IrqHandler(); + } + /* I2C Ch.2 Receive completed */ + if(1ul == bM4_I2C2_CR2_RFULLIE) + { + if ((1ul == bM4_I2C2_SR_RFULLF) && (VSSEL141 & BIT_MASK_08)) + { + I2c2RxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Transmit data empty */ + if(1ul == bM4_I2C2_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C2_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_09)) + { + I2c2TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Transmit completed */ + if(1ul == bM4_I2C2_CR2_TENDIE) + { + if ((1ul == bM4_I2C2_SR_TENDF) && (VSSEL141 & BIT_MASK_10)) + { + I2c2TxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = M4_I2C2->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C2->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_11)) + { + I2c2Err_IrqHandler(); + } + /* I2C Ch.3 Receive completed */ + if(1ul == bM4_I2C3_CR2_RFULLIE) + { + if ((1ul == bM4_I2C3_SR_RFULLF) && (VSSEL141 & BIT_MASK_12)) + { + I2c3RxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Transmit data empty */ + if(1ul == bM4_I2C3_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C3_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_13)) + { + I2c3TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Transmit completed */ + if(1ul == bM4_I2C3_CR2_TENDIE) + { + if ((1ul == bM4_I2C3_SR_TENDF) && (VSSEL141 & BIT_MASK_14)) + { + I2c3TxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = M4_I2C3->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C3->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_15)) + { + I2c3Err_IrqHandler(); + } + /* PVD Ch.1 detected */ + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG) + { + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG) && (VSSEL141 & BIT_MASK_17)) + { + Pvd1_IrqHandler(); + } + } + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG) + { + /* PVD Ch.2 detected */ + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG) && (VSSEL141 & BIT_MASK_18)) + { + Pvd2_IrqHandler(); + } + } + /* Freq. calculate error detected */ + if(1ul == bM4_FCM_RIER_ERRIE) + { + if((1ul == bM4_FCM_SR_ERRF) && (VSSEL141 & BIT_MASK_20)) + { + FcmErr_IrqHandler(); + } + } + /* Freq. calculate completed */ + if(1ul == bM4_FCM_RIER_MENDIE) + { + if((1ul == bM4_FCM_SR_MENDF) && (VSSEL141 & BIT_MASK_21)) + { + FcmEnd_IrqHandler(); + } + } + /* Freq. calculate overflow */ + if(1ul == bM4_FCM_RIER_OVFIE) + { + if((1ul == bM4_FCM_SR_OVF) && (VSSEL141 & BIT_MASK_22)) + { + FcmOV_IrqHandler(); + } + } + + /* WDT */ + if ((M4_WDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL141 & BIT_MASK_23)) + { + Wdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.142 share IRQ handler + ** + ******************************************************************************/ +void IRQ142_Handler(void) +{ + uint32_t u32VSSEL142 = M4_INTC->VSSEL142; + uint16_t u16Tmp = 0u; + /* ADC unit.1 seq. A */ + if (1ul == bM4_ADC1_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_00)) + { + ADC1A_IrqHandler(); + } + } + /* ADC unit.1 seq. B */ + if (1ul == bM4_ADC1_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_01)) + { + ADC1B_IrqHandler(); + } + } + /* ADC unit.1 seq. A */ + u16Tmp = M4_ADC1->AWDSR0; + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_02)) + { + ADC1ChCmp_IrqHandler(); + } + } + /* ADC unit.1 seq. cmp */ + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_03)) + { + ADC1SeqCmp_IrqHandler(); + } + } + + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_04)) + { + ADC2A_IrqHandler(); + } + } + /* ADC unit.2 seq. B */ + if (1ul == bM4_ADC2_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_05)) + { + ADC2B_IrqHandler(); + } + } + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_06)) + { + ADC2ChCmp_IrqHandler(); + } + } + /* ADC unit.2 seq. cmp */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_07)) + { + ADC2SeqCmp_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.143 share IRQ handler + ** + ******************************************************************************/ +void IRQ143_Handler(void) +{ + uint8_t RTIF = 0u; + uint8_t RTIE = 0u; + uint8_t ERRINT = 0u; + uint8_t TTCFG = 0u; + uint16_t NORINTST = 0u; + uint16_t NORINTSGEN = 0u; + uint16_t ERRINTST = 0u; + uint16_t ERRINTSGEN = 0u; + + /* SDIO Ch.1 */ + if (1ul == bM4_INTC_VSSEL143_VSEL2) + { + NORINTST = M4_SDIOC1->NORINTST; + NORINTSGEN = M4_SDIOC1->NORINTSGEN; + ERRINTST = M4_SDIOC1->ERRINTST; + ERRINTSGEN = M4_SDIOC1->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio1_IrqHandler(); + } + } + + /* SDIO Ch.2 */ + if (1ul == bM4_INTC_VSSEL143_VSEL5) + { + NORINTST = M4_SDIOC2->NORINTST; + NORINTSGEN = M4_SDIOC2->NORINTSGEN; + ERRINTST = M4_SDIOC2->ERRINTST; + ERRINTSGEN = M4_SDIOC2->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio2_IrqHandler(); + } + } + + /* CAN */ + if (1ul == bM4_INTC_VSSEL143_VSEL6) + { + RTIF = M4_CAN->RTIF; + RTIE = M4_CAN->RTIE; + ERRINT = M4_CAN->ERRINT; + TTCFG = M4_CAN->TTCFG; + if ( (TTCFG & BIT_MASK_05) || \ + (RTIF & BIT_MASK_00) || \ + (RTIF & RTIE & 0xFEu) || \ + ((ERRINT & BIT_MASK_00) && (ERRINT & BIT_MASK_01)) || \ + ((ERRINT & BIT_MASK_02) && (ERRINT & BIT_MASK_03)) || \ + ((ERRINT & BIT_MASK_04) && (ERRINT & BIT_MASK_05)) || \ + ((TTCFG & BIT_MASK_03) && (TTCFG & BIT_MASK_04)) || \ + ((TTCFG & BIT_MASK_06) && (TTCFG & BIT_MASK_07))) + { + Can_IrqHandler(); + } + } +} + +#endif + +//@} // InterruptGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_keyscan.c b/lib/hc32f460/driver/src/hc32f460_keyscan.c new file mode 100644 index 000000000000..5da482cd2d2e --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_keyscan.c @@ -0,0 +1,203 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.c + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_keyscan.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup KeyscanGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for Hiz cycle */ +#define IS_VALID_HIZ_CLCYE(x) \ +( ((x) == Hiz4) || \ + ((x) == Hiz8) || \ + ((x) == Hiz16) || \ + ((x) == Hiz32) || \ + ((x) == Hiz64) || \ + ((x) == Hiz256) || \ + ((x) == Hiz512) || \ + ((x) == Hiz1K)) + +/*! Parameter validity check for Low cycle */ +#define IS_VALID_LOW_CLCYE(x) \ +( ((x) == Low8) || \ + ((x) == Low16) || \ + ((x) == Low32) || \ + ((x) == Low64) || \ + ((x) == Low128) || \ + ((x) == Low256) || \ + ((x) == Low512) || \ + ((x) == Low1K) || \ + ((x) == Low2K) || \ + ((x) == Low4K) || \ + ((x) == Low8K) || \ + ((x) == Low16K) || \ + ((x) == Low32K) || \ + ((x) == Low64K) || \ + ((x) == Low128K) || \ + ((x) == Low256K) || \ + ((x) == Low512K) || \ + ((x) == Low1M) || \ + ((x) == Low2M) || \ + ((x) == Low4M) || \ + ((x) == Low8M) || \ + ((x) == Low16M)) + +/*! Parameter validity check for scan clock */ +#define IS_VALID_SCAN_CLK(x) \ +( ((x) == KeyscanHclk) || \ + ((x) == KeyscanLrc) || \ + ((x) == KeyscanXtal32)) + +/*! Parameter validity check for keyout selection */ +#define IS_VALID_KEY_OUT(x) \ +( ((x) == Keyout0To1) || \ + ((x) == Keyout0To2) || \ + ((x) == Keyout0To3) || \ + ((x) == Keyout0To4) || \ + ((x) == Keyout0To5) || \ + ((x) == Keyout0To6) || \ + ((x) == Keyout0To7)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief KEYSCAN initialization + ** + ** \param [in] pstcKeyscanConfig KEYSCAN configure structure + ** + ** \retval Ok KEYSCAN initialized + ** ErrorInvalidMode Uninitialized, cannot configure it properly + ** + ******************************************************************************/ +en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_HIZ_CLCYE(pstcKeyscanConfig->enHizCycle)); + DDL_ASSERT(IS_VALID_LOW_CLCYE(pstcKeyscanConfig->enLowCycle)); + DDL_ASSERT(IS_VALID_SCAN_CLK(pstcKeyscanConfig->enKeyscanClk)); + DDL_ASSERT(IS_VALID_KEY_OUT(pstcKeyscanConfig->enKeyoutSel)); + + /* cannot configure keyscan control register when running */ + if (Set == M4_KEYSCAN->SER_f.SEN) + { + enRet = ErrorInvalidMode; + } + else + { + M4_KEYSCAN->SCR_f.T_HIZ = pstcKeyscanConfig->enHizCycle; + M4_KEYSCAN->SCR_f.T_LLEVEL = pstcKeyscanConfig->enLowCycle; + M4_KEYSCAN->SCR_f.CKSEL = pstcKeyscanConfig->enKeyscanClk; + M4_KEYSCAN->SCR_f.KEYOUTSEL = pstcKeyscanConfig->enKeyoutSel; + M4_KEYSCAN->SCR_f.KEYINSEL = pstcKeyscanConfig->u16KeyinSel; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief KEYSCAN de-initialization + ** + ** \param None + ** + ** \retval Ok KEYSCAN de-initialized + ** + ******************************************************************************/ +en_result_t KEYSCAN_DeInit(void) +{ + M4_KEYSCAN->SER = 0ul; + M4_KEYSCAN->SCR = 0ul; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Start keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function started + ** + ******************************************************************************/ +en_result_t KEYSCAN_Start(void) +{ + M4_KEYSCAN->SER_f.SEN = Set; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Stop keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function stopped + ** + ******************************************************************************/ +en_result_t KEYSCAN_Stop(void) +{ + M4_KEYSCAN->SER_f.SEN = Reset; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Key column index + ** + ** \param None + ** + ** \retval uint8_t Index of KEYOUT + ** + ******************************************************************************/ +uint8_t KEYSCAN_GetColIdx(void) +{ + return (uint8_t)(M4_KEYSCAN->SSR_f.INDEX); +} + +//@} // KeyscanGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_mpu.c b/lib/hc32f460/driver/src/hc32f460_mpu.c new file mode 100644 index 000000000000..118b0e95a41b --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_mpu.c @@ -0,0 +1,1053 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.c + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_mpu.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup MpuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for MPU region number. */ +#define IS_VALID_MPU_REGION_NUM(x) \ +( (MpuRegionNum0 == (x)) || \ + (MpuRegionNum1 == (x)) || \ + (MpuRegionNum2 == (x)) || \ + (MpuRegionNum3 == (x)) || \ + (MpuRegionNum4 == (x)) || \ + (MpuRegionNum5 == (x)) || \ + (MpuRegionNum6 == (x)) || \ + (MpuRegionNum7 == (x)) || \ + (MpuRegionNum8 == (x)) || \ + (MpuRegionNum9 == (x)) || \ + (MpuRegionNum10 == (x)) || \ + (MpuRegionNum11 == (x)) || \ + (MpuRegionNum12 == (x)) || \ + (MpuRegionNum13 == (x)) || \ + (MpuRegionNum14 == (x)) || \ + (MpuRegionNum15 == (x))) + +/*!< Parameter valid check for MPU region size. */ +#define IS_VALID_MPU_REGION_SIZE(x) \ +( (MpuRegionSize32Byte == (x)) || \ + (MpuRegionSize64Byte == (x)) || \ + (MpuRegionSize128Byte == (x)) || \ + (MpuRegionSize256Byte == (x)) || \ + (MpuRegionSize512Byte == (x)) || \ + (MpuRegionSize1KByte == (x)) || \ + (MpuRegionSize2KByte == (x)) || \ + (MpuRegionSize4KByte == (x)) || \ + (MpuRegionSize8KByte == (x)) || \ + (MpuRegionSize16KByte == (x)) || \ + (MpuRegionSize32KByte == (x)) || \ + (MpuRegionSize64KByte == (x)) || \ + (MpuRegionSize128KByte == (x)) || \ + (MpuRegionSize256KByte == (x)) || \ + (MpuRegionSize512KByte == (x)) || \ + (MpuRegionSize1MByte == (x)) || \ + (MpuRegionSize2MByte == (x)) || \ + (MpuRegionSize4MByte == (x)) || \ + (MpuRegionSize8MByte == (x)) || \ + (MpuRegionSize16MByte == (x)) || \ + (MpuRegionSize32MByte == (x)) || \ + (MpuRegionSize64MByte == (x)) || \ + (MpuRegionSize128MByte == (x)) || \ + (MpuRegionSize256MByte == (x)) || \ + (MpuRegionSize512MByte == (x)) || \ + (MpuRegionSize1GByte == (x)) || \ + (MpuRegionSize2GByte == (x)) || \ + (MpuRegionSize4GByte == (x))) + +/*!< Parameter valid check for MPU region type. */ +#define IS_VALID_MPU_REGION_TYPE(x) \ +( (SMPU1Region == (x)) || \ + (SMPU2Region == (x)) || \ + (FMPURegion == (x))) + +/*!< Parameter valid check for MPU action. */ +#define IS_VALID_MPU_ACTION(x) \ +( (MpuTrigNmi == (x)) || \ + (MpuTrigReset == (x)) || \ + (MpuNoneAction == (x)) || \ + (MpuTrigBusError == (x))) + +/******************************************************************************/ +/* MPU */ +/******************************************************************************/ +/*!< Get the RGD register address of the specified MPU region */ +#define MPU_RGDx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGD0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< Get the RGCR register address of the specified MPU region */ +#define MPU_RGCRx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGCR0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< MPU RGD register: RGADDR position */ +#define MPU_RGD_RGADDR_Pos (5u) /*!< MPU_RGD: RGADDR Position */ + +/*!< MPU write protection key */ +#define MPU_WRITE_PROT_KEY (0x96A4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Configure MPU protect region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] pstcInitCfg Pointer to MPU protection region configuration structure + ** \arg the structure detail refer @ref stc_mpu_prot_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32WriteProt = M4_MPU->WP; + stc_mpu_rgd_field_t *RGD_f = NULL; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(pstcInitCfg->enRegionSize)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU1Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU2Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcFMPUPermission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enReadEnable)); + + /* Check base address and region size */ + if (!(pstcInitCfg->u32RegionBaseAddress & (~ (0xFFFFFFFFUL << ((uint32_t)pstcInitCfg->enRegionSize + 1UL))))) + { + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Get RGD && RGCR register address */ + RGD_f = (stc_mpu_rgd_field_t *)MPU_RGDx(enRegionNum); + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + /* Disable region protection function */ + RGCR_f->FRG0E = (uint32_t)0ul; + RGCR_f->S1RG0E = (uint32_t)0ul; + RGCR_f->S2RG0E = (uint32_t)0ul; + + /* Set region size */ + RGD_f->MPURGSIZE = (uint32_t)(pstcInitCfg->enRegionSize); + + /* Set region base address */ + RGD_f->MPURGADDR = (pstcInitCfg->u32RegionBaseAddress >> MPU_RGD_RGADDR_Pos); + + /* Set region FMPU */ + RGCR_f->FRG0RP = (pstcInitCfg->stcFMPUPermission.enReadEnable) ? 0ul : 1ul; + RGCR_f->FRG0WP = (pstcInitCfg->stcFMPUPermission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->FRG0E = (uint32_t)(pstcInitCfg->stcFMPUPermission.enRegionEnable); + M4_MPU->CR_f.FMPUACT = (uint32_t)(pstcInitCfg->stcFMPUPermission.enAction); + + /* Set region SMPU1 */ + RGCR_f->S1RG0RP = (pstcInitCfg->stcSMPU1Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S1RG0WP = (pstcInitCfg->stcSMPU1Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S1RG0E = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enRegionEnable); + M4_MPU->CR_f.SMPU1ACT = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enAction); + + /* Set region SMPU2 */ + RGCR_f->S2RG0RP = (pstcInitCfg->stcSMPU2Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S2RG0WP = (pstcInitCfg->stcSMPU2Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S2RG0E = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enRegionEnable); + M4_MPU->CR_f.SMPU2ACT = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enAction); + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure MPU background region. + ** + ** \param [in] pstcInitCfg Pointer to MPU background region configuration structure + ** \arg the structure detail refer @ref stc_mpu_bkgd_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg) +{ + uint32_t u32WriteProt = M4_MPU->WP; + en_result_t enRet = ErrorInvalidParameter; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enReadEnable)); + + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Set SMPU1 */ + M4_MPU->CR_f.SMPU1BWP = (pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU1BRP = (pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set SMPU2 */ + M4_MPU->CR_f.SMPU2BWP = (pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU2BRP = (pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set FMPU */ + M4_MPU->CR_f.FMPUBWP = (pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.FMPUBRP = (pstcInitCfg->stcFMPUBkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enRegionSize MPU region size + ** \arg This parameter can be a value of @ref en_mpu_region_size_t + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize) +{ + stc_mpu_rgd_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(enRegionSize)); + + RGD_f = (stc_mpu_rgd_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURGSIZE = (uint32_t)enRegionSize; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** + ** \retval MPU size of the specified region. + ** + ******************************************************************************/ +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd_field_t *)MPU_RGDx(enRegionNum); + + return (en_mpu_region_size_t)(RGD_f->MPURGSIZE); +} + +/** + ******************************************************************************* + ** \brief Set MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] u32RegionBaseAddr the specified base address + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr) +{ + stc_mpu_rgd_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURGADDR = (u32RegionBaseAddr >> MPU_RGD_RGADDR_Pos); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t +s ** + ** \retval MPU base address of the specified region. + ** + ******************************************************************************/ +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd_field_t *)MPU_RGDx(enRegionNum); + + return (RGD_f->MPURGADDR << MPU_RGD_RGADDR_Pos); +} + +/** + ******************************************************************************* + ** \brief Set the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enActionSel MPU action + ** \arg MpuNoneAction MPU don't action. + ** \arg MpuTrigBusError MPU trigger bus error + ** \arg MpuTrigNmi MPU trigger bus NMI interrupt + ** \arg MpuTrigReset MPU trigger reset + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enActionSel is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_ACTION(enActionSel)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1ACT = (uint32_t)enActionSel; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2ACT = (uint32_t)enActionSel; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUACT = (uint32_t)enActionSel; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval MpuNoneAction MPU don't action. + ** \retval MpuTrigBusError MPU trigger bus error + ** \retval MpuTrigNmi MPU trigger bus NMI interrupt + ** \retval MpuTrigReset MPU trigger reset + ** + ******************************************************************************/ +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32ActionSel = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32ActionSel = M4_MPU->CR_f.SMPU1ACT; + break; + case SMPU2Region: + u32ActionSel = M4_MPU->CR_f.SMPU2ACT; + break; + case FMPURegion: + u32ActionSel = M4_MPU->CR_f.FMPUACT; + break; + default: + break; + } + + return (en_mpu_action_sel_t)(u32ActionSel); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region function + ** \arg Disable Disable the specified MPU region function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0E = (uint32_t)enState; + break; + case SMPU2Region: + RGCR_f->S2RG0E = (uint32_t)enState; + break; + case FMPURegion: + RGCR_f->FRG0E = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified type region function of MPU + ** \arg Disable Disable the specified type region function of MPU + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1E = (uint32_t)enState; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2E = (uint32_t)enState; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUE = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU status + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enMpuRegionType is invalid. + ** + ******************************************************************************/ +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32Flag = 0ul; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32Flag = M4_MPU->SR_f.SMPU1EAF; + break; + case SMPU2Region: + u32Flag = M4_MPU->SR_f.SMPU2EAF; + break; + case FMPURegion: + u32Flag = M4_MPU->SR_f.FMPUEAF; + break; + default: + break; + } + + return (en_flag_status_t)(u32Flag); +} + +/** + ******************************************************************************* + ** \brief Clear MPU status. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->ECLR_f.SMPU1ECLR = 1u; + break; + case SMPU2Region: + M4_MPU->ECLR_f.SMPU2ECLR = 1u; + break; + case FMPURegion: + M4_MPU->ECLR_f.FMPUECLR = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case SMPU2Region: + RGCR_f->S2RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case FMPURegion: + RGCR_f->FRG0RP = (Enable == enState) ? 0ul : 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0RP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0RP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0RP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + RGCR_f->S2RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + RGCR_f->FRG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0WP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0WP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0WP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBRP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BRP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BRP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBRP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBWP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BWP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BWP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBWP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enState MPU write protection state + ** \arg Enable Enable the write protection function + ** \arg Disable Disable the write protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_WriteProtCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_MPU->WP = (MPU_WRITE_PROT_KEY | ((Enable == enState) ? 0ul : 1ul)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable the specified IP Write/Read protection. + ** + ** \param [in] u32ProtMode Ip protection mode + ** \arg AesReadProt AES read protection + ** \arg AesWriteProt AES write protection + ** \arg HashReadProt HASH read protection + ** \arg HashWriteProt HASH write protection + ** \arg TrngReadProt TRNG read protection + ** \arg TrngWriteProt TRNG write protection + ** \arg CrcReadProt CRC read protection + ** \arg CrcWriteProt CRC write protection + ** \arg FmcReadProt FMC read protection + ** \arg FmcWriteProt FMC write protection + ** \arg WdtReadProt WDT read protection + ** \arg WdtWriteProt WDT write protection + ** \arg SwdtReadProt WDT read protection + ** \arg SwdtWriteProt WDT write protection + ** \arg BksramReadProt BKSRAM read protection + ** \arg BksramWriteProt BKSRAM write protection + ** \arg RtcReadProt RTC read protection + ** \arg RtcWriteProt RTC write protection + ** \arg DmpuReadProt DMPU read protection + ** \arg DmpuWriteProt DMPU write protection + ** \arg SramcReadProt SRAMC read protection + ** \arg SramcWriteProt SRAMC write protection + ** \arg IntcReadProt INTC read protection + ** \arg IntcWriteProt INTC write protection + ** \arg SyscReadProt SYSC read protection + ** \arg SyscWriteProt SYSC write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg BusErrProt BUSERR write protection + ** \param [in] enState MPU IP protection state + ** \arg Enable Enable the IP protection function + ** \arg Disable Disable the IP protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if(Enable == enState) + { + M4_SYSREG->MPU_IPPR |= u32ProtMode; + } + else + { + M4_SYSREG->MPU_IPPR &= (~u32ProtMode); + } + + return Ok; +} + +//@} // MpuGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_ots.c b/lib/hc32f460/driver/src/hc32f460_ots.c new file mode 100644 index 000000000000..569cdb94c3ce --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_ots.c @@ -0,0 +1,382 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.c + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_ots.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup OtsGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for OTS auto off configuration value. */ +#define IS_OTS_AUTO_OFF(EN) \ +( ((EN) == OtsAutoOff_Disable) || \ + ((EN) == OtsAutoOff_Enable)) + +/*! Parameter validity check for OTS interrupt enable/disable. */ +#define IS_OTS_IE(IE) \ +( ((IE) == OtsInt_Disable) || \ + ((IE) == OtsInt_Enable)) + +/*! Parameter validity check for OTS clock selection configuration value. */ +#define IS_OTS_CLK_SEL(CLK) \ +( ((CLK) == OtsClkSel_Xtal) || \ + ((CLK) == OtsClkSel_Hrc)) + +/*! Parameter validity check for OTS trigger source event . */ +#define IS_OTS_TRIG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter validity check for OTS common trigger. */ +#define IS_OTS_COM_TRIGGER(x) \ +( ((x) == OtsComTrigger_1) || \ + ((x) == OtsComTrigger_2) || \ + ((x) == OtsComTrigger_1_2)) + +#define EXPERIMENT_COUNT ((uint8_t)10) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static float32_t m_f32SlopeK = 0.0f; +static float32_t m_f32OffsetM = 0.0f; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief Initializes the OTS. + ** + ** \param [in] pstcInit See @ref stc_ots_init_t for details. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Init(const stc_ots_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + DDL_ASSERT(IS_OTS_AUTO_OFF(pstcInit->enAutoOff)); + DDL_ASSERT(IS_OTS_CLK_SEL(pstcInit->enClkSel)); + + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + /* Disable OTS interrupt default. */ + bM4_OTS_CTL_OTSIE = OtsInt_Disable; + + bM4_OTS_CTL_TSSTP = pstcInit->enAutoOff; + bM4_OTS_CTL_OTSCK = pstcInit->enClkSel; + m_f32SlopeK = pstcInit->f32SlopeK; + m_f32OffsetM = pstcInit->f32OffsetM; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_DeInit(void) +{ + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + + /* Set the value of all registers to the reset value. */ + M4_OTS->CTL = 0u; + M4_OTS->DR1 = 0u; + M4_OTS->DR2 = 0u; + M4_OTS->ECR = 0u; +} + +/** + ******************************************************************************* + ** \brief Get temperature via normal mode. + ** + ** \param [out] pf32Temp The address to store the temperature value. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout OTS works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pf32Temp != NULL) + { + enRet = ErrorTimeout; + + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + *pf32Temp = OTS_CalculateTemp(); + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable OTS interrupt. + ** + ** \param [in] enState Enable or disable OTS interrupt. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_IntCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + bM4_OTS_CTL_OTSIE = (uint32_t)enState; +} + +/** + ******************************************************************************* + ** \brief Set OTS AOS trigger source. + ** + ** \param [in] enEvent See @ref en_event_src_t for details. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_SetTriggerSrc(en_event_src_t enEvent) +{ + uint32_t u32OtrTrg = M4_AOS->OTS_TRG; + + DDL_ASSERT(IS_OTS_TRIG_SRC_EVENT(enEvent) && (EVT_OTS != enEvent)); + + u32OtrTrg &= ~0x1FFul; + u32OtrTrg |= enEvent; + + M4_AOS->OTS_TRG = u32OtrTrg; +} + +/** + ******************************************************************************* + ** \brief Enable or disable OTS common trigger. + ** + ** \param [in] enComTrigger OTS common trigger selection. See @ref en_ots_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + + DDL_ASSERT(IS_OTS_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u32ComTrig <<= 30u; + + if (enState == Enable) + { + M4_AOS->OTS_TRG |= u32ComTrig; + } + else + { + M4_AOS->OTS_TRG &= ~u32ComTrig; + } +} + +/** +******************************************************************************* +** \brief OTS scaling experiment. If you want to get a more accurate temperature value, +** you need to do a calibration experiment. +** +** \param [out] pu16Dr1 Address to store OTS data register 1. +** +** \param [out] pu16Dr2 Address to store OTS data register 2. +** +** \param [out] pu16Ecr Address to store OTS error compensation register. +** +** \param [out] pf32A Address to store parameter A(for calibration experiments). +** +** \param [in] u32Timeout Timeout value. +** +** \retval Ok No error occurred. +** \retval ErrorTimeout OTS works timeout. +** \retval ErrorInvalidParameter Parameter error. +******************************************************************************/ +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) + { + enRet = ErrorTimeout; + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + + if (enRet == Ok) + { + *pu16Dr1 = M4_OTS->DR1; + *pu16Dr2 = M4_OTS->DR2; + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Hrc) + { + *pu16Ecr = M4_OTS->ECR; + f32Ecr = (float32_t)(*pu16Ecr); + } + else + { + *pu16Ecr = 1U; + f32Ecr = 1.0f; + } + + if ((f32Dr1 != 0.f) && (f32Dr2 != 0.f) && (f32Ecr != 0.f)) + { + *pf32A = ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr; + } + } + } + + return enRet; +} + + +/** +******************************************************************************* +** \brief Calculate the value of temperature. +** +** \retval A float32_t type value of temperature value. +******************************************************************************/ +float OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0f; + uint16_t u16Dr1 = M4_OTS->DR1; + uint16_t u16Dr2 = M4_OTS->DR2; + uint16_t u16Ecr = M4_OTS->ECR; + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Xtal) + { + f32Ecr = 1.0f; + } + + if ((f32Dr1 != 0.f) && (f32Dr2 != 0.f) && (f32Ecr != 0.f)) + { + f32Ret = m_f32SlopeK * ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +//@} // OtsGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_pwc.c b/lib/hc32f460/driver/src/hc32f460_pwc.c new file mode 100644 index 000000000000..d57c534183dd --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_pwc.c @@ -0,0 +1,2021 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.c + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_pwc.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup PwcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa503u) +#define DISABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~3u)))) + +#define ENABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + +#define ENABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa508u) +#define DISABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~8u)))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP_EVENT(evt) ((0x00u) != ((evt) & (0xFF))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP2_EVENT(evt) ((0x00u) != ((evt) & (0xB7))) + +#define IS_PWC_WKUP_EDGE_EVENT(evt) ((0x00u) != ((evt) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP0_FLAG(flag) ((0x00u) != ((flag) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP1_FLAG(flag) ((0x07u) != ((flag) & (0xB8))) + +/*! Parameter validity check for power down mode. */ +#define IS_PWC_PWR_DOWN_MODE(md) \ +( ((md) == PowerDownMd1) || \ + ((md) == PowerDownMd2) || \ + ((md) == PowerDownMd3) || \ + ((md) == PowerDownMd4)) + +/*! Parameter validity check for power down wake_up time control. */ +#define IS_PWC_PWR_DOWN_WKUP_TIM(x) \ +( ((x) == Vcap01) || \ + ((x) == Vcap0047)) + +/*! Parameter validity check for IO retain state while power down. */ +#define IS_PWC_PWR_DWON_IO_STATE(x) \ +( ((x) == IoPwrDownRetain) || \ + ((x) == IoPwrRstRetain) || \ + ((x) == IoHighImp)) + +/*! Parameter validity check for driver ability while enter stop mode. */ +#define IS_PWC_STP_DRIVER_ABILITY(x) \ +( ((x) == StopHighspeed) || \ + ((x) == StopUlowspeed)) + +/*! Parameter validity check for driver ability. */ +#define IS_PWC_DRIVER_ABILITY(x) \ +( ((x) == Ulowspeed) || \ + ((x) == HighSpeed)) + +/*! Parameter validity check for dynamic voltage. */ +#define IS_PWC_DYNAMIC_VOLTAGE(val) \ +( ((val) == RunUHighspeed) || \ + ((val) == RunUlowspeed) || \ + ((val) == RunHighspeed)) + +/*! Parameter validity check for wake_up edge. */ +#define IS_PWC_EDGE_SEL(edg) \ +( ((edg) == EdgeFalling) || \ + ((edg) == EdgeRising)) + +/*! Parameter validity check for peripheral in fcg0. */ +#define IS_PWC_FCG0_PERIPH(per) \ +( (((per) & (0x700C3AEEu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg1. */ +#define IS_PWC_FCG1_PERIPH(per) \ +( (((per) & (0xF0F00286u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg2. */ +#define IS_PWC_FCG2_PERIPH(per) \ +( (((per) & (0xFFF87800u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg3. */ +#define IS_PWC_FCG3_PERIPH(per) \ +( (((per) & (0xFFFFEEECu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for clock value while stop mode mode. */ +#define IS_PWC_STOP_MODE_CLK(clk) \ +( ((clk) == ClkFix) || \ + ((clk) == ClkMrc)) + +/*! Parameter validity check for flash mode while stop mode mode. */ +#define IS_PWC_STOP_MODE_FLASH(x) \ +( ((x) == Wait) || \ + ((x) == NotWait)) + +/*! Parameter validity check for wake_up timer over flag. */ +#define IS_PWC_WKTMOVER_FLAG(flag) \ +( ((flag) == UnEqual) || \ + ((flag) == Equal)) + +/*! Parameter validity check for ram operate mode. */ +#define IS_PWC_RAM_OP_MD(x) \ +( ((x) == HighSpeedMd) || \ + ((x) == UlowSpeedMd)) + +/*! Parameter validity check for wake_up timer clock. */ +#define IS_PWC_WKTM_CLK(clk) \ +( ((clk) == Wk64hz) || \ + ((clk) == WkXtal32) || \ + ((clk) == WkLrc)) + + +/*! Parameter validity check for handle of pvd. */ +#define IS_PWC_PVD_MD(x) \ +( ((x) == PvdInt) || \ + ((x) == PvdReset)) + + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD_FILTER_CLK(clk) \ +( ((clk) == PvdLrc025) || \ + ((clk) == PvdLrc05) || \ + ((clk) == PvdLrc1) || \ + ((clk) == PvdLrc2)) + +/*! Parameter validity check for pvd2 level. */ +#define IS_PWC_PVD2_LEVEL(lvl) \ +( ((lvl) == Pvd2Level0) || \ + ((lvl) == Pvd2Level1) || \ + ((lvl) == Pvd2Level2) || \ + ((lvl) == Pvd2Level3) || \ + ((lvl) == Pvd2Level4) || \ + ((lvl) == Pvd2Level5) || \ + ((lvl) == Pvd2Level6) || \ + ((lvl) == Pvd2Level7)) + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD1_LEVEL(lvl) \ +( ((lvl) == Pvd1Level0) || \ + ((lvl) == Pvd1Level1) || \ + ((lvl) == Pvd1Level2) || \ + ((lvl) == Pvd1Level3) || \ + ((lvl) == Pvd1Level4) || \ + ((lvl) == Pvd1Level5) || \ + ((lvl) == Pvd1Level6) || \ + ((lvl) == Pvd1Level7)) + +/*! Parameter validity check for pvd interrupt. */ +#define IS_PWC_PVD_INT_SEL(x) \ +( ((x) == NonMskInt) || \ + ((x) == MskInt)) + +/*! Parameter validity check for valid wakeup source from stop mode. */ +#define IS_VALID_WKUP_SRC(x) \ +( ((x) == INT_USART1_WUPI) || \ + ((x) == INT_TMR01_GCMA) || \ + ((x) == INT_RTC_ALM) || \ + ((x) == INT_RTC_PRD) || \ + ((x) == INT_WKTM_PRD) || \ + ((x) == INT_ACMP1) || \ + ((x) == INT_PVD_PVD1) || \ + ((x) == INT_PVD_PVD2) || \ + ((x) == INT_SWDT_REFUDF) || \ + ((x) == INT_PORT_EIRQ0) || \ + ((x) == INT_PORT_EIRQ1) || \ + ((x) == INT_PORT_EIRQ2) || \ + ((x) == INT_PORT_EIRQ3) || \ + ((x) == INT_PORT_EIRQ4) || \ + ((x) == INT_PORT_EIRQ5) || \ + ((x) == INT_PORT_EIRQ6) || \ + ((x) == INT_PORT_EIRQ7) || \ + ((x) == INT_PORT_EIRQ8) || \ + ((x) == INT_PORT_EIRQ9) || \ + ((x) == INT_PORT_EIRQ10) || \ + ((x) == INT_PORT_EIRQ11) || \ + ((x) == INT_PORT_EIRQ12) || \ + ((x) == INT_PORT_EIRQ13) || \ + ((x) == INT_PORT_EIRQ14) || \ + ((x) == INT_PORT_EIRQ15)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t NVIC_ISER_BAK[5]; +uint8_t u8HrcState = 0u; +uint8_t u8MrcState = 0u; +uint8_t u8WkupIntCnt = 0u; +uint8_t u8StopFlag = 0u; +uint8_t u8SysClkSrc = 1u; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ** \param [in] pstcPwrMdCfg The power mode configuration. + ** \arg enPwrDownMd The power down mode. + ** \arg enRLdo Enable or disable RLDO. + ** \arg enRetSram Enable or disable RetSram. + ** \arg enIoRetain The IO state while power down. + ** \arg enPwrDWkupTm The wake_up timer while power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg) +{ + DDL_ASSERT(IS_PWC_PWR_DOWN_MODE(pstcPwrMdCfg->enPwrDownMd )); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRLdo)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRetSram)); + DDL_ASSERT(IS_PWC_PWR_DWON_IO_STATE(pstcPwrMdCfg->enIoRetain)); + DDL_ASSERT(IS_PWC_PWR_DOWN_WKUP_TIM(pstcPwrMdCfg->enPwrDWkupTm)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC0 = (pstcPwrMdCfg->enPwrDownMd | + (uint8_t)(((Enable == pstcPwrMdCfg->enRLdo) ? 0u : 1u) << 2u) | + (uint8_t)(((Enable == pstcPwrMdCfg->enRetSram) ? 0u : 1u) << 3u) | + (pstcPwrMdCfg->enIoRetain << 4u)); + + M4_SYSREG->PWR_PWRC3 = (pstcPwrMdCfg->enPwrDWkupTm | (0x03)) << 2u; + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enter power down mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be put ram + ** + ******************************************************************************/ +__RAM_FUNC void PWC_EnterPowerDownMd(void) +{ + ENABLE_PVD_REG_WRITE(); + + /* Reset PVD1IRS & PVD2IRS */ + M4_SYSREG->PWR_PVDCR1 &= 0xddu; + + DISABLE_PVD_REG_WRITE(); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + + __disable_irq(); + M4_SYSREG->PWR_PWRC0_f.PWDN = 1u; + for(uint8_t i = 0u; i < 10u; i++) + { + __NOP(); + } + __enable_irq(); + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN0_WKUP00 Wake_up 0_0 event + ** \arg PWC_PDWKEN0_WKUP01 Wake_up 0_1 event + ** \arg PWC_PDWKEN0_WKUP02 Wake_up 0_2 event + ** \arg PWC_PDWKEN0_WKUP03 Wake_up 0_3 event + ** \arg PWC_PDWKEN0_WKUP10 Wake_up 1_0 event + ** \arg PWC_PDWKEN0_WKUP11 Wake_up 1_1 event + ** \arg PWC_PDWKEN0_WKUP12 Wake_up 1_2 event + ** \arg PWC_PDWKEN0_WKUP13 Wake_up 1_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup0Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE0 |= (uint8_t)u32Wkup0Event; + } + else + { + M4_SYSREG->PWR_PDWKE0 &= (uint8_t)(~u32Wkup0Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup1Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN1_WKUP20 Wake_up 2_0 event + ** \arg PWC_PDWKEN1_WKUP21 Wake_up 2_1 event + ** \arg PWC_PDWKEN1_WKUP22 Wake_up 2_2 event + ** \arg PWC_PDWKEN1_WKUP23 Wake_up 2_3 event + ** \arg PWC_PDWKEN1_WKUP30 Wake_up 3_0 event + ** \arg PWC_PDWKEN1_WKUP31 Wake_up 3_1 event + ** \arg PWC_PDWKEN1_WKUP32 Wake_up 3_2 event + ** \arg PWC_PDWKEN1_WKUP33 Wake_up 3_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup1Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE1 |= (uint8_t)u32Wkup1Event; + } + else + { + M4_SYSREG->PWR_PDWKE1 &= (uint8_t)(~u32Wkup1Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup2Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN2_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKEN2_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKEN2_NMI Wake_up NMI event + ** \arg PWC_PDWKEN2_RTCPRD Wake_up RTCPRD event + ** \arg PWC_PDWKEN2_RTCAL Wake_up RTCAL event + ** \arg PWC_PDWKEN2_WKTM Wake_up WKTM event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP2_EVENT(u32Wkup2Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE2 |= (uint8_t)u32Wkup2Event; + } + else + { + M4_SYSREG->PWR_PDWKE2 &= (uint8_t)(~u32Wkup2Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configure the power down wake up event edge. + ** + ** \param [in] u8WkupEvent The wake_up event in PDWKEN0. + ** \arg PWC_PDWKUP_EDGE_WKP0 Wake_up WKP0 event + ** \arg PWC_PDWKUP_EDGE_WKP1 Wake_up WKP1 event + ** \arg PWC_PDWKUP_EDGE_WKP2 Wake_up WKP2 event + ** \arg PWC_PDWKUP_EDGE_WKP3 Wake_up WKP3 event + ** \arg PWC_PDWKUP_EDGE_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKUP_EDGE_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKUP_EDGE_NMI Wake_up NMI event + ** + ** \param [in] enEdge The wake_up event edge select. + ** \arg EdgeRising Wake_up event edge rising. + ** \arg EdgeFalling Wake_up event edge falling. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge) +{ + DDL_ASSERT(IS_PWC_WKUP_EDGE_EVENT(u8WkupEvent)); + DDL_ASSERT(IS_PWC_EDGE_SEL(enEdge)); + + ENABLE_PWR_REG_WRITE(); + + if(EdgeRising == enEdge) + { + M4_SYSREG->PWR_PDWKES |= (uint8_t)u8WkupEvent; + } + else + { + M4_SYSREG->PWR_PDWKES &= (uint8_t)(~u8WkupEvent); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF0 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF1 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF0 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF1 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable power monitor . + ** + ** \param [in] enNewState The power monitor state. + ** \arg Enable Enable power monitor. + ** \arg Disable Disable power monitor. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PwrMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWCMR_f.ADBUFE = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG0 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg0Periph The peripheral in FCG0. + ** \arg PWC_FCG0_PERIPH_SRAMH RAMHS clock + ** \arg PWC_FCG0_PERIPH_SRAM12 RAM0 clock + ** \arg PWC_FCG0_PERIPH_SRAM3 ECCRAM clock + ** \arg PWC_FCG0_PERIPH_SRAMRET RetRAM clock + ** \arg PWC_FCG0_PERIPH_DMA1 DMA1 clock + ** \arg PWC_FCG0_PERIPH_DMA2 DMA2 clock + ** \arg PWC_FCG0_PERIPH_FCM FCM clock + ** \arg PWC_FCG0_PERIPH_AOS PTDIS clock + ** \arg PWC_FCG0_PERIPH_AES AES clock + ** \arg PWC_FCG0_PERIPH_HASH HASH clock + ** \arg PWC_FCG0_PERIPH_TRNG TRNG clock + ** \arg PWC_FCG0_PERIPH_CRC CRC clock + ** \arg PWC_FCG0_PERIPH_DCU1 DCU1 clock + ** \arg PWC_FCG0_PERIPH_DCU2 DCU2 clock + ** \arg PWC_FCG0_PERIPH_DCU3 DCU3 clock + ** \arg PWC_FCG0_PERIPH_DCU4 DCU4 clock + ** \arg PWC_FCG0_PERIPH_KEY KEY clock + + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_FCG0_REG_WRITE(); + + if(Enable == enNewState) + { + M4_MSTP->FCG0 &= ~u32Fcg0Periph; + } + else + { + M4_MSTP->FCG0 |= u32Fcg0Periph; + } + + DISABLE_FCG0_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG1 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg1Periph The peripheral in FCG1. + ** \arg PWC_FCG1_PERIPH_CAN CAN clock + ** \arg PWC_FCG1_PERIPH_QSPI QSPI clock + ** \arg PWC_FCG1_PERIPH_I2C1 I2C1 clock + ** \arg PWC_FCG1_PERIPH_I2C2 I2C2 clock + ** \arg PWC_FCG1_PERIPH_I2C3 I2C3 clock + ** \arg PWC_FCG1_PERIPH_USBFS USBFS clock + ** \arg PWC_FCG1_PERIPH_SDIOC1 SDIOC1 clock + ** \arg PWC_FCG1_PERIPH_SDIOC2 SDIOC2 clock + ** \arg PWC_FCG1_PERIPH_I2S1 I2S1 clock + ** \arg PWC_FCG1_PERIPH_I2S2 I2S2 clock + ** \arg PWC_FCG1_PERIPH_I2S3 I2S3 clock + ** \arg PWC_FCG1_PERIPH_I2S4 I2S4 clock + ** \arg PWC_FCG1_PERIPH_SPI1 SPI1 clock + ** \arg PWC_FCG1_PERIPH_SPI2 SPI2 clock + ** \arg PWC_FCG1_PERIPH_SPI3 SPI3 clock + ** \arg PWC_FCG1_PERIPH_SPI4 SPI4 clock + ** \arg PWC_FCG1_PERIPH_USART1 USART1 clock + ** \arg PWC_FCG1_PERIPH_USART2 USART2 clock + ** \arg PWC_FCG1_PERIPH_USART3 USART3 clock + ** \arg PWC_FCG1_PERIPH_USART4 USART4 clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG1 &= ~u32Fcg1Periph; + } + else + { + M4_MSTP->FCG1 |= u32Fcg1Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG2 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg2Periph The peripheral in FCG2. + ** \arg PWC_FCG2_PERIPH_TIM01 TIM01 clock + ** \arg PWC_FCG2_PERIPH_TIM02 TIM02 clock + ** \arg PWC_FCG2_PERIPH_TIMA1 TIMA1 clock + ** \arg PWC_FCG2_PERIPH_TIMA2 TIMA2 clock + ** \arg PWC_FCG2_PERIPH_TIMA3 TIMA3 clock + ** \arg PWC_FCG2_PERIPH_TIMA4 TIMA4 clock + ** \arg PWC_FCG2_PERIPH_TIMA5 TIMA5 clock + ** \arg PWC_FCG2_PERIPH_TIMA6 TIMA6 clock + ** \arg PWC_FCG2_PERIPH_TIM41 TIM41 clock + ** \arg PWC_FCG2_PERIPH_TIM42 TIM42 clock + ** \arg PWC_FCG2_PERIPH_TIM43 TIM43 clock + ** \arg PWC_FCG2_PERIPH_EMB EMB clock + ** \arg PWC_FCG2_PERIPH_TIM61 TIM61 clock + ** \arg PWC_FCG2_PERIPH_TIM62 TIM62 clock + ** \arg PWC_FCG2_PERIPH_TIM63 TIM63 clock + + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG2 &= ~u32Fcg2Periph; + } + else + { + M4_MSTP->FCG2 |= u32Fcg2Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG3 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg3Periph The peripheral in FCG3. + ** \arg PWC_FCG3_PERIPH_ADC1 ADC1 clock + ** \arg PWC_FCG3_PERIPH_ADC2 ADC2 clock + ** \arg PWC_FCG3_PERIPH_CMP CMP clock + ** \arg PWC_FCG3_PERIPH_OTS OTS clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG3 &= ~u32Fcg3Periph; + } + else + { + M4_MSTP->FCG3 |= u32Fcg3Periph; + } +} + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ** \param [in] pstcStpMdCfg Pointer to stop mode configuration structure. + ** \arg Enable Enable stop mode. + ** \arg Disable Disable stop mode. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_PWC_STOP_MODE_FLASH(pstcStpMdCfg->enStopFlash)); + DDL_ASSERT(IS_PWC_STOP_MODE_CLK(pstcStpMdCfg->enStopClk)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR = (pstcStpMdCfg->enStopFlash | + (pstcStpMdCfg->enStopClk << 1u) | + (1u << 14u)); + + /* if should close HRC & PLL while stop mode, please disable before modifying the register */ + if(Disable == pstcStpMdCfg->enPll) + { + /* PLL is system clock */ + if(5u == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Disable PLL */ + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + + /* Hrc power should be enable. */ + M4_SYSREG->PWR_PWRC1_f.VHRCSD = 0u; + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == pstcStpMdCfg->enPll) ? 0u : 1u); + M4_SYSREG->PWR_PWRC1_f.STPDAS = pstcStpMdCfg->enStpDrvAbi; + + DISABLE_PWR_REG0_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_STOPWKUPEN_EIRQ0 EIRQ0 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ1 EIRQ1 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ2 EIRQ2 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ3 EIRQ3 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ4 EIRQ4 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ5 EIRQ5 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ6 EIRQ6 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ7 EIRQ7 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ8 EIRQ8 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ9 EIRQ9 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ10 EIRQ10 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ11 EIRQ11 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ12 EIRQ12 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ13 EIRQ13 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ14 EIRQ14 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ15 EIRQ15 wake_up event + ** \arg PWC_STOPWKUPEN_SWDT SWDT wake_up event + ** \arg PWC_STOPWKUPEN_VDU1 VDU1 wake_up event + ** \arg PWC_STOPWKUPEN_VDU2 VDU2 wake_up event + ** \arg PWC_STOPWKUPEN_CMPI0 CMPI0 wake_up event + ** \arg PWC_STOPWKUPEN_WKTM WKTM wake_up event + ** \arg PWC_STOPWKUPEN_RTCAL RTCAL wake_up event + ** \arg PWC_STOPWKUPEN_RTCPRD RTCPRD wake_up event + ** \arg PWC_STOPWKUPEN_TMR0 TMR0 wake_up event + ** \arg PWC_STOPWKUPEN_USARTRXD USARTRXD wake_up event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_INTC->WUPEN |= u32Wkup0Event; + } + else + { + M4_INTC->WUPEN &= ~u32Wkup0Event; + } +} + +/** + ******************************************************************************* + ** \brief Enter sleep mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterSleepMd(void) +{ + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 0u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} +/** + ******************************************************************************* + ** \brief Ram area power down commond. + ** + ** \param [in] u32RamCtlBit The ram area contol. + ** \arg PWC_RAMPWRDOWN_SRAM1 Ram0(0x20000000-0x2000FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM2 Ram1(0x20010000-0x2001FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM3 Ram2(0x20020000-0x20026FFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAMH Ram3(0x1FFF8000-0x1FFFFFFF) power down control. + ** \arg PWC_RAMPWRDOWN_USBFS Usbfs power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC0 Sdioc0 power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC1 Sdioc1 power down control. + ** \arg PWC_RAMPWRDOWN_CAN Can power down control. + ** \arg PWC_RAMPWRDOWN_CACHE Cache power down control. + ** \arg PWC_RAMPWRDOWN_FULL Full. + ** + ** \param [in] enNewState The new state of the Ram area. + ** \arg Enable Ten ram area run. + ** \arg Disable The ram area power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_RAMPC0 &= ~u32RamCtlBit; + } + else + { + M4_SYSREG->PWR_RAMPC0 |= u32RamCtlBit; + } + + DISABLE_PWR_REG_WRITE(); +} + +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd) +{ + DDL_ASSERT(IS_PWC_RAM_OP_MD(enRamOpMd)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_RAMOPM = enRamOpMd; + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable XTAL/RTC/WKTM bias current. + ** + ** \param [in] enNewState The XTAL/RTC/WKTM bias current state. + ** \arg Enable Enable XTAL/RTC/WKTM bias current. + ** \arg Disable Disable XTAL/RTC/WKTM bias current. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Xtal32CsCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_XTAL32CS_f.CSDIS = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief wake_up timer control. + ** + ** \param [in] pstcWktmCtl The wake_up timer configuration. + ** \arg enWktmEn Enable or disable wake_up timer. + ** \arg enWkclk The wake_up timer clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWktmCtl->enWktmEn)); + DDL_ASSERT(IS_PWC_WKTM_CLK(pstcWktmCtl->enWkclk)); + DDL_ASSERT(IS_PWC_WKTMOVER_FLAG(pstcWktmCtl->enWkOverFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_WKTM->CR = ((pstcWktmCtl->u16WktmCmp & PWC_WKTMCMP_MSK) | + (pstcWktmCtl->enWkOverFlag << 12) | + (pstcWktmCtl->enWkclk << 13) | + (pstcWktmCtl->enWktmEn << 15)); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief The pvd configuration. + ** + ** \param [in] pstcPvdCfg The pvd configuration. + ** \arg enPtwk0Edge Ptwk0 edge + ** \arg enPtwk1Edge Ptwk1 edge + ** \arg enPtwk2Edge Ptwk2 edge + ** \arg enPtwk3Edge Ptwk3 edge + ** \arg enPvd1Edge Pvd1 edge + ** \arg enPvd1Edge Pvd2 edge + ** \arg enNmiEdge Nmi edge + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd1Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd2Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd1FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd1Filtclk)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd2FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd2Filtclk)); + DDL_ASSERT(IS_PWC_PVD1_LEVEL(pstcPvdCfg->enPvd1Level)); + DDL_ASSERT(IS_PWC_PVD2_LEVEL(pstcPvdCfg->enPvd2Level)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd1Int)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd2Int)); + + ENABLE_PVD_REG_WRITE(); + + /* Config Pvd control. */ + M4_SYSREG->PWR_PVDCR1 = (pstcPvdCfg->stcPvd1Ctl.enPvdIREn | + (pstcPvdCfg->stcPvd1Ctl.enPvdMode << 1) | + (pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn << 2) | + (pstcPvdCfg->stcPvd2Ctl.enPvdIREn<< 4) | + (pstcPvdCfg->stcPvd2Ctl.enPvdMode << 5) | + (pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn << 6)); + /* Set pvd filter sampling. */ + M4_SYSREG->PWR_PVDFCR = (~(pstcPvdCfg->enPvd1FilterEn) | + (pstcPvdCfg->enPvd1Filtclk << 1) | + ((~pstcPvdCfg->enPvd2FilterEn) << 4) | + (pstcPvdCfg->enPvd2Filtclk << 5)); + /* Set pvd level. */ + M4_SYSREG->PWR_PVDLCR = (pstcPvdCfg->enPvd1Level | + (pstcPvdCfg->enPvd2Level << 4)); + /* Set pvd interrupt(non_maskable or maskable). */ + M4_SYSREG->PWR_PVDICR = (pstcPvdCfg->enPvd1Int | + (pstcPvdCfg->enPvd2Int << 4)); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd1. + ** + ** \param [in] enNewState The pvd1 state. + ** \arg Enable Enable pvd1. + ** \arg Disable Disable pvd1. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd1Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD1EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd2. + ** + ** \param [in] enNewState The pvd2 state. + ** \arg Enable Enable pvd2. + ** \arg Disable Disable pvd2. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd2Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD2EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable external vcc. + ** + ** \param [in] enNewState The external vcc state. + ** \arg Enable Enable external vcc. + ** \arg Disable Disable external vcc. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ExVccCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.EXVCCINEN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection status. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1MON; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2MON; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd) +{ + ENABLE_PVD_REG_WRITE(); + switch(enPvd) + { + case PvdU1: + M4_SYSREG->PWR_PVDDSR_f.PVD1MON = 0u; + break; + case PvdU2: + M4_SYSREG->PWR_PVDDSR_f.PVD2MON = 0u; + break; + default: + break; + } + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable HRC power. + ** + ** \param [in] enNewState The HRC power state. + ** \arg Enable Enable HRC power. + ** \arg Disable Disable HRC power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_HrcPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VHRCSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable PLL power. + ** + ** \param [in] enNewState The PLL power state. + ** \arg Enable Enable PLL power. + ** \arg Disable Disable PLL power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_PllPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief NVIC backup and disable before entry from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicBackup(void) +{ + uint8_t u8Cnt; + stc_intc_sel_field_t *stcIntSel; + uint32_t u32WakeupSrc = INT_MAX; + + /* Backup NVIC set enable register for IRQ0~143*/ + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC_ISER_BAK[u8Cnt] = NVIC->ISER[u8Cnt]; + } + + /* Disable share vector */ + for (u8Cnt = 128u; u8Cnt < 144u; u8Cnt++) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + + for (u8Cnt = 0u; u8Cnt < 128u; u8Cnt++) + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * u8Cnt)); + /* Disable NVIC if it is the wakeup-able source from stop mode */ + u32WakeupSrc = stcIntSel->INTSEL; + if (IS_VALID_WKUP_SRC(u32WakeupSrc)) + { + switch (stcIntSel->INTSEL) + { + case INT_USART1_WUPI: + if (Reset == bM4_INTC_WUPEN_RXWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_TMR01_GCMA: + if (Reset == bM4_INTC_WUPEN_TMR0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_ALM: + if (Reset == bM4_INTC_WUPEN_RTCALMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_PRD: + if (Reset == bM4_INTC_WUPEN_RTCPRDWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_WKTM_PRD: + if (Reset == bM4_INTC_WUPEN_WKTMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_ACMP1: + if (Reset == bM4_INTC_WUPEN_CMPI0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD1: + if (Reset == bM4_INTC_WUPEN_PVD1WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD2: + if (Reset == bM4_INTC_WUPEN_PVD2WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_SWDT_REFUDF: + if (Reset == bM4_INTC_WUPEN_SWDTWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ0: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN0) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ1: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN1) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ2: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN2) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ3: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN3) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ4: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN4) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ5: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN5) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ6: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN6) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ7: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN7) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ8: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN8) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ9: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN9) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ10: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN10) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ11: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN11) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ12: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN12) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ13: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN13) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ14: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN14) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ15: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN15) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + default: + break; + } + } + /* Disable NVIC for all none-wakeup source */ + else if (INT_MAX != stcIntSel->INTSEL) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + else + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief NVIC recover after wakeup from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicRecover(void) +{ + uint8_t u8Cnt; + + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC->ISER[u8Cnt] = NVIC_ISER_BAK[u8Cnt]; + } +} + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] u8SysSrc The system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** This function only be called in func. PWC_enClockBackup and + ** PWC_enClockRecover. + ** If need to switch system clock please call CLK_SetSysClkSource. + ** + ******************************************************************************/ +static void PWC_SetSysClk(uint8_t u8SysSrc) +{ + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((5u == M4_SYSREG->CMU_CKSWR_f.CKSW) || (5u == u8SysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = 0xFFFFFAEEul; + M4_MSTP->FCG1 = 0xFFFFFFFFul; + M4_MSTP->FCG2 = 0xFFFFFFFFul; + M4_MSTP->FCG3 = 0xFFFFFFFFul; + + Ddl_Delay1us(1ul); + } + + /* Switch to target system clock source. */ + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = u8SysSrc; + + DISABLE_PWR_REG0_WRITE(); + + /* update system clock frequency. */ + SystemCoreClockUpdate(); + + Ddl_Delay1us(1ul); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + Ddl_Delay1us(1ul); +} +/** + ******************************************************************************* + ** \brief Backup HRC/MRC state and system clock , enable HRC/MRC ,set MRC as + ** system clock before enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockBackup(void) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status = Reset; + + /* HRC state backup. */ + u8HrcState = (uint8_t)bM4_SYSREG_CMU_HRCCR_HRCSTP; + /* System clock backup*/ + u8SysClkSrc = M4_SYSREG->CMU_CKSWR_f.CKSW; + + ENABLE_PWR_REG0_WRITE(); + + /* Enable HRC before enter stop mode. */ + if(0u != u8HrcState) + { + bM4_SYSREG_CMU_HRCCR_HRCSTP = 0u; + do + { + status = (en_flag_status_t)M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF; + timeout++; + }while((timeout < 0x1000ul) && (status != Set)); + } + else + { + /* code */ + } + /* When system clock source is HRC and MPLL, set MRC as system clock. . */ + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* MRC state backup. */ + u8MrcState = (uint8_t)bM4_SYSREG_CMU_MRCCR_MRCSTP; + if(0u != u8MrcState) + { + bM4_SYSREG_CMU_MRCCR_MRCSTP = 0u; + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + PWC_SetSysClk(1u); + } + else + { + /* code */ + } + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Recover HRC/MRC state and system clock after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockRecover(void) +{ + ENABLE_PWR_REG0_WRITE(); + + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* Recover MRC state & system clock source. */ + M4_SYSREG->CMU_MRCCR_f.MRCSTP = u8MrcState; + PWC_SetSysClk(u8SysClkSrc); + } + /* Recover HRC state after wakeup stop mode. */ + M4_SYSREG->CMU_HRCCR_f.HRCSTP = u8HrcState; + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before enter stop mode and mark it. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkBackup(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* HRC/MRC backup and switch system clock as MRC before entry from stop mode. */ + PWC_enClockBackup(); + + /* Mark the system clock has been switch as MRC, and will enter the stop mode. */ + u8StopFlag = 1u; + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock recover after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called after func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkRecover(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* Mark the system clock will be switch as MRC, and has waked_up from stop mode. */ + u8StopFlag = 0u; + + /* Recover HRC/MRC state and system clock after wakeup stop mode. */ + PWC_enClockRecover(); + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before exit wakup interrupt. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before exit wakup interrput. + ******************************************************************************/ +void PWC_IrqClkBackup(void) +{ + if((1ul == u8StopFlag) && (1ul == u8WkupIntCnt)) + { + /* HRC/MRC backup and switch system clock as MRC. */ + PWC_enClockBackup(); + } + u8WkupIntCnt--; +} + +/** + ******************************************************************************* + ** \brief Clock recover after enter wakeup interrupt. + ** + ** \param None + ** + ** \retval None + ** +** \note This function should be called after enter wakup interrput. + ******************************************************************************/ +void PWC_IrqClkRecover(void) +{ + /* The varibale to display how many waked_up interrupt has been occured + simultaneously and to decided whether backup clock before exit wake_up + interrupt. */ + u8WkupIntCnt++; + + if(1ul == u8StopFlag) + { + /* Recover HRC/MRC state and system clock. */ + PWC_enClockRecover(); + } +} + +/** + ******************************************************************************* + ** \brief Enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterStopMd(void) +{ + /* NVIC backup and disable before entry from stop mode.*/ + PWC_enNvicBackup(); + /* Clock backup and switch system clock as MRC before entry from stop mode. */ + PWC_ClkBackup(); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG0_WRITE(); + + __WFI(); + + /* Recover HRC/MRC state and system clock after wakeup from stop mode. */ + PWC_ClkRecover(); + /* NVIC recover after wakeup from stop mode. */ + PWC_enNvicRecover(); +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low_speed (HCLK < 8MHz) to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + M4_SYSREG->PWR_PWRC2 = 0xE1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to low_speed (HCLK < 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HS(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1ul); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2HP(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2HS(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low-speed (HCLK <= 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HP(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to low-speed (HCLK <= 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + u32To = 10000ul; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + M4_SYSREG->PWR_PWRC2 = 0xD1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1); + + return Ok; +} + +//@} // PwcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_qspi.c b/lib/hc32f460/driver/src/hc32f460_qspi.c new file mode 100644 index 000000000000..5edd4e9428c4 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_qspi.c @@ -0,0 +1,752 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.c + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_qspi.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup QspiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( ((x) == QspiHclkDiv2) || \ + (((x) >= QspiHclkDiv3) && ((x) <= QspiHclkDiv64))) + +/*!< Parameter valid check for spi mode */ +#define IS_VALID_SPI_MODE(x) \ +( (QspiSpiMode0 == (x)) || \ + (QspiSpiMode3 == (x))) + +/*!< Parameter valid check for bus communication mode */ +#define IS_VALID_BUS_COMM_MODE(x) \ +( (QspiBusModeRomAccess == (x)) || \ + (QspiBusModeDirectAccess == (x))) + +/*!< Parameter valid check for prefetch stop location */ +#define IS_VALID_PREFETCH_STOP_LOCATION(x) \ +( (QspiPrefetchStopComplete == (x)) || \ + (QspiPrefetchStopImmediately == (x))) + +/*!< Parameter valid check for receive data protocol */ +#define IS_VALID_RECE_DATA_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit address protocol */ +#define IS_VALID_TRANS_ADDR_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit instruction protocol */ +#define IS_VALID_TRANS_INSTRUCT_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for serial interface read mode */ +#define IS_VALID_INTERFACE_READ_MODE(x) \ +( (QspiReadModeStandard == (x)) || \ + (QspiReadModeFast == (x)) || \ + (QspiReadModeTwoWiresOutput == (x)) || \ + (QspiReadModeTwoWiresIO == (x)) || \ + (QspiReadModeFourWiresOutput == (x)) || \ + (QspiReadModeFourWiresIO == (x)) || \ + (QspiReadModeCustomStandard == (x)) || \ + (QspiReadModeCustomFast == (x))) + +/*!< Parameter valid check for QSSN valid extend delay time */ +#define IS_VALID_QSSN_VALID_EXTEND_TIME(x) \ +( (QspiQssnValidExtendNot == (x)) || \ + (QspiQssnValidExtendSck32 == (x)) || \ + (QspiQssnValidExtendSck128 == (x)) || \ + (QspiQssnValidExtendSckEver == (x))) + +/*!< Parameter valid check for QSSN minimum interval time */ +#define IS_VALID_QSSN_INTERVAL_TIME(x) \ +( (QspiQssnIntervalQsck1 == (x)) || \ + (QspiQssnIntervalQsck2 == (x)) || \ + (QspiQssnIntervalQsck3 == (x)) || \ + (QspiQssnIntervalQsck4 == (x)) || \ + (QspiQssnIntervalQsck5 == (x)) || \ + (QspiQssnIntervalQsck6 == (x)) || \ + (QspiQssnIntervalQsck7 == (x)) || \ + (QspiQssnIntervalQsck8 == (x)) || \ + (QspiQssnIntervalQsck9 == (x)) || \ + (QspiQssnIntervalQsck10 == (x)) || \ + (QspiQssnIntervalQsck11 == (x)) || \ + (QspiQssnIntervalQsck12 == (x)) || \ + (QspiQssnIntervalQsck13 == (x)) || \ + (QspiQssnIntervalQsck14 == (x)) || \ + (QspiQssnIntervalQsck15 == (x)) || \ + (QspiQssnIntervalQsck16 <= (x))) + +/*!< Parameter valid check for QSCK duty correction */ +#define IS_VALID_QSCK_DUTY_CORR(x) \ +( (QspiQsckDutyCorrNot == (x)) || \ + (QspiQsckDutyCorrHalfHclk == (x))) + +/*!< Parameter valid check for virtual cycles */ +#define IS_VALID_VIRTUAL_CYCLES(x) \ +( (QspiVirtualPeriodQsck3 == (x)) || \ + (QspiVirtualPeriodQsck4 == (x)) || \ + (QspiVirtualPeriodQsck5 == (x)) || \ + (QspiVirtualPeriodQsck6 == (x)) || \ + (QspiVirtualPeriodQsck7 == (x)) || \ + (QspiVirtualPeriodQsck8 == (x)) || \ + (QspiVirtualPeriodQsck9 == (x)) || \ + (QspiVirtualPeriodQsck10 == (x)) || \ + (QspiVirtualPeriodQsck11 == (x)) || \ + (QspiVirtualPeriodQsck12 == (x)) || \ + (QspiVirtualPeriodQsck13 == (x)) || \ + (QspiVirtualPeriodQsck14 == (x)) || \ + (QspiVirtualPeriodQsck15 == (x)) || \ + (QspiVirtualPeriodQsck16 == (x)) || \ + (QspiVirtualPeriodQsck17 == (x)) || \ + (QspiVirtualPeriodQsck18 == (x))) + +/*!< Parameter valid check for WP pin output level */ +#define IS_VALID_WP_OUTPUT_LEVEL(x) \ +( (QspiWpPinOutputLow == (x)) || \ + (QspiWpPinOutputHigh == (x))) + +/*!< Parameter valid check for QSSN setup delay time */ +#define IS_VALID_QSSN_SETUP_DELAY(x) \ +( (QspiQssnSetupDelayHalfQsck == (x)) || \ + (QspiQssnSetupDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for QSSN hold delay time */ +#define IS_VALID_QSSN_HOLD_TIME(x) \ +( (QspiQssnHoldDelayHalfQsck == (x)) || \ + (QspiQssnHoldDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for interface address width */ +#define IS_VALID_INTERFACE_ADDR_WIDTH(x) \ +( (QspiAddressByteOne == (x)) || \ + (QspiAddressByteTwo == (x)) || \ + (QspiAddressByteThree == (x)) || \ + (QspiAddressByteFour == (x))) + +/*!< Parameter valid check for extend address */ +#define IS_VALID_SET_EXTEND_ADDR(x) ((x) <= 0x3Fu) + +/*!< Parameter valid check for get flag type */ +#define IS_VALID_GET_FLAG_TYPE(x) \ +( (QspiFlagBusBusy == (x)) || \ + (QspiFlagXipMode == (x)) || \ + (QspiFlagRomAccessError == (x)) || \ + (QspiFlagPrefetchBufferFull == (x)) || \ + (QspiFlagPrefetchStop == (x))) + +/*!< Parameter valid check for clear flag type */ +#define IS_VALID_CLEAR_FLAG_TYPE(x) (QspiFlagRomAccessError == (x)) + +/*!< QSPI registers reset value */ +#define QSPI_REG_CR_RESET_VALUE (0x003F0000ul) +#define QSPI_REG_CSCR_RESET_VALUE (0x0000000Ful) +#define QSPI_REG_FCR_RESET_VALUE (0x000080B3ul) +#define QSPI_REG_SR_RESET_VALUE (0x00008000ul) +#define QSPI_REG_CCMD_RESET_VALUE (0x00000000ul) +#define QSPI_REG_XCMD_RESET_VALUE (0x000000FFul) +#define QSPI_REG_EXAR_RESET_VALUE (0x00000000ul) +#define QSPI_REG_SR2_RESET_VALUE (0x00000000ul) +#define QSPI_REG_DCOM_RESET_VALUE (0x00000000ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize QSPI unit + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_DeInit(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR = QSPI_REG_CR_RESET_VALUE; + if (1u == M4_QSPI->SR_f.RAER) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + M4_QSPI->CSCR = QSPI_REG_CSCR_RESET_VALUE; + M4_QSPI->FCR = QSPI_REG_FCR_RESET_VALUE; + M4_QSPI->EXAR = QSPI_REG_EXAR_RESET_VALUE; + M4_QSPI->SR = QSPI_REG_SR_RESET_VALUE; + M4_QSPI->CCMD = QSPI_REG_CCMD_RESET_VALUE; + M4_QSPI->XCMD = QSPI_REG_XCMD_RESET_VALUE; + M4_QSPI->DCOM = QSPI_REG_DCOM_RESET_VALUE; + M4_QSPI->SR2 = QSPI_REG_SR2_RESET_VALUE; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize QSPI unit + ** + ** \param [in] pstcQspiInitCfg Pointer to qspi configuration + ** \arg See the struct #stc_qspi_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcQspiInitCfg) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_DIV(pstcQspiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_SPI_MODE(pstcQspiInitCfg->enSpiMode)); + DDL_ASSERT(IS_VALID_BUS_COMM_MODE(pstcQspiInitCfg->enBusCommMode)); + DDL_ASSERT(IS_VALID_PREFETCH_STOP_LOCATION(pstcQspiInitCfg->enPrefetchMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enPrefetchFuncEn)); + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcQspiInitCfg->stcCommProtocol.enReadMode)); + DDL_ASSERT(IS_VALID_QSSN_VALID_EXTEND_TIME(pstcQspiInitCfg->enQssnValidExtendTime)); + DDL_ASSERT(IS_VALID_QSSN_INTERVAL_TIME(pstcQspiInitCfg->enQssnIntervalTime)); + DDL_ASSERT(IS_VALID_QSCK_DUTY_CORR(pstcQspiInitCfg->enQsckDutyCorr)); + DDL_ASSERT(IS_VALID_VIRTUAL_CYCLES(pstcQspiInitCfg->enVirtualPeriod)); + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(pstcQspiInitCfg->enWpPinLevel)); + DDL_ASSERT(IS_VALID_QSSN_SETUP_DELAY(pstcQspiInitCfg->enQssnSetupDelayTime)); + DDL_ASSERT(IS_VALID_QSSN_HOLD_TIME(pstcQspiInitCfg->enQssnHoldDelayTime)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enFourByteAddrReadEn)); + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(pstcQspiInitCfg->enAddrWidth)); + + /* Configure control register */ + M4_QSPI->CR_f.DIV = pstcQspiInitCfg->enClkDiv; + M4_QSPI->CR_f.SPIMD3 = pstcQspiInitCfg->enSpiMode; + M4_QSPI->CR_f.PFE = pstcQspiInitCfg->enPrefetchFuncEn; + M4_QSPI->CR_f.PFSAE = pstcQspiInitCfg->enPrefetchMode; + M4_QSPI->CR_f.MDSEL = pstcQspiInitCfg->stcCommProtocol.enReadMode; + + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcQspiInitCfg->stcCommProtocol.enReadMode) || + (QspiReadModeCustomStandard == pstcQspiInitCfg->stcCommProtocol.enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcQspiInitCfg->stcCommProtocol.enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + + /* Configure chip select control register */ + M4_QSPI->CSCR_f.SSNW = pstcQspiInitCfg->enQssnValidExtendTime; + M4_QSPI->CSCR_f.SSHW = pstcQspiInitCfg->enQssnIntervalTime; + + /* Configure format control register */ + if (((pstcQspiInitCfg->enClkDiv % 2) != 0) && + (pstcQspiInitCfg->enQsckDutyCorr != QspiQsckDutyCorrNot)) + { + M4_QSPI->FCR_f.DUTY = QspiQsckDutyCorrNot; + } + else + { + M4_QSPI->FCR_f.DUTY = pstcQspiInitCfg->enQsckDutyCorr; + } + M4_QSPI->FCR_f.DMCYCN = pstcQspiInitCfg->enVirtualPeriod; + M4_QSPI->FCR_f.WPOL = pstcQspiInitCfg->enWpPinLevel; + M4_QSPI->FCR_f.SSNLD = pstcQspiInitCfg->enQssnSetupDelayTime; + M4_QSPI->FCR_f.SSNHD = pstcQspiInitCfg->enQssnHoldDelayTime; + M4_QSPI->FCR_f.FOUR_BIC = pstcQspiInitCfg->enFourByteAddrReadEn; + M4_QSPI->FCR_f.AWSL = pstcQspiInitCfg->enAddrWidth; + M4_QSPI->CR_f.DCOME = pstcQspiInitCfg->enBusCommMode; + + /* Configure ROM access instruction */ + M4_QSPI->CCMD = pstcQspiInitCfg->u8RomAccessInstr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Config communication protocol structure + ** + ** \param [in] pstcCommProtocol Pointer to qspi communication protocol configuration + ** \arg See the struct #stc_qspi_comm_protocol_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol) +{ + en_result_t enRet = Ok; + + if (NULL == pstcCommProtocol) + { + enRet = Error; + } + else + { + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcCommProtocol->enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcCommProtocol->enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcCommProtocol->enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcCommProtocol->enReadMode)); + + M4_QSPI->CR_f.MDSEL = pstcCommProtocol->enReadMode; + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcCommProtocol->enReadMode) || + (QspiReadModeCustomStandard == pstcCommProtocol->enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcCommProtocol->enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcCommProtocol->enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcCommProtocol->enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable prefetch function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable prefetch function + ** \arg Enable Enable prefetch function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->CR_f.PFE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set clock division + ** + ** \param [in] enClkDiv Clock division + ** \arg QspiHclkDiv2 Clock source: HCLK/2 + ** \arg QspiHclkDiv3 Clock source: HCLK/3 + ** \arg QspiHclkDiv4 Clock source: HCLK/4 + ** \arg QspiHclkDiv5 Clock source: HCLK/5 + ** \arg QspiHclkDiv6 Clock source: HCLK/6 + ** \arg QspiHclkDiv7 Clock source: HCLK/7 + ** \arg QspiHclkDiv8 Clock source: HCLK/8 + ** \arg QspiHclkDiv9 Clock source: HCLK/9 + ** \arg QspiHclkDiv10 Clock source: HCLK/10 + ** \arg QspiHclkDiv11 Clock source: HCLK/11 + ** \arg QspiHclkDiv12 Clock source: HCLK/12 + ** \arg QspiHclkDiv13 Clock source: HCLK/13 + ** \arg QspiHclkDiv14 Clock source: HCLK/14 + ** \arg QspiHclkDiv15 Clock source: HCLK/15 + ** \arg QspiHclkDiv16 Clock source: HCLK/16 + ** \arg QspiHclkDiv17 Clock source: HCLK/17 + ** \arg QspiHclkDiv18 Clock source: HCLK/18 + ** \arg QspiHclkDiv19 Clock source: HCLK/19 + ** \arg QspiHclkDiv20 Clock source: HCLK/20 + ** \arg QspiHclkDiv21 Clock source: HCLK/21 + ** \arg QspiHclkDiv22 Clock source: HCLK/22 + ** \arg QspiHclkDiv23 Clock source: HCLK/23 + ** \arg QspiHclkDiv24 Clock source: HCLK/24 + ** \arg QspiHclkDiv25 Clock source: HCLK/25 + ** \arg QspiHclkDiv26 Clock source: HCLK/26 + ** \arg QspiHclkDiv27 Clock source: HCLK/27 + ** \arg QspiHclkDiv28 Clock source: HCLK/28 + ** \arg QspiHclkDiv29 Clock source: HCLK/29 + ** \arg QspiHclkDiv30 Clock source: HCLK/30 + ** \arg QspiHclkDiv31 Clock source: HCLK/31 + ** \arg QspiHclkDiv32 Clock source: HCLK/32 + ** \arg QspiHclkDiv33 Clock source: HCLK/33 + ** \arg QspiHclkDiv34 Clock source: HCLK/34 + ** \arg QspiHclkDiv35 Clock source: HCLK/35 + ** \arg QspiHclkDiv36 Clock source: HCLK/36 + ** \arg QspiHclkDiv37 Clock source: HCLK/37 + ** \arg QspiHclkDiv38 Clock source: HCLK/38 + ** \arg QspiHclkDiv39 Clock source: HCLK/39 + ** \arg QspiHclkDiv40 Clock source: HCLK/40 + ** \arg QspiHclkDiv41 Clock source: HCLK/41 + ** \arg QspiHclkDiv42 Clock source: HCLK/42 + ** \arg QspiHclkDiv43 Clock source: HCLK/43 + ** \arg QspiHclkDiv44 Clock source: HCLK/44 + ** \arg QspiHclkDiv45 Clock source: HCLK/45 + ** \arg QspiHclkDiv46 Clock source: HCLK/46 + ** \arg QspiHclkDiv47 Clock source: HCLK/47 + ** \arg QspiHclkDiv48 Clock source: HCLK/48 + ** \arg QspiHclkDiv49 Clock source: HCLK/49 + ** \arg QspiHclkDiv50 Clock source: HCLK/50 + ** \arg QspiHclkDiv51 Clock source: HCLK/51 + ** \arg QspiHclkDiv52 Clock source: HCLK/52 + ** \arg QspiHclkDiv53 Clock source: HCLK/53 + ** \arg QspiHclkDiv54 Clock source: HCLK/54 + ** \arg QspiHclkDiv55 Clock source: HCLK/55 + ** \arg QspiHclkDiv56 Clock source: HCLK/56 + ** \arg QspiHclkDiv57 Clock source: HCLK/57 + ** \arg QspiHclkDiv58 Clock source: HCLK/58 + ** \arg QspiHclkDiv59 Clock source: HCLK/59 + ** \arg QspiHclkDiv60 Clock source: HCLK/60 + ** \arg QspiHclkDiv61 Clock source: HCLK/61 + ** \arg QspiHclkDiv62 Clock source: HCLK/62 + ** \arg QspiHclkDiv63 Clock source: HCLK/63 + ** \arg QspiHclkDiv64 Clock source: HCLK/64 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + M4_QSPI->CR_f.DIV = enClkDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set WP Pin level + ** + ** \param [in] enWpLevel WP pin level + ** \arg QspiWpPinOutputLow WP pin(QIO2) output low level + ** \arg QspiWpPinOutputHigh WP pin(QIO2) output high level + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(enWpLevel)); + + M4_QSPI->FCR_f.WPOL = enWpLevel; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set communication address width + ** + ** \param [in] enAddrWidth Communication address width + ** \arg QspiAddressByteOne One byte address + ** \arg QspiAddressByteTwo Two byte address + ** \arg QspiAddressByteThree Three byte address + ** \arg QspiAddressByteFour Four byte address + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(enAddrWidth)); + + M4_QSPI->FCR_f.AWSL = enAddrWidth; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set extend address value + ** + ** \param [in] u8Addr Extend address value + ** \arg 0~0x3F + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_SET_EXTEND_ADDR(u8Addr)); + + M4_QSPI->EXAR_f.EXADR = u8Addr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set rom access instruction + ** + ** \param [in] u8Instr Rom access instruction + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr) +{ + en_result_t enRet = Ok; + + M4_QSPI->CCMD = u8Instr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write direct communication value + ** + ** \param [in] u8Val Direct communication value + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val) +{ + en_result_t enRet = Ok; + + M4_QSPI->DCOM = u8Val; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read direct communication value + ** + ** \param [in] None + ** + ** \retval uint8_t Direct communication read value + ** + ******************************************************************************/ +uint8_t QSPI_ReadDirectCommValue(void) +{ + return ((uint8_t)M4_QSPI->DCOM); +} + +/** + ******************************************************************************* + ** \brief Enable or disable xip mode + ** + ** \param [in] u8Instr Enable or disable xip mode instruction + ** \arg 0~0xFF + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable xip mode + ** \arg Enable Enable xip mode + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->XCMD = u8Instr; + if (Enable == enNewSta) + { + M4_QSPI->CR_f.XIPE = 1u; + } + else + { + M4_QSPI->CR_f.XIPE = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ** \note If you are in XIP mode, you need to exit XIP mode and then start direct communication mode. + ** + ******************************************************************************/ +en_result_t QSPI_EnterDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 1u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_ExitDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 0u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get prefetch buffer current byte number + ** + ** \param [in] None + ** + ** \retval uint8_t Current buffer byte number + ** + ******************************************************************************/ +uint8_t QSPI_GetPrefetchBufferNum(void) +{ + return ((uint8_t)M4_QSPI->SR_f.PFNUM); +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagBusBusy QSPI bus work status flag in direct communication mode + ** \arg QspiFlagXipMode XIP mode status signal + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** \arg QspiFlagPrefetchBufferFull Prefetch buffer area status signal + ** \arg QspiFlagPrefetchStop Prefetch action status signal + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + DDL_ASSERT(IS_VALID_GET_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case QspiFlagBusBusy: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.BUSY; + break; + case QspiFlagXipMode: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.XIPF; + break; + case QspiFlagRomAccessError: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.RAER; + break; + case QspiFlagPrefetchBufferFull: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFFUL; + break; + case QspiFlagPrefetchStop: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFAN; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + if (QspiFlagRomAccessError == enFlag) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +//@} // QspiGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_rmu.c b/lib/hc32f460/driver/src/hc32f460_rmu.c new file mode 100644 index 000000000000..64a1eaadd8b8 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_rmu.c @@ -0,0 +1,139 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.c + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rmu.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup RmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa502u) +#define DISABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa500u) + +#define RMU_FLAG_TIM ((uint16_t)0x1000u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Get the chip reset cause. + ** + ** \param [in] pstcData Pointer to return reset cause structure. + ** + ** \retval Ok Get successfully. + ** + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData) +{ + uint16_t u16RstCause = 0u; + stc_sysreg_rmu_rstf0_field_t *RMU_RSTF0_f = NULL; + + if(NULL == pstcData) + { + return ErrorInvalidParameter; + } + + u16RstCause = M4_SYSREG->RMU_RSTF0; + RMU_RSTF0_f = (stc_sysreg_rmu_rstf0_field_t *)(&u16RstCause); + + pstcData->enMultiRst = (en_flag_status_t)(RMU_RSTF0_f->MULTIRF == 1u); + pstcData->enXtalErr = (en_flag_status_t)(RMU_RSTF0_f->XTALERF == 1u); + pstcData->enClkFreqErr = (en_flag_status_t)(RMU_RSTF0_f->CKFERF == 1u); + pstcData->enRamEcc = (en_flag_status_t)(RMU_RSTF0_f->RAECRF == 1u); + pstcData->enRamParityErr = (en_flag_status_t)(RMU_RSTF0_f->RAPERF == 1u); + pstcData->enMpuErr = (en_flag_status_t)(RMU_RSTF0_f->MPUERF == 1u); + pstcData->enSoftware = (en_flag_status_t)(RMU_RSTF0_f->SWRF == 1u); + pstcData->enPowerDown = (en_flag_status_t)(RMU_RSTF0_f->PDRF == 1u); + pstcData->enSwdt = (en_flag_status_t)(RMU_RSTF0_f->SWDRF == 1u); + pstcData->enWdt = (en_flag_status_t)(RMU_RSTF0_f->WDRF == 1u); + pstcData->enPvd2 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enPvd1 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enBrownOut = (en_flag_status_t)(RMU_RSTF0_f->BORF == 1u); + pstcData->enRstPin = (en_flag_status_t)(RMU_RSTF0_f->PINRF == 1u); + pstcData->enPowerOn = (en_flag_status_t)(RMU_RSTF0_f->PORF == 1u); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Clear the reset flag. + ** + ** \param None + ** + ** \retval Ok Clear successfully. + ** + ** \note clear reset flag should be done after read RMU_RSTF0 register. + ******************************************************************************/ +en_result_t RMU_ClrResetFlag(void) +{ + uint16_t u16status = 0u; + uint32_t u32timeout = 0u; + + ENABLE_RMU_REG_WRITE(); + + do + { + u32timeout++; + M4_SYSREG->RMU_RSTF0_f.CLRF = 1u; + u16status = M4_SYSREG->RMU_RSTF0; + }while((u32timeout != RMU_FLAG_TIM) && u16status); + + DISABLE_RMU_REG_WRITE(); + + if(u32timeout >= RMU_FLAG_TIM) + { + return ErrorTimeout; + } + + return Ok; +} + + +//@} // RmuGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/lib/hc32f460/driver/src/hc32f460_rtc.c b/lib/hc32f460/driver/src/hc32f460_rtc.c new file mode 100644 index 000000000000..45695d961b3e --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_rtc.c @@ -0,0 +1,974 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.c + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rtc.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock source type */ +#define IS_VALID_CLK_SOURCE_TYPE(x) \ +( (RtcClkXtal32 == (x)) || \ + (RtcClkLrc == (x))) + +/*!< Parameter valid check for period interrupt condition */ +#define IS_VALID_PERIOD_INT_CONDITION(x) \ +( (RtcPeriodIntInvalid == (x)) || \ + (RtcPeriodIntHalfSec == (x)) || \ + (RtcPeriodIntOneSec == (x)) || \ + (RtcPeriodIntOneMin == (x)) || \ + (RtcPeriodIntOneHour == (x)) || \ + (RtcPeriodIntOneDay == (x)) || \ + (RtcPeriodIntOneMon == (x))) + +/*!< Parameter valid check for time format */ +#define IS_VALID_TIME_FORMAT(x) \ +( (RtcTimeFormat12Hour == (x)) || \ + (RtcTimeFormat24Hour == (x))) + +/*!< Parameter valid check for compensation way */ +#define IS_VALID_COMPEN_WAY(x) \ +( (RtcOutputCompenDistributed == (x)) || \ + (RtcOutputCompenUniform == (x))) + +/*!< Parameter valid check for compensation value range */ +#define IS_VALID_COMPEN_VALUE_RANGE(x) ((x) <= 0x1FFu) + +/*!< Parameter valid check for data format */ +#define IS_VALID_DATA_FORMAT(x) \ +( (RtcDataFormatDec == (x)) || \ + (RtcDataFormatBcd == (x))) + +/*!< Parameter valid check for time second */ +#define IS_VALID_TIME_SECOND(x) ((x) <= 59u) + +/*!< Parameter valid check for time minute */ +#define IS_VALID_TIME_MINUTE(x) ((x) <= 59u) + +/*!< Parameter valid check for time hour */ +#define IS_VALID_TIME_HOUR12(x) (((x) >= 1u) && ((x) <= 12u)) +#define IS_VALID_TIME_HOUR24(x) ((x) <= 23u) + +/*!< Parameter valid check for date weekday */ +#define IS_VALID_DATE_WEEKDAY(x) ((x) <= 6u) + +/*!< Parameter valid check for date day */ +#define IS_VALID_DATE_DAY(x) (((x) >= 1u) && ((x) <= 31u)) + +/*!< Parameter valid check for date month */ +#define IS_VALID_DATE_MONTH(x) (((x) >= 1u) && ((x) <= 12u)) + +/*!< Parameter valid check for date year */ +#define IS_VALID_DATE_YEAR(x) ((x) <= 99u) + +/*!< Parameter valid check for hour12 am/pm */ +#define IS_VALID_HOUR12_AMPM(x) \ +( (RtcHour12Am == (x)) || \ + (RtcHour12Pm == (x))) + +/*!< Parameter valid check for alarm weekday */ +#define IS_VALID_ALARM_WEEKDAY(x) (((x) >= 1u) && ((x) <= 0x7Fu)) + +/*!< Parameter valid check for interrupt request type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (RtcIrqPeriod == (x)) || \ + (RtcIrqAlarm == (x))) + +/*!< 12 hour format am/pm status bit */ +#define RTC_HOUR12_AMPM_MASK (0x20u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize RTC + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout De-Initialize timeout + ** + ******************************************************************************/ +en_result_t RTC_DeInit(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + M4_RTC->CR0_f.RESET = 0u; + /* Waiting for normal count status or end of RTC software reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR0_f.RESET; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + /* Initialize all RTC registers */ + M4_RTC->CR0_f.RESET = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize RTC + ** + ** \param [in] pstcRtcInit Pointer to RTC init configuration + ** \arg See the struct #stc_rtc_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_SOURCE_TYPE(pstcRtcInit->enClkSource)); + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(pstcRtcInit->enPeriodInt)); + DDL_ASSERT(IS_VALID_TIME_FORMAT(pstcRtcInit->enTimeFormat)); + DDL_ASSERT(IS_VALID_COMPEN_WAY(pstcRtcInit->enCompenWay)); + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(pstcRtcInit->u16CompenVal)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcRtcInit->enCompenEn)); + + /* Configure clock */ + if (RtcClkLrc == pstcRtcInit->enClkSource) + { + M4_RTC->CR3_f.LRCEN = 1u; + } + M4_RTC->CR3_f.RCKSEL = pstcRtcInit->enClkSource; + + /* Configure control register */ + M4_RTC->CR1_f.PRDS = pstcRtcInit->enPeriodInt; + M4_RTC->CR1_f.AMPM = pstcRtcInit->enTimeFormat; + M4_RTC->CR1_f.ONEHZSEL = pstcRtcInit->enCompenWay; + + /* Configure clock error compensation register */ + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)pstcRtcInit->u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)pstcRtcInit->u16CompenVal & 0x00FFu; + M4_RTC->ERRCRH_f.COMPEN = pstcRtcInit->enCompenEn; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Enter mode timeout + ** + ******************************************************************************/ +en_result_t RTC_EnterRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RWEN bit set */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Exit mode timeout + ** + ******************************************************************************/ +en_result_t RTC_ExitRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RWEN bit reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC count + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC count + ** \arg Enable Enable RTC count + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_Cmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.START = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC period interrupt config + ** + ** \param [in] enIntType Period interrupt request type + ** \arg RtcPeriodIntInvalid Period interrupt invalid + ** \arg RtcPeriodIntHalfSec 0.5 second period interrupt + ** \arg RtcPeriodIntOneSec 1 second period interrupt + ** \arg RtcPeriodIntOneMin 1 minute period interrupt + ** \arg RtcPeriodIntOneHour 1 hour period interrupt + ** \arg RtcPeriodIntOneDay 1 day period interrupt + ** \arg RtcPeriodIntOneMon 1 month period interrupt + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(enIntType)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.PRDIE; + /* Disable period interrupt when START=1 and PRDIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 0u; + } + M4_RTC->CR1_f.PRDS = enIntType; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC switch to low power mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode RTC count not start + ** \retval ErrorTimeout Switch timeout + ** + ******************************************************************************/ +en_result_t RTC_LowPowerSwitch(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = ErrorInvalidMode; + + /* Check RTC work status */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RTC RWEN bit set */ + u32Timeout = SystemCoreClock / 100u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RTC RWEN bit reset */ + u32TimeCnt = 0u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC 1hz output compensation value + ** + ** \param [in] u16CompenVal Clock compensation value + ** \arg 0~0x1FF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(u16CompenVal)); + + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)u16CompenVal & 0x00FFu; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable clock compensation + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC clock compensation + ** \arg Enable Enable RTC clock compensation + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->ERRCRH_f.COMPEN = enNewSta; + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Enable or disable RTC 1hz output + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC 1hz output + ** \arg Enable Enable RTC 1hz output + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.ONEHZOE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \param [in] enUpdateDateEn The function new state(Contain year/month/day/weekday) + ** \arg Disable Disable update RTC date + ** \arg Enable Enable update RTC date + ** + ** \param [in] enUpdateTimeEn The function new state(Contain hour/minute/second) + ** \arg Disable Disable update RTC time + ** \arg Enable Enable update RTC time + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** \retval ErrorInvalidParameter Parameter enUpdateDateEn or enUpdateTimeEn invalid + ** + ******************************************************************************/ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateDateEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateTimeEn)); + + /* Check update status */ + if (((Disable == enUpdateDateEn) && (Disable == enUpdateTimeEn)) || (NULL == pstcRtcDateTime)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check the date parameters */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + DDL_ASSERT(IS_VALID_DATE_YEAR(pstcRtcDateTime->u8Year)); + DDL_ASSERT(IS_VALID_DATE_MONTH(pstcRtcDateTime->u8Month)); + DDL_ASSERT(IS_VALID_DATE_DAY(pstcRtcDateTime->u8Day)); + } + else + { + DDL_ASSERT(IS_VALID_DATE_YEAR(BCD2DEC(pstcRtcDateTime->u8Year))); + DDL_ASSERT(IS_VALID_DATE_MONTH(BCD2DEC(pstcRtcDateTime->u8Month))); + DDL_ASSERT(IS_VALID_DATE_DAY(BCD2DEC(pstcRtcDateTime->u8Day))); + } + DDL_ASSERT(IS_VALID_DATE_WEEKDAY(pstcRtcDateTime->u8Weekday)); + } + /* Check the time parameters */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcDateTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcDateTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcDateTime->u8Minute)); + DDL_ASSERT(IS_VALID_TIME_SECOND(pstcRtcDateTime->u8Second)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcDateTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcDateTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcDateTime->u8Minute))); + DDL_ASSERT(IS_VALID_TIME_SECOND(BCD2DEC(pstcRtcDateTime->u8Second))); + } + } + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Update date */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + M4_RTC->YEAR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Year); + M4_RTC->MON = DEC2BCD((uint32_t)pstcRtcDateTime->u8Month); + M4_RTC->DAY = DEC2BCD((uint32_t)pstcRtcDateTime->u8Day); + } + else + { + M4_RTC->YEAR = pstcRtcDateTime->u8Year; + M4_RTC->MON = pstcRtcDateTime->u8Month; + M4_RTC->DAY = pstcRtcDateTime->u8Day; + } + M4_RTC->WEEK = pstcRtcDateTime->u8Weekday; + } + /* Update time */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour); + } + M4_RTC->MIN = DEC2BCD((uint32_t)pstcRtcDateTime->u8Minute); + M4_RTC->SEC = DEC2BCD((uint32_t)pstcRtcDateTime->u8Second); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour; + } + M4_RTC->MIN = pstcRtcDateTime->u8Minute; + M4_RTC->SEC = pstcRtcDateTime->u8Second; + } + } + /* Exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** + ******************************************************************************/ +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcDateTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Get RTC date and time registers */ + pstcRtcDateTime->u8Year = (uint8_t)(M4_RTC->YEAR); + pstcRtcDateTime->u8Month = (uint8_t)(M4_RTC->MON); + pstcRtcDateTime->u8Day = (uint8_t)(M4_RTC->DAY); + pstcRtcDateTime->u8Weekday = (uint8_t)(M4_RTC->WEEK); + pstcRtcDateTime->u8Hour = (uint8_t)(M4_RTC->HOUR); + pstcRtcDateTime->u8Minute = (uint8_t)(M4_RTC->MIN); + pstcRtcDateTime->u8Second = (uint8_t)(M4_RTC->SEC); + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if (RTC_HOUR12_AMPM_MASK == (pstcRtcDateTime->u8Hour & RTC_HOUR12_AMPM_MASK)) + { + pstcRtcDateTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcDateTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcDateTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcDateTime->u8Year = BCD2DEC(pstcRtcDateTime->u8Year); + pstcRtcDateTime->u8Month = BCD2DEC(pstcRtcDateTime->u8Month); + pstcRtcDateTime->u8Day = BCD2DEC(pstcRtcDateTime->u8Day); + pstcRtcDateTime->u8Hour = BCD2DEC(pstcRtcDateTime->u8Hour); + pstcRtcDateTime->u8Minute = BCD2DEC(pstcRtcDateTime->u8Minute); + pstcRtcDateTime->u8Second = BCD2DEC(pstcRtcDateTime->u8Second); + } + + /* exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcAlarmTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcAlarmTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcAlarmTime->u8Minute)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcAlarmTime->u8Minute))); + } + DDL_ASSERT(IS_VALID_ALARM_WEEKDAY(pstcRtcAlarmTime->u8Weekday)); + + /* Configure alarm registers */ + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour); + } + M4_RTC->ALMMIN = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Minute); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour; + } + M4_RTC->ALMMIN = pstcRtcAlarmTime->u8Minute; + } + M4_RTC->ALMWEEK = pstcRtcAlarmTime->u8Weekday; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Get RTC date and time register */ + pstcRtcAlarmTime->u8Weekday = (uint8_t)M4_RTC->ALMWEEK; + pstcRtcAlarmTime->u8Minute = (uint8_t)M4_RTC->ALMMIN; + pstcRtcAlarmTime->u8Hour = (uint8_t)M4_RTC->ALMHOUR; + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if ((pstcRtcAlarmTime->u8Hour & RTC_HOUR12_AMPM_MASK) == RTC_HOUR12_AMPM_MASK) + { + pstcRtcAlarmTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcAlarmTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcAlarmTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcAlarmTime->u8Hour = BCD2DEC(pstcRtcAlarmTime->u8Hour); + pstcRtcAlarmTime->u8Minute = BCD2DEC(pstcRtcAlarmTime->u8Minute); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC alarm function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC alarm function + ** \arg Enable Enable RTC alarm function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.ALMIE; + /* Disable alarm interrupt and clear alarm flag when START=1 and ALMIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.ALMIE = 0u; + } + M4_RTC->CR2_f.ALME = enNewSta; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR1_f.ALMFCLR = 0u; + M4_RTC->CR2_f.ALMIE = u8IntSta; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC interrupt request + ** + ** \param [in] enIrq RTC interrupt request type + ** \arg RtcIrqPeriod Period count interrupt request + ** \arg RtcIrqAlarm Alarm interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* enable/disable interrupt */ + switch (enIrq) + { + case RtcIrqPeriod: + M4_RTC->CR2_f.PRDIE = enNewSta; + break; + case RtcIrqAlarm: + M4_RTC->CR2_f.ALMIE = enNewSta; + break; + default: + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t RTC_GetAlarmFlag(void) +{ + return (en_flag_status_t)(M4_RTC->CR2_f.ALMF); +} + +/** + ******************************************************************************* + ** \brief Clear RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClearAlarmFlag(void) +{ + en_result_t enRet = Ok; + + M4_RTC->CR1_f.ALMFCLR = 0u; + + return enRet; +} + +//@} // RtcGroup + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_sdioc.c b/lib/hc32f460/driver/src/hc32f460_sdioc.c new file mode 100644 index 000000000000..5697202a2b75 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_sdioc.c @@ -0,0 +1,2217 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sdioc.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SDIOC internal data + ** + ******************************************************************************/ +typedef struct stc_sdioc_intern_data +{ + stc_sdioc_normal_irq_cb_t stcNormalIrqCb; ///< Normal irq callback function structure + + stc_sdioc_error_irq_cb_t stcErrorIrqCb; ///< Error irq callback function structure +} stc_sdioc_intern_data_t; + +/** + ******************************************************************************* + ** \brief SDIOC instance data + ** + ******************************************************************************/ +typedef struct stc_sdioc_instance_data +{ + const M4_SDIOC_TypeDef *SDIOCx; ///< pointer to registers of an instance + + stc_sdioc_intern_data_t stcInternData; ///< module internal data of instance +} stc_sdioc_instance_data_t; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SDIOC(__SDIOCx__) \ +( (M4_SDIOC1 == (__SDIOCx__)) || \ + (M4_SDIOC2 == (__SDIOCx__))) + +/*!< Parameter valid check for SDIOC mode. */ +#define IS_VALID_SDIOC_MODE(x) \ +( (SdiocModeSD == (x)) || \ + (SdiocModeMMC == (x))) + +/*!< Parameter valid check for SDIOC Response Register. */ +#define IS_VALID_SDIOC_RESP(x) \ +( (SdiocRegResp01 == (x)) || \ + (SdiocRegResp23 == (x)) || \ + (SdiocRegResp45 == (x)) || \ + (SdiocRegResp67 == (x))) + +/*!< Parameter valid check for SDIOC bus width. */ +#define IS_VALID_SDIOC_BUS_WIDTH(x) \ +( (SdiocBusWidth1Bit == (x)) || \ + (SdiocBusWidth4Bit == (x)) || \ + (SdiocBusWidth8Bit == (x))) + +/*!< Parameter valid check for SDIOC speed mode. */ +#define IS_VALID_SDIOC_SPEED_MODE(x) \ +( (SdiocHighSpeedMode == (x)) || \ + (SdiocNormalSpeedMode == (x))) + +/*!< Parameter valid check for SDIOC Clock division. */ +#define IS_VALID_SDIOC_CLK_DIV(x) \ +( (SdiocClkDiv_1 == (x)) || \ + (SdiocClkDiv_2 == (x)) || \ + (SdiocClkDiv_4 == (x)) || \ + (SdiocClkDiv_8 == (x)) || \ + (SdiocClkDiv_16 == (x)) || \ + (SdiocClkDiv_32 == (x)) || \ + (SdiocClkDiv_64 == (x)) || \ + (SdiocClkDiv_128 == (x)) || \ + (SdiocClkDiv_256 == (x))) + +/*!< Parameter valid check for SDIOC command type. */ +#define IS_VALID_SDIOC_CMD_TYPE(x) \ +( (SdiocCmdAbort == (x)) || \ + (SdiocCmdResume == (x)) || \ + (SdiocCmdNormal == (x)) || \ + (SdiocCmdSuspend == (x))) + +/*!< Parameter valid check for SDIOC data transfer direction. */ +#define IS_VALID_SDIOC_TRANSFER_DIR(x) \ +( (SdiocTransferToCard == (x)) || \ + (SdiocTransferToHost == (x))) + +/*!< Parameter valid check for SDIOC software reset type. */ +#define IS_VALID_SDIOC_SWRESETTYPE(x) \ +( (SdiocSwResetAll == (x)) || \ + (SdiocSwResetCmdLine == (x)) || \ + (SdiocSwResetDatLine == (x))) + +/*!< Parameter valid check for SDIOC data transfer mode. */ +#define IS_VALID_SDIOC_TRANSFER_MODE(x) \ +( (SdiocTransferSingle == (x)) || \ + (SdiocTransferInfinite == (x)) || \ + (SdiocTransferMultiple == (x)) || \ + (SdiocTransferStopMultiple == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_DATA_TIMEOUT(x) \ +( (SdiocDtoSdclk_2_13 == (x)) || \ + (SdiocDtoSdclk_2_14 == (x)) || \ + (SdiocDtoSdclk_2_15 == (x)) || \ + (SdiocDtoSdclk_2_16 == (x)) || \ + (SdiocDtoSdclk_2_17 == (x)) || \ + (SdiocDtoSdclk_2_18 == (x)) || \ + (SdiocDtoSdclk_2_19 == (x)) || \ + (SdiocDtoSdclk_2_20 == (x)) || \ + (SdiocDtoSdclk_2_21 == (x)) || \ + (SdiocDtoSdclk_2_22 == (x)) || \ + (SdiocDtoSdclk_2_23 == (x)) || \ + (SdiocDtoSdclk_2_24 == (x)) || \ + (SdiocDtoSdclk_2_25 == (x)) || \ + (SdiocDtoSdclk_2_26 == (x)) || \ + (SdiocDtoSdclk_2_27 == (x))) + +/*!< Parameter valid check for SDIOC Response type name. */ +#define IS_VALID_SDIOC_RESP_TYPE_NAME(x) \ +( (SdiocCmdRspR1 == (x)) || \ + (SdiocCmdRspR1b == (x)) || \ + (SdiocCmdRspR2 == (x)) || \ + (SdiocCmdRspR3 == (x)) || \ + (SdiocCmdRspR4 == (x)) || \ + (SdiocCmdRspR5 == (x)) || \ + (SdiocCmdRspR5b == (x)) || \ + (SdiocCmdRspR6 == (x)) || \ + (SdiocCmdRspR7 == (x)) || \ + (SdiocCmdNoRsp == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_HOST_STATUS(x) \ +( (SdiocCmdPinLvl == (x)) || \ + (SdiocData0PinLvl == (x)) || \ + (SdiocData1PinLvl == (x)) || \ + (SdiocData2PinLvl == (x)) || \ + (SdiocData3PinLvl == (x)) || \ + (SdiocCardInserted == (x)) || \ + (SdiocDataLineActive == (x)) || \ + (SdiocCardStateStable == (x)) || \ + (SdiocBufferReadEnble == (x)) || \ + (SdiocBufferWriteEnble == (x)) || \ + (SdiocCardDetectPinLvl == (x)) || \ + (SdiocCommandInhibitCmd == (x)) || \ + (SdiocWriteProtectPinLvl == (x)) || \ + (SdiocCommandInhibitData == (x)) || \ + (SdiocReadTransferActive == (x)) || \ + (SdiocWriteTransferActive == (x))) + +/*!< Parameter valid check for SDIOC normal interrupt. */ +#define IS_VALID_SDIOC_NOR_INT(x) \ +( (SdiocCardInt == (x)) || \ + (SdiocErrorInt == (x)) || \ + (SdiocCardRemoval == (x)) || \ + (SdiocBlockGapEvent == (x)) || \ + (SdiocCardInsertedInt == (x)) || \ + (SdiocCommandComplete == (x)) || \ + (SdiocBufferReadReady == (x)) || \ + (SdiocBufferWriteReady == (x)) || \ + (SdiocTransferComplete == (x))) + +/*!< Parameter valid check for SDIOC error interrupt. */ +#define IS_VALID_SDIOC_ERR_INT(x) \ +( (SdiocCmdCrcErr == (x)) || \ + (SdiocDataCrcErr == (x)) || \ + (SdiocCmdIndexErr == (x)) || \ + (SdiocCmdEndBitErr == (x)) || \ + (SdiocAutoCmd12Err == (x)) || \ + (SdiocCmdTimeoutErr == (x)) || \ + (SdiocDataEndBitErr == (x)) || \ + (SdiocDataTimeoutErr == (x))) + +/*!< Parameter valid check for SDIOC auto CMD12 error status. */ +#define IS_VALID_SDIOC_AUTOCMD_ERR(x) \ +( (SdiocCmdNotIssuedErr == (x)) || \ + (SdiocAutoCmd12CrcErr == (x)) || \ + (SdiocAutoCmd12Timeout == (x)) || \ + (SdiocAutoCmd12IndexErr == (x)) || \ + (SdiocAutoCmd12EndBitErr == (x)) || \ + (SdiocAutoCmd12NotExecuted == (x))) + +/*!< Parameter valid check for SDIOC detect card signal. */ +#define IS_VALID_SDIOC_DETECT_SIG(x) \ +( (SdiocSdcdPinLevel == (x)) || \ + (SdiocCardDetectTestLevel == (x))) + +/*!< Parameter valid check for SDIOC data block count value. */ +#define IS_VALID_SDIOC_BLKCNT(x) ((x) != 0u) + +/*!< Parameter valid check for SDIOC data block size value. */ +#define IS_VALID_SDIOC_BLKSIZE(x) (!((x) & 0xF000ul)) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_SDIOC_CMD_VAL(x) (!(0xC0u & (x))) + +/*!< Parameter valid check for buffer address. */ +#define IS_VALID_TRANSFER_BUF_ALIGN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_TRANSFER_BUF_LEN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< SDIOC unit max count value. */ +#define SDIOC_UNIT_MAX_CNT (ARRAY_SZ(m_astcSdiocInstanceDataLut)) + +/*!< SDIOC default sdclk frequency. */ +#define SDIOC_SDCLK_400K (400000ul) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->ARG0))) +#define SDIOC_BUF01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->BUF0))) +#define SDIOC_RESPx(__SDIOCx__, RESP_REG) ((uint32_t)(&((__SDIOCx__)->RESP0)) + (uint32_t)(RESP_REG)) + +/* SDIOC buffer align size */ +#define SDIOC_BUF_ALIGN_SIZE (4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32SdiocClkFreq); +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get SDIOC clock division. + ** + ** \param [in] u32Exclk Exclk frequency + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** \retval SdiocClkDiv_256 EXCLK/256 + ** + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32ClkFreq) +{ + uint32_t u32SdClkDiv = 0ul; + en_sdioc_clk_div_t enClockDiv = SdiocClkDiv_256; + + if(0ul != u32ClkFreq) + { + u32SdClkDiv = u32Exclk / u32ClkFreq; + if (u32Exclk % u32ClkFreq) + { + u32SdClkDiv++; + } + + if ((128ul < u32SdClkDiv) && (u32SdClkDiv <= 256ul)) + { + enClockDiv = SdiocClkDiv_256; + } + else if ((64ul < u32SdClkDiv) && (u32SdClkDiv <= 128ul)) + { + enClockDiv = SdiocClkDiv_128; + } + else if ((32ul < u32SdClkDiv) && (u32SdClkDiv <= 64ul)) + { + enClockDiv = SdiocClkDiv_64; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((8ul < u32SdClkDiv) && (u32SdClkDiv <= 16ul)) + { + enClockDiv = SdiocClkDiv_16; + } + else if ((4ul < u32SdClkDiv) && (u32SdClkDiv <= 8ul)) + { + enClockDiv = SdiocClkDiv_8; + } + else if ((2ul < u32SdClkDiv) && (u32SdClkDiv <= 4ul)) + { + enClockDiv = SdiocClkDiv_4; + } + else if ((1ul < u32SdClkDiv) && (u32SdClkDiv <= 2ul)) + { + enClockDiv = SdiocClkDiv_2; + } + else + { + enClockDiv = SdiocClkDiv_1; + } + } + + return enClockDiv; +} + +/** + ******************************************************************************* + ** \brief Return the internal data for a certain SDIOC instance. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx) +{ + uint8_t i; + stc_sdioc_intern_data_t *pstcInternData = NULL; + static stc_sdioc_instance_data_t m_astcSdiocInstanceDataLut[2]; + + m_astcSdiocInstanceDataLut[0].SDIOCx = M4_SDIOC1; + m_astcSdiocInstanceDataLut[1].SDIOCx = M4_SDIOC2; + + if (NULL != SDIOCx) + { + for (i = 0u; i < SDIOC_UNIT_MAX_CNT; i++) + { + if (SDIOCx == m_astcSdiocInstanceDataLut[i].SDIOCx) + { + pstcInternData = &m_astcSdiocInstanceDataLut[i].stcInternData; + break; + } + } + } + + return pstcInternData; +} + +/** + ******************************************************************************* + ** \brief SDIOC instance interrupt service routine + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval None + ** + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx) +{ + stc_sdioc_intern_data_t *pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + + /* Check for NULL pointer */ + if (NULL != pstcSdiocInternData) + { + /**************** Normal interrupt handler ****************/ + if (1u == SDIOCx->NORINTST_f.CC) /* Command complete */ + { + SDIOCx->NORINTST_f.CC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.TC) /* Transfer complete */ + { + SDIOCx->NORINTST_f.TC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BGE) /* Block gap event */ + { + SDIOCx->NORINTST_f.BGE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BWR) /* Buffer write ready */ + { + SDIOCx->NORINTST_f.BWR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BRR) /* Buffer read ready */ + { + SDIOCx->NORINTST_f.BRR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CIST) /* Card insertion */ + { + SDIOCx->NORINTST_f.CIST = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CRM) /* Card removal */ + { + SDIOCx->NORINTST_f.CRM = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CINT) /* Card interrupt */ + { + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb(); + } + } + + /**************** Error interrupt handler ****************/ + if (1u == SDIOCx->ERRINTST_f.CTOE) /* Command timeout error */ + { + SDIOCx->ERRINTST_f.CTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CCE) /* Command CRC error */ + { + SDIOCx->ERRINTST_f.CCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CEBE) /* Command end bit error */ + { + SDIOCx->ERRINTST_f.CEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CIE) /* Command index error */ + { + SDIOCx->ERRINTST_f.CIE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DTOE) /* Data timeout error */ + { + SDIOCx->ERRINTST_f.DTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DEBE) /* Data end bit error */ + { + SDIOCx->ERRINTST_f.DEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DCE) /* Data CRC error */ + { + SDIOCx->ERRINTST_f.DCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.ACE) /* Auto CMD12 error */ + { + SDIOCx->ERRINTST_f.ACE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb(); + } + } + } +} + +/** + ******************************************************************************* + ** \brief Initializes a SDIOC. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcInitCfg Pointer to SDIOC configure structure + ** \arg This parameter detail refer @ref stc_sdioc_init_t + ** + ** \retval Ok SDIOC initialized normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg) +{ + __IO uint32_t i = 0ul; + uint32_t u32Exclk = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.FS = SdiocGetClkDiv(u32Exclk, SdiocClk400K); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + SDIOCx->CLKCON_f.ICE = (uint16_t)1u; + SDIOCx->PWRCON_f.PWON = (uint8_t)1u; /* Power on */ + + /* Enable all status */ + SDIOCx->ERRINTST = (uint16_t)0x017Fu; /* Clear Error interrupt status */ + SDIOCx->ERRINTSTEN = (uint16_t)0x017Fu; /* Enable Error interrupt status */ + SDIOCx->NORINTST = (uint16_t)0x00F7u; /* Clear Normal interrupt status */ + SDIOCx->NORINTSTEN = (uint16_t)0x01F7u; /* Enable Normal interrupt status */ + + /* Enable normal interrupt signal */ + if (NULL != pstcInitCfg) + { + if (NULL != pstcInitCfg->pstcNormalIrqEn) + { + SDIOCx->NORINTSGEN = pstcInitCfg->pstcNormalIrqEn->u16NormalIntsgEn; + } + + /* Set normal interrupt callback functions */ + if (NULL != pstcInitCfg->pstcNormalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCommandCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnTransferCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBlockGapIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferWriteReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferReadReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardInsertIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardRemovalIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardIrqCb; + } + + /* Enable error interrupt signal */ + if (NULL != pstcInitCfg->pstcErrorIrqEn) + { + SDIOCx->ERRINTSGEN = pstcInitCfg->pstcErrorIrqEn->u16ErrorIntsgEn; + } + + /* Set error interrupt callback functions */ + if (NULL != pstcInitCfg->pstcErrorIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdIndexErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnAutoCmdErrIrqCb; + } + } + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified SDIOC unit. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorTimeout SDIOCx reset timeout. + ** \retval ErrorInvalidParameter SDIOCx is invalid. + ** + ******************************************************************************/ +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Set normal interrupt callback functions */ + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = NULL; + + /* Set error interrupt callback functions */ + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = NULL; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + * @brief Set SDIOC mode. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enMode SDIOCx mode + * @arg SdiocModeSD: SD mode + * @arg SdiocModeMMC: MMC mode + */ +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_MODE(enMode)); + + if (M4_SDIOC1 == SDIOCx) + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC1 = (uint32_t)enMode; + } + else + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC2 = (uint32_t)enMode; + } +} + +/** + ******************************************************************************* + ** \brief Send SD command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcCmdCfg Pointer to command transfer configuration structure. + ** \arg This parameter detail refer @ref stc_sdioc_cmd_cfg_t + ** + ** \retval Ok Command sent normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcCmdCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg) +{ + uint32_t u32Addr; + stc_sdioc_cmd_field_t stcCmdField; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for NULL pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcCmdCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CMD_VAL(pstcCmdCfg->u8CmdIndex)); + DDL_ASSERT(IS_VALID_SDIOC_CMD_TYPE(pstcCmdCfg->enCmdType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCmdCfg->enDataPresentEnable)); + DDL_ASSERT(IS_VALID_SDIOC_RESP_TYPE_NAME(pstcCmdCfg->enRspIndex)); + + enRet = Ok; + switch (pstcCmdCfg->enRspIndex) + { + case SdiocCmdNoRsp: + stcCmdField.RESTYP = SdiocResponseNoneBit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR2: + stcCmdField.RESTYP = SdiocResponse136Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR3: + case SdiocCmdRspR4: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR1: + case SdiocCmdRspR5: + case SdiocCmdRspR6: + case SdiocCmdRspR7: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + case SdiocCmdRspR1b: + case SdiocCmdRspR5b: + stcCmdField.RESTYP = SdiocResponse48BitCheckBusy; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcCmdField.RESERVED2 = (uint16_t)0u; + stcCmdField.TYP = (uint16_t)pstcCmdCfg->enCmdType; + stcCmdField.IDX = (uint16_t)pstcCmdCfg->u8CmdIndex; + stcCmdField.DAT = (uint16_t)(pstcCmdCfg->enDataPresentEnable); + + u32Addr = SDIOC_ARG01(SDIOCx); + *(__IO uint32_t *)u32Addr = pstcCmdCfg->u32Argument; + + u32Addr = (uint32_t)&stcCmdField; + SDIOCx->CMD = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the response received from the card for the last command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enRespReg Response Specifies the SDIOC response register. + ** \arg SdiocRegResp01 Response0 and Response1 Register + ** \arg SdiocRegResp23 Response2 and Response3 Register + ** \arg SdiocRegResp45 Response4 and Response5 Register + ** \arg SdiocRegResp67 Response6 and Response7 Register + ** + ** \retval The Corresponding response register value + ** + ******************************************************************************/ +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_RESP(enRespReg)); + + return *(__IO uint32_t *)SDIOC_RESPx(SDIOCx, enRespReg) ; +} + +/** + ******************************************************************************* + ** \brief Read data from SDIOCx data buffer + ** + ** This function reads 32-bit data from data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will store SDIOC_BUFFER data + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is read normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu32Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul;; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = *SDIO_BUF_REG; + au8Data[i++] = (uint8_t)((u32Temp >> 0ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 8ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 16ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 24ul) & 0x000000FF); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write data to SDIOCx data buffer + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will be wrote to SDIOC_BUFFER + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is written normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu8Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = (((uint32_t)au8Data[i++]) << 0ul) & 0x000000FFul; + u32Temp += (((uint32_t)au8Data[i++]) << 8ul) & 0x0000FF00ul; + u32Temp += (((uint32_t)au8Data[i++]) << 16ul) & 0x00FF0000ul; + u32Temp += (((uint32_t)au8Data[i++]) << 24ul) & 0xFF000000ul; + + *SDIO_BUF_REG = u32Temp; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure SDIOCx data parameters + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcDataCfg Pointer to SDIOC data transfer configuration structure + ** \arg This parameter detail refer @ref stc_sdioc_data_cfg_t + ** + ** \retval Ok configure normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcDataCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg) +{ + uint16_t u16BlkCnt = (uint16_t)0; + uint32_t u32Addr; + stc_sdioc_transmode_field_t stcTransModeField = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pstcDataCfg pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcDataCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BLKCNT(pstcDataCfg->u16BlkCnt)); + DDL_ASSERT(IS_VALID_SDIOC_BLKSIZE(pstcDataCfg->u16BlkSize)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDataCfg->enAutoCmd12Enable)); + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(pstcDataCfg->enDataTimeOut)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_DIR(pstcDataCfg->enTransferDir)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_MODE(pstcDataCfg->enTransferMode)); + + enRet = Ok; + + switch (pstcDataCfg->enTransferMode) + { + case SdiocTransferSingle: + stcTransModeField.MULB = 0u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferInfinite: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferMultiple: + u16BlkCnt = pstcDataCfg->u16BlkCnt; + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + case SdiocTransferStopMultiple: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcTransModeField.RESERVED0 = (uint16_t)0u; + stcTransModeField.DDIR = (uint16_t)(pstcDataCfg->enTransferDir); + stcTransModeField.ATCEN = (uint16_t)(pstcDataCfg->enAutoCmd12Enable); + + /* Set the SDIOC Data Transfer Timeout value */ + SDIOCx->TOUTCON = (uint8_t)(pstcDataCfg->enDataTimeOut); + /* Set the SDIOC Block Count value */ + SDIOCx->BLKCNT = u16BlkCnt; + /* Set the SDIOC Block Size value */ + SDIOCx->BLKSIZE = pstcDataCfg->u16BlkSize; + /* Set the SDIOC Data Transfer Mode */ + u32Addr = (uint32_t)&stcTransModeField; + SDIOCx->TRANSMODE = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable SDCLK output + ** + ** SD host drives SDCLK line. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd The SDCLK functional state command + ** \arg Enable Enable SDCLK function + ** \arg Disable Disable SDCLK function + ** + ** \retval Ok SDCLK output of SDIOCx enabled normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + SDIOCx->CLKCON_f.CE = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the clock division of SD clock + ** + ** This function changes the SD clock division. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enClkDiv SDIOC clock division value + ** \arg SdiocClkDiv_1 EXCLK/1 + ** \arg SdiocClkDiv_2 EXCLK/2 + ** \arg SdiocClkDiv_4 EXCLK/4 + ** \arg SdiocClkDiv_8 EXCLK/8 + ** \arg SdiocClkDiv_16 EXCLK/16 + ** \arg SdiocClkDiv_32 EXCLK/32 + ** \arg SdiocClkDiv_64 EXCLK/64 + ** \arg SdiocClkDiv_128 EXCLK/128 + ** \arg SdiocClkDiv_256 EXCLK/256 + ** + ** \retval Ok SDIOC clock division is changed normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CLK_DIV(enClkDiv)); + + /* Set clock division */ + SDIOCx->CLKCON_f.FS = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** + ******************************************************************************/ +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((en_sdioc_clk_div_t)SDIOCx->CLKCON_f.FS); +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq) +{ + uint32_t u32Exclk = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.CE = (uint16_t)0u; + SDIOCx->CLKCON_f.FS = (uint16_t)SdiocGetClkDiv(u32Exclk, u32ClkFreq); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the bus width of SD Bus + ** + ** This function changes the SD bus width. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enBusWidth Bus width + ** \arg SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \arg SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \arg SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ** \retval Ok Bus width is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enBusWidth is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BUS_WIDTH(enBusWidth)); + + enRet = Ok; + + switch (enBusWidth) + { + case SdiocBusWidth1Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 0u; + break; + case SdiocBusWidth4Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 1u; + break; + case SdiocBusWidth8Bit: + SDIOCx->HOSTCON_f.EXDW = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus width of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \retval SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \retval SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ******************************************************************************/ +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx) +{ + en_sdioc_bus_width_t enBusWidth = SdiocBusWidth4Bit; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + if (0u == SDIOCx->HOSTCON_f.EXDW) + { + if (0u == SDIOCx->HOSTCON_f.DW) + { + enBusWidth = SdiocBusWidth1Bit; + } + } + else + { + enBusWidth = SdiocBusWidth8Bit; + } + + return enBusWidth; +} + +/** + ******************************************************************************* + ** \brief Set the bus speed mode of SD Bus + ** + ** This function changes the SD bus speed mode. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSpeedMode Speed mode + ** \arg SdiocHighSpeedMode High speed mode + ** \arg SdiocNormalSpeedMode Normal speed mode + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SPEED_MODE(enSpeedMode)); + + /* Set high speed mode */ + SDIOCx->HOSTCON_f.HSEN = ((SdiocHighSpeedMode == enSpeedMode) ? 1u : 0u); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus speed mode of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocHighSpeedMode High speed mode + ** \retval SdiocNormalSpeedMode Normal speed mode + ** + ******************************************************************************/ +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((SDIOCx->HOSTCON_f.HSEN) ? SdiocHighSpeedMode : SdiocNormalSpeedMode); +} + +/** + ******************************************************************************* + ** \brief Set data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enTimeout Data timeout count value + ** \arg SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \arg SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \arg SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \arg SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \arg SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \arg SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \arg SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \arg SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \arg SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \arg SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \arg SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \arg SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \arg SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \arg SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \arg SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(enTimeout)); + + /* Set data timeout */ + SDIOCx->TOUTCON_f.DTO = (uint8_t)enTimeout; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \retval SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \retval SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \retval SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \retval SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \retval SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \retval SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \retval SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \retval SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \retval SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \retval SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \retval SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \retval SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \retval SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \retval SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ******************************************************************************/ +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_sdioc_data_timeout_t)(SDIOCx->TOUTCON_f.DTO); +} + +/** + ******************************************************************************* + ** \brief Set the card detect signal + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enDetectSignal Card detect signal + ** \arg SdiocSdcdPinLevel SDCD# is selected (for normal use) + ** \arg SdiocCardDetectTestLevel The Card Detect Test Level is selected(for test purpose) + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DETECT_SIG(enDetectSignal)); + SDIOCx->HOSTCON_f.CDSS = (uint8_t)enDetectSignal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get card inserted or not. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Set Card Inserted + ** \retval Reset No Card + ** + ** \note This bit is enabled while the Card Detect Signal Selection is set to 1 + ** and it indicates card inserted or not. + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_flag_status_t)(SDIOCx->HOSTCON_f.CDTL); +} + +/** + ******************************************************************************* + ** \brief Power on SD bus power + ** + ** This function starts power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power on normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Power off SD bus power + ** + ** This function stops power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power off normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Stop At Block Gap Request during block gap + ** + ** This function is used to stop data trasnfer of multi-block transfer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Stop At Block Gap Request functional state + ** \arg Enable Enable the function of Stop At Block Gap Request + ** \arg Disable Disable the function of Stop At Block Gap Request + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.SABGR = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Restart data transfer + ** + ** This function is used to restart data transfer when transfer is pending + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->BLKGPCON_f.CR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Read Wait Control + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Read Wait Control functional state + ** \arg Enable Enable the Read Wait Control function + ** \arg Disable Disable the Read Wait Control function + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.RWC = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Interrupt At Block Gap + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Interrupt At Block Gap functional state + ** \arg Enable Enable the function of Interrupt At Block Gap + ** \arg Disable Disable the function of Interrupt At Block Gap + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.IABG = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Generate software reset to SD card + ** + ** This function generates software reset all command to SD card + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSwResetType Software reset type + ** \arg SdiocSwResetAll This reset affects the entire Host Controller except for the card detection circuit. + ** \arg SdiocSwResetCmdLine Only part of command circuit is reset. + ** \arg SdiocSwResetDataLine Only part of data circuit is reset. + ** + ** \retval Ok Software reset is done normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enSwResetType is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SWRESETTYPE(enSwResetType)); + + enRet = Ok; + switch (enSwResetType) + { + case SdiocSwResetAll: + SDIOCx->SFTRST_f.RSTA = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetCmdLine: + SDIOCx->SFTRST_f.RSTC = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTC) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetDatLine: + SDIOCx->SFTRST_f.RSTD = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTD) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (i > u32Cnt) + { + enRet = ErrorTimeout; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of SDIOC host controller + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enHostStatus SDIOC host status + ** \arg SdiocCommandInhibitCmd Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + ** \arg SdiocCommandInhibitData Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + ** \arg SdiocDataLineActive 1: DAT Line Active; 0: DAT Line Inactive + ** \arg SdiocWriteTransferActive Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocReadTransferActive Read Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocBufferWriteEnble 1: Write enable; 0: Write Disable + ** \arg SdiocBufferReadEnble 1: Read enable; 0: Read Disable + ** \arg SdiocCardInserted 1: Card Inserted; 0: Reset or Debouncing or No Card + ** \arg SdiocCardStateStable 1: No Card or Inserted; 0: Reset or Debouncing + ** \arg SdiocCardDetectPinLvl 1: Card present; 0: No card present + ** \arg SdiocWriteProtectPinLvl 1: Write enabled; 0: Write protected + ** \arg SdiocData0PinLvl 1: DAT0 line signal level high; 0: DAT0 line signal level low + ** \arg SdiocData1PinLvl 1: DAT1 line signal level high; 0: DAT1 line signal level low + ** \arg SdiocData2PinLvl 1: DAT2 line signal level high; 0: DAT2 line signal level low + ** \arg SdiocData3PinLvl 1: DAT3 line signal level high; 0: DAT3 line signal level low + ** \arg SdiocCmdPinLvl 1: CMD line signal level high; 0: CMD line signal level low + ** + ** \retval Set The specified status is set + ** \retval Reset The specified status is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_HOST_STATUS(enHostStatus)); + + return ((SDIOCx->PSTAT & ((uint32_t)enHostStatus)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the specified signal of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt signal functional state + ** \arg Enable Enable the specified signal of SD normal interrupt + ** \arg Disable Disable the specified signal of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSGEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSGEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt status functional state + ** \arg Enable Enable the specified status of SD normal interrupt + ** \arg Disable Disable the specified status of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSTEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSTEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + return ((SDIOCx->NORINTST & ((uint16_t)enNorInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + SDIOCx->NORINTST = (uint16_t)enNorInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the signal of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt signal functional state + ** \arg Enable Enable the specified signal of SD error interrupt + ** \arg Disable Disable the specified signal of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSGEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSGEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt status functional state + ** \arg Enable Enable the specified status of SD error interrupt + ** \arg Disable Disable the specified status of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSTEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSTEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + + return ((SDIOCx->ERRINTST & ((uint16_t)enErrInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->ERRINTST = (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Force the specified error interrupt flag + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->FEE |= (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error status selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Set The specified status flag is set + ** \retval Reset The specified status flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + + return ((SDIOCx->ATCERRST & ((uint16_t)enAutoCmdErr)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Force the specified auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + SDIOCx->FEA |= (uint16_t)enAutoCmdErr; + enRet = Ok; + } + + return enRet; +} + +//@} // SdiocGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_spi.c b/lib/hc32f460/driver/src/hc32f460_spi.c new file mode 100644 index 000000000000..f851709834fa --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_spi.c @@ -0,0 +1,1133 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.c + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_spi.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup SpiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for SPI unit */ +#define IS_VALID_SPI_UNIT(x) \ +( (M4_SPI1 == (x)) || \ + (M4_SPI2 == (x)) || \ + (M4_SPI3 == (x)) || \ + (M4_SPI4 == (x))) + +/*!< Parameter valid check for SS setup delay option */ +#define IS_VALID_SS_SETUP_DELAY_OPTION(x) \ +( (SpiSsSetupDelayTypicalSck1 == (x)) || \ + (SpiSsSetupDelayCustomValue == (x))) + +/*!< Parameter valid check for SS setup delay time */ +#define IS_VALID_SS_SETUP_DELAY_TIME(x) \ +( (SpiSsSetupDelaySck1 == (x)) || \ + (SpiSsSetupDelaySck2 == (x)) || \ + (SpiSsSetupDelaySck3 == (x)) || \ + (SpiSsSetupDelaySck4 == (x)) || \ + (SpiSsSetupDelaySck5 == (x)) || \ + (SpiSsSetupDelaySck6 == (x)) || \ + (SpiSsSetupDelaySck7 == (x)) || \ + (SpiSsSetupDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay time */ +#define IS_VALID_SS_HOLD_DELAY_TIME(x) \ +( (SpiSsHoldDelaySck1 == (x)) || \ + (SpiSsHoldDelaySck2 == (x)) || \ + (SpiSsHoldDelaySck3 == (x)) || \ + (SpiSsHoldDelaySck4 == (x)) || \ + (SpiSsHoldDelaySck5 == (x)) || \ + (SpiSsHoldDelaySck6 == (x)) || \ + (SpiSsHoldDelaySck7 == (x)) || \ + (SpiSsHoldDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay option */ +#define IS_VALID_SS_HOLD_DELAY_OPTION(x) \ +( (SpiSsHoldDelayTypicalSck1 == (x)) || \ + (SpiSsHoldDelayCustomValue == (x))) + +/*!< Parameter valid check for SS interval time option */ +#define IS_VALID_SS_INTERVAL_TIME_OPTION(x) \ +( (SpiSsIntervalTypicalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalCustomValue == (x))) + +/*!< Parameter valid check for SS interval time */ +#define IS_VALID_SS_INTERVAL_TIME(x) \ +( (SpiSsIntervalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalSck2PlusPck2 == (x)) || \ + (SpiSsIntervalSck3PlusPck2 == (x)) || \ + (SpiSsIntervalSck4PlusPck2 == (x)) || \ + (SpiSsIntervalSck5PlusPck2 == (x)) || \ + (SpiSsIntervalSck6PlusPck2 == (x)) || \ + (SpiSsIntervalSck7PlusPck2 == (x)) || \ + (SpiSsIntervalSck8PlusPck2 == (x))) + +/*!< Parameter valid check for SS valid channel select */ +#define IS_VALID_SS_VALID_CHANNEL(x) \ +( (SpiSsValidChannel0 == (x)) || \ + (SpiSsValidChannel1 == (x)) || \ + (SpiSsValidChannel2 == (x)) || \ + (SpiSsValidChannel3 == (x))) + +/*!< Parameter valid check for SS polarity */ +#define IS_VALID_SS_POLARITY(x) \ +( (SpiSsLowValid == (x)) || \ + (SpiSsHighValid == (x))) + +/*!< Parameter valid check for read data register object */ +#define IS_VALID_READ_DATA_REG_OBJECT(x) \ +( (SpiReadReceiverBuffer == (x)) || \ + (SpiReadSendBuffer == (x))) + +/*!< Parameter valid check for SCK polarity */ +#define IS_VALID_SCK_POLARITY(x) \ +( (SpiSckIdleLevelLow == (x)) || \ + (SpiSckIdleLevelHigh == (x))) + +/*!< Parameter valid check for SCK phase */ +#define IS_VALID_SCK_PHASE(x) \ +( (SpiSckOddSampleEvenChange == (x)) || \ + (SpiSckOddChangeEvenSample == (x))) + +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( (SpiClkDiv2 == (x)) || \ + (SpiClkDiv4 == (x)) || \ + (SpiClkDiv8 == (x)) || \ + (SpiClkDiv16 == (x)) || \ + (SpiClkDiv32 == (x)) || \ + (SpiClkDiv64 == (x)) || \ + (SpiClkDiv128 == (x)) || \ + (SpiClkDiv256 == (x))) + +/*!< Parameter valid check for data length */ +#define IS_VALID_DATA_LENGTH(x) \ +( (SpiDataLengthBit4 == (x)) || \ + (SpiDataLengthBit5 == (x)) || \ + (SpiDataLengthBit6 == (x)) || \ + (SpiDataLengthBit7 == (x)) || \ + (SpiDataLengthBit8 == (x)) || \ + (SpiDataLengthBit9 == (x)) || \ + (SpiDataLengthBit10 == (x)) || \ + (SpiDataLengthBit11 == (x)) || \ + (SpiDataLengthBit12 == (x)) || \ + (SpiDataLengthBit13 == (x)) || \ + (SpiDataLengthBit14 == (x)) || \ + (SpiDataLengthBit15 == (x)) || \ + (SpiDataLengthBit16 == (x)) || \ + (SpiDataLengthBit20 == (x)) || \ + (SpiDataLengthBit24 == (x)) || \ + (SpiDataLengthBit32 == (x))) + +/*!< Parameter valid check for first bit position */ +#define IS_VALID_FIRST_BIT_POSITION(x) \ +( (SpiFirstBitPositionMSB == (x)) || \ + (SpiFirstBitPositionLSB == (x))) + +/*!< Parameter valid check for frame number */ +#define IS_VALID_FRAME_NUMBER(x) \ +( (SpiFrameNumber1 == (x)) || \ + (SpiFrameNumber2 == (x)) || \ + (SpiFrameNumber3 == (x)) || \ + (SpiFrameNumber4 == (x))) + +/*!< Parameter valid check for work mode */ +#define IS_VALID_WORK_MODE(x) \ +( (SpiWorkMode4Line == (x)) || \ + (SpiWorkMode3Line == (x))) + +/*!< Parameter valid check for transmission mode */ +#define IS_VALID_COMM_MODE(x) \ +( (SpiTransFullDuplex == (x)) || \ + (SpiTransOnlySend == (x))) + +/*!< Parameter valid check for master slave mode */ +#define IS_VALID_MASTER_SLAVE_MODE(x) \ +( (SpiModeSlave == (x)) || \ + (SpiModeMaster == (x))) + +/*!< Parameter valid check for parity mode */ +#define IS_VALID_PARITY_MODE(x) \ +( (SpiParityEven == (x)) || \ + (SpiParityOdd == (x))) + +/*!< Parameter valid check for SS channel */ +#define IS_VALID_SS_CHANNEL(x) \ +( (SpiSsChannel0 == (x)) || \ + (SpiSsChannel1 == (x)) || \ + (SpiSsChannel2 == (x)) || \ + (SpiSsChannel3 == (x))) + +/*!< Parameter valid check for irq type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (SpiIrqIdle == (x)) || \ + (SpiIrqReceive == (x)) || \ + (SpiIrqSend == (x)) || \ + (SpiIrqError == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SpiFlagReceiveBufferFull == (x)) || \ + (SpiFlagSendBufferEmpty == (x)) || \ + (SpiFlagUnderloadError == (x)) || \ + (SpiFlagParityError == (x)) || \ + (SpiFlagModeFaultError == (x)) || \ + (SpiFlagSpiIdle == (x)) || \ + (SpiFlagOverloadError == (x))) + +/*!< Parameter valid check for clear flag type */ +#define IS_VALID_CLR_FLAG_TYPE(x) \ +( (SpiFlagReceiveBufferFull == (x)) || \ + (SpiFlagSendBufferEmpty == (x)) || \ + (SpiFlagUnderloadError == (x)) || \ + (SpiFlagParityError == (x)) || \ + (SpiFlagModeFaultError == (x)) || \ + (SpiFlagOverloadError == (x))) + +/*!< SPI registers reset value */ +#define SPI_REG_DR_RESET_VALUE 0x00000000ul +#define SPI_REG_CR1_RESET_VALUE 0x00000000ul +#define SPI_REG_CFG1_RESET_VALUE 0x00000010ul +#define SPI_REG_SR_RESET_VALUE 0x00000020ul +#define SPI_REG_CFG2_RESET_VALUE 0x0000031Dul + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t regTemp = 0ul; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + regTemp = SPIx->SR; + if (SPI_REG_SR_RESET_VALUE != regTemp) + { + SPIx->SR = SPI_REG_SR_RESET_VALUE; + } + SPIx->CR1 = SPI_REG_CR1_RESET_VALUE; + SPIx->DR = SPI_REG_DR_RESET_VALUE; + SPIx->CFG1 = SPI_REG_CFG1_RESET_VALUE; + SPIx->CFG2 = SPI_REG_CFG2_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] pstcSpiInitCfg Pointer to SPI init configuration + ** \arg See the struct #stc_spi_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** - pstcSpiInitCfg == NULL + ** + ******************************************************************************/ +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if((IS_VALID_SPI_UNIT(SPIx)) && (NULL != pstcSpiInitCfg)) + { + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption)); + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime)); + DDL_ASSERT(IS_VALID_SS_VALID_CHANNEL(pstcSpiInitCfg->stcSsConfig.enSsValidBit)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs0Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs1Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs2Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs3Polarity)); + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(pstcSpiInitCfg->enReadBufferObject)); + DDL_ASSERT(IS_VALID_SCK_POLARITY(pstcSpiInitCfg->enSckPolarity)); + DDL_ASSERT(IS_VALID_SCK_PHASE(pstcSpiInitCfg->enSckPhase)); + DDL_ASSERT(IS_VALID_CLK_DIV(pstcSpiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_DATA_LENGTH(pstcSpiInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(pstcSpiInitCfg->enFirstBitPosition)); + DDL_ASSERT(IS_VALID_FRAME_NUMBER(pstcSpiInitCfg->enFrameNumber)); + DDL_ASSERT(IS_VALID_WORK_MODE(pstcSpiInitCfg->enWorkMode)); + DDL_ASSERT(IS_VALID_COMM_MODE(pstcSpiInitCfg->enTransMode)); + DDL_ASSERT(IS_VALID_MASTER_SLAVE_MODE(pstcSpiInitCfg->enMasterSlaveMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enCommAutoSuspendEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enModeFaultErrorDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParitySelfDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParityEn)); + DDL_ASSERT(IS_VALID_PARITY_MODE(pstcSpiInitCfg->enParity)); + + /* Master mode */ + if (SpiModeMaster == pstcSpiInitCfg->enMasterSlaveMode) + { + SPIx->CFG2_f.MSSIE = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption; + SPIx->CFG2_f.MSSDLE = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption; + SPIx->CFG2_f.MIDIE = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption; + SPIx->CFG1_f.MSSI = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime; + SPIx->CFG1_f.MSSDL = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime; + SPIx->CFG1_f.MIDI = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime; + } + else + { + SPIx->CFG2_f.MSSIE = SpiSsSetupDelayTypicalSck1; + SPIx->CFG2_f.MSSDLE = SpiSsHoldDelayTypicalSck1; + SPIx->CFG2_f.MIDIE = SpiSsIntervalTypicalSck1PlusPck2; + SPIx->CFG1_f.MSSI = SpiSsSetupDelaySck1; + SPIx->CFG1_f.MSSDL = SpiSsHoldDelaySck1; + SPIx->CFG1_f.MIDI = SpiSsIntervalSck1PlusPck2; + } + + /* 4 lines spi mode */ + if (SpiWorkMode4Line == pstcSpiInitCfg->enWorkMode) + { + SPIx->CFG2_f.SSA = pstcSpiInitCfg->stcSsConfig.enSsValidBit; + SPIx->CFG1_f.SS0PV = pstcSpiInitCfg->stcSsConfig.enSs0Polarity; + SPIx->CFG1_f.SS1PV = pstcSpiInitCfg->stcSsConfig.enSs1Polarity; + SPIx->CFG1_f.SS2PV = pstcSpiInitCfg->stcSsConfig.enSs2Polarity; + SPIx->CFG1_f.SS3PV = pstcSpiInitCfg->stcSsConfig.enSs3Polarity; + } + else + { + SPIx->CFG2_f.SSA = SpiSsValidChannel0; + SPIx->CFG1_f.SS0PV = SpiSsLowValid; + SPIx->CFG1_f.SS1PV = SpiSsLowValid; + SPIx->CFG1_f.SS2PV = SpiSsLowValid; + SPIx->CFG1_f.SS3PV = SpiSsLowValid; + } + + /* Configure communication config register 1 */ + SPIx->CFG1_f.SPRDTD = pstcSpiInitCfg->enReadBufferObject; + SPIx->CFG1_f.FTHLV = pstcSpiInitCfg->enFrameNumber; + + /* Configure communication config register 2 */ + SPIx->CFG2_f.LSBF = pstcSpiInitCfg->enFirstBitPosition; + SPIx->CFG2_f.DSIZE = pstcSpiInitCfg->enDataLength; + SPIx->CFG2_f.MBR = pstcSpiInitCfg->enClkDiv; + SPIx->CFG2_f.CPOL = pstcSpiInitCfg->enSckPolarity; + SPIx->CFG2_f.CPHA = pstcSpiInitCfg->enSckPhase; + + /* Configure control register */ + SPIx->CR1_f.SPIMDS = pstcSpiInitCfg->enWorkMode; + SPIx->CR1_f.TXMDS = pstcSpiInitCfg->enTransMode; + SPIx->CR1_f.MSTR = pstcSpiInitCfg->enMasterSlaveMode; + SPIx->CR1_f.CSUSPE = pstcSpiInitCfg->enCommAutoSuspendEn; + SPIx->CR1_f.MODFE = pstcSpiInitCfg->enModeFaultErrorDetectEn; + SPIx->CR1_f.PATE = pstcSpiInitCfg->enParitySelfDetectEn; + SPIx->CR1_f.PAE = pstcSpiInitCfg->enParityEn; + SPIx->CR1_f.PAOE = pstcSpiInitCfg->enParity; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI general loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable general loopback + ** \arg Enable Enable general loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK2 = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI reverse loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable reverse loopback + ** \arg Enable Enable reverse loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI working + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable SPI working + ** \arg Enable Enable SPI working + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPE = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u8Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u16Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u32Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI receive 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint8_t Receive data value + ** + ******************************************************************************/ +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint8_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint16_t Receive data value + ** + ******************************************************************************/ +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint16_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint32_t Receive data value + ** + ******************************************************************************/ +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint32_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI set SS channel valid level polarity + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \param [in] enPolarity SS channel valid level polarity + ** \arg SpiSsLowValid SS0~3 signal low level valid + ** \arg SpiSsHighValid SS0~3 signal high level valid + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SS_POLARITY(enPolarity)); + + switch (enChannel) + { + case SpiSsChannel0: + SPIx->CFG1_f.SS0PV = enPolarity; + break; + case SpiSsChannel1: + SPIx->CFG1_f.SS1PV = enPolarity; + break; + case SpiSsChannel2: + SPIx->CFG1_f.SS2PV = enPolarity; + break; + case SpiSsChannel3: + SPIx->CFG1_f.SS3PV = enPolarity; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set SS valid channel + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + + SPIx->CFG2_f.SSA = enChannel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set read data register object + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enObject Read data register object + ** \arg SpiReadReceiverBuffer Read receive buffer + ** \arg SpiReadSendBuffer Read send buffer(must be read when TDEF=1) + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(enObject)); + + SPIx->CFG1_f.SPRDTD = enObject; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set frame number + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFrameNum Once read or write frame number + ** \arg SpiFrameNumber1 1 frame data + ** \arg SpiFrameNumber2 2 frame data + ** \arg SpiFrameNumber3 3 frame data + ** \arg SpiFrameNumber4 4 frame data + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FRAME_NUMBER(enFrameNum)); + + SPIx->CFG1_f.FTHLV = enFrameNum; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set data length + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enDataLength Read or write data length + ** \arg SpiDataLengthBit4 4 bits + ** \arg SpiDataLengthBit5 5 bits + ** \arg SpiDataLengthBit6 6 bits + ** \arg SpiDataLengthBit7 7 bits + ** \arg SpiDataLengthBit8 8 bits + ** \arg SpiDataLengthBit9 9 bits + ** \arg SpiDataLengthBit10 10 bits + ** \arg SpiDataLengthBit11 11 bits + ** \arg SpiDataLengthBit12 12 bits + ** \arg SpiDataLengthBit13 13 bits + ** \arg SpiDataLengthBit14 14 bits + ** \arg SpiDataLengthBit15 15 bits + ** \arg SpiDataLengthBit16 16 bits + ** \arg SpiDataLengthBit20 20 bits + ** \arg SpiDataLengthBit24 24 bits + ** \arg SpiDataLengthBit32 32 bits + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_DATA_LENGTH(enDataLength)); + + SPIx->CFG2_f.DSIZE = enDataLength; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set first bit position + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enPosition First bit position + ** \arg SpiFirstBitPositionMSB Spi first bit to MSB + ** \arg SpiFirstBitPositionLSB Spi first bit to LSB + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(enPosition)); + + SPIx->CFG2_f.LSBF = enPosition; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set clock division + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enClkDiv Clock division + ** \arg SpiClkDiv2 Spi pclk1 division 2 + ** \arg SpiClkDiv4 Spi pclk1 division 4 + ** \arg SpiClkDiv8 Spi pclk1 division 8 + ** \arg SpiClkDiv16 Spi pclk1 division 16 + ** \arg SpiClkDiv32 Spi pclk1 division 32 + ** \arg SpiClkDiv64 Spi pclk1 division 64 + ** \arg SpiClkDiv128 Spi pclk1 division 128 + ** \arg SpiClkDiv256 Spi pclk1 division 256 + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + SPIx->CFG2_f.MBR = enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI interrupt request + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enIrq SPI interrupt request type + ** \arg SpiIrqIdle Spi idle interrupt request + ** \arg SpiIrqReceive Spi receive interrupt request + ** \arg SpiIrqSend Spi send interrupt request + ** \arg SpiIrqError Spi error interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case SpiIrqIdle: + SPIx->CR1_f.IDIE = enNewSta; + break; + case SpiIrqReceive: + SPIx->CR1_f.RXIE = enNewSta; + break; + case SpiIrqSend: + SPIx->CR1_f.TXIE = enNewSta; + break; + case SpiIrqError: + SPIx->CR1_f.EIE = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI idle flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if (IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + enFlagSta = (en_flag_status_t)SPIx->SR_f.RDFF; + break; + case SpiFlagSendBufferEmpty: + enFlagSta = (en_flag_status_t)SPIx->SR_f.TDEF; + break; + case SpiFlagUnderloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.UDRERF; + break; + case SpiFlagParityError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.PERF; + break; + case SpiFlagModeFaultError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.MODFERF; + break; + case SpiFlagSpiIdle: + enFlagSta = (en_flag_status_t)(bool)(!SPIx->SR_f.IDLNF); + break; + case SpiFlagOverloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.OVRERF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_CLR_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + SPIx->SR_f.RDFF = 0u; + break; + case SpiFlagSendBufferEmpty: + SPIx->SR_f.TDEF = 0u; + break; + case SpiFlagUnderloadError: + SPIx->SR_f.UDRERF = 0u; + break; + case SpiFlagParityError: + SPIx->SR_f.PERF = 0u; + break; + case SpiFlagModeFaultError: + SPIx->SR_f.MODFERF = 0u; + break; + case SpiFlagOverloadError: + SPIx->SR_f.OVRERF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +//@} // SpiGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_sram.c b/lib/hc32f460/driver/src/hc32f460_sram.c new file mode 100644 index 000000000000..b87e16d2e3b0 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_sram.c @@ -0,0 +1,282 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.c + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sram.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup SramGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ECC/Parity error handling. */ +#define IS_VALID_ERR_OP(x) \ +( ((x) == SramNmi) || \ + ((x) == SramReset)) + +/*! Parameter validity check for SRAM ECC mode */ +#define IS_VALID_ECC_MD(x) \ +( ((x) == EccMode0) || \ + ((x) == EccMode1) || \ + ((x) == EccMode2) || \ + ((x) == EccMode3)) + +/*! Parameter validity check for SRAM Index */ +#define IS_VALID_INDEX(x) \ +( ((x) == Sram12Idx) || \ + ((x) == Sram3Idx) || \ + ((x) == SramHsIdx) || \ + ((x) == SramRetIdx)) + +/*! Parameter validity check for SRAM R/W wait cycle */ +#define IS_VALID_WAIT_CYCLE(x) \ +( ((x) == SramCycle1) || \ + ((x) == SramCycle2) || \ + ((x) == SramCycle3) || \ + ((x) == SramCycle4) || \ + ((x) == SramCycle5) || \ + ((x) == SramCycle6) || \ + ((x) == SramCycle7) || \ + ((x) == SramCycle8)) + +/*! Parameter validity check for SRAM error status */ +#define IS_VALID_ERR(x) \ +( ((x) == Sram3EccErr1) || \ + ((x) == Sram3EccErr2) || \ + ((x) == Sram12ParityErr) || \ + ((x) == SramHSParityErr) || \ + ((x) == SramRetParityErr)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register disable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register disabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Disable(void) +{ + M4_SRAMC->WTPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register enable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register enabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Enable(void) +{ + M4_SRAMC->WTPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register disable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register disabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Disable(void) +{ + M4_SRAMC->CKPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register enable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register enabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Enable(void) +{ + M4_SRAMC->CKPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Set Corresponding error occurs + ** Reset Corresponding error not occurs + ** + ******************************************************************************/ +en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + if (true == !!(enSramErrStatus & M4_SRAMC->CKSR)) + { + return Set; + } + else + { + return Reset; + } +} + +/** + ******************************************************************************* + ** \brief Clear SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Ok Corresponding error flag be cleared + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + M4_SRAMC->CKSR |= enSramErrStatus; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM initialization + ** + ** \param [in] pstcSramConfig SRAM configure structure + ** + ** \retval Ok SRAM initialized + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig) +{ + uint8_t i = 0u; + uint8_t u8TmpIdx; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramRC)); + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramWC)); + DDL_ASSERT(IS_VALID_ECC_MD(pstcSramConfig->enSramEccMode)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramEccOp)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramPyOp)); + + u8TmpIdx = pstcSramConfig->u8SramIdx; + + if (0u == u8TmpIdx) + { + enRet = ErrorInvalidParameter; + } + else + { + SRAM_WT_Enable(); + SRAM_CK_Enable(); + for (i = 0u; i < 4u; i++) + { + if (true == (u8TmpIdx & 0x01u)) + { + M4_SRAMC->WTCR |= (pstcSramConfig->enSramRC | \ + (pstcSramConfig->enSramWC << 4ul)) << (i * 8ul); + } + u8TmpIdx >>= 1u; + } + /* SRAM3 ECC config */ + if (pstcSramConfig->u8SramIdx & Sram3Idx) + { + M4_SRAMC->CKCR_f.ECCMOD = pstcSramConfig->enSramEccMode; + M4_SRAMC->CKCR_f.ECCOAD = pstcSramConfig->enSramEccOp; + } + /* SRAM1/2/HS/Ret parity config */ + else + { + M4_SRAMC->CKCR_f.PYOAD = pstcSramConfig->enSramPyOp; + } + + SRAM_WT_Disable(); + SRAM_CK_Disable(); + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief SRAM de-initialization + ** + ** \param None + ** + ** \retval Ok SRAM de-initialized + ** + ******************************************************************************/ +en_result_t SRAM_DeInit(void) +{ + /* SRAM R/W wait register */ + M4_SRAMC->WTPR = 0x77ul; + M4_SRAMC->WTCR = 0ul; + M4_SRAMC->WTPR = 0x76ul; + + /* SRAM check register */ + M4_SRAMC->CKPR = 0x77ul; + M4_SRAMC->CKCR = 0ul; + M4_SRAMC->CKPR = 0x76ul; + + /* SRAM status register */ + M4_SRAMC->CKSR = 0x1Ful; + + return Ok; +} + +//@} // SramGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_swdt.c b/lib/hc32f460/driver/src/hc32f460_swdt.c new file mode 100644 index 000000000000..391193e3827e --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_swdt.c @@ -0,0 +1,166 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.c + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_swdt.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup SwdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SwdtFlagCountUnderflow == (x)) || \ + (SwdtFlagRefreshError == (x))) + +/*!< SWDT_RR register refresh key */ +#define SWDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define SWDT_REFRESH_END_KEY_ ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT refresh counter + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_SWDT->RR = SWDT_REFRESH_START_KEY; + M4_SWDT->RR = SWDT_REFRESH_END_KEY_; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SWDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t SWDT counter current count value + ** + ******************************************************************************/ +uint16_t SWDT_GetCountValue(void) +{ + return ((uint16_t)M4_SWDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.UDF; + break; + case SwdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + M4_SWDT->SR_f.UDF = 0u; + break; + case SwdtFlagRefreshError: + M4_SWDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // SwdtGroup + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer0.c b/lib/hc32f460/driver/src/hc32f460_timer0.c new file mode 100644 index 000000000000..7e3ef5688a6f --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer0.c @@ -0,0 +1,963 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.c + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer0.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer0Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_TMR01) || \ + ((x) == M4_TMR02)) + +/* Parameter validity check for channel. */ +#define IS_VALID_CHANNEL(x) \ +( ((x) == Tim0_ChannelA) || \ + ((x) == Tim0_ChannelB)) + +/* Parameter validity check for command. */ +#define IS_VALID_COMMAND(x) \ +( ((x) == Disable) || \ + ((x) == Enable)) + +/* Parameter validity check for timer0 function mode. */ +#define IS_VALID_FUNCTION(x) \ +( ((x) == Tim0_OutputCapare) || \ + ((x) == Tim0_InputCaptrue)) + +/* Parameter validity check for clock division. */ +#define IS_VALID_CLK_DIVISION(x) \ +( ((x) == Tim0_ClkDiv0) || \ + ((x) == Tim0_ClkDiv2) || \ + ((x) == Tim0_ClkDiv4) || \ + ((x) == Tim0_ClkDiv8) || \ + ((x) == Tim0_ClkDiv16) || \ + ((x) == Tim0_ClkDiv32) || \ + ((x) == Tim0_ClkDiv64) || \ + ((x) == Tim0_ClkDiv128) || \ + ((x) == Tim0_ClkDiv256) || \ + ((x) == Tim0_ClkDiv512) || \ + ((x) == Tim0_ClkDiv1024)) + +/* Parameter validity check for synchronous clock source. */ +#define IS_VALID_CLK_SYN_SRC(x) \ +( ((x) == Tim0_Pclk1) || \ + ((x) == Tim0_InsideHardTrig)) + +/* Parameter validity check for asynchronous clock source. */ +#define IS_VALID_CLK_ASYN_SRC(x) \ +( ((x) == Tim0_LRC) || \ + ((x) == Tim0_XTAL32)) + +/* Parameter validity check for counter clock mode. */ +#define IS_VALID_CLK_MODE(x) \ +( ((x) == Tim0_Sync) || \ + ((x) == Tim0_Async)) + +/* Parameter validity check for counter clock mode for M4_TMR01. */ +#define IS_VALID_CLK_MODE_UNIT01(x) \ +( (x) == Tim0_Async) + +/* Parameter validity check for external trigger event. */ +#define IS_VALID_TRIG_SRC_EVENT(x) \ +( ((x) <= EVT_PORT_EIRQ15) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW))) + +/* Parameter validity check for common trigger. */ +#define IS_VALID_TIM0_COM_TRIGGER(x) \ +( ((x) == Tim0ComTrigger_1) || \ + ((x) == Tim0ComTrigger_2) || \ + ((x) == Tim0ComTrigger_1_2)) + +/* Delay count for time out */ +#define TIMER0_TMOUT (0x5000ul) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get clock mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Tim0_Sync: Synchronous clock + ** \retval Tim0_Async: Asynchronous clock + ** + ******************************************************************************/ +static en_tim0_counter_mode_t TIMER0_GetClkMode(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_tim0_counter_mode_t enMode = Tim0_Sync; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSA; + break; + case Tim0_ChannelB: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSB; + break; + default: + break; + } + return enMode; +} + +/** + ******************************************************************************* + ** \brief Time delay for register write in asynchronous mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enIsPublicReg Enable for BCONR and STFLR register delay + ** + ** \retval None + ** + ******************************************************************************/ +static void AsyncDelay(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enIsPublicReg) +{ + en_functional_state_t enDelayEn = Disable; + en_tim0_counter_mode_t enModeA = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelA); + en_tim0_counter_mode_t enModeB = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelB); + + if(Enable == enIsPublicReg) + { + if((Tim0_Async == enModeA) || (Tim0_Async == enModeB)) + { + enDelayEn = Enable; + } + } + else + { + if(Tim0_Async == TIMER0_GetClkMode(pstcTim0Reg, enCh)) + { + enDelayEn = Enable; + } + } + + if(Enable == enDelayEn) + { + for(uint32_t i=0ul; iSTFLR_f.CMAF; + break; + case Tim0_ChannelB: + enFlag = (en_flag_status_t)pstcTim0Reg->STFLR_f.CMBF; + break; + default: + break; + } + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer0 status flag + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->STFLR_f.CMAF =0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMAF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->STFLR_f.CMBF = 0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMBF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Command the timer0 function + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CSTA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CSTB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select the timer0 function mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enFunc Timer0 function,Tim0_OutputCapare or Tim0_InputCapture + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_tim0_function_t enFunc) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(enFunc)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CAPMDA = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CAPMDB = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 interrupt function command + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.INTENA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.INTENB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CNTAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CNTBR)&0xFFFFu); + } + + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Write Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CNTAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CNTBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Base compare count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CMPAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CMPBR)&0xFFFFu); + } + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Wirte Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CMPAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CMPBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initialize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pstcBaseInit Timer0 function base parameter structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_base_init_t* pstcBaseInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + if (NULL != pstcBaseInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_CLK_DIVISION(pstcBaseInit->Tim0_ClockDivision)); + DDL_ASSERT(IS_VALID_CLK_SYN_SRC(pstcBaseInit->Tim0_SyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_ASYN_SRC(pstcBaseInit->Tim0_AsyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_MODE(pstcBaseInit->Tim0_CounterMode)); + + if((M4_TMR01 == pstcTim0Reg)&&(Tim0_ChannelA == enCh)) + { + DDL_ASSERT(IS_VALID_CLK_MODE_UNIT01(pstcBaseInit->Tim0_CounterMode)); + } + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + /* Clear current configurate CH */ + if(Tim0_ChannelA == enCh) + { + *(uint32_t *)&stcBconrTmp &= 0xFFFF0000ul; + } + else + { + *(uint32_t *)&stcBconrTmp &= 0x0000FFFFul; + } + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(*(uint32_t *)&stcBconrTmp != *(uint32_t *)&(pstcTim0Reg->BCONR_f)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + switch(enCh) + { + case Tim0_ChannelA: + + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKA = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKA = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVA = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPAR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSA = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + break; + + case Tim0_ChannelB: + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKB = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKB = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVB = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPBR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSB = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + + default: + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Ok Process finished. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR &= 0xFFFF0000ul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0x0000FFFFul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPAR = 0x0000FFFFul; + pstcTim0Reg->CNTAR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMAF =0u; + break; + + case Tim0_ChannelB: + pstcTim0Reg->BCONR &= 0x0000FFFFul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0xFFFF0000ul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPBR = 0x0000FFFFul; + pstcTim0Reg->CNTBR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMBF =0u; + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set external trigger source for Timer0 + ** + ** \param [in] enEvent External event source + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_SetTriggerSrc(en_event_src_t enEvent) +{ + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(enEvent)); + + M4_AOS->TMR0_HTSSR_f.TRGSEL = enEvent; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer0 common trigger. + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_tim0_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIM0_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR0_HTSSR |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR0_HTSSR &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Timer0 hardware trigger function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pStcInit Timer0 hareware trigger function structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_trigger_init_t* pStcInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + + if(NULL != pStcInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(pStcInit->Tim0_OCMode)); + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(pStcInit->Tim0_SelTrigSrc)); + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + + switch(enCh) + { + case Tim0_ChannelA: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDA = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPA = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEA = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAA = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPA = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + case Tim0_ChannelB: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDB = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPB = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEB = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAB = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPB = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + default: + break; + } + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /* Set trigger source*/ + M4_AOS->TMR0_HTSSR_f.TRGSEL = pStcInit->Tim0_SelTrigSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; + +} + +//@} // Timer0Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer4_cnt.c b/lib/hc32f460/driver/src/hc32f460_timer4_cnt.c new file mode 100644 index 000000000000..ac56c07158c7 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer4_cnt.c @@ -0,0 +1,838 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_cnt.c + ** + ** A detailed description is available at + ** @link Timer4CntGroup Timer4CNT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_cnt.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer4CntGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for CNT pclk division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( (Timer4CntPclkDiv1 == (x)) || \ + (Timer4CntPclkDiv2 == (x)) || \ + (Timer4CntPclkDiv4 == (x)) || \ + (Timer4CntPclkDiv8 == (x)) || \ + (Timer4CntPclkDiv16 == (x)) || \ + (Timer4CntPclkDiv32 == (x)) || \ + (Timer4CntPclkDiv64 == (x)) || \ + (Timer4CntPclkDiv128 == (x)) || \ + (Timer4CntPclkDiv256 == (x)) || \ + (Timer4CntPclkDiv512 == (x)) || \ + (Timer4CntPclkDiv1024 == (x))) + +/*!< Parameter validity check for CNT mode */ +#define IS_VALID_CNT_MODE(x) \ +( (Timer4CntSawtoothWave == (x)) || \ + (Timer4CntTriangularWave == (x))) + +/*!< Parameter validity check for CNT interrupt mask */ +#define IS_VALID_CNT_INT_MSK(x) \ +( (Timer4CntIntMask0 == (x)) || \ + (Timer4CntIntMask1 == (x)) || \ + (Timer4CntIntMask2 == (x)) || \ + (Timer4CntIntMask3 == (x)) || \ + (Timer4CntIntMask4 == (x)) || \ + (Timer4CntIntMask5 == (x)) || \ + (Timer4CntIntMask6 == (x)) || \ + (Timer4CntIntMask7 == (x)) || \ + (Timer4CntIntMask8 == (x)) || \ + (Timer4CntIntMask9 == (x)) || \ + (Timer4CntIntMask10 == (x)) || \ + (Timer4CntIntMask11 == (x)) || \ + (Timer4CntIntMask12 == (x)) || \ + (Timer4CntIntMask13 == (x)) || \ + (Timer4CntIntMask14 == (x)) || \ + (Timer4CntIntMask15 == (x))) + +/*!< Parameter validity check for CNT match interrupt type */ +#define IS_VALID_CNT_INT_TYPE(x) \ +( (Timer4CntZeroMatchInt == (x)) || \ + (Timer4CntPeakMatchInt == (x))) + +/*!< Parameter validity check for CNT clock source */ +#define IS_VALID_CNT_CLK(x) \ +( (Timer4CntPclk == (x)) || \ + (Timer4CntExtclk == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CNT initialization configuration structure + ** \arg This parameter detail refer @ref stc_timer4_cnt_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_cnt_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_tmr4_ccsr_field_t CCSR_f = {0}; + stc_tmr4_cvpr_field_t CVPR_f = {0}; + + /* Check for TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(pstcInitCfg->enClk)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcInitCfg->enCntMode)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enBufferCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enZeroIntCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enPeakIntCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enZeroIntMsk)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enPeakIntMsk)); + + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + + /* stop count of CNT */ + CCSR_f.STOP = 1u; + + /* set count clock div of CNT */ + CCSR_f.CKDIV = pstcInitCfg->enClkDiv; + + /* set cnt mode */ + CCSR_f.MODE = pstcInitCfg->enCntMode; + + /* set buffer enable bit */ + CCSR_f.BUFEN = (uint16_t)(pstcInitCfg->enBufferCmd); + + /* set external clock enable bit */ + CCSR_f.ECKEN = (Timer4CntExtclk == pstcInitCfg->enClk) ? ((uint16_t)1u) : ((uint16_t)0u); + + /* Set interrupt enable */ + CCSR_f.IRQZEN = (uint16_t)(pstcInitCfg->enZeroIntCmd); + CCSR_f.IRQPEN = (uint16_t)(pstcInitCfg->enPeakIntCmd); + + /* set intterrupt mask times */ + CVPR_f.ZIM = (uint16_t)(pstcInitCfg->enZeroIntMsk); + CVPR_f.PIM = (uint16_t)(pstcInitCfg->enPeakIntMsk); + + /* Set Timer4 register */ + TMR4x->CVPR = *(uint16_t *)(&CVPR_f); + TMR4x->CCSR_f = CCSR_f; + TMR4x->CPSR = pstcInitCfg->u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCntClk Timer4 CNT clock source + ** \arg Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \arg Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_t enCntClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(enCntClk)); + /* set external clock enable bit */ + TMR4x->CCSR_f.ECKEN = (uint16_t)(enCntClk); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \retval Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ******************************************************************************/ +en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_t)(TMR4x->CCSR_f.ECKEN); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enClkDiv Timer4 CNT clock division + ** \arg Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \arg Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \arg Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \arg Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \arg Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \arg Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \arg Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \arg Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \arg Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \arg Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \arg Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(enClkDiv)); + TMR4x->CCSR_f.CKDIV = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \retval Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \retval Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \retval Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \retval Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \retval Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \retval Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \retval Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \retval Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \retval Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \retval Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ******************************************************************************/ +en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_div_t)(TMR4x->CCSR_f.CKDIV); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enMode Timer4 CNT mode + ** \arg Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \arg Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_MODE(enMode)); + TMR4x->CCSR_f.MODE = (uint16_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \retval Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ******************************************************************************/ +en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_mode_t)(TMR4x->CCSR_f.MODE); +} + +/** + ******************************************************************************* + ** \brief Start Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Start successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Stop successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType The specified type of Timer4 CNT interrupt + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified Timer4 CNT interrupt function + ** \arg Disable Disable the specified Timer4 CNT interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZEN = (uint16_t)enCmd; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPEN = (uint16_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Reset None interrupt request on Timer4 CNT + ** \retval Set Detection interrupt request on Timer4 CNT + ** + ******************************************************************************/ +en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16Flag = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16Flag = TMR4x->CCSR_f.IRQZF; + break; + case Timer4CntPeakMatchInt: + u16Flag = TMR4x->CCSR_f.IRQPF; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZF = (uint16_t)0u; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPF = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Cycle The Timer4 CNT cycle value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CPSR = u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The cycle value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CPSR; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT register CNTR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.CLEAR = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the current count value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Count The Timer4 CNT current count value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CNTR = u16Count; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT current count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The current count value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CNTR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enMaskTimes Timer4 CNT interrupt mask times + ** \arg Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \arg Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \arg Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \arg Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \arg Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \arg Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \arg Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \arg Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \arg Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \arg Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \arg Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \arg Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \arg Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \arg Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \arg Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \arg Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_timer4_cnt_int_mask_t enMaskTimes) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(enMaskTimes)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CVPR_f.ZIM = (uint16_t)enMaskTimes; + break; + case Timer4CntPeakMatchInt: + TMR4x->CVPR_f.PIM = (uint16_t)enMaskTimes; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \retval Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \retval Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \retval Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \retval Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \retval Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \retval Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \retval Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \retval Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \retval Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \retval Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \retval Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \retval Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \retval Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \retval Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \retval Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ******************************************************************************/ +en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16MaskTimes = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16MaskTimes = TMR4x->CVPR_f.ZIM; + break; + case Timer4CntPeakMatchInt: + u16MaskTimes = TMR4x->CVPR_f.PIM; + break; + default: + break; + } + + return (en_timer4_cnt_int_mask_t)u16MaskTimes; +} + +//@} // Timer4CntGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer4_emb.c b/lib/hc32f460/driver/src/hc32f460_timer4_emb.c new file mode 100644 index 000000000000..46e7e26b64d3 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer4_emb.c @@ -0,0 +1,274 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_emb.c + ** + ** A detailed description is available at + ** @link Timer4EmbGroup Timer4EMB description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_emb.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer4EmbGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter valid check for EMB HOLD mode. */ +#define IS_VALID_EMB_HOLD_MODE(x) \ +( (EmbHoldPwm == (x)) || \ + (EmbChangePwm == (x))) + +/*!< Parameter valid check for EMB state. */ +#define IS_VALID_EMB_STATE(x) \ +( (EmbTrigPwmOutputHiz == (x)) || \ + (EmbTrigPwmOutputNormal == (x)) || \ + (EmbTrigPwmOutputLowLevel == (x)) || \ + (EmbTrigPwmOutputHighLevel == (x))) + +/*!< Timer4x ECER register address. */ +#define TMR4_ECERx(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) ? &M4_TMR4_CR->ECER1 : \ + ((M4_TMR42 == (__TMRx__)) ? &M4_TMR4_CR->ECER2 : &M4_TMR4_CR->ECER3)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg The pointer of EMB configure structure + ** \arg This parameter detail refer @ref stc_timer4_emb_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_emb_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(pstcInitCfg->enEmbState)); + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(pstcInitCfg->enPwmHold)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)(pstcInitCfg->enPwmHold); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)(pstcInitCfg->enEmbState); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set reset value(0x0000) to register ESCR */ + TMR4x->ECSR = 0u; + + /* Set reset value(0x0000) to register ECER */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)0ul; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enHoldMode EMB HOLD mode + ** \arg EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \arg EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetHoldMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_hold_mode_t enHoldMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(enHoldMode)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)enHoldMode; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \retval EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ******************************************************************************/ +en_timer4_emb_hold_mode_t TIMER4_EMB_GetHoldMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_emb_hold_mode_t)(TMR4x->ECSR_f.HOLD); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enEmbState EMB state + ** \arg EmbTrigPwmOutputNormal PWM output signal normally. + ** \arg EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \arg EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \arg EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetState(const M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_state_t enEmbState) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(enEmbState)); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)enEmbState; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbTrigPwmOutputNormal PWM output signal normally. + ** \retval EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \retval EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \retval EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ******************************************************************************/ +en_timer4_emb_state_t TIMER4_EMB_GetState(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return *(__IO en_timer4_emb_state_t *)TMR4_ECERx(TMR4x); +} + +//@} // Timer4EmbGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer4_oco.c b/lib/hc32f460/driver/src/hc32f460_timer4_oco.c new file mode 100644 index 000000000000..35e97f1a522f --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer4_oco.c @@ -0,0 +1,1291 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_oco.c + ** + ** A detailed description is available at + ** @link Timer4OcoGroup Timer4OCO description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4OCO. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_oco.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer4OcoGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for oco channel */ +#define IS_VALID_OCO_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOul == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwh == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for oco low channel */ +#define IS_VALID_OCO_LOW_CH(x) \ +( (Timer4OcoOul == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for even high channel */ +#define IS_VALID_OCO_HIGH_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOwh == (x))) + +/*!< Parameter validity check for occr buffer mode */ +#define IS_VALID_OCCR_BUF_MODE(x) \ +( (OccrBufDisable == (x)) || \ + (OccrBufTrsfByCntZero == (x)) || \ + (OccrBufTrsfByCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroZicZero == (x)) || \ + (OccrBufTrsfByCntPeakPicZero == (x)) || \ + (OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for ocmr buffer mode */ +#define IS_VALID_OCMR_BUF_MODE(x) \ +( (OcmrBufDisable == (x)) || \ + (OcmrBufTrsfByCntZero == (x)) || \ + (OcmrBufTrsfByCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroZicZero == (x)) || \ + (OcmrBufTrsfByCntPeakPicZero == (x)) || \ + (OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for output level type */ +#define IS_VALID_OP_PORT_LEVEL(x) \ +( (OcPortLevelLow == (x)) || \ + (OcPortLevelHigh == (x))) + +/*!< Parameter validity check for oco OP state */ +#define IS_VALID_OP_STATE(x) \ +( (OcoOpOutputLow == (x)) || \ + (OcoOpOutputHigh == (x)) || \ + (OcoOpOutputHold == (x)) || \ + (OcoOpOutputReverse == (x))) + +/*!< Parameter validity check for oco OCF state */ +#define IS_VALID_OCF_STATE(x) \ +( (OcoOcfSet == (x)) || \ + (OcoOcfHold == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_OCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCMRHUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCERx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCERU + (((uint32_t)(__CH__))/2ul)*4ul) +#define TMR4_OCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCSRU + (((uint32_t)(__CH__))/2ul)*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcInitCfg The pointer of OCO configure structure + ** \arg This parameter detail refer @ref stc_timer4_oco_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_timer4_oco_init_t* pstcInitCfg) +{ + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enOcoIntCmd)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(pstcInitCfg->enPortLevel)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(pstcInitCfg->enOcmrBufMode)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(pstcInitCfg->enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x,enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x,enCh); + + /* Set OCMR and OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPH = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEH = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPL = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEL = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + __IO uint32_t u32OCMR = 0ul; + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + u32OCMR = TMR4_OCMRx(TMR4x, enCh); + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set default value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + pstcOCSR->OCIEH = (uint16_t)0u; + pstcOCSR->OCPH = (uint16_t)0u; + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + pstcOCER->MCECH = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint16_t*)u32OCMR = (uint16_t)0u; + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + pstcOCSR->OCIEL = (uint16_t)0u; + pstcOCSR->OCPL = (uint16_t)0u; + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + pstcOCER->MCECL = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint32_t*)u32OCMR = (uint32_t)0ul; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOccrBufMode Occr buffer mode + ** \arg OccrBufDisable Disable the register buffer function + ** \arg OccrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OccrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OccrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OccrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OccrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** \retval Ok OCO occr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOccrBufMode is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_occr_buf_t enOccrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOcmrBufMode Occr buffer mode + ** \arg OcmrBufDisable Disable the register buffer function + ** \arg OcmrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OcmrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OcmrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OcmrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OcmrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** + ** \retval Ok OCO ocmr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOcmrBufMode is invalid. + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_ocmr_buf_t enOcmrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(enOcmrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCMR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Extend the matching determination conditions of OCO channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd Extend the match conditions functional state + ** \arg Enable Extend the match conditions function + ** \arg Disable Don't extend the match conditions function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ExtMatchCondCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCER->MCECH = (uint16_t)enCmd) : (pstcOCER->MCECL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO high channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref stc_oco_high_ch_compare_mode_t + ** + ** \retval Ok OCO high channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_high_ch_compare_mode_t *pstcMode) +{ + uint16_t u16OCMR = 0u; + __IO uint16_t *pu16OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_HIGH_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownCntMatchOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu16OCMR = (__IO uint16_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + pstcOCER->MCECH = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOpState << 10u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroNotMatchOpState << 14u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOpState << 8u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOpState << 6u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakNotMatchOpState << 12u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOpState << 4u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOcfState << 3u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOcfState << 1u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu16OCMR = u16OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO low channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref TIMER4_OCO_SetLowChCompareMode + ** + ** \retval Ok OCO low channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_low_ch_compare_mode_t *pstcMode) +{ + uint32_t u32OCMR = 0ul; + __IO uint32_t *pu32OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer and pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_LOW_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu32OCMR = (__IO uint32_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh);; + + pstcOCER->MCECL = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighMatchLowChOpState << 26u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState << 10u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState << 30u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState << 14u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighMatchLowChOpState << 24u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState << 8u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState << 18u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighMatchLowChOpState << 22u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState << 6u) ; + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState << 28u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState << 12u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighMatchLowChOpState << 20u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighNotMatchLowChOpState << 4u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowNotMatchHighMatchLowChOpState << 16u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroMatchOcfState << 3u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakMatchOcfState << 1u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu32OCMR = u32OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set output function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The output functional state + ** \arg Enable Enable output function + ** \arg Disable Disable output function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_OutputCompareCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCEH = (uint16_t)enCmd) : (pstcOCSR->OCEL = (uint16_t)enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OCO interrupt function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The interrupt functional state + ** \arg Enable Enable interrupt function + ** \arg Disable Disable interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCIEH = (uint16_t)enCmd) : (pstcOCSR->OCIEL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Reset None interrupt request on Timer4 OCO + ** \retval Set Detection interrupt request on Timer4 OCO + ** + ******************************************************************************/ +en_flag_status_t TIMER4_OCO_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + en_flag_status_t enFlag = Reset; + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set return value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set return value */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = 0u) : (pstcOCSR->OCFL = 0u); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enLevel OP port level of OCO + ** \arg OcPortLevelLow Output low level to OC port + ** \arg OcPortLevelHigh Output high level to OC port + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOpPortLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_port_level_t enLevel) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(enLevel)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = (uint16_t)enLevel) : (pstcOCSR->OCFL = (uint16_t)enLevel); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OcPortLevelLow Output low level to OC port + ** \retval OcPortLevelHigh Output high level to OC port + ** + ******************************************************************************/ +en_timer4_oco_port_level_t TIMER4_OCO_GetOpPinLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_timer4_oco_port_level_t enLevel = OcPortLevelLow; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enLevel; +} + +/** + ******************************************************************************* + ** \brief Write OCCR register + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] u16Occr The value of occr + ** \arg 16bit value + ** + ** \retval Ok OCCR written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_WriteOccr(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + uint16_t u16Occr) +{ + __IO uint16_t *pu16OCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + /* set register */ + *pu16OCCR = u16Occr; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCCR register value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OCCR register value + ** + ******************************************************************************/ +uint16_t TIMER4_OCO_ReadOccr(const M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + + return (*pu16OCCR); +} + +//@} // Timer4OcoGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer4_pwm.c b/lib/hc32f460/driver/src/hc32f460_timer4_pwm.c new file mode 100644 index 000000000000..fb4090a83bd5 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer4_pwm.c @@ -0,0 +1,596 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_pwm.c + ** + ** A detailed description is available at + ** @link Timer4PwmGroup Timer4PWM description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4PWM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_pwm.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer4PwmGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for PWM channel */ +#define IS_VALID_PWM_CH(x) \ +( (Timer4PwmU == (x)) || \ + (Timer4PwmV == (x)) || \ + (Timer4PwmW == (x))) + +/*!< Parameter validity check for PWM mode */ +#define IS_VALID_PWM_MODE(x) \ +( (PwmThroughMode == (x)) || \ + (PwmDeadTimerMode == (x)) || \ + (PwmDeadTimerFilterMode == (x))) + +/*!< Parameter valid check for PWM output state. */ +#define IS_VALID_PWM_OUTPUT_STATE(x) \ +( (PwmHPwmLHold == (x)) || \ + (PwmHPwmLReverse == (x)) || \ + (PwmHReversePwmLHold == (x)) || \ + (PwmHHoldPwmLReverse == (x))) + +/*!< Parameter valid check for PWM clock division. */ +#define IS_VALID_PWM_CLK_DIV(x) \ +( (PwmPlckDiv1 == (x)) || \ + (PwmPlckDiv2 == (x)) || \ + (PwmPlckDiv4 == (x)) || \ + (PwmPlckDiv8 == (x)) || \ + (PwmPlckDiv16 == (x)) || \ + (PwmPlckDiv32 == (x)) || \ + (PwmPlckDiv64 == (x)) || \ + (PwmPlckDiv128 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_RCSRx(__TMR4x__) ((uint32_t)&(__TMR4x__)->RCSR) +#define TMR4_POCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->POCRU + ((uint32_t)(__CH__))*4ul) +#define TMR4_PDARx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDARU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PDBRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDBRU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PFSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PFSRU + ((uint32_t)(__CH__))*8ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] pstcInitCfg The pointer of PWM configure structure + ** \arg This parameter detail refer @ref stc_timer4_pwm_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + const stc_timer4_pwm_init_t *pstcInitCfg) +{ + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + en_result_t enRet = Ok; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_PWM_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enRtIntMaskCmd)); + DDL_ASSERT(IS_VALID_PWM_OUTPUT_STATE(pstcInitCfg->enOutputState)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + /* Configure PWM mode */ + pstcPOCR_f->PWMMD = (uint16_t)(pstcInitCfg->enMode); + + /* Configure PWM mode */ + pstcPOCR_f->LVLS = (uint16_t)(pstcInitCfg->enOutputState); + + /* Set timer clock division */ + pstcPOCR_f->DIVCK = (uint16_t)(pstcInitCfg->enClkDiv); + + /* Set interrupt mask */ + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = Ok; + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + __IO uint16_t *pu16PFSR = NULL; + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t*)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t*)TMR4_PDBRx(TMR4x, enCh); + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + *pu16PDAR = (uint16_t)0u; + *pu16PDBR = (uint16_t)0u; + *pu16PFSR = (uint16_t)0u; + pstcPOCR_f->DIVCK = (uint16_t)0u; + pstcPOCR_f->LVLS = (uint16_t)0u; + pstcPOCR_f->PWMMD = (uint16_t)0u; + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)0u; + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)0u; + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Start timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StartTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTEU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTEV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTEW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Stop timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StopTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTSU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTSV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTSW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Reset None interrupt request on PWM reload-timer + ** \retval Set Detection interrupt request on PWM reload-timer + ** + ******************************************************************************/ +en_flag_status_t TIMER4_PWM_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + uint16_t u16Flag = 0u; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + u16Flag = pstcRCSR_f->RTIFU; + break; + case Timer4PwmV: + u16Flag = pstcRCSR_f->RTIFV; + break; + case Timer4PwmW: + u16Flag = pstcRCSR_f->RTIFW; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok PWM reload-timer interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTICU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTICV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTICW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write timer count cycle + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16PDAR PDAR value + ** \arg 0~65535 + ** \param [in] u16PDBR PDBR value + ** \arg 0~65535 + ** + ** \retval Ok Timer count cycle is written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_WriteDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16PDAR, + uint16_t u16PDBR) +{ + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + /* set the register */ + *pu16PDAR = u16PDAR; + *pu16PDBR = u16PDBR; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read dead region count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [out] u16PDAR Pointer of uint16_t type + ** \arg 0~65535 + ** \param [out] u16PDBR Pointer of uint16_t type + ** \arg 0~65535 + ** + ** \retval Ok Read successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ReadDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t *u16PDAR, + uint16_t *u16PDBR) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + *u16PDAR = *(__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + *u16PDBR = *(__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set cycle of PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16Count PWM pulse counter value + ** \arg 0~65535 + ** + ** \retval Ok Cycle of PWM timer is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16Count) +{ + __IO uint16_t *pu16PFSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + *pu16PFSR =u16Count; + + enRet = Ok; + } + + return enRet; +} + +//@} // Timer4PwmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer4_sevt.c b/lib/hc32f460/driver/src/hc32f460_timer4_sevt.c new file mode 100644 index 000000000000..bd650374a2c7 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer4_sevt.c @@ -0,0 +1,589 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_sevt.c + ** + ** A detailed description is available at + ** @link Timer4SevtGroup Timer4SEVT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4SEVT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_sevt.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer4SevtGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for SEVT channel */ +#define IS_VALID_SEVT_CH(x) \ +( (Timer4SevtCh0 == (x)) || \ + (Timer4SevtCh1 == (x)) || \ + (Timer4SevtCh2 == (x)) || \ + (Timer4SevtCh3 == (x)) || \ + (Timer4SevtCh4 == (x)) || \ + (Timer4SevtCh5 == (x))) + +/*!< Parameter validity check for adct buffer mode */ +#define IS_VALID_SEVT_BUF_MODE(x) \ +( (SevtBufDisable == (x)) || \ + (SevtBufCntZero == (x)) || \ + (SevtBufCntPeak == (x)) || \ + (SevtBufCntZeroOrCntPeak == (x)) || \ + (SevtBufCntZeroZicZero == (x)) || \ + (SevtBufCntPeakPicZero == (x)) || \ + (SevtBufCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for SEVT trigger event */ +#define IS_VALID_SEVT_TRG_EVT(x) \ +( (SevtTrgEvtSCMUH == (x)) || \ + (SevtTrgEvtSCMUL == (x)) || \ + (SevtTrgEvtSCMVH == (x)) || \ + (SevtTrgEvtSCMVL == (x)) || \ + (SevtTrgEvtSCMWH == (x)) || \ + (SevtTrgEvtSCMWL == (x))) + +/*!< Parameter validity check for SEVT OCCR selection */ +#define IS_VALID_SEVT_OCCR_SEL(x) \ +( (SevtSelOCCRxh == (x)) || \ + (SevtSelOCCRxl == (x))) + +/*!< Parameter validity check for SEVT running mode */ +#define IS_VALID_SEVT_MODE(x) \ +( (SevtDelayTrigMode == (x)) || \ + (SevtCompareTrigMode == (x))) + +/*!< Parameter validity check for SEVT mask time */ +#define IS_VALID_SEVT_MSK(x) \ +( (Timer4SevtMask0 == (x)) || \ + (Timer4SevtMask1 == (x)) || \ + (Timer4SevtMask2 == (x)) || \ + (Timer4SevtMask3 == (x)) || \ + (Timer4SevtMask4 == (x)) || \ + (Timer4SevtMask5 == (x)) || \ + (Timer4SevtMask6 == (x)) || \ + (Timer4SevtMask7 == (x)) || \ + (Timer4SevtMask8 == (x)) || \ + (Timer4SevtMask9 == (x)) || \ + (Timer4SevtMask10 == (x)) || \ + (Timer4SevtMask11 == (x)) || \ + (Timer4SevtMask12 == (x)) || \ + (Timer4SevtMask13 == (x)) || \ + (Timer4SevtMask14 == (x)) || \ + (Timer4SevtMask15 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_SCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCSRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCMRUH + ((uint32_t)(__CH__))*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a Special-Event channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcInitCfg The pointer of SEVT configure structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_init_t *pstcInitCfg) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t stcSCSR_f; + __IO stc_tmr4_scmr_field_t stcSCMR_f; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_SEVT_BUF_MODE(pstcInitCfg->enBuf)); + DDL_ASSERT(IS_VALID_SEVT_MSK(pstcInitCfg->enMaskTimes)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(pstcInitCfg->enTrigEvt)); + DDL_ASSERT(IS_VALID_SEVT_OCCR_SEL(pstcInitCfg->enOccrSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcZicCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcPicCmd)); + + enRet = Ok; + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = (uint16_t)0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + switch (pstcInitCfg->enBuf) + { + case SevtBufDisable: + stcSCSR_f.BUFEN = (uint16_t)0u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntPeak: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroOrCntPeak: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroZicZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntZeroZicZeroOrCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (Ok == enRet) + { + /* Configure start trigger output channel number */ + stcSCSR_f.EVTOS = (uint16_t)(pstcInitCfg->enTrigEvt); + + /* Select SEVT running mode */ + stcSCSR_f.EVTMS = (uint16_t)(pstcInitCfg->enMode); + + /* select OCO OCCR register: OCCR(x) */ + stcSCSR_f.EVTDS = (uint16_t)(pstcInitCfg->enOccrSel); + + /* Set the comparison with CNT interrupt mask counter */ + stcSCMR_f.AMC = (uint16_t)(pstcInitCfg->enMaskTimes); + stcSCMR_f.MZCE = (uint16_t)(pstcInitCfg->enCmpAmcZicCmd); + stcSCMR_f.MPCE = (uint16_t)(pstcInitCfg->enCmpAmcPicCmd); + + *pstcSCSR_f = stcSCSR_f; + *pstcSCMR_f = stcSCMR_f; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a SEVT channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = 0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enTrgEvt Timer4 Special-EVT Event + ** \arg SevtTrgEvtSCMUH Timer4 Special-EVT Event: TMR4_Ux_SCMUH + ** \arg SevtTrgEvtSCMUL Timer4 Special-EVT Event: TMR4_Ux_SCMUL + ** \arg SevtTrgEvtSCMVH Timer4 Special-EVT Event: TMR4_Ux_SCMVH + ** \arg SevtTrgEvtSCMVL Timer4 Special-EVT Event: TMR4_Ux_SCMVL + ** \arg SevtTrgEvtSCMWH Timer4 Special-EVT Event: TMR4_Ux_SCMWH + ** \arg SevtTrgEvtSCMWL Timer4 Special-EVT Event: TMR4_Ux_SCMWL + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerEvent(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_trigger_evt_t enTrgEvt) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(enTrgEvt)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->EVTOS = (uint16_t)(enTrgEvt); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger condition. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcTrigCond The pointer of SEVT trigger condition structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_trigger_cond_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerCond(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_trigger_cond_t *pstcTrigCond) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enUpMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enZeroMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enDownMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enPeakMatchCmd)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->PEN = (uint16_t)(pstcTrigCond->enPeakMatchCmd); + pstcSCSR_f->ZEN = (uint16_t)(pstcTrigCond->enZeroMatchCmd); + pstcSCSR_f->UEN = (uint16_t)(pstcTrigCond->enUpMatchCmd); + pstcSCSR_f->DEN = (uint16_t)(pstcTrigCond->enDownMatchCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write compare or delay value to Timer4 SEVT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] u16SccrVal Timer4 SEVT compare value + ** + ** \retval Ok Compare or delay value to Timer4 SEVT is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_WriteSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + uint16_t u16SccrVal) +{ + __IO uint16_t *pu16SCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + *pu16SCCR = u16SccrVal; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read compare value or delay value of ATVR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Value of register SCCR + ** + ******************************************************************************/ +uint16_t TIMER4_SEVT_ReadSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + + /* check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + + return *pu16SCCR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enMaskTimes Timer4 Special-EVT event mask times + ** \arg Timer4SevtMask0 Mask 0 time. + ** \arg Timer4SevtMask1 Mask 1 times. + ** \arg Timer4SevtMask2 Mask 2 times. + ** \arg Timer4SevtMask3 Mask 3 times. + ** \arg Timer4SevtMask4 Mask 4 times. + ** \arg Timer4SevtMask5 Mask 5 times. + ** \arg Timer4SevtMask6 Mask 6 times. + ** \arg Timer4SevtMask7 Mask 7 times. + ** \arg Timer4SevtMask8 Mask 8 times. + ** \arg Timer4SevtMask9 Mask 9 times. + ** \arg Timer4SevtMask10 Mask 10 times + ** \arg Timer4SevtMask11 Mask 11 times + ** \arg Timer4SevtMask12 Mask 12 times + ** \arg Timer4SevtMask13 Mask 13 times + ** \arg Timer4SevtMask14 Mask 14 times + ** \arg Timer4SevtMask15 Mask 15 times + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_mask_t enMaskTimes) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MSK(enMaskTimes)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + pstcSCMR_f->AMC = (uint16_t)(enMaskTimes); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 SEVT mask count. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Timer4SevtMask0 Mask 0 time. + ** \retval Timer4SevtMask1 Mask 1 times. + ** \retval Timer4SevtMask2 Mask 2 times. + ** \retval Timer4SevtMask3 Mask 3 times. + ** \retval Timer4SevtMask4 Mask 4 times. + ** \retval Timer4SevtMask5 Mask 5 times. + ** \retval Timer4SevtMask6 Mask 6 times. + ** \retval Timer4SevtMask7 Mask 7 times. + ** \retval Timer4SevtMask8 Mask 8 times. + ** \retval Timer4SevtMask9 Mask 9 times. + ** \retval Timer4SevtMask10 Mask 10 times + ** \retval Timer4SevtMask11 Mask 11 times + ** \retval Timer4SevtMask12 Mask 12 times + ** \retval Timer4SevtMask13 Mask 13 times + ** \retval Timer4SevtMask14 Mask 14 times + ** \retval Timer4SevtMask15 Mask 15 times + ** + ******************************************************************************/ +en_timer4_sevt_mask_t TIMER4_SEVT_GetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + return (en_timer4_sevt_mask_t)pstcSCMR_f->AMC; +} + +//@} // Timer4SevtGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timer6.c b/lib/hc32f460/driver/src/hc32f460_timer6.c new file mode 100644 index 000000000000..9474fcac0cdd --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timer6.c @@ -0,0 +1,1820 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer6.c + ** + ** A detailed description is available at + ** @link Timer6Group Timer6 description @endlink + ** + ** - 2018-11-23 CDT First version for Device Driver Library of Timer6. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer6.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup Timer6Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timer6 unit */ +#define IS_VALID_NORMAL_TIMER6_UNIT(__TMR6x__) \ +( (M4_TMR61 == (__TMR6x__)) || \ + (M4_TMR62 == (__TMR6x__)) || \ + (M4_TMR63 == (__TMR6x__))) + +/*!< Parameter valid check for period register*/ +#define IS_VALID_PERIOD_TYPE(x) \ +( (Timer6PeriodA == (x)) || \ + (Timer6PeriodB == (x)) || \ + (Timer6PeriodC == (x))) +/*!< Parameter valid check for General compare register*/ +#define IS_VALID_GEN_CMP_TYPE(x) \ +( (Timer6GenCompareA == (x)) || \ + (Timer6GenCompareB == (x)) || \ + (Timer6GenCompareC == (x)) || \ + (Timer6GenCompareD == (x)) || \ + (Timer6GenCompareE == (x)) || \ + (Timer6GenCompareF == (x))) + +/*!< Parameter valid check for Special compare register*/ +#define IS_VALID_SPECIAL_CMP_TYPE(x) \ +( (Timer6SpclCompA == (x)) || \ + (Timer6SpclCompB == (x)) || \ + (Timer6SpclCompC == (x)) || \ + (Timer6SpclCompD == (x)) || \ + (Timer6SpclCompE == (x)) || \ + (Timer6SpclCompF == (x))) +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (Timer6PclkDiv1 == (x)) || \ + (Timer6PclkDiv2 == (x)) || \ + (Timer6PclkDiv4 == (x)) || \ + (Timer6PclkDiv8 == (x)) || \ + (Timer6PclkDiv16 == (x)) || \ + (Timer6PclkDiv64 == (x)) || \ + (Timer6PclkDiv256 == (x)) || \ + (Timer6PclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (Timer6CntSawtoothMode == (x)) || \ + (Timer6CntTriangularModeA == (x)) || \ + (Timer6CntTriangularModeB == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (Timer6CntDirDown == (x)) || \ + (Timer6CntDirUp == (x))) + +/*!< Parameter valid check for timer6 output port */ +#define IS_VALID_TIMER6_OUTPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x))) + +/*!< Parameter valid check for timer6 port mode */ +#define IS_VALID_TIMER6_PORT_MODE(x) \ +( (Timer6ModeCompareOutput == (x)) || \ + (Timer6ModeCaptureInput == (x))) + +/*!< Parameter valid check for timer6 input port */ +#define IS_VALID_TIMER6_INPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for start/stop count output status */ +#define IS_VALID_STA_STP_OUTPUT_STATUS(x) \ +( (Timer6PWMxPortOutLow == (x)) || \ + (Timer6PWMxPortOutHigh == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (Timer6FltClkPclk0Div1 == (x)) || \ + (Timer6FltClkPclk0Div4 == (x)) || \ + (Timer6FltClkPclk0Div16 == (x)) || \ + (Timer6FltClkPclk0Div64 == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_NUM(x) \ +( (Timer6PeriodCnts0 == (x)) || \ + (Timer6PeriodCnts1 == (x)) || \ + (Timer6PeriodCnts2 == (x)) || \ + (Timer6PeriodCnts3 == (x)) || \ + (Timer6PeriodCnts4 == (x)) || \ + (Timer6PeriodCnts5 == (x)) || \ + (Timer6PeriodCnts6 == (x)) || \ + (Timer6PeriodCnts7 == (x))) +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_EN_SOURCE(x) \ +( (Timer6PeriodCnteDisable == (x)) || \ + (Timer6PeriodCnteMin == (x)) || \ + (Timer6PeriodCnteMax == (x)) || \ + (Timer6PeriodCnteBoth == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (Timer6INTENA == (x)) || \ + (Timer6INTENB == (x)) || \ + (Timer6INTENC == (x)) || \ + (Timer6INTEND == (x)) || \ + (Timer6INTENE == (x)) || \ + (Timer6INTENF == (x)) || \ + (Timer6INTENOVF == (x)) || \ + (Timer6INTENUDF == (x)) || \ + (Timer6INTENDTE == (x)) || \ + (Timer6INTENSAU == (x)) || \ + (Timer6INTENSAD == (x)) || \ + (Timer6INTENSBU == (x)) || \ + (Timer6INTENSBD == (x))) + +/*!< Parameter valid check for status type */ +#define IS_VALID_STATUS_TYPE(x) \ +( (Timer6CMAF == (x)) || \ + (Timer6CMBF == (x)) || \ + (Timer6CMCF == (x)) || \ + (Timer6CMDF == (x)) || \ + (Timer6CMEF == (x)) || \ + (Timer6CMFF == (x)) || \ + (Timer6OVFF == (x)) || \ + (Timer6UDFF == (x)) || \ + (Timer6DTEF == (x)) || \ + (Timer6CMSAUF == (x)) || \ + (Timer6CMSADF == (x)) || \ + (Timer6CMSBUF == (x)) || \ + (Timer6CMSBDF == (x)) || \ + (Timer6VPERNUM == (x)) || \ + (Timer6DIRF == (x))) + +/*!< Parameter valid check for hardware up count/down count event type */ +#define IS_VALID_HW_COUNT_TYPE(x) \ +( (Timer6HwCntPWMALowPWMBRise == (x)) || \ + (Timer6HwCntPWMALowPWMBFall == (x)) || \ + (Timer6HwCntPWMAHighPWMBRise == (x)) || \ + (Timer6HwCntPWMAHighPWMBFall == (x)) || \ + (Timer6HwCntPWMBLowPWMARise == (x)) || \ + (Timer6HwCntPWMBLowPWMAFall == (x)) || \ + (Timer6HwCntPWMBHighPWMARise == (x)) || \ + (Timer6HwCntPWMBHighPWMAFall == (x)) || \ + (Timer6HwCntTRIGARise == (x)) || \ + (Timer6HwCntTRIGAFall == (x)) || \ + (Timer6HwCntTRIGBRise == (x)) || \ + (Timer6HwCntTRIGBFall == (x)) || \ + (Timer6HwCntAos0 == (x)) || \ + (Timer6HwCntAos1 == (x))) + +/*!< Parameter valid check for hardware up start/stop/clear/capture event type */ +#define IS_VALID_HW_STA_STP_CLR_CAP_TYPE(x) \ +( (Timer6HwTrigAos0 == (x)) || \ + (Timer6HwTrigAos1 == (x)) || \ + (Timer6HwTrigPWMARise == (x)) || \ + (Timer6HwTrigPWMAFall == (x)) || \ + (Timer6HwTrigPWMBRise == (x)) || \ + (Timer6HwTrigPWMBFall == (x)) || \ + (Timer6HwTrigTimTriARise == (x)) || \ + (Timer6HwTrigTimTriAFall == (x)) || \ + (Timer6HwTrigTimTriBRise == (x)) || \ + (Timer6HwTrigTimTriBFall == (x)) || \ + (Timer6HwTrigEnd == (x))) + +/*!< Parameter valid check for timer6 input port type */ +#define IS_VALID_INPUT_PORT_TYPE(x) \ +( (Timer6xCHA == (x)) || \ + (Timer6xCHB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for GenCMP and period register buffer transfer type*/ +#define IS_VALID_GCMP_PRD_BUF_TYPE(x) \ +( (Timer6GcmpPrdSingleBuf == (x)) || \ + (Timer6GcmpPrdDoubleBuf == (x))) + +/*!< Parameter valid check for special compare register buffer transfer type */ +#define IS_VALID_SPCL_BUF_TYPE(x) \ +( (Timer6SpclSingleBuf == (x)) || \ + (Timer6SpclDoubleBuf == (x))) + +/*!< Parameter valid check for spcl register transfer opportunity type */ +#define IS_VALID_SPCL_TRANS_OPT_TYPE(x) \ +( (Timer6SplcOptNone == (x)) || \ + (Timer6SplcOptOverFlow == (x)) || \ + (Timer6SplcOptUnderFlow == (x)) || \ + (Timer6SplcOptBoth == (x))) + +/*!< Parameter valid check for dead time register type */ +#define IS_VALID_DEAD_TIME_TYPE(x) \ +( (Timer6DeadTimUpAR == (x)) || \ + (Timer6DeadTimUpBR == (x)) || \ + (Timer6DeadTimDwnAR == (x)) || \ + (Timer6DeadTimDwnBR == (x))) + +/*!< Parameter valid check for Z Phase input mask periods */ +#define IS_VALID_ZPHASE_MASK_PRD(x) \ +( (Timer6ZMaskDis == (x)) || \ + (Timer6ZMask4Cyl == (x)) || \ + (Timer6ZMask8Cyl == (x)) || \ + (Tiemr6ZMask16Cyl == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511) + +/*!< Parameter validity check for common trigger. */ +#define IS_VALID_TIMER6_COM_TRIGGER(x) \ +( (Timer6ComTrigger_1 == (x)) || \ + (Timer6ComTrigger_2 == (x)) || \ + (Timer6ComTrigger_1_2 == (x))) + +/*! TimerA registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_GCONR_RESET_VALUE (0x00000100ul) +#define TIMERA_REG_ICONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_PCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_BCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_DCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_FCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_VPERR_RESET_VALUE (0x00000000ul) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief Timer6 interrupt request enable or disable + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Irq Irq type + * \param [in] bEn true/false + * + * \retval Ok: config successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enTimer6Irq)); + + switch (enTimer6Irq) + { + case Timer6INTENA: + TMR6x->ICONR_f.INTENA = bEn; + break; + case Timer6INTENB: + TMR6x->ICONR_f.INTENB = bEn; + break; + case Timer6INTENC: + TMR6x->ICONR_f.INTENC = bEn; + break; + case Timer6INTEND: + TMR6x->ICONR_f.INTEND = bEn; + break; + case Timer6INTENE: + TMR6x->ICONR_f.INTENE = bEn; + break; + case Timer6INTENF: + TMR6x->ICONR_f.INTENF = bEn; + break; + case Timer6INTENOVF: + TMR6x->ICONR_f.INTENOVF = bEn; + break; + case Timer6INTENUDF: + TMR6x->ICONR_f.INTENUDF = bEn; + break; + case Timer6INTENDTE: + TMR6x->ICONR_f.INTENDTE = bEn; + break; + case Timer6INTENSAU: + TMR6x->ICONR_f.INTENSAU = bEn; + break; + case Timer6INTENSAD: + TMR6x->ICONR_f.INTENSAD = bEn; + break; + case Timer6INTENSBU: + TMR6x->ICONR_f.INTENSBU = bEn; + break; + case Timer6INTENSBD: + TMR6x->ICONR_f.INTENSBD = bEn; + break; + default: + break; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Timer6 status flag + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \param [in] enStatus Timer6 status type + ** + ** \retval Timer6 status + ** + ******************************************************************************/ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus) +{ + uint8_t status = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case Timer6CMAF: + status = (uint8_t)TMR6x->STFLR_f.CMAF; + break; + case Timer6CMBF: + status = (uint8_t)TMR6x->STFLR_f.CMBF; + break; + case Timer6CMCF: + status = (uint8_t)TMR6x->STFLR_f.CMCF; + break; + case Timer6CMDF: + status = (uint8_t)TMR6x->STFLR_f.CMDF; + break; + case Timer6CMEF: + status = (uint8_t)TMR6x->STFLR_f.CMEF; + break; + case Timer6CMFF: + status = (uint8_t)TMR6x->STFLR_f.CMFF; + break; + case Timer6OVFF: + status = (uint8_t)TMR6x->STFLR_f.OVFF; + break; + case Timer6UDFF: + status = (uint8_t)TMR6x->STFLR_f.UDFF; + break; + case Timer6DTEF: + status = (uint8_t)TMR6x->STFLR_f.DTEF; + break; + case Timer6CMSAUF: + status = (uint8_t)TMR6x->STFLR_f.CMSAUF; + break; + case Timer6CMSADF: + status = (uint8_t)TMR6x->STFLR_f.CMSADF; + break; + case Timer6CMSBUF: + status = (uint8_t)TMR6x->STFLR_f.CMSBUF; + break; + case Timer6CMSBDF: + status = (uint8_t)TMR6x->STFLR_f.CMSBDF; + break; + case Timer6VPERNUM: + status = (uint8_t)TMR6x->STFLR_f.VPERNUM; + break; + case Timer6DIRF: + status = (uint8_t)TMR6x->STFLR_f.DIRF; + break; + default: + break; + } + + return status; +} + + + +/** + ******************************************************************************* + ** \brief De-Initialize Timer6 unit + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TMR6x->GCONR = TIMERA_REG_GCONR_RESET_VALUE; + TMR6x->PCONR = TIMERA_REG_PCONR_RESET_VALUE; + TMR6x->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TMR6x->BCONR = TIMERA_REG_BCONR_RESET_VALUE; + TMR6x->DCONR = TIMERA_REG_DCONR_RESET_VALUE; + TMR6x->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TMR6x->VPERR = TIMERA_REG_VPERR_RESET_VALUE; + TMR6x->HSTAR = 0x00000000ul; + TMR6x->HSTPR = 0x00000000ul; + TMR6x->HCLRR = 0x00000000ul; + TMR6x->HCPAR = 0x00000000ul; + TMR6x->HCPBR = 0x00000000ul; + TMR6x->HCUPR = 0x00000000ul; + TMR6x->HCDOR = 0x00000000ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Base Config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6BaseCntCfg Bsee Config Pointer + * + * \retval Ok: Config Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6BaseCntCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcTimer6BaseCntCfg->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcTimer6BaseCntCfg->enCntDir)); + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcTimer6BaseCntCfg->enCntClkDiv)); + + + TMR6x->GCONR_f.MODE = pstcTimer6BaseCntCfg->enCntMode; + TMR6x->GCONR_f.DIR = pstcTimer6BaseCntCfg->enCntDir; + TMR6x->GCONR_f.CKDIV = pstcTimer6BaseCntCfg->enCntClkDiv; + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Unit Start Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 1ul; + + return Ok; +} + +/******************************************************************************* + * \brief TImer6 Unit Stop Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Set Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = u16Value; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Get Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x) +{ + uint16_t u16Value; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u16Value = (uint16_t)TMR6x->CNTER_f.CNT; + + return u16Value; +} + +/******************************************************************************* + * \brief Timer6 Unit Clear Count Value + * + * + * \param [in] TMR6x Timer6 unit + * + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit set count period and buffer value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Periodx Period register name + * \param [in] u16Period Count period value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_TYPE(enTimer6Periodx)); + + switch (enTimer6Periodx) + { + case Timer6PeriodA: + TMR6x->PERAR = u16Period; + break; + case Timer6PeriodB: + TMR6x->PERBR = u16Period; + break; + case Timer6PeriodC: + TMR6x->PERCR = u16Period; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * \param [in] u16Compare General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + TMR6x->GCMAR = u16Compare; + break; + case Timer6GenCompareB: + TMR6x->GCMBR = u16Compare; + break; + case Timer6GenCompareC: + TMR6x->GCMCR = u16Compare; + break; + case Timer6GenCompareD: + TMR6x->GCMDR = u16Compare; + break; + case Timer6GenCompareE: + TMR6x->GCMER = u16Compare; + break; + case Timer6GenCompareF: + TMR6x->GCMFR = u16Compare; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set Special Compare Register Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp General Compare Register name + * \param [in] u16SpclCmp General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->SCMAR = u16SpclCmp; + break; + case Timer6SpclCompB: + TMR6x->SCMBR = u16SpclCmp; + break; + case Timer6SpclCompC: + TMR6x->SCMCR = u16SpclCmp; + break; + case Timer6SpclCompD: + TMR6x->SCMDR = u16SpclCmp; + break; + case Timer6SpclCompE: + TMR6x->SCMER = u16SpclCmp; + break; + case Timer6SpclCompF: + TMR6x->SCMFR = u16SpclCmp; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config general compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort PWM channel of timer6 + * \param [in] pstcTimer6GenBufCfg General Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6GenBufCfg->enGcmpBufTransType)); + + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->BCONR_f.BENA = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEA = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + case Timer6PWMB: + TMR6x->BCONR_f.BENB = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEB = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config special compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp Special Compare Register nameunit + * \param [in] pstcTimer6SpclBufCfg Special Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + DDL_ASSERT(IS_VALID_SPCL_BUF_TYPE(pstcTimer6SpclBufCfg->enSpclBufTransType)); + DDL_ASSERT(IS_VALID_SPCL_TRANS_OPT_TYPE(pstcTimer6SpclBufCfg->enSpclBufOptType)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->BCONR_f.BENSPA = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPA = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPA = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + case Timer6SpclCompB: + TMR6x->BCONR_f.BENSPB = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPB = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPB = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config period buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PrdBufCfg Period Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6PrdBufCfg->enPeriodBufTransType)); + + TMR6x->BCONR_f.BENP = pstcTimer6PrdBufCfg->bEnPeriodTransBuf; + TMR6x->BCONR_f.BSEP = pstcTimer6PrdBufCfg->enPeriodBufTransType; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit get General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * + * + * \retval u16TempValue: General Compare Register value + * + ******************************************************************************/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare) +{ + uint16_t u16TempValue = 0u; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + u16TempValue = (uint16_t)TMR6x->GCMAR; + break; + case Timer6GenCompareB: + u16TempValue = (uint16_t)TMR6x->GCMBR; + break; + case Timer6GenCompareC: + u16TempValue = (uint16_t)TMR6x->GCMCR; + break; + case Timer6GenCompareD: + u16TempValue = (uint16_t)TMR6x->GCMDR; + break; + case Timer6GenCompareE: + u16TempValue = (uint16_t)TMR6x->GCMER; + break; + case Timer6GenCompareF: + u16TempValue = (uint16_t)TMR6x->GCMFR; + break; + default: + break; + } + + return u16TempValue; +} + +/*********************************************************************** + * \brief Timer6 Config valid count period + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ValidPerCfg Valid Count Period Pointer + * + * \retval Ok: Config successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ***********************************************************************/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6ValidPerCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_EN_SOURCE(pstcTimer6ValidPerCfg->enValidCdtEn)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_NUM(pstcTimer6ValidPerCfg->enValidCntNum)); + + TMR6x->VPERR_f.PCNTS = pstcTimer6ValidPerCfg->enValidCntNum; + TMR6x->VPERR_f.PCNTE = pstcTimer6ValidPerCfg->enValidCdtEn; + TMR6x->VPERR_f.SPPERIA = pstcTimer6ValidPerCfg->bPeriodSCMA; + TMR6x->VPERR_f.SPPERIB = pstcTimer6ValidPerCfg->bPeriodSCMB; + } + return enRet; +} + +/******************************************************************************* + * \brief Port input config(Trig) + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6InputPort Input port select @ref en_timer6_input_port_t + * \param [in] pstcTimer6PortInputCfg port Input Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_input_port_t enTimer6InputPort, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6PortInputCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (enTimer6InputPort) + { + case Timer6xCHA: + TMR6x->FCONR_f.NOFIENGA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6xCHB: + TMR6x->FCONR_f.NOFIENGB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGB = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigA: + M4_TMR61->FCONR_f.NOFIENTA = pstcTimer6PortInputCfg->bFltEn; + M4_TMR61->FCONR_f.NOFICKTA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigB: + M4_TMR61->FCONR_f.NOFIENTB = pstcTimer6PortInputCfg->bFltEn; + M4_TMR61->FCONR_f.NOFICKTB = pstcTimer6PortInputCfg->enFltClk; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + + +/******************************************************************************* + * \brief Set channel function + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort Port to be configured @ref en_timer6_chx_port_t + * \param [in] enMode Channel mode @ref en_timer6_func_mode_t + * \retval None + ******************************************************************************/ +void Timer6_SetFunc(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, en_timer6_func_mode_t enMode) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + DDL_ASSERT(IS_VALID_TIMER6_PORT_MODE(enMode)); + + switch (enTimer6PWMPort) + { + case Timer6xCHA: + TMR6x->PCONR_f.CAPMDA = enMode; + break; + + case Timer6xCHB: + TMR6x->PCONR_f.CAPMDB = enMode; + break; + + default: + break; + } +} + +/******************************************************************************* + * \brief Timer6 Output Port config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort Timer6 Port(PWMA/PWMB) + * \param [in] pstcTimer6PortOutCfg timer6 Port Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, + en_timer6_chx_port_t enTimer6PWMPort, + const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + + if (NULL == pstcTimer6PortOutCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->PCONR_f.STACA = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCA = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSA = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCA = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCA = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENA = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALA = pstcTimer6PortOutCfg->enDisVal; + break; + + case Timer6PWMB: + TMR6x->PCONR_f.STACB = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCB = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSB = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCB = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCB = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENB = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALB = pstcTimer6PortOutCfg->enDisVal; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + + +/******************************************************************************* + * \brief Timer6 unit Set DeadTime Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6DTReg DeadTime Register name + * \param [in] u16DTValue DeadTime Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEAD_TIME_TYPE(enTimer6DTReg)); + + switch (enTimer6DTReg) + { + case Timer6DeadTimUpAR: + TMR6x->DTUAR = u16DTValue; + break; + case Timer6DeadTimUpBR: + TMR6x->DTUBR = u16DTValue; + break; + case Timer6DeadTimDwnAR: + TMR6x->DTDAR = u16DTValue; + break; + case Timer6DeadTimDwnBR: + TMR6x->DTDBR = u16DTValue; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Config DeadTime function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6DTCfg Timer6 dead time config pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6DTCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + TMR6x->DCONR_f.SEPA = pstcTimer6DTCfg->bEnDtEqualUpDwn; + TMR6x->DCONR_f.DTBENU = pstcTimer6DTCfg->bEnDtBufUp; + TMR6x->DCONR_f.DTBEND = pstcTimer6DTCfg->bEnDtBufDwn; + TMR6x->DCONR_f.DTCEN = pstcTimer6DTCfg->bEnDeadtime; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Start + * + * + * \param [in] pstcTimer6SwSyncStart Software Synchrony Start Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStart) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStart->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStart->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStart->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTAR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Stop + * + * + * \param [in] pstcTimer6SwSyncStop Software Synchrony Stop Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStop) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStop->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStop->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStop->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTPR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Clear + * + * + * \param [in] pstcTimer6SwSyncClear Software Synchrony Clear Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncClear) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncClear->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncClear->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncClear->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SCLRR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Get Software Synchrony status + * + * + * \param [in] pstcTimer6SwSyncState Software Synchrony State Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6SwSyncState) + { + enRet = ErrorInvalidParameter; + } + else + { + if (M4_TMR6_CR->SSTAR & 0x1ul) + { + pstcTimer6SwSyncState->bTimer61 = true; + } + else + { + pstcTimer6SwSyncState->bTimer61 = false; + } + if (M4_TMR6_CR->SSTAR & 0x2ul) + { + pstcTimer6SwSyncState->bTimer62 = true; + } + else + { + pstcTimer6SwSyncState->bTimer62 = false; + } + if (M4_TMR6_CR->SSTAR & 0x4ul) + { + pstcTimer6SwSyncState->bTimer63 = true; + } + else + { + pstcTimer6SwSyncState->bTimer63 = false; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Hardware UpCount Event config + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntUp Hardware UpCount Event + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntUp)); + + u32Val = TMR6x->HCUPR; + TMR6x->HCUPR = u32Val | (1ul << enTimer6HwCntUp); + + return Ok; +} + +/************************************************************** + * \brief Clear Timer6 Hardware UpCount Event + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ************************************************************/ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCUPR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Set Timer6 Hardware DownCount Event + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntDwn Hardware DownCount Event + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntDwn)); + + u32Val = TMR6x->HCDOR; + TMR6x->HCDOR = u32Val | (1ul << enTimer6HwCntDwn); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Timer6 Hardware DownCount Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCDOR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStart Hardware Start Event + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStart)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << enTimer6HwStart); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStop Hardware Stop Event + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStop)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << enTimer6HwStop); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTPR = 0ul; + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << 31u); + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwClear Hardware Clear Event + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwClear)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << enTimer6HwClear); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCLRR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureA Hardware capture event A selection + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureA)); + + u32Val = TMR6x->HCPAR; + TMR6x->HCPAR = u32Val | (1ul << enTimer6HwCaptureA); + //TMR6x->PCONR_f.CAPMDA = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureB Hardware capture event B selection + * + * \retval Ok: Set successfully + * \note Please make sure that peripheral clock of M4_TMR61 is valid if The + * TRIGX pin is used. + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureB)); + + u32Val = TMR6x->HCPBR; + TMR6x->HCPBR = u32Val | (1ul << enTimer6HwCaptureB); + //TMR6x->PCONR_f.CAPMDB = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPBR = 0ul; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 0 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR0_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 1 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 0 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR0 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR0 &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 1 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR1 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR1 &= ~(u32ComTrig << 30u); + } +} + +/******************************************************************************* + * \brief Z phase input mask config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ZMaskCfg Z phase input mask config pointer + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_ZPHASE_MASK_PRD(pstcTimer6ZMaskCfg->enZMaskCycle)); + + TMR6x->GCONR_f.ZMSKVAL = pstcTimer6ZMaskCfg->enZMaskCycle; + TMR6x->GCONR_f.ZMSKPOS = pstcTimer6ZMaskCfg->bFltPosCntMaksEn; + TMR6x->GCONR_f.ZMSKREV = pstcTimer6ZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + + +//@} // Timer6Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_timera.c b/lib/hc32f460/driver/src/hc32f460_timera.c new file mode 100644 index 000000000000..3f9a213b2949 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_timera.c @@ -0,0 +1,1968 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.c + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timera.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup TimeraGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timera unit */ +#define IS_VALID_NORMAL_TIMERA_UNIT(x) \ +( (M4_TMRA1 == (x)) || \ + (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for sync startup timera unit */ +#define IS_VALID_SYNC_STARTUP_TIMERA_UNIT(x) \ +( (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (TimeraPclkDiv1 == (x)) || \ + (TimeraPclkDiv2 == (x)) || \ + (TimeraPclkDiv4 == (x)) || \ + (TimeraPclkDiv8 == (x)) || \ + (TimeraPclkDiv16 == (x)) || \ + (TimeraPclkDiv32 == (x)) || \ + (TimeraPclkDiv64 == (x)) || \ + (TimeraPclkDiv128 == (x)) || \ + (TimeraPclkDiv256 == (x)) || \ + (TimeraPclkDiv512 == (x)) || \ + (TimeraPclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (TimeraCountModeSawtoothWave == (x)) || \ + (TimeraCountModeTriangularWave == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (TimeraCountDirUp == (x)) || \ + (TimeraCountDirDown == (x))) + +/*!< Parameter valid check for normal timera channel */ +#define IS_VALID_NORMAL_TIMERA_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh2 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh4 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh6 == (x)) || \ + (TimeraCh7 == (x)) || \ + (TimeraCh8 == (x))) + +/*!< Parameter valid check for set cache channel */ +#define IS_VALID_SET_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for enable cache channel */ +#define IS_VALID_ENABLE_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for timera count start output status */ +#define IS_VALID_COUNT_START_OUTPUT(x) \ +( (TimeraCountStartOutputLow == (x)) || \ + (TimeraCountStartOutputHigh == (x)) || \ + (TimeraCountStartOutputKeep == (x))) + +/*!< Parameter valid check for timera count stop output status */ +#define IS_VALID_COUNT_STOP_OUTPUT(x) \ +( (TimeraCountStopOutputLow == (x)) || \ + (TimeraCountStopOutputHigh == (x)) || \ + (TimeraCountStopOutputKeep == (x))) + +/*!< Parameter valid check for compare match output status */ +#define IS_VALID_COMPARE_MATCH_OUTPUT(x) \ +( (TimeraCompareMatchOutputLow == (x)) || \ + (TimeraCompareMatchOutputHigh == (x)) || \ + (TimeraCompareMatchOutputKeep == (x)) || \ + (TimeraCompareMatchOutputReverse == (x))) + +/*!< Parameter valid check for period match output status */ +#define IS_VALID_PERIOD_MATCH_OUTPUT(x) \ +( (TimeraPeriodMatchOutputLow == (x)) || \ + (TimeraPeriodMatchOutputHigh == (x)) || \ + (TimeraPeriodMatchOutputKeep == (x)) || \ + (TimeraPeriodMatchOutputReverse == (x))) + +/*!< Parameter valid check for specify output status */ +#define IS_VALID_SPECIFY_OUTPUT_STATUS(x) \ +( (TimeraSpecifyOutputInvalid == (x)) || \ + (TimeraSpecifyOutputLow == (x)) || \ + (TimeraSpecifyOutputHigh == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (TimeraFilterPclkDiv1 == (x)) || \ + (TimeraFilterPclkDiv4 == (x)) || \ + (TimeraFilterPclkDiv16 == (x)) || \ + (TimeraFilterPclkDiv64 == (x))) + +/*!< Parameter valid check for capture filter port source */ +#define IS_VALID_CAPTURE_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceCh1 == (x)) || \ + (TimeraFilterSourceCh2 == (x)) || \ + (TimeraFilterSourceCh3 == (x)) || \ + (TimeraFilterSourceCh4 == (x)) || \ + (TimeraFilterSourceCh5 == (x)) || \ + (TimeraFilterSourceCh6 == (x)) || \ + (TimeraFilterSourceCh7 == (x)) || \ + (TimeraFilterSourceCh8 == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for coding filter port source */ +#define IS_VALID_CODING_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceClkA == (x)) || \ + (TimeraFilterSourceClkB == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (TimeraIrqCaptureOrCompareCh1 == (x)) || \ + (TimeraIrqCaptureOrCompareCh2 == (x)) || \ + (TimeraIrqCaptureOrCompareCh3 == (x)) || \ + (TimeraIrqCaptureOrCompareCh4 == (x)) || \ + (TimeraIrqCaptureOrCompareCh5 == (x)) || \ + (TimeraIrqCaptureOrCompareCh6 == (x)) || \ + (TimeraIrqCaptureOrCompareCh7 == (x)) || \ + (TimeraIrqCaptureOrCompareCh8 == (x)) || \ + (TimeraIrqOverflow == (x)) || \ + (TimeraIrqUnderflow == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (TimeraFlagCaptureOrCompareCh1 == (x)) || \ + (TimeraFlagCaptureOrCompareCh2 == (x)) || \ + (TimeraFlagCaptureOrCompareCh3 == (x)) || \ + (TimeraFlagCaptureOrCompareCh4 == (x)) || \ + (TimeraFlagCaptureOrCompareCh5 == (x)) || \ + (TimeraFlagCaptureOrCompareCh6 == (x)) || \ + (TimeraFlagCaptureOrCompareCh7 == (x)) || \ + (TimeraFlagCaptureOrCompareCh8 == (x)) || \ + (TimeraFlagOverflow == (x)) || \ + (TimeraFlagUnderflow == (x))) + +/*! Parameter valid check for common trigger. */ +#define IS_VALID_COM_TRIGGER(x) \ +( (TimeraComTrigger_1 == (x)) || \ + (TimeraComTrigger_2 == (x)) || \ + (TimeraComTrigger_1_2 == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511u) + +/*!< Timera registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_PERAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_CMPAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_BCSTR_RESET_VALUE (0x0002u) +#define TIMERA_REG_ICONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_ECONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_FCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_STFLR_RESET_VALUE (0x0000u) +#define TIMERA_REG_BCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_CCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_PCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCUPR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCDOR_RESET_VALUE (0x0000u) + +#define TIMERA_REG_HTSSR0_RESET_VALUE (0x000001FFul) +#define TIMERA_REG_HTSSR1_RESET_VALUE (0x000001FFul) + +/*!< Timera calculate register address of channel */ +#define TIMERA_CALC_REG_ADDR(reg, chl) ((uint32_t)(&(reg)) + (chl)*0x4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize Timera unit + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Cnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TIMERAx->PERAR = TIMERA_REG_PERAR_RESET_VALUE; + TIMERAx->BCSTR = TIMERA_REG_BCSTR_RESET_VALUE; + TIMERAx->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TIMERAx->ECONR = TIMERA_REG_ECONR_RESET_VALUE; + TIMERAx->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TIMERAx->STFLR = TIMERA_REG_STFLR_RESET_VALUE; + TIMERAx->HCONR = TIMERA_REG_HCONR_RESET_VALUE; + TIMERAx->HCUPR = TIMERA_REG_HCUPR_RESET_VALUE; + TIMERAx->HCDOR = TIMERA_REG_HCDOR_RESET_VALUE; + + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, u32Cnt) = TIMERA_REG_CMPAR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 4u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, u32Cnt * 2u) = TIMERA_REG_BCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, u32Cnt) = TIMERA_REG_CCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, u32Cnt) = TIMERA_REG_PCONR_RESET_VALUE; + } + + M4_AOS->TMRA_HTSSR0 = TIMERA_REG_HTSSR0_RESET_VALUE; + M4_AOS->TMRA_HTSSR1 = TIMERA_REG_HTSSR1_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit base function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcBaseInit Pointer to timera base init configuration + ** \arg See the struct #stc_timera_base_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode Unit 1 sync startup invalid + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcBaseInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcBaseInit)) + { + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcBaseInit->enClkDiv)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcBaseInit->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcBaseInit->enCntDir)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcBaseInit->enSyncStartupEn)); + + /* Configure control status register */ + TIMERAx->BCSTR_f.CKDIV = pstcBaseInit->enClkDiv; + TIMERAx->BCSTR_f.MODE = pstcBaseInit->enCntMode; + TIMERAx->BCSTR_f.DIR = pstcBaseInit->enCntDir; + + /* Unit 1 sync startup invalid */ + if ((M4_TMRA1 == TIMERAx) && (Enable == pstcBaseInit->enSyncStartupEn)) + { + enRet = ErrorInvalidMode; + } + else + { + TIMERAx->BCSTR_f.SYNST = pstcBaseInit->enSyncStartupEn; + enRet = Ok; + } + + /* Configure period value register */ + TIMERAx->PERAR = pstcBaseInit->u16PeriodVal; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Cnt Timera current count value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16Cnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current count value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CurrCntVal = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CurrCntVal = (uint16_t)TIMERAx->CNTER; + } + + return u16CurrCntVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera period value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Period Timera period value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->PERAR = u16Period; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera period count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current period value + ** + ******************************************************************************/ +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16PeriodVal = 0u; + + /* Check parameters */ + if (IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16PeriodVal = (uint16_t)TIMERAx->PERAR; + } + + return u16PeriodVal; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera software synchronous startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable synchronous startup + ** \arg Enable Enable synchronous startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SYNC_STARTUP_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.SYNST = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera startup + ** \arg Enable Enable timera startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.START = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCompareInit Pointer to timera compare init configuration + ** \arg See the struct #stc_timera_compare_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCompareInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCompareInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_COUNT_START_OUTPUT(pstcCompareInit->enStartCountOutput)); + DDL_ASSERT(IS_VALID_COUNT_STOP_OUTPUT(pstcCompareInit->enStopCountOutput)); + DDL_ASSERT(IS_VALID_COMPARE_MATCH_OUTPUT(pstcCompareInit->enCompareMatchOutput)); + DDL_ASSERT(IS_VALID_PERIOD_MATCH_OUTPUT(pstcCompareInit->enPeriodMatchOutput)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(pstcCompareInit->enSpecifyOutput)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enCacheEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularCrestTransEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularTroughTransEn)); + + /* Configure port control register */ + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->STAC = pstcCompareInit->enStartCountOutput; + pstcTimeraPort->STPC = pstcCompareInit->enStopCountOutput; + pstcTimeraPort->CMPC = pstcCompareInit->enCompareMatchOutput; + pstcTimeraPort->PERC = pstcCompareInit->enPeriodMatchOutput; + pstcTimeraPort->FORC = pstcCompareInit->enSpecifyOutput; + + /* Configure cache control register */ + if ((TimeraCh1 == enChannel) || (TimeraCh3 == enChannel) || + (TimeraCh5 == enChannel) || (TimeraCh7 == enChannel)) + { + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BSE0 = pstcCompareInit->enTriangularCrestTransEn; + pstcTimeraCache->BSE1 = pstcCompareInit->enTriangularTroughTransEn; + pstcTimeraCache->BEN = pstcCompareInit->enCacheEn; + /* Configure compare cache value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareCacheVal; + } + + /* Configure compare value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareVal; + + /* Set compare output function */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->CAPMD = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] u16CompareVal Timera campare value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = u16CompareVal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera compare value + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CompareVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CompareVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CompareVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare cache value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] u16CompareCache Timera compare cache value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_SET_CACHE_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = u16CompareCache; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare cache + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare cache + ** \arg Enable Enable timera compare cache + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_ENABLE_CACHE_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* Configure cache control register */ + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Specify Timera port output status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enOutputSta Timera port output status + ** \arg TimeraSpecifyOutputInvalid Port output invalid + ** \arg TimeraSpecifyOutputLow Port output low level from next period + ** \arg TimeraSpecifyOutputHigh Port output high level from next period + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(enOutputSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->FORC = enOutputSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare function + ** \arg Enable Enable timera compare function + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->OUTEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit capture function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCapInit Pointer to timera capture init configuration + ** \arg See the struct #stc_timera_capture_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCapInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCapInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureSpecifyEventEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enPwmFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enTrigFilterEn)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enPwmClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enTrigClkDiv)); + + /* Configure capture control register */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->HICP0 = pstcCapInit->enCapturePwmRisingEn; + pstcTimeraCapture->HICP1 = pstcCapInit->enCapturePwmFallingEn; + pstcTimeraCapture->HICP2 = pstcCapInit->enCaptureSpecifyEventEn; + pstcTimeraCapture->NOFICKCP = pstcCapInit->enPwmClkDiv; + pstcTimeraCapture->NOFIENCP = pstcCapInit->enPwmFilterEn; + + /* TIMA__TRIG port capture function only valid for TimeraCh3 */ + if (TimeraCh3 == enChannel) + { + pstcTimeraCapture->HICP3 = pstcCapInit->enCaptureTrigRisingEn; + pstcTimeraCapture->HICP4 = pstcCapInit->enCaptureTrigFallingEn; + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCapInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCapInit->enTrigFilterEn; + } + + /* Set capture input function */ + pstcTimeraCapture->CAPMD = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera capture filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera capture filter input port + ** \arg TimeraFilterSourceCh1 TIMA__PWM1 input port + ** \arg TimeraFilterSourceCh2 TIMA__PWM2 input port + ** \arg TimeraFilterSourceCh3 TIMA__PWM3 input port + ** \arg TimeraFilterSourceCh4 TIMA__PWM4 input port + ** \arg TimeraFilterSourceCh5 TIMA__PWM5 input port + ** \arg TimeraFilterSourceCh6 TIMA__PWM6 input port + ** \arg TimeraFilterSourceCh7 TIMA__PWM7 input port + ** \arg TimeraFilterSourceCh8 TIMA__PWM8 input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera capture filter + ** \arg Enable Enable timera capture filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CAPTURE_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (TimeraFilterSourceTrig == enFilterPort) + { + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + } + else + { + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enFilterPort); + pstcTimeraCapture->NOFIENCP = enNewSta; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera capture value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera capture value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CapVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CapVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CapVal; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit orthogonal coding function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcCodingInit Pointer to timera orthogonal coding configuration + ** \arg See the struct #stc_timera_orthogonal_coding_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCodingInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCodingInit)) + { + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enTrigClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkBClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkAClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enTrigFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkBFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkAFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitUnderflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitUnderflowEn)); + + /* Configure hardware increase event register */ + TIMERAx->HCUPR_f.HCUP0 = pstcCodingInit->enIncClkALowAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP1 = pstcCodingInit->enIncClkALowAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP2 = pstcCodingInit->enIncClkAHighAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP3 = pstcCodingInit->enIncClkAHighAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP4 = pstcCodingInit->enIncClkBLowAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP5 = pstcCodingInit->enIncClkBLowAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP6 = pstcCodingInit->enIncClkBHighAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP7 = pstcCodingInit->enIncClkBHighAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP8 = pstcCodingInit->enIncTrigRisingEn; + TIMERAx->HCUPR_f.HCUP9 = pstcCodingInit->enIncTrigFallingEn; + TIMERAx->HCUPR_f.HCUP10 = pstcCodingInit->enIncSpecifyEventTriggerEn; + TIMERAx->HCUPR_f.HCUP11 = pstcCodingInit->enIncAnotherUnitOverflowEn; + TIMERAx->HCUPR_f.HCUP12 = pstcCodingInit->enIncAnotherUnitUnderflowEn; + + /* Configure hardware decrease event register */ + TIMERAx->HCDOR_f.HCDO0 = pstcCodingInit->enDecClkALowAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO1 = pstcCodingInit->enDecClkALowAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO2 = pstcCodingInit->enDecClkAHighAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO3 = pstcCodingInit->enDecClkAHighAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO4 = pstcCodingInit->enDecClkBLowAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO5 = pstcCodingInit->enDecClkBLowAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO6 = pstcCodingInit->enDecClkBHighAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO7 = pstcCodingInit->enDecClkBHighAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO8 = pstcCodingInit->enDecTrigRisingEn; + TIMERAx->HCDOR_f.HCDO9 = pstcCodingInit->enDecTrigFallingEn; + TIMERAx->HCDOR_f.HCDO10 = pstcCodingInit->enDecSpecifyEventTriggerEn; + TIMERAx->HCDOR_f.HCDO11 = pstcCodingInit->enDecAnotherUnitOverflowEn; + TIMERAx->HCDOR_f.HCDO12 = pstcCodingInit->enDecAnotherUnitUnderflowEn; + + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCodingInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCodingInit->enTrigFilterEn; + TIMERAx->FCONR_f.NOFICKCB = pstcCodingInit->enClkBClkDiv; + TIMERAx->FCONR_f.NOFIENCB = pstcCodingInit->enClkBFilterEn; + TIMERAx->FCONR_f.NOFICKCA = pstcCodingInit->enClkAClkDiv; + TIMERAx->FCONR_f.NOFIENCA = pstcCodingInit->enClkAFilterEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16CodingCnt Timera orthogonal coding value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16CodingCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera orthogonal coding value + ** + ******************************************************************************/ +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CodingCnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CodingCnt = (uint16_t)TIMERAx->CNTER; + } + + return u16CodingCnt; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera orthogonal coding filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera orthogonal coding filter input port + ** \arg TimeraFilterSourceClkA TIMA__CLKA input port + ** \arg TimeraFilterSourceClkB TIMA__CLKB input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera orthogonal coding filter + ** \arg Enable Enable timera orthogonal coding filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CODING_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enFilterPort) + { + case TimeraFilterSourceClkA: + TIMERAx->FCONR_f.NOFIENCA = enNewSta; + break; + case TimeraFilterSourceClkB: + TIMERAx->FCONR_f.NOFIENCB = enNewSta; + break; + case TimeraFilterSourceTrig: + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit hardware trigger event function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwTriggerInit Pointer to timera hardware trigger event configuration + ** \arg See the struct #stc_timera_hw_trigger_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwTriggerInit == NULL + ** + ** \note If sync startup(BCSTR.SYNST) bit set 1 trigger hardware sync startup when HCONR.HSTA1~0 bit set + ** + ******************************************************************************/ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwTriggerInit)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn)); + + /* Configure hardware startup conditions */ + TIMERAx->HCONR_f.HSTA0 = pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn; + + /* Configure hardware stop conditions */ + TIMERAx->HCONR_f.HSTP0 = pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn; + + /* Configure hardware clear conditions */ + TIMERAx->HCONR_f.HCLE0 = pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware startup Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStartup Pointer to timera hardware startup configuration + ** \arg See the struct #stc_timera_hw_startup_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStartup == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStartup)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enSpecifyEventStartupEn)); + + TIMERAx->HCONR_f.HSTA0 = pstcHwStartup->enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwStartup->enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwStartup->enSpecifyEventStartupEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware stop Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStop Pointer to timera hardware stop configuration + ** \arg See the struct #stc_timera_hw_stop_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStop == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStop)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enSpecifyEventStopEn)); + + TIMERAx->HCONR_f.HSTP0 = pstcHwStop->enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwStop->enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwStop->enSpecifyEventStopEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware clear Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwClear Pointer to timera hardware clear configuration + ** \arg See the struct #stc_timera_hw_clear_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwClear == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwClear)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3FallingClearEn)); + + TIMERAx->HCONR_f.HCLE0 = pstcHwClear->enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwClear->enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwClear->enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwClear->enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwClear->enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwClear->enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwClear->enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera interrupt request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enIrq Timera interrupt request + ** \arg TimeraIrqCaptureOrCompareCh1 Channel 1 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh2 Channel 2 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh3 Channel 3 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh4 Channel 4 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh5 Channel 5 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh6 Channel 6 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh7 Channel 7 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh8 Channel 8 interrupt request + ** \arg TimeraIrqOverflow Count overflow interrupt request + ** \arg TimeraIrqUnderflow Count underflow interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera interrupt request + ** \arg Enable Enable timera interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case TimeraIrqCaptureOrCompareCh1: + TIMERAx->ICONR_f.ITEN1 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh2: + TIMERAx->ICONR_f.ITEN2 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh3: + TIMERAx->ICONR_f.ITEN3 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh4: + TIMERAx->ICONR_f.ITEN4 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh5: + TIMERAx->ICONR_f.ITEN5 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh6: + TIMERAx->ICONR_f.ITEN6 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh7: + TIMERAx->ICONR_f.ITEN7 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh8: + TIMERAx->ICONR_f.ITEN8 = enNewSta; + break; + case TimeraIrqOverflow: + TIMERAx->BCSTR_f.ITENOVF = enNewSta; + break; + case TimeraIrqUnderflow: + TIMERAx->BCSTR_f.ITENUDF = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera event request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera event request channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera event request + ** \arg Enable Enable timera event request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + switch (enChannel) + { + case TimeraCh1: + TIMERAx->ECONR_f.ETEN1 = enNewSta; + break; + case TimeraCh2: + TIMERAx->ECONR_f.ETEN2 = enNewSta; + break; + case TimeraCh3: + TIMERAx->ECONR_f.ETEN3 = enNewSta; + break; + case TimeraCh4: + TIMERAx->ECONR_f.ETEN4 = enNewSta; + break; + case TimeraCh5: + TIMERAx->ECONR_f.ETEN5 = enNewSta; + break; + case TimeraCh6: + TIMERAx->ECONR_f.ETEN6 = enNewSta; + break; + case TimeraCh7: + TIMERAx->ECONR_f.ETEN7 = enNewSta; + break; + case TimeraCh8: + TIMERAx->ECONR_f.ETEN8 = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF1; + break; + case TimeraFlagCaptureOrCompareCh2: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF2; + break; + case TimeraFlagCaptureOrCompareCh3: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF3; + break; + case TimeraFlagCaptureOrCompareCh4: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF4; + break; + case TimeraFlagCaptureOrCompareCh5: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF5; + break; + case TimeraFlagCaptureOrCompareCh6: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF6; + break; + case TimeraFlagCaptureOrCompareCh7: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF7; + break; + case TimeraFlagCaptureOrCompareCh8: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF8; + break; + case TimeraFlagOverflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.OVFF; + break; + case TimeraFlagUnderflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.UDFF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + TIMERAx->STFLR_f.CMPF1 = 0u; + break; + case TimeraFlagCaptureOrCompareCh2: + TIMERAx->STFLR_f.CMPF2 = 0u; + break; + case TimeraFlagCaptureOrCompareCh3: + TIMERAx->STFLR_f.CMPF3 = 0u; + break; + case TimeraFlagCaptureOrCompareCh4: + TIMERAx->STFLR_f.CMPF4 = 0u; + break; + case TimeraFlagCaptureOrCompareCh5: + TIMERAx->STFLR_f.CMPF5 = 0u; + break; + case TimeraFlagCaptureOrCompareCh6: + TIMERAx->STFLR_f.CMPF6 = 0u; + break; + case TimeraFlagCaptureOrCompareCh7: + TIMERAx->STFLR_f.CMPF7 = 0u; + break; + case TimeraFlagCaptureOrCompareCh8: + TIMERAx->STFLR_f.CMPF8 = 0u; + break; + case TimeraFlagOverflow: + TIMERAx->BCSTR_f.OVFF = 0u; + break; + case TimeraFlagUnderflow: + TIMERAx->BCSTR_f.UDFF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set counter event trigger source + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR0_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set capture event trigger source + ** + ** \param [in] enTriggerSrc Capture event trigger source + ** \arg 0-511 Used to trigger the capture function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA counter common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR0 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR0 &= ~u32ComTrig; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA capture common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR1 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR1 &= ~u32ComTrig; + } + + return enRet; +} + +//@} // TimeraGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_trng.c b/lib/hc32f460/driver/src/hc32f460_trng.c new file mode 100644 index 000000000000..d06a651e1e1d --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_trng.c @@ -0,0 +1,260 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.c + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_trng.h" +#include "hc32f460_utility.h" +#include + +/** + ******************************************************************************* + ** \addtogroup TrngGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for TRNG load control. */ +#define IS_TRNG_LOAD_CTRL(CTRL) \ +( ((CTRL) == TrngLoadNewInitValue_Enable) || \ + ((CTRL) == TrngLoadNewInitValue_Disable)) + +/*! Parameter validity check for TRNG shift count. */ +#define IS_TRNG_SHIFT_COUNT(COUNT) \ +( ((COUNT) == TrngShiftCount_32) || \ + ((COUNT) == TrngShiftCount_64) || \ + ((COUNT) == TrngShiftCount_128) || \ + ((COUNT) == TrngShiftCount_256)) + + +#define RANDOM_NUM_LENGTH (2u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the TRNG. + ** + ** \param [in] pstcInit Pointer to TRNG initialization structure. + ** \arg enLoadCtrl + ** \- TrngLoadNewInitValue_Enable Data register load new initial value before + ** random number is generated. + ** \- TrngLoadNewInitValue_Disable Data register do not load new initial value + ** before random number is generated. + ** + ** \arg enShiftCount Shift count control bit when capturing random noise. + ** \- TrngShiftCount_32 Shift 32 times. + ** \- TrngShiftCount_64 Shift 64 times. + ** \- TrngShiftCount_128 Shift 128 times. + ** \- TrngShiftCount_256 Shift 256 times. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + /* Parameter validity check */ + DDL_ASSERT(IS_TRNG_LOAD_CTRL(pstcInit->enLoadCtrl)); + DDL_ASSERT(IS_TRNG_SHIFT_COUNT(pstcInit->enShiftCount)); + + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + M4_TRNG->MR_f.LOAD = pstcInit->enLoadCtrl; + M4_TRNG->MR_f.CNT = pstcInit->enShiftCount; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_DeInit(void) +{ + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + /* Set the value of all registers to the reset value. */ + M4_TRNG->CR = 0u; + M4_TRNG->MR = 0x12ul; + M4_TRNG->DR0 = 0x08000000ul; + M4_TRNG->DR0 = 0x08000200ul; +} + +/** + ******************************************************************************* + ** \brief Start TRNG and generate random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout TRNG works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TrngTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu32Random) && (0u != u32Timeout) && (0u != u8Length)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32TrngTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; + + /* wait generation done and check if timeout. */ + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32TrngTimeout) + { + if (bM4_TRNG_CR_RUN == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (Ok == enRet) + { + /* read the random number. */ + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + } + + /* Stop TRNG generating. */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit. */ + bM4_TRNG_CR_EN = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start TRNG only. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_StartIT(void) +{ + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; +} + +/** + ******************************************************************************* + ** \brief Get random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length) +{ + if ((NULL != pu32Random) && (0u != u8Length)) + { + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + + /* Stop TRNG generating */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + } +} + +//@} // TrngGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_usart.c b/lib/hc32f460/driver/src/hc32f460_usart.c new file mode 100644 index 000000000000..cd56ab2883cf --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_usart.c @@ -0,0 +1,1636 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.c + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_usart.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup UsartGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_USART(__USARTx__) \ +( (M4_USART1 == (__USARTx__)) || \ + (M4_USART2 == (__USARTx__)) || \ + (M4_USART3 == (__USARTx__)) || \ + (M4_USART4 == (__USARTx__))) + +/*!< Parameter valid check for USART clock prescale. */ +#define IS_VALID_USART_CLK_DIV(x) \ +( (UsartClkDiv_1 == (x)) || \ + (UsartClkDiv_4 == (x)) || \ + (UsartClkDiv_16 == (x)) || \ + (UsartClkDiv_64 == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_FUNC(x) \ +( (UsartRx == (x)) || \ + (UsartTx == (x)) || \ + (UsartCts == (x)) || \ + (UsartRxInt == (x)) || \ + (UsartTimeOut == (x)) || \ + (UsartSmartCard == (x)) || \ + (UsartSilentMode == (x)) || \ + (UsartTxEmptyInt == (x)) || \ + (UsartTimeOutInt == (x)) || \ + (UsartTxCmpltInt == (x)) || \ + (UsartParityCheck == (x)) || \ + (UsartNoiseFilter == (x)) || \ + (UsartFracBaudrate == (x)) || \ + (UsartMulProcessor == (x)) || \ + (UsartTxAndTxEmptyInt == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_STATUS(x) \ +( (UsartRxMpb == (x)) || \ + (UsartTxEmpty == (x)) || \ + (UsartFrameErr == (x)) || \ + (UsartRxNoEmpty == (x)) || \ + (UsartRxTimeOut == (x)) || \ + (UsartParityErr == (x)) || \ + (UsartOverrunErr == (x)) || \ + (UsartTxComplete == (x))) + +/*!< Parameter valid check for USART clock mode. */ +#define IS_VALID_USART_CLK_MODE(x) \ +( (UsartExtClk == (x)) || \ + (UsartIntClkCkOutput == (x)) || \ + (UsartIntClkCkNoOutput == (x))) + +/*!< Parameter valid check for USART stop bit. */ +#define IS_VALID_USART_STOP_BIT(x) \ +( (UsartOneStopBit == (x)) || \ + (UsartTwoStopBit == (x))) + +/*!< Parameter valid check for USART parity bit. */ +#define IS_VALID_USART_PARITY_BIT(x) \ +( (UsartParityOdd == (x)) || \ + (UsartParityEven == (x)) || \ + (UsartParityNone == (x))) + +/*!< Parameter valid check for USART data length. */ +#define IS_VALID_USART_DATA_LEN(x) \ +( (UsartDataBits8 == (x)) || \ + (UsartDataBits9 == (x))) + +/*!< Parameter valid check for USART data direction. */ +#define IS_VALID_USART_DATA_DIR(x) \ +( (UsartDataLsbFirst == (x)) || \ + (UsartDataMsbFirst == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_SAMPLE_MODE(x) \ +( (UsartSampleBit8 == (x)) || \ + (UsartSampleBit16 == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_HW_FLOW_MODE(x) \ +( (UsartRtsEnable == (x)) || \ + (UsartCtsEnable == (x))) + +/*!< Parameter valid check for USART detect mode. */ +#define IS_VALID_USART_SB_DETECT_MODE(x) \ +( (UsartStartBitLowLvl == (x)) || \ + (UsartStartBitFallEdge == (x))) + +/*!< Parameter valid check for USART mode. */ +#define IS_VALID_USART_MODE(x) \ +( (UsartUartMode == (x)) || \ + (UsartClkSyncMode == (x)) || \ + (UsartSmartCardMode == (x))) + +/*!< Parameter valid check for USART ETU clocks number. */ +#define IS_VALID_USART_ETU_CLK(x) \ +( (UsartScEtuClk32 == (x)) || \ + (UsartScEtuClk64 == (x)) || \ + (UsartScEtuClk128 == (x)) || \ + (UsartScEtuClk256 == (x)) || \ + (UsartScEtuClk372 == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx); +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize UART mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to USART mode configure structure + ** \arg This parameter detail refer @ref stc_usart_uart_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_STOP_BIT(pstcInitCfg->enStopBit)); + DDL_ASSERT(IS_VALID_USART_PARITY_BIT(pstcInitCfg->enParity)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_DATA_LEN(pstcInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(pstcInitCfg->enSampleMode)); + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(pstcInitCfg->enDetectMode)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set USART mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)0ul; + + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR1_f.M = (uint32_t)(pstcInitCfg->enDataLength); + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.STOP = (uint32_t)(pstcInitCfg->enStopBit); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + + switch(pstcInitCfg->enParity) + { + case UsartParityNone: + CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + CR1_f.PS = (uint32_t)0ul; + CR1_f.PCE = (uint32_t)1ul; + break; + case UsartParityOdd: + CR1_f.PS = (uint32_t)1ul; + CR1_f.PCE = (uint32_t)1ul; + break; + default: + break; + } + + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + CR1_f.SBS = (uint32_t)(pstcInitCfg->enDetectMode); + CR1_f.OVER8 = (uint32_t)(pstcInitCfg->enSampleMode); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Initialize clock sync mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to clock sync mode configure structure + ** \arg This parameter detail refer @ref stc_usart_clksync_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set Clock Sync mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize smart card mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to smart card mode configure structure + ** \arg This parameter detail refer @ref stc_usart_sc_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + CR1_f.PCE = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.SCEN = (uint32_t)1ul; /* Set USART mode */ + CR3_f.BCN = (uint32_t)UsartScEtuClk372; /* ETU = 372 * CK */ + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Ok USART is de-initialized normally + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus Choose need get status's flag + ** \arg UsartParityError Parity check error + ** \arg UsartFrameError Frame error + ** \arg UsartOverRunError Overrun error + ** \arg UsartRxRegNoEmpty Rx register is no empty + ** \arg UsartTxComplete Transfer completely + ** \arg UsartTxRegNoEmpty Tx register is no empty + ** \arg UsartRxTimeOut Data receive timeout + ** \arg UsartRxDataType Data is multiple processor id or normal data. + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + DDL_ASSERT(IS_VALID_USART_STATUS(enStatus)); + + return ((USARTx->SR & enStatus) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified USART status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus The specified status + ** \arg UsartParityErr Parity check error + ** \arg UsartFrameErr Frame error + ** \arg UsartOverRunErr Overrun error + ** \arg UsartRxTimeOut Data receive timeout + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enStatus is invalid + ** + ******************************************************************************/ +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch (enStatus) + { + case UsartParityErr: + USARTx->CR1_f.CPE = 1ul; + break; + case UsartFrameErr: + USARTx->CR1_f.CFE = 1ul; + break; + case UsartOverrunErr: + USARTx->CR1_f.CORE = 1ul; + break; + case UsartRxTimeOut: + USARTx->CR1_f.CRTOF = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure USART function. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enFunc USART function selection + ** \arg UsartTimeOut UART RX timeout function + ** \arg UsartTimeOutInt UART RX timeout interrupt function + ** \arg UsartRx UART RX function + ** \arg UsartTx UART TX function + ** \arg UsartSilentMode USART silent function + ** \arg UsartRxInt USART RX interrupt function + ** \arg UsartTxCmpltInt USART TX complete interrupt function + ** \arg UsartTxEmptyInt USART TX empty interrupt function + ** \arg UsartParityCheck USART Parity check function + ** \arg UsartFracBaudrate USART fractional baudrate function + ** \arg UsartNoiseFilter USART noise filter function + ** \param [in] enCmd USART functional state + ** \arg Enable Enable the specified USART function + ** \arg Disable Disable the specified USART function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx == NULL + ** + ******************************************************************************/ +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd) +{ + uint32_t u32Addr; + __IO stc_usart_cr1_field_t CR1_f; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enFunc) + { + case UsartRx: + USARTx->CR1_f.RE = (uint32_t)enCmd; + break; + case UsartRxInt: + USARTx->CR1_f.RIE = (uint32_t)enCmd; + break; + case UsartTx: + USARTx->CR1_f.TE = (uint32_t)enCmd; + break; + case UsartTxEmptyInt: + USARTx->CR1_f.TXEIE = (uint32_t)enCmd; + break; + case UsartTimeOut: + USARTx->CR1_f.RTOE = (uint32_t)enCmd; + break; + case UsartTimeOutInt: + USARTx->CR1_f.RTOIE = (uint32_t)enCmd; + break; + case UsartSilentMode: + USARTx->CR1_f.SLME = (uint32_t)enCmd; + break; + case UsartParityCheck: + USARTx->CR1_f.PCE = (uint32_t)enCmd; + break; + case UsartNoiseFilter: + USARTx->CR1_f.NFE = (uint32_t)enCmd; + break; + case UsartTxCmpltInt: + USARTx->CR1_f.TCIE = (uint32_t)enCmd; + break; + case UsartTxAndTxEmptyInt: + CR1_f = USARTx->CR1_f; + CR1_f.TE = (uint32_t)enCmd; + CR1_f.TXEIE = (uint32_t)enCmd; + u32Addr = (uint32_t)&CR1_f; + USARTx->CR1 = *(__IO uint32_t *)u32Addr; + break; + case UsartFracBaudrate: + USARTx->CR1_f.FBME = (uint32_t)enCmd; + break; + case UsartMulProcessor: + USARTx->CR2_f.MPE = (uint32_t)enCmd; + break; + case UsartSmartCard: + USARTx->CR3_f.SCEN = (uint32_t)enCmd; + break; + case UsartCts: + USARTx->CR3_f.CTSE = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enParity USART parity selection + ** \arg UsartParityNone USART none parity + ** \arg UsartParityEven USART even parity + ** \arg UsartParityOdd USART odd parity + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enParity is invalid + ** + ******************************************************************************/ +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enParity) + { + case UsartParityNone: + USARTx->CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + USARTx->CR1_f.PS = (uint32_t)0ul; + USARTx->CR1_f.PCE = (uint32_t)1u; + break; + case UsartParityOdd: + USARTx->CR1_f.PS = (uint32_t)1ul; + USARTx->CR1_f.PCE = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartParityNone USART none parity + ** \retval UsartParityEven USART even parity + ** \retval UsartParityOdd USART odd parity + ** + ******************************************************************************/ +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx) +{ + en_usart_parity_t enParity = UsartParityNone; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if(0ul == USARTx->CR1_f.PCE) + { + enParity = UsartParityNone; + } + else if(0ul == USARTx->CR1_f.PS) + { + enParity = UsartParityEven; + } + else + { + enParity = UsartParityOdd; + } + + return enParity; +} + +/** + ******************************************************************************* + ** \brief Set USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enSampleMode USART parity selection + ** \arg UsartSampleBit16 16 Bit + ** \arg UsartSampleBit8 8 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(enSampleMode)); + + USARTx->CR1_f.OVER8 = (uint32_t)enSampleMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartSampleBit16 16 Bit + ** \retval UsartSampleBit8 8 Bit + ** + ******************************************************************************/ +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sample_mode_t)USARTx->CR1_f.OVER8; +} + +/** + ******************************************************************************* + ** \brief Set USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDir USART data direction selection + ** \arg UsartDataLsbFirst USART data LSB first + ** \arg UsartDataMsbFirst USART data MSB first + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetTransferDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_DIR(enDir)); + + USARTx->CR1_f.ML = (uint32_t)enDir; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataLsbFirst USART data LSB first + ** \retval UsartDataMsbFirst USART data MSB first + ** + ******************************************************************************/ +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_dir_t)(USARTx->CR1_f.ML); +} + +/** + ******************************************************************************* + ** \brief Set USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDataLen USART data bit length + ** \arg UsartDataBits8 8 Bit + ** \arg UsartDataBits8 9 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_LEN(enDataLen)); + + USARTx->CR1_f.M = (uint32_t)enDataLen; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataBits8 Data bit length:8 Bits + ** \retval UsartDataBits8 Data bit length:9 Bits + ** + ******************************************************************************/ +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_len_t)(USARTx->CR1_f.M); +} + +/** + ******************************************************************************* + ** \brief Set USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkMode USART clock mode selection + ** \arg UsartExtClk Select external clock source + ** \arg UsartIntClkCkOutput Select internal clock source and output clock + ** \arg UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_MODE(enClkMode)); + + USARTx->CR2_f.CLKC = (uint32_t)enClkMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartExtClk Select external clock source + ** \retval UsartIntClkCkOutput Select internal clock source and output clock + ** \retval UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ******************************************************************************/ +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_mode_t)(USARTx->CR2_f.CLKC); +} + +/** + ******************************************************************************* + ** \brief Set USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enMode USART clock mode selection + ** \arg UsartUartMode UART mode + ** \arg UsartClkSyncMode Clock sync mode + ** \arg UsartSmartCardMode Smart card mode + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enMode is invalid + ** + ******************************************************************************/ +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enMode) + { + case UsartUartMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)0ul; + break; + case UsartClkSyncMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)1ul; + break; + case UsartSmartCardMode: + USARTx->CR3_f.SCEN = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartUartMode UART mode + ** \retval UsartClkSyncMode Clock sync mode + ** \retval UsartSmartCardMode Smart card mode + ** + ******************************************************************************/ +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx) +{ + en_usart_mode_t enMode; + + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if (1ul == USARTx->CR3_f.SCEN) + { + enMode = UsartSmartCardMode; + } + else if (1ul == USARTx->CR1_f.MS) + { + enMode = UsartClkSyncMode; + } + else + { + enMode = UsartUartMode; + } + + return enMode; +} + +/** + ******************************************************************************* + ** \brief Set USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStopBit USART stop bit selection + ** \arg UsartOneStopBit 1 Stop Bit + ** \arg UsartTwoStopBits 2 Stop Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_STOP_BIT(enStopBit)); + + USARTx->CR2_f.STOP = (uint32_t)enStopBit; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartOneStopBit 1 Stop Bit + ** \retval UsartTwoStopBits 2 Stop Bit + ** + ******************************************************************************/ +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_stop_bit_t)(USARTx->CR2_f.STOP); +} + +/** + ******************************************************************************* + ** \brief Set USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDetectMode USART start bit detect mode + ** \arg UsartStartBitLowLvl Start bit: RD pin low level + ** \arg UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(enDetectMode)); + + USARTx->CR1_f.SBS = (uint32_t)enDetectMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartStartBitLowLvl Start bit: RD pin low level + ** \retval UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ******************************************************************************/ +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sb_detect_mode_t)(USARTx->CR1_f.SBS); +} + + +/** + ******************************************************************************* + ** \brief Set USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enHwFlowCtrl Hardware flow control + ** \arg UsartRtsEnable Enable RTS + ** \arg UsartCtsEnable Enable CTS + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(enHwFlowCtrl)); + + USARTx->CR3_f.CTSE = (uint32_t)enHwFlowCtrl; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartRtsEnable Enable RTS + ** \retval UsartCtsEnable Enable CTS + ** + ******************************************************************************/ +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_hw_flow_ctrl_t)(USARTx->CR3_f.CTSE); +} + +/** + ******************************************************************************* + ** \brief Set USART clock prescale. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkPrescale USART clock prescale + ** \arg UsartClkDiv_0 PCLK/1 + ** \arg UsartClkDiv_4 PCLK/4 + ** \arg UsartClkDiv_16 PCLK/16 + ** \arg UsartClkDiv_64 PCLK/64 + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(enClkPrescale)); + + USARTx->PR_f.PSC = (uint32_t)enClkPrescale; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock division. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartClkDiv_0 PCLK/1 + ** \retval UsartClkDiv_4 PCLK/4 + ** \retval UsartClkDiv_16 PCLK/16 + ** \retval UsartClkDiv_64 PCLK/64 + ** + ******************************************************************************/ +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_div_t)(USARTx->PR_f.PSC); +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enEtuClk ETU clocks of smart card + ** \arg UsartScEtuClk32 1 etu = 32/f + ** \arg UsartScEtuClk64 1 etu = 64/f + ** \arg UsartScEtuClk93 1 etu = 93/f + ** \arg UsartScEtuClk128 1 etu = 128/f + ** \arg UsartScEtuClk186 1 etu = 186/f + ** \arg UsartScEtuClk256 1 etu = 256/f + ** \arg UsartScEtuClk372 1 etu = 372/f + ** \arg UsartScEtuClk512 1 etu = 512/f + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_ETU_CLK(enEtuClk)); + + USARTx->CR3_f.BCN = (uint32_t)enEtuClk; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartScEtuClk32 1 etu = 32/f + ** \retval UsartScEtuClk64 1 etu = 64/f + ** \retval UsartScEtuClk93 1 etu = 93/f + ** \retval UsartScEtuClk128 1 etu = 128/f + ** \retval UsartScEtuClk186 1 etu = 186/f + ** \retval UsartScEtuClk256 1 etu = 256/f + ** \retval UsartScEtuClk372 1 etu = 372/f + ** \retval UsartScEtuClk512 1 etu = 512/f + ** + ******************************************************************************/ +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sc_etu_clk_t)(USARTx->CR3_f.BCN); +} + +/** + ****************************************************************************** + ** \brief Write UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** + ******************************************************************************/ +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + USARTx->DR_f.TDR = (uint32_t)u16Data; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Read UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t USART_RecData(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return ((uint16_t)(USARTx->DR_f.RDR)); +} + +/** + ******************************************************************************* + ** \brief Set USART baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + if(1ul == USARTx->CR3_f.SCEN) + { + enRet = SetScBaudrate(USARTx, u32Baudrate); + } + else if(1ul == USARTx->CR1_f.MS) + { + enRet = SetClkSyncBaudrate(USARTx, u32Baudrate); + } + else + { + enRet = SetUartBaudrate(USARTx, u32Baudrate); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set UART mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t OVER8 = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + OVER8 = USARTx->CR1_f.OVER8; + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)2ul - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(2048ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set smart card mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t S = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + const uint16_t au16EtuClkCnts[] = {32u, 64u, 93u, 128u, 186u, 256u, 372u, 512u}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + S = au16EtuClkCnts[USARTx->CR3_f.BCN]; + + /* FBME = 0 Calculation formula */ + /* B = C / (2 * S * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * S)) - 1 */ + DIV = ((float)C / ((float)B * (float)S * 2.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / ((2 * S) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((2 * S) * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * S * 512 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * B * S); + DIV_Fraction = (uint32_t)(512ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t C = 0ul; + uint32_t B = 0ul; + uint64_t u64Tmp = 0u; + float32_t DIV = 0.0f; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + if (C > 0ul) + { + B = u32Baudrate; + + /* FBME = 0 Calculation formula */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV = ((float)C / ((float)B * 4.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (4 * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * 1024 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(1024ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval USART clock frequency + ** + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx) +{ + uint32_t u32PClk1 = 0ul; + uint32_t u32UartClk = 0ul; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + u32PClk1 = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.PCLK1S); + u32UartClk = u32PClk1 / (1ul << (2ul * USARTx->PR_f.PSC)); + + return u32UartClk; +} + +//@} // UsartGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_utility.c b/lib/hc32f460/driver/src/hc32f460_utility.c new file mode 100644 index 000000000000..87d82d39a824 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_utility.c @@ -0,0 +1,526 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.c + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_utility.h" + +#if defined(DDL_UTILITY_ENABLE) +asdf +/** + ******************************************************************************* + ** \addtogroup DdlUtilityGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#if defined(PRINT_ENABLE) +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_UART(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x))) + +#define UART_EnableClk(x) \ +do { \ + if (M4_USART1 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART1 = 0ul; \ + } \ + else if (M4_USART2 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART2 = 0ul; \ + } \ + else if (M4_USART3 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART3 = 0ul; \ + } \ + else \ + { \ + M4_MSTP->FCG1_f.USART4 = 0ul; \ + } \ +} while (0) +#endif + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if defined(PRINT_ENABLE) +static M4_USART_TypeDef *m_PrintfDevice; +static uint32_t m_u32PrintfTimeout; +#endif + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +#if defined(PRINT_ENABLE) +/** + ******************************************************************************* + ** \brief UART transmit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] cData The data for transmitting + ** + ** \retval An en_result_t enumeration value: + ** - Ok: Send successfully + ** - ErrorTimeout: Send timeout + ** - ErrorInvalidParameter: The parameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData) +{ + uint32_t u32TxEmpty; + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32Timeout = m_u32PrintfTimeout; + + if (NULL != USARTx) + { + /* Wait TX data register empty */ + do + { + u32Timeout--; + u32TxEmpty = USARTx->SR_f.TXE; + } while ((u32Timeout > 0ul) && (0ul == u32TxEmpty)); + + if (u32TxEmpty > 0ul) + { + USARTx->DR = (uint32_t)cData; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, uint32_t u32Baudrate) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t DIV; + uint64_t u64Tmp; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + uint32_t u32PClk1; + uint32_t u32UartClk; + en_result_t enRet = ErrorInvalidParameter; + + u32PClk1 = SystemCoreClock / (1ul << (M4_SYSREG->CMU_SCFGR_f.PCLK1S)); + u32UartClk = u32PClk1 / (1ul << (2ul * (USARTx->PR_f.PSC))); + + B = u32Baudrate; + C = u32UartClk; + DIV_Fraction = 0ul; + + if ((0ul != C) && (0ul != B)) + { + OVER8 = USARTx->CR1_f.OVER8; + + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if ((DIV < 0.0f) || (DIV_Integer > 0xFFul)) + { + enRet = ErrorInvalidParameter; + } + else + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (2u - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1u) * (uint64_t)B; + DIV_Fraction = (uint32_t)(2048ul * u64Tmp/C - 128ul); + } + + USARTx->CR1_f.FBME = (DIV_Fraction > 0UL) ? 1ul : 0ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + enRet = Ok; + } + } + + return enRet; +} + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + ******************************************************************************* + ** \brief Re-target _write function. + ** + ** \param [in] fd + ** \param [in] data + ** \param [in] size + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) + { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) + { + if (Ok != UartPutChar(m_PrintfDevice, data[i])) + { + break; + } + } + } + + return i ? i : -1; +} + +#else +/** + ******************************************************************************* + ** \brief Re-target fputc function. + ** + ** \param [in] ch + ** \param [in] f + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (Ok == UartPutChar(m_PrintfDevice, (char)ch)) ? ch: -1; +} +#endif + +/** + ******************************************************************************* + ** \brief Debug printf initialization function + ** + ** \param [in] UARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** \param [in] PortInit The pointer of printf port initialization function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_UART(UARTx) && (0ul != u32Baudrate) && (NULL != PortInit)) + { + /* Initialize port */ + PortInit(); + + /* Enable clock */ + UART_EnableClk(UARTx); + + /* Initialize USART */ + UARTx->CR1_f.ML = 0ul; /* LSB */ + UARTx->CR1_f.MS = 0ul; /* UART mode */ + UARTx->CR1_f.OVER8 = 1ul; /* 8bit sampling mode */ + UARTx->CR1_f.M = 0ul; /* 8 bit data length */ + UARTx->CR1_f.PCE = 0ul; /* no parity bit */ + + /* Set baudrate */ + if(Ok != SetUartBaudrate(UARTx, u32Baudrate)) + { + enRet = Error; + } + else + { + UARTx->CR2 = 0ul; /* 1 stop bit, single uart mode */ + UARTx->CR3 = 0ul; /* CTS disable, Smart Card mode disable */ + UARTx->CR1_f.TE = 1ul; /* TX enable */ + + m_PrintfDevice = UARTx; + m_u32PrintfTimeout = (SystemCoreClock / u32Baudrate); + } + } + + return enRet; +} +#endif /* DDL_PRINT_ENABLE */ + +/** + ******************************************************************************* + ** \brief Delay function, delay 1ms approximately + ** + ** \param [in] u32Cnt ms + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1ms(uint32_t u32Cnt) +{ + volatile uint32_t i; + uint32_t u32Cyc; + + u32Cyc = SystemCoreClock; + u32Cyc = u32Cyc / 10000ul; + while (u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief Delay function, delay 1us approximately + ** + ** \param [in] u32Cnt us + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1us(uint32_t u32Cnt) +{ + uint32_t u32Cyc; + volatile uint32_t i; + + if(SystemCoreClock > 10000000ul) + { + u32Cyc = SystemCoreClock / 10000000ul; + while(u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } + } + else + { + while(u32Cnt-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief This function Initializes the interrupt frequency of the SysTick. + ** + ** \param [in] u32Freq SysTick interrupt frequency (1 to 1000). + ** + ** \retval Ok SysTick Initializes succeed + ** \retval Error SysTick Initializes failed + ** + ******************************************************************************/ +__WEAKDEF en_result_t SysTick_Init(uint32_t u32Freq) +{ + en_result_t enRet = Error; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) + { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(SystemCoreClock / u32Freq)) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief This function provides minimum delay (in milliseconds). + ** + ** \param [in] u32Delay Delay specifies the delay time. + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd = u32Delay; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) + { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) + { + tickEnd = tickMax; + } + while ((SysTick_GetTick() - tickStart) < tickEnd) + { + } + } +} + +/** + ******************************************************************************* + ** \brief This function is called to increment a global variable "u32TickCount". + ** \note This variable is incremented in SysTick ISR. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + ******************************************************************************* + ** \brief Provides a tick value in millisecond. + ** + ** \param None + ** + ** \retval Tick value + ** + ******************************************************************************/ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + ******************************************************************************* + ** \brief Suspend SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief Resume SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief ddl assert error handle function + ** + ** \param [in] file Point to the current assert the wrong file + ** \param [in] line Point line assert the wrong file in the current + ** + ******************************************************************************/ +#ifdef __DEBUG +__WEAKDEF void Ddl_AssertHandler(uint8_t *file, int16_t line) +{ + /* Users can re-implement this function to print information */ +#if defined(PRINT_ENABLE) + printf("Wrong parameters value: file %s on line %d\r\n", file, line); +#else + (void)file; + (void)line; +#endif + for (;;) + { + ; + } +} +#endif /* __DEBUG */ + +//@} // DdlUtilityGroup + +#endif /* DDL_UTILITY_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/driver/src/hc32f460_wdt.c b/lib/hc32f460/driver/src/hc32f460_wdt.c new file mode 100644 index 000000000000..db1f1930c0a9 --- /dev/null +++ b/lib/hc32f460/driver/src/hc32f460_wdt.c @@ -0,0 +1,250 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.c + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_wdt.h" +#include "hc32f460_utility.h" + +/** + ******************************************************************************* + ** \addtogroup WdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter validity check for count cycle */ +#define IS_VALID_COUNT_CYCLE(x) \ +( (WdtCountCycle256 == (x)) || \ + (WdtCountCycle4096 == (x)) || \ + (WdtCountCycle16384 == (x)) || \ + (WdtCountCycle65536 == (x))) + +/*!< Parameter validity check for clock division */ +#define IS_VALID_CLOCK_DIV(x) \ +( (WdtPclk3Div4 == (x)) || \ + (WdtPclk3Div64 == (x)) || \ + (WdtPclk3Div128 == (x)) || \ + (WdtPclk3Div256 == (x)) || \ + (WdtPclk3Div512 == (x)) || \ + (WdtPclk3Div1024 == (x)) || \ + (WdtPclk3Div2048 == (x)) || \ + (WdtPclk3Div8192 == (x))) + +/*!< Parameter validity check for allow refresh percent range */ +#define IS_VALID_ALLOW_REFRESH_RANGE(x) \ +( (WdtRefresh100Pct == (x)) || \ + (WdtRefresh0To25Pct == (x)) || \ + (WdtRefresh25To50Pct == (x)) || \ + (WdtRefresh0To50Pct == (x)) || \ + (WdtRefresh50To75Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To75Pct == (x)) || \ + (WdtRefresh25To75Pct == (x)) || \ + (WdtRefresh0To75Pct == (x)) || \ + (WdtRefresh75To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd75To100Pct == (x)) || \ + (WdtRefresh25To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh0To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh50To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To100Pct == (x)) || \ + (WdtRefresh25To100Pct == (x)) || \ + (WdtRefresh0To100Pct == (x))) + +/*!< Parameter validity check for event request type */ +#define IS_VALID_EVENT_REQUEST_TYPE(x) \ +( (WdtTriggerInterruptRequest == (x)) || \ + (WdtTriggerResetRequest == (x))) + +/*!< Parameter validity check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (WdtFlagCountUnderflow == (x)) || \ + (WdtFlagRefreshError == (x))) + +/*!< WDT_RR register refresh key */ +#define WDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define WDT_REFRESH_END_KEY ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize WDT function + ** + ** \param [in] pstcWdtInit Pointer to WDT init configuration + ** \arg See the struct #stc_wdt_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + en_result_t enRet = Ok; + uint32_t regTemp; + + if (NULL == pstcWdtInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_COUNT_CYCLE(pstcWdtInit->enCountCycle)); + DDL_ASSERT(IS_VALID_CLOCK_DIV(pstcWdtInit->enClkDiv)); + DDL_ASSERT(IS_VALID_ALLOW_REFRESH_RANGE(pstcWdtInit->enRefreshRange)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWdtInit->enSleepModeCountEn)); + DDL_ASSERT(IS_VALID_EVENT_REQUEST_TYPE(pstcWdtInit->enRequestType)); + + /* software start mode */ + regTemp = ((((uint32_t)pstcWdtInit->enRequestType) << 31) | \ + (((uint32_t)(bool)(!pstcWdtInit->enSleepModeCountEn)) << 16) | \ + (((uint32_t)pstcWdtInit->enRefreshRange) << 8) | \ + (((uint32_t)pstcWdtInit->enClkDiv) << 4) | \ + ((uint32_t)pstcWdtInit->enCountCycle)); + /* store the new value */ + M4_WDT->CR = regTemp; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief WDT refresh counter(First refresh start count when software start) + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_WDT->RR = WDT_REFRESH_START_KEY; + M4_WDT->RR = WDT_REFRESH_END_KEY; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get WDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t WDT counter current count value + ** + ******************************************************************************/ +uint16_t WDT_GetCountValue(void) +{ + return ((uint16_t)M4_WDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.UDF; + break; + case WdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + M4_WDT->SR_f.UDF = 0u; + break; + case WdtFlagRefreshError: + M4_WDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // WdtGroup + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/lib/hc32f460/mcu/common/hc32_common.h b/lib/hc32f460/mcu/common/hc32_common.h new file mode 100644 index 000000000000..21f27671778d --- /dev/null +++ b/lib/hc32f460/mcu/common/hc32_common.h @@ -0,0 +1,219 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_common.h + ** + ** A detailed description is available at + ** @link Hc32CommonGroup Hc32 Series Comm Part description @endlink + ** + ** - 2018-10-18 CDT First version for Hc32 Series of common part. + ** + ******************************************************************************/ +#ifndef __HC32_COMMON_H__ +#define __HC32_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32CommonGroup Hc32 Series Common Part(HC32COMMON) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief single precision floating point number (4 byte) + ******************************************************************************/ +typedef float float32_t; + +/** + ******************************************************************************* + ** \brief double precision floating point number (8 byte) + ******************************************************************************/ +typedef double float64_t; + +/** + ******************************************************************************* + ** \brief function pointer type to void/void function + ******************************************************************************/ +typedef void (*func_ptr_t)(void); + +/** + ******************************************************************************* + ** \brief function pointer type to void/uint8_t function + ******************************************************************************/ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** + ******************************************************************************* + ** \brief functional state + ******************************************************************************/ +typedef enum en_functional_state +{ + Disable = 0u, + Enable = 1u, +} en_functional_state_t; + +/** + ******************************************************************************* + ** \brief flag status + ******************************************************************************/ +typedef enum en_flag_status +{ + Reset = 0u, + Set = 1u, +} en_flag_status_t, en_int_status_t; + +/** + ******************************************************************************* + ** \brief generic error codes + ******************************************************************************/ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u, ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Device include + ******************************************************************************/ +#if defined(HC32F460) +#include "hc32f460.h" +#include "system_hc32f460.h" +#elif defined(HC32xxxx) +#include "hc32xxxx.h" +#include "system_hc32xxxx.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/*! Weak and Align compiler definition */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __attribute__((aligned (4))) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif /* __UNUSED */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) + /* Usage: void __RAM_FUNC foo(void) */ + #endif /* __RAM_FUNC */ +#elif defined (__ICCARM__) ///< IAR Compiler +#define __WEAKDEF __weak +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#define __NOINLINE _Pragma("optimize = no_inline") +#define __UNUSED __attribute__((unused)) +#define __RAM_FUNC __ramfunc +#elif defined (__CC_ARM) ///< ARM Compiler +#define __WEAKDEF __attribute__((weak)) +#define __ALIGN_BEGIN __align(4) +#define __NOINLINE __attribute__((noinline)) +#define __UNUSED __attribute__((unused)) +/* RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. */ +#define __RAM_FUNC +#else +#error "unsupported compiler!!" +#endif /* __GNUC__ */ + +/*! Pointer correspond to zero value */ +#if !defined (NULL) +#define NULL (0) +#endif + +/*! Memory clear */ +#define MEM_ZERO_STRUCT(x) do { \ + memset((void*)&(x), 0L, (sizeof(x))); \ + }while(0) + +/*! Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10u) << 4u) + ((x) % 10u)) + +/*! BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4u) * 10u) + ((x) & 0x0Fu)) + +/*! Returns the minimum value out of two values */ +#define MIN(x, y) ((x) < (y) ? (x) : (y)) + +/*! Returns the maximum value out of two values */ +#define MAX(x, y) ((x) > (y) ? (x) : (y)) + +/*! Returns the dimension of an array */ +#define ARRAY_SZ(X) (sizeof((X)) / sizeof((X)[0])) + +/*! Check if it is a functional state */ +#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable)) + +#define BIT_SET(value,bit) ((value) |= (bit)) + +#define BIT_CLEAR(value,bit) ((value) &= ~(bit)) + +#define BIT_READ(value,bit) ((value) & (bit)) + +#define BIT_VALUE(index) (1UL << (index)) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32CommonGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/mcu/common/hc32f460.h b/lib/hc32f460/mcu/common/hc32f460.h new file mode 100644 index 000000000000..34f5298cd478 --- /dev/null +++ b/lib/hc32f460/mcu/common/hc32f460.h @@ -0,0 +1,30698 @@ +/** + ****************************************************************************** + * @file HC32F460.h + * @brief Headerfile for HC32F460 series MCU + @verbatim + Change Logs: + Date Author Notes + 2021-10-13 CDT First version + @endverbatim + ****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + **/ + +#ifndef __HC32F460_H__ +#define __HC32F460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< HC32F460 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + Int000_IRQn = 0, + Int001_IRQn = 1, + Int002_IRQn = 2, + Int003_IRQn = 3, + Int004_IRQn = 4, + Int005_IRQn = 5, + Int006_IRQn = 6, + Int007_IRQn = 7, + Int008_IRQn = 8, + Int009_IRQn = 9, + Int010_IRQn = 10, + Int011_IRQn = 11, + Int012_IRQn = 12, + Int013_IRQn = 13, + Int014_IRQn = 14, + Int015_IRQn = 15, + Int016_IRQn = 16, + Int017_IRQn = 17, + Int018_IRQn = 18, + Int019_IRQn = 19, + Int020_IRQn = 20, + Int021_IRQn = 21, + Int022_IRQn = 22, + Int023_IRQn = 23, + Int024_IRQn = 24, + Int025_IRQn = 25, + Int026_IRQn = 26, + Int027_IRQn = 27, + Int028_IRQn = 28, + Int029_IRQn = 29, + Int030_IRQn = 30, + Int031_IRQn = 31, + Int032_IRQn = 32, + Int033_IRQn = 33, + Int034_IRQn = 34, + Int035_IRQn = 35, + Int036_IRQn = 36, + Int037_IRQn = 37, + Int038_IRQn = 38, + Int039_IRQn = 39, + Int040_IRQn = 40, + Int041_IRQn = 41, + Int042_IRQn = 42, + Int043_IRQn = 43, + Int044_IRQn = 44, + Int045_IRQn = 45, + Int046_IRQn = 46, + Int047_IRQn = 47, + Int048_IRQn = 48, + Int049_IRQn = 49, + Int050_IRQn = 50, + Int051_IRQn = 51, + Int052_IRQn = 52, + Int053_IRQn = 53, + Int054_IRQn = 54, + Int055_IRQn = 55, + Int056_IRQn = 56, + Int057_IRQn = 57, + Int058_IRQn = 58, + Int059_IRQn = 59, + Int060_IRQn = 60, + Int061_IRQn = 61, + Int062_IRQn = 62, + Int063_IRQn = 63, + Int064_IRQn = 64, + Int065_IRQn = 65, + Int066_IRQn = 66, + Int067_IRQn = 67, + Int068_IRQn = 68, + Int069_IRQn = 69, + Int070_IRQn = 70, + Int071_IRQn = 71, + Int072_IRQn = 72, + Int073_IRQn = 73, + Int074_IRQn = 74, + Int075_IRQn = 75, + Int076_IRQn = 76, + Int077_IRQn = 77, + Int078_IRQn = 78, + Int079_IRQn = 79, + Int080_IRQn = 80, + Int081_IRQn = 81, + Int082_IRQn = 82, + Int083_IRQn = 83, + Int084_IRQn = 84, + Int085_IRQn = 85, + Int086_IRQn = 86, + Int087_IRQn = 87, + Int088_IRQn = 88, + Int089_IRQn = 89, + Int090_IRQn = 90, + Int091_IRQn = 91, + Int092_IRQn = 92, + Int093_IRQn = 93, + Int094_IRQn = 94, + Int095_IRQn = 95, + Int096_IRQn = 96, + Int097_IRQn = 97, + Int098_IRQn = 98, + Int099_IRQn = 99, + Int100_IRQn = 100, + Int101_IRQn = 101, + Int102_IRQn = 102, + Int103_IRQn = 103, + Int104_IRQn = 104, + Int105_IRQn = 105, + Int106_IRQn = 106, + Int107_IRQn = 107, + Int108_IRQn = 108, + Int109_IRQn = 109, + Int110_IRQn = 110, + Int111_IRQn = 111, + Int112_IRQn = 112, + Int113_IRQn = 113, + Int114_IRQn = 114, + Int115_IRQn = 115, + Int116_IRQn = 116, + Int117_IRQn = 117, + Int118_IRQn = 118, + Int119_IRQn = 119, + Int120_IRQn = 120, + Int121_IRQn = 121, + Int122_IRQn = 122, + Int123_IRQn = 123, + Int124_IRQn = 124, + Int125_IRQn = 125, + Int126_IRQn = 126, + Int127_IRQn = 127, + Int128_IRQn = 128, + Int129_IRQn = 129, + Int130_IRQn = 130, + Int131_IRQn = 131, + Int132_IRQn = 132, + Int133_IRQn = 133, + Int134_IRQn = 134, + Int135_IRQn = 135, + Int136_IRQn = 136, + Int137_IRQn = 137, + Int138_IRQn = 138, + Int139_IRQn = 139, + Int140_IRQn = 140, + Int141_IRQn = 141, + Int142_IRQn = 142, + Int143_IRQn = 143, + +}IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum en_event_src +{ + EVT_SWI_IRQ0 = 0U, + EVT_SWI_IRQ1 = 1U, + EVT_SWI_IRQ2 = 2U, + EVT_SWI_IRQ3 = 3U, + EVT_SWI_IRQ4 = 4U, + EVT_SWI_IRQ5 = 5U, + EVT_SWI_IRQ6 = 6U, + EVT_SWI_IRQ7 = 7U, + EVT_SWI_IRQ8 = 8U, + EVT_SWI_IRQ9 = 9U, + EVT_SWI_IRQ10 = 10U, + EVT_SWI_IRQ11 = 11U, + EVT_SWI_IRQ12 = 12U, + EVT_SWI_IRQ13 = 13U, + EVT_SWI_IRQ14 = 14U, + EVT_SWI_IRQ15 = 15U, + EVT_SWI_IRQ16 = 16U, + EVT_SWI_IRQ17 = 17U, + EVT_SWI_IRQ18 = 18U, + EVT_SWI_IRQ19 = 19U, + EVT_SWI_IRQ20 = 20U, + EVT_SWI_IRQ21 = 21U, + EVT_SWI_IRQ22 = 22U, + EVT_SWI_IRQ23 = 23U, + EVT_SWI_IRQ24 = 24U, + EVT_SWI_IRQ25 = 25U, + EVT_SWI_IRQ26 = 26U, + EVT_SWI_IRQ27 = 27U, + EVT_SWI_IRQ28 = 28U, + EVT_SWI_IRQ29 = 29U, + EVT_SWI_IRQ30 = 30U, + EVT_SWI_IRQ31 = 31U, + + /* External Interrupt. */ + EVT_PORT_EIRQ0 = 0U, + EVT_PORT_EIRQ1 = 1U, + EVT_PORT_EIRQ2 = 2U, + EVT_PORT_EIRQ3 = 3U, + EVT_PORT_EIRQ4 = 4U, + EVT_PORT_EIRQ5 = 5U, + EVT_PORT_EIRQ6 = 6U, + EVT_PORT_EIRQ7 = 7U, + EVT_PORT_EIRQ8 = 8U, + EVT_PORT_EIRQ9 = 9U, + EVT_PORT_EIRQ10 = 10U, + EVT_PORT_EIRQ11 = 11U, + EVT_PORT_EIRQ12 = 12U, + EVT_PORT_EIRQ13 = 13U, + EVT_PORT_EIRQ14 = 14U, + EVT_PORT_EIRQ15 = 15U, + + /* DMAC */ + EVT_DMA1_TC0 = 32U, + EVT_DMA1_TC1 = 33U, + EVT_DMA1_TC2 = 34U, + EVT_DMA1_TC3 = 35U, + EVT_DMA2_TC0 = 36U, + EVT_DMA2_TC1 = 37U, + EVT_DMA2_TC2 = 38U, + EVT_DMA2_TC3 = 39U, + EVT_DMA1_BTC0 = 40U, + EVT_DMA1_BTC1 = 41U, + EVT_DMA1_BTC2 = 42U, + EVT_DMA1_BTC3 = 43U, + EVT_DMA2_BTC0 = 44U, + EVT_DMA2_BTC1 = 45U, + EVT_DMA2_BTC2 = 46U, + EVT_DMA2_BTC3 = 47U, + + /* EFM */ + EVT_EFM_OPTEND = 52U, + + /* USB SOF */ + EVT_USBFS_SOF = 53U, + + /* DCU */ + EVT_DCU1 = 55U, + EVT_DCU2 = 56U, + EVT_DCU3 = 57U, + EVT_DCU4 = 58U, + + /* TIMER 0 */ + EVT_TMR01_GCMA = 64U, + EVT_TMR01_GCMB = 65U, + EVT_TMR02_GCMA = 66U, + EVT_TMR02_GCMB = 67U, + + /* RTC */ + EVT_RTC_ALM = 81U, + EVT_RTC_PRD = 82U, + + /* TIMER 6 */ + EVT_TMR61_GCMA = 96U, + EVT_TMR61_GCMB = 97U, + EVT_TMR61_GCMC = 98U, + EVT_TMR61_GCMD = 99U, + EVT_TMR61_GCME = 100U, + EVT_TMR61_GCMF = 101U, + EVT_TMR61_GOVF = 102U, + EVT_TMR61_GUDF = 103U, + EVT_TMR61_SCMA = 107U, + EVT_TMR61_SCMB = 108U, + EVT_TMR62_GCMA = 112U, + EVT_TMR62_GCMB = 113U, + EVT_TMR62_GCMC = 114U, + EVT_TMR62_GCMD = 115U, + EVT_TMR62_GCME = 116U, + EVT_TMR62_GCMF = 117U, + EVT_TMR62_GOVF = 118U, + EVT_TMR62_GUDF = 119U, + EVT_TMR62_SCMA = 123U, + EVT_TMR62_SCMB = 124U, + EVT_TMR63_GCMA = 128U, + EVT_TMR63_GCMB = 129U, + EVT_TMR63_GCMC = 130U, + EVT_TMR63_GCMD = 131U, + EVT_TMR63_GCME = 132U, + EVT_TMR63_GCMF = 133U, + EVT_TMR63_GOVF = 134U, + EVT_TMR63_GUDF = 135U, + EVT_TMR63_SCMA = 139U, + EVT_TMR63_SCMB = 140U, + + /* TIMER A */ + EVT_TMRA1_OVF = 256U, + EVT_TMRA1_UDF = 257U, + EVT_TMRA1_CMP = 258U, + EVT_TMRA2_OVF = 259U, + EVT_TMRA2_UDF = 260U, + EVT_TMRA2_CMP = 261U, + EVT_TMRA3_OVF = 262U, + EVT_TMRA3_UDF = 263U, + EVT_TMRA3_CMP = 264U, + EVT_TMRA4_OVF = 265U, + EVT_TMRA4_UDF = 266U, + EVT_TMRA4_CMP = 267U, + EVT_TMRA5_OVF = 268U, + EVT_TMRA5_UDF = 269U, + EVT_TMRA5_CMP = 270U, + EVT_TMRA6_OVF = 272U, + EVT_TMRA6_UDF = 273U, + EVT_TMRA6_CMP = 274U, + + /* USART */ + EVT_USART1_EI = 278U, + EVT_USART1_RI = 279U, + EVT_USART1_TI = 280U, + EVT_USART1_TCI = 281U, + EVT_USART1_RTO = 282U, + EVT_USART2_EI = 283U, + EVT_USART2_RI = 284U, + EVT_USART2_TI = 285U, + EVT_USART2_TCI = 286U, + EVT_USART2_RTO = 287U, + EVT_USART3_EI = 288U, + EVT_USART3_RI = 289U, + EVT_USART3_TI = 290U, + EVT_USART3_TCI = 291U, + EVT_USART3_RTO = 292U, + EVT_USART4_EI = 293U, + EVT_USART4_RI = 294U, + EVT_USART4_TI = 295U, + EVT_USART4_TCI = 296U, + EVT_USART4_RTO = 297U, + + /* SPI */ + EVT_SPI1_SPRI = 299U, + EVT_SPI1_SPTI = 300U, + EVT_SPI1_SPII = 301U, + EVT_SPI1_SPEI = 302U, + EVT_SPI1_SPTEND = 303U, + EVT_SPI2_SPRI = 304U, + EVT_SPI2_SPTI = 305U, + EVT_SPI2_SPII = 306U, + EVT_SPI2_SPEI = 307U, + EVT_SPI2_SPTEND = 308U, + EVT_SPI3_SPRI = 309U, + EVT_SPI3_SPTI = 310U, + EVT_SPI3_SPII = 311U, + EVT_SPI3_SPEI = 312U, + EVT_SPI3_SPTEND = 313U, + EVT_SPI4_SPRI = 314U, + EVT_SPI4_SPTI = 315U, + EVT_SPI4_SPII = 316U, + EVT_SPI4_SPEI = 317U, + EVT_SPI4_SPTEND = 318U, + + /* AOS */ + EVT_AOS_STRG = 319U, + + /* TIMER 4 */ + EVT_TMR41_SCMUH = 368U, + EVT_TMR41_SCMUL = 369U, + EVT_TMR41_SCMVH = 370U, + EVT_TMR41_SCMVL = 371U, + EVT_TMR41_SCMWH = 372U, + EVT_TMR41_SCMWL = 373U, + EVT_TMR42_SCMUH = 374U, + EVT_TMR42_SCMUL = 375U, + EVT_TMR42_SCMVH = 376U, + EVT_TMR42_SCMVL = 377U, + EVT_TMR42_SCMWH = 378U, + EVT_TMR42_SCMWL = 379U, + EVT_TMR43_SCMUH = 384U, + EVT_TMR43_SCMUL = 385U, + EVT_TMR43_SCMVH = 386U, + EVT_TMR43_SCMVL = 387U, + EVT_TMR43_SCMWH = 388U, + EVT_TMR43_SCMWL = 389U, + + /* EVENT PORT */ + EVT_EVENT_PORT1 = 394U, + EVT_EVENT_PORT2 = 395U, + EVT_EVENT_PORT3 = 396U, + EVT_EVENT_PORT4 = 397U, + + /* I2S */ + EVT_I2S1_TXIRQOUT = 400U, + EVT_I2S1_RXIRQOUT = 401U, + EVT_I2S2_TXIRQOUT = 403U, + EVT_I2S2_RXIRQOUT = 404U, + EVT_I2S3_TXIRQOUT = 406U, + EVT_I2S3_RXIRQOUT = 407U, + EVT_I2S4_TXIRQOUT = 409U, + EVT_I2S4_RXIRQOUT = 410U, + + /* COMPARATOR */ + EVT_ACMP1 = 416U, + EVT_ACMP2 = 417U, + EVT_ACMP3 = 418U, + + /* I2C */ + EVT_I2C1_RXI = 420U, + EVT_I2C1_TXI = 421U, + EVT_I2C1_TEI = 422U, + EVT_I2C1_EEI = 423U, + EVT_I2C2_RXI = 424U, + EVT_I2C2_TXI = 425U, + EVT_I2C2_TEI = 426U, + EVT_I2C2_EEI = 427U, + EVT_I2C3_RXI = 428U, + EVT_I2C3_TXI = 429U, + EVT_I2C3_TEI = 430U, + EVT_I2C3_EEI = 431U, + + /* PVD */ + EVT_PVD_PVD1 = 433U, + EVT_PVD_PVD2 = 434U, + + /* OTS */ + EVT_OTS = 435U, + + /* WDT */ + EVT_WDT_REFUDF = 439U, + + /* ADC */ + EVT_ADC1_EOCA = 448U, + EVT_ADC1_EOCB = 449U, + EVT_ADC1_CHCMP = 450U, + EVT_ADC1_SEQCMP = 451U, + EVT_ADC2_EOCA = 452U, + EVT_ADC2_EOCB = 453U, + EVT_ADC2_CHCMP = 454U, + EVT_ADC2_SEQCMP = 455U, + + /* TRNG */ + EVT_TRNG_END = 456U, + + /* SDIO */ + EVT_SDIOC1_DMAR = 480U, + EVT_SDIOC1_DMAW = 481U, + EVT_SDIOC2_DMAR = 483U, + EVT_SDIOC2_DMAW = 484U, + EVT_MAX = 511U, +}en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum en_int_src +{ + INT_SWI_IRQ0 = 0U, + INT_SWI_IRQ1 = 1U, + INT_SWI_IRQ2 = 2U, + INT_SWI_IRQ3 = 3U, + INT_SWI_IRQ4 = 4U, + INT_SWI_IRQ5 = 5U, + INT_SWI_IRQ6 = 6U, + INT_SWI_IRQ7 = 7U, + INT_SWI_IRQ8 = 8U, + INT_SWI_IRQ9 = 9U, + INT_SWI_IRQ10 = 10U, + INT_SWI_IRQ11 = 11U, + INT_SWI_IRQ12 = 12U, + INT_SWI_IRQ13 = 13U, + INT_SWI_IRQ14 = 14U, + INT_SWI_IRQ15 = 15U, + INT_SWI_IRQ16 = 16U, + INT_SWI_IRQ17 = 17U, + INT_SWI_IRQ18 = 18U, + INT_SWI_IRQ19 = 19U, + INT_SWI_IRQ20 = 20U, + INT_SWI_IRQ21 = 21U, + INT_SWI_IRQ22 = 22U, + INT_SWI_IRQ23 = 23U, + INT_SWI_IRQ24 = 24U, + INT_SWI_IRQ25 = 25U, + INT_SWI_IRQ26 = 26U, + INT_SWI_IRQ27 = 27U, + INT_SWI_IRQ28 = 28U, + INT_SWI_IRQ29 = 29U, + INT_SWI_IRQ30 = 30U, + INT_SWI_IRQ31 = 31U, + + /* External Interrupt. */ + INT_PORT_EIRQ0 = 0U, + INT_PORT_EIRQ1 = 1U, + INT_PORT_EIRQ2 = 2U, + INT_PORT_EIRQ3 = 3U, + INT_PORT_EIRQ4 = 4U, + INT_PORT_EIRQ5 = 5U, + INT_PORT_EIRQ6 = 6U, + INT_PORT_EIRQ7 = 7U, + INT_PORT_EIRQ8 = 8U, + INT_PORT_EIRQ9 = 9U, + INT_PORT_EIRQ10 = 10U, + INT_PORT_EIRQ11 = 11U, + INT_PORT_EIRQ12 = 12U, + INT_PORT_EIRQ13 = 13U, + INT_PORT_EIRQ14 = 14U, + INT_PORT_EIRQ15 = 15U, + + /* DMAC */ + INT_DMA1_TC0 = 32U, + INT_DMA1_TC1 = 33U, + INT_DMA1_TC2 = 34U, + INT_DMA1_TC3 = 35U, + INT_DMA2_TC0 = 36U, + INT_DMA2_TC1 = 37U, + INT_DMA2_TC2 = 38U, + INT_DMA2_TC3 = 39U, + INT_DMA1_BTC0 = 40U, + INT_DMA1_BTC1 = 41U, + INT_DMA1_BTC2 = 42U, + INT_DMA1_BTC3 = 43U, + INT_DMA2_BTC0 = 44U, + INT_DMA2_BTC1 = 45U, + INT_DMA2_BTC2 = 46U, + INT_DMA2_BTC3 = 47U, + INT_DMA1_ERR = 48U, + INT_DMA2_ERR = 49U, + + /* EFM */ + INT_EFM_PEERR = 50U, + INT_EFM_COLERR = 51U, + INT_EFM_OPTEND = 52U, + + /* QSPI */ + INT_QSPI_INTR = 54U, + + /* DCU */ + INT_DCU1 = 55U, + INT_DCU2 = 56U, + INT_DCU3 = 57U, + INT_DCU4 = 58U, + + /* TIMER 0 */ + INT_TMR01_GCMA = 64U, + INT_TMR01_GCMB = 65U, + INT_TMR02_GCMA = 66U, + INT_TMR02_GCMB = 67U, + + /* RTC */ + INT_RTC_ALM = 81U, + INT_RTC_PRD = 82U, + + /* XTAL32 stop */ + INT_XTAL32_STOP = 84U, + + /* XTAL stop */ + INT_XTAL_STOP = 85U, + + /* wake-up timer */ + INT_WKTM_PRD = 86U, + + /* SWDT */ + INT_SWDT_REFUDF = 87U, + + /* TIMER 6 */ + INT_TMR61_GCMA = 96U, + INT_TMR61_GCMB = 97U, + INT_TMR61_GCMC = 98U, + INT_TMR61_GCMD = 99U, + INT_TMR61_GCME = 100U, + INT_TMR61_GCMF = 101U, + INT_TMR61_GOVF = 102U, + INT_TMR61_GUDF = 103U, + INT_TMR61_GDTE = 104U, + INT_TMR61_SCMA = 107U, + INT_TMR61_SCMB = 108U, + INT_TMR62_GCMA = 112U, + INT_TMR62_GCMB = 113U, + INT_TMR62_GCMC = 114U, + INT_TMR62_GCMD = 115U, + INT_TMR62_GCME = 116U, + INT_TMR62_GCMF = 117U, + INT_TMR62_GOVF = 118U, + INT_TMR62_GUDF = 119U, + INT_TMR62_GDTE = 120U, + INT_TMR62_SCMA = 123U, + INT_TMR62_SCMB = 124U, + INT_TMR63_GCMA = 128U, + INT_TMR63_GCMB = 129U, + INT_TMR63_GCMC = 130U, + INT_TMR63_GCMD = 131U, + INT_TMR63_GCME = 132U, + INT_TMR63_GCMF = 133U, + INT_TMR63_GOVF = 134U, + INT_TMR63_GUDF = 135U, + INT_TMR63_GDTE = 136U, + INT_TMR63_SCMA = 139U, + INT_TMR63_SCMB = 140U, + + /* TIMER A */ + INT_TMRA1_OVF = 256U, + INT_TMRA1_UDF = 257U, + INT_TMRA1_CMP = 258U, + INT_TMRA2_OVF = 259U, + INT_TMRA2_UDF = 260U, + INT_TMRA2_CMP = 261U, + INT_TMRA3_OVF = 262U, + INT_TMRA3_UDF = 263U, + INT_TMRA3_CMP = 264U, + INT_TMRA4_OVF = 265U, + INT_TMRA4_UDF = 266U, + INT_TMRA4_CMP = 267U, + INT_TMRA5_OVF = 268U, + INT_TMRA5_UDF = 269U, + INT_TMRA5_CMP = 270U, + INT_TMRA6_OVF = 272U, + INT_TMRA6_UDF = 273U, + INT_TMRA6_CMP = 274U, + + /* USB FS */ + INT_USBFS_GLB = 275U, + + /* USRAT */ + INT_USART1_EI = 278U, + INT_USART1_RI = 279U, + INT_USART1_TI = 280U, + INT_USART1_TCI = 281U, + INT_USART1_RTO = 282U, + INT_USART1_WUPI = 432U, + INT_USART2_EI = 283U, + INT_USART2_RI = 284U, + INT_USART2_TI = 285U, + INT_USART2_TCI = 286U, + INT_USART2_RTO = 287U, + INT_USART3_EI = 288U, + INT_USART3_RI = 289U, + INT_USART3_TI = 290U, + INT_USART3_TCI = 291U, + INT_USART3_RTO = 292U, + INT_USART4_EI = 293U, + INT_USART4_RI = 294U, + INT_USART4_TI = 295U, + INT_USART4_TCI = 296U, + INT_USART4_RTO = 297U, + + /* SPI */ + INT_SPI1_SPRI = 299U, + INT_SPI1_SPTI = 300U, + INT_SPI1_SPII = 301U, + INT_SPI1_SPEI = 302U, + INT_SPI2_SPRI = 304U, + INT_SPI2_SPTI = 305U, + INT_SPI2_SPII = 306U, + INT_SPI2_SPEI = 307U, + INT_SPI3_SPRI = 309U, + INT_SPI3_SPTI = 310U, + INT_SPI3_SPII = 311U, + INT_SPI3_SPEI = 312U, + INT_SPI4_SPRI = 314U, + INT_SPI4_SPTI = 315U, + INT_SPI4_SPII = 316U, + INT_SPI4_SPEI = 317U, + + /* TIMER 4 */ + INT_TMR41_GCMUH = 320U, + INT_TMR41_GCMUL = 321U, + INT_TMR41_GCMVH = 322U, + INT_TMR41_GCMVL = 323U, + INT_TMR41_GCMWH = 324U, + INT_TMR41_GCMWL = 325U, + INT_TMR41_GOVF = 326U, + INT_TMR41_GUDF = 327U, + INT_TMR41_RLOU = 328U, + INT_TMR41_RLOV = 329U, + INT_TMR41_RLOW = 330U, + INT_TMR42_GCMUH = 336U, + INT_TMR42_GCMUL = 337U, + INT_TMR42_GCMVH = 338U, + INT_TMR42_GCMVL = 339U, + INT_TMR42_GCMWH = 340U, + INT_TMR42_GCMWL = 341U, + INT_TMR42_GOVF = 342U, + INT_TMR42_GUDF = 343U, + INT_TMR42_RLOU = 344U, + INT_TMR42_RLOV = 345U, + INT_TMR42_RLOW = 346U, + INT_TMR43_GCMUH = 352U, + INT_TMR43_GCMUL = 353U, + INT_TMR43_GCMVH = 354U, + INT_TMR43_GCMVL = 355U, + INT_TMR43_GCMWH = 356U, + INT_TMR43_GCMWL = 357U, + INT_TMR43_GOVF = 358U, + INT_TMR43_GUDF = 359U, + INT_TMR43_RLOU = 360U, + INT_TMR43_RLOV = 361U, + INT_TMR43_RLOW = 362U, + + /* EMB */ + INT_EMB_GR0 = 390U, + INT_EMB_GR1 = 391U, + INT_EMB_GR2 = 392U, + INT_EMB_GR3 = 393U, + + /* EVENT PORT */ + INT_EVENT_PORT1 = 394U, + INT_EVENT_PORT2 = 395U, + INT_EVENT_PORT3 = 396U, + INT_EVENT_PORT4 = 397U, + + /* I2S */ + INT_I2S1_TXIRQOUT = 400U, + INT_I2S1_RXIRQOUT = 401U, + INT_I2S1_ERRIRQOUT = 402U, + INT_I2S2_TXIRQOUT = 403U, + INT_I2S2_RXIRQOUT = 404U, + INT_I2S2_ERRIRQOUT = 405U, + INT_I2S3_TXIRQOUT = 406U, + INT_I2S3_RXIRQOUT = 407U, + INT_I2S3_ERRIRQOUT = 408U, + INT_I2S4_TXIRQOUT = 409U, + INT_I2S4_RXIRQOUT = 410U, + INT_I2S4_ERRIRQOUT = 411U, + + /* COMPARATOR */ + INT_ACMP1 = 416U, + INT_ACMP2 = 417U, + INT_ACMP3 = 418U, + + /* I2C */ + INT_I2C1_RXI = 420U, + INT_I2C1_TXI = 421U, + INT_I2C1_TEI = 422U, + INT_I2C1_EEI = 423U, + INT_I2C2_RXI = 424U, + INT_I2C2_TXI = 425U, + INT_I2C2_TEI = 426U, + INT_I2C2_EEI = 427U, + INT_I2C3_RXI = 428U, + INT_I2C3_TXI = 429U, + INT_I2C3_TEI = 430U, + INT_I2C3_EEI = 431U, + + /* PVD */ + INT_PVD_PVD1 = 433U, + INT_PVD_PVD2 = 434U, + + /* Temp. sensor */ + INT_OTS = 435U, + + /* FCM */ + INT_FCMFERRI = 436U, + INT_FCMMENDI = 437U, + INT_FCMCOVFI = 438U, + + /* WDT */ + INT_WDT_REFUDF = 439U, + + /* ADC */ + INT_ADC1_EOCA = 448U, + INT_ADC1_EOCB = 449U, + INT_ADC1_CHCMP = 450U, + INT_ADC1_SEQCMP = 451U, + INT_ADC2_EOCA = 452U, + INT_ADC2_EOCB = 453U, + INT_ADC2_CHCMP = 454U, + INT_ADC2_SEQCMP = 455U, + + /* TRNG */ + INT_TRNG_END = 456U, + + /* SDIOC */ + INT_SDIOC1_SD = 482U, + INT_SDIOC2_SD = 485U, + + /* CAN */ + INT_CAN_INT = 486U, + + INT_MAX = 511U, +}en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint8_t STRT : 1; + uint8_t RESERVED1 : 7; +} stc_adc_str_field_t; + +typedef struct +{ + __IO uint16_t MS : 2; + uint16_t RESERVED2 : 2; + __IO uint16_t ACCSEL : 2; + __IO uint16_t CLREN : 1; + __IO uint16_t DFMT : 1; + __IO uint16_t AVCNT : 3; + uint16_t RESERVED11 : 5; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 2; + __IO uint16_t RSCHSEL : 1; + uint16_t RESERVED3 :13; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint16_t TRGSELA : 3; + uint16_t RESERVED3 : 4; + __IO uint16_t TRGENA : 1; + __IO uint16_t TRGSELB : 3; + uint16_t RESERVED11 : 4; + __IO uint16_t TRGENB : 1; +} stc_adc_trgsr_field_t; + +typedef struct +{ + __IO uint16_t CHSELA16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselra1_field_t; + +typedef struct +{ + __IO uint16_t CHSELB16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselrb1_field_t; + +typedef struct +{ + __IO uint16_t AVCHSEL16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_avchselr1_field_t; + +typedef struct +{ + __IO uint16_t CH00MUX : 4; + __IO uint16_t CH01MUX : 4; + __IO uint16_t CH02MUX : 4; + __IO uint16_t CH03MUX : 4; +} stc_adc_chmuxr0_field_t; + +typedef struct +{ + __IO uint16_t CH04MUX : 4; + __IO uint16_t CH05MUX : 4; + __IO uint16_t CH06MUX : 4; + __IO uint16_t CH07MUX : 4; +} stc_adc_chmuxr1_field_t; + +typedef struct +{ + __IO uint16_t CH08MUX : 4; + __IO uint16_t CH09MUX : 4; + __IO uint16_t CH10MUX : 4; + __IO uint16_t CH11MUX : 4; +} stc_adc_chmuxr2_field_t; + +typedef struct +{ + __IO uint16_t CH12MUX : 4; + __IO uint16_t CH13MUX : 4; + __IO uint16_t CH14MUX : 4; + __IO uint16_t CH15MUX : 4; +} stc_adc_chmuxr3_field_t; + +typedef struct +{ + __IO uint8_t EOCAF : 1; + __IO uint8_t EOCBF : 1; + uint8_t RESERVED2 : 6; +} stc_adc_isr_field_t; + +typedef struct +{ + __IO uint8_t EOCAIEN : 1; + __IO uint8_t EOCBIEN : 1; + uint8_t RESERVED2 : 6; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint16_t SYNCEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t SYNCMD : 3; + uint16_t RESERVED7 : 1; + __IO uint16_t SYNCDLY : 8; +} stc_adc_synccr_field_t; + +typedef struct +{ + __IO uint16_t AWDEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t AWDMD : 1; + uint16_t RESERVED5 : 1; + __IO uint16_t AWDSS : 2; + __IO uint16_t AWDIEN : 1; + uint16_t RESERVED9 : 7; +} stc_adc_awdcr_field_t; + +typedef struct +{ + __IO uint16_t AWDCH16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdchsr1_field_t; + +typedef struct +{ + __IO uint16_t AWDF16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdsr1_field_t; + +typedef struct +{ + __IO uint16_t PGACTL : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgacr_field_t; + +typedef struct +{ + __IO uint16_t GAIN : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgagsr_field_t; + +typedef struct +{ + __IO uint16_t PGAINSEL : 9; + uint16_t RESERVED9 : 7; +} stc_adc_pgainsr0_field_t; + +typedef struct +{ + __IO uint16_t PGAVSSEN : 1; + uint16_t RESERVED1 :15; +} stc_adc_pgainsr1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; + uint32_t RESERVED2 :30; +} stc_aes_cr_field_t; + +typedef struct +{ + __O uint32_t STRG : 1; + uint32_t RESERVED1 :31; +} stc_aos_int_sfttrg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu3_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu4_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel3_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma_trgselrc_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr6_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr0_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_pevnttrgsr12_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_pevnttrgsr34_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmra_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_ots_trg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc1_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc2_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg1_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg2_field_t; + +typedef struct +{ + __IO uint32_t PDIR00 : 1; + __IO uint32_t PDIR01 : 1; + __IO uint32_t PDIR02 : 1; + __IO uint32_t PDIR03 : 1; + __IO uint32_t PDIR04 : 1; + __IO uint32_t PDIR05 : 1; + __IO uint32_t PDIR06 : 1; + __IO uint32_t PDIR07 : 1; + __IO uint32_t PDIR08 : 1; + __IO uint32_t PDIR09 : 1; + __IO uint32_t PDIR10 : 1; + __IO uint32_t PDIR11 : 1; + __IO uint32_t PDIR12 : 1; + __IO uint32_t PDIR13 : 1; + __IO uint32_t PDIR14 : 1; + __IO uint32_t PDIR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntdirr_field_t; + +typedef struct +{ + __I uint32_t PIN00 : 1; + __I uint32_t PIN01 : 1; + __I uint32_t PIN02 : 1; + __I uint32_t PIN03 : 1; + __I uint32_t PIN04 : 1; + __I uint32_t PIN05 : 1; + __I uint32_t PIN06 : 1; + __I uint32_t PIN07 : 1; + __I uint32_t PIN08 : 1; + __I uint32_t PIN09 : 1; + __I uint32_t PIN10 : 1; + __I uint32_t PIN11 : 1; + __I uint32_t PIN12 : 1; + __I uint32_t PIN13 : 1; + __I uint32_t PIN14 : 1; + __I uint32_t PIN15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntidr_field_t; + +typedef struct +{ + __IO uint32_t POUT00 : 1; + __IO uint32_t POUT01 : 1; + __IO uint32_t POUT02 : 1; + __IO uint32_t POUT03 : 1; + __IO uint32_t POUT04 : 1; + __IO uint32_t POUT05 : 1; + __IO uint32_t POUT06 : 1; + __IO uint32_t POUT07 : 1; + __IO uint32_t POUT08 : 1; + __IO uint32_t POUT09 : 1; + __IO uint32_t POUT10 : 1; + __IO uint32_t POUT11 : 1; + __IO uint32_t POUT12 : 1; + __IO uint32_t POUT13 : 1; + __IO uint32_t POUT14 : 1; + __IO uint32_t POUT15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntodr_field_t; + +typedef struct +{ + __IO uint32_t POR00 : 1; + __IO uint32_t POR01 : 1; + __IO uint32_t POR02 : 1; + __IO uint32_t POR03 : 1; + __IO uint32_t POR04 : 1; + __IO uint32_t POR05 : 1; + __IO uint32_t POR06 : 1; + __IO uint32_t POR07 : 1; + __IO uint32_t POR08 : 1; + __IO uint32_t POR09 : 1; + __IO uint32_t POR10 : 1; + __IO uint32_t POR11 : 1; + __IO uint32_t POR12 : 1; + __IO uint32_t POR13 : 1; + __IO uint32_t POR14 : 1; + __IO uint32_t POR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntorr_field_t; + +typedef struct +{ + __IO uint32_t POS00 : 1; + __IO uint32_t POS01 : 1; + __IO uint32_t POS02 : 1; + __IO uint32_t POS03 : 1; + __IO uint32_t POS04 : 1; + __IO uint32_t POS05 : 1; + __IO uint32_t POS06 : 1; + __IO uint32_t POS07 : 1; + __IO uint32_t POS08 : 1; + __IO uint32_t POS09 : 1; + __IO uint32_t POS10 : 1; + __IO uint32_t POS11 : 1; + __IO uint32_t POS12 : 1; + __IO uint32_t POS13 : 1; + __IO uint32_t POS14 : 1; + __IO uint32_t POS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntosr_field_t; + +typedef struct +{ + __IO uint32_t RIS00 : 1; + __IO uint32_t RIS01 : 1; + __IO uint32_t RIS02 : 1; + __IO uint32_t RIS03 : 1; + __IO uint32_t RIS04 : 1; + __IO uint32_t RIS05 : 1; + __IO uint32_t RIS06 : 1; + __IO uint32_t RIS07 : 1; + __IO uint32_t RIS08 : 1; + __IO uint32_t RIS09 : 1; + __IO uint32_t RIS10 : 1; + __IO uint32_t RIS11 : 1; + __IO uint32_t RIS12 : 1; + __IO uint32_t RIS13 : 1; + __IO uint32_t RIS14 : 1; + __IO uint32_t RIS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntrisr_field_t; + +typedef struct +{ + __IO uint32_t FAL00 : 1; + __IO uint32_t FAL01 : 1; + __IO uint32_t FAL02 : 1; + __IO uint32_t FAL03 : 1; + __IO uint32_t FAL04 : 1; + __IO uint32_t FAL05 : 1; + __IO uint32_t FAL06 : 1; + __IO uint32_t FAL07 : 1; + __IO uint32_t FAL08 : 1; + __IO uint32_t FAL09 : 1; + __IO uint32_t FAL10 : 1; + __IO uint32_t FAL11 : 1; + __IO uint32_t FAL12 : 1; + __IO uint32_t FAL13 : 1; + __IO uint32_t FAL14 : 1; + __IO uint32_t FAL15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntfal_field_t; + +typedef struct +{ + __IO uint32_t NFEN1 : 1; + __IO uint32_t DIVS1 : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NFEN2 : 1; + __IO uint32_t DIVS2 : 2; + uint32_t RESERVED11 : 5; + __IO uint32_t NFEN3 : 1; + __IO uint32_t DIVS3 : 2; + uint32_t RESERVED19 : 5; + __IO uint32_t NFEN4 : 1; + __IO uint32_t DIVS4 : 2; + uint32_t RESERVED27 : 5; +} stc_aos_pevntnfcr_field_t; + +typedef struct +{ + __IO uint8_t BUSOFF : 1; + __I uint8_t TACTIVE : 1; + __I uint8_t RACTIVE : 1; + __IO uint8_t TSSS : 1; + __IO uint8_t TPSS : 1; + __IO uint8_t LBMI : 1; + __IO uint8_t LBME : 1; + __IO uint8_t RESET : 1; +} stc_can_cfg_stat_field_t; + +typedef struct +{ + __IO uint8_t TSA : 1; + __IO uint8_t TSALL : 1; + __IO uint8_t TSONE : 1; + __IO uint8_t TPA : 1; + __IO uint8_t TPE : 1; + uint8_t RESERVED5 : 1; + __IO uint8_t LOM : 1; + __IO uint8_t TBSEL : 1; +} stc_can_tcmd_field_t; + +typedef struct +{ + __I uint8_t TSSTAT : 2; + uint8_t RESERVED2 : 2; + __IO uint8_t TTTBM : 1; + __IO uint8_t TSMODE : 1; + __IO uint8_t TSNEXT : 1; + uint8_t RESERVED7 : 1; +} stc_can_tctrl_field_t; + +typedef struct +{ + __I uint8_t RSTAT : 2; + uint8_t RESERVED2 : 1; + __IO uint8_t RBALL : 1; + __IO uint8_t RREL : 1; + __I uint8_t ROV : 1; + __IO uint8_t ROM : 1; + __IO uint8_t SACK : 1; +} stc_can_rctrl_field_t; + +typedef struct +{ + __I uint8_t TSFF : 1; + __IO uint8_t EIE : 1; + __IO uint8_t TSIE : 1; + __IO uint8_t TPIE : 1; + __IO uint8_t RAFIE : 1; + __IO uint8_t RFIE : 1; + __IO uint8_t ROIE : 1; + __IO uint8_t RIE : 1; +} stc_can_rtie_field_t; + +typedef struct +{ + __IO uint8_t AIF : 1; + __IO uint8_t EIF : 1; + __IO uint8_t TSIF : 1; + __IO uint8_t TPIF : 1; + __IO uint8_t RAFIF : 1; + __IO uint8_t RFIF : 1; + __IO uint8_t ROIF : 1; + __IO uint8_t RIF : 1; +} stc_can_rtif_field_t; + +typedef struct +{ + __IO uint8_t BEIF : 1; + __IO uint8_t BEIE : 1; + __IO uint8_t ALIF : 1; + __IO uint8_t ALIE : 1; + __IO uint8_t EPIF : 1; + __IO uint8_t EPIE : 1; + __I uint8_t EPASS : 1; + __I uint8_t EWARN : 1; +} stc_can_errint_field_t; + +typedef struct +{ + __IO uint8_t EWL : 4; + __IO uint8_t AFWL : 4; +} stc_can_limit_field_t; + +typedef struct +{ + __IO uint32_t SEG_1 : 8; + __IO uint32_t SEG_2 : 7; + uint32_t RESERVED15 : 1; + __IO uint32_t SJW : 7; + uint32_t RESERVED23 : 1; + __IO uint32_t PRESC : 8; +} stc_can_bt_field_t; + +typedef struct +{ + __I uint8_t ALC : 5; + __I uint8_t KOER : 3; +} stc_can_ealcap_field_t; + +typedef struct +{ + __IO uint8_t ACFADR : 4; + uint8_t RESERVED4 : 1; + __IO uint8_t SELMASK : 1; + uint8_t RESERVED6 : 2; +} stc_can_acfctrl_field_t; + +typedef struct +{ + __IO uint8_t AE_1 : 1; + __IO uint8_t AE_2 : 1; + __IO uint8_t AE_3 : 1; + __IO uint8_t AE_4 : 1; + __IO uint8_t AE_5 : 1; + __IO uint8_t AE_6 : 1; + __IO uint8_t AE_7 : 1; + __IO uint8_t AE_8 : 1; +} stc_can_acfen_field_t; + +typedef struct +{ + __IO uint32_t ACODEORAMASK :29; + __IO uint32_t AIDE : 1; + __IO uint32_t AIDEE : 1; + uint32_t RESERVED31 : 1; +} stc_can_acf_field_t; + +typedef struct +{ + __IO uint8_t TBPTR : 6; + __IO uint8_t TBF : 1; + __IO uint8_t TBE : 1; +} stc_can_tbslot_field_t; + +typedef struct +{ + __IO uint8_t TTEN : 1; + __IO uint8_t T_PRESC : 2; + __IO uint8_t TTIF : 1; + __IO uint8_t TTIE : 1; + __IO uint8_t TEIF : 1; + __IO uint8_t WTIF : 1; + __IO uint8_t WTIE : 1; +} stc_can_ttcfg_field_t; + +typedef struct +{ + __IO uint32_t REF_ID :29; + uint32_t RESERVED29 : 2; + __IO uint32_t REF_IDE : 1; +} stc_can_ref_msg_field_t; + +typedef struct +{ + __IO uint16_t TTPTR : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t TTYPE : 3; + uint16_t RESERVED11 : 1; + __IO uint16_t TEW : 4; +} stc_can_trg_cfg_field_t; + +typedef struct +{ + __IO uint16_t FLTSL : 3; + uint16_t RESERVED3 : 2; + __IO uint16_t EDGSL : 2; + __IO uint16_t IEN : 1; + __IO uint16_t CVSEN : 1; + uint16_t RESERVED9 : 3; + __IO uint16_t OUTEN : 1; + __IO uint16_t INV : 1; + __IO uint16_t CMPOE : 1; + __IO uint16_t CMPON : 1; +} stc_cmp_ctrl_field_t; + +typedef struct +{ + __IO uint16_t RVSL : 4; + uint16_t RESERVED4 : 4; + __IO uint16_t CVSL : 4; + __IO uint16_t C4SL : 3; + uint16_t RESERVED15 : 1; +} stc_cmp_vltsel_field_t; + +typedef struct +{ + __I uint16_t OMON : 1; + uint16_t RESERVED1 : 7; + __I uint16_t CVST : 4; + uint16_t RESERVED12 : 4; +} stc_cmp_outmon_field_t; + +typedef struct +{ + __IO uint16_t STB : 4; + uint16_t RESERVED4 :12; +} stc_cmp_cvsstb_field_t; + +typedef struct +{ + __IO uint16_t PRD : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cvsprd_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr1_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr2_field_t; + +typedef struct +{ + __IO uint16_t DA1EN : 1; + __IO uint16_t DA2EN : 1; + uint16_t RESERVED2 :14; +} stc_cmp_cr_dacr_field_t; + +typedef struct +{ + __IO uint16_t DA1SW : 1; + __IO uint16_t DA2SW : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t VREFSW : 1; + uint16_t RESERVED5 : 3; + __IO uint16_t WPRT : 8; +} stc_cmp_cr_rvadc_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t CRC_SEL : 1; + __IO uint32_t REFIN : 1; + __IO uint32_t REFOUT : 1; + __IO uint32_t XOROUT : 1; + uint32_t RESERVED5 :27; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t CRC_REG :16; + __I uint32_t CRCFLAG_16 : 1; + uint32_t RESERVED17 :15; +} stc_crc_reslt_field_t; + +typedef struct +{ + __I uint32_t FLAG : 1; + uint32_t RESERVED1 :31; +} stc_crc_flg_field_t; + +typedef struct +{ + __IO uint32_t AUTH : 1; + __IO uint32_t REMVLOCK : 1; + __IO uint32_t SAFTYLOCK1 : 1; + __IO uint32_t SAFTYLOCK2 : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t CPUSTOP : 1; + __IO uint32_t CPUSLEEP : 1; + uint32_t RESERVED10 :22; +} stc_dbgc_mcustat_field_t; + +typedef struct +{ + __IO uint32_t EDBGRQ : 1; + __IO uint32_t RESTART : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t DIRQ : 1; + uint32_t RESERVED9 :23; +} stc_dbgc_mcuctl_field_t; + +typedef struct +{ + __IO uint32_t ERASEREQ : 1; + __IO uint32_t ERASEACK : 1; + __IO uint32_t ERASEERR : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_fmcctl_field_t; + +typedef struct +{ + __IO uint32_t CDBGPWRUPREQ : 1; + __IO uint32_t CDBGPWRUPACK : 1; + uint32_t RESERVED2 :30; +} stc_dbgc_mcudbgstat_field_t; + +typedef struct +{ + __IO uint32_t SWDTSTP : 1; + __IO uint32_t WDTSTP : 1; + __IO uint32_t RTCSTP : 1; + __IO uint32_t PVD0STP : 1; + __IO uint32_t PVD1STP : 1; + __IO uint32_t PVD2STP : 1; + uint32_t RESERVED6 : 8; + __IO uint32_t TMR01STP : 1; + __IO uint32_t TMR02STP : 1; + uint32_t RESERVED16 : 4; + __IO uint32_t TMR41STP : 1; + __IO uint32_t TMR42STP : 1; + __IO uint32_t TMR43STP : 1; + __IO uint32_t TM61STP : 1; + __IO uint32_t TM62STP : 1; + __IO uint32_t TMR63STP : 1; + __IO uint32_t TMRA1STP : 1; + __IO uint32_t TMRA2STP : 1; + __IO uint32_t TMRA3STP : 1; + __IO uint32_t TMRA4STP : 1; + __IO uint32_t TMRA5STP : 1; + __IO uint32_t TMRA6STP : 1; +} stc_dbgc_mcustpctl_field_t; + +typedef struct +{ + __IO uint32_t TRACEMODE : 2; + __IO uint32_t TRACEIOEN : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_mcutracectl_field_t; + +typedef struct +{ + __IO uint32_t MODE : 3; + __IO uint32_t DATASIZE : 2; + uint32_t RESERVED5 : 3; + __IO uint32_t COMP_TRG : 1; + uint32_t RESERVED9 :22; + __IO uint32_t INTEN : 1; +} stc_dcu_ctl_field_t; + +typedef struct +{ + __I uint32_t FLAG_OP : 1; + __I uint32_t FLAG_LS2 : 1; + __I uint32_t FLAG_EQ2 : 1; + __I uint32_t FLAG_GT2 : 1; + __I uint32_t FLAG_LS1 : 1; + __I uint32_t FLAG_EQ1 : 1; + __I uint32_t FLAG_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flag_field_t; + +typedef struct +{ + __O uint32_t CLR_OP : 1; + __O uint32_t CLR_LS2 : 1; + __O uint32_t CLR_EQ2 : 1; + __O uint32_t CLR_GT2 : 1; + __O uint32_t CLR_LS1 : 1; + __O uint32_t CLR_EQ1 : 1; + __O uint32_t CLR_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flagclr_field_t; + +typedef struct +{ + __IO uint32_t INT_OP : 1; + __IO uint32_t INT_LS2 : 1; + __IO uint32_t INT_EQ2 : 1; + __IO uint32_t INT_GT2 : 1; + __IO uint32_t INT_LS1 : 1; + __IO uint32_t INT_EQ1 : 1; + __IO uint32_t INT_GT1 : 1; + __IO uint32_t INT_WIN : 2; + uint32_t RESERVED9 :23; +} stc_dcu_intsel_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 :31; +} stc_dma_en_field_t; + +typedef struct +{ + __I uint32_t TRNERR : 4; + uint32_t RESERVED4 :12; + __I uint32_t REQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat0_field_t; + +typedef struct +{ + __I uint32_t TC : 4; + uint32_t RESERVED4 :12; + __I uint32_t BTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat1_field_t; + +typedef struct +{ + __IO uint32_t MSKTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask0_field_t; + +typedef struct +{ + __IO uint32_t MSKTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask1_field_t; + +typedef struct +{ + __O uint32_t CLRTRNERR : 4; + uint32_t RESERVED4 :12; + __O uint32_t CLRREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr0_field_t; + +typedef struct +{ + __O uint32_t CLRTC : 4; + uint32_t RESERVED4 :12; + __O uint32_t CLRBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr1_field_t; + +typedef struct +{ + __IO uint32_t CHEN : 4; + uint32_t RESERVED4 :28; +} stc_dma_chen_field_t; + +typedef struct +{ + __I uint32_t CHREQ : 4; + uint32_t RESERVED4 :11; + __I uint32_t RCFGREQ : 1; + uint32_t RESERVED16 :16; +} stc_dma_reqstat_field_t; + +typedef struct +{ + __I uint32_t DMAACT : 1; + __I uint32_t RCFGACT : 1; + uint32_t RESERVED2 :14; + __I uint32_t CHACT : 4; + uint32_t RESERVED20 :12; +} stc_dma_chstat_field_t; + +typedef struct +{ + __IO uint32_t RCFGEN : 1; + __IO uint32_t RCFGLLP : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t RCFGCHS : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SARMD : 2; + __IO uint32_t DARMD : 2; + __IO uint32_t CNTMD : 2; + uint32_t RESERVED22 :10; +} stc_dma_rcfgctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_dtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_rpt_field_t; + +typedef struct +{ + __IO uint32_t SRPTB :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPTB :10; + uint32_t RESERVED26 : 6; +} stc_dma_rptb_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_snseqctl_field_t; + +typedef struct +{ + __IO uint32_t SNSDIST :20; + __IO uint32_t SNSCNTB :12; +} stc_dma_snseqctlb_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_dnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DNSDIST :20; + __IO uint32_t DNSCNTB :12; +} stc_dma_dnseqctlb_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t LLP :30; +} stc_dma_llp_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_chctl_field_t; + +typedef struct +{ + __I uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __I uint32_t CNT :16; +} stc_dma_mondtctl_field_t; + +typedef struct +{ + __I uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __I uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_monrpt_field_t; + +typedef struct +{ + __I uint32_t SOFFSET :20; + __I uint32_t SNSCNT :12; +} stc_dma_monsnseqctl_field_t; + +typedef struct +{ + __I uint32_t DOFFSET :20; + __I uint32_t DNSCNT :12; +} stc_dma_mondnseqctl_field_t; + +typedef struct +{ + __IO uint32_t FAPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_faprt_field_t; + +typedef struct +{ + __IO uint32_t FSTP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fstp_field_t; + +typedef struct +{ + __IO uint32_t SLPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t FLWT : 4; + __IO uint32_t LVM : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t CACHE : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t CRST : 1; + uint32_t RESERVED25 : 7; +} stc_efm_frmc_field_t; + +typedef struct +{ + __IO uint32_t PEMODE : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t PEMOD : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t BUSHLDCTL : 1; + uint32_t RESERVED9 :23; +} stc_efm_fwmc_field_t; + +typedef struct +{ + __I uint32_t PEWERR : 1; + __I uint32_t PEPRTERR : 1; + __I uint32_t PGSZERR : 1; + __I uint32_t PGMISMTCH : 1; + __I uint32_t OPTEND : 1; + __I uint32_t COLERR : 1; + uint32_t RESERVED6 : 2; + __I uint32_t RDY : 1; + uint32_t RESERVED9 :23; +} stc_efm_fsr_field_t; + +typedef struct +{ + __IO uint32_t PEWERRCLR : 1; + __IO uint32_t PEPRTERRCLR : 1; + __IO uint32_t PGSZERRCLR : 1; + __IO uint32_t PGMISMTCHCLR : 1; + __IO uint32_t OPTENDCLR : 1; + __IO uint32_t COLERRCLR : 1; + uint32_t RESERVED6 :26; +} stc_efm_fsclr_field_t; + +typedef struct +{ + __IO uint32_t PEERRITE : 1; + __IO uint32_t OPTENDITE : 1; + __IO uint32_t COLERRITE : 1; + uint32_t RESERVED3 :29; +} stc_efm_fite_field_t; + +typedef struct +{ + __I uint32_t FSWP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fswp_field_t; + +typedef struct +{ + __IO uint32_t FPMTSW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtsw_field_t; + +typedef struct +{ + __IO uint32_t FPMTEW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtew_field_t; + +typedef struct +{ + __IO uint32_t REMPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_mmf_remprt_field_t; + +typedef struct +{ + __IO uint32_t RM0SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM0TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN0 : 1; +} stc_efm_mmf_remcr0_field_t; + +typedef struct +{ + __IO uint32_t RM1SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM1TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN1 : 1; +} stc_efm_mmf_remcr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t FRANDS :14; + uint32_t RESERVED15 : 1; + __IO uint32_t FRANDFG : 1; + uint32_t RESERVED17 :15; +} stc_efm_frands_field_t; + +typedef struct +{ + __IO uint32_t PORTINEN : 1; + __IO uint32_t CMPEN : 3; + uint32_t RESERVED4 : 1; + __IO uint32_t OSCSTPEN : 1; + __IO uint32_t PWMSEN : 3; + uint32_t RESERVED9 :19; + __IO uint32_t NFSEL : 2; + __IO uint32_t NFEN : 1; + __IO uint32_t INVSEL : 1; +} stc_emb_ctl_field_t; + +typedef struct +{ + __IO uint32_t PWMLV : 3; + uint32_t RESERVED3 :29; +} stc_emb_pwmlv_field_t; + +typedef struct +{ + __IO uint32_t SOE : 1; + uint32_t RESERVED1 :31; +} stc_emb_soe_field_t; + +typedef struct +{ + __I uint32_t PORTINF : 1; + __I uint32_t PWMSF : 1; + __I uint32_t CMPF : 1; + __I uint32_t OSF : 1; + __I uint32_t PORTINST : 1; + __I uint32_t PWMST : 1; + uint32_t RESERVED6 :26; +} stc_emb_stat_field_t; + +typedef struct +{ + __O uint32_t PORTINFCLR : 1; + __O uint32_t PWMSFCLR : 1; + __O uint32_t CMPFCLR : 1; + __O uint32_t OSFCLR : 1; + uint32_t RESERVED4 :28; +} stc_emb_statclr_field_t; + +typedef struct +{ + __IO uint32_t PORTINTEN : 1; + __IO uint32_t PWMINTEN : 1; + __IO uint32_t CMPINTEN : 1; + __IO uint32_t OSINTEN : 1; + uint32_t RESERVED4 :28; +} stc_emb_inten_field_t; + +typedef struct +{ + __IO uint32_t LVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_lvr_field_t; + +typedef struct +{ + __IO uint32_t UVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_uvr_field_t; + +typedef struct +{ + __I uint32_t CNTR :16; + uint32_t RESERVED16 :16; +} stc_fcm_cntr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :31; +} stc_fcm_str_field_t; + +typedef struct +{ + __IO uint32_t MDIVS : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t MCKS : 4; + uint32_t RESERVED8 :24; +} stc_fcm_mccr_field_t; + +typedef struct +{ + __IO uint32_t RDIVS : 2; + uint32_t RESERVED2 : 1; + __IO uint32_t RCKS : 4; + __IO uint32_t INEXS : 1; + __IO uint32_t DNFS : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t EDGES : 2; + uint32_t RESERVED14 : 1; + __IO uint32_t EXREFE : 1; + uint32_t RESERVED16 :16; +} stc_fcm_rccr_field_t; + +typedef struct +{ + __IO uint32_t ERRIE : 1; + __IO uint32_t MENDIE : 1; + __IO uint32_t OVFIE : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t ERRINTRS : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ERRE : 1; + uint32_t RESERVED8 :24; +} stc_fcm_rier_field_t; + +typedef struct +{ + __I uint32_t ERRF : 1; + __I uint32_t MENDF : 1; + __I uint32_t OVF : 1; + uint32_t RESERVED3 :29; +} stc_fcm_sr_field_t; + +typedef struct +{ + __O uint32_t ERRFCLR : 1; + __O uint32_t MENDFCLR : 1; + __O uint32_t OVFCLR : 1; + uint32_t RESERVED3 :29; +} stc_fcm_clr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t FST_GRP : 1; + uint32_t RESERVED2 :30; +} stc_hash_cr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t SMBUS : 1; + __IO uint32_t SMBALRTEN : 1; + __IO uint32_t SMBDEFAULTEN : 1; + __IO uint32_t SMBHOSTEN : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ENGC : 1; + __IO uint32_t RESTART : 1; + __IO uint32_t START : 1; + __IO uint32_t STOP : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t SWRST : 1; + uint32_t RESERVED16 :16; +} stc_i2c_cr1_field_t; + +typedef struct +{ + __IO uint32_t STARTIE : 1; + __IO uint32_t SLADDR0IE : 1; + __IO uint32_t SLADDR1IE : 1; + __IO uint32_t TENDIE : 1; + __IO uint32_t STOPIE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLIE : 1; + __IO uint32_t TEMPTYIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOIE : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKIE : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTIE : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLIE : 1; + __IO uint32_t SMBDEFAULTIE : 1; + __IO uint32_t SMBHOSTIE : 1; + __IO uint32_t SMBALRTIE : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_cr2_field_t; + +typedef struct +{ + __IO uint32_t TMOUTEN : 1; + __IO uint32_t LTMOUT : 1; + __IO uint32_t HTMOUT : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t FACKEN : 1; + uint32_t RESERVED8 :24; +} stc_i2c_cr3_field_t; + +typedef struct +{ + uint32_t RESERVED0 :10; + __IO uint32_t BUSWAIT : 1; + uint32_t RESERVED11 :21; +} stc_i2c_cr4_field_t; + +typedef struct +{ + __IO uint32_t SLADDR0 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR0EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD0 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr0_field_t; + +typedef struct +{ + __IO uint32_t SLADDR1 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR1EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD1 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr1_field_t; + +typedef struct +{ + __IO uint32_t TOUTLOW :16; + __IO uint32_t TOUTHIGH :16; +} stc_i2c_sltr_field_t; + +typedef struct +{ + __IO uint32_t STARTF : 1; + __IO uint32_t SLADDR0F : 1; + __IO uint32_t SLADDR1F : 1; + __IO uint32_t TENDF : 1; + __IO uint32_t STOPF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLF : 1; + __IO uint32_t TEMPTYF : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOF : 1; + __IO uint32_t ACKRF : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t NACKF : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTF : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t MSL : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t TRA : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t GENCALLF : 1; + __IO uint32_t SMBDEFAULTF : 1; + __IO uint32_t SMBHOSTF : 1; + __IO uint32_t SMBALRTF : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_sr_field_t; + +typedef struct +{ + __O uint32_t STARTFCLR : 1; + __O uint32_t SLADDR0FCLR : 1; + __O uint32_t SLADDR1FCLR : 1; + __O uint32_t TENDFCLR : 1; + __O uint32_t STOPFCLR : 1; + uint32_t RESERVED5 : 1; + __O uint32_t RFULLFCLR : 1; + __O uint32_t TEMPTYFCLR : 1; + uint32_t RESERVED8 : 1; + __O uint32_t ARLOFCLR : 1; + uint32_t RESERVED10 : 2; + __O uint32_t NACKFCLR : 1; + uint32_t RESERVED13 : 1; + __O uint32_t TMOUTFCLR : 1; + uint32_t RESERVED15 : 5; + __O uint32_t GENCALLFCLR : 1; + __O uint32_t SMBDEFAULTFCLR : 1; + __O uint32_t SMBHOSTFCLR : 1; + __O uint32_t SMBALRTFCLR : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_clr_field_t; + +typedef struct +{ + __O uint8_t DT : 8; +} stc_i2c_dtr_field_t; + +typedef struct +{ + __I uint8_t DR : 8; +} stc_i2c_drr_field_t; + +typedef struct +{ + __IO uint32_t SLOWW : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t SHIGHW : 5; + uint32_t RESERVED13 : 3; + __IO uint32_t FREQ : 3; + uint32_t RESERVED19 :13; +} stc_i2c_ccr_field_t; + +typedef struct +{ + __IO uint32_t DNF : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t DNFEN : 1; + __IO uint32_t ANFEN : 1; + uint32_t RESERVED6 :26; +} stc_i2c_fltr_field_t; + +typedef struct +{ + __IO uint32_t TXE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t WMS : 1; + __IO uint32_t ODD : 1; + __IO uint32_t MCKOE : 1; + __IO uint32_t TXBIRQWL : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t RXBIRQWL : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t FIFOR : 1; + __IO uint32_t CODECRC : 1; + __IO uint32_t I2SPLLSEL : 1; + __IO uint32_t SDOE : 1; + __IO uint32_t LRCKOE : 1; + __IO uint32_t CKOE : 1; + __IO uint32_t DUPLEX : 1; + __IO uint32_t CLKSEL : 1; + uint32_t RESERVED24 : 8; +} stc_i2s_ctrl_field_t; + +typedef struct +{ + __I uint32_t TXBA : 1; + __I uint32_t RXBA : 1; + __I uint32_t TXBE : 1; + __I uint32_t TXBF : 1; + __I uint32_t RXBE : 1; + __I uint32_t RXBF : 1; + uint32_t RESERVED6 :26; +} stc_i2s_sr_field_t; + +typedef struct +{ + __IO uint32_t TXERR : 1; + __IO uint32_t RXERR : 1; + uint32_t RESERVED2 :30; +} stc_i2s_er_field_t; + +typedef struct +{ + __IO uint32_t I2SSTD : 2; + __IO uint32_t DATLEN : 2; + __IO uint32_t CHLEN : 1; + __IO uint32_t PCMSYNC : 1; + uint32_t RESERVED6 :26; +} stc_i2s_cfgr_field_t; + +typedef struct +{ + __IO uint32_t I2SDIV : 8; + uint32_t RESERVED8 :24; +} stc_i2s_pr_field_t; + +typedef struct +{ + __I uint32_t SWDTAUTS : 1; + __I uint32_t SWDTITS : 1; + __I uint32_t SWDTPERI : 2; + __I uint32_t SWDTCKS : 4; + __I uint32_t SWDTWDPT : 4; + __I uint32_t SWDTSLPOFF : 1; + uint32_t RESERVED13 : 3; + __I uint32_t WDTAUTS : 1; + __I uint32_t WDTITS : 1; + __I uint32_t WDTPERI : 2; + __I uint32_t WDTCKS : 4; + __I uint32_t WDTWDPT : 4; + __I uint32_t WDTSLPOFF : 1; + uint32_t RESERVED29 : 3; +} stc_icg_icg0_field_t; + +typedef struct +{ + __I uint32_t HRCFREQSEL : 1; + uint32_t RESERVED1 : 7; + __I uint32_t HRCSTOP : 1; + uint32_t RESERVED9 : 7; + __I uint32_t BOR_LEV : 2; + __I uint32_t BORDIS : 1; + uint32_t RESERVED19 : 7; + __I uint32_t SMPCLK : 2; + __I uint32_t NMITRG : 1; + __I uint32_t NMIENR : 1; + __I uint32_t NFEN : 1; + __I uint32_t NMIICGENA : 1; +} stc_icg_icg1_field_t; + +typedef struct +{ + __IO uint32_t NMITRG : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t NSMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t NFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_nmicr_field_t; + +typedef struct +{ + __IO uint32_t NMIENR : 1; + __IO uint32_t SWDTENR : 1; + __IO uint32_t PVD1ENR : 1; + __IO uint32_t PVD2ENR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPENR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPENR : 1; + __IO uint32_t RECCENR : 1; + __IO uint32_t BUSMENR : 1; + __IO uint32_t WDTENR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmienr_field_t; + +typedef struct +{ + __IO uint32_t NMIFR : 1; + __IO uint32_t SWDTFR : 1; + __IO uint32_t PVD1FR : 1; + __IO uint32_t PVD2FR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPFR : 1; + __IO uint32_t RECCFR : 1; + __IO uint32_t BUSMFR : 1; + __IO uint32_t WDTFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmifr_field_t; + +typedef struct +{ + __IO uint32_t NMICFR : 1; + __IO uint32_t SWDTCFR : 1; + __IO uint32_t PVD1CFR : 1; + __IO uint32_t PVD2CFR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPCFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPCFR : 1; + __IO uint32_t RECCCFR : 1; + __IO uint32_t BUSMCFR : 1; + __IO uint32_t WDTCFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmicfr_field_t; + +typedef struct +{ + __IO uint32_t EIRQTRG : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t EISMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t EFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_eirqcr_field_t; + +typedef struct +{ + __IO uint32_t EIRQWUEN :16; + __IO uint32_t SWDTWUEN : 1; + __IO uint32_t PVD1WUEN : 1; + __IO uint32_t PVD2WUEN : 1; + __IO uint32_t CMPI0WUEN : 1; + __IO uint32_t WKTMWUEN : 1; + __IO uint32_t RTCALMWUEN : 1; + __IO uint32_t RTCPRDWUEN : 1; + __IO uint32_t TMR0WUEN : 1; + uint32_t RESERVED24 : 1; + __IO uint32_t RXWUEN : 1; + uint32_t RESERVED26 : 6; +} stc_intc_wupen_field_t; + +typedef struct +{ + __IO uint32_t EIFR0 : 1; + __IO uint32_t EIFR1 : 1; + __IO uint32_t EIFR2 : 1; + __IO uint32_t EIFR3 : 1; + __IO uint32_t EIFR4 : 1; + __IO uint32_t EIFR5 : 1; + __IO uint32_t EIFR6 : 1; + __IO uint32_t EIFR7 : 1; + __IO uint32_t EIFR8 : 1; + __IO uint32_t EIFR9 : 1; + __IO uint32_t EIFR10 : 1; + __IO uint32_t EIFR11 : 1; + __IO uint32_t EIFR12 : 1; + __IO uint32_t EIFR13 : 1; + __IO uint32_t EIFR14 : 1; + __IO uint32_t EIFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eifr_field_t; + +typedef struct +{ + __IO uint32_t EICFR0 : 1; + __IO uint32_t EICFR1 : 1; + __IO uint32_t EICFR2 : 1; + __IO uint32_t EICFR3 : 1; + __IO uint32_t EICFR4 : 1; + __IO uint32_t EICFR5 : 1; + __IO uint32_t EICFR6 : 1; + __IO uint32_t EICFR7 : 1; + __IO uint32_t EICFR8 : 1; + __IO uint32_t EICFR9 : 1; + __IO uint32_t EICFR10 : 1; + __IO uint32_t EICFR11 : 1; + __IO uint32_t EICFR12 : 1; + __IO uint32_t EICFR13 : 1; + __IO uint32_t EICFR14 : 1; + __IO uint32_t EICFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eicfr_field_t; + +typedef struct +{ + __IO uint32_t INTSEL : 9; + uint32_t RESERVED9 :23; +} stc_intc_sel_field_t; + +typedef struct +{ + __IO uint32_t VSEL0 : 1; + __IO uint32_t VSEL1 : 1; + __IO uint32_t VSEL2 : 1; + __IO uint32_t VSEL3 : 1; + __IO uint32_t VSEL4 : 1; + __IO uint32_t VSEL5 : 1; + __IO uint32_t VSEL6 : 1; + __IO uint32_t VSEL7 : 1; + __IO uint32_t VSEL8 : 1; + __IO uint32_t VSEL9 : 1; + __IO uint32_t VSEL10 : 1; + __IO uint32_t VSEL11 : 1; + __IO uint32_t VSEL12 : 1; + __IO uint32_t VSEL13 : 1; + __IO uint32_t VSEL14 : 1; + __IO uint32_t VSEL15 : 1; + __IO uint32_t VSEL16 : 1; + __IO uint32_t VSEL17 : 1; + __IO uint32_t VSEL18 : 1; + __IO uint32_t VSEL19 : 1; + __IO uint32_t VSEL20 : 1; + __IO uint32_t VSEL21 : 1; + __IO uint32_t VSEL22 : 1; + __IO uint32_t VSEL23 : 1; + __IO uint32_t VSEL24 : 1; + __IO uint32_t VSEL25 : 1; + __IO uint32_t VSEL26 : 1; + __IO uint32_t VSEL27 : 1; + __IO uint32_t VSEL28 : 1; + __IO uint32_t VSEL29 : 1; + __IO uint32_t VSEL30 : 1; + __IO uint32_t VSEL31 : 1; +} stc_intc_vssel_field_t; + +typedef struct +{ + __IO uint32_t SWIE0 : 1; + __IO uint32_t SWIE1 : 1; + __IO uint32_t SWIE2 : 1; + __IO uint32_t SWIE3 : 1; + __IO uint32_t SWIE4 : 1; + __IO uint32_t SWIE5 : 1; + __IO uint32_t SWIE6 : 1; + __IO uint32_t SWIE7 : 1; + __IO uint32_t SWIE8 : 1; + __IO uint32_t SWIE9 : 1; + __IO uint32_t SWIE10 : 1; + __IO uint32_t SWIE11 : 1; + __IO uint32_t SWIE12 : 1; + __IO uint32_t SWIE13 : 1; + __IO uint32_t SWIE14 : 1; + __IO uint32_t SWIE15 : 1; + __IO uint32_t SWIE16 : 1; + __IO uint32_t SWIE17 : 1; + __IO uint32_t SWIE18 : 1; + __IO uint32_t SWIE19 : 1; + __IO uint32_t SWIE20 : 1; + __IO uint32_t SWIE21 : 1; + __IO uint32_t SWIE22 : 1; + __IO uint32_t SWIE23 : 1; + __IO uint32_t SWIE24 : 1; + __IO uint32_t SWIE25 : 1; + __IO uint32_t SWIE26 : 1; + __IO uint32_t SWIE27 : 1; + __IO uint32_t SWIE28 : 1; + __IO uint32_t SWIE29 : 1; + __IO uint32_t SWIE30 : 1; + __IO uint32_t SWIE31 : 1; +} stc_intc_swier_field_t; + +typedef struct +{ + __IO uint32_t EVTE0 : 1; + __IO uint32_t EVTE1 : 1; + __IO uint32_t EVTE2 : 1; + __IO uint32_t EVTE3 : 1; + __IO uint32_t EVTE4 : 1; + __IO uint32_t EVTE5 : 1; + __IO uint32_t EVTE6 : 1; + __IO uint32_t EVTE7 : 1; + __IO uint32_t EVTE8 : 1; + __IO uint32_t EVTE9 : 1; + __IO uint32_t EVTE10 : 1; + __IO uint32_t EVTE11 : 1; + __IO uint32_t EVTE12 : 1; + __IO uint32_t EVTE13 : 1; + __IO uint32_t EVTE14 : 1; + __IO uint32_t EVTE15 : 1; + __IO uint32_t EVTE16 : 1; + __IO uint32_t EVTE17 : 1; + __IO uint32_t EVTE18 : 1; + __IO uint32_t EVTE19 : 1; + __IO uint32_t EVTE20 : 1; + __IO uint32_t EVTE21 : 1; + __IO uint32_t EVTE22 : 1; + __IO uint32_t EVTE23 : 1; + __IO uint32_t EVTE24 : 1; + __IO uint32_t EVTE25 : 1; + __IO uint32_t EVTE26 : 1; + __IO uint32_t EVTE27 : 1; + __IO uint32_t EVTE28 : 1; + __IO uint32_t EVTE29 : 1; + __IO uint32_t EVTE30 : 1; + __IO uint32_t EVTE31 : 1; +} stc_intc_evter_field_t; + +typedef struct +{ + __IO uint32_t IER0 : 1; + __IO uint32_t IER1 : 1; + __IO uint32_t IER2 : 1; + __IO uint32_t IER3 : 1; + __IO uint32_t IER4 : 1; + __IO uint32_t IER5 : 1; + __IO uint32_t IER6 : 1; + __IO uint32_t IER7 : 1; + __IO uint32_t IER8 : 1; + __IO uint32_t IER9 : 1; + __IO uint32_t IER10 : 1; + __IO uint32_t IER11 : 1; + __IO uint32_t IER12 : 1; + __IO uint32_t IER13 : 1; + __IO uint32_t IER14 : 1; + __IO uint32_t IER15 : 1; + __IO uint32_t IER16 : 1; + __IO uint32_t IER17 : 1; + __IO uint32_t IER18 : 1; + __IO uint32_t IER19 : 1; + __IO uint32_t IER20 : 1; + __IO uint32_t IER21 : 1; + __IO uint32_t IER22 : 1; + __IO uint32_t IER23 : 1; + __IO uint32_t IER24 : 1; + __IO uint32_t IER25 : 1; + __IO uint32_t IER26 : 1; + __IO uint32_t IER27 : 1; + __IO uint32_t IER28 : 1; + __IO uint32_t IER29 : 1; + __IO uint32_t IER30 : 1; + __IO uint32_t IER31 : 1; +} stc_intc_ier_field_t; + +typedef struct +{ + __IO uint32_t KEYINSEL :16; + __IO uint32_t KEYOUTSEL : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t CKSEL : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t T_LLEVEL : 5; + __IO uint32_t T_HIZ : 3; +} stc_keyscan_scr_field_t; + +typedef struct +{ + __IO uint32_t SEN : 1; + uint32_t RESERVED1 :31; +} stc_keyscan_ser_field_t; + +typedef struct +{ + __IO uint32_t INDEX : 3; + uint32_t RESERVED3 :29; +} stc_keyscan_ssr_field_t; + +typedef struct +{ + __IO uint32_t MPURGSIZE : 5; + __IO uint32_t MPURGADDR :27; +} stc_mpu_rgd_field_t; + +typedef struct +{ + __IO uint32_t S2RG0RP : 1; + __IO uint32_t S2RG0WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG0E : 1; + __IO uint32_t S1RG0RP : 1; + __IO uint32_t S1RG0WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG0E : 1; + __IO uint32_t FRG0RP : 1; + __IO uint32_t FRG0WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG0E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr0_field_t; + +typedef struct +{ + __IO uint32_t S2RG1RP : 1; + __IO uint32_t S2RG1WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG1E : 1; + __IO uint32_t S1RG1RP : 1; + __IO uint32_t S1RG1WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG1E : 1; + __IO uint32_t FRG1RP : 1; + __IO uint32_t FRG1WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG1E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr1_field_t; + +typedef struct +{ + __IO uint32_t S2RG2RP : 1; + __IO uint32_t S2RG2WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG2E : 1; + __IO uint32_t S1RG2RP : 1; + __IO uint32_t S1RG2WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG2E : 1; + __IO uint32_t FRG2RP : 1; + __IO uint32_t FRG2WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG2E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr2_field_t; + +typedef struct +{ + __IO uint32_t S2RG3RP : 1; + __IO uint32_t S2RG3WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG3E : 1; + __IO uint32_t S1RG3RP : 1; + __IO uint32_t S1RG3WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG3E : 1; + __IO uint32_t FRG3RP : 1; + __IO uint32_t FRG3WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG3E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr3_field_t; + +typedef struct +{ + __IO uint32_t S2RG4RP : 1; + __IO uint32_t S2RG4WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG4E : 1; + __IO uint32_t S1RG4RP : 1; + __IO uint32_t S1RG4WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG4E : 1; + __IO uint32_t FRG4RP : 1; + __IO uint32_t FRG4WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG4E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr4_field_t; + +typedef struct +{ + __IO uint32_t S2RG5RP : 1; + __IO uint32_t S2RG5WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG5E : 1; + __IO uint32_t S1RG5RP : 1; + __IO uint32_t S1RG5WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG5E : 1; + __IO uint32_t FRG5RP : 1; + __IO uint32_t FRG5WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG5E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr5_field_t; + +typedef struct +{ + __IO uint32_t S2RG6RP : 1; + __IO uint32_t S2RG6WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG6E : 1; + __IO uint32_t S1RG6RP : 1; + __IO uint32_t S1RG6WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG6E : 1; + __IO uint32_t FRG6RP : 1; + __IO uint32_t FRG6WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG6E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr6_field_t; + +typedef struct +{ + __IO uint32_t S2RG7RP : 1; + __IO uint32_t S2RG7WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG7E : 1; + __IO uint32_t S1RG7RP : 1; + __IO uint32_t S1RG7WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG7E : 1; + __IO uint32_t FRG7RP : 1; + __IO uint32_t FRG7WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG7E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr7_field_t; + +typedef struct +{ + __IO uint32_t S2RG8RP : 1; + __IO uint32_t S2RG8WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG8E : 1; + __IO uint32_t S1RG8RP : 1; + __IO uint32_t S1RG8WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG8E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr8_field_t; + +typedef struct +{ + __IO uint32_t S2RG9RP : 1; + __IO uint32_t S2RG9WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG9E : 1; + __IO uint32_t S1RG9RP : 1; + __IO uint32_t S1RG9WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG9E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr9_field_t; + +typedef struct +{ + __IO uint32_t S2RG10RP : 1; + __IO uint32_t S2RG10WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG10E : 1; + __IO uint32_t S1RG10RP : 1; + __IO uint32_t S1RG10WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG10E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr10_field_t; + +typedef struct +{ + __IO uint32_t S2RG11RP : 1; + __IO uint32_t S2RG11WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG11E : 1; + __IO uint32_t S1RG11RP : 1; + __IO uint32_t S1RG11WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG11E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr11_field_t; + +typedef struct +{ + __IO uint32_t S2RG12RP : 1; + __IO uint32_t S2RG12WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG12E : 1; + __IO uint32_t S1RG12RP : 1; + __IO uint32_t S1RG12WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG12E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr12_field_t; + +typedef struct +{ + __IO uint32_t S2RG13RP : 1; + __IO uint32_t S2RG13WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG13E : 1; + __IO uint32_t S1RG13RP : 1; + __IO uint32_t S1RG13WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG13E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr13_field_t; + +typedef struct +{ + __IO uint32_t S2RG14RP : 1; + __IO uint32_t S2RG14WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG14E : 1; + __IO uint32_t S1RG14RP : 1; + __IO uint32_t S1RG14WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG14E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr14_field_t; + +typedef struct +{ + __IO uint32_t S2RG15RP : 1; + __IO uint32_t S2RG15WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG15E : 1; + __IO uint32_t S1RG15RP : 1; + __IO uint32_t S1RG15WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG15E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr15_field_t; + +typedef struct +{ + __IO uint32_t SMPU2BRP : 1; + __IO uint32_t SMPU2BWP : 1; + __IO uint32_t SMPU2ACT : 2; + uint32_t RESERVED4 : 3; + __IO uint32_t SMPU2E : 1; + __IO uint32_t SMPU1BRP : 1; + __IO uint32_t SMPU1BWP : 1; + __IO uint32_t SMPU1ACT : 2; + uint32_t RESERVED12 : 3; + __IO uint32_t SMPU1E : 1; + __IO uint32_t FMPUBRP : 1; + __IO uint32_t FMPUBWP : 1; + __IO uint32_t FMPUACT : 2; + uint32_t RESERVED20 : 3; + __IO uint32_t FMPUE : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_cr_field_t; + +typedef struct +{ + __I uint32_t SMPU2EAF : 1; + uint32_t RESERVED1 : 7; + __I uint32_t SMPU1EAF : 1; + uint32_t RESERVED9 : 7; + __I uint32_t FMPUEAF : 1; + uint32_t RESERVED17 :15; +} stc_mpu_sr_field_t; + +typedef struct +{ + __O uint32_t SMPU2ECLR : 1; + uint32_t RESERVED1 : 7; + __O uint32_t SMPU1ECLR : 1; + uint32_t RESERVED9 : 7; + __O uint32_t FMPUECLR : 1; + uint32_t RESERVED17 :15; +} stc_mpu_eclr_field_t; + +typedef struct +{ + __IO uint32_t MPUWE : 1; + __O uint32_t WKEY :15; + uint32_t RESERVED16 :16; +} stc_mpu_wp_field_t; + +typedef struct +{ + __IO uint32_t SRAMH : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t SRAM12 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t SRAM3 : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SRAMRET : 1; + uint32_t RESERVED11 : 3; + __IO uint32_t DMA1 : 1; + __IO uint32_t DMA2 : 1; + __IO uint32_t FCM : 1; + __IO uint32_t AOS : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t AES : 1; + __IO uint32_t HASH : 1; + __IO uint32_t TRNG : 1; + __IO uint32_t CRC : 1; + __IO uint32_t DCU1 : 1; + __IO uint32_t DCU2 : 1; + __IO uint32_t DCU3 : 1; + __IO uint32_t DCU4 : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t KEY : 1; +} stc_mstp_fcg0_field_t; + +typedef struct +{ + __IO uint32_t CAN : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t QSPI : 1; + __IO uint32_t IIC1 : 1; + __IO uint32_t IIC2 : 1; + __IO uint32_t IIC3 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t USBFS : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SDIOC1 : 1; + __IO uint32_t SDIOC2 : 1; + __IO uint32_t I2S1 : 1; + __IO uint32_t I2S2 : 1; + __IO uint32_t I2S3 : 1; + __IO uint32_t I2S4 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t SPI2 : 1; + __IO uint32_t SPI3 : 1; + __IO uint32_t SPI4 : 1; + uint32_t RESERVED20 : 4; + __IO uint32_t USART1 : 1; + __IO uint32_t USART2 : 1; + __IO uint32_t USART3 : 1; + __IO uint32_t USART4 : 1; + uint32_t RESERVED28 : 4; +} stc_mstp_fcg1_field_t; + +typedef struct +{ + __IO uint32_t TIMER0_1 : 1; + __IO uint32_t TIMER0_2 : 1; + __IO uint32_t TIMERA_1 : 1; + __IO uint32_t TIMERA_2 : 1; + __IO uint32_t TIMERA_3 : 1; + __IO uint32_t TIMERA_4 : 1; + __IO uint32_t TIMERA_5 : 1; + __IO uint32_t TIMERA_6 : 1; + __IO uint32_t TIMER4_1 : 1; + __IO uint32_t TIMER4_2 : 1; + __IO uint32_t TIMER4_3 : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t EMB : 1; + __IO uint32_t TIMER6_1 : 1; + __IO uint32_t TIMER6_2 : 1; + __IO uint32_t TIMER6_3 : 1; + uint32_t RESERVED19 :13; +} stc_mstp_fcg2_field_t; + +typedef struct +{ + __IO uint32_t ADC1 : 1; + __IO uint32_t ADC2 : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t CMP : 1; + uint32_t RESERVED9 : 3; + __IO uint32_t OTS : 1; + uint32_t RESERVED13 :19; +} stc_mstp_fcg3_field_t; + +typedef struct +{ + __IO uint32_t PRT0 : 1; + uint32_t RESERVED1 :15; + __O uint32_t FCG0PCWE :16; +} stc_mstp_fcg0pc_field_t; + +typedef struct +{ + __IO uint16_t OTSST : 1; + __IO uint16_t OTSCK : 1; + __IO uint16_t OTSIE : 1; + __IO uint16_t TSSTP : 1; + uint16_t RESERVED4 :12; +} stc_ots_ctl_field_t; + +typedef struct +{ + __I uint32_t TSOFS : 8; + __I uint32_t TSSLP :24; +} stc_ots_lpr_field_t; + +typedef struct +{ + __IO uint32_t DFB : 1; + __IO uint32_t SOFEN : 1; + uint32_t RESERVED2 :30; +} stc_peric_usbfs_syctlreg_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t SELMMC1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SELMMC2 : 1; + uint32_t RESERVED4 :28; +} stc_peric_sdioc_syctlreg_field_t; + +typedef struct +{ + __I uint16_t PIN00 : 1; + __I uint16_t PIN01 : 1; + __I uint16_t PIN02 : 1; + __I uint16_t PIN03 : 1; + __I uint16_t PIN04 : 1; + __I uint16_t PIN05 : 1; + __I uint16_t PIN06 : 1; + __I uint16_t PIN07 : 1; + __I uint16_t PIN08 : 1; + __I uint16_t PIN09 : 1; + __I uint16_t PIN10 : 1; + __I uint16_t PIN11 : 1; + __I uint16_t PIN12 : 1; + __I uint16_t PIN13 : 1; + __I uint16_t PIN14 : 1; + __I uint16_t PIN15 : 1; +} stc_port_pidr_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + __IO uint16_t POUT03 : 1; + __IO uint16_t POUT04 : 1; + __IO uint16_t POUT05 : 1; + __IO uint16_t POUT06 : 1; + __IO uint16_t POUT07 : 1; + __IO uint16_t POUT08 : 1; + __IO uint16_t POUT09 : 1; + __IO uint16_t POUT10 : 1; + __IO uint16_t POUT11 : 1; + __IO uint16_t POUT12 : 1; + __IO uint16_t POUT13 : 1; + __IO uint16_t POUT14 : 1; + __IO uint16_t POUT15 : 1; +} stc_port_podr_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + __IO uint16_t POUTE03 : 1; + __IO uint16_t POUTE04 : 1; + __IO uint16_t POUTE05 : 1; + __IO uint16_t POUTE06 : 1; + __IO uint16_t POUTE07 : 1; + __IO uint16_t POUTE08 : 1; + __IO uint16_t POUTE09 : 1; + __IO uint16_t POUTE10 : 1; + __IO uint16_t POUTE11 : 1; + __IO uint16_t POUTE12 : 1; + __IO uint16_t POUTE13 : 1; + __IO uint16_t POUTE14 : 1; + __IO uint16_t POUTE15 : 1; +} stc_port_poer_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + __IO uint16_t POS03 : 1; + __IO uint16_t POS04 : 1; + __IO uint16_t POS05 : 1; + __IO uint16_t POS06 : 1; + __IO uint16_t POS07 : 1; + __IO uint16_t POS08 : 1; + __IO uint16_t POS09 : 1; + __IO uint16_t POS10 : 1; + __IO uint16_t POS11 : 1; + __IO uint16_t POS12 : 1; + __IO uint16_t POS13 : 1; + __IO uint16_t POS14 : 1; + __IO uint16_t POS15 : 1; +} stc_port_posr_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + __IO uint16_t POR03 : 1; + __IO uint16_t POR04 : 1; + __IO uint16_t POR05 : 1; + __IO uint16_t POR06 : 1; + __IO uint16_t POR07 : 1; + __IO uint16_t POR08 : 1; + __IO uint16_t POR09 : 1; + __IO uint16_t POR10 : 1; + __IO uint16_t POR11 : 1; + __IO uint16_t POR12 : 1; + __IO uint16_t POR13 : 1; + __IO uint16_t POR14 : 1; + __IO uint16_t POR15 : 1; +} stc_port_porr_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + __IO uint16_t POT03 : 1; + __IO uint16_t POT04 : 1; + __IO uint16_t POT05 : 1; + __IO uint16_t POT06 : 1; + __IO uint16_t POT07 : 1; + __IO uint16_t POT08 : 1; + __IO uint16_t POT09 : 1; + __IO uint16_t POT10 : 1; + __IO uint16_t POT11 : 1; + __IO uint16_t POT12 : 1; + __IO uint16_t POT13 : 1; + __IO uint16_t POT14 : 1; + __IO uint16_t POT15 : 1; +} stc_port_potr_field_t; + +typedef struct +{ + __I uint16_t PIN00 : 1; + __I uint16_t PIN01 : 1; + __I uint16_t PIN02 : 1; + uint16_t RESERVED3 :13; +} stc_port_pidrh_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_podrh_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + uint16_t RESERVED3 :13; +} stc_port_poerh_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + uint16_t RESERVED3 :13; +} stc_port_posrh_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + uint16_t RESERVED3 :13; +} stc_port_porrh_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_potrh_field_t; + +typedef struct +{ + __IO uint16_t SPFE : 5; + uint16_t RESERVED5 :11; +} stc_port_pspcr_field_t; + +typedef struct +{ + __IO uint16_t BFSEL : 4; + uint16_t RESERVED4 :10; + __IO uint16_t RDWT : 2; +} stc_port_pccr_field_t; + +typedef struct +{ + __IO uint16_t PINAE : 6; + uint16_t RESERVED6 :10; +} stc_port_pinaer_field_t; + +typedef struct +{ + __IO uint16_t WE : 1; + uint16_t RESERVED1 : 7; + __O uint16_t WP : 8; +} stc_port_pwpr_field_t; + +typedef struct +{ + __IO uint16_t POUT : 1; + __IO uint16_t POUTE : 1; + __IO uint16_t NOD : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t DRV : 2; + __IO uint16_t PUU : 1; + uint16_t RESERVED7 : 1; + __I uint16_t PIN : 1; + __IO uint16_t INVE : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t INTE : 1; + uint16_t RESERVED13 : 1; + __IO uint16_t LTE : 1; + __IO uint16_t DDIS : 1; +} stc_port_pcr_field_t; + +typedef struct +{ + __IO uint16_t FSEL : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t BFE : 1; + uint16_t RESERVED9 : 7; +} stc_port_pfsr_field_t; + +typedef struct +{ + __IO uint32_t MDSEL : 3; + __IO uint32_t PFE : 1; + __IO uint32_t PFSAE : 1; + __IO uint32_t DCOME : 1; + __IO uint32_t XIPE : 1; + __IO uint32_t SPIMD3 : 1; + __IO uint32_t IPRSL : 2; + __IO uint32_t APRSL : 2; + __IO uint32_t DPRSL : 2; + uint32_t RESERVED14 : 2; + __IO uint32_t DIV : 6; + uint32_t RESERVED22 :10; +} stc_qspi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSHW : 4; + __IO uint32_t SSNW : 2; + uint32_t RESERVED6 :26; +} stc_qspi_cscr_field_t; + +typedef struct +{ + __IO uint32_t AWSL : 2; + __IO uint32_t FOUR_BIC : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t SSNHD : 1; + __IO uint32_t SSNLD : 1; + __IO uint32_t WPOL : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t DMCYCN : 4; + uint32_t RESERVED12 : 3; + __IO uint32_t DUTY : 1; + uint32_t RESERVED16 :16; +} stc_qspi_fcr_field_t; + +typedef struct +{ + __IO uint32_t BUSY : 1; + uint32_t RESERVED1 : 5; + __IO uint32_t XIPF : 1; + __IO uint32_t RAER : 1; + __IO uint32_t PFNUM : 5; + uint32_t RESERVED13 : 1; + __IO uint32_t PFFUL : 1; + __IO uint32_t PFAN : 1; + uint32_t RESERVED16 :16; +} stc_qspi_sr_field_t; + +typedef struct +{ + __IO uint32_t DCOM : 8; + uint32_t RESERVED8 :24; +} stc_qspi_dcom_field_t; + +typedef struct +{ + __IO uint32_t RIC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_ccmd_field_t; + +typedef struct +{ + __IO uint32_t XIPMC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_xcmd_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 7; + __O uint32_t RAERCLR : 1; + uint32_t RESERVED8 :24; +} stc_qspi_sr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 :26; + __IO uint32_t EXADR : 6; +} stc_qspi_exar_field_t; + +typedef struct +{ + __IO uint8_t RESET : 1; + uint8_t RESERVED1 : 7; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint8_t PRDS : 3; + __IO uint8_t AMPM : 1; + __IO uint8_t ALMFCLR : 1; + __IO uint8_t ONEHZOE : 1; + __IO uint8_t ONEHZSEL : 1; + __IO uint8_t START : 1; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint8_t RWREQ : 1; + __IO uint8_t RWEN : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t ALMF : 1; + uint8_t RESERVED4 : 1; + __IO uint8_t PRDIE : 1; + __IO uint8_t ALMIE : 1; + __IO uint8_t ALME : 1; +} stc_rtc_cr2_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t LRCEN : 1; + uint8_t RESERVED5 : 2; + __IO uint8_t RCKSEL : 1; +} stc_rtc_cr3_field_t; + +typedef struct +{ + __IO uint8_t SECU : 4; + __IO uint8_t SECD : 3; + uint8_t RESERVED7 : 1; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint8_t MINU : 4; + __IO uint8_t MIND : 3; + uint8_t RESERVED7 : 1; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint8_t HOURU : 4; + __IO uint8_t HOURD : 2; + uint8_t RESERVED6 : 2; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint8_t WEEK : 3; + uint8_t RESERVED3 : 5; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint8_t DAYU : 4; + __IO uint8_t DAYD : 2; + uint8_t RESERVED6 : 2; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint8_t MON : 5; + uint8_t RESERVED5 : 3; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint8_t YEARU : 4; + __IO uint8_t YEARD : 4; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint8_t ALMMINU : 4; + __IO uint8_t ALMMIND : 3; + uint8_t RESERVED7 : 1; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint8_t ALMHOURU : 4; + __IO uint8_t ALMHOURD : 2; + uint8_t RESERVED6 : 2; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint8_t ALMWEEK : 7; + uint8_t RESERVED7 : 1; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint8_t COMP8 : 1; + uint8_t RESERVED1 : 6; + __IO uint8_t COMPEN : 1; +} stc_rtc_errcrh_field_t; + +typedef struct +{ + __IO uint8_t COMP : 8; +} stc_rtc_errcrl_field_t; + +typedef struct +{ + __IO uint16_t TBS :12; + uint16_t RESERVED12 : 4; +} stc_sdioc_blksize_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 1; + __IO uint16_t BCE : 1; + __IO uint16_t ATCEN : 2; + __IO uint16_t DDIR : 1; + __IO uint16_t MULB : 1; + uint16_t RESERVED6 :10; +} stc_sdioc_transmode_field_t; + +typedef struct +{ + __IO uint16_t RESTYP : 2; + uint16_t RESERVED2 : 1; + __IO uint16_t CCE : 1; + __IO uint16_t ICE : 1; + __IO uint16_t DAT : 1; + __IO uint16_t TYP : 2; + __IO uint16_t IDX : 6; + uint16_t RESERVED14 : 2; +} stc_sdioc_cmd_field_t; + +typedef struct +{ + __I uint32_t CIC : 1; + __I uint32_t CID : 1; + __I uint32_t DA : 1; + uint32_t RESERVED3 : 5; + __I uint32_t WTA : 1; + __I uint32_t RTA : 1; + __I uint32_t BWE : 1; + __I uint32_t BRE : 1; + uint32_t RESERVED12 : 4; + __I uint32_t CIN : 1; + __I uint32_t CSS : 1; + __I uint32_t CDL : 1; + __I uint32_t WPL : 1; + __I uint32_t DATL : 4; + __I uint32_t CMDL : 1; + uint32_t RESERVED25 : 7; +} stc_sdioc_pstat_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 1; + __IO uint8_t DW : 1; + __IO uint8_t HSEN : 1; + uint8_t RESERVED3 : 2; + __IO uint8_t EXDW : 1; + __IO uint8_t CDTL : 1; + __IO uint8_t CDSS : 1; +} stc_sdioc_hostcon_field_t; + +typedef struct +{ + __IO uint8_t PWON : 1; + uint8_t RESERVED1 : 7; +} stc_sdioc_pwrcon_field_t; + +typedef struct +{ + __IO uint8_t SABGR : 1; + __IO uint8_t CR : 1; + __IO uint8_t RWC : 1; + __IO uint8_t IABG : 1; + uint8_t RESERVED4 : 4; +} stc_sdioc_blkgpcon_field_t; + +typedef struct +{ + __IO uint16_t ICE : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t CE : 1; + uint16_t RESERVED3 : 5; + __IO uint16_t FS : 8; +} stc_sdioc_clkcon_field_t; + +typedef struct +{ + __IO uint8_t DTO : 4; + uint8_t RESERVED4 : 4; +} stc_sdioc_toutcon_field_t; + +typedef struct +{ + __IO uint8_t RSTA : 1; + __IO uint8_t RSTC : 1; + __IO uint8_t RSTD : 1; + uint8_t RESERVED3 : 5; +} stc_sdioc_sftrst_field_t; + +typedef struct +{ + __IO uint16_t CC : 1; + __IO uint16_t TC : 1; + __IO uint16_t BGE : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWR : 1; + __IO uint16_t BRR : 1; + __IO uint16_t CIST : 1; + __IO uint16_t CRM : 1; + __I uint16_t CINT : 1; + uint16_t RESERVED9 : 6; + __I uint16_t EI : 1; +} stc_sdioc_norintst_field_t; + +typedef struct +{ + __IO uint16_t CTOE : 1; + __IO uint16_t CCE : 1; + __IO uint16_t CEBE : 1; + __IO uint16_t CIE : 1; + __IO uint16_t DTOE : 1; + __IO uint16_t DCE : 1; + __IO uint16_t DEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintst_field_t; + +typedef struct +{ + __IO uint16_t CCEN : 1; + __IO uint16_t TCEN : 1; + __IO uint16_t BGEEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWREN : 1; + __IO uint16_t BRREN : 1; + __IO uint16_t CISTEN : 1; + __IO uint16_t CRMEN : 1; + __IO uint16_t CINTEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsten_field_t; + +typedef struct +{ + __IO uint16_t CTOEEN : 1; + __IO uint16_t CCEEN : 1; + __IO uint16_t CEBEEN : 1; + __IO uint16_t CIEEN : 1; + __IO uint16_t DTOEEN : 1; + __IO uint16_t DCEEN : 1; + __IO uint16_t DEBEEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACEEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsten_field_t; + +typedef struct +{ + __IO uint16_t CCSEN : 1; + __IO uint16_t TCSEN : 1; + __IO uint16_t BGESEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWRSEN : 1; + __IO uint16_t BRRSEN : 1; + __IO uint16_t CISTSEN : 1; + __IO uint16_t CRMSEN : 1; + __IO uint16_t CINTSEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsgen_field_t; + +typedef struct +{ + __IO uint16_t CTOESEN : 1; + __IO uint16_t CCESEN : 1; + __IO uint16_t CEBESEN : 1; + __IO uint16_t CIESEN : 1; + __IO uint16_t DTOESEN : 1; + __IO uint16_t DCESEN : 1; + __IO uint16_t DEBESEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACESEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsgen_field_t; + +typedef struct +{ + __I uint16_t NE : 1; + __I uint16_t TOE : 1; + __I uint16_t CE : 1; + __I uint16_t EBE : 1; + __I uint16_t IE : 1; + uint16_t RESERVED5 : 2; + __I uint16_t CMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_atcerrst_field_t; + +typedef struct +{ + __O uint16_t FNE : 1; + __O uint16_t FTOE : 1; + __O uint16_t FCE : 1; + __O uint16_t FEBE : 1; + __O uint16_t FIE : 1; + uint16_t RESERVED5 : 2; + __O uint16_t FCMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_fea_field_t; + +typedef struct +{ + __O uint16_t FCTOE : 1; + __O uint16_t FCCE : 1; + __O uint16_t FCEBE : 1; + __O uint16_t FCIE : 1; + __O uint16_t FDTOE : 1; + __O uint16_t FDCE : 1; + __O uint16_t FDEBE : 1; + uint16_t RESERVED7 : 1; + __O uint16_t FACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_fee_field_t; + +typedef struct +{ + __IO uint32_t SPIMDS : 1; + __IO uint32_t TXMDS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t MSTR : 1; + __IO uint32_t SPLPBK : 1; + __IO uint32_t SPLPBK2 : 1; + __IO uint32_t SPE : 1; + __IO uint32_t CSUSPE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t IDIE : 1; + __IO uint32_t MODFE : 1; + __IO uint32_t PATE : 1; + __IO uint32_t PAOE : 1; + __IO uint32_t PAE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cr1_field_t; + +typedef struct +{ + __IO uint32_t FTHLV : 2; + uint32_t RESERVED2 : 4; + __IO uint32_t SPRDTD : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SS0PV : 1; + __IO uint32_t SS1PV : 1; + __IO uint32_t SS2PV : 1; + __IO uint32_t SS3PV : 1; + uint32_t RESERVED12 : 8; + __IO uint32_t MSSI : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t MSSDL : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t MIDI : 3; + uint32_t RESERVED31 : 1; +} stc_spi_cfg1_field_t; + +typedef struct +{ + __IO uint32_t OVRERF : 1; + __I uint32_t IDLNF : 1; + __IO uint32_t MODFERF : 1; + __IO uint32_t PERF : 1; + __IO uint32_t UDRERF : 1; + __IO uint32_t TDEF : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t RDFF : 1; + uint32_t RESERVED8 :24; +} stc_spi_sr_field_t; + +typedef struct +{ + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MBR : 3; + __IO uint32_t SSA : 3; + __IO uint32_t DSIZE : 4; + __IO uint32_t LSBF : 1; + __IO uint32_t MIDIE : 1; + __IO uint32_t MSSDLE : 1; + __IO uint32_t MSSIE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cfg2_field_t; + +typedef struct +{ + __IO uint32_t SRAM12_RWT : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t SRAM12_WWT : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t SRAM3_RWT : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t SRAM3_WWT : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t SRAMH_RWT : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t SRAMH_WWT : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t SRAMR_RWT : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t SRAMR_WWT : 3; + uint32_t RESERVED31 : 1; +} stc_sramc_wtcr_field_t; + +typedef struct +{ + __IO uint32_t WTPRC : 1; + __IO uint32_t WTPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_wtpr_field_t; + +typedef struct +{ + __IO uint32_t PYOAD : 1; + uint32_t RESERVED1 :15; + __IO uint32_t ECCOAD : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t ECCMOD : 2; + uint32_t RESERVED26 : 6; +} stc_sramc_ckcr_field_t; + +typedef struct +{ + __IO uint32_t CKPRC : 1; + __IO uint32_t CKPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_ckpr_field_t; + +typedef struct +{ + __IO uint32_t SRAM3_1ERR : 1; + __IO uint32_t SRAM3_2ERR : 1; + __IO uint32_t SRAM12_PYERR : 1; + __IO uint32_t SRAMH_PYERR : 1; + __IO uint32_t SRAMR_PYERR : 1; + uint32_t RESERVED5 :27; +} stc_sramc_cksr_field_t; + +typedef struct +{ + __I uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_swdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_swdt_rr_field_t; + +typedef struct +{ + __IO uint16_t FLNWT : 1; + __IO uint16_t CKSMRC : 1; + uint16_t RESERVED2 :13; + __IO uint16_t STOP : 1; +} stc_sysreg_pwr_stpmcr_field_t; + +typedef struct +{ + __IO uint16_t PERICKSEL : 4; + uint16_t RESERVED4 :12; +} stc_sysreg_cmu_pericksel_field_t; + +typedef struct +{ + __IO uint16_t I2S1CKSEL : 4; + __IO uint16_t I2S2CKSEL : 4; + __IO uint16_t I2S3CKSEL : 4; + __IO uint16_t I2S4CKSEL : 4; +} stc_sysreg_cmu_i2scksel_field_t; + +typedef struct +{ + __IO uint32_t RAMPDC0 : 1; + __IO uint32_t RAMPDC1 : 1; + __IO uint32_t RAMPDC2 : 1; + __IO uint32_t RAMPDC3 : 1; + __IO uint32_t RAMPDC4 : 1; + __IO uint32_t RAMPDC5 : 1; + __IO uint32_t RAMPDC6 : 1; + __IO uint32_t RAMPDC7 : 1; + __IO uint32_t RAMPDC8 : 1; + uint32_t RESERVED9 :23; +} stc_sysreg_pwr_rampc0_field_t; + +typedef struct +{ + __IO uint32_t AESRDP : 1; + __IO uint32_t AESWRP : 1; + __IO uint32_t HASHRDP : 1; + __IO uint32_t HASHWRP : 1; + __IO uint32_t TRNGRDP : 1; + __IO uint32_t TRNGWRP : 1; + __IO uint32_t CRCRDP : 1; + __IO uint32_t CRCWRP : 1; + __IO uint32_t FMCRDP : 1; + __IO uint32_t FMCWRP : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t WDTRDP : 1; + __IO uint32_t WDTWRP : 1; + __IO uint32_t SWDTRDP : 1; + __IO uint32_t SWDTWRP : 1; + __IO uint32_t BKSRAMRDP : 1; + __IO uint32_t BKSRAMWRP : 1; + __IO uint32_t RTCRDP : 1; + __IO uint32_t RTCWRP : 1; + __IO uint32_t DMPURDP : 1; + __IO uint32_t DMPUWRP : 1; + __IO uint32_t SRAMCRDP : 1; + __IO uint32_t SRAMCWRP : 1; + __IO uint32_t INTCRDP : 1; + __IO uint32_t INTCWRP : 1; + __IO uint32_t SYSCRDP : 1; + __IO uint32_t SYSCWRP : 1; + __IO uint32_t MSTPRDP : 1; + __IO uint32_t MSTPWRP : 1; + uint32_t RESERVED30 : 1; + __IO uint32_t BUSERRE : 1; +} stc_sysreg_mpu_ippr_field_t; + +typedef struct +{ + __IO uint32_t PCLK0S : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t PCLK1S : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t PCLK2S : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t PCLK3S : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t PCLK4S : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t EXCKS : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t HCLKS : 3; + uint32_t RESERVED27 : 5; +} stc_sysreg_cmu_scfgr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t USBCKS : 4; +} stc_sysreg_cmu_ufsckcfgr_field_t; + +typedef struct +{ + __IO uint8_t CKSW : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_ckswr_field_t; + +typedef struct +{ + __IO uint8_t MPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_pllcr_field_t; + +typedef struct +{ + __IO uint8_t UPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_upllcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalcr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_hrccr_field_t; + +typedef struct +{ + __IO uint8_t MRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_mrccr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTBF : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t XTALSTBF : 1; + uint8_t RESERVED4 : 1; + __IO uint8_t MPLLSTBF : 1; + __IO uint8_t UPLLSTBF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_cmu_oscstbsr_field_t; + +typedef struct +{ + __IO uint8_t MCO1SEL : 4; + __IO uint8_t MCO1DIV : 3; + __IO uint8_t MCO1EN : 1; +} stc_sysreg_cmu_mco1cfgr_field_t; + +typedef struct +{ + __IO uint8_t MCO2SEL : 4; + __IO uint8_t MCO2DIV : 3; + __IO uint8_t MCO2EN : 1; +} stc_sysreg_cmu_mco2cfgr_field_t; + +typedef struct +{ + __IO uint8_t TPIUCKS : 2; + uint8_t RESERVED2 : 5; + __IO uint8_t TPIUCKOE : 1; +} stc_sysreg_cmu_tpiuckcfgr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDIE : 1; + __IO uint8_t XTALSTDRE : 1; + __IO uint8_t XTALSTDRIS : 1; + uint8_t RESERVED3 : 4; + __IO uint8_t XTALSTDE : 1; +} stc_sysreg_cmu_xtalstdcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalstdsr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTB : 4; + uint8_t RESERVED4 : 4; +} stc_sysreg_cmu_xtalstbcr_field_t; + +typedef struct +{ + __IO uint16_t PORF : 1; + __IO uint16_t PINRF : 1; + __IO uint16_t BORF : 1; + __IO uint16_t PVD1RF : 1; + __IO uint16_t PVD2RF : 1; + __IO uint16_t WDRF : 1; + __IO uint16_t SWDRF : 1; + __IO uint16_t PDRF : 1; + __IO uint16_t SWRF : 1; + __IO uint16_t MPUERF : 1; + __IO uint16_t RAPERF : 1; + __IO uint16_t RAECRF : 1; + __IO uint16_t CKFERF : 1; + __IO uint16_t XTALERF : 1; + __IO uint16_t MULTIRF : 1; + __IO uint16_t CLRF : 1; +} stc_sysreg_rmu_rstf0_field_t; + +typedef struct +{ + __IO uint8_t PVD1NMIS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t PVD2NMIS : 1; + uint8_t RESERVED5 : 3; +} stc_sysreg_pwr_pvdicr_field_t; + +typedef struct +{ + __IO uint8_t PVD1MON : 1; + __IO uint8_t PVD1DETFLG : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t PVD2MON : 1; + __IO uint8_t PVD2DETFLG : 1; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pvddsr_field_t; + +typedef struct +{ + __IO uint32_t MPLLM : 5; + uint32_t RESERVED5 : 2; + __IO uint32_t PLLSRC : 1; + __IO uint32_t MPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t MPLLR : 4; + __IO uint32_t MPLLQ : 4; + __IO uint32_t MPLLP : 4; +} stc_sysreg_cmu_pllcfgr_field_t; + +typedef struct +{ + __IO uint32_t UPLLM : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t UPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t UPLLR : 4; + __IO uint32_t UPLLQ : 4; + __IO uint32_t UPLLP : 4; +} stc_sysreg_cmu_upllcfgr_field_t; + +typedef struct +{ + __IO uint16_t FPRCB0 : 1; + __IO uint16_t FPRCB1 : 1; + __IO uint16_t FPRCB2 : 1; + __IO uint16_t FPRCB3 : 1; + uint16_t RESERVED4 : 4; + __IO uint16_t FPRCWE : 8; +} stc_sysreg_pwr_fprc_field_t; + +typedef struct +{ + __IO uint8_t PDMDS : 2; + __IO uint8_t VVDRSD : 1; + __IO uint8_t RETRAMSD : 1; + __IO uint8_t IORTN : 2; + uint8_t RESERVED6 : 1; + __IO uint8_t PWDN : 1; +} stc_sysreg_pwr_pwrc0_field_t; + +typedef struct +{ + __IO uint8_t VPLLSD : 1; + __IO uint8_t VHRCSD : 1; + uint8_t RESERVED2 : 4; + __IO uint8_t STPDAS : 2; +} stc_sysreg_pwr_pwrc1_field_t; + +typedef struct +{ + __IO uint8_t DDAS : 4; + __IO uint8_t DVS : 2; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pwrc2_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 2; + __IO uint8_t PDTS : 1; + uint8_t RESERVED3 : 5; +} stc_sysreg_pwr_pwrc3_field_t; + +typedef struct +{ + __IO uint8_t WKE00 : 1; + __IO uint8_t WKE01 : 1; + __IO uint8_t WKE02 : 1; + __IO uint8_t WKE03 : 1; + __IO uint8_t WKE10 : 1; + __IO uint8_t WKE11 : 1; + __IO uint8_t WKE12 : 1; + __IO uint8_t WKE13 : 1; +} stc_sysreg_pwr_pdwke0_field_t; + +typedef struct +{ + __IO uint8_t WKE20 : 1; + __IO uint8_t WKE21 : 1; + __IO uint8_t WKE22 : 1; + __IO uint8_t WKE23 : 1; + __IO uint8_t WKE30 : 1; + __IO uint8_t WKE31 : 1; + __IO uint8_t WKE32 : 1; + __IO uint8_t WKE33 : 1; +} stc_sysreg_pwr_pdwke1_field_t; + +typedef struct +{ + __IO uint8_t VD1WKE : 1; + __IO uint8_t VD2WKE : 1; + __IO uint8_t NMIWKE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t RTCPRDWKE : 1; + __IO uint8_t RTCALMWKE : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKE : 1; +} stc_sysreg_pwr_pdwke2_field_t; + +typedef struct +{ + __IO uint8_t WK0EGS : 1; + __IO uint8_t WK1EGS : 1; + __IO uint8_t WK2EGS : 1; + __IO uint8_t WK3EGS : 1; + __IO uint8_t VD1EGS : 1; + __IO uint8_t VD2EGS : 1; + __IO uint8_t NMIEGS : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkes_field_t; + +typedef struct +{ + __IO uint8_t PTWK0F : 1; + __IO uint8_t PTWK1F : 1; + __IO uint8_t PTWK2F : 1; + __IO uint8_t PTWK3F : 1; + __IO uint8_t VD1WKF : 1; + __IO uint8_t VD2WKF : 1; + __IO uint8_t NMIWKF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkf0_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t RTCPRDWKF : 1; + __IO uint8_t RTCALMWKF : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKF : 1; +} stc_sysreg_pwr_pdwkf1_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t ADBUFE : 1; +} stc_sysreg_pwr_pwcmr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t XTALDRV : 2; + __IO uint8_t XTALMS : 1; + __IO uint8_t SUPDRV : 1; +} stc_sysreg_cmu_xtalcfgr_field_t; + +typedef struct +{ + __IO uint8_t EXVCCINEN : 1; + uint8_t RESERVED1 : 4; + __IO uint8_t PVD1EN : 1; + __IO uint8_t PVD2EN : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr0_field_t; + +typedef struct +{ + __IO uint8_t PVD1IRE : 1; + __IO uint8_t PVD1IRS : 1; + __IO uint8_t PVD1CMPOE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2IRE : 1; + __IO uint8_t PVD2IRS : 1; + __IO uint8_t PVD2CMPOE : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr1_field_t; + +typedef struct +{ + __IO uint8_t PVD1NFDIS : 1; + __IO uint8_t PVD1NFCKS : 2; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2NFDIS : 1; + __IO uint8_t PVD2NFCKS : 2; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdfcr_field_t; + +typedef struct +{ + __IO uint8_t PVD1LVL : 3; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2LVL : 3; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdlcr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32STP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtal32cr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32DRV : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_xtal32cfgr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32NF : 2; + uint8_t RESERVED2 : 6; +} stc_sysreg_cmu_xtal32nfr_field_t; + +typedef struct +{ + __IO uint8_t LRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_lrccr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t CSDIS : 1; +} stc_sysreg_pwr_xtal32cs_field_t; + +typedef struct +{ + __IO uint32_t CNTA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntar_field_t; + +typedef struct +{ + __IO uint32_t CNTB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntbr_field_t; + +typedef struct +{ + __IO uint32_t CMPA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpar_field_t; + +typedef struct +{ + __IO uint32_t CMPB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpbr_field_t; + +typedef struct +{ + __IO uint32_t CSTA : 1; + __IO uint32_t CAPMDA : 1; + __IO uint32_t INTENA : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t CKDIVA : 4; + __IO uint32_t SYNSA : 1; + __IO uint32_t SYNCLKA : 1; + __IO uint32_t ASYNCLKA : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HSTAA : 1; + __IO uint32_t HSTPA : 1; + __IO uint32_t HCLEA : 1; + __IO uint32_t HICPA : 1; + __IO uint32_t CSTB : 1; + __IO uint32_t CAPMDB : 1; + __IO uint32_t INTENB : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t CKDIVB : 4; + __IO uint32_t SYNSB : 1; + __IO uint32_t SYNCLKB : 1; + __IO uint32_t ASYNCLKB : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t HSTAB : 1; + __IO uint32_t HSTPB : 1; + __IO uint32_t HCLEB : 1; + __IO uint32_t HICPB : 1; +} stc_tmr0_bconr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + uint32_t RESERVED1 :15; + __IO uint32_t CMBF : 1; + uint32_t RESERVED17 :15; +} stc_tmr0_stflr_field_t; + +typedef struct +{ + __IO uint16_t OCEH : 1; + __IO uint16_t OCEL : 1; + __IO uint16_t OCPH : 1; + __IO uint16_t OCPL : 1; + __IO uint16_t OCIEH : 1; + __IO uint16_t OCIEL : 1; + __IO uint16_t OCFH : 1; + __IO uint16_t OCFL : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ocsr_field_t; + +typedef struct +{ + __IO uint16_t CHBUFEN : 2; + __IO uint16_t CLBUFEN : 2; + __IO uint16_t MHBUFEN : 2; + __IO uint16_t MLBUFEN : 2; + __IO uint16_t LMCH : 1; + __IO uint16_t LMCL : 1; + __IO uint16_t LMMH : 1; + __IO uint16_t LMML : 1; + __IO uint16_t MCECH : 1; + __IO uint16_t MCECL : 1; + uint16_t RESERVED14 : 2; +} stc_tmr4_ocer_field_t; + +typedef struct +{ + __IO uint16_t OCFDCH : 1; + __IO uint16_t OCFPKH : 1; + __IO uint16_t OCFUCH : 1; + __IO uint16_t OCFZRH : 1; + __IO uint16_t OPDCH : 2; + __IO uint16_t OPPKH : 2; + __IO uint16_t OPUCH : 2; + __IO uint16_t OPZRH : 2; + __IO uint16_t OPNPKH : 2; + __IO uint16_t OPNZRH : 2; +} stc_tmr4_ocmrh_field_t; + +typedef struct +{ + __IO uint32_t OCFDCL : 1; + __IO uint32_t OCFPKL : 1; + __IO uint32_t OCFUCL : 1; + __IO uint32_t OCFZRL : 1; + __IO uint32_t OPDCL : 2; + __IO uint32_t OPPKL : 2; + __IO uint32_t OPUCL : 2; + __IO uint32_t OPZRL : 2; + __IO uint32_t OPNPKL : 2; + __IO uint32_t OPNZRL : 2; + __IO uint32_t EOPNDCL : 2; + __IO uint32_t EOPNUCL : 2; + __IO uint32_t EOPDCL : 2; + __IO uint32_t EOPPKL : 2; + __IO uint32_t EOPUCL : 2; + __IO uint32_t EOPZRL : 2; + __IO uint32_t EOPNPKL : 2; + __IO uint32_t EOPNZRL : 2; +} stc_tmr4_ocmrl_field_t; + +typedef struct +{ + __IO uint16_t CKDIV : 4; + __IO uint16_t CLEAR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BUFEN : 1; + __IO uint16_t IRQPEN : 1; + __IO uint16_t IRQPF : 1; + uint16_t RESERVED10 : 3; + __IO uint16_t IRQZEN : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKEN : 1; +} stc_tmr4_ccsr_field_t; + +typedef struct +{ + __IO uint16_t ZIM : 4; + __IO uint16_t PIM : 4; + __I uint16_t ZIC : 4; + __I uint16_t PIC : 4; +} stc_tmr4_cvpr_field_t; + +typedef struct +{ + __IO uint16_t DIVCK : 4; + __IO uint16_t PWMMD : 2; + __IO uint16_t LVLS : 2; + uint16_t RESERVED8 : 8; +} stc_tmr4_pocr_field_t; + +typedef struct +{ + __IO uint16_t RTIDU : 1; + __IO uint16_t RTIDV : 1; + __IO uint16_t RTIDW : 1; + uint16_t RESERVED3 : 1; + __I uint16_t RTIFU : 1; + __IO uint16_t RTICU : 1; + __IO uint16_t RTEU : 1; + __IO uint16_t RTSU : 1; + __I uint16_t RTIFV : 1; + __IO uint16_t RTICV : 1; + __IO uint16_t RTEV : 1; + __IO uint16_t RTSV : 1; + __I uint16_t RTIFW : 1; + __IO uint16_t RTICW : 1; + __IO uint16_t RTEW : 1; + __IO uint16_t RTSW : 1; +} stc_tmr4_rcsr_field_t; + +typedef struct +{ + __IO uint16_t BUFEN : 2; + __IO uint16_t EVTOS : 3; + __IO uint16_t LMC : 1; + uint16_t RESERVED6 : 2; + __IO uint16_t EVTMS : 1; + __IO uint16_t EVTDS : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t DEN : 1; + __IO uint16_t PEN : 1; + __IO uint16_t UEN : 1; + __IO uint16_t ZEN : 1; +} stc_tmr4_scsr_field_t; + +typedef struct +{ + __IO uint16_t AMC : 4; + uint16_t RESERVED4 : 2; + __IO uint16_t MZCE : 1; + __IO uint16_t MPCE : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_scmr_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 7; + __IO uint16_t HOLD : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ecsr_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer1_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer2_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer3_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmr6_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perbr_field_t; + +typedef struct +{ + __IO uint32_t PERC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_percr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t GCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmer_field_t; + +typedef struct +{ + __IO uint32_t GCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmfr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmbr_field_t; + +typedef struct +{ + __IO uint32_t SCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmcr_field_t; + +typedef struct +{ + __IO uint32_t SCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmdr_field_t; + +typedef struct +{ + __IO uint32_t SCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmer_field_t; + +typedef struct +{ + __IO uint32_t SCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmfr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdar_field_t; + +typedef struct +{ + __IO uint32_t DTUB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtubr_field_t; + +typedef struct +{ + __IO uint32_t DTDB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdbr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSKVAL : 2; + uint32_t RESERVED20 :12; +} stc_tmr6_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + __IO uint32_t INTENE : 1; + __IO uint32_t INTENF : 1; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDTE : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; + uint32_t RESERVED20 :12; +} stc_tmr6_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMDA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t EMBVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPMDB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + uint32_t RESERVED25 : 2; + __IO uint32_t EMBVALB : 2; + uint32_t RESERVED29 : 3; +} stc_tmr6_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + __IO uint32_t BSEA : 1; + __IO uint32_t BENB : 1; + __IO uint32_t BSEB : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t BENP : 1; + __IO uint32_t BSEP : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t BENSPA : 1; + __IO uint32_t BSESPA : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t BTRSPA : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t BENSPB : 1; + __IO uint32_t BSESPB : 1; + uint32_t RESERVED26 : 2; + __IO uint32_t BTRSPB : 2; + uint32_t RESERVED30 : 2; +} stc_tmr6_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTBENU : 1; + __IO uint32_t DTBEND : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t SEPA : 1; + uint32_t RESERVED9 :23; +} stc_tmr6_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 9; +} stc_tmr6_fconr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t SPPERIA : 1; + __IO uint32_t SPPERIB : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; + uint32_t RESERVED21 :11; +} stc_tmr6_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + __IO uint32_t CMEF : 1; + __IO uint32_t CMFF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __I uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __I uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __I uint32_t DIRF : 1; +} stc_tmr6_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STARTS : 1; +} stc_tmr6_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STOPS : 1; +} stc_tmr6_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + __IO uint32_t HCLE7 : 1; + __IO uint32_t HCLE8 : 1; + __IO uint32_t HCLE9 : 1; + __IO uint32_t HCLE10 : 1; + __IO uint32_t HCLE11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t CLEARS : 1; +} stc_tmr6_hclrr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcdor_field_t; + +typedef struct +{ + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; + __IO uint32_t SSTA3 : 1; + uint32_t RESERVED3 :13; + __IO uint32_t RESV0 : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t RESV : 1; + uint32_t RESERVED25 : 7; +} stc_tmr6_cr_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; + __IO uint32_t SSTP3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLE1 : 1; + __IO uint32_t SCLE2 : 1; + __IO uint32_t SCLE3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sclrr_field_t; + +typedef struct +{ + __IO uint16_t CNT :16; +} stc_tmra_cnter_field_t; + +typedef struct +{ + __IO uint16_t PER :16; +} stc_tmra_perar_field_t; + +typedef struct +{ + __IO uint16_t CMP :16; +} stc_tmra_cmpar_field_t; + +typedef struct +{ + __IO uint16_t START : 1; + __IO uint16_t DIR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t SYNST : 1; + __IO uint16_t CKDIV : 4; + uint16_t RESERVED8 : 4; + __IO uint16_t ITENOVF : 1; + __IO uint16_t ITENUDF : 1; + __IO uint16_t OVFF : 1; + __IO uint16_t UDFF : 1; +} stc_tmra_bcstr_field_t; + +typedef struct +{ + __IO uint16_t HSTA0 : 1; + __IO uint16_t HSTA1 : 1; + __IO uint16_t HSTA2 : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t HSTP0 : 1; + __IO uint16_t HSTP1 : 1; + __IO uint16_t HSTP2 : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t HCLE0 : 1; + __IO uint16_t HCLE1 : 1; + __IO uint16_t HCLE2 : 1; + uint16_t RESERVED11 : 1; + __IO uint16_t HCLE3 : 1; + __IO uint16_t HCLE4 : 1; + __IO uint16_t HCLE5 : 1; + __IO uint16_t HCLE6 : 1; +} stc_tmra_hconr_field_t; + +typedef struct +{ + __IO uint16_t HCUP0 : 1; + __IO uint16_t HCUP1 : 1; + __IO uint16_t HCUP2 : 1; + __IO uint16_t HCUP3 : 1; + __IO uint16_t HCUP4 : 1; + __IO uint16_t HCUP5 : 1; + __IO uint16_t HCUP6 : 1; + __IO uint16_t HCUP7 : 1; + __IO uint16_t HCUP8 : 1; + __IO uint16_t HCUP9 : 1; + __IO uint16_t HCUP10 : 1; + __IO uint16_t HCUP11 : 1; + __IO uint16_t HCUP12 : 1; + uint16_t RESERVED13 : 3; +} stc_tmra_hcupr_field_t; + +typedef struct +{ + __IO uint16_t HCDO0 : 1; + __IO uint16_t HCDO1 : 1; + __IO uint16_t HCDO2 : 1; + __IO uint16_t HCDO3 : 1; + __IO uint16_t HCDO4 : 1; + __IO uint16_t HCDO5 : 1; + __IO uint16_t HCDO6 : 1; + __IO uint16_t HCDO7 : 1; + __IO uint16_t HCDO8 : 1; + __IO uint16_t HCDO9 : 1; + __IO uint16_t HCDO10 : 1; + __IO uint16_t HCDO11 : 1; + __IO uint16_t HCDO12 : 1; + uint16_t RESERVED13 : 3; +} stc_tmra_hcdor_field_t; + +typedef struct +{ + __IO uint16_t ITEN1 : 1; + __IO uint16_t ITEN2 : 1; + __IO uint16_t ITEN3 : 1; + __IO uint16_t ITEN4 : 1; + __IO uint16_t ITEN5 : 1; + __IO uint16_t ITEN6 : 1; + __IO uint16_t ITEN7 : 1; + __IO uint16_t ITEN8 : 1; + uint16_t RESERVED8 : 8; +} stc_tmra_iconr_field_t; + +typedef struct +{ + __IO uint16_t ETEN1 : 1; + __IO uint16_t ETEN2 : 1; + __IO uint16_t ETEN3 : 1; + __IO uint16_t ETEN4 : 1; + __IO uint16_t ETEN5 : 1; + __IO uint16_t ETEN6 : 1; + __IO uint16_t ETEN7 : 1; + __IO uint16_t ETEN8 : 1; + uint16_t RESERVED8 : 8; +} stc_tmra_econr_field_t; + +typedef struct +{ + __IO uint16_t NOFIENTG : 1; + __IO uint16_t NOFICKTG : 2; + uint16_t RESERVED3 : 5; + __IO uint16_t NOFIENCA : 1; + __IO uint16_t NOFICKCA : 2; + uint16_t RESERVED11 : 1; + __IO uint16_t NOFIENCB : 1; + __IO uint16_t NOFICKCB : 2; + uint16_t RESERVED15 : 1; +} stc_tmra_fconr_field_t; + +typedef struct +{ + __IO uint16_t CMPF1 : 1; + __IO uint16_t CMPF2 : 1; + __IO uint16_t CMPF3 : 1; + __IO uint16_t CMPF4 : 1; + __IO uint16_t CMPF5 : 1; + __IO uint16_t CMPF6 : 1; + __IO uint16_t CMPF7 : 1; + __IO uint16_t CMPF8 : 1; + uint16_t RESERVED8 : 8; +} stc_tmra_stflr_field_t; + +typedef struct +{ + __IO uint16_t BEN : 1; + __IO uint16_t BSE0 : 1; + __IO uint16_t BSE1 : 1; + uint16_t RESERVED3 :13; +} stc_tmra_bconr_field_t; + +typedef struct +{ + __IO uint16_t CAPMD : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t HICP0 : 1; + __IO uint16_t HICP1 : 1; + __IO uint16_t HICP2 : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t HICP3 : 1; + __IO uint16_t HICP4 : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t NOFIENCP : 1; + __IO uint16_t NOFICKCP : 2; + uint16_t RESERVED15 : 1; +} stc_tmra_cconr_field_t; + +typedef struct +{ + __IO uint16_t STAC : 2; + __IO uint16_t STPC : 2; + __IO uint16_t CMPC : 2; + __IO uint16_t PERC : 2; + __IO uint16_t FORC : 2; + uint16_t RESERVED10 : 2; + __IO uint16_t OUTEN : 1; + uint16_t RESERVED13 : 3; +} stc_tmra_pconr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t RUN : 1; + uint32_t RESERVED2 :30; +} stc_trng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CNT : 3; + uint32_t RESERVED5 :27; +} stc_trng_mr_field_t; + +typedef struct +{ + __I uint32_t PE : 1; + __I uint32_t FE : 1; + uint32_t RESERVED2 : 1; + __I uint32_t ORE : 1; + uint32_t RESERVED4 : 1; + __I uint32_t RXNE : 1; + __I uint32_t TC : 1; + __I uint32_t TXE : 1; + __I uint32_t RTOF : 1; + uint32_t RESERVED9 : 7; + __I uint32_t MPB : 1; + uint32_t RESERVED17 :15; +} stc_usart_sr_field_t; + +typedef struct +{ + __IO uint32_t TDR : 9; + __IO uint32_t MPID : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t RDR : 9; + uint32_t RESERVED25 : 7; +} stc_usart_dr_field_t; + +typedef struct +{ + __IO uint32_t DIV_FRACTION : 7; + uint32_t RESERVED7 : 1; + __IO uint32_t DIV_INTEGER : 8; + uint32_t RESERVED16 :16; +} stc_usart_brr_field_t; + +typedef struct +{ + __IO uint32_t RTOE : 1; + __IO uint32_t RTOIE : 1; + __IO uint32_t RE : 1; + __IO uint32_t TE : 1; + __IO uint32_t SLME : 1; + __IO uint32_t RIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t TXEIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t PS : 1; + __IO uint32_t PCE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t M : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t OVER8 : 1; + __O uint32_t CPE : 1; + __O uint32_t CFE : 1; + uint32_t RESERVED18 : 1; + __O uint32_t CORE : 1; + __O uint32_t CRTOF : 1; + uint32_t RESERVED21 : 3; + __IO uint32_t MS : 1; + uint32_t RESERVED25 : 3; + __IO uint32_t ML : 1; + __IO uint32_t FBME : 1; + __IO uint32_t NFE : 1; + __IO uint32_t SBS : 1; +} stc_usart_cr1_field_t; + +typedef struct +{ + __IO uint32_t MPE : 1; + uint32_t RESERVED1 :10; + __IO uint32_t CLKC : 2; + __IO uint32_t STOP : 1; + uint32_t RESERVED14 :18; +} stc_usart_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t SCEN : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t CTSE : 1; + uint32_t RESERVED10 :11; + __IO uint32_t BCN : 3; + uint32_t RESERVED24 : 8; +} stc_usart_cr3_field_t; + +typedef struct +{ + __IO uint32_t PSC : 2; + uint32_t RESERVED2 :30; +} stc_usart_pr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 6; + __IO uint32_t VBUSOVEN : 1; + __IO uint32_t VBUSVAL : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_gvbuscfg_field_t; + +typedef struct +{ + __IO uint32_t GINTMSK : 1; + __IO uint32_t HBSTLEN : 4; + __IO uint32_t DMAEN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXFELVL : 1; + __IO uint32_t PTXFELVL : 1; + uint32_t RESERVED9 :23; +} stc_usbfs_gahbcfg_field_t; + +typedef struct +{ + __IO uint32_t TOCAL : 3; + uint32_t RESERVED3 : 3; + __IO uint32_t PHYSEL : 1; + uint32_t RESERVED7 : 3; + __IO uint32_t TRDT : 4; + uint32_t RESERVED14 :15; + __IO uint32_t FHMOD : 1; + __IO uint32_t FDMOD : 1; + uint32_t RESERVED31 : 1; +} stc_usbfs_gusbcfg_field_t; + +typedef struct +{ + __IO uint32_t CSRST : 1; + __IO uint32_t HSRST : 1; + __IO uint32_t FCRST : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t RXFFLSH : 1; + __IO uint32_t TXFFLSH : 1; + __IO uint32_t TXFNUM : 5; + uint32_t RESERVED11 :19; + __I uint32_t DMAREQ : 1; + __I uint32_t AHBIDL : 1; +} stc_usbfs_grstctl_field_t; + +typedef struct +{ + __I uint32_t CMOD : 1; + __IO uint32_t MMIS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOF : 1; + __I uint32_t RXFNE : 1; + __I uint32_t NPTXFE : 1; + __I uint32_t GINAKEFF : 1; + __I uint32_t GONAKEFF : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSP : 1; + __IO uint32_t USBSUSP : 1; + __IO uint32_t USBRST : 1; + __IO uint32_t ENUMDNE : 1; + __IO uint32_t ISOODRP : 1; + __IO uint32_t EOPF : 1; + uint32_t RESERVED16 : 2; + __I uint32_t IEPINT : 1; + __I uint32_t OEPINT : 1; + __IO uint32_t IISOIXFR : 1; + __IO uint32_t IPXFR_INCOMPISOOUT : 1; + __IO uint32_t DATAFSUSP : 1; + uint32_t RESERVED23 : 1; + __I uint32_t HPRTINT : 1; + __I uint32_t HCINT : 1; + __I uint32_t PTXFE : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHG : 1; + __IO uint32_t DISCINT : 1; + __IO uint32_t VBUSVINT : 1; + __IO uint32_t WKUINT : 1; +} stc_usbfs_gintsts_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t MMISM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOFM : 1; + __IO uint32_t RXFNEM : 1; + __IO uint32_t NPTXFEM : 1; + __IO uint32_t GINAKEFFM : 1; + __IO uint32_t GONAKEFFM : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSPM : 1; + __IO uint32_t USBSUSPM : 1; + __IO uint32_t USBRSTM : 1; + __IO uint32_t ENUMDNEM : 1; + __IO uint32_t ISOODRPM : 1; + __IO uint32_t EOPFM : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPIM : 1; + __IO uint32_t OEPIM : 1; + __IO uint32_t IISOIXFRM : 1; + __IO uint32_t IPXFRM_INCOMPISOOUTM : 1; + __IO uint32_t DATAFSUSPM : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTIM : 1; + __IO uint32_t HCIM : 1; + __IO uint32_t PTXFEM : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHGM : 1; + __IO uint32_t DISCIM : 1; + __IO uint32_t VBUSVIM : 1; + __IO uint32_t WKUIM : 1; +} stc_usbfs_gintmsk_field_t; + +typedef struct +{ + __I uint32_t CHNUM_EPNUM : 4; + __I uint32_t BCNT :11; + __I uint32_t DPID : 2; + __I uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsr_field_t; + +typedef struct +{ + __I uint32_t CHNUM_EPNUM : 4; + __I uint32_t BCNT :11; + __I uint32_t DPID : 2; + __I uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsp_field_t; + +typedef struct +{ + __IO uint32_t RXFD :11; + uint32_t RESERVED11 :21; +} stc_usbfs_grxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSA :16; + __IO uint32_t NPTXFD :16; +} stc_usbfs_hnptxfsiz_field_t; + +typedef struct +{ + __I uint32_t NPTXFSAV :16; + __I uint32_t NPTQXSAV : 8; + __I uint32_t NPTXQTOP : 7; + uint32_t RESERVED31 : 1; +} stc_usbfs_hnptxsts_field_t; + +typedef struct +{ + __IO uint32_t PTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t PTXFD :11; + uint32_t RESERVED27 : 5; +} stc_usbfs_hptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t INEPTXFD :10; + uint32_t RESERVED26 : 6; +} stc_usbfs_dieptxf_field_t; + +typedef struct +{ + __IO uint32_t FSLSPCS : 2; + __IO uint32_t FSLSS : 1; + uint32_t RESERVED3 :29; +} stc_usbfs_hcfg_field_t; + +typedef struct +{ + __IO uint32_t FRIVL :16; + uint32_t RESERVED16 :16; +} stc_usbfs_hfir_field_t; + +typedef struct +{ + __I uint32_t FRNUM :16; + __I uint32_t FTREM :16; +} stc_usbfs_hfnum_field_t; + +typedef struct +{ + __I uint32_t PTXFSAVL :16; + __I uint32_t PTXQSAV : 8; + __I uint32_t PTXQTOP : 8; +} stc_usbfs_hptxsts_field_t; + +typedef struct +{ + __I uint32_t HAINT :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haint_field_t; + +typedef struct +{ + __IO uint32_t HAINTM :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haintmsk_field_t; + +typedef struct +{ + __I uint32_t PCSTS : 1; + __IO uint32_t PCDET : 1; + __IO uint32_t PENA : 1; + __IO uint32_t PENCHNG : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t PRES : 1; + __IO uint32_t PSUSP : 1; + __IO uint32_t PRST : 1; + uint32_t RESERVED9 : 1; + __I uint32_t PLSTS : 2; + __IO uint32_t PWPR : 1; + uint32_t RESERVED13 : 4; + __I uint32_t PSPD : 2; + uint32_t RESERVED19 :13; +} stc_usbfs_hprt_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + __IO uint32_t EPNUM : 4; + __IO uint32_t EPDIR : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t LSDEV : 1; + __I uint32_t EPTYP : 2; + uint32_t RESERVED20 : 2; + __IO uint32_t DAD : 7; + __IO uint32_t ODDFRM : 1; + __IO uint32_t CHDIS : 1; + __IO uint32_t CHENA : 1; +} stc_usbfs_hcchar_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t CHH : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t NAK : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERR : 1; + __IO uint32_t BBERR : 1; + __IO uint32_t FRMOR : 1; + __IO uint32_t DTERR : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcint_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t CHHM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALLM : 1; + __IO uint32_t NAKM : 1; + __IO uint32_t ACKM : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERRM : 1; + __IO uint32_t BBERRM : 1; + __IO uint32_t FRMORM : 1; + __IO uint32_t DTERRM : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcintmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + __IO uint32_t DPID : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_hctsiz_field_t; + +typedef struct +{ + __IO uint32_t DSPD : 2; + __IO uint32_t NZLSOHSK : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t DAD : 7; + __IO uint32_t PFIVL : 2; + uint32_t RESERVED13 :19; +} stc_usbfs_dcfg_field_t; + +typedef struct +{ + __IO uint32_t RWUSIG : 1; + __IO uint32_t SDIS : 1; + __I uint32_t GINSTS : 1; + __I uint32_t GONSTS : 1; + uint32_t RESERVED4 : 3; + __O uint32_t SGINAK : 1; + __O uint32_t CGINAK : 1; + __O uint32_t SGONAK : 1; + __O uint32_t CGONAK : 1; + __IO uint32_t POPRGDNE : 1; + uint32_t RESERVED12 :20; +} stc_usbfs_dctl_field_t; + +typedef struct +{ + __I uint32_t SUSPSTS : 1; + __I uint32_t ENUMSPD : 2; + __I uint32_t EERR : 1; + uint32_t RESERVED4 : 4; + __I uint32_t FNSOF :14; + uint32_t RESERVED22 :10; +} stc_usbfs_dsts_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOM : 1; + __IO uint32_t ITTXFEMSK : 1; + __IO uint32_t INEPNMM : 1; + __IO uint32_t INEPNEM : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_diepmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUPM : 1; + __IO uint32_t OTEPDM : 1; + uint32_t RESERVED5 :27; +} stc_usbfs_doepmsk_field_t; + +typedef struct +{ + __I uint32_t IEPINT : 6; + uint32_t RESERVED6 :10; + __I uint32_t OEPINT : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daint_field_t; + +typedef struct +{ + __I uint32_t IEPINTM : 6; + uint32_t RESERVED6 :10; + __I uint32_t OEPINTM : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daintmsk_field_t; + +typedef struct +{ + __IO uint32_t INEPTXFEM : 6; + uint32_t RESERVED6 :26; +} stc_usbfs_diepempmsk_field_t; + +typedef struct +{ + __I uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __I uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __I uint32_t NAKSTS : 1; + __I uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __O uint32_t CNAK : 1; + __O uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __I uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __I uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint0_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 2; + uint32_t RESERVED21 :11; +} stc_usbfs_dieptsiz0_field_t; + +typedef struct +{ + __I uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __I uint32_t USBAEP : 1; + __I uint32_t EONUM_DPID : 1; + __I uint32_t NAKSTS : 1; + __I uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __O uint32_t CNAK : 1; + __O uint32_t SNAK : 1; + __O uint32_t SD0PID_SEVNFRM : 1; + __O uint32_t SODDFRM : 1; + __I uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __I uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_dieptsiz_field_t; + +typedef struct +{ + __I uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts_field_t; + +typedef struct +{ + __I uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __I uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __I uint32_t NAKSTS : 1; + __I uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __O uint32_t CNAK : 1; + __O uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __I uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUP : 1; + __IO uint32_t OTEPDIS : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t B2BSTUP : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_doepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 1; + uint32_t RESERVED20 : 9; + __IO uint32_t STUPCNT : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_doeptsiz0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __I uint32_t USBAEP : 1; + __I uint32_t DPID : 1; + __I uint32_t NAKSTS : 1; + __I uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __O uint32_t CNAK : 1; + __O uint32_t SNAK : 1; + __IO uint32_t SD0PID : 1; + __IO uint32_t SD1PID : 1; + __I uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_doeptsiz_field_t; + +typedef struct +{ + __IO uint32_t STPPCLK : 1; + __IO uint32_t GATEHCLK : 1; + uint32_t RESERVED2 :30; +} stc_usbfs_pcgcctl_field_t; + +typedef struct +{ + __IO uint32_t PERI : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t CKS : 4; + __IO uint32_t WDPT : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SLPOFF : 1; + uint32_t RESERVED17 :14; + __IO uint32_t ITS : 1; +} stc_wdt_cr_field_t; + +typedef struct +{ + __I uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_wdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_wdt_rr_field_t; + +typedef struct +{ + __IO uint16_t WKTMCMP :12; + __IO uint16_t WKOVF : 1; + __IO uint16_t WKCKS : 2; + __IO uint16_t WKTCE : 1; +} stc_wktm_cr_field_t; + + +/** + * @brief ADC + */ +typedef struct +{ + union + { + __IO uint8_t STR; + stc_adc_str_field_t STR_f; + }; + uint8_t RESERVED0[1]; + union + { + __IO uint16_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint16_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint16_t TRGSR; + stc_adc_trgsr_field_t TRGSR_f; + }; + __IO uint16_t CHSELRA0; + union + { + __IO uint16_t CHSELRA1; + stc_adc_chselra1_field_t CHSELRA1_f; + }; + __IO uint16_t CHSELRB0; + union + { + __IO uint16_t CHSELRB1; + stc_adc_chselrb1_field_t CHSELRB1_f; + }; + __IO uint16_t AVCHSELR0; + union + { + __IO uint16_t AVCHSELR1; + stc_adc_avchselr1_field_t AVCHSELR1_f; + }; + uint8_t RESERVED2[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED3[7]; + union + { + __IO uint16_t CHMUXR0; + stc_adc_chmuxr0_field_t CHMUXR0_f; + }; + union + { + __IO uint16_t CHMUXR1; + stc_adc_chmuxr1_field_t CHMUXR1_f; + }; + union + { + __IO uint16_t CHMUXR2; + stc_adc_chmuxr2_field_t CHMUXR2_f; + }; + union + { + __IO uint16_t CHMUXR3; + stc_adc_chmuxr3_field_t CHMUXR3_f; + }; + uint8_t RESERVED4[6]; + union + { + __IO uint8_t ISR; + stc_adc_isr_field_t ISR_f; + }; + union + { + __IO uint8_t ICR; + stc_adc_icr_field_t ICR_f; + }; + uint8_t RESERVED5[4]; + union + { + __IO uint16_t SYNCCR; + stc_adc_synccr_field_t SYNCCR_f; + }; + uint8_t RESERVED6[2]; + __IO uint16_t DR0; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t DR3; + __IO uint16_t DR4; + __IO uint16_t DR5; + __IO uint16_t DR6; + __IO uint16_t DR7; + __IO uint16_t DR8; + __IO uint16_t DR9; + __IO uint16_t DR10; + __IO uint16_t DR11; + __IO uint16_t DR12; + __IO uint16_t DR13; + __IO uint16_t DR14; + __IO uint16_t DR15; + __IO uint16_t DR16; + uint8_t RESERVED7[46]; + union + { + __IO uint16_t AWDCR; + stc_adc_awdcr_field_t AWDCR_f; + }; + uint8_t RESERVED8[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED9[4]; + __IO uint16_t AWDCHSR0; + union + { + __IO uint16_t AWDCHSR1; + stc_adc_awdchsr1_field_t AWDCHSR1_f; + }; + __IO uint16_t AWDSR0; + union + { + __IO uint16_t AWDSR1; + stc_adc_awdsr1_field_t AWDSR1_f; + }; + uint8_t RESERVED10[12]; + union + { + __IO uint16_t PGACR; + stc_adc_pgacr_field_t PGACR_f; + }; + union + { + __IO uint16_t PGAGSR; + stc_adc_pgagsr_field_t PGAGSR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint16_t PGAINSR0; + stc_adc_pgainsr0_field_t PGAINSR0_f; + }; + union + { + __IO uint16_t PGAINSR1; + stc_adc_pgainsr1_field_t PGAINSR1_f; + }; +} M4_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +} M4_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct +{ + union + { + __IO uint32_t INT_SFTTRG; + stc_aos_int_sfttrg_field_t INT_SFTTRG_f; + }; + union + { + __IO uint32_t DCU1_TRGSEL; + stc_aos_dcu1_trgsel_field_t DCU1_TRGSEL_f; + }; + union + { + __IO uint32_t DCU2_TRGSEL; + stc_aos_dcu2_trgsel_field_t DCU2_TRGSEL_f; + }; + union + { + __IO uint32_t DCU3_TRGSEL; + stc_aos_dcu3_trgsel_field_t DCU3_TRGSEL_f; + }; + union + { + __IO uint32_t DCU4_TRGSEL; + stc_aos_dcu4_trgsel_field_t DCU4_TRGSEL_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL0; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL1; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL2; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL3; + stc_aos_dma1_trgsel3_field_t DMA1_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL0; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL1; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL2; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL3; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA_TRGSELRC; + stc_aos_dma_trgselrc_field_t DMA_TRGSELRC_f; + }; + union + { + __IO uint32_t TMR6_HTSSR0; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR0_f; + }; + union + { + __IO uint32_t TMR6_HTSSR1; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR1_f; + }; + union + { + __IO uint32_t TMR0_HTSSR; + stc_aos_tmr0_htssr_field_t TMR0_HTSSR_f; + }; + union + { + __IO uint32_t PEVNTTRGSR12; + stc_aos_pevnttrgsr12_field_t PEVNTTRGSR12_f; + }; + union + { + __IO uint32_t PEVNTTRGSR34; + stc_aos_pevnttrgsr34_field_t PEVNTTRGSR34_f; + }; + union + { + __IO uint32_t TMRA_HTSSR0; + stc_aos_tmra_htssr_field_t TMRA_HTSSR0_f; + }; + union + { + __IO uint32_t TMRA_HTSSR1; + stc_aos_tmra_htssr_field_t TMRA_HTSSR1_f; + }; + union + { + __IO uint32_t OTS_TRG; + stc_aos_ots_trg_field_t OTS_TRG_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR0; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR1; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR1_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR0; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR1; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR1_f; + }; + union + { + __IO uint32_t COMTRG1; + stc_aos_comtrg1_field_t COMTRG1_f; + }; + union + { + __IO uint32_t COMTRG2; + stc_aos_comtrg2_field_t COMTRG2_f; + }; + uint8_t RESERVED0[144]; + union + { + __IO uint32_t PEVNTDIRR1; + stc_aos_pevntdirr_field_t PEVNTDIRR1_f; + }; + union + { + __IO uint32_t PEVNTIDR1; + stc_aos_pevntidr_field_t PEVNTIDR1_f; + }; + union + { + __IO uint32_t PEVNTODR1; + stc_aos_pevntodr_field_t PEVNTODR1_f; + }; + union + { + __IO uint32_t PEVNTORR1; + stc_aos_pevntorr_field_t PEVNTORR1_f; + }; + union + { + __IO uint32_t PEVNTOSR1; + stc_aos_pevntosr_field_t PEVNTOSR1_f; + }; + union + { + __IO uint32_t PEVNTRISR1; + stc_aos_pevntrisr_field_t PEVNTRISR1_f; + }; + union + { + __IO uint32_t PEVNTFAL1; + stc_aos_pevntfal_field_t PEVNTFAL1_f; + }; + union + { + __IO uint32_t PEVNTDIRR2; + stc_aos_pevntdirr_field_t PEVNTDIRR2_f; + }; + union + { + __IO uint32_t PEVNTIDR2; + stc_aos_pevntidr_field_t PEVNTIDR2_f; + }; + union + { + __IO uint32_t PEVNTODR2; + stc_aos_pevntodr_field_t PEVNTODR2_f; + }; + union + { + __IO uint32_t PEVNTORR2; + stc_aos_pevntorr_field_t PEVNTORR2_f; + }; + union + { + __IO uint32_t PEVNTOSR2; + stc_aos_pevntosr_field_t PEVNTOSR2_f; + }; + union + { + __IO uint32_t PEVNTRISR2; + stc_aos_pevntrisr_field_t PEVNTRISR2_f; + }; + union + { + __IO uint32_t PEVNTFAL2; + stc_aos_pevntfal_field_t PEVNTFAL2_f; + }; + union + { + __IO uint32_t PEVNTDIRR3; + stc_aos_pevntdirr_field_t PEVNTDIRR3_f; + }; + union + { + __IO uint32_t PEVNTIDR3; + stc_aos_pevntidr_field_t PEVNTIDR3_f; + }; + union + { + __IO uint32_t PEVNTODR3; + stc_aos_pevntodr_field_t PEVNTODR3_f; + }; + union + { + __IO uint32_t PEVNTORR3; + stc_aos_pevntorr_field_t PEVNTORR3_f; + }; + union + { + __IO uint32_t PEVNTOSR3; + stc_aos_pevntosr_field_t PEVNTOSR3_f; + }; + union + { + __IO uint32_t PEVNTRISR3; + stc_aos_pevntrisr_field_t PEVNTRISR3_f; + }; + union + { + __IO uint32_t PEVNTFAL3; + stc_aos_pevntfal_field_t PEVNTFAL3_f; + }; + union + { + __IO uint32_t PEVNTDIRR4; + stc_aos_pevntdirr_field_t PEVNTDIRR4_f; + }; + union + { + __IO uint32_t PEVNTIDR4; + stc_aos_pevntidr_field_t PEVNTIDR4_f; + }; + union + { + __IO uint32_t PEVNTODR4; + stc_aos_pevntodr_field_t PEVNTODR4_f; + }; + union + { + __IO uint32_t PEVNTORR4; + stc_aos_pevntorr_field_t PEVNTORR4_f; + }; + union + { + __IO uint32_t PEVNTOSR4; + stc_aos_pevntosr_field_t PEVNTOSR4_f; + }; + union + { + __IO uint32_t PEVNTRISR4; + stc_aos_pevntrisr_field_t PEVNTRISR4_f; + }; + union + { + __IO uint32_t PEVNTFAL4; + stc_aos_pevntfal_field_t PEVNTFAL4_f; + }; + union + { + __IO uint32_t PEVNTNFCR; + stc_aos_pevntnfcr_field_t PEVNTNFCR_f; + }; +} M4_AOS_TypeDef; + +/** + * @brief CAN + */ +typedef struct +{ + __IO uint32_t RBUF; + uint8_t RESERVED0[76]; + __IO uint32_t TBUF; + uint8_t RESERVED1[76]; + union + { + __IO uint8_t CFG_STAT; + stc_can_cfg_stat_field_t CFG_STAT_f; + }; + union + { + __IO uint8_t TCMD; + stc_can_tcmd_field_t TCMD_f; + }; + union + { + __IO uint8_t TCTRL; + stc_can_tctrl_field_t TCTRL_f; + }; + union + { + __IO uint8_t RCTRL; + stc_can_rctrl_field_t RCTRL_f; + }; + union + { + __IO uint8_t RTIE; + stc_can_rtie_field_t RTIE_f; + }; + union + { + __IO uint8_t RTIF; + stc_can_rtif_field_t RTIF_f; + }; + union + { + __IO uint8_t ERRINT; + stc_can_errint_field_t ERRINT_f; + }; + union + { + __IO uint8_t LIMIT; + stc_can_limit_field_t LIMIT_f; + }; + union + { + __IO uint32_t BT; + stc_can_bt_field_t BT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint8_t EALCAP; + stc_can_ealcap_field_t EALCAP_f; + }; + uint8_t RESERVED3[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + union + { + __IO uint8_t ACFCTRL; + stc_can_acfctrl_field_t ACFCTRL_f; + }; + uint8_t RESERVED4[1]; + union + { + __IO uint8_t ACFEN; + stc_can_acfen_field_t ACFEN_f; + }; + uint8_t RESERVED5[1]; + union + { + __IO uint32_t ACF; + stc_can_acf_field_t ACF_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint8_t TBSLOT; + stc_can_tbslot_field_t TBSLOT_f; + }; + union + { + __IO uint8_t TTCFG; + stc_can_ttcfg_field_t TTCFG_f; + }; + union + { + __IO uint32_t REF_MSG; + stc_can_ref_msg_field_t REF_MSG_f; + }; + union + { + __IO uint16_t TRG_CFG; + stc_can_trg_cfg_field_t TRG_CFG_f; + }; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +} M4_CAN_TypeDef; + +/** + * @brief CMP + */ +typedef struct +{ + union + { + __IO uint16_t CTRL; + stc_cmp_ctrl_field_t CTRL_f; + }; + union + { + __IO uint16_t VLTSEL; + stc_cmp_vltsel_field_t VLTSEL_f; + }; + union + { + __IO uint16_t OUTMON; + stc_cmp_outmon_field_t OUTMON_f; + }; + union + { + __IO uint16_t CVSSTB; + stc_cmp_cvsstb_field_t CVSSTB_f; + }; + union + { + __IO uint16_t CVSPRD; + stc_cmp_cvsprd_field_t CVSPRD_f; + }; +} M4_CMP_TypeDef; + +/** + * @brief CMP_CR + */ +typedef struct +{ + uint8_t RESERVED0[256]; + union + { + __IO uint16_t DADR1; + stc_cmp_cr_dadr1_field_t DADR1_f; + }; + union + { + __IO uint16_t DADR2; + stc_cmp_cr_dadr2_field_t DADR2_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint16_t DACR; + stc_cmp_cr_dacr_field_t DACR_f; + }; + uint8_t RESERVED2[2]; + union + { + __IO uint16_t RVADC; + stc_cmp_cr_rvadc_field_t RVADC_f; + }; +} M4_CMP_CR_TypeDef; + +/** + * @brief CRC + */ +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + union + { + __IO uint32_t RESLT; + stc_crc_reslt_field_t RESLT_f; + }; + uint8_t RESERVED0[4]; + union + { + __IO uint32_t FLG; + stc_crc_flg_field_t FLG_f; + }; + uint8_t RESERVED1[112]; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; +} M4_CRC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct +{ + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __IO uint32_t RESV0; + union + { + __IO uint32_t MCUSTAT; + stc_dbgc_mcustat_field_t MCUSTAT_f; + }; + union + { + __IO uint32_t MCUCTL; + stc_dbgc_mcuctl_field_t MCUCTL_f; + }; + union + { + __IO uint32_t FMCCTL; + stc_dbgc_fmcctl_field_t FMCCTL_f; + }; + union + { + __IO uint32_t MCUDBGSTAT; + stc_dbgc_mcudbgstat_field_t MCUDBGSTAT_f; + }; + union + { + __IO uint32_t MCUSTPCTL; + stc_dbgc_mcustpctl_field_t MCUSTPCTL_f; + }; + union + { + __IO uint32_t MCUTRACECTL; + stc_dbgc_mcutracectl_field_t MCUTRACECTL_f; + }; +} M4_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_dcu_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t FLAG; + stc_dcu_flag_field_t FLAG_f; + }; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + union + { + __IO uint32_t FLAGCLR; + stc_dcu_flagclr_field_t FLAGCLR_f; + }; + union + { + __IO uint32_t INTSEL; + stc_dcu_intsel_field_t INTSEL_f; + }; +} M4_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct +{ + union + { + __IO uint32_t EN; + stc_dma_en_field_t EN_f; + }; + union + { + __IO uint32_t INTSTAT0; + stc_dma_intstat0_field_t INTSTAT0_f; + }; + union + { + __IO uint32_t INTSTAT1; + stc_dma_intstat1_field_t INTSTAT1_f; + }; + union + { + __IO uint32_t INTMASK0; + stc_dma_intmask0_field_t INTMASK0_f; + }; + union + { + __IO uint32_t INTMASK1; + stc_dma_intmask1_field_t INTMASK1_f; + }; + union + { + __IO uint32_t INTCLR0; + stc_dma_intclr0_field_t INTCLR0_f; + }; + union + { + __IO uint32_t INTCLR1; + stc_dma_intclr1_field_t INTCLR1_f; + }; + union + { + __IO uint32_t CHEN; + stc_dma_chen_field_t CHEN_f; + }; + union + { + __IO uint32_t REQSTAT; + stc_dma_reqstat_field_t REQSTAT_f; + }; + union + { + __IO uint32_t CHSTAT; + stc_dma_chstat_field_t CHSTAT_f; + }; + uint8_t RESERVED0[4]; + union + { + __IO uint32_t RCFGCTL; + stc_dma_rcfgctl_field_t RCFGCTL_f; + }; + uint8_t RESERVED1[16]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + union + { + __IO uint32_t DTCTL0; + stc_dma_dtctl_field_t DTCTL0_f; + }; + union + { + __IO uint32_t RPT0; + stc_dma_rpt_field_t RPT0_f; + __IO uint32_t RPTB0; + stc_dma_rptb_field_t RPTB0_f; + }; + union + { + __IO uint32_t SNSEQCTL0; + stc_dma_snseqctl_field_t SNSEQCTL0_f; + __IO uint32_t SNSEQCTLB0; + stc_dma_snseqctlb_field_t SNSEQCTLB0_f; + }; + union + { + __IO uint32_t DNSEQCTL0; + stc_dma_dnseqctl_field_t DNSEQCTL0_f; + __IO uint32_t DNSEQCTLB0; + stc_dma_dnseqctlb_field_t DNSEQCTLB0_f; + }; + union + { + __IO uint32_t LLP0; + stc_dma_llp_field_t LLP0_f; + }; + union + { + __IO uint32_t CHCTL0; + stc_dma_chctl_field_t CHCTL0_f; + }; + __IO uint32_t MONSAR0; + __IO uint32_t MONDAR0; + union + { + __IO uint32_t MONDTCTL0; + stc_dma_mondtctl_field_t MONDTCTL0_f; + }; + union + { + __IO uint32_t MONRPT0; + stc_dma_monrpt_field_t MONRPT0_f; + }; + union + { + __IO uint32_t MONSNSEQCTL0; + stc_dma_monsnseqctl_field_t MONSNSEQCTL0_f; + }; + union + { + __IO uint32_t MONDNSEQCTL0; + stc_dma_mondnseqctl_field_t MONDNSEQCTL0_f; + }; + uint8_t RESERVED2[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + union + { + __IO uint32_t DTCTL1; + stc_dma_dtctl_field_t DTCTL1_f; + }; + union + { + __IO uint32_t RPT1; + stc_dma_rpt_field_t RPT1_f; + __IO uint32_t RPTB1; + stc_dma_rptb_field_t RPTB1_f; + }; + union + { + __IO uint32_t SNSEQCTL1; + stc_dma_snseqctl_field_t SNSEQCTL1_f; + __IO uint32_t SNSEQCTLB1; + stc_dma_snseqctlb_field_t SNSEQCTLB1_f; + }; + union + { + __IO uint32_t DNSEQCTL1; + stc_dma_dnseqctl_field_t DNSEQCTL1_f; + __IO uint32_t DNSEQCTLB1; + stc_dma_dnseqctlb_field_t DNSEQCTLB1_f; + }; + union + { + __IO uint32_t LLP1; + stc_dma_llp_field_t LLP1_f; + }; + union + { + __IO uint32_t CHCTL1; + stc_dma_chctl_field_t CHCTL1_f; + }; + __IO uint32_t MONSAR1; + __IO uint32_t MONDAR1; + union + { + __IO uint32_t MONDTCTL1; + stc_dma_mondtctl_field_t MONDTCTL1_f; + }; + union + { + __IO uint32_t MONRPT1; + stc_dma_monrpt_field_t MONRPT1_f; + }; + union + { + __IO uint32_t MONSNSEQCTL1; + stc_dma_monsnseqctl_field_t MONSNSEQCTL1_f; + }; + union + { + __IO uint32_t MONDNSEQCTL1; + stc_dma_mondnseqctl_field_t MONDNSEQCTL1_f; + }; + uint8_t RESERVED3[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + union + { + __IO uint32_t DTCTL2; + stc_dma_dtctl_field_t DTCTL2_f; + }; + union + { + __IO uint32_t RPT2; + stc_dma_rpt_field_t RPT2_f; + __IO uint32_t RPTB2; + stc_dma_rptb_field_t RPTB2_f; + }; + union + { + __IO uint32_t SNSEQCTL2; + stc_dma_snseqctl_field_t SNSEQCTL2_f; + __IO uint32_t SNSEQCTLB2; + stc_dma_snseqctlb_field_t SNSEQCTLB2_f; + }; + union + { + __IO uint32_t DNSEQCTL2; + stc_dma_dnseqctl_field_t DNSEQCTL2_f; + __IO uint32_t DNSEQCTLB2; + stc_dma_dnseqctlb_field_t DNSEQCTLB2_f; + }; + union + { + __IO uint32_t LLP2; + stc_dma_llp_field_t LLP2_f; + }; + union + { + __IO uint32_t CHCTL2; + stc_dma_chctl_field_t CHCTL2_f; + }; + __IO uint32_t MONSAR2; + __IO uint32_t MONDAR2; + union + { + __IO uint32_t MONDTCTL2; + stc_dma_mondtctl_field_t MONDTCTL2_f; + }; + union + { + __IO uint32_t MONRPT2; + stc_dma_monrpt_field_t MONRPT2_f; + }; + union + { + __IO uint32_t MONSNSEQCTL2; + stc_dma_monsnseqctl_field_t MONSNSEQCTL2_f; + }; + union + { + __IO uint32_t MONDNSEQCTL2; + stc_dma_mondnseqctl_field_t MONDNSEQCTL2_f; + }; + uint8_t RESERVED4[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + union + { + __IO uint32_t DTCTL3; + stc_dma_dtctl_field_t DTCTL3_f; + }; + union + { + __IO uint32_t RPT3; + stc_dma_rpt_field_t RPT3_f; + __IO uint32_t RPTB3; + stc_dma_rptb_field_t RPTB3_f; + }; + union + { + __IO uint32_t SNSEQCTL3; + stc_dma_snseqctl_field_t SNSEQCTL3_f; + __IO uint32_t SNSEQCTLB3; + stc_dma_snseqctlb_field_t SNSEQCTLB3_f; + }; + union + { + __IO uint32_t DNSEQCTL3; + stc_dma_dnseqctl_field_t DNSEQCTL3_f; + __IO uint32_t DNSEQCTLB3; + stc_dma_dnseqctlb_field_t DNSEQCTLB3_f; + }; + union + { + __IO uint32_t LLP3; + stc_dma_llp_field_t LLP3_f; + }; + union + { + __IO uint32_t CHCTL3; + stc_dma_chctl_field_t CHCTL3_f; + }; + __IO uint32_t MONSAR3; + __IO uint32_t MONDAR3; + union + { + __IO uint32_t MONDTCTL3; + stc_dma_mondtctl_field_t MONDTCTL3_f; + }; + union + { + __IO uint32_t MONRPT3; + stc_dma_monrpt_field_t MONRPT3_f; + }; + union + { + __IO uint32_t MONSNSEQCTL3; + stc_dma_monsnseqctl_field_t MONSNSEQCTL3_f; + }; + union + { + __IO uint32_t MONDNSEQCTL3; + stc_dma_mondnseqctl_field_t MONDNSEQCTL3_f; + }; +} M4_DMA_TypeDef; + +/** + * @brief EFM + */ +typedef struct +{ + union + { + __IO uint32_t FAPRT; + stc_efm_faprt_field_t FAPRT_f; + }; + union + { + __IO uint32_t FSTP; + stc_efm_fstp_field_t FSTP_f; + }; + union + { + __IO uint32_t FRMC; + stc_efm_frmc_field_t FRMC_f; + }; + union + { + __IO uint32_t FWMC; + stc_efm_fwmc_field_t FWMC_f; + }; + union + { + __IO uint32_t FSR; + stc_efm_fsr_field_t FSR_f; + }; + union + { + __IO uint32_t FSCLR; + stc_efm_fsclr_field_t FSCLR_f; + }; + union + { + __IO uint32_t FITE; + stc_efm_fite_field_t FITE_f; + }; + union + { + __IO uint32_t FSWP; + stc_efm_fswp_field_t FSWP_f; + }; + union + { + __IO uint32_t FPMTSW; + stc_efm_fpmtsw_field_t FPMTSW_f; + }; + union + { + __IO uint32_t FPMTEW; + stc_efm_fpmtew_field_t FPMTEW_f; + }; + uint8_t RESERVED0[40]; + __IO uint32_t UQID1; + __IO uint32_t UQID2; + __IO uint32_t UQID3; + uint8_t RESERVED1[164]; + union + { + __IO uint32_t MMF_REMPRT; + stc_efm_mmf_remprt_field_t MMF_REMPRT_f; + }; + union + { + __IO uint32_t MMF_REMCR0; + stc_efm_mmf_remcr0_field_t MMF_REMCR0_f; + }; + union + { + __IO uint32_t MMF_REMCR1; + stc_efm_mmf_remcr1_field_t MMF_REMCR1_f; + }; + uint8_t RESERVED2[248]; + union + { + __IO uint32_t FRANDS; + stc_efm_frands_field_t FRANDS_f; + }; +} M4_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_emb_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t PWMLV; + stc_emb_pwmlv_field_t PWMLV_f; + }; + union + { + __IO uint32_t SOE; + stc_emb_soe_field_t SOE_f; + }; + union + { + __IO uint32_t STAT; + stc_emb_stat_field_t STAT_f; + }; + union + { + __IO uint32_t STATCLR; + stc_emb_statclr_field_t STATCLR_f; + }; + union + { + __IO uint32_t INTEN; + stc_emb_inten_field_t INTEN_f; + }; +} M4_EMB_TypeDef; + +/** + * @brief FCM + */ +typedef struct +{ + union + { + __IO uint32_t LVR; + stc_fcm_lvr_field_t LVR_f; + }; + union + { + __IO uint32_t UVR; + stc_fcm_uvr_field_t UVR_f; + }; + union + { + __IO uint32_t CNTR; + stc_fcm_cntr_field_t CNTR_f; + }; + union + { + __IO uint32_t STR; + stc_fcm_str_field_t STR_f; + }; + union + { + __IO uint32_t MCCR; + stc_fcm_mccr_field_t MCCR_f; + }; + union + { + __IO uint32_t RCCR; + stc_fcm_rccr_field_t RCCR_f; + }; + union + { + __IO uint32_t RIER; + stc_fcm_rier_field_t RIER_f; + }; + union + { + __IO uint32_t SR; + stc_fcm_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_fcm_clr_field_t CLR_f; + }; +} M4_FCM_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + union + { + __IO uint32_t CR; + stc_hash_cr_field_t CR_f; + }; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} M4_HASH_TypeDef; + +/** + * @brief I2C + */ +typedef struct +{ + union + { + __IO uint32_t CR1; + stc_i2c_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_i2c_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_i2c_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t CR4; + stc_i2c_cr4_field_t CR4_f; + }; + union + { + __IO uint32_t SLR0; + stc_i2c_slr0_field_t SLR0_f; + }; + union + { + __IO uint32_t SLR1; + stc_i2c_slr1_field_t SLR1_f; + }; + union + { + __IO uint32_t SLTR; + stc_i2c_sltr_field_t SLTR_f; + }; + union + { + __IO uint32_t SR; + stc_i2c_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_i2c_clr_field_t CLR_f; + }; + union + { + __IO uint8_t DTR; + stc_i2c_dtr_field_t DTR_f; + }; + uint8_t RESERVED0[3]; + union + { + __IO uint8_t DRR; + stc_i2c_drr_field_t DRR_f; + }; + uint8_t RESERVED1[3]; + union + { + __IO uint32_t CCR; + stc_i2c_ccr_field_t CCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_i2c_fltr_field_t FLTR_f; + }; +} M4_I2C_TypeDef; + +/** + * @brief I2S + */ +typedef struct +{ + union + { + __IO uint32_t CTRL; + stc_i2s_ctrl_field_t CTRL_f; + }; + union + { + __IO uint32_t SR; + stc_i2s_sr_field_t SR_f; + }; + union + { + __IO uint32_t ER; + stc_i2s_er_field_t ER_f; + }; + union + { + __IO uint32_t CFGR; + stc_i2s_cfgr_field_t CFGR_f; + }; + __IO uint32_t TXBUF; + __IO uint32_t RXBUF; + union + { + __IO uint32_t PR; + stc_i2s_pr_field_t PR_f; + }; +} M4_I2S_TypeDef; + +/** + * @brief ICG + */ +typedef struct +{ + union + { + __IO uint32_t ICG0; + stc_icg_icg0_field_t ICG0_f; + }; + union + { + __IO uint32_t ICG1; + stc_icg_icg1_field_t ICG1_f; + }; + __IO uint32_t ICG2; + __IO uint32_t ICG3; + __IO uint32_t ICG4; + __IO uint32_t ICG5; + __IO uint32_t ICG6; + __IO uint32_t ICG7; +} M4_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct +{ + union + { + __IO uint32_t NMICR; + stc_intc_nmicr_field_t NMICR_f; + }; + union + { + __IO uint32_t NMIENR; + stc_intc_nmienr_field_t NMIENR_f; + }; + union + { + __IO uint32_t NMIFR; + stc_intc_nmifr_field_t NMIFR_f; + }; + union + { + __IO uint32_t NMICFR; + stc_intc_nmicfr_field_t NMICFR_f; + }; + union + { + __IO uint32_t EIRQCR0; + stc_intc_eirqcr_field_t EIRQCR0_f; + }; + union + { + __IO uint32_t EIRQCR1; + stc_intc_eirqcr_field_t EIRQCR1_f; + }; + union + { + __IO uint32_t EIRQCR2; + stc_intc_eirqcr_field_t EIRQCR2_f; + }; + union + { + __IO uint32_t EIRQCR3; + stc_intc_eirqcr_field_t EIRQCR3_f; + }; + union + { + __IO uint32_t EIRQCR4; + stc_intc_eirqcr_field_t EIRQCR4_f; + }; + union + { + __IO uint32_t EIRQCR5; + stc_intc_eirqcr_field_t EIRQCR5_f; + }; + union + { + __IO uint32_t EIRQCR6; + stc_intc_eirqcr_field_t EIRQCR6_f; + }; + union + { + __IO uint32_t EIRQCR7; + stc_intc_eirqcr_field_t EIRQCR7_f; + }; + union + { + __IO uint32_t EIRQCR8; + stc_intc_eirqcr_field_t EIRQCR8_f; + }; + union + { + __IO uint32_t EIRQCR9; + stc_intc_eirqcr_field_t EIRQCR9_f; + }; + union + { + __IO uint32_t EIRQCR10; + stc_intc_eirqcr_field_t EIRQCR10_f; + }; + union + { + __IO uint32_t EIRQCR11; + stc_intc_eirqcr_field_t EIRQCR11_f; + }; + union + { + __IO uint32_t EIRQCR12; + stc_intc_eirqcr_field_t EIRQCR12_f; + }; + union + { + __IO uint32_t EIRQCR13; + stc_intc_eirqcr_field_t EIRQCR13_f; + }; + union + { + __IO uint32_t EIRQCR14; + stc_intc_eirqcr_field_t EIRQCR14_f; + }; + union + { + __IO uint32_t EIRQCR15; + stc_intc_eirqcr_field_t EIRQCR15_f; + }; + union + { + __IO uint32_t WUPEN; + stc_intc_wupen_field_t WUPEN_f; + }; + union + { + __IO uint32_t EIFR; + stc_intc_eifr_field_t EIFR_f; + }; + union + { + __IO uint32_t EICFR; + stc_intc_eicfr_field_t EICFR_f; + }; + union + { + __IO uint32_t SEL0; + stc_intc_sel_field_t SEL0_f; + }; + union + { + __IO uint32_t SEL1; + stc_intc_sel_field_t SEL1_f; + }; + union + { + __IO uint32_t SEL2; + stc_intc_sel_field_t SEL2_f; + }; + union + { + __IO uint32_t SEL3; + stc_intc_sel_field_t SEL3_f; + }; + union + { + __IO uint32_t SEL4; + stc_intc_sel_field_t SEL4_f; + }; + union + { + __IO uint32_t SEL5; + stc_intc_sel_field_t SEL5_f; + }; + union + { + __IO uint32_t SEL6; + stc_intc_sel_field_t SEL6_f; + }; + union + { + __IO uint32_t SEL7; + stc_intc_sel_field_t SEL7_f; + }; + union + { + __IO uint32_t SEL8; + stc_intc_sel_field_t SEL8_f; + }; + union + { + __IO uint32_t SEL9; + stc_intc_sel_field_t SEL9_f; + }; + union + { + __IO uint32_t SEL10; + stc_intc_sel_field_t SEL10_f; + }; + union + { + __IO uint32_t SEL11; + stc_intc_sel_field_t SEL11_f; + }; + union + { + __IO uint32_t SEL12; + stc_intc_sel_field_t SEL12_f; + }; + union + { + __IO uint32_t SEL13; + stc_intc_sel_field_t SEL13_f; + }; + union + { + __IO uint32_t SEL14; + stc_intc_sel_field_t SEL14_f; + }; + union + { + __IO uint32_t SEL15; + stc_intc_sel_field_t SEL15_f; + }; + union + { + __IO uint32_t SEL16; + stc_intc_sel_field_t SEL16_f; + }; + union + { + __IO uint32_t SEL17; + stc_intc_sel_field_t SEL17_f; + }; + union + { + __IO uint32_t SEL18; + stc_intc_sel_field_t SEL18_f; + }; + union + { + __IO uint32_t SEL19; + stc_intc_sel_field_t SEL19_f; + }; + union + { + __IO uint32_t SEL20; + stc_intc_sel_field_t SEL20_f; + }; + union + { + __IO uint32_t SEL21; + stc_intc_sel_field_t SEL21_f; + }; + union + { + __IO uint32_t SEL22; + stc_intc_sel_field_t SEL22_f; + }; + union + { + __IO uint32_t SEL23; + stc_intc_sel_field_t SEL23_f; + }; + union + { + __IO uint32_t SEL24; + stc_intc_sel_field_t SEL24_f; + }; + union + { + __IO uint32_t SEL25; + stc_intc_sel_field_t SEL25_f; + }; + union + { + __IO uint32_t SEL26; + stc_intc_sel_field_t SEL26_f; + }; + union + { + __IO uint32_t SEL27; + stc_intc_sel_field_t SEL27_f; + }; + union + { + __IO uint32_t SEL28; + stc_intc_sel_field_t SEL28_f; + }; + union + { + __IO uint32_t SEL29; + stc_intc_sel_field_t SEL29_f; + }; + union + { + __IO uint32_t SEL30; + stc_intc_sel_field_t SEL30_f; + }; + union + { + __IO uint32_t SEL31; + stc_intc_sel_field_t SEL31_f; + }; + union + { + __IO uint32_t SEL32; + stc_intc_sel_field_t SEL32_f; + }; + union + { + __IO uint32_t SEL33; + stc_intc_sel_field_t SEL33_f; + }; + union + { + __IO uint32_t SEL34; + stc_intc_sel_field_t SEL34_f; + }; + union + { + __IO uint32_t SEL35; + stc_intc_sel_field_t SEL35_f; + }; + union + { + __IO uint32_t SEL36; + stc_intc_sel_field_t SEL36_f; + }; + union + { + __IO uint32_t SEL37; + stc_intc_sel_field_t SEL37_f; + }; + union + { + __IO uint32_t SEL38; + stc_intc_sel_field_t SEL38_f; + }; + union + { + __IO uint32_t SEL39; + stc_intc_sel_field_t SEL39_f; + }; + union + { + __IO uint32_t SEL40; + stc_intc_sel_field_t SEL40_f; + }; + union + { + __IO uint32_t SEL41; + stc_intc_sel_field_t SEL41_f; + }; + union + { + __IO uint32_t SEL42; + stc_intc_sel_field_t SEL42_f; + }; + union + { + __IO uint32_t SEL43; + stc_intc_sel_field_t SEL43_f; + }; + union + { + __IO uint32_t SEL44; + stc_intc_sel_field_t SEL44_f; + }; + union + { + __IO uint32_t SEL45; + stc_intc_sel_field_t SEL45_f; + }; + union + { + __IO uint32_t SEL46; + stc_intc_sel_field_t SEL46_f; + }; + union + { + __IO uint32_t SEL47; + stc_intc_sel_field_t SEL47_f; + }; + union + { + __IO uint32_t SEL48; + stc_intc_sel_field_t SEL48_f; + }; + union + { + __IO uint32_t SEL49; + stc_intc_sel_field_t SEL49_f; + }; + union + { + __IO uint32_t SEL50; + stc_intc_sel_field_t SEL50_f; + }; + union + { + __IO uint32_t SEL51; + stc_intc_sel_field_t SEL51_f; + }; + union + { + __IO uint32_t SEL52; + stc_intc_sel_field_t SEL52_f; + }; + union + { + __IO uint32_t SEL53; + stc_intc_sel_field_t SEL53_f; + }; + union + { + __IO uint32_t SEL54; + stc_intc_sel_field_t SEL54_f; + }; + union + { + __IO uint32_t SEL55; + stc_intc_sel_field_t SEL55_f; + }; + union + { + __IO uint32_t SEL56; + stc_intc_sel_field_t SEL56_f; + }; + union + { + __IO uint32_t SEL57; + stc_intc_sel_field_t SEL57_f; + }; + union + { + __IO uint32_t SEL58; + stc_intc_sel_field_t SEL58_f; + }; + union + { + __IO uint32_t SEL59; + stc_intc_sel_field_t SEL59_f; + }; + union + { + __IO uint32_t SEL60; + stc_intc_sel_field_t SEL60_f; + }; + union + { + __IO uint32_t SEL61; + stc_intc_sel_field_t SEL61_f; + }; + union + { + __IO uint32_t SEL62; + stc_intc_sel_field_t SEL62_f; + }; + union + { + __IO uint32_t SEL63; + stc_intc_sel_field_t SEL63_f; + }; + union + { + __IO uint32_t SEL64; + stc_intc_sel_field_t SEL64_f; + }; + union + { + __IO uint32_t SEL65; + stc_intc_sel_field_t SEL65_f; + }; + union + { + __IO uint32_t SEL66; + stc_intc_sel_field_t SEL66_f; + }; + union + { + __IO uint32_t SEL67; + stc_intc_sel_field_t SEL67_f; + }; + union + { + __IO uint32_t SEL68; + stc_intc_sel_field_t SEL68_f; + }; + union + { + __IO uint32_t SEL69; + stc_intc_sel_field_t SEL69_f; + }; + union + { + __IO uint32_t SEL70; + stc_intc_sel_field_t SEL70_f; + }; + union + { + __IO uint32_t SEL71; + stc_intc_sel_field_t SEL71_f; + }; + union + { + __IO uint32_t SEL72; + stc_intc_sel_field_t SEL72_f; + }; + union + { + __IO uint32_t SEL73; + stc_intc_sel_field_t SEL73_f; + }; + union + { + __IO uint32_t SEL74; + stc_intc_sel_field_t SEL74_f; + }; + union + { + __IO uint32_t SEL75; + stc_intc_sel_field_t SEL75_f; + }; + union + { + __IO uint32_t SEL76; + stc_intc_sel_field_t SEL76_f; + }; + union + { + __IO uint32_t SEL77; + stc_intc_sel_field_t SEL77_f; + }; + union + { + __IO uint32_t SEL78; + stc_intc_sel_field_t SEL78_f; + }; + union + { + __IO uint32_t SEL79; + stc_intc_sel_field_t SEL79_f; + }; + union + { + __IO uint32_t SEL80; + stc_intc_sel_field_t SEL80_f; + }; + union + { + __IO uint32_t SEL81; + stc_intc_sel_field_t SEL81_f; + }; + union + { + __IO uint32_t SEL82; + stc_intc_sel_field_t SEL82_f; + }; + union + { + __IO uint32_t SEL83; + stc_intc_sel_field_t SEL83_f; + }; + union + { + __IO uint32_t SEL84; + stc_intc_sel_field_t SEL84_f; + }; + union + { + __IO uint32_t SEL85; + stc_intc_sel_field_t SEL85_f; + }; + union + { + __IO uint32_t SEL86; + stc_intc_sel_field_t SEL86_f; + }; + union + { + __IO uint32_t SEL87; + stc_intc_sel_field_t SEL87_f; + }; + union + { + __IO uint32_t SEL88; + stc_intc_sel_field_t SEL88_f; + }; + union + { + __IO uint32_t SEL89; + stc_intc_sel_field_t SEL89_f; + }; + union + { + __IO uint32_t SEL90; + stc_intc_sel_field_t SEL90_f; + }; + union + { + __IO uint32_t SEL91; + stc_intc_sel_field_t SEL91_f; + }; + union + { + __IO uint32_t SEL92; + stc_intc_sel_field_t SEL92_f; + }; + union + { + __IO uint32_t SEL93; + stc_intc_sel_field_t SEL93_f; + }; + union + { + __IO uint32_t SEL94; + stc_intc_sel_field_t SEL94_f; + }; + union + { + __IO uint32_t SEL95; + stc_intc_sel_field_t SEL95_f; + }; + union + { + __IO uint32_t SEL96; + stc_intc_sel_field_t SEL96_f; + }; + union + { + __IO uint32_t SEL97; + stc_intc_sel_field_t SEL97_f; + }; + union + { + __IO uint32_t SEL98; + stc_intc_sel_field_t SEL98_f; + }; + union + { + __IO uint32_t SEL99; + stc_intc_sel_field_t SEL99_f; + }; + union + { + __IO uint32_t SEL100; + stc_intc_sel_field_t SEL100_f; + }; + union + { + __IO uint32_t SEL101; + stc_intc_sel_field_t SEL101_f; + }; + union + { + __IO uint32_t SEL102; + stc_intc_sel_field_t SEL102_f; + }; + union + { + __IO uint32_t SEL103; + stc_intc_sel_field_t SEL103_f; + }; + union + { + __IO uint32_t SEL104; + stc_intc_sel_field_t SEL104_f; + }; + union + { + __IO uint32_t SEL105; + stc_intc_sel_field_t SEL105_f; + }; + union + { + __IO uint32_t SEL106; + stc_intc_sel_field_t SEL106_f; + }; + union + { + __IO uint32_t SEL107; + stc_intc_sel_field_t SEL107_f; + }; + union + { + __IO uint32_t SEL108; + stc_intc_sel_field_t SEL108_f; + }; + union + { + __IO uint32_t SEL109; + stc_intc_sel_field_t SEL109_f; + }; + union + { + __IO uint32_t SEL110; + stc_intc_sel_field_t SEL110_f; + }; + union + { + __IO uint32_t SEL111; + stc_intc_sel_field_t SEL111_f; + }; + union + { + __IO uint32_t SEL112; + stc_intc_sel_field_t SEL112_f; + }; + union + { + __IO uint32_t SEL113; + stc_intc_sel_field_t SEL113_f; + }; + union + { + __IO uint32_t SEL114; + stc_intc_sel_field_t SEL114_f; + }; + union + { + __IO uint32_t SEL115; + stc_intc_sel_field_t SEL115_f; + }; + union + { + __IO uint32_t SEL116; + stc_intc_sel_field_t SEL116_f; + }; + union + { + __IO uint32_t SEL117; + stc_intc_sel_field_t SEL117_f; + }; + union + { + __IO uint32_t SEL118; + stc_intc_sel_field_t SEL118_f; + }; + union + { + __IO uint32_t SEL119; + stc_intc_sel_field_t SEL119_f; + }; + union + { + __IO uint32_t SEL120; + stc_intc_sel_field_t SEL120_f; + }; + union + { + __IO uint32_t SEL121; + stc_intc_sel_field_t SEL121_f; + }; + union + { + __IO uint32_t SEL122; + stc_intc_sel_field_t SEL122_f; + }; + union + { + __IO uint32_t SEL123; + stc_intc_sel_field_t SEL123_f; + }; + union + { + __IO uint32_t SEL124; + stc_intc_sel_field_t SEL124_f; + }; + union + { + __IO uint32_t SEL125; + stc_intc_sel_field_t SEL125_f; + }; + union + { + __IO uint32_t SEL126; + stc_intc_sel_field_t SEL126_f; + }; + union + { + __IO uint32_t SEL127; + stc_intc_sel_field_t SEL127_f; + }; + union + { + __IO uint32_t VSSEL128; + stc_intc_vssel_field_t VSSEL128_f; + }; + union + { + __IO uint32_t VSSEL129; + stc_intc_vssel_field_t VSSEL129_f; + }; + union + { + __IO uint32_t VSSEL130; + stc_intc_vssel_field_t VSSEL130_f; + }; + union + { + __IO uint32_t VSSEL131; + stc_intc_vssel_field_t VSSEL131_f; + }; + union + { + __IO uint32_t VSSEL132; + stc_intc_vssel_field_t VSSEL132_f; + }; + union + { + __IO uint32_t VSSEL133; + stc_intc_vssel_field_t VSSEL133_f; + }; + union + { + __IO uint32_t VSSEL134; + stc_intc_vssel_field_t VSSEL134_f; + }; + union + { + __IO uint32_t VSSEL135; + stc_intc_vssel_field_t VSSEL135_f; + }; + union + { + __IO uint32_t VSSEL136; + stc_intc_vssel_field_t VSSEL136_f; + }; + union + { + __IO uint32_t VSSEL137; + stc_intc_vssel_field_t VSSEL137_f; + }; + union + { + __IO uint32_t VSSEL138; + stc_intc_vssel_field_t VSSEL138_f; + }; + union + { + __IO uint32_t VSSEL139; + stc_intc_vssel_field_t VSSEL139_f; + }; + union + { + __IO uint32_t VSSEL140; + stc_intc_vssel_field_t VSSEL140_f; + }; + union + { + __IO uint32_t VSSEL141; + stc_intc_vssel_field_t VSSEL141_f; + }; + union + { + __IO uint32_t VSSEL142; + stc_intc_vssel_field_t VSSEL142_f; + }; + union + { + __IO uint32_t VSSEL143; + stc_intc_vssel_field_t VSSEL143_f; + }; + union + { + __IO uint32_t SWIER; + stc_intc_swier_field_t SWIER_f; + }; + union + { + __IO uint32_t EVTER; + stc_intc_evter_field_t EVTER_f; + }; + union + { + __IO uint32_t IER; + stc_intc_ier_field_t IER_f; + }; +} M4_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct +{ + union + { + __IO uint32_t SCR; + stc_keyscan_scr_field_t SCR_f; + }; + union + { + __IO uint32_t SER; + stc_keyscan_ser_field_t SER_f; + }; + union + { + __IO uint32_t SSR; + stc_keyscan_ssr_field_t SSR_f; + }; +} M4_KEYSCAN_TypeDef; + +/** + * @brief MPU + */ +typedef struct +{ + union + { + __IO uint32_t RGD0; + stc_mpu_rgd_field_t RGD0_f; + }; + union + { + __IO uint32_t RGD1; + stc_mpu_rgd_field_t RGD1_f; + }; + union + { + __IO uint32_t RGD2; + stc_mpu_rgd_field_t RGD2_f; + }; + union + { + __IO uint32_t RGD3; + stc_mpu_rgd_field_t RGD3_f; + }; + union + { + __IO uint32_t RGD4; + stc_mpu_rgd_field_t RGD4_f; + }; + union + { + __IO uint32_t RGD5; + stc_mpu_rgd_field_t RGD5_f; + }; + union + { + __IO uint32_t RGD6; + stc_mpu_rgd_field_t RGD6_f; + }; + union + { + __IO uint32_t RGD7; + stc_mpu_rgd_field_t RGD7_f; + }; + union + { + __IO uint32_t RGD8; + stc_mpu_rgd_field_t RGD8_f; + }; + union + { + __IO uint32_t RGD9; + stc_mpu_rgd_field_t RGD9_f; + }; + union + { + __IO uint32_t RGD10; + stc_mpu_rgd_field_t RGD10_f; + }; + union + { + __IO uint32_t RGD11; + stc_mpu_rgd_field_t RGD11_f; + }; + union + { + __IO uint32_t RGD12; + stc_mpu_rgd_field_t RGD12_f; + }; + union + { + __IO uint32_t RGD13; + stc_mpu_rgd_field_t RGD13_f; + }; + union + { + __IO uint32_t RGD14; + stc_mpu_rgd_field_t RGD14_f; + }; + union + { + __IO uint32_t RGD15; + stc_mpu_rgd_field_t RGD15_f; + }; + union + { + __IO uint32_t RGCR0; + stc_mpu_rgcr0_field_t RGCR0_f; + }; + union + { + __IO uint32_t RGCR1; + stc_mpu_rgcr1_field_t RGCR1_f; + }; + union + { + __IO uint32_t RGCR2; + stc_mpu_rgcr2_field_t RGCR2_f; + }; + union + { + __IO uint32_t RGCR3; + stc_mpu_rgcr3_field_t RGCR3_f; + }; + union + { + __IO uint32_t RGCR4; + stc_mpu_rgcr4_field_t RGCR4_f; + }; + union + { + __IO uint32_t RGCR5; + stc_mpu_rgcr5_field_t RGCR5_f; + }; + union + { + __IO uint32_t RGCR6; + stc_mpu_rgcr6_field_t RGCR6_f; + }; + union + { + __IO uint32_t RGCR7; + stc_mpu_rgcr7_field_t RGCR7_f; + }; + union + { + __IO uint32_t RGCR8; + stc_mpu_rgcr8_field_t RGCR8_f; + }; + union + { + __IO uint32_t RGCR9; + stc_mpu_rgcr9_field_t RGCR9_f; + }; + union + { + __IO uint32_t RGCR10; + stc_mpu_rgcr10_field_t RGCR10_f; + }; + union + { + __IO uint32_t RGCR11; + stc_mpu_rgcr11_field_t RGCR11_f; + }; + union + { + __IO uint32_t RGCR12; + stc_mpu_rgcr12_field_t RGCR12_f; + }; + union + { + __IO uint32_t RGCR13; + stc_mpu_rgcr13_field_t RGCR13_f; + }; + union + { + __IO uint32_t RGCR14; + stc_mpu_rgcr14_field_t RGCR14_f; + }; + union + { + __IO uint32_t RGCR15; + stc_mpu_rgcr15_field_t RGCR15_f; + }; + union + { + __IO uint32_t CR; + stc_mpu_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_mpu_sr_field_t SR_f; + }; + union + { + __IO uint32_t ECLR; + stc_mpu_eclr_field_t ECLR_f; + }; + union + { + __IO uint32_t WP; + stc_mpu_wp_field_t WP_f; + }; +} M4_MPU_TypeDef; + +/** + * @brief MSTP + */ +typedef struct +{ + union + { + __IO uint32_t FCG0; + stc_mstp_fcg0_field_t FCG0_f; + }; + union + { + __IO uint32_t FCG1; + stc_mstp_fcg1_field_t FCG1_f; + }; + union + { + __IO uint32_t FCG2; + stc_mstp_fcg2_field_t FCG2_f; + }; + union + { + __IO uint32_t FCG3; + stc_mstp_fcg3_field_t FCG3_f; + }; + union + { + __IO uint32_t FCG0PC; + stc_mstp_fcg0pc_field_t FCG0PC_f; + }; +} M4_MSTP_TypeDef; + +/** + * @brief OTS + */ +typedef struct +{ + union + { + __IO uint16_t CTL; + stc_ots_ctl_field_t CTL_f; + }; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; + union + { + __IO uint32_t LPR; + stc_ots_lpr_field_t LPR_f; + }; +} M4_OTS_TypeDef; + +/** + * @brief PERIC + */ +typedef struct +{ + union + { + __IO uint32_t USBFS_SYCTLREG; + stc_peric_usbfs_syctlreg_field_t USBFS_SYCTLREG_f; + }; + union + { + __IO uint32_t SDIOC_SYCTLREG; + stc_peric_sdioc_syctlreg_field_t SDIOC_SYCTLREG_f; + }; +} M4_PERIC_TypeDef; + +/** + * @brief PORT + */ +typedef struct +{ + union + { + __IO uint16_t PIDRA; + stc_port_pidr_field_t PIDRA_f; + }; + uint8_t RESERVED0[2]; + union + { + __IO uint16_t PODRA; + stc_port_podr_field_t PODRA_f; + }; + union + { + __IO uint16_t POERA; + stc_port_poer_field_t POERA_f; + }; + union + { + __IO uint16_t POSRA; + stc_port_posr_field_t POSRA_f; + }; + union + { + __IO uint16_t PORRA; + stc_port_porr_field_t PORRA_f; + }; + union + { + __IO uint16_t POTRA; + stc_port_potr_field_t POTRA_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t PIDRB; + stc_port_pidr_field_t PIDRB_f; + }; + uint8_t RESERVED2[2]; + union + { + __IO uint16_t PODRB; + stc_port_podr_field_t PODRB_f; + }; + union + { + __IO uint16_t POERB; + stc_port_poer_field_t POERB_f; + }; + union + { + __IO uint16_t POSRB; + stc_port_posr_field_t POSRB_f; + }; + union + { + __IO uint16_t PORRB; + stc_port_porr_field_t PORRB_f; + }; + union + { + __IO uint16_t POTRB; + stc_port_potr_field_t POTRB_f; + }; + uint8_t RESERVED3[2]; + union + { + __IO uint16_t PIDRC; + stc_port_pidr_field_t PIDRC_f; + }; + uint8_t RESERVED4[2]; + union + { + __IO uint16_t PODRC; + stc_port_podr_field_t PODRC_f; + }; + union + { + __IO uint16_t POERC; + stc_port_poer_field_t POERC_f; + }; + union + { + __IO uint16_t POSRC; + stc_port_posr_field_t POSRC_f; + }; + union + { + __IO uint16_t PORRC; + stc_port_porr_field_t PORRC_f; + }; + union + { + __IO uint16_t POTRC; + stc_port_potr_field_t POTRC_f; + }; + uint8_t RESERVED5[2]; + union + { + __IO uint16_t PIDRD; + stc_port_pidr_field_t PIDRD_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint16_t PODRD; + stc_port_podr_field_t PODRD_f; + }; + union + { + __IO uint16_t POERD; + stc_port_poer_field_t POERD_f; + }; + union + { + __IO uint16_t POSRD; + stc_port_posr_field_t POSRD_f; + }; + union + { + __IO uint16_t PORRD; + stc_port_porr_field_t PORRD_f; + }; + union + { + __IO uint16_t POTRD; + stc_port_potr_field_t POTRD_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t PIDRE; + stc_port_pidr_field_t PIDRE_f; + }; + uint8_t RESERVED8[2]; + union + { + __IO uint16_t PODRE; + stc_port_podr_field_t PODRE_f; + }; + union + { + __IO uint16_t POERE; + stc_port_poer_field_t POERE_f; + }; + union + { + __IO uint16_t POSRE; + stc_port_posr_field_t POSRE_f; + }; + union + { + __IO uint16_t PORRE; + stc_port_porr_field_t PORRE_f; + }; + union + { + __IO uint16_t POTRE; + stc_port_potr_field_t POTRE_f; + }; + uint8_t RESERVED9[2]; + union + { + __IO uint16_t PIDRH; + stc_port_pidrh_field_t PIDRH_f; + }; + uint8_t RESERVED10[2]; + union + { + __IO uint16_t PODRH; + stc_port_podrh_field_t PODRH_f; + }; + union + { + __IO uint16_t POERH; + stc_port_poerh_field_t POERH_f; + }; + union + { + __IO uint16_t POSRH; + stc_port_posrh_field_t POSRH_f; + }; + union + { + __IO uint16_t PORRH; + stc_port_porrh_field_t PORRH_f; + }; + union + { + __IO uint16_t POTRH; + stc_port_potrh_field_t POTRH_f; + }; + uint8_t RESERVED11[918]; + union + { + __IO uint16_t PSPCR; + stc_port_pspcr_field_t PSPCR_f; + }; + uint8_t RESERVED12[2]; + union + { + __IO uint16_t PCCR; + stc_port_pccr_field_t PCCR_f; + }; + union + { + __IO uint16_t PINAER; + stc_port_pinaer_field_t PINAER_f; + }; + union + { + __IO uint16_t PWPR; + stc_port_pwpr_field_t PWPR_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint16_t PCRA0; + stc_port_pcr_field_t PCRA0_f; + }; + union + { + __IO uint16_t PFSRA0; + stc_port_pfsr_field_t PFSRA0_f; + }; + union + { + __IO uint16_t PCRA1; + stc_port_pcr_field_t PCRA1_f; + }; + union + { + __IO uint16_t PFSRA1; + stc_port_pfsr_field_t PFSRA1_f; + }; + union + { + __IO uint16_t PCRA2; + stc_port_pcr_field_t PCRA2_f; + }; + union + { + __IO uint16_t PFSRA2; + stc_port_pfsr_field_t PFSRA2_f; + }; + union + { + __IO uint16_t PCRA3; + stc_port_pcr_field_t PCRA3_f; + }; + union + { + __IO uint16_t PFSRA3; + stc_port_pfsr_field_t PFSRA3_f; + }; + union + { + __IO uint16_t PCRA4; + stc_port_pcr_field_t PCRA4_f; + }; + union + { + __IO uint16_t PFSRA4; + stc_port_pfsr_field_t PFSRA4_f; + }; + union + { + __IO uint16_t PCRA5; + stc_port_pcr_field_t PCRA5_f; + }; + union + { + __IO uint16_t PFSRA5; + stc_port_pfsr_field_t PFSRA5_f; + }; + union + { + __IO uint16_t PCRA6; + stc_port_pcr_field_t PCRA6_f; + }; + union + { + __IO uint16_t PFSRA6; + stc_port_pfsr_field_t PFSRA6_f; + }; + union + { + __IO uint16_t PCRA7; + stc_port_pcr_field_t PCRA7_f; + }; + union + { + __IO uint16_t PFSRA7; + stc_port_pfsr_field_t PFSRA7_f; + }; + union + { + __IO uint16_t PCRA8; + stc_port_pcr_field_t PCRA8_f; + }; + union + { + __IO uint16_t PFSRA8; + stc_port_pfsr_field_t PFSRA8_f; + }; + union + { + __IO uint16_t PCRA9; + stc_port_pcr_field_t PCRA9_f; + }; + union + { + __IO uint16_t PFSRA9; + stc_port_pfsr_field_t PFSRA9_f; + }; + union + { + __IO uint16_t PCRA10; + stc_port_pcr_field_t PCRA10_f; + }; + union + { + __IO uint16_t PFSRA10; + stc_port_pfsr_field_t PFSRA10_f; + }; + union + { + __IO uint16_t PCRA11; + stc_port_pcr_field_t PCRA11_f; + }; + union + { + __IO uint16_t PFSRA11; + stc_port_pfsr_field_t PFSRA11_f; + }; + union + { + __IO uint16_t PCRA12; + stc_port_pcr_field_t PCRA12_f; + }; + union + { + __IO uint16_t PFSRA12; + stc_port_pfsr_field_t PFSRA12_f; + }; + union + { + __IO uint16_t PCRA13; + stc_port_pcr_field_t PCRA13_f; + }; + union + { + __IO uint16_t PFSRA13; + stc_port_pfsr_field_t PFSRA13_f; + }; + union + { + __IO uint16_t PCRA14; + stc_port_pcr_field_t PCRA14_f; + }; + union + { + __IO uint16_t PFSRA14; + stc_port_pfsr_field_t PFSRA14_f; + }; + union + { + __IO uint16_t PCRA15; + stc_port_pcr_field_t PCRA15_f; + }; + union + { + __IO uint16_t PFSRA15; + stc_port_pfsr_field_t PFSRA15_f; + }; + union + { + __IO uint16_t PCRB0; + stc_port_pcr_field_t PCRB0_f; + }; + union + { + __IO uint16_t PFSRB0; + stc_port_pfsr_field_t PFSRB0_f; + }; + union + { + __IO uint16_t PCRB1; + stc_port_pcr_field_t PCRB1_f; + }; + union + { + __IO uint16_t PFSRB1; + stc_port_pfsr_field_t PFSRB1_f; + }; + union + { + __IO uint16_t PCRB2; + stc_port_pcr_field_t PCRB2_f; + }; + union + { + __IO uint16_t PFSRB2; + stc_port_pfsr_field_t PFSRB2_f; + }; + union + { + __IO uint16_t PCRB3; + stc_port_pcr_field_t PCRB3_f; + }; + union + { + __IO uint16_t PFSRB3; + stc_port_pfsr_field_t PFSRB3_f; + }; + union + { + __IO uint16_t PCRB4; + stc_port_pcr_field_t PCRB4_f; + }; + union + { + __IO uint16_t PFSRB4; + stc_port_pfsr_field_t PFSRB4_f; + }; + union + { + __IO uint16_t PCRB5; + stc_port_pcr_field_t PCRB5_f; + }; + union + { + __IO uint16_t PFSRB5; + stc_port_pfsr_field_t PFSRB5_f; + }; + union + { + __IO uint16_t PCRB6; + stc_port_pcr_field_t PCRB6_f; + }; + union + { + __IO uint16_t PFSRB6; + stc_port_pfsr_field_t PFSRB6_f; + }; + union + { + __IO uint16_t PCRB7; + stc_port_pcr_field_t PCRB7_f; + }; + union + { + __IO uint16_t PFSRB7; + stc_port_pfsr_field_t PFSRB7_f; + }; + union + { + __IO uint16_t PCRB8; + stc_port_pcr_field_t PCRB8_f; + }; + union + { + __IO uint16_t PFSRB8; + stc_port_pfsr_field_t PFSRB8_f; + }; + union + { + __IO uint16_t PCRB9; + stc_port_pcr_field_t PCRB9_f; + }; + union + { + __IO uint16_t PFSRB9; + stc_port_pfsr_field_t PFSRB9_f; + }; + union + { + __IO uint16_t PCRB10; + stc_port_pcr_field_t PCRB10_f; + }; + union + { + __IO uint16_t PFSRB10; + stc_port_pfsr_field_t PFSRB10_f; + }; + union + { + __IO uint16_t PCRB11; + stc_port_pcr_field_t PCRB11_f; + }; + union + { + __IO uint16_t PFSRB11; + stc_port_pfsr_field_t PFSRB11_f; + }; + union + { + __IO uint16_t PCRB12; + stc_port_pcr_field_t PCRB12_f; + }; + union + { + __IO uint16_t PFSRB12; + stc_port_pfsr_field_t PFSRB12_f; + }; + union + { + __IO uint16_t PCRB13; + stc_port_pcr_field_t PCRB13_f; + }; + union + { + __IO uint16_t PFSRB13; + stc_port_pfsr_field_t PFSRB13_f; + }; + union + { + __IO uint16_t PCRB14; + stc_port_pcr_field_t PCRB14_f; + }; + union + { + __IO uint16_t PFSRB14; + stc_port_pfsr_field_t PFSRB14_f; + }; + union + { + __IO uint16_t PCRB15; + stc_port_pcr_field_t PCRB15_f; + }; + union + { + __IO uint16_t PFSRB15; + stc_port_pfsr_field_t PFSRB15_f; + }; + union + { + __IO uint16_t PCRC0; + stc_port_pcr_field_t PCRC0_f; + }; + union + { + __IO uint16_t PFSRC0; + stc_port_pfsr_field_t PFSRC0_f; + }; + union + { + __IO uint16_t PCRC1; + stc_port_pcr_field_t PCRC1_f; + }; + union + { + __IO uint16_t PFSRC1; + stc_port_pfsr_field_t PFSRC1_f; + }; + union + { + __IO uint16_t PCRC2; + stc_port_pcr_field_t PCRC2_f; + }; + union + { + __IO uint16_t PFSRC2; + stc_port_pfsr_field_t PFSRC2_f; + }; + union + { + __IO uint16_t PCRC3; + stc_port_pcr_field_t PCRC3_f; + }; + union + { + __IO uint16_t PFSRC3; + stc_port_pfsr_field_t PFSRC3_f; + }; + union + { + __IO uint16_t PCRC4; + stc_port_pcr_field_t PCRC4_f; + }; + union + { + __IO uint16_t PFSRC4; + stc_port_pfsr_field_t PFSRC4_f; + }; + union + { + __IO uint16_t PCRC5; + stc_port_pcr_field_t PCRC5_f; + }; + union + { + __IO uint16_t PFSRC5; + stc_port_pfsr_field_t PFSRC5_f; + }; + union + { + __IO uint16_t PCRC6; + stc_port_pcr_field_t PCRC6_f; + }; + union + { + __IO uint16_t PFSRC6; + stc_port_pfsr_field_t PFSRC6_f; + }; + union + { + __IO uint16_t PCRC7; + stc_port_pcr_field_t PCRC7_f; + }; + union + { + __IO uint16_t PFSRC7; + stc_port_pfsr_field_t PFSRC7_f; + }; + union + { + __IO uint16_t PCRC8; + stc_port_pcr_field_t PCRC8_f; + }; + union + { + __IO uint16_t PFSRC8; + stc_port_pfsr_field_t PFSRC8_f; + }; + union + { + __IO uint16_t PCRC9; + stc_port_pcr_field_t PCRC9_f; + }; + union + { + __IO uint16_t PFSRC9; + stc_port_pfsr_field_t PFSRC9_f; + }; + union + { + __IO uint16_t PCRC10; + stc_port_pcr_field_t PCRC10_f; + }; + union + { + __IO uint16_t PFSRC10; + stc_port_pfsr_field_t PFSRC10_f; + }; + union + { + __IO uint16_t PCRC11; + stc_port_pcr_field_t PCRC11_f; + }; + union + { + __IO uint16_t PFSRC11; + stc_port_pfsr_field_t PFSRC11_f; + }; + union + { + __IO uint16_t PCRC12; + stc_port_pcr_field_t PCRC12_f; + }; + union + { + __IO uint16_t PFSRC12; + stc_port_pfsr_field_t PFSRC12_f; + }; + union + { + __IO uint16_t PCRC13; + stc_port_pcr_field_t PCRC13_f; + }; + union + { + __IO uint16_t PFSRC13; + stc_port_pfsr_field_t PFSRC13_f; + }; + union + { + __IO uint16_t PCRC14; + stc_port_pcr_field_t PCRC14_f; + }; + union + { + __IO uint16_t PFSRC14; + stc_port_pfsr_field_t PFSRC14_f; + }; + union + { + __IO uint16_t PCRC15; + stc_port_pcr_field_t PCRC15_f; + }; + union + { + __IO uint16_t PFSRC15; + stc_port_pfsr_field_t PFSRC15_f; + }; + union + { + __IO uint16_t PCRD0; + stc_port_pcr_field_t PCRD0_f; + }; + union + { + __IO uint16_t PFSRD0; + stc_port_pfsr_field_t PFSRD0_f; + }; + union + { + __IO uint16_t PCRD1; + stc_port_pcr_field_t PCRD1_f; + }; + union + { + __IO uint16_t PFSRD1; + stc_port_pfsr_field_t PFSRD1_f; + }; + union + { + __IO uint16_t PCRD2; + stc_port_pcr_field_t PCRD2_f; + }; + union + { + __IO uint16_t PFSRD2; + stc_port_pfsr_field_t PFSRD2_f; + }; + union + { + __IO uint16_t PCRD3; + stc_port_pcr_field_t PCRD3_f; + }; + union + { + __IO uint16_t PFSRD3; + stc_port_pfsr_field_t PFSRD3_f; + }; + union + { + __IO uint16_t PCRD4; + stc_port_pcr_field_t PCRD4_f; + }; + union + { + __IO uint16_t PFSRD4; + stc_port_pfsr_field_t PFSRD4_f; + }; + union + { + __IO uint16_t PCRD5; + stc_port_pcr_field_t PCRD5_f; + }; + union + { + __IO uint16_t PFSRD5; + stc_port_pfsr_field_t PFSRD5_f; + }; + union + { + __IO uint16_t PCRD6; + stc_port_pcr_field_t PCRD6_f; + }; + union + { + __IO uint16_t PFSRD6; + stc_port_pfsr_field_t PFSRD6_f; + }; + union + { + __IO uint16_t PCRD7; + stc_port_pcr_field_t PCRD7_f; + }; + union + { + __IO uint16_t PFSRD7; + stc_port_pfsr_field_t PFSRD7_f; + }; + union + { + __IO uint16_t PCRD8; + stc_port_pcr_field_t PCRD8_f; + }; + union + { + __IO uint16_t PFSRD8; + stc_port_pfsr_field_t PFSRD8_f; + }; + union + { + __IO uint16_t PCRD9; + stc_port_pcr_field_t PCRD9_f; + }; + union + { + __IO uint16_t PFSRD9; + stc_port_pfsr_field_t PFSRD9_f; + }; + union + { + __IO uint16_t PCRD10; + stc_port_pcr_field_t PCRD10_f; + }; + union + { + __IO uint16_t PFSRD10; + stc_port_pfsr_field_t PFSRD10_f; + }; + union + { + __IO uint16_t PCRD11; + stc_port_pcr_field_t PCRD11_f; + }; + union + { + __IO uint16_t PFSRD11; + stc_port_pfsr_field_t PFSRD11_f; + }; + union + { + __IO uint16_t PCRD12; + stc_port_pcr_field_t PCRD12_f; + }; + union + { + __IO uint16_t PFSRD12; + stc_port_pfsr_field_t PFSRD12_f; + }; + union + { + __IO uint16_t PCRD13; + stc_port_pcr_field_t PCRD13_f; + }; + union + { + __IO uint16_t PFSRD13; + stc_port_pfsr_field_t PFSRD13_f; + }; + union + { + __IO uint16_t PCRD14; + stc_port_pcr_field_t PCRD14_f; + }; + union + { + __IO uint16_t PFSRD14; + stc_port_pfsr_field_t PFSRD14_f; + }; + union + { + __IO uint16_t PCRD15; + stc_port_pcr_field_t PCRD15_f; + }; + union + { + __IO uint16_t PFSRD15; + stc_port_pfsr_field_t PFSRD15_f; + }; + union + { + __IO uint16_t PCRE0; + stc_port_pcr_field_t PCRE0_f; + }; + union + { + __IO uint16_t PFSRE0; + stc_port_pfsr_field_t PFSRE0_f; + }; + union + { + __IO uint16_t PCRE1; + stc_port_pcr_field_t PCRE1_f; + }; + union + { + __IO uint16_t PFSRE1; + stc_port_pfsr_field_t PFSRE1_f; + }; + union + { + __IO uint16_t PCRE2; + stc_port_pcr_field_t PCRE2_f; + }; + union + { + __IO uint16_t PFSRE2; + stc_port_pfsr_field_t PFSRE2_f; + }; + union + { + __IO uint16_t PCRE3; + stc_port_pcr_field_t PCRE3_f; + }; + union + { + __IO uint16_t PFSRE3; + stc_port_pfsr_field_t PFSRE3_f; + }; + union + { + __IO uint16_t PCRE4; + stc_port_pcr_field_t PCRE4_f; + }; + union + { + __IO uint16_t PFSRE4; + stc_port_pfsr_field_t PFSRE4_f; + }; + union + { + __IO uint16_t PCRE5; + stc_port_pcr_field_t PCRE5_f; + }; + union + { + __IO uint16_t PFSRE5; + stc_port_pfsr_field_t PFSRE5_f; + }; + union + { + __IO uint16_t PCRE6; + stc_port_pcr_field_t PCRE6_f; + }; + union + { + __IO uint16_t PFSRE6; + stc_port_pfsr_field_t PFSRE6_f; + }; + union + { + __IO uint16_t PCRE7; + stc_port_pcr_field_t PCRE7_f; + }; + union + { + __IO uint16_t PFSRE7; + stc_port_pfsr_field_t PFSRE7_f; + }; + union + { + __IO uint16_t PCRE8; + stc_port_pcr_field_t PCRE8_f; + }; + union + { + __IO uint16_t PFSRE8; + stc_port_pfsr_field_t PFSRE8_f; + }; + union + { + __IO uint16_t PCRE9; + stc_port_pcr_field_t PCRE9_f; + }; + union + { + __IO uint16_t PFSRE9; + stc_port_pfsr_field_t PFSRE9_f; + }; + union + { + __IO uint16_t PCRE10; + stc_port_pcr_field_t PCRE10_f; + }; + union + { + __IO uint16_t PFSRE10; + stc_port_pfsr_field_t PFSRE10_f; + }; + union + { + __IO uint16_t PCRE11; + stc_port_pcr_field_t PCRE11_f; + }; + union + { + __IO uint16_t PFSRE11; + stc_port_pfsr_field_t PFSRE11_f; + }; + union + { + __IO uint16_t PCRE12; + stc_port_pcr_field_t PCRE12_f; + }; + union + { + __IO uint16_t PFSRE12; + stc_port_pfsr_field_t PFSRE12_f; + }; + union + { + __IO uint16_t PCRE13; + stc_port_pcr_field_t PCRE13_f; + }; + union + { + __IO uint16_t PFSRE13; + stc_port_pfsr_field_t PFSRE13_f; + }; + union + { + __IO uint16_t PCRE14; + stc_port_pcr_field_t PCRE14_f; + }; + union + { + __IO uint16_t PFSRE14; + stc_port_pfsr_field_t PFSRE14_f; + }; + union + { + __IO uint16_t PCRE15; + stc_port_pcr_field_t PCRE15_f; + }; + union + { + __IO uint16_t PFSRE15; + stc_port_pfsr_field_t PFSRE15_f; + }; + union + { + __IO uint16_t PCRH0; + stc_port_pcr_field_t PCRH0_f; + }; + union + { + __IO uint16_t PFSRH0; + stc_port_pfsr_field_t PFSRH0_f; + }; + union + { + __IO uint16_t PCRH1; + stc_port_pcr_field_t PCRH1_f; + }; + union + { + __IO uint16_t PFSRH1; + stc_port_pfsr_field_t PFSRH1_f; + }; + union + { + __IO uint16_t PCRH2; + stc_port_pcr_field_t PCRH2_f; + }; + union + { + __IO uint16_t PFSRH2; + stc_port_pfsr_field_t PFSRH2_f; + }; +} M4_PORT_TypeDef; + +/** + * @brief QSPI + */ +typedef struct +{ + union + { + __IO uint32_t CR; + stc_qspi_cr_field_t CR_f; + }; + union + { + __IO uint32_t CSCR; + stc_qspi_cscr_field_t CSCR_f; + }; + union + { + __IO uint32_t FCR; + stc_qspi_fcr_field_t FCR_f; + }; + union + { + __IO uint32_t SR; + stc_qspi_sr_field_t SR_f; + }; + union + { + __IO uint32_t DCOM; + stc_qspi_dcom_field_t DCOM_f; + }; + union + { + __IO uint32_t CCMD; + stc_qspi_ccmd_field_t CCMD_f; + }; + union + { + __IO uint32_t XCMD; + stc_qspi_xcmd_field_t XCMD_f; + }; + uint8_t RESERVED0[8]; + union + { + __IO uint32_t SR2; + stc_qspi_sr2_field_t SR2_f; + }; + uint8_t RESERVED1[2012]; + union + { + __IO uint32_t EXAR; + stc_qspi_exar_field_t EXAR_f; + }; +} M4_QSPI_TypeDef; + +/** + * @brief RTC + */ +typedef struct +{ + union + { + __IO uint8_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + uint8_t RESERVED0[3]; + union + { + __IO uint8_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + uint8_t RESERVED1[3]; + union + { + __IO uint8_t CR2; + stc_rtc_cr2_field_t CR2_f; + }; + uint8_t RESERVED2[3]; + union + { + __IO uint8_t CR3; + stc_rtc_cr3_field_t CR3_f; + }; + uint8_t RESERVED3[3]; + union + { + __IO uint8_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + uint8_t RESERVED4[3]; + union + { + __IO uint8_t MIN; + stc_rtc_min_field_t MIN_f; + }; + uint8_t RESERVED5[3]; + union + { + __IO uint8_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + uint8_t RESERVED6[3]; + union + { + __IO uint8_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + uint8_t RESERVED7[3]; + union + { + __IO uint8_t DAY; + stc_rtc_day_field_t DAY_f; + }; + uint8_t RESERVED8[3]; + union + { + __IO uint8_t MON; + stc_rtc_mon_field_t MON_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint8_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + uint8_t RESERVED11[3]; + union + { + __IO uint8_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + uint8_t RESERVED12[3]; + union + { + __IO uint8_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + uint8_t RESERVED13[3]; + union + { + __IO uint8_t ERRCRH; + stc_rtc_errcrh_field_t ERRCRH_f; + }; + uint8_t RESERVED14[3]; + union + { + __IO uint8_t ERRCRL; + stc_rtc_errcrl_field_t ERRCRL_f; + }; +} M4_RTC_TypeDef; + +/** + * @brief SDIOC + */ +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint16_t BLKSIZE; + stc_sdioc_blksize_field_t BLKSIZE_f; + }; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + union + { + __IO uint16_t TRANSMODE; + stc_sdioc_transmode_field_t TRANSMODE_f; + }; + union + { + __IO uint16_t CMD; + stc_sdioc_cmd_field_t CMD_f; + }; + __IO uint16_t RESP0; + __IO uint16_t RESP1; + __IO uint16_t RESP2; + __IO uint16_t RESP3; + __IO uint16_t RESP4; + __IO uint16_t RESP5; + __IO uint16_t RESP6; + __IO uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + union + { + __IO uint32_t PSTAT; + stc_sdioc_pstat_field_t PSTAT_f; + }; + union + { + __IO uint8_t HOSTCON; + stc_sdioc_hostcon_field_t HOSTCON_f; + }; + union + { + __IO uint8_t PWRCON; + stc_sdioc_pwrcon_field_t PWRCON_f; + }; + union + { + __IO uint8_t BLKGPCON; + stc_sdioc_blkgpcon_field_t BLKGPCON_f; + }; + uint8_t RESERVED1[1]; + union + { + __IO uint16_t CLKCON; + stc_sdioc_clkcon_field_t CLKCON_f; + }; + union + { + __IO uint8_t TOUTCON; + stc_sdioc_toutcon_field_t TOUTCON_f; + }; + union + { + __IO uint8_t SFTRST; + stc_sdioc_sftrst_field_t SFTRST_f; + }; + union + { + __IO uint16_t NORINTST; + stc_sdioc_norintst_field_t NORINTST_f; + }; + union + { + __IO uint16_t ERRINTST; + stc_sdioc_errintst_field_t ERRINTST_f; + }; + union + { + __IO uint16_t NORINTSTEN; + stc_sdioc_norintsten_field_t NORINTSTEN_f; + }; + union + { + __IO uint16_t ERRINTSTEN; + stc_sdioc_errintsten_field_t ERRINTSTEN_f; + }; + union + { + __IO uint16_t NORINTSGEN; + stc_sdioc_norintsgen_field_t NORINTSGEN_f; + }; + union + { + __IO uint16_t ERRINTSGEN; + stc_sdioc_errintsgen_field_t ERRINTSGEN_f; + }; + union + { + __IO uint16_t ATCERRST; + stc_sdioc_atcerrst_field_t ATCERRST_f; + }; + uint8_t RESERVED2[18]; + union + { + __IO uint16_t FEA; + stc_sdioc_fea_field_t FEA_f; + }; + union + { + __IO uint16_t FEE; + stc_sdioc_fee_field_t FEE_f; + }; +} M4_SDIOC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t DR; + union + { + __IO uint32_t CR1; + stc_spi_cr1_field_t CR1_f; + }; + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CFG1; + stc_spi_cfg1_field_t CFG1_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t SR; + stc_spi_sr_field_t SR_f; + }; + union + { + __IO uint32_t CFG2; + stc_spi_cfg2_field_t CFG2_f; + }; +} M4_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct +{ + union + { + __IO uint32_t WTCR; + stc_sramc_wtcr_field_t WTCR_f; + }; + union + { + __IO uint32_t WTPR; + stc_sramc_wtpr_field_t WTPR_f; + }; + union + { + __IO uint32_t CKCR; + stc_sramc_ckcr_field_t CKCR_f; + }; + union + { + __IO uint32_t CKPR; + stc_sramc_ckpr_field_t CKPR_f; + }; + union + { + __IO uint32_t CKSR; + stc_sramc_cksr_field_t CKSR_f; + }; +} M4_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t SR; + stc_swdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_swdt_rr_field_t RR_f; + }; +} M4_SWDT_TypeDef; + +/** + * @brief SYSREG + */ +typedef struct +{ + uint8_t RESERVED0[12]; + union + { + __IO uint16_t PWR_STPMCR; + stc_sysreg_pwr_stpmcr_field_t PWR_STPMCR_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t CMU_PERICKSEL; + stc_sysreg_cmu_pericksel_field_t CMU_PERICKSEL_f; + }; + union + { + __IO uint16_t CMU_I2SCKSEL; + stc_sysreg_cmu_i2scksel_field_t CMU_I2SCKSEL_f; + }; + union + { + __IO uint32_t PWR_RAMPC0; + stc_sysreg_pwr_rampc0_field_t PWR_RAMPC0_f; + }; + __IO uint16_t PWR_RAMOPM; + uint8_t RESERVED2[2]; + union + { + __IO uint32_t MPU_IPPR; + stc_sysreg_mpu_ippr_field_t MPU_IPPR_f; + }; + union + { + __IO uint32_t CMU_SCFGR; + stc_sysreg_cmu_scfgr_field_t CMU_SCFGR_f; + }; + union + { + __IO uint8_t CMU_UFSCKCFGR; + stc_sysreg_cmu_ufsckcfgr_field_t CMU_UFSCKCFGR_f; + }; + uint8_t RESERVED3[1]; + union + { + __IO uint8_t CMU_CKSWR; + stc_sysreg_cmu_ckswr_field_t CMU_CKSWR_f; + }; + uint8_t RESERVED4[3]; + union + { + __IO uint8_t CMU_PLLCR; + stc_sysreg_cmu_pllcr_field_t CMU_PLLCR_f; + }; + uint8_t RESERVED5[3]; + union + { + __IO uint8_t CMU_UPLLCR; + stc_sysreg_cmu_upllcr_field_t CMU_UPLLCR_f; + }; + uint8_t RESERVED6[3]; + union + { + __IO uint8_t CMU_XTALCR; + stc_sysreg_cmu_xtalcr_field_t CMU_XTALCR_f; + }; + uint8_t RESERVED7[3]; + union + { + __IO uint8_t CMU_HRCCR; + stc_sysreg_cmu_hrccr_field_t CMU_HRCCR_f; + }; + uint8_t RESERVED8[1]; + union + { + __IO uint8_t CMU_MRCCR; + stc_sysreg_cmu_mrccr_field_t CMU_MRCCR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t CMU_OSCSTBSR; + stc_sysreg_cmu_oscstbsr_field_t CMU_OSCSTBSR_f; + }; + union + { + __IO uint8_t CMU_MCO1CFGR; + stc_sysreg_cmu_mco1cfgr_field_t CMU_MCO1CFGR_f; + }; + union + { + __IO uint8_t CMU_MCO2CFGR; + stc_sysreg_cmu_mco2cfgr_field_t CMU_MCO2CFGR_f; + }; + union + { + __IO uint8_t CMU_TPIUCKCFGR; + stc_sysreg_cmu_tpiuckcfgr_field_t CMU_TPIUCKCFGR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDCR; + stc_sysreg_cmu_xtalstdcr_field_t CMU_XTALSTDCR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDSR; + stc_sysreg_cmu_xtalstdsr_field_t CMU_XTALSTDSR_f; + }; + uint8_t RESERVED10[31]; + __IO uint8_t CMU_MRCTRM; + __IO uint8_t CMU_HRCTRM; + uint8_t RESERVED11[63]; + union + { + __IO uint8_t CMU_XTALSTBCR; + stc_sysreg_cmu_xtalstbcr_field_t CMU_XTALSTBCR_f; + }; + uint8_t RESERVED12[29]; + union + { + __IO uint16_t RMU_RSTF0; + stc_sysreg_rmu_rstf0_field_t RMU_RSTF0_f; + }; + uint8_t RESERVED13[30]; + union + { + __IO uint8_t PWR_PVDICR; + stc_sysreg_pwr_pvdicr_field_t PWR_PVDICR_f; + }; + union + { + __IO uint8_t PWR_PVDDSR; + stc_sysreg_pwr_pvddsr_field_t PWR_PVDDSR_f; + }; + uint8_t RESERVED14[30]; + union + { + __IO uint32_t CMU_PLLCFGR; + stc_sysreg_cmu_pllcfgr_field_t CMU_PLLCFGR_f; + }; + union + { + __IO uint32_t CMU_UPLLCFGR; + stc_sysreg_cmu_upllcfgr_field_t CMU_UPLLCFGR_f; + }; + uint8_t RESERVED15[758]; + union + { + __IO uint16_t PWR_FPRC; + stc_sysreg_pwr_fprc_field_t PWR_FPRC_f; + }; + union + { + __IO uint8_t PWR_PWRC0; + stc_sysreg_pwr_pwrc0_field_t PWR_PWRC0_f; + }; + union + { + __IO uint8_t PWR_PWRC1; + stc_sysreg_pwr_pwrc1_field_t PWR_PWRC1_f; + }; + union + { + __IO uint8_t PWR_PWRC2; + stc_sysreg_pwr_pwrc2_field_t PWR_PWRC2_f; + }; + union + { + __IO uint8_t PWR_PWRC3; + stc_sysreg_pwr_pwrc3_field_t PWR_PWRC3_f; + }; + union + { + __IO uint8_t PWR_PDWKE0; + stc_sysreg_pwr_pdwke0_field_t PWR_PDWKE0_f; + }; + union + { + __IO uint8_t PWR_PDWKE1; + stc_sysreg_pwr_pdwke1_field_t PWR_PDWKE1_f; + }; + union + { + __IO uint8_t PWR_PDWKE2; + stc_sysreg_pwr_pdwke2_field_t PWR_PDWKE2_f; + }; + union + { + __IO uint8_t PWR_PDWKES; + stc_sysreg_pwr_pdwkes_field_t PWR_PDWKES_f; + }; + union + { + __IO uint8_t PWR_PDWKF0; + stc_sysreg_pwr_pdwkf0_field_t PWR_PDWKF0_f; + }; + union + { + __IO uint8_t PWR_PDWKF1; + stc_sysreg_pwr_pdwkf1_field_t PWR_PDWKF1_f; + }; + union + { + __IO uint8_t PWR_PWCMR; + stc_sysreg_pwr_pwcmr_field_t PWR_PWCMR_f; + }; + uint8_t RESERVED16[4]; + __IO uint8_t PWR_MDSWCR; + union + { + __IO uint8_t CMU_XTALCFGR; + stc_sysreg_cmu_xtalcfgr_field_t CMU_XTALCFGR_f; + }; + uint8_t RESERVED17[1]; + union + { + __IO uint8_t PWR_PVDCR0; + stc_sysreg_pwr_pvdcr0_field_t PWR_PVDCR0_f; + }; + union + { + __IO uint8_t PWR_PVDCR1; + stc_sysreg_pwr_pvdcr1_field_t PWR_PVDCR1_f; + }; + union + { + __IO uint8_t PWR_PVDFCR; + stc_sysreg_pwr_pvdfcr_field_t PWR_PVDFCR_f; + }; + union + { + __IO uint8_t PWR_PVDLCR; + stc_sysreg_pwr_pvdlcr_field_t PWR_PVDLCR_f; + }; + uint8_t RESERVED18[10]; + union + { + __IO uint8_t CMU_XTAL32CR; + stc_sysreg_cmu_xtal32cr_field_t CMU_XTAL32CR_f; + }; + union + { + __IO uint8_t CMU_XTAL32CFGR; + stc_sysreg_cmu_xtal32cfgr_field_t CMU_XTAL32CFGR_f; + }; + uint8_t RESERVED19[3]; + union + { + __IO uint8_t CMU_XTAL32NFR; + stc_sysreg_cmu_xtal32nfr_field_t CMU_XTAL32NFR_f; + }; + uint8_t RESERVED20[1]; + union + { + __IO uint8_t CMU_LRCCR; + stc_sysreg_cmu_lrccr_field_t CMU_LRCCR_f; + }; + uint8_t RESERVED21[1]; + __IO uint8_t CMU_LRCTRM; + uint8_t RESERVED22[1]; + union + { + __IO uint8_t PWR_XTAL32CS; + stc_sysreg_pwr_xtal32cs_field_t PWR_XTAL32CS_f; + }; +} M4_SYSREG_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct +{ + union + { + __IO uint32_t CNTAR; + stc_tmr0_cntar_field_t CNTAR_f; + }; + union + { + __IO uint32_t CNTBR; + stc_tmr0_cntbr_field_t CNTBR_f; + }; + union + { + __IO uint32_t CMPAR; + stc_tmr0_cmpar_field_t CMPAR_f; + }; + union + { + __IO uint32_t CMPBR; + stc_tmr0_cmpbr_field_t CMPBR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr0_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr0_stflr_field_t STFLR_f; + }; +} M4_TMR0_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct +{ + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + union + { + __IO uint16_t OCSRU; + stc_tmr4_ocsr_field_t OCSRU_f; + }; + union + { + __IO uint16_t OCERU; + stc_tmr4_ocer_field_t OCERU_f; + }; + union + { + __IO uint16_t OCSRV; + stc_tmr4_ocsr_field_t OCSRV_f; + }; + union + { + __IO uint16_t OCERV; + stc_tmr4_ocer_field_t OCERV_f; + }; + union + { + __IO uint16_t OCSRW; + stc_tmr4_ocsr_field_t OCSRW_f; + }; + union + { + __IO uint16_t OCERW; + stc_tmr4_ocer_field_t OCERW_f; + }; + union + { + __IO uint16_t OCMRHUH; + stc_tmr4_ocmrh_field_t OCMRHUH_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint32_t OCMRLUL; + stc_tmr4_ocmrl_field_t OCMRLUL_f; + }; + union + { + __IO uint16_t OCMRHVH; + stc_tmr4_ocmrh_field_t OCMRHVH_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint32_t OCMRLVL; + stc_tmr4_ocmrl_field_t OCMRLVL_f; + }; + union + { + __IO uint16_t OCMRHWH; + stc_tmr4_ocmrh_field_t OCMRHWH_f; + }; + uint8_t RESERVED8[2]; + union + { + __IO uint32_t OCMRLWL; + stc_tmr4_ocmrl_field_t OCMRLWL_f; + }; + uint8_t RESERVED9[6]; + __IO uint16_t CPSR; + uint8_t RESERVED10[2]; + __IO uint16_t CNTR; + union + { + __IO uint16_t CCSR; + stc_tmr4_ccsr_field_t CCSR_f; + }; + union + { + __IO uint16_t CVPR; + stc_tmr4_cvpr_field_t CVPR_f; + }; + uint8_t RESERVED11[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED12[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED13[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + union + { + __IO uint16_t POCRU; + stc_tmr4_pocr_field_t POCRU_f; + }; + uint8_t RESERVED14[2]; + union + { + __IO uint16_t POCRV; + stc_tmr4_pocr_field_t POCRV_f; + }; + uint8_t RESERVED15[2]; + union + { + __IO uint16_t POCRW; + stc_tmr4_pocr_field_t POCRW_f; + }; + uint8_t RESERVED16[2]; + union + { + __IO uint16_t RCSR; + stc_tmr4_rcsr_field_t RCSR_f; + }; + uint8_t RESERVED17[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED18[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED19[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED20[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRWL; + union + { + __IO uint16_t SCSRUH; + stc_tmr4_scsr_field_t SCSRUH_f; + }; + union + { + __IO uint16_t SCMRUH; + stc_tmr4_scmr_field_t SCMRUH_f; + }; + union + { + __IO uint16_t SCSRUL; + stc_tmr4_scsr_field_t SCSRUL_f; + }; + union + { + __IO uint16_t SCMRUL; + stc_tmr4_scmr_field_t SCMRUL_f; + }; + union + { + __IO uint16_t SCSRVH; + stc_tmr4_scsr_field_t SCSRVH_f; + }; + union + { + __IO uint16_t SCMRVH; + stc_tmr4_scmr_field_t SCMRVH_f; + }; + union + { + __IO uint16_t SCSRVL; + stc_tmr4_scsr_field_t SCSRVL_f; + }; + union + { + __IO uint16_t SCMRVL; + stc_tmr4_scmr_field_t SCMRVL_f; + }; + union + { + __IO uint16_t SCSRWH; + stc_tmr4_scsr_field_t SCSRWH_f; + }; + union + { + __IO uint16_t SCMRWH; + stc_tmr4_scmr_field_t SCMRWH_f; + }; + union + { + __IO uint16_t SCSRWL; + stc_tmr4_scsr_field_t SCSRWL_f; + }; + union + { + __IO uint16_t SCMRWL; + stc_tmr4_scmr_field_t SCMRWL_f; + }; + uint8_t RESERVED23[16]; + union + { + __IO uint16_t ECSR; + stc_tmr4_ecsr_field_t ECSR_f; + }; +} M4_TMR4_TypeDef; + +/** + * @brief TMR4_CR + */ +typedef struct +{ + union + { + __IO uint16_t ECER1; + stc_tmr4_cr_ecer1_field_t ECER1_f; + }; + uint8_t RESERVED0[2]; + union + { + __IO uint16_t ECER2; + stc_tmr4_cr_ecer2_field_t ECER2_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t ECER3; + stc_tmr4_cr_ecer3_field_t ECER3_f; + }; +} M4_TMR4_CR_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmr6_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmr6_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tmr6_perbr_field_t PERBR_f; + }; + union + { + __IO uint32_t PERCR; + stc_tmr6_percr_field_t PERCR_f; + }; + union + { + __IO uint32_t GCMAR; + stc_tmr6_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tmr6_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tmr6_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tmr6_gcmdr_field_t GCMDR_f; + }; + union + { + __IO uint32_t GCMER; + stc_tmr6_gcmer_field_t GCMER_f; + }; + union + { + __IO uint32_t GCMFR; + stc_tmr6_gcmfr_field_t GCMFR_f; + }; + union + { + __IO uint32_t SCMAR; + stc_tmr6_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tmr6_scmbr_field_t SCMBR_f; + }; + union + { + __IO uint32_t SCMCR; + stc_tmr6_scmcr_field_t SCMCR_f; + }; + union + { + __IO uint32_t SCMDR; + stc_tmr6_scmdr_field_t SCMDR_f; + }; + union + { + __IO uint32_t SCMER; + stc_tmr6_scmer_field_t SCMER_f; + }; + union + { + __IO uint32_t SCMFR; + stc_tmr6_scmfr_field_t SCMFR_f; + }; + union + { + __IO uint32_t DTUAR; + stc_tmr6_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tmr6_dtdar_field_t DTDAR_f; + }; + union + { + __IO uint32_t DTUBR; + stc_tmr6_dtubr_field_t DTUBR_f; + }; + union + { + __IO uint32_t DTDBR; + stc_tmr6_dtdbr_field_t DTDBR_f; + }; + union + { + __IO uint32_t GCONR; + stc_tmr6_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmr6_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tmr6_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr6_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tmr6_dconr_field_t DCONR_f; + }; + uint8_t RESERVED0[4]; + union + { + __IO uint32_t FCONR; + stc_tmr6_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tmr6_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr6_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tmr6_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tmr6_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCLRR; + stc_tmr6_hclrr_field_t HCLRR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tmr6_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tmr6_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmr6_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmr6_hcdor_field_t HCDOR_f; + }; +} M4_TMR6_TypeDef; + +/** + * @brief TMR6_CR + */ +typedef struct +{ + uint8_t RESERVED0[1012]; + union + { + __IO uint32_t SSTAR; + stc_tmr6_cr_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tmr6_cr_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tmr6_cr_sclrr_field_t SCLRR_f; + }; +} M4_TMR6_CR_TypeDef; + +/** + * @brief TMRA + */ +typedef struct +{ + union + { + __IO uint16_t CNTER; + stc_tmra_cnter_field_t CNTER_f; + }; + uint8_t RESERVED0[2]; + union + { + __IO uint16_t PERAR; + stc_tmra_perar_field_t PERAR_f; + }; + uint8_t RESERVED1[58]; + union + { + __IO uint16_t CMPAR1; + stc_tmra_cmpar_field_t CMPAR1_f; + }; + uint8_t RESERVED2[2]; + union + { + __IO uint16_t CMPAR2; + stc_tmra_cmpar_field_t CMPAR2_f; + }; + uint8_t RESERVED3[2]; + union + { + __IO uint16_t CMPAR3; + stc_tmra_cmpar_field_t CMPAR3_f; + }; + uint8_t RESERVED4[2]; + union + { + __IO uint16_t CMPAR4; + stc_tmra_cmpar_field_t CMPAR4_f; + }; + uint8_t RESERVED5[2]; + union + { + __IO uint16_t CMPAR5; + stc_tmra_cmpar_field_t CMPAR5_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint16_t CMPAR6; + stc_tmra_cmpar_field_t CMPAR6_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t CMPAR7; + stc_tmra_cmpar_field_t CMPAR7_f; + }; + uint8_t RESERVED8[2]; + union + { + __IO uint16_t CMPAR8; + stc_tmra_cmpar_field_t CMPAR8_f; + }; + uint8_t RESERVED9[34]; + union + { + __IO uint16_t BCSTR; + stc_tmra_bcstr_field_t BCSTR_f; + }; + uint8_t RESERVED10[2]; + union + { + __IO uint16_t HCONR; + stc_tmra_hconr_field_t HCONR_f; + }; + uint8_t RESERVED11[2]; + union + { + __IO uint16_t HCUPR; + stc_tmra_hcupr_field_t HCUPR_f; + }; + uint8_t RESERVED12[2]; + union + { + __IO uint16_t HCDOR; + stc_tmra_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint16_t ICONR; + stc_tmra_iconr_field_t ICONR_f; + }; + uint8_t RESERVED14[2]; + union + { + __IO uint16_t ECONR; + stc_tmra_econr_field_t ECONR_f; + }; + uint8_t RESERVED15[2]; + union + { + __IO uint16_t FCONR; + stc_tmra_fconr_field_t FCONR_f; + }; + uint8_t RESERVED16[2]; + union + { + __IO uint16_t STFLR; + stc_tmra_stflr_field_t STFLR_f; + }; + uint8_t RESERVED17[34]; + union + { + __IO uint16_t BCONR1; + stc_tmra_bconr_field_t BCONR1_f; + }; + uint8_t RESERVED18[6]; + union + { + __IO uint16_t BCONR2; + stc_tmra_bconr_field_t BCONR2_f; + }; + uint8_t RESERVED19[6]; + union + { + __IO uint16_t BCONR3; + stc_tmra_bconr_field_t BCONR3_f; + }; + uint8_t RESERVED20[6]; + union + { + __IO uint16_t BCONR4; + stc_tmra_bconr_field_t BCONR4_f; + }; + uint8_t RESERVED21[38]; + union + { + __IO uint16_t CCONR1; + stc_tmra_cconr_field_t CCONR1_f; + }; + uint8_t RESERVED22[2]; + union + { + __IO uint16_t CCONR2; + stc_tmra_cconr_field_t CCONR2_f; + }; + uint8_t RESERVED23[2]; + union + { + __IO uint16_t CCONR3; + stc_tmra_cconr_field_t CCONR3_f; + }; + uint8_t RESERVED24[2]; + union + { + __IO uint16_t CCONR4; + stc_tmra_cconr_field_t CCONR4_f; + }; + uint8_t RESERVED25[2]; + union + { + __IO uint16_t CCONR5; + stc_tmra_cconr_field_t CCONR5_f; + }; + uint8_t RESERVED26[2]; + union + { + __IO uint16_t CCONR6; + stc_tmra_cconr_field_t CCONR6_f; + }; + uint8_t RESERVED27[2]; + union + { + __IO uint16_t CCONR7; + stc_tmra_cconr_field_t CCONR7_f; + }; + uint8_t RESERVED28[2]; + union + { + __IO uint16_t CCONR8; + stc_tmra_cconr_field_t CCONR8_f; + }; + uint8_t RESERVED29[34]; + union + { + __IO uint16_t PCONR1; + stc_tmra_pconr_field_t PCONR1_f; + }; + uint8_t RESERVED30[2]; + union + { + __IO uint16_t PCONR2; + stc_tmra_pconr_field_t PCONR2_f; + }; + uint8_t RESERVED31[2]; + union + { + __IO uint16_t PCONR3; + stc_tmra_pconr_field_t PCONR3_f; + }; + uint8_t RESERVED32[2]; + union + { + __IO uint16_t PCONR4; + stc_tmra_pconr_field_t PCONR4_f; + }; + uint8_t RESERVED33[2]; + union + { + __IO uint16_t PCONR5; + stc_tmra_pconr_field_t PCONR5_f; + }; + uint8_t RESERVED34[2]; + union + { + __IO uint16_t PCONR6; + stc_tmra_pconr_field_t PCONR6_f; + }; + uint8_t RESERVED35[2]; + union + { + __IO uint16_t PCONR7; + stc_tmra_pconr_field_t PCONR7_f; + }; + uint8_t RESERVED36[2]; + union + { + __IO uint16_t PCONR8; + stc_tmra_pconr_field_t PCONR8_f; + }; +} M4_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct +{ + union + { + __IO uint32_t CR; + stc_trng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MR; + stc_trng_mr_field_t MR_f; + }; + uint8_t RESERVED0[4]; + __IO uint32_t DR0; + __IO uint32_t DR1; +} M4_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct +{ + union + { + __IO uint32_t SR; + stc_usart_sr_field_t SR_f; + }; + union + { + __IO uint32_t DR; + stc_usart_dr_field_t DR_f; + }; + union + { + __IO uint32_t BRR; + stc_usart_brr_field_t BRR_f; + }; + union + { + __IO uint32_t CR1; + stc_usart_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_usart_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_usart_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t PR; + stc_usart_pr_field_t PR_f; + }; +} M4_USART_TypeDef; + +/** + * @brief USBFS + */ +typedef struct +{ + union + { + __IO uint32_t GVBUSCFG; + stc_usbfs_gvbuscfg_field_t GVBUSCFG_f; + }; + uint8_t RESERVED0[4]; + union + { + __IO uint32_t GAHBCFG; + stc_usbfs_gahbcfg_field_t GAHBCFG_f; + }; + union + { + __IO uint32_t GUSBCFG; + stc_usbfs_gusbcfg_field_t GUSBCFG_f; + }; + union + { + __IO uint32_t GRSTCTL; + stc_usbfs_grstctl_field_t GRSTCTL_f; + }; + union + { + __IO uint32_t GINTSTS; + stc_usbfs_gintsts_field_t GINTSTS_f; + }; + union + { + __IO uint32_t GINTMSK; + stc_usbfs_gintmsk_field_t GINTMSK_f; + }; + union + { + __IO uint32_t GRXSTSR; + stc_usbfs_grxstsr_field_t GRXSTSR_f; + }; + union + { + __IO uint32_t GRXSTSP; + stc_usbfs_grxstsp_field_t GRXSTSP_f; + }; + union + { + __IO uint32_t GRXFSIZ; + stc_usbfs_grxfsiz_field_t GRXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXFSIZ; + stc_usbfs_hnptxfsiz_field_t HNPTXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXSTS; + stc_usbfs_hnptxsts_field_t HNPTXSTS_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t CID; + uint8_t RESERVED2[192]; + union + { + __IO uint32_t HPTXFSIZ; + stc_usbfs_hptxfsiz_field_t HPTXFSIZ_f; + }; + union + { + __IO uint32_t DIEPTXF1; + stc_usbfs_dieptxf_field_t DIEPTXF1_f; + }; + union + { + __IO uint32_t DIEPTXF2; + stc_usbfs_dieptxf_field_t DIEPTXF2_f; + }; + union + { + __IO uint32_t DIEPTXF3; + stc_usbfs_dieptxf_field_t DIEPTXF3_f; + }; + union + { + __IO uint32_t DIEPTXF4; + stc_usbfs_dieptxf_field_t DIEPTXF4_f; + }; + union + { + __IO uint32_t DIEPTXF5; + stc_usbfs_dieptxf_field_t DIEPTXF5_f; + }; + uint8_t RESERVED3[744]; + union + { + __IO uint32_t HCFG; + stc_usbfs_hcfg_field_t HCFG_f; + }; + union + { + __IO uint32_t HFIR; + stc_usbfs_hfir_field_t HFIR_f; + }; + union + { + __IO uint32_t HFNUM; + stc_usbfs_hfnum_field_t HFNUM_f; + }; + uint8_t RESERVED4[4]; + union + { + __IO uint32_t HPTXSTS; + stc_usbfs_hptxsts_field_t HPTXSTS_f; + }; + union + { + __IO uint32_t HAINT; + stc_usbfs_haint_field_t HAINT_f; + }; + union + { + __IO uint32_t HAINTMSK; + stc_usbfs_haintmsk_field_t HAINTMSK_f; + }; + uint8_t RESERVED5[36]; + union + { + __IO uint32_t HPRT; + stc_usbfs_hprt_field_t HPRT_f; + }; + uint8_t RESERVED6[188]; + union + { + __IO uint32_t HCCHAR0; + stc_usbfs_hcchar_field_t HCCHAR0_f; + }; + uint8_t RESERVED7[4]; + union + { + __IO uint32_t HCINT0; + stc_usbfs_hcint_field_t HCINT0_f; + }; + union + { + __IO uint32_t HCINTMSK0; + stc_usbfs_hcintmsk_field_t HCINTMSK0_f; + }; + union + { + __IO uint32_t HCTSIZ0; + stc_usbfs_hctsiz_field_t HCTSIZ0_f; + }; + __IO uint32_t HCDMA0; + uint8_t RESERVED8[8]; + union + { + __IO uint32_t HCCHAR1; + stc_usbfs_hcchar_field_t HCCHAR1_f; + }; + uint8_t RESERVED9[4]; + union + { + __IO uint32_t HCINT1; + stc_usbfs_hcint_field_t HCINT1_f; + }; + union + { + __IO uint32_t HCINTMSK1; + stc_usbfs_hcintmsk_field_t HCINTMSK1_f; + }; + union + { + __IO uint32_t HCTSIZ1; + stc_usbfs_hctsiz_field_t HCTSIZ1_f; + }; + __IO uint32_t HCDMA1; + uint8_t RESERVED10[8]; + union + { + __IO uint32_t HCCHAR2; + stc_usbfs_hcchar_field_t HCCHAR2_f; + }; + uint8_t RESERVED11[4]; + union + { + __IO uint32_t HCINT2; + stc_usbfs_hcint_field_t HCINT2_f; + }; + union + { + __IO uint32_t HCINTMSK2; + stc_usbfs_hcintmsk_field_t HCINTMSK2_f; + }; + union + { + __IO uint32_t HCTSIZ2; + stc_usbfs_hctsiz_field_t HCTSIZ2_f; + }; + __IO uint32_t HCDMA2; + uint8_t RESERVED12[8]; + union + { + __IO uint32_t HCCHAR3; + stc_usbfs_hcchar_field_t HCCHAR3_f; + }; + uint8_t RESERVED13[4]; + union + { + __IO uint32_t HCINT3; + stc_usbfs_hcint_field_t HCINT3_f; + }; + union + { + __IO uint32_t HCINTMSK3; + stc_usbfs_hcintmsk_field_t HCINTMSK3_f; + }; + union + { + __IO uint32_t HCTSIZ3; + stc_usbfs_hctsiz_field_t HCTSIZ3_f; + }; + __IO uint32_t HCDMA3; + uint8_t RESERVED14[8]; + union + { + __IO uint32_t HCCHAR4; + stc_usbfs_hcchar_field_t HCCHAR4_f; + }; + uint8_t RESERVED15[4]; + union + { + __IO uint32_t HCINT4; + stc_usbfs_hcint_field_t HCINT4_f; + }; + union + { + __IO uint32_t HCINTMSK4; + stc_usbfs_hcintmsk_field_t HCINTMSK4_f; + }; + union + { + __IO uint32_t HCTSIZ4; + stc_usbfs_hctsiz_field_t HCTSIZ4_f; + }; + __IO uint32_t HCDMA4; + uint8_t RESERVED16[8]; + union + { + __IO uint32_t HCCHAR5; + stc_usbfs_hcchar_field_t HCCHAR5_f; + }; + uint8_t RESERVED17[4]; + union + { + __IO uint32_t HCINT5; + stc_usbfs_hcint_field_t HCINT5_f; + }; + union + { + __IO uint32_t HCINTMSK5; + stc_usbfs_hcintmsk_field_t HCINTMSK5_f; + }; + union + { + __IO uint32_t HCTSIZ5; + stc_usbfs_hctsiz_field_t HCTSIZ5_f; + }; + __IO uint32_t HCDMA5; + uint8_t RESERVED18[8]; + union + { + __IO uint32_t HCCHAR6; + stc_usbfs_hcchar_field_t HCCHAR6_f; + }; + uint8_t RESERVED19[4]; + union + { + __IO uint32_t HCINT6; + stc_usbfs_hcint_field_t HCINT6_f; + }; + union + { + __IO uint32_t HCINTMSK6; + stc_usbfs_hcintmsk_field_t HCINTMSK6_f; + }; + union + { + __IO uint32_t HCTSIZ6; + stc_usbfs_hctsiz_field_t HCTSIZ6_f; + }; + __IO uint32_t HCDMA6; + uint8_t RESERVED20[8]; + union + { + __IO uint32_t HCCHAR7; + stc_usbfs_hcchar_field_t HCCHAR7_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t HCINT7; + stc_usbfs_hcint_field_t HCINT7_f; + }; + union + { + __IO uint32_t HCINTMSK7; + stc_usbfs_hcintmsk_field_t HCINTMSK7_f; + }; + union + { + __IO uint32_t HCTSIZ7; + stc_usbfs_hctsiz_field_t HCTSIZ7_f; + }; + __IO uint32_t HCDMA7; + uint8_t RESERVED22[8]; + union + { + __IO uint32_t HCCHAR8; + stc_usbfs_hcchar_field_t HCCHAR8_f; + }; + uint8_t RESERVED23[4]; + union + { + __IO uint32_t HCINT8; + stc_usbfs_hcint_field_t HCINT8_f; + }; + union + { + __IO uint32_t HCINTMSK8; + stc_usbfs_hcintmsk_field_t HCINTMSK8_f; + }; + union + { + __IO uint32_t HCTSIZ8; + stc_usbfs_hctsiz_field_t HCTSIZ8_f; + }; + __IO uint32_t HCDMA8; + uint8_t RESERVED24[8]; + union + { + __IO uint32_t HCCHAR9; + stc_usbfs_hcchar_field_t HCCHAR9_f; + }; + uint8_t RESERVED25[4]; + union + { + __IO uint32_t HCINT9; + stc_usbfs_hcint_field_t HCINT9_f; + }; + union + { + __IO uint32_t HCINTMSK9; + stc_usbfs_hcintmsk_field_t HCINTMSK9_f; + }; + union + { + __IO uint32_t HCTSIZ9; + stc_usbfs_hctsiz_field_t HCTSIZ9_f; + }; + __IO uint32_t HCDMA9; + uint8_t RESERVED26[8]; + union + { + __IO uint32_t HCCHAR10; + stc_usbfs_hcchar_field_t HCCHAR10_f; + }; + uint8_t RESERVED27[4]; + union + { + __IO uint32_t HCINT10; + stc_usbfs_hcint_field_t HCINT10_f; + }; + union + { + __IO uint32_t HCINTMSK10; + stc_usbfs_hcintmsk_field_t HCINTMSK10_f; + }; + union + { + __IO uint32_t HCTSIZ10; + stc_usbfs_hctsiz_field_t HCTSIZ10_f; + }; + __IO uint32_t HCDMA10; + uint8_t RESERVED28[8]; + union + { + __IO uint32_t HCCHAR11; + stc_usbfs_hcchar_field_t HCCHAR11_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t HCINT11; + stc_usbfs_hcint_field_t HCINT11_f; + }; + union + { + __IO uint32_t HCINTMSK11; + stc_usbfs_hcintmsk_field_t HCINTMSK11_f; + }; + union + { + __IO uint32_t HCTSIZ11; + stc_usbfs_hctsiz_field_t HCTSIZ11_f; + }; + __IO uint32_t HCDMA11; + uint8_t RESERVED30[392]; + union + { + __IO uint32_t DCFG; + stc_usbfs_dcfg_field_t DCFG_f; + }; + union + { + __IO uint32_t DCTL; + stc_usbfs_dctl_field_t DCTL_f; + }; + union + { + __IO uint32_t DSTS; + stc_usbfs_dsts_field_t DSTS_f; + }; + uint8_t RESERVED31[4]; + union + { + __IO uint32_t DIEPMSK; + stc_usbfs_diepmsk_field_t DIEPMSK_f; + }; + union + { + __IO uint32_t DOEPMSK; + stc_usbfs_doepmsk_field_t DOEPMSK_f; + }; + union + { + __IO uint32_t DAINT; + stc_usbfs_daint_field_t DAINT_f; + }; + union + { + __IO uint32_t DAINTMSK; + stc_usbfs_daintmsk_field_t DAINTMSK_f; + }; + uint8_t RESERVED32[20]; + union + { + __IO uint32_t DIEPEMPMSK; + stc_usbfs_diepempmsk_field_t DIEPEMPMSK_f; + }; + uint8_t RESERVED33[200]; + union + { + __IO uint32_t DIEPCTL0; + stc_usbfs_diepctl0_field_t DIEPCTL0_f; + }; + uint8_t RESERVED34[4]; + union + { + __IO uint32_t DIEPINT0; + stc_usbfs_diepint0_field_t DIEPINT0_f; + }; + uint8_t RESERVED35[4]; + union + { + __IO uint32_t DIEPTSIZ0; + stc_usbfs_dieptsiz0_field_t DIEPTSIZ0_f; + }; + __IO uint32_t DIEPDMA0; + union + { + __IO uint32_t DTXFSTS0; + stc_usbfs_dtxfsts0_field_t DTXFSTS0_f; + }; + uint8_t RESERVED36[4]; + union + { + __IO uint32_t DIEPCTL1; + stc_usbfs_diepctl_field_t DIEPCTL1_f; + }; + uint8_t RESERVED37[4]; + union + { + __IO uint32_t DIEPINT1; + stc_usbfs_diepint_field_t DIEPINT1_f; + }; + uint8_t RESERVED38[4]; + union + { + __IO uint32_t DIEPTSIZ1; + stc_usbfs_dieptsiz_field_t DIEPTSIZ1_f; + }; + __IO uint32_t DIEPDMA1; + union + { + __IO uint32_t DTXFSTS1; + stc_usbfs_dtxfsts_field_t DTXFSTS1_f; + }; + uint8_t RESERVED39[4]; + union + { + __IO uint32_t DIEPCTL2; + stc_usbfs_diepctl_field_t DIEPCTL2_f; + }; + uint8_t RESERVED40[4]; + union + { + __IO uint32_t DIEPINT2; + stc_usbfs_diepint_field_t DIEPINT2_f; + }; + uint8_t RESERVED41[4]; + union + { + __IO uint32_t DIEPTSIZ2; + stc_usbfs_dieptsiz_field_t DIEPTSIZ2_f; + }; + __IO uint32_t DIEPDMA2; + union + { + __IO uint32_t DTXFSTS2; + stc_usbfs_dtxfsts_field_t DTXFSTS2_f; + }; + uint8_t RESERVED42[4]; + union + { + __IO uint32_t DIEPCTL3; + stc_usbfs_diepctl_field_t DIEPCTL3_f; + }; + uint8_t RESERVED43[4]; + union + { + __IO uint32_t DIEPINT3; + stc_usbfs_diepint_field_t DIEPINT3_f; + }; + uint8_t RESERVED44[4]; + union + { + __IO uint32_t DIEPTSIZ3; + stc_usbfs_dieptsiz_field_t DIEPTSIZ3_f; + }; + __IO uint32_t DIEPDMA3; + union + { + __IO uint32_t DTXFSTS3; + stc_usbfs_dtxfsts_field_t DTXFSTS3_f; + }; + uint8_t RESERVED45[4]; + union + { + __IO uint32_t DIEPCTL4; + stc_usbfs_diepctl_field_t DIEPCTL4_f; + }; + uint8_t RESERVED46[4]; + union + { + __IO uint32_t DIEPINT4; + stc_usbfs_diepint_field_t DIEPINT4_f; + }; + uint8_t RESERVED47[4]; + union + { + __IO uint32_t DIEPTSIZ4; + stc_usbfs_dieptsiz_field_t DIEPTSIZ4_f; + }; + __IO uint32_t DIEPDMA4; + union + { + __IO uint32_t DTXFSTS4; + stc_usbfs_dtxfsts_field_t DTXFSTS4_f; + }; + uint8_t RESERVED48[4]; + union + { + __IO uint32_t DIEPCTL5; + stc_usbfs_diepctl_field_t DIEPCTL5_f; + }; + uint8_t RESERVED49[4]; + union + { + __IO uint32_t DIEPINT5; + stc_usbfs_diepint_field_t DIEPINT5_f; + }; + uint8_t RESERVED50[4]; + union + { + __IO uint32_t DIEPTSIZ5; + stc_usbfs_dieptsiz_field_t DIEPTSIZ5_f; + }; + __IO uint32_t DIEPDMA5; + union + { + __IO uint32_t DTXFSTS5; + stc_usbfs_dtxfsts_field_t DTXFSTS5_f; + }; + uint8_t RESERVED51[324]; + union + { + __IO uint32_t DOEPCTL0; + stc_usbfs_doepctl0_field_t DOEPCTL0_f; + }; + uint8_t RESERVED52[4]; + union + { + __IO uint32_t DOEPINT0; + stc_usbfs_doepint_field_t DOEPINT0_f; + }; + uint8_t RESERVED53[4]; + union + { + __IO uint32_t DOEPTSIZ0; + stc_usbfs_doeptsiz0_field_t DOEPTSIZ0_f; + }; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED54[8]; + union + { + __IO uint32_t DOEPCTL1; + stc_usbfs_doepctl_field_t DOEPCTL1_f; + }; + uint8_t RESERVED55[4]; + union + { + __IO uint32_t DOEPINT1; + stc_usbfs_doepint_field_t DOEPINT1_f; + }; + uint8_t RESERVED56[4]; + union + { + __IO uint32_t DOEPTSIZ1; + stc_usbfs_doeptsiz_field_t DOEPTSIZ1_f; + }; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED57[8]; + union + { + __IO uint32_t DOEPCTL2; + stc_usbfs_doepctl_field_t DOEPCTL2_f; + }; + uint8_t RESERVED58[4]; + union + { + __IO uint32_t DOEPINT2; + stc_usbfs_doepint_field_t DOEPINT2_f; + }; + uint8_t RESERVED59[4]; + union + { + __IO uint32_t DOEPTSIZ2; + stc_usbfs_doeptsiz_field_t DOEPTSIZ2_f; + }; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED60[8]; + union + { + __IO uint32_t DOEPCTL3; + stc_usbfs_doepctl_field_t DOEPCTL3_f; + }; + uint8_t RESERVED61[4]; + union + { + __IO uint32_t DOEPINT3; + stc_usbfs_doepint_field_t DOEPINT3_f; + }; + uint8_t RESERVED62[4]; + union + { + __IO uint32_t DOEPTSIZ3; + stc_usbfs_doeptsiz_field_t DOEPTSIZ3_f; + }; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED63[8]; + union + { + __IO uint32_t DOEPCTL4; + stc_usbfs_doepctl_field_t DOEPCTL4_f; + }; + uint8_t RESERVED64[4]; + union + { + __IO uint32_t DOEPINT4; + stc_usbfs_doepint_field_t DOEPINT4_f; + }; + uint8_t RESERVED65[4]; + union + { + __IO uint32_t DOEPTSIZ4; + stc_usbfs_doeptsiz_field_t DOEPTSIZ4_f; + }; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED66[8]; + union + { + __IO uint32_t DOEPCTL5; + stc_usbfs_doepctl_field_t DOEPCTL5_f; + }; + uint8_t RESERVED67[4]; + union + { + __IO uint32_t DOEPINT5; + stc_usbfs_doepint_field_t DOEPINT5_f; + }; + uint8_t RESERVED68[4]; + union + { + __IO uint32_t DOEPTSIZ5; + stc_usbfs_doeptsiz_field_t DOEPTSIZ5_f; + }; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED69[584]; + union + { + __IO uint32_t PCGCCTL; + stc_usbfs_pcgcctl_field_t PCGCCTL_f; + }; +} M4_USBFS_TypeDef; + +/** + * @brief WDT + */ +typedef struct +{ + union + { + __IO uint32_t CR; + stc_wdt_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_wdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_wdt_rr_field_t RR_f; + }; +} M4_WDT_TypeDef; + +/** + * @brief WKTM + */ +typedef struct +{ + union + { + __IO uint16_t CR; + stc_wktm_cr_field_t CR_f; + }; +} M4_WKTM_TypeDef; + + + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ + +#define M4_ADC1 ((M4_ADC_TypeDef *)0x40040000UL) +#define M4_ADC2 ((M4_ADC_TypeDef *)0x40040400UL) +#define M4_AES ((M4_AES_TypeDef *)0x40008000UL) +#define M4_AOS ((M4_AOS_TypeDef *)0x40010800UL) +#define M4_CAN ((M4_CAN_TypeDef *)0x40070400UL) +#define M4_CMP1 ((M4_CMP_TypeDef *)0x4004A000UL) +#define M4_CMP2 ((M4_CMP_TypeDef *)0x4004A010UL) +#define M4_CMP3 ((M4_CMP_TypeDef *)0x4004A020UL) +#define M4_CMP_CR ((M4_CMP_CR_TypeDef *)0x4004A000UL) +#define M4_CRC ((M4_CRC_TypeDef *)0x40008C00UL) +#define M4_DBGC ((M4_DBGC_TypeDef *)0xE0042000UL) +#define M4_DCU1 ((M4_DCU_TypeDef *)0x40052000UL) +#define M4_DCU2 ((M4_DCU_TypeDef *)0x40052400UL) +#define M4_DCU3 ((M4_DCU_TypeDef *)0x40052800UL) +#define M4_DCU4 ((M4_DCU_TypeDef *)0x40052C00UL) +#define M4_DMA1 ((M4_DMA_TypeDef *)0x40053000UL) +#define M4_DMA2 ((M4_DMA_TypeDef *)0x40053400UL) +#define M4_EFM ((M4_EFM_TypeDef *)0x40010400UL) +#define M4_EMB1 ((M4_EMB_TypeDef *)0x40017C00UL) +#define M4_EMB2 ((M4_EMB_TypeDef *)0x40017C20UL) +#define M4_EMB3 ((M4_EMB_TypeDef *)0x40017C40UL) +#define M4_EMB4 ((M4_EMB_TypeDef *)0x40017C60UL) +#define M4_FCM ((M4_FCM_TypeDef *)0x40048400UL) +#define M4_HASH ((M4_HASH_TypeDef *)0x40008400UL) +#define M4_I2C1 ((M4_I2C_TypeDef *)0x4004E000UL) +#define M4_I2C2 ((M4_I2C_TypeDef *)0x4004E400UL) +#define M4_I2C3 ((M4_I2C_TypeDef *)0x4004E800UL) +#define M4_I2S1 ((M4_I2S_TypeDef *)0x4001E000UL) +#define M4_I2S2 ((M4_I2S_TypeDef *)0x4001E400UL) +#define M4_I2S3 ((M4_I2S_TypeDef *)0x40022000UL) +#define M4_I2S4 ((M4_I2S_TypeDef *)0x40022400UL) +#define M4_ICG ((M4_ICG_TypeDef *)0x00000400UL) +#define M4_INTC ((M4_INTC_TypeDef *)0x40051000UL) +#define M4_KEYSCAN ((M4_KEYSCAN_TypeDef *)0x40050C00UL) +#define M4_MPU ((M4_MPU_TypeDef *)0x40050000UL) +#define M4_MSTP ((M4_MSTP_TypeDef *)0x40048000UL) +#define M4_OTS ((M4_OTS_TypeDef *)0x4004A400UL) +#define M4_PERIC ((M4_PERIC_TypeDef *)0x40055400UL) +#define M4_PORT ((M4_PORT_TypeDef *)0x40053800UL) +#define M4_QSPI ((M4_QSPI_TypeDef *)0x9C000000UL) +#define M4_RTC ((M4_RTC_TypeDef *)0x4004C000UL) +#define M4_SDIOC1 ((M4_SDIOC_TypeDef *)0x4006FC00UL) +#define M4_SDIOC2 ((M4_SDIOC_TypeDef *)0x40070000UL) +#define M4_SPI1 ((M4_SPI_TypeDef *)0x4001C000UL) +#define M4_SPI2 ((M4_SPI_TypeDef *)0x4001C400UL) +#define M4_SPI3 ((M4_SPI_TypeDef *)0x40020000UL) +#define M4_SPI4 ((M4_SPI_TypeDef *)0x40020400UL) +#define M4_SRAMC ((M4_SRAMC_TypeDef *)0x40050800UL) +#define M4_SWDT ((M4_SWDT_TypeDef *)0x40049400UL) +#define M4_SYSREG ((M4_SYSREG_TypeDef *)0x40054000UL) +#define M4_TMR01 ((M4_TMR0_TypeDef *)0x40024000UL) +#define M4_TMR02 ((M4_TMR0_TypeDef *)0x40024400UL) +#define M4_TMR41 ((M4_TMR4_TypeDef *)0x40017000UL) +#define M4_TMR42 ((M4_TMR4_TypeDef *)0x40024800UL) +#define M4_TMR43 ((M4_TMR4_TypeDef *)0x40024C00UL) +#define M4_TMR4_CR ((M4_TMR4_CR_TypeDef *)0x40055408UL) +#define M4_TMR61 ((M4_TMR6_TypeDef *)0x40018000UL) +#define M4_TMR62 ((M4_TMR6_TypeDef *)0x40018400UL) +#define M4_TMR63 ((M4_TMR6_TypeDef *)0x40018800UL) +#define M4_TMR6_CR ((M4_TMR6_CR_TypeDef *)0x40018000UL) +#define M4_TMRA1 ((M4_TMRA_TypeDef *)0x40015000UL) +#define M4_TMRA2 ((M4_TMRA_TypeDef *)0x40015400UL) +#define M4_TMRA3 ((M4_TMRA_TypeDef *)0x40015800UL) +#define M4_TMRA4 ((M4_TMRA_TypeDef *)0x40015C00UL) +#define M4_TMRA5 ((M4_TMRA_TypeDef *)0x40016000UL) +#define M4_TMRA6 ((M4_TMRA_TypeDef *)0x40016400UL) +#define M4_TRNG ((M4_TRNG_TypeDef *)0x40041000UL) +#define M4_USART1 ((M4_USART_TypeDef *)0x4001D000UL) +#define M4_USART2 ((M4_USART_TypeDef *)0x4001D400UL) +#define M4_USART3 ((M4_USART_TypeDef *)0x40021000UL) +#define M4_USART4 ((M4_USART_TypeDef *)0x40021400UL) +#define M4_USBFS ((M4_USBFS_TypeDef *)0x400C0000UL) +#define M4_WDT ((M4_WDT_TypeDef *)0x40049000UL) +#define M4_WKTM ((M4_WKTM_TypeDef *)0x4004C400UL) + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ + +#define bM4_ADC1_STR_STRT (*((volatile unsigned int*)(0x42800000UL))) +#define bM4_ADC1_CR0_MS0 (*((volatile unsigned int*)(0x42800040UL))) +#define bM4_ADC1_CR0_MS1 (*((volatile unsigned int*)(0x42800044UL))) +#define bM4_ADC1_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42800050UL))) +#define bM4_ADC1_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42800054UL))) +#define bM4_ADC1_CR0_CLREN (*((volatile unsigned int*)(0x42800058UL))) +#define bM4_ADC1_CR0_DFMT (*((volatile unsigned int*)(0x4280005CUL))) +#define bM4_ADC1_CR0_AVCNT0 (*((volatile unsigned int*)(0x42800060UL))) +#define bM4_ADC1_CR0_AVCNT1 (*((volatile unsigned int*)(0x42800064UL))) +#define bM4_ADC1_CR0_AVCNT2 (*((volatile unsigned int*)(0x42800068UL))) +#define bM4_ADC1_CR1_RSCHSEL (*((volatile unsigned int*)(0x42800088UL))) +#define bM4_ADC1_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42800140UL))) +#define bM4_ADC1_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42800144UL))) +#define bM4_ADC1_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42800148UL))) +#define bM4_ADC1_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280015CUL))) +#define bM4_ADC1_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42800160UL))) +#define bM4_ADC1_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42800164UL))) +#define bM4_ADC1_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42800168UL))) +#define bM4_ADC1_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280017CUL))) +#define bM4_ADC1_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428001C0UL))) +#define bM4_ADC1_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42800240UL))) +#define bM4_ADC1_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428002C0UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42800700UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42800704UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42800708UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280070CUL))) +#define bM4_ADC1_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42800710UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42800714UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42800718UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280071CUL))) +#define bM4_ADC1_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42800720UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42800724UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42800728UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280072CUL))) +#define bM4_ADC1_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42800730UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42800734UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42800738UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280073CUL))) +#define bM4_ADC1_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42800740UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42800744UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42800748UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280074CUL))) +#define bM4_ADC1_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42800750UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42800754UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42800758UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280075CUL))) +#define bM4_ADC1_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42800760UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42800764UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42800768UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280076CUL))) +#define bM4_ADC1_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42800770UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42800774UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42800778UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280077CUL))) +#define bM4_ADC1_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42800780UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42800784UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42800788UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280078CUL))) +#define bM4_ADC1_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42800790UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42800794UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42800798UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280079CUL))) +#define bM4_ADC1_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428007A0UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428007A4UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428007A8UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428007ACUL))) +#define bM4_ADC1_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428007B0UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428007B4UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428007B8UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428007BCUL))) +#define bM4_ADC1_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428007C0UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428007C4UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428007C8UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428007CCUL))) +#define bM4_ADC1_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428007D0UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428007D4UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428007D8UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428007DCUL))) +#define bM4_ADC1_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428007E0UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428007E4UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428007E8UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428007ECUL))) +#define bM4_ADC1_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428007F0UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428007F4UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428007F8UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428007FCUL))) +#define bM4_ADC1_ISR_EOCAF (*((volatile unsigned int*)(0x428008C0UL))) +#define bM4_ADC1_ISR_EOCBF (*((volatile unsigned int*)(0x428008C4UL))) +#define bM4_ADC1_ICR_EOCAIEN (*((volatile unsigned int*)(0x428008E0UL))) +#define bM4_ADC1_ICR_EOCBIEN (*((volatile unsigned int*)(0x428008E4UL))) +#define bM4_ADC1_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42800980UL))) +#define bM4_ADC1_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42800990UL))) +#define bM4_ADC1_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42800994UL))) +#define bM4_ADC1_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42800998UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428009A0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428009A4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428009A8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428009ACUL))) +#define bM4_ADC1_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428009B0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428009B4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428009B8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428009BCUL))) +#define bM4_ADC1_AWDCR_AWDEN (*((volatile unsigned int*)(0x42801400UL))) +#define bM4_ADC1_AWDCR_AWDMD (*((volatile unsigned int*)(0x42801410UL))) +#define bM4_ADC1_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42801418UL))) +#define bM4_ADC1_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280141CUL))) +#define bM4_ADC1_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42801420UL))) +#define bM4_ADC1_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428015C0UL))) +#define bM4_ADC1_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42801640UL))) +#define bM4_ADC1_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42801800UL))) +#define bM4_ADC1_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42801804UL))) +#define bM4_ADC1_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42801808UL))) +#define bM4_ADC1_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280180CUL))) +#define bM4_ADC1_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42801840UL))) +#define bM4_ADC1_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42801844UL))) +#define bM4_ADC1_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42801848UL))) +#define bM4_ADC1_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280184CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42801980UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42801984UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42801988UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280198CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42801990UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42801994UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42801998UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280199CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428019A0UL))) +#define bM4_ADC1_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428019C0UL))) +#define bM4_ADC2_STR_STRT (*((volatile unsigned int*)(0x42808000UL))) +#define bM4_ADC2_CR0_MS0 (*((volatile unsigned int*)(0x42808040UL))) +#define bM4_ADC2_CR0_MS1 (*((volatile unsigned int*)(0x42808044UL))) +#define bM4_ADC2_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42808050UL))) +#define bM4_ADC2_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42808054UL))) +#define bM4_ADC2_CR0_CLREN (*((volatile unsigned int*)(0x42808058UL))) +#define bM4_ADC2_CR0_DFMT (*((volatile unsigned int*)(0x4280805CUL))) +#define bM4_ADC2_CR0_AVCNT0 (*((volatile unsigned int*)(0x42808060UL))) +#define bM4_ADC2_CR0_AVCNT1 (*((volatile unsigned int*)(0x42808064UL))) +#define bM4_ADC2_CR0_AVCNT2 (*((volatile unsigned int*)(0x42808068UL))) +#define bM4_ADC2_CR1_RSCHSEL (*((volatile unsigned int*)(0x42808088UL))) +#define bM4_ADC2_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42808140UL))) +#define bM4_ADC2_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42808144UL))) +#define bM4_ADC2_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42808148UL))) +#define bM4_ADC2_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280815CUL))) +#define bM4_ADC2_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42808160UL))) +#define bM4_ADC2_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42808164UL))) +#define bM4_ADC2_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42808168UL))) +#define bM4_ADC2_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280817CUL))) +#define bM4_ADC2_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428081C0UL))) +#define bM4_ADC2_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42808240UL))) +#define bM4_ADC2_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428082C0UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42808700UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42808704UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42808708UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280870CUL))) +#define bM4_ADC2_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42808710UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42808714UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42808718UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280871CUL))) +#define bM4_ADC2_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42808720UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42808724UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42808728UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280872CUL))) +#define bM4_ADC2_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42808730UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42808734UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42808738UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280873CUL))) +#define bM4_ADC2_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42808740UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42808744UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42808748UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280874CUL))) +#define bM4_ADC2_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42808750UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42808754UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42808758UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280875CUL))) +#define bM4_ADC2_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42808760UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42808764UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42808768UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280876CUL))) +#define bM4_ADC2_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42808770UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42808774UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42808778UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280877CUL))) +#define bM4_ADC2_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42808780UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42808784UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42808788UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280878CUL))) +#define bM4_ADC2_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42808790UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42808794UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42808798UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280879CUL))) +#define bM4_ADC2_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428087A0UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428087A4UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428087A8UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428087ACUL))) +#define bM4_ADC2_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428087B0UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428087B4UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428087B8UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428087BCUL))) +#define bM4_ADC2_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428087C0UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428087C4UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428087C8UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428087CCUL))) +#define bM4_ADC2_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428087D0UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428087D4UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428087D8UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428087DCUL))) +#define bM4_ADC2_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428087E0UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428087E4UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428087E8UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428087ECUL))) +#define bM4_ADC2_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428087F0UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428087F4UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428087F8UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428087FCUL))) +#define bM4_ADC2_ISR_EOCAF (*((volatile unsigned int*)(0x428088C0UL))) +#define bM4_ADC2_ISR_EOCBF (*((volatile unsigned int*)(0x428088C4UL))) +#define bM4_ADC2_ICR_EOCAIEN (*((volatile unsigned int*)(0x428088E0UL))) +#define bM4_ADC2_ICR_EOCBIEN (*((volatile unsigned int*)(0x428088E4UL))) +#define bM4_ADC2_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42808980UL))) +#define bM4_ADC2_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42808990UL))) +#define bM4_ADC2_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42808994UL))) +#define bM4_ADC2_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42808998UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428089A0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428089A4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428089A8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428089ACUL))) +#define bM4_ADC2_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428089B0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428089B4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428089B8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428089BCUL))) +#define bM4_ADC2_AWDCR_AWDEN (*((volatile unsigned int*)(0x42809400UL))) +#define bM4_ADC2_AWDCR_AWDMD (*((volatile unsigned int*)(0x42809410UL))) +#define bM4_ADC2_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42809418UL))) +#define bM4_ADC2_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280941CUL))) +#define bM4_ADC2_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42809420UL))) +#define bM4_ADC2_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428095C0UL))) +#define bM4_ADC2_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42809640UL))) +#define bM4_ADC2_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42809800UL))) +#define bM4_ADC2_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42809804UL))) +#define bM4_ADC2_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42809808UL))) +#define bM4_ADC2_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280980CUL))) +#define bM4_ADC2_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42809840UL))) +#define bM4_ADC2_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42809844UL))) +#define bM4_ADC2_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42809848UL))) +#define bM4_ADC2_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280984CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42809980UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42809984UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42809988UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280998CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42809990UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42809994UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42809998UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280999CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428099A0UL))) +#define bM4_ADC2_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428099C0UL))) +#define bM4_AES_CR_START (*((volatile unsigned int*)(0x42100000UL))) +#define bM4_AES_CR_MODE (*((volatile unsigned int*)(0x42100004UL))) +#define bM4_AOS_INT_SFTTRG_STRG (*((volatile unsigned int*)(0x42210000UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210080UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210084UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210088UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221008CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210090UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210094UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210098UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221009CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422100A0UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422100F8UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422100FCUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210100UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210104UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210108UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221010CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210110UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210114UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210118UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221011CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210120UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210178UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221017CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210180UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210184UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210188UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221018CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210190UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210194UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210198UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221019CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422101A0UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422101F8UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422101FCUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210200UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210204UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210208UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221020CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210210UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210214UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210218UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221021CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210220UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210278UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221027CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210280UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210284UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210288UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221028CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210290UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210294UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210298UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221029CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422102A0UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422102F8UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422102FCUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210300UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210304UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210308UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221030CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210310UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210314UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210318UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221031CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210320UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210378UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221037CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210380UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210384UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210388UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221038CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210390UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210394UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210398UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221039CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422103A0UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422103F8UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422103FCUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210400UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210404UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210408UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221040CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210410UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210414UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210418UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221041CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210420UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210478UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221047CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210480UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210484UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210488UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221048CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210490UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210494UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210498UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221049CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422104A0UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422104F8UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422104FCUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210500UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210504UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210508UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221050CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210510UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210514UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210518UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221051CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210520UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210578UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221057CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210580UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210584UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210588UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221058CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210590UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210594UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210598UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221059CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422105A0UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422105F8UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422105FCUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210600UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210604UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210608UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221060CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210610UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210614UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210618UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221061CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210620UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210678UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221067CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL0 (*((volatile unsigned int*)(0x42210680UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL1 (*((volatile unsigned int*)(0x42210684UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL2 (*((volatile unsigned int*)(0x42210688UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL3 (*((volatile unsigned int*)(0x4221068CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL4 (*((volatile unsigned int*)(0x42210690UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL5 (*((volatile unsigned int*)(0x42210694UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL6 (*((volatile unsigned int*)(0x42210698UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL7 (*((volatile unsigned int*)(0x4221069CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL8 (*((volatile unsigned int*)(0x422106A0UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN0 (*((volatile unsigned int*)(0x422106F8UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN1 (*((volatile unsigned int*)(0x422106FCUL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL0 (*((volatile unsigned int*)(0x42210700UL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL1 (*((volatile unsigned int*)(0x42210704UL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL2 (*((volatile unsigned int*)(0x42210708UL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL3 (*((volatile unsigned int*)(0x4221070CUL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL4 (*((volatile unsigned int*)(0x42210710UL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL5 (*((volatile unsigned int*)(0x42210714UL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL6 (*((volatile unsigned int*)(0x42210718UL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL7 (*((volatile unsigned int*)(0x4221071CUL))) +#define bM4_AOS_TMR6_HTSSR0_TRGSEL8 (*((volatile unsigned int*)(0x42210720UL))) +#define bM4_AOS_TMR6_HTSSR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210778UL))) +#define bM4_AOS_TMR6_HTSSR0_COMTRG_EN1 (*((volatile unsigned int*)(0x4221077CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210780UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210784UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210788UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x4221078CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210790UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210794UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210798UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x4221079CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x422107A0UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x422107F8UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x422107FCUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL0 (*((volatile unsigned int*)(0x42210800UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL1 (*((volatile unsigned int*)(0x42210804UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL2 (*((volatile unsigned int*)(0x42210808UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL3 (*((volatile unsigned int*)(0x4221080CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL4 (*((volatile unsigned int*)(0x42210810UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL5 (*((volatile unsigned int*)(0x42210814UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL6 (*((volatile unsigned int*)(0x42210818UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL7 (*((volatile unsigned int*)(0x4221081CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL8 (*((volatile unsigned int*)(0x42210820UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN0 (*((volatile unsigned int*)(0x42210878UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN1 (*((volatile unsigned int*)(0x4221087CUL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL0 (*((volatile unsigned int*)(0x42210880UL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL1 (*((volatile unsigned int*)(0x42210884UL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL2 (*((volatile unsigned int*)(0x42210888UL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL3 (*((volatile unsigned int*)(0x4221088CUL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL4 (*((volatile unsigned int*)(0x42210890UL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL5 (*((volatile unsigned int*)(0x42210894UL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL6 (*((volatile unsigned int*)(0x42210898UL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL7 (*((volatile unsigned int*)(0x4221089CUL))) +#define bM4_AOS_PEVNTTRGSR12_TRGSEL8 (*((volatile unsigned int*)(0x422108A0UL))) +#define bM4_AOS_PEVNTTRGSR12_COMTRG_EN0 (*((volatile unsigned int*)(0x422108F8UL))) +#define bM4_AOS_PEVNTTRGSR12_COMTRG_EN1 (*((volatile unsigned int*)(0x422108FCUL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL0 (*((volatile unsigned int*)(0x42210900UL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL1 (*((volatile unsigned int*)(0x42210904UL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL2 (*((volatile unsigned int*)(0x42210908UL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL3 (*((volatile unsigned int*)(0x4221090CUL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL4 (*((volatile unsigned int*)(0x42210910UL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL5 (*((volatile unsigned int*)(0x42210914UL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL6 (*((volatile unsigned int*)(0x42210918UL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL7 (*((volatile unsigned int*)(0x4221091CUL))) +#define bM4_AOS_PEVNTTRGSR34_TRGSEL8 (*((volatile unsigned int*)(0x42210920UL))) +#define bM4_AOS_PEVNTTRGSR34_COMTRG_EN0 (*((volatile unsigned int*)(0x42210978UL))) +#define bM4_AOS_PEVNTTRGSR34_COMTRG_EN1 (*((volatile unsigned int*)(0x4221097CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL0 (*((volatile unsigned int*)(0x42210980UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL1 (*((volatile unsigned int*)(0x42210984UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL2 (*((volatile unsigned int*)(0x42210988UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL3 (*((volatile unsigned int*)(0x4221098CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL4 (*((volatile unsigned int*)(0x42210990UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL5 (*((volatile unsigned int*)(0x42210994UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL6 (*((volatile unsigned int*)(0x42210998UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL7 (*((volatile unsigned int*)(0x4221099CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL8 (*((volatile unsigned int*)(0x422109A0UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN0 (*((volatile unsigned int*)(0x422109F8UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN1 (*((volatile unsigned int*)(0x422109FCUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210A00UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210A04UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210A08UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x42210A0CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210A10UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210A14UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210A18UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x42210A1CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210A20UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210A78UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210A7CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL0 (*((volatile unsigned int*)(0x42210A80UL))) +#define bM4_AOS_OTS_TRG_TRGSEL1 (*((volatile unsigned int*)(0x42210A84UL))) +#define bM4_AOS_OTS_TRG_TRGSEL2 (*((volatile unsigned int*)(0x42210A88UL))) +#define bM4_AOS_OTS_TRG_TRGSEL3 (*((volatile unsigned int*)(0x42210A8CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL4 (*((volatile unsigned int*)(0x42210A90UL))) +#define bM4_AOS_OTS_TRG_TRGSEL5 (*((volatile unsigned int*)(0x42210A94UL))) +#define bM4_AOS_OTS_TRG_TRGSEL6 (*((volatile unsigned int*)(0x42210A98UL))) +#define bM4_AOS_OTS_TRG_TRGSEL7 (*((volatile unsigned int*)(0x42210A9CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL8 (*((volatile unsigned int*)(0x42210AA0UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN0 (*((volatile unsigned int*)(0x42210AF8UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN1 (*((volatile unsigned int*)(0x42210AFCUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210B00UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210B04UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210B08UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210B0CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210B10UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210B14UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210B18UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210B1CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210B20UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210B78UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210B7CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210B80UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210B84UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210B88UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210B8CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210B90UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210B94UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210B98UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210B9CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210BA0UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210BF8UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210BFCUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210C00UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210C04UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210C08UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210C0CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210C10UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210C14UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210C18UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210C1CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210C20UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210C78UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210C7CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210C80UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210C84UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210C88UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210C8CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210C90UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210C94UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210C98UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210C9CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210CA0UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210CF8UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210CFCUL))) +#define bM4_AOS_COMTRG1_TRGSEL0 (*((volatile unsigned int*)(0x42210D00UL))) +#define bM4_AOS_COMTRG1_TRGSEL1 (*((volatile unsigned int*)(0x42210D04UL))) +#define bM4_AOS_COMTRG1_TRGSEL2 (*((volatile unsigned int*)(0x42210D08UL))) +#define bM4_AOS_COMTRG1_TRGSEL3 (*((volatile unsigned int*)(0x42210D0CUL))) +#define bM4_AOS_COMTRG1_TRGSEL4 (*((volatile unsigned int*)(0x42210D10UL))) +#define bM4_AOS_COMTRG1_TRGSEL5 (*((volatile unsigned int*)(0x42210D14UL))) +#define bM4_AOS_COMTRG1_TRGSEL6 (*((volatile unsigned int*)(0x42210D18UL))) +#define bM4_AOS_COMTRG1_TRGSEL7 (*((volatile unsigned int*)(0x42210D1CUL))) +#define bM4_AOS_COMTRG1_TRGSEL8 (*((volatile unsigned int*)(0x42210D20UL))) +#define bM4_AOS_COMTRG2_TRGSEL0 (*((volatile unsigned int*)(0x42210D80UL))) +#define bM4_AOS_COMTRG2_TRGSEL1 (*((volatile unsigned int*)(0x42210D84UL))) +#define bM4_AOS_COMTRG2_TRGSEL2 (*((volatile unsigned int*)(0x42210D88UL))) +#define bM4_AOS_COMTRG2_TRGSEL3 (*((volatile unsigned int*)(0x42210D8CUL))) +#define bM4_AOS_COMTRG2_TRGSEL4 (*((volatile unsigned int*)(0x42210D90UL))) +#define bM4_AOS_COMTRG2_TRGSEL5 (*((volatile unsigned int*)(0x42210D94UL))) +#define bM4_AOS_COMTRG2_TRGSEL6 (*((volatile unsigned int*)(0x42210D98UL))) +#define bM4_AOS_COMTRG2_TRGSEL7 (*((volatile unsigned int*)(0x42210D9CUL))) +#define bM4_AOS_COMTRG2_TRGSEL8 (*((volatile unsigned int*)(0x42210DA0UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR00 (*((volatile unsigned int*)(0x42212000UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR01 (*((volatile unsigned int*)(0x42212004UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR02 (*((volatile unsigned int*)(0x42212008UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR03 (*((volatile unsigned int*)(0x4221200CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR04 (*((volatile unsigned int*)(0x42212010UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR05 (*((volatile unsigned int*)(0x42212014UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR06 (*((volatile unsigned int*)(0x42212018UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR07 (*((volatile unsigned int*)(0x4221201CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR08 (*((volatile unsigned int*)(0x42212020UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR09 (*((volatile unsigned int*)(0x42212024UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR10 (*((volatile unsigned int*)(0x42212028UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR11 (*((volatile unsigned int*)(0x4221202CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR12 (*((volatile unsigned int*)(0x42212030UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR13 (*((volatile unsigned int*)(0x42212034UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR14 (*((volatile unsigned int*)(0x42212038UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR15 (*((volatile unsigned int*)(0x4221203CUL))) +#define bM4_AOS_PEVNTIDR1_PIN00 (*((volatile unsigned int*)(0x42212080UL))) +#define bM4_AOS_PEVNTIDR1_PIN01 (*((volatile unsigned int*)(0x42212084UL))) +#define bM4_AOS_PEVNTIDR1_PIN02 (*((volatile unsigned int*)(0x42212088UL))) +#define bM4_AOS_PEVNTIDR1_PIN03 (*((volatile unsigned int*)(0x4221208CUL))) +#define bM4_AOS_PEVNTIDR1_PIN04 (*((volatile unsigned int*)(0x42212090UL))) +#define bM4_AOS_PEVNTIDR1_PIN05 (*((volatile unsigned int*)(0x42212094UL))) +#define bM4_AOS_PEVNTIDR1_PIN06 (*((volatile unsigned int*)(0x42212098UL))) +#define bM4_AOS_PEVNTIDR1_PIN07 (*((volatile unsigned int*)(0x4221209CUL))) +#define bM4_AOS_PEVNTIDR1_PIN08 (*((volatile unsigned int*)(0x422120A0UL))) +#define bM4_AOS_PEVNTIDR1_PIN09 (*((volatile unsigned int*)(0x422120A4UL))) +#define bM4_AOS_PEVNTIDR1_PIN10 (*((volatile unsigned int*)(0x422120A8UL))) +#define bM4_AOS_PEVNTIDR1_PIN11 (*((volatile unsigned int*)(0x422120ACUL))) +#define bM4_AOS_PEVNTIDR1_PIN12 (*((volatile unsigned int*)(0x422120B0UL))) +#define bM4_AOS_PEVNTIDR1_PIN13 (*((volatile unsigned int*)(0x422120B4UL))) +#define bM4_AOS_PEVNTIDR1_PIN14 (*((volatile unsigned int*)(0x422120B8UL))) +#define bM4_AOS_PEVNTIDR1_PIN15 (*((volatile unsigned int*)(0x422120BCUL))) +#define bM4_AOS_PEVNTODR1_POUT00 (*((volatile unsigned int*)(0x42212100UL))) +#define bM4_AOS_PEVNTODR1_POUT01 (*((volatile unsigned int*)(0x42212104UL))) +#define bM4_AOS_PEVNTODR1_POUT02 (*((volatile unsigned int*)(0x42212108UL))) +#define bM4_AOS_PEVNTODR1_POUT03 (*((volatile unsigned int*)(0x4221210CUL))) +#define bM4_AOS_PEVNTODR1_POUT04 (*((volatile unsigned int*)(0x42212110UL))) +#define bM4_AOS_PEVNTODR1_POUT05 (*((volatile unsigned int*)(0x42212114UL))) +#define bM4_AOS_PEVNTODR1_POUT06 (*((volatile unsigned int*)(0x42212118UL))) +#define bM4_AOS_PEVNTODR1_POUT07 (*((volatile unsigned int*)(0x4221211CUL))) +#define bM4_AOS_PEVNTODR1_POUT08 (*((volatile unsigned int*)(0x42212120UL))) +#define bM4_AOS_PEVNTODR1_POUT09 (*((volatile unsigned int*)(0x42212124UL))) +#define bM4_AOS_PEVNTODR1_POUT10 (*((volatile unsigned int*)(0x42212128UL))) +#define bM4_AOS_PEVNTODR1_POUT11 (*((volatile unsigned int*)(0x4221212CUL))) +#define bM4_AOS_PEVNTODR1_POUT12 (*((volatile unsigned int*)(0x42212130UL))) +#define bM4_AOS_PEVNTODR1_POUT13 (*((volatile unsigned int*)(0x42212134UL))) +#define bM4_AOS_PEVNTODR1_POUT14 (*((volatile unsigned int*)(0x42212138UL))) +#define bM4_AOS_PEVNTODR1_POUT15 (*((volatile unsigned int*)(0x4221213CUL))) +#define bM4_AOS_PEVNTORR1_POR00 (*((volatile unsigned int*)(0x42212180UL))) +#define bM4_AOS_PEVNTORR1_POR01 (*((volatile unsigned int*)(0x42212184UL))) +#define bM4_AOS_PEVNTORR1_POR02 (*((volatile unsigned int*)(0x42212188UL))) +#define bM4_AOS_PEVNTORR1_POR03 (*((volatile unsigned int*)(0x4221218CUL))) +#define bM4_AOS_PEVNTORR1_POR04 (*((volatile unsigned int*)(0x42212190UL))) +#define bM4_AOS_PEVNTORR1_POR05 (*((volatile unsigned int*)(0x42212194UL))) +#define bM4_AOS_PEVNTORR1_POR06 (*((volatile unsigned int*)(0x42212198UL))) +#define bM4_AOS_PEVNTORR1_POR07 (*((volatile unsigned int*)(0x4221219CUL))) +#define bM4_AOS_PEVNTORR1_POR08 (*((volatile unsigned int*)(0x422121A0UL))) +#define bM4_AOS_PEVNTORR1_POR09 (*((volatile unsigned int*)(0x422121A4UL))) +#define bM4_AOS_PEVNTORR1_POR10 (*((volatile unsigned int*)(0x422121A8UL))) +#define bM4_AOS_PEVNTORR1_POR11 (*((volatile unsigned int*)(0x422121ACUL))) +#define bM4_AOS_PEVNTORR1_POR12 (*((volatile unsigned int*)(0x422121B0UL))) +#define bM4_AOS_PEVNTORR1_POR13 (*((volatile unsigned int*)(0x422121B4UL))) +#define bM4_AOS_PEVNTORR1_POR14 (*((volatile unsigned int*)(0x422121B8UL))) +#define bM4_AOS_PEVNTORR1_POR15 (*((volatile unsigned int*)(0x422121BCUL))) +#define bM4_AOS_PEVNTOSR1_POS00 (*((volatile unsigned int*)(0x42212200UL))) +#define bM4_AOS_PEVNTOSR1_POS01 (*((volatile unsigned int*)(0x42212204UL))) +#define bM4_AOS_PEVNTOSR1_POS02 (*((volatile unsigned int*)(0x42212208UL))) +#define bM4_AOS_PEVNTOSR1_POS03 (*((volatile unsigned int*)(0x4221220CUL))) +#define bM4_AOS_PEVNTOSR1_POS04 (*((volatile unsigned int*)(0x42212210UL))) +#define bM4_AOS_PEVNTOSR1_POS05 (*((volatile unsigned int*)(0x42212214UL))) +#define bM4_AOS_PEVNTOSR1_POS06 (*((volatile unsigned int*)(0x42212218UL))) +#define bM4_AOS_PEVNTOSR1_POS07 (*((volatile unsigned int*)(0x4221221CUL))) +#define bM4_AOS_PEVNTOSR1_POS08 (*((volatile unsigned int*)(0x42212220UL))) +#define bM4_AOS_PEVNTOSR1_POS09 (*((volatile unsigned int*)(0x42212224UL))) +#define bM4_AOS_PEVNTOSR1_POS10 (*((volatile unsigned int*)(0x42212228UL))) +#define bM4_AOS_PEVNTOSR1_POS11 (*((volatile unsigned int*)(0x4221222CUL))) +#define bM4_AOS_PEVNTOSR1_POS12 (*((volatile unsigned int*)(0x42212230UL))) +#define bM4_AOS_PEVNTOSR1_POS13 (*((volatile unsigned int*)(0x42212234UL))) +#define bM4_AOS_PEVNTOSR1_POS14 (*((volatile unsigned int*)(0x42212238UL))) +#define bM4_AOS_PEVNTOSR1_POS15 (*((volatile unsigned int*)(0x4221223CUL))) +#define bM4_AOS_PEVNTRISR1_RIS00 (*((volatile unsigned int*)(0x42212280UL))) +#define bM4_AOS_PEVNTRISR1_RIS01 (*((volatile unsigned int*)(0x42212284UL))) +#define bM4_AOS_PEVNTRISR1_RIS02 (*((volatile unsigned int*)(0x42212288UL))) +#define bM4_AOS_PEVNTRISR1_RIS03 (*((volatile unsigned int*)(0x4221228CUL))) +#define bM4_AOS_PEVNTRISR1_RIS04 (*((volatile unsigned int*)(0x42212290UL))) +#define bM4_AOS_PEVNTRISR1_RIS05 (*((volatile unsigned int*)(0x42212294UL))) +#define bM4_AOS_PEVNTRISR1_RIS06 (*((volatile unsigned int*)(0x42212298UL))) +#define bM4_AOS_PEVNTRISR1_RIS07 (*((volatile unsigned int*)(0x4221229CUL))) +#define bM4_AOS_PEVNTRISR1_RIS08 (*((volatile unsigned int*)(0x422122A0UL))) +#define bM4_AOS_PEVNTRISR1_RIS09 (*((volatile unsigned int*)(0x422122A4UL))) +#define bM4_AOS_PEVNTRISR1_RIS10 (*((volatile unsigned int*)(0x422122A8UL))) +#define bM4_AOS_PEVNTRISR1_RIS11 (*((volatile unsigned int*)(0x422122ACUL))) +#define bM4_AOS_PEVNTRISR1_RIS12 (*((volatile unsigned int*)(0x422122B0UL))) +#define bM4_AOS_PEVNTRISR1_RIS13 (*((volatile unsigned int*)(0x422122B4UL))) +#define bM4_AOS_PEVNTRISR1_RIS14 (*((volatile unsigned int*)(0x422122B8UL))) +#define bM4_AOS_PEVNTRISR1_RIS15 (*((volatile unsigned int*)(0x422122BCUL))) +#define bM4_AOS_PEVNTFAL1_FAL00 (*((volatile unsigned int*)(0x42212300UL))) +#define bM4_AOS_PEVNTFAL1_FAL01 (*((volatile unsigned int*)(0x42212304UL))) +#define bM4_AOS_PEVNTFAL1_FAL02 (*((volatile unsigned int*)(0x42212308UL))) +#define bM4_AOS_PEVNTFAL1_FAL03 (*((volatile unsigned int*)(0x4221230CUL))) +#define bM4_AOS_PEVNTFAL1_FAL04 (*((volatile unsigned int*)(0x42212310UL))) +#define bM4_AOS_PEVNTFAL1_FAL05 (*((volatile unsigned int*)(0x42212314UL))) +#define bM4_AOS_PEVNTFAL1_FAL06 (*((volatile unsigned int*)(0x42212318UL))) +#define bM4_AOS_PEVNTFAL1_FAL07 (*((volatile unsigned int*)(0x4221231CUL))) +#define bM4_AOS_PEVNTFAL1_FAL08 (*((volatile unsigned int*)(0x42212320UL))) +#define bM4_AOS_PEVNTFAL1_FAL09 (*((volatile unsigned int*)(0x42212324UL))) +#define bM4_AOS_PEVNTFAL1_FAL10 (*((volatile unsigned int*)(0x42212328UL))) +#define bM4_AOS_PEVNTFAL1_FAL11 (*((volatile unsigned int*)(0x4221232CUL))) +#define bM4_AOS_PEVNTFAL1_FAL12 (*((volatile unsigned int*)(0x42212330UL))) +#define bM4_AOS_PEVNTFAL1_FAL13 (*((volatile unsigned int*)(0x42212334UL))) +#define bM4_AOS_PEVNTFAL1_FAL14 (*((volatile unsigned int*)(0x42212338UL))) +#define bM4_AOS_PEVNTFAL1_FAL15 (*((volatile unsigned int*)(0x4221233CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR00 (*((volatile unsigned int*)(0x42212380UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR01 (*((volatile unsigned int*)(0x42212384UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR02 (*((volatile unsigned int*)(0x42212388UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR03 (*((volatile unsigned int*)(0x4221238CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR04 (*((volatile unsigned int*)(0x42212390UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR05 (*((volatile unsigned int*)(0x42212394UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR06 (*((volatile unsigned int*)(0x42212398UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR07 (*((volatile unsigned int*)(0x4221239CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR08 (*((volatile unsigned int*)(0x422123A0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR09 (*((volatile unsigned int*)(0x422123A4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR10 (*((volatile unsigned int*)(0x422123A8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR11 (*((volatile unsigned int*)(0x422123ACUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR12 (*((volatile unsigned int*)(0x422123B0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR13 (*((volatile unsigned int*)(0x422123B4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR14 (*((volatile unsigned int*)(0x422123B8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR15 (*((volatile unsigned int*)(0x422123BCUL))) +#define bM4_AOS_PEVNTIDR2_PIN00 (*((volatile unsigned int*)(0x42212400UL))) +#define bM4_AOS_PEVNTIDR2_PIN01 (*((volatile unsigned int*)(0x42212404UL))) +#define bM4_AOS_PEVNTIDR2_PIN02 (*((volatile unsigned int*)(0x42212408UL))) +#define bM4_AOS_PEVNTIDR2_PIN03 (*((volatile unsigned int*)(0x4221240CUL))) +#define bM4_AOS_PEVNTIDR2_PIN04 (*((volatile unsigned int*)(0x42212410UL))) +#define bM4_AOS_PEVNTIDR2_PIN05 (*((volatile unsigned int*)(0x42212414UL))) +#define bM4_AOS_PEVNTIDR2_PIN06 (*((volatile unsigned int*)(0x42212418UL))) +#define bM4_AOS_PEVNTIDR2_PIN07 (*((volatile unsigned int*)(0x4221241CUL))) +#define bM4_AOS_PEVNTIDR2_PIN08 (*((volatile unsigned int*)(0x42212420UL))) +#define bM4_AOS_PEVNTIDR2_PIN09 (*((volatile unsigned int*)(0x42212424UL))) +#define bM4_AOS_PEVNTIDR2_PIN10 (*((volatile unsigned int*)(0x42212428UL))) +#define bM4_AOS_PEVNTIDR2_PIN11 (*((volatile unsigned int*)(0x4221242CUL))) +#define bM4_AOS_PEVNTIDR2_PIN12 (*((volatile unsigned int*)(0x42212430UL))) +#define bM4_AOS_PEVNTIDR2_PIN13 (*((volatile unsigned int*)(0x42212434UL))) +#define bM4_AOS_PEVNTIDR2_PIN14 (*((volatile unsigned int*)(0x42212438UL))) +#define bM4_AOS_PEVNTIDR2_PIN15 (*((volatile unsigned int*)(0x4221243CUL))) +#define bM4_AOS_PEVNTODR2_POUT00 (*((volatile unsigned int*)(0x42212480UL))) +#define bM4_AOS_PEVNTODR2_POUT01 (*((volatile unsigned int*)(0x42212484UL))) +#define bM4_AOS_PEVNTODR2_POUT02 (*((volatile unsigned int*)(0x42212488UL))) +#define bM4_AOS_PEVNTODR2_POUT03 (*((volatile unsigned int*)(0x4221248CUL))) +#define bM4_AOS_PEVNTODR2_POUT04 (*((volatile unsigned int*)(0x42212490UL))) +#define bM4_AOS_PEVNTODR2_POUT05 (*((volatile unsigned int*)(0x42212494UL))) +#define bM4_AOS_PEVNTODR2_POUT06 (*((volatile unsigned int*)(0x42212498UL))) +#define bM4_AOS_PEVNTODR2_POUT07 (*((volatile unsigned int*)(0x4221249CUL))) +#define bM4_AOS_PEVNTODR2_POUT08 (*((volatile unsigned int*)(0x422124A0UL))) +#define bM4_AOS_PEVNTODR2_POUT09 (*((volatile unsigned int*)(0x422124A4UL))) +#define bM4_AOS_PEVNTODR2_POUT10 (*((volatile unsigned int*)(0x422124A8UL))) +#define bM4_AOS_PEVNTODR2_POUT11 (*((volatile unsigned int*)(0x422124ACUL))) +#define bM4_AOS_PEVNTODR2_POUT12 (*((volatile unsigned int*)(0x422124B0UL))) +#define bM4_AOS_PEVNTODR2_POUT13 (*((volatile unsigned int*)(0x422124B4UL))) +#define bM4_AOS_PEVNTODR2_POUT14 (*((volatile unsigned int*)(0x422124B8UL))) +#define bM4_AOS_PEVNTODR2_POUT15 (*((volatile unsigned int*)(0x422124BCUL))) +#define bM4_AOS_PEVNTORR2_POR00 (*((volatile unsigned int*)(0x42212500UL))) +#define bM4_AOS_PEVNTORR2_POR01 (*((volatile unsigned int*)(0x42212504UL))) +#define bM4_AOS_PEVNTORR2_POR02 (*((volatile unsigned int*)(0x42212508UL))) +#define bM4_AOS_PEVNTORR2_POR03 (*((volatile unsigned int*)(0x4221250CUL))) +#define bM4_AOS_PEVNTORR2_POR04 (*((volatile unsigned int*)(0x42212510UL))) +#define bM4_AOS_PEVNTORR2_POR05 (*((volatile unsigned int*)(0x42212514UL))) +#define bM4_AOS_PEVNTORR2_POR06 (*((volatile unsigned int*)(0x42212518UL))) +#define bM4_AOS_PEVNTORR2_POR07 (*((volatile unsigned int*)(0x4221251CUL))) +#define bM4_AOS_PEVNTORR2_POR08 (*((volatile unsigned int*)(0x42212520UL))) +#define bM4_AOS_PEVNTORR2_POR09 (*((volatile unsigned int*)(0x42212524UL))) +#define bM4_AOS_PEVNTORR2_POR10 (*((volatile unsigned int*)(0x42212528UL))) +#define bM4_AOS_PEVNTORR2_POR11 (*((volatile unsigned int*)(0x4221252CUL))) +#define bM4_AOS_PEVNTORR2_POR12 (*((volatile unsigned int*)(0x42212530UL))) +#define bM4_AOS_PEVNTORR2_POR13 (*((volatile unsigned int*)(0x42212534UL))) +#define bM4_AOS_PEVNTORR2_POR14 (*((volatile unsigned int*)(0x42212538UL))) +#define bM4_AOS_PEVNTORR2_POR15 (*((volatile unsigned int*)(0x4221253CUL))) +#define bM4_AOS_PEVNTOSR2_POS00 (*((volatile unsigned int*)(0x42212580UL))) +#define bM4_AOS_PEVNTOSR2_POS01 (*((volatile unsigned int*)(0x42212584UL))) +#define bM4_AOS_PEVNTOSR2_POS02 (*((volatile unsigned int*)(0x42212588UL))) +#define bM4_AOS_PEVNTOSR2_POS03 (*((volatile unsigned int*)(0x4221258CUL))) +#define bM4_AOS_PEVNTOSR2_POS04 (*((volatile unsigned int*)(0x42212590UL))) +#define bM4_AOS_PEVNTOSR2_POS05 (*((volatile unsigned int*)(0x42212594UL))) +#define bM4_AOS_PEVNTOSR2_POS06 (*((volatile unsigned int*)(0x42212598UL))) +#define bM4_AOS_PEVNTOSR2_POS07 (*((volatile unsigned int*)(0x4221259CUL))) +#define bM4_AOS_PEVNTOSR2_POS08 (*((volatile unsigned int*)(0x422125A0UL))) +#define bM4_AOS_PEVNTOSR2_POS09 (*((volatile unsigned int*)(0x422125A4UL))) +#define bM4_AOS_PEVNTOSR2_POS10 (*((volatile unsigned int*)(0x422125A8UL))) +#define bM4_AOS_PEVNTOSR2_POS11 (*((volatile unsigned int*)(0x422125ACUL))) +#define bM4_AOS_PEVNTOSR2_POS12 (*((volatile unsigned int*)(0x422125B0UL))) +#define bM4_AOS_PEVNTOSR2_POS13 (*((volatile unsigned int*)(0x422125B4UL))) +#define bM4_AOS_PEVNTOSR2_POS14 (*((volatile unsigned int*)(0x422125B8UL))) +#define bM4_AOS_PEVNTOSR2_POS15 (*((volatile unsigned int*)(0x422125BCUL))) +#define bM4_AOS_PEVNTRISR2_RIS00 (*((volatile unsigned int*)(0x42212600UL))) +#define bM4_AOS_PEVNTRISR2_RIS01 (*((volatile unsigned int*)(0x42212604UL))) +#define bM4_AOS_PEVNTRISR2_RIS02 (*((volatile unsigned int*)(0x42212608UL))) +#define bM4_AOS_PEVNTRISR2_RIS03 (*((volatile unsigned int*)(0x4221260CUL))) +#define bM4_AOS_PEVNTRISR2_RIS04 (*((volatile unsigned int*)(0x42212610UL))) +#define bM4_AOS_PEVNTRISR2_RIS05 (*((volatile unsigned int*)(0x42212614UL))) +#define bM4_AOS_PEVNTRISR2_RIS06 (*((volatile unsigned int*)(0x42212618UL))) +#define bM4_AOS_PEVNTRISR2_RIS07 (*((volatile unsigned int*)(0x4221261CUL))) +#define bM4_AOS_PEVNTRISR2_RIS08 (*((volatile unsigned int*)(0x42212620UL))) +#define bM4_AOS_PEVNTRISR2_RIS09 (*((volatile unsigned int*)(0x42212624UL))) +#define bM4_AOS_PEVNTRISR2_RIS10 (*((volatile unsigned int*)(0x42212628UL))) +#define bM4_AOS_PEVNTRISR2_RIS11 (*((volatile unsigned int*)(0x4221262CUL))) +#define bM4_AOS_PEVNTRISR2_RIS12 (*((volatile unsigned int*)(0x42212630UL))) +#define bM4_AOS_PEVNTRISR2_RIS13 (*((volatile unsigned int*)(0x42212634UL))) +#define bM4_AOS_PEVNTRISR2_RIS14 (*((volatile unsigned int*)(0x42212638UL))) +#define bM4_AOS_PEVNTRISR2_RIS15 (*((volatile unsigned int*)(0x4221263CUL))) +#define bM4_AOS_PEVNTFAL2_FAL00 (*((volatile unsigned int*)(0x42212680UL))) +#define bM4_AOS_PEVNTFAL2_FAL01 (*((volatile unsigned int*)(0x42212684UL))) +#define bM4_AOS_PEVNTFAL2_FAL02 (*((volatile unsigned int*)(0x42212688UL))) +#define bM4_AOS_PEVNTFAL2_FAL03 (*((volatile unsigned int*)(0x4221268CUL))) +#define bM4_AOS_PEVNTFAL2_FAL04 (*((volatile unsigned int*)(0x42212690UL))) +#define bM4_AOS_PEVNTFAL2_FAL05 (*((volatile unsigned int*)(0x42212694UL))) +#define bM4_AOS_PEVNTFAL2_FAL06 (*((volatile unsigned int*)(0x42212698UL))) +#define bM4_AOS_PEVNTFAL2_FAL07 (*((volatile unsigned int*)(0x4221269CUL))) +#define bM4_AOS_PEVNTFAL2_FAL08 (*((volatile unsigned int*)(0x422126A0UL))) +#define bM4_AOS_PEVNTFAL2_FAL09 (*((volatile unsigned int*)(0x422126A4UL))) +#define bM4_AOS_PEVNTFAL2_FAL10 (*((volatile unsigned int*)(0x422126A8UL))) +#define bM4_AOS_PEVNTFAL2_FAL11 (*((volatile unsigned int*)(0x422126ACUL))) +#define bM4_AOS_PEVNTFAL2_FAL12 (*((volatile unsigned int*)(0x422126B0UL))) +#define bM4_AOS_PEVNTFAL2_FAL13 (*((volatile unsigned int*)(0x422126B4UL))) +#define bM4_AOS_PEVNTFAL2_FAL14 (*((volatile unsigned int*)(0x422126B8UL))) +#define bM4_AOS_PEVNTFAL2_FAL15 (*((volatile unsigned int*)(0x422126BCUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR00 (*((volatile unsigned int*)(0x42212700UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR01 (*((volatile unsigned int*)(0x42212704UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR02 (*((volatile unsigned int*)(0x42212708UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR03 (*((volatile unsigned int*)(0x4221270CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR04 (*((volatile unsigned int*)(0x42212710UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR05 (*((volatile unsigned int*)(0x42212714UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR06 (*((volatile unsigned int*)(0x42212718UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR07 (*((volatile unsigned int*)(0x4221271CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR08 (*((volatile unsigned int*)(0x42212720UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR09 (*((volatile unsigned int*)(0x42212724UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR10 (*((volatile unsigned int*)(0x42212728UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR11 (*((volatile unsigned int*)(0x4221272CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR12 (*((volatile unsigned int*)(0x42212730UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR13 (*((volatile unsigned int*)(0x42212734UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR14 (*((volatile unsigned int*)(0x42212738UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR15 (*((volatile unsigned int*)(0x4221273CUL))) +#define bM4_AOS_PEVNTIDR3_PIN00 (*((volatile unsigned int*)(0x42212780UL))) +#define bM4_AOS_PEVNTIDR3_PIN01 (*((volatile unsigned int*)(0x42212784UL))) +#define bM4_AOS_PEVNTIDR3_PIN02 (*((volatile unsigned int*)(0x42212788UL))) +#define bM4_AOS_PEVNTIDR3_PIN03 (*((volatile unsigned int*)(0x4221278CUL))) +#define bM4_AOS_PEVNTIDR3_PIN04 (*((volatile unsigned int*)(0x42212790UL))) +#define bM4_AOS_PEVNTIDR3_PIN05 (*((volatile unsigned int*)(0x42212794UL))) +#define bM4_AOS_PEVNTIDR3_PIN06 (*((volatile unsigned int*)(0x42212798UL))) +#define bM4_AOS_PEVNTIDR3_PIN07 (*((volatile unsigned int*)(0x4221279CUL))) +#define bM4_AOS_PEVNTIDR3_PIN08 (*((volatile unsigned int*)(0x422127A0UL))) +#define bM4_AOS_PEVNTIDR3_PIN09 (*((volatile unsigned int*)(0x422127A4UL))) +#define bM4_AOS_PEVNTIDR3_PIN10 (*((volatile unsigned int*)(0x422127A8UL))) +#define bM4_AOS_PEVNTIDR3_PIN11 (*((volatile unsigned int*)(0x422127ACUL))) +#define bM4_AOS_PEVNTIDR3_PIN12 (*((volatile unsigned int*)(0x422127B0UL))) +#define bM4_AOS_PEVNTIDR3_PIN13 (*((volatile unsigned int*)(0x422127B4UL))) +#define bM4_AOS_PEVNTIDR3_PIN14 (*((volatile unsigned int*)(0x422127B8UL))) +#define bM4_AOS_PEVNTIDR3_PIN15 (*((volatile unsigned int*)(0x422127BCUL))) +#define bM4_AOS_PEVNTODR3_POUT00 (*((volatile unsigned int*)(0x42212800UL))) +#define bM4_AOS_PEVNTODR3_POUT01 (*((volatile unsigned int*)(0x42212804UL))) +#define bM4_AOS_PEVNTODR3_POUT02 (*((volatile unsigned int*)(0x42212808UL))) +#define bM4_AOS_PEVNTODR3_POUT03 (*((volatile unsigned int*)(0x4221280CUL))) +#define bM4_AOS_PEVNTODR3_POUT04 (*((volatile unsigned int*)(0x42212810UL))) +#define bM4_AOS_PEVNTODR3_POUT05 (*((volatile unsigned int*)(0x42212814UL))) +#define bM4_AOS_PEVNTODR3_POUT06 (*((volatile unsigned int*)(0x42212818UL))) +#define bM4_AOS_PEVNTODR3_POUT07 (*((volatile unsigned int*)(0x4221281CUL))) +#define bM4_AOS_PEVNTODR3_POUT08 (*((volatile unsigned int*)(0x42212820UL))) +#define bM4_AOS_PEVNTODR3_POUT09 (*((volatile unsigned int*)(0x42212824UL))) +#define bM4_AOS_PEVNTODR3_POUT10 (*((volatile unsigned int*)(0x42212828UL))) +#define bM4_AOS_PEVNTODR3_POUT11 (*((volatile unsigned int*)(0x4221282CUL))) +#define bM4_AOS_PEVNTODR3_POUT12 (*((volatile unsigned int*)(0x42212830UL))) +#define bM4_AOS_PEVNTODR3_POUT13 (*((volatile unsigned int*)(0x42212834UL))) +#define bM4_AOS_PEVNTODR3_POUT14 (*((volatile unsigned int*)(0x42212838UL))) +#define bM4_AOS_PEVNTODR3_POUT15 (*((volatile unsigned int*)(0x4221283CUL))) +#define bM4_AOS_PEVNTORR3_POR00 (*((volatile unsigned int*)(0x42212880UL))) +#define bM4_AOS_PEVNTORR3_POR01 (*((volatile unsigned int*)(0x42212884UL))) +#define bM4_AOS_PEVNTORR3_POR02 (*((volatile unsigned int*)(0x42212888UL))) +#define bM4_AOS_PEVNTORR3_POR03 (*((volatile unsigned int*)(0x4221288CUL))) +#define bM4_AOS_PEVNTORR3_POR04 (*((volatile unsigned int*)(0x42212890UL))) +#define bM4_AOS_PEVNTORR3_POR05 (*((volatile unsigned int*)(0x42212894UL))) +#define bM4_AOS_PEVNTORR3_POR06 (*((volatile unsigned int*)(0x42212898UL))) +#define bM4_AOS_PEVNTORR3_POR07 (*((volatile unsigned int*)(0x4221289CUL))) +#define bM4_AOS_PEVNTORR3_POR08 (*((volatile unsigned int*)(0x422128A0UL))) +#define bM4_AOS_PEVNTORR3_POR09 (*((volatile unsigned int*)(0x422128A4UL))) +#define bM4_AOS_PEVNTORR3_POR10 (*((volatile unsigned int*)(0x422128A8UL))) +#define bM4_AOS_PEVNTORR3_POR11 (*((volatile unsigned int*)(0x422128ACUL))) +#define bM4_AOS_PEVNTORR3_POR12 (*((volatile unsigned int*)(0x422128B0UL))) +#define bM4_AOS_PEVNTORR3_POR13 (*((volatile unsigned int*)(0x422128B4UL))) +#define bM4_AOS_PEVNTORR3_POR14 (*((volatile unsigned int*)(0x422128B8UL))) +#define bM4_AOS_PEVNTORR3_POR15 (*((volatile unsigned int*)(0x422128BCUL))) +#define bM4_AOS_PEVNTOSR3_POS00 (*((volatile unsigned int*)(0x42212900UL))) +#define bM4_AOS_PEVNTOSR3_POS01 (*((volatile unsigned int*)(0x42212904UL))) +#define bM4_AOS_PEVNTOSR3_POS02 (*((volatile unsigned int*)(0x42212908UL))) +#define bM4_AOS_PEVNTOSR3_POS03 (*((volatile unsigned int*)(0x4221290CUL))) +#define bM4_AOS_PEVNTOSR3_POS04 (*((volatile unsigned int*)(0x42212910UL))) +#define bM4_AOS_PEVNTOSR3_POS05 (*((volatile unsigned int*)(0x42212914UL))) +#define bM4_AOS_PEVNTOSR3_POS06 (*((volatile unsigned int*)(0x42212918UL))) +#define bM4_AOS_PEVNTOSR3_POS07 (*((volatile unsigned int*)(0x4221291CUL))) +#define bM4_AOS_PEVNTOSR3_POS08 (*((volatile unsigned int*)(0x42212920UL))) +#define bM4_AOS_PEVNTOSR3_POS09 (*((volatile unsigned int*)(0x42212924UL))) +#define bM4_AOS_PEVNTOSR3_POS10 (*((volatile unsigned int*)(0x42212928UL))) +#define bM4_AOS_PEVNTOSR3_POS11 (*((volatile unsigned int*)(0x4221292CUL))) +#define bM4_AOS_PEVNTOSR3_POS12 (*((volatile unsigned int*)(0x42212930UL))) +#define bM4_AOS_PEVNTOSR3_POS13 (*((volatile unsigned int*)(0x42212934UL))) +#define bM4_AOS_PEVNTOSR3_POS14 (*((volatile unsigned int*)(0x42212938UL))) +#define bM4_AOS_PEVNTOSR3_POS15 (*((volatile unsigned int*)(0x4221293CUL))) +#define bM4_AOS_PEVNTRISR3_RIS00 (*((volatile unsigned int*)(0x42212980UL))) +#define bM4_AOS_PEVNTRISR3_RIS01 (*((volatile unsigned int*)(0x42212984UL))) +#define bM4_AOS_PEVNTRISR3_RIS02 (*((volatile unsigned int*)(0x42212988UL))) +#define bM4_AOS_PEVNTRISR3_RIS03 (*((volatile unsigned int*)(0x4221298CUL))) +#define bM4_AOS_PEVNTRISR3_RIS04 (*((volatile unsigned int*)(0x42212990UL))) +#define bM4_AOS_PEVNTRISR3_RIS05 (*((volatile unsigned int*)(0x42212994UL))) +#define bM4_AOS_PEVNTRISR3_RIS06 (*((volatile unsigned int*)(0x42212998UL))) +#define bM4_AOS_PEVNTRISR3_RIS07 (*((volatile unsigned int*)(0x4221299CUL))) +#define bM4_AOS_PEVNTRISR3_RIS08 (*((volatile unsigned int*)(0x422129A0UL))) +#define bM4_AOS_PEVNTRISR3_RIS09 (*((volatile unsigned int*)(0x422129A4UL))) +#define bM4_AOS_PEVNTRISR3_RIS10 (*((volatile unsigned int*)(0x422129A8UL))) +#define bM4_AOS_PEVNTRISR3_RIS11 (*((volatile unsigned int*)(0x422129ACUL))) +#define bM4_AOS_PEVNTRISR3_RIS12 (*((volatile unsigned int*)(0x422129B0UL))) +#define bM4_AOS_PEVNTRISR3_RIS13 (*((volatile unsigned int*)(0x422129B4UL))) +#define bM4_AOS_PEVNTRISR3_RIS14 (*((volatile unsigned int*)(0x422129B8UL))) +#define bM4_AOS_PEVNTRISR3_RIS15 (*((volatile unsigned int*)(0x422129BCUL))) +#define bM4_AOS_PEVNTFAL3_FAL00 (*((volatile unsigned int*)(0x42212A00UL))) +#define bM4_AOS_PEVNTFAL3_FAL01 (*((volatile unsigned int*)(0x42212A04UL))) +#define bM4_AOS_PEVNTFAL3_FAL02 (*((volatile unsigned int*)(0x42212A08UL))) +#define bM4_AOS_PEVNTFAL3_FAL03 (*((volatile unsigned int*)(0x42212A0CUL))) +#define bM4_AOS_PEVNTFAL3_FAL04 (*((volatile unsigned int*)(0x42212A10UL))) +#define bM4_AOS_PEVNTFAL3_FAL05 (*((volatile unsigned int*)(0x42212A14UL))) +#define bM4_AOS_PEVNTFAL3_FAL06 (*((volatile unsigned int*)(0x42212A18UL))) +#define bM4_AOS_PEVNTFAL3_FAL07 (*((volatile unsigned int*)(0x42212A1CUL))) +#define bM4_AOS_PEVNTFAL3_FAL08 (*((volatile unsigned int*)(0x42212A20UL))) +#define bM4_AOS_PEVNTFAL3_FAL09 (*((volatile unsigned int*)(0x42212A24UL))) +#define bM4_AOS_PEVNTFAL3_FAL10 (*((volatile unsigned int*)(0x42212A28UL))) +#define bM4_AOS_PEVNTFAL3_FAL11 (*((volatile unsigned int*)(0x42212A2CUL))) +#define bM4_AOS_PEVNTFAL3_FAL12 (*((volatile unsigned int*)(0x42212A30UL))) +#define bM4_AOS_PEVNTFAL3_FAL13 (*((volatile unsigned int*)(0x42212A34UL))) +#define bM4_AOS_PEVNTFAL3_FAL14 (*((volatile unsigned int*)(0x42212A38UL))) +#define bM4_AOS_PEVNTFAL3_FAL15 (*((volatile unsigned int*)(0x42212A3CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR00 (*((volatile unsigned int*)(0x42212A80UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR01 (*((volatile unsigned int*)(0x42212A84UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR02 (*((volatile unsigned int*)(0x42212A88UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR03 (*((volatile unsigned int*)(0x42212A8CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR04 (*((volatile unsigned int*)(0x42212A90UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR05 (*((volatile unsigned int*)(0x42212A94UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR06 (*((volatile unsigned int*)(0x42212A98UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR07 (*((volatile unsigned int*)(0x42212A9CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR08 (*((volatile unsigned int*)(0x42212AA0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR09 (*((volatile unsigned int*)(0x42212AA4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR10 (*((volatile unsigned int*)(0x42212AA8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR11 (*((volatile unsigned int*)(0x42212AACUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR12 (*((volatile unsigned int*)(0x42212AB0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR13 (*((volatile unsigned int*)(0x42212AB4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR14 (*((volatile unsigned int*)(0x42212AB8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR15 (*((volatile unsigned int*)(0x42212ABCUL))) +#define bM4_AOS_PEVNTIDR4_PIN00 (*((volatile unsigned int*)(0x42212B00UL))) +#define bM4_AOS_PEVNTIDR4_PIN01 (*((volatile unsigned int*)(0x42212B04UL))) +#define bM4_AOS_PEVNTIDR4_PIN02 (*((volatile unsigned int*)(0x42212B08UL))) +#define bM4_AOS_PEVNTIDR4_PIN03 (*((volatile unsigned int*)(0x42212B0CUL))) +#define bM4_AOS_PEVNTIDR4_PIN04 (*((volatile unsigned int*)(0x42212B10UL))) +#define bM4_AOS_PEVNTIDR4_PIN05 (*((volatile unsigned int*)(0x42212B14UL))) +#define bM4_AOS_PEVNTIDR4_PIN06 (*((volatile unsigned int*)(0x42212B18UL))) +#define bM4_AOS_PEVNTIDR4_PIN07 (*((volatile unsigned int*)(0x42212B1CUL))) +#define bM4_AOS_PEVNTIDR4_PIN08 (*((volatile unsigned int*)(0x42212B20UL))) +#define bM4_AOS_PEVNTIDR4_PIN09 (*((volatile unsigned int*)(0x42212B24UL))) +#define bM4_AOS_PEVNTIDR4_PIN10 (*((volatile unsigned int*)(0x42212B28UL))) +#define bM4_AOS_PEVNTIDR4_PIN11 (*((volatile unsigned int*)(0x42212B2CUL))) +#define bM4_AOS_PEVNTIDR4_PIN12 (*((volatile unsigned int*)(0x42212B30UL))) +#define bM4_AOS_PEVNTIDR4_PIN13 (*((volatile unsigned int*)(0x42212B34UL))) +#define bM4_AOS_PEVNTIDR4_PIN14 (*((volatile unsigned int*)(0x42212B38UL))) +#define bM4_AOS_PEVNTIDR4_PIN15 (*((volatile unsigned int*)(0x42212B3CUL))) +#define bM4_AOS_PEVNTODR4_POUT00 (*((volatile unsigned int*)(0x42212B80UL))) +#define bM4_AOS_PEVNTODR4_POUT01 (*((volatile unsigned int*)(0x42212B84UL))) +#define bM4_AOS_PEVNTODR4_POUT02 (*((volatile unsigned int*)(0x42212B88UL))) +#define bM4_AOS_PEVNTODR4_POUT03 (*((volatile unsigned int*)(0x42212B8CUL))) +#define bM4_AOS_PEVNTODR4_POUT04 (*((volatile unsigned int*)(0x42212B90UL))) +#define bM4_AOS_PEVNTODR4_POUT05 (*((volatile unsigned int*)(0x42212B94UL))) +#define bM4_AOS_PEVNTODR4_POUT06 (*((volatile unsigned int*)(0x42212B98UL))) +#define bM4_AOS_PEVNTODR4_POUT07 (*((volatile unsigned int*)(0x42212B9CUL))) +#define bM4_AOS_PEVNTODR4_POUT08 (*((volatile unsigned int*)(0x42212BA0UL))) +#define bM4_AOS_PEVNTODR4_POUT09 (*((volatile unsigned int*)(0x42212BA4UL))) +#define bM4_AOS_PEVNTODR4_POUT10 (*((volatile unsigned int*)(0x42212BA8UL))) +#define bM4_AOS_PEVNTODR4_POUT11 (*((volatile unsigned int*)(0x42212BACUL))) +#define bM4_AOS_PEVNTODR4_POUT12 (*((volatile unsigned int*)(0x42212BB0UL))) +#define bM4_AOS_PEVNTODR4_POUT13 (*((volatile unsigned int*)(0x42212BB4UL))) +#define bM4_AOS_PEVNTODR4_POUT14 (*((volatile unsigned int*)(0x42212BB8UL))) +#define bM4_AOS_PEVNTODR4_POUT15 (*((volatile unsigned int*)(0x42212BBCUL))) +#define bM4_AOS_PEVNTORR4_POR00 (*((volatile unsigned int*)(0x42212C00UL))) +#define bM4_AOS_PEVNTORR4_POR01 (*((volatile unsigned int*)(0x42212C04UL))) +#define bM4_AOS_PEVNTORR4_POR02 (*((volatile unsigned int*)(0x42212C08UL))) +#define bM4_AOS_PEVNTORR4_POR03 (*((volatile unsigned int*)(0x42212C0CUL))) +#define bM4_AOS_PEVNTORR4_POR04 (*((volatile unsigned int*)(0x42212C10UL))) +#define bM4_AOS_PEVNTORR4_POR05 (*((volatile unsigned int*)(0x42212C14UL))) +#define bM4_AOS_PEVNTORR4_POR06 (*((volatile unsigned int*)(0x42212C18UL))) +#define bM4_AOS_PEVNTORR4_POR07 (*((volatile unsigned int*)(0x42212C1CUL))) +#define bM4_AOS_PEVNTORR4_POR08 (*((volatile unsigned int*)(0x42212C20UL))) +#define bM4_AOS_PEVNTORR4_POR09 (*((volatile unsigned int*)(0x42212C24UL))) +#define bM4_AOS_PEVNTORR4_POR10 (*((volatile unsigned int*)(0x42212C28UL))) +#define bM4_AOS_PEVNTORR4_POR11 (*((volatile unsigned int*)(0x42212C2CUL))) +#define bM4_AOS_PEVNTORR4_POR12 (*((volatile unsigned int*)(0x42212C30UL))) +#define bM4_AOS_PEVNTORR4_POR13 (*((volatile unsigned int*)(0x42212C34UL))) +#define bM4_AOS_PEVNTORR4_POR14 (*((volatile unsigned int*)(0x42212C38UL))) +#define bM4_AOS_PEVNTORR4_POR15 (*((volatile unsigned int*)(0x42212C3CUL))) +#define bM4_AOS_PEVNTOSR4_POS00 (*((volatile unsigned int*)(0x42212C80UL))) +#define bM4_AOS_PEVNTOSR4_POS01 (*((volatile unsigned int*)(0x42212C84UL))) +#define bM4_AOS_PEVNTOSR4_POS02 (*((volatile unsigned int*)(0x42212C88UL))) +#define bM4_AOS_PEVNTOSR4_POS03 (*((volatile unsigned int*)(0x42212C8CUL))) +#define bM4_AOS_PEVNTOSR4_POS04 (*((volatile unsigned int*)(0x42212C90UL))) +#define bM4_AOS_PEVNTOSR4_POS05 (*((volatile unsigned int*)(0x42212C94UL))) +#define bM4_AOS_PEVNTOSR4_POS06 (*((volatile unsigned int*)(0x42212C98UL))) +#define bM4_AOS_PEVNTOSR4_POS07 (*((volatile unsigned int*)(0x42212C9CUL))) +#define bM4_AOS_PEVNTOSR4_POS08 (*((volatile unsigned int*)(0x42212CA0UL))) +#define bM4_AOS_PEVNTOSR4_POS09 (*((volatile unsigned int*)(0x42212CA4UL))) +#define bM4_AOS_PEVNTOSR4_POS10 (*((volatile unsigned int*)(0x42212CA8UL))) +#define bM4_AOS_PEVNTOSR4_POS11 (*((volatile unsigned int*)(0x42212CACUL))) +#define bM4_AOS_PEVNTOSR4_POS12 (*((volatile unsigned int*)(0x42212CB0UL))) +#define bM4_AOS_PEVNTOSR4_POS13 (*((volatile unsigned int*)(0x42212CB4UL))) +#define bM4_AOS_PEVNTOSR4_POS14 (*((volatile unsigned int*)(0x42212CB8UL))) +#define bM4_AOS_PEVNTOSR4_POS15 (*((volatile unsigned int*)(0x42212CBCUL))) +#define bM4_AOS_PEVNTRISR4_RIS00 (*((volatile unsigned int*)(0x42212D00UL))) +#define bM4_AOS_PEVNTRISR4_RIS01 (*((volatile unsigned int*)(0x42212D04UL))) +#define bM4_AOS_PEVNTRISR4_RIS02 (*((volatile unsigned int*)(0x42212D08UL))) +#define bM4_AOS_PEVNTRISR4_RIS03 (*((volatile unsigned int*)(0x42212D0CUL))) +#define bM4_AOS_PEVNTRISR4_RIS04 (*((volatile unsigned int*)(0x42212D10UL))) +#define bM4_AOS_PEVNTRISR4_RIS05 (*((volatile unsigned int*)(0x42212D14UL))) +#define bM4_AOS_PEVNTRISR4_RIS06 (*((volatile unsigned int*)(0x42212D18UL))) +#define bM4_AOS_PEVNTRISR4_RIS07 (*((volatile unsigned int*)(0x42212D1CUL))) +#define bM4_AOS_PEVNTRISR4_RIS08 (*((volatile unsigned int*)(0x42212D20UL))) +#define bM4_AOS_PEVNTRISR4_RIS09 (*((volatile unsigned int*)(0x42212D24UL))) +#define bM4_AOS_PEVNTRISR4_RIS10 (*((volatile unsigned int*)(0x42212D28UL))) +#define bM4_AOS_PEVNTRISR4_RIS11 (*((volatile unsigned int*)(0x42212D2CUL))) +#define bM4_AOS_PEVNTRISR4_RIS12 (*((volatile unsigned int*)(0x42212D30UL))) +#define bM4_AOS_PEVNTRISR4_RIS13 (*((volatile unsigned int*)(0x42212D34UL))) +#define bM4_AOS_PEVNTRISR4_RIS14 (*((volatile unsigned int*)(0x42212D38UL))) +#define bM4_AOS_PEVNTRISR4_RIS15 (*((volatile unsigned int*)(0x42212D3CUL))) +#define bM4_AOS_PEVNTFAL4_FAL00 (*((volatile unsigned int*)(0x42212D80UL))) +#define bM4_AOS_PEVNTFAL4_FAL01 (*((volatile unsigned int*)(0x42212D84UL))) +#define bM4_AOS_PEVNTFAL4_FAL02 (*((volatile unsigned int*)(0x42212D88UL))) +#define bM4_AOS_PEVNTFAL4_FAL03 (*((volatile unsigned int*)(0x42212D8CUL))) +#define bM4_AOS_PEVNTFAL4_FAL04 (*((volatile unsigned int*)(0x42212D90UL))) +#define bM4_AOS_PEVNTFAL4_FAL05 (*((volatile unsigned int*)(0x42212D94UL))) +#define bM4_AOS_PEVNTFAL4_FAL06 (*((volatile unsigned int*)(0x42212D98UL))) +#define bM4_AOS_PEVNTFAL4_FAL07 (*((volatile unsigned int*)(0x42212D9CUL))) +#define bM4_AOS_PEVNTFAL4_FAL08 (*((volatile unsigned int*)(0x42212DA0UL))) +#define bM4_AOS_PEVNTFAL4_FAL09 (*((volatile unsigned int*)(0x42212DA4UL))) +#define bM4_AOS_PEVNTFAL4_FAL10 (*((volatile unsigned int*)(0x42212DA8UL))) +#define bM4_AOS_PEVNTFAL4_FAL11 (*((volatile unsigned int*)(0x42212DACUL))) +#define bM4_AOS_PEVNTFAL4_FAL12 (*((volatile unsigned int*)(0x42212DB0UL))) +#define bM4_AOS_PEVNTFAL4_FAL13 (*((volatile unsigned int*)(0x42212DB4UL))) +#define bM4_AOS_PEVNTFAL4_FAL14 (*((volatile unsigned int*)(0x42212DB8UL))) +#define bM4_AOS_PEVNTFAL4_FAL15 (*((volatile unsigned int*)(0x42212DBCUL))) +#define bM4_AOS_PEVNTNFCR_NFEN1 (*((volatile unsigned int*)(0x42212E00UL))) +#define bM4_AOS_PEVNTNFCR_DIVS10 (*((volatile unsigned int*)(0x42212E04UL))) +#define bM4_AOS_PEVNTNFCR_DIVS11 (*((volatile unsigned int*)(0x42212E08UL))) +#define bM4_AOS_PEVNTNFCR_NFEN2 (*((volatile unsigned int*)(0x42212E20UL))) +#define bM4_AOS_PEVNTNFCR_DIVS20 (*((volatile unsigned int*)(0x42212E24UL))) +#define bM4_AOS_PEVNTNFCR_DIVS21 (*((volatile unsigned int*)(0x42212E28UL))) +#define bM4_AOS_PEVNTNFCR_NFEN3 (*((volatile unsigned int*)(0x42212E40UL))) +#define bM4_AOS_PEVNTNFCR_DIVS30 (*((volatile unsigned int*)(0x42212E44UL))) +#define bM4_AOS_PEVNTNFCR_DIVS31 (*((volatile unsigned int*)(0x42212E48UL))) +#define bM4_AOS_PEVNTNFCR_NFEN4 (*((volatile unsigned int*)(0x42212E60UL))) +#define bM4_AOS_PEVNTNFCR_DIVS40 (*((volatile unsigned int*)(0x42212E64UL))) +#define bM4_AOS_PEVNTNFCR_DIVS41 (*((volatile unsigned int*)(0x42212E68UL))) +#define bM4_CAN_CFG_STAT_BUSOFF (*((volatile unsigned int*)(0x42E09400UL))) +#define bM4_CAN_CFG_STAT_TACTIVE (*((volatile unsigned int*)(0x42E09404UL))) +#define bM4_CAN_CFG_STAT_RACTIVE (*((volatile unsigned int*)(0x42E09408UL))) +#define bM4_CAN_CFG_STAT_TSSS (*((volatile unsigned int*)(0x42E0940CUL))) +#define bM4_CAN_CFG_STAT_TPSS (*((volatile unsigned int*)(0x42E09410UL))) +#define bM4_CAN_CFG_STAT_LBMI (*((volatile unsigned int*)(0x42E09414UL))) +#define bM4_CAN_CFG_STAT_LBME (*((volatile unsigned int*)(0x42E09418UL))) +#define bM4_CAN_CFG_STAT_RESET (*((volatile unsigned int*)(0x42E0941CUL))) +#define bM4_CAN_TCMD_TSA (*((volatile unsigned int*)(0x42E09420UL))) +#define bM4_CAN_TCMD_TSALL (*((volatile unsigned int*)(0x42E09424UL))) +#define bM4_CAN_TCMD_TSONE (*((volatile unsigned int*)(0x42E09428UL))) +#define bM4_CAN_TCMD_TPA (*((volatile unsigned int*)(0x42E0942CUL))) +#define bM4_CAN_TCMD_TPE (*((volatile unsigned int*)(0x42E09430UL))) +#define bM4_CAN_TCMD_LOM (*((volatile unsigned int*)(0x42E09438UL))) +#define bM4_CAN_TCMD_TBSEL (*((volatile unsigned int*)(0x42E0943CUL))) +#define bM4_CAN_TCTRL_TSSTAT0 (*((volatile unsigned int*)(0x42E09440UL))) +#define bM4_CAN_TCTRL_TSSTAT1 (*((volatile unsigned int*)(0x42E09444UL))) +#define bM4_CAN_TCTRL_TTTBM (*((volatile unsigned int*)(0x42E09450UL))) +#define bM4_CAN_TCTRL_TSMODE (*((volatile unsigned int*)(0x42E09454UL))) +#define bM4_CAN_TCTRL_TSNEXT (*((volatile unsigned int*)(0x42E09458UL))) +#define bM4_CAN_RCTRL_RSTAT0 (*((volatile unsigned int*)(0x42E09460UL))) +#define bM4_CAN_RCTRL_RSTAT1 (*((volatile unsigned int*)(0x42E09464UL))) +#define bM4_CAN_RCTRL_RBALL (*((volatile unsigned int*)(0x42E0946CUL))) +#define bM4_CAN_RCTRL_RREL (*((volatile unsigned int*)(0x42E09470UL))) +#define bM4_CAN_RCTRL_ROV (*((volatile unsigned int*)(0x42E09474UL))) +#define bM4_CAN_RCTRL_ROM (*((volatile unsigned int*)(0x42E09478UL))) +#define bM4_CAN_RCTRL_SACK (*((volatile unsigned int*)(0x42E0947CUL))) +#define bM4_CAN_RTIE_TSFF (*((volatile unsigned int*)(0x42E09480UL))) +#define bM4_CAN_RTIE_EIE (*((volatile unsigned int*)(0x42E09484UL))) +#define bM4_CAN_RTIE_TSIE (*((volatile unsigned int*)(0x42E09488UL))) +#define bM4_CAN_RTIE_TPIE (*((volatile unsigned int*)(0x42E0948CUL))) +#define bM4_CAN_RTIE_RAFIE (*((volatile unsigned int*)(0x42E09490UL))) +#define bM4_CAN_RTIE_RFIE (*((volatile unsigned int*)(0x42E09494UL))) +#define bM4_CAN_RTIE_ROIE (*((volatile unsigned int*)(0x42E09498UL))) +#define bM4_CAN_RTIE_RIE (*((volatile unsigned int*)(0x42E0949CUL))) +#define bM4_CAN_RTIF_AIF (*((volatile unsigned int*)(0x42E094A0UL))) +#define bM4_CAN_RTIF_EIF (*((volatile unsigned int*)(0x42E094A4UL))) +#define bM4_CAN_RTIF_TSIF (*((volatile unsigned int*)(0x42E094A8UL))) +#define bM4_CAN_RTIF_TPIF (*((volatile unsigned int*)(0x42E094ACUL))) +#define bM4_CAN_RTIF_RAFIF (*((volatile unsigned int*)(0x42E094B0UL))) +#define bM4_CAN_RTIF_RFIF (*((volatile unsigned int*)(0x42E094B4UL))) +#define bM4_CAN_RTIF_ROIF (*((volatile unsigned int*)(0x42E094B8UL))) +#define bM4_CAN_RTIF_RIF (*((volatile unsigned int*)(0x42E094BCUL))) +#define bM4_CAN_ERRINT_BEIF (*((volatile unsigned int*)(0x42E094C0UL))) +#define bM4_CAN_ERRINT_BEIE (*((volatile unsigned int*)(0x42E094C4UL))) +#define bM4_CAN_ERRINT_ALIF (*((volatile unsigned int*)(0x42E094C8UL))) +#define bM4_CAN_ERRINT_ALIE (*((volatile unsigned int*)(0x42E094CCUL))) +#define bM4_CAN_ERRINT_EPIF (*((volatile unsigned int*)(0x42E094D0UL))) +#define bM4_CAN_ERRINT_EPIE (*((volatile unsigned int*)(0x42E094D4UL))) +#define bM4_CAN_ERRINT_EPASS (*((volatile unsigned int*)(0x42E094D8UL))) +#define bM4_CAN_ERRINT_EWARN (*((volatile unsigned int*)(0x42E094DCUL))) +#define bM4_CAN_LIMIT_EWL0 (*((volatile unsigned int*)(0x42E094E0UL))) +#define bM4_CAN_LIMIT_EWL1 (*((volatile unsigned int*)(0x42E094E4UL))) +#define bM4_CAN_LIMIT_EWL2 (*((volatile unsigned int*)(0x42E094E8UL))) +#define bM4_CAN_LIMIT_EWL3 (*((volatile unsigned int*)(0x42E094ECUL))) +#define bM4_CAN_LIMIT_AFWL0 (*((volatile unsigned int*)(0x42E094F0UL))) +#define bM4_CAN_LIMIT_AFWL1 (*((volatile unsigned int*)(0x42E094F4UL))) +#define bM4_CAN_LIMIT_AFWL2 (*((volatile unsigned int*)(0x42E094F8UL))) +#define bM4_CAN_LIMIT_AFWL3 (*((volatile unsigned int*)(0x42E094FCUL))) +#define bM4_CAN_BT_SEG_10 (*((volatile unsigned int*)(0x42E09500UL))) +#define bM4_CAN_BT_SEG_11 (*((volatile unsigned int*)(0x42E09504UL))) +#define bM4_CAN_BT_SEG_12 (*((volatile unsigned int*)(0x42E09508UL))) +#define bM4_CAN_BT_SEG_13 (*((volatile unsigned int*)(0x42E0950CUL))) +#define bM4_CAN_BT_SEG_14 (*((volatile unsigned int*)(0x42E09510UL))) +#define bM4_CAN_BT_SEG_15 (*((volatile unsigned int*)(0x42E09514UL))) +#define bM4_CAN_BT_SEG_16 (*((volatile unsigned int*)(0x42E09518UL))) +#define bM4_CAN_BT_SEG_17 (*((volatile unsigned int*)(0x42E0951CUL))) +#define bM4_CAN_BT_SEG_20 (*((volatile unsigned int*)(0x42E09520UL))) +#define bM4_CAN_BT_SEG_21 (*((volatile unsigned int*)(0x42E09524UL))) +#define bM4_CAN_BT_SEG_22 (*((volatile unsigned int*)(0x42E09528UL))) +#define bM4_CAN_BT_SEG_23 (*((volatile unsigned int*)(0x42E0952CUL))) +#define bM4_CAN_BT_SEG_24 (*((volatile unsigned int*)(0x42E09530UL))) +#define bM4_CAN_BT_SEG_25 (*((volatile unsigned int*)(0x42E09534UL))) +#define bM4_CAN_BT_SEG_26 (*((volatile unsigned int*)(0x42E09538UL))) +#define bM4_CAN_BT_SJW0 (*((volatile unsigned int*)(0x42E09540UL))) +#define bM4_CAN_BT_SJW1 (*((volatile unsigned int*)(0x42E09544UL))) +#define bM4_CAN_BT_SJW2 (*((volatile unsigned int*)(0x42E09548UL))) +#define bM4_CAN_BT_SJW3 (*((volatile unsigned int*)(0x42E0954CUL))) +#define bM4_CAN_BT_SJW4 (*((volatile unsigned int*)(0x42E09550UL))) +#define bM4_CAN_BT_SJW5 (*((volatile unsigned int*)(0x42E09554UL))) +#define bM4_CAN_BT_SJW6 (*((volatile unsigned int*)(0x42E09558UL))) +#define bM4_CAN_BT_PRESC0 (*((volatile unsigned int*)(0x42E09560UL))) +#define bM4_CAN_BT_PRESC1 (*((volatile unsigned int*)(0x42E09564UL))) +#define bM4_CAN_BT_PRESC2 (*((volatile unsigned int*)(0x42E09568UL))) +#define bM4_CAN_BT_PRESC3 (*((volatile unsigned int*)(0x42E0956CUL))) +#define bM4_CAN_BT_PRESC4 (*((volatile unsigned int*)(0x42E09570UL))) +#define bM4_CAN_BT_PRESC5 (*((volatile unsigned int*)(0x42E09574UL))) +#define bM4_CAN_BT_PRESC6 (*((volatile unsigned int*)(0x42E09578UL))) +#define bM4_CAN_BT_PRESC7 (*((volatile unsigned int*)(0x42E0957CUL))) +#define bM4_CAN_EALCAP_ALC0 (*((volatile unsigned int*)(0x42E09600UL))) +#define bM4_CAN_EALCAP_ALC1 (*((volatile unsigned int*)(0x42E09604UL))) +#define bM4_CAN_EALCAP_ALC2 (*((volatile unsigned int*)(0x42E09608UL))) +#define bM4_CAN_EALCAP_ALC3 (*((volatile unsigned int*)(0x42E0960CUL))) +#define bM4_CAN_EALCAP_ALC4 (*((volatile unsigned int*)(0x42E09610UL))) +#define bM4_CAN_EALCAP_KOER0 (*((volatile unsigned int*)(0x42E09614UL))) +#define bM4_CAN_EALCAP_KOER1 (*((volatile unsigned int*)(0x42E09618UL))) +#define bM4_CAN_EALCAP_KOER2 (*((volatile unsigned int*)(0x42E0961CUL))) +#define bM4_CAN_ACFCTRL_ACFADR0 (*((volatile unsigned int*)(0x42E09680UL))) +#define bM4_CAN_ACFCTRL_ACFADR1 (*((volatile unsigned int*)(0x42E09684UL))) +#define bM4_CAN_ACFCTRL_ACFADR2 (*((volatile unsigned int*)(0x42E09688UL))) +#define bM4_CAN_ACFCTRL_ACFADR3 (*((volatile unsigned int*)(0x42E0968CUL))) +#define bM4_CAN_ACFCTRL_SELMASK (*((volatile unsigned int*)(0x42E09694UL))) +#define bM4_CAN_ACFEN_AE_1 (*((volatile unsigned int*)(0x42E096C0UL))) +#define bM4_CAN_ACFEN_AE_2 (*((volatile unsigned int*)(0x42E096C4UL))) +#define bM4_CAN_ACFEN_AE_3 (*((volatile unsigned int*)(0x42E096C8UL))) +#define bM4_CAN_ACFEN_AE_4 (*((volatile unsigned int*)(0x42E096CCUL))) +#define bM4_CAN_ACFEN_AE_5 (*((volatile unsigned int*)(0x42E096D0UL))) +#define bM4_CAN_ACFEN_AE_6 (*((volatile unsigned int*)(0x42E096D4UL))) +#define bM4_CAN_ACFEN_AE_7 (*((volatile unsigned int*)(0x42E096D8UL))) +#define bM4_CAN_ACFEN_AE_8 (*((volatile unsigned int*)(0x42E096DCUL))) +#define bM4_CAN_ACF_ACODEORAMASK0 (*((volatile unsigned int*)(0x42E09700UL))) +#define bM4_CAN_ACF_ACODEORAMASK1 (*((volatile unsigned int*)(0x42E09704UL))) +#define bM4_CAN_ACF_ACODEORAMASK2 (*((volatile unsigned int*)(0x42E09708UL))) +#define bM4_CAN_ACF_ACODEORAMASK3 (*((volatile unsigned int*)(0x42E0970CUL))) +#define bM4_CAN_ACF_ACODEORAMASK4 (*((volatile unsigned int*)(0x42E09710UL))) +#define bM4_CAN_ACF_ACODEORAMASK5 (*((volatile unsigned int*)(0x42E09714UL))) +#define bM4_CAN_ACF_ACODEORAMASK6 (*((volatile unsigned int*)(0x42E09718UL))) +#define bM4_CAN_ACF_ACODEORAMASK7 (*((volatile unsigned int*)(0x42E0971CUL))) +#define bM4_CAN_ACF_ACODEORAMASK8 (*((volatile unsigned int*)(0x42E09720UL))) +#define bM4_CAN_ACF_ACODEORAMASK9 (*((volatile unsigned int*)(0x42E09724UL))) +#define bM4_CAN_ACF_ACODEORAMASK10 (*((volatile unsigned int*)(0x42E09728UL))) +#define bM4_CAN_ACF_ACODEORAMASK11 (*((volatile unsigned int*)(0x42E0972CUL))) +#define bM4_CAN_ACF_ACODEORAMASK12 (*((volatile unsigned int*)(0x42E09730UL))) +#define bM4_CAN_ACF_ACODEORAMASK13 (*((volatile unsigned int*)(0x42E09734UL))) +#define bM4_CAN_ACF_ACODEORAMASK14 (*((volatile unsigned int*)(0x42E09738UL))) +#define bM4_CAN_ACF_ACODEORAMASK15 (*((volatile unsigned int*)(0x42E0973CUL))) +#define bM4_CAN_ACF_ACODEORAMASK16 (*((volatile unsigned int*)(0x42E09740UL))) +#define bM4_CAN_ACF_ACODEORAMASK17 (*((volatile unsigned int*)(0x42E09744UL))) +#define bM4_CAN_ACF_ACODEORAMASK18 (*((volatile unsigned int*)(0x42E09748UL))) +#define bM4_CAN_ACF_ACODEORAMASK19 (*((volatile unsigned int*)(0x42E0974CUL))) +#define bM4_CAN_ACF_ACODEORAMASK20 (*((volatile unsigned int*)(0x42E09750UL))) +#define bM4_CAN_ACF_ACODEORAMASK21 (*((volatile unsigned int*)(0x42E09754UL))) +#define bM4_CAN_ACF_ACODEORAMASK22 (*((volatile unsigned int*)(0x42E09758UL))) +#define bM4_CAN_ACF_ACODEORAMASK23 (*((volatile unsigned int*)(0x42E0975CUL))) +#define bM4_CAN_ACF_ACODEORAMASK24 (*((volatile unsigned int*)(0x42E09760UL))) +#define bM4_CAN_ACF_ACODEORAMASK25 (*((volatile unsigned int*)(0x42E09764UL))) +#define bM4_CAN_ACF_ACODEORAMASK26 (*((volatile unsigned int*)(0x42E09768UL))) +#define bM4_CAN_ACF_ACODEORAMASK27 (*((volatile unsigned int*)(0x42E0976CUL))) +#define bM4_CAN_ACF_ACODEORAMASK28 (*((volatile unsigned int*)(0x42E09770UL))) +#define bM4_CAN_ACF_AIDE (*((volatile unsigned int*)(0x42E09774UL))) +#define bM4_CAN_ACF_AIDEE (*((volatile unsigned int*)(0x42E09778UL))) +#define bM4_CAN_TBSLOT_TBPTR0 (*((volatile unsigned int*)(0x42E097C0UL))) +#define bM4_CAN_TBSLOT_TBPTR1 (*((volatile unsigned int*)(0x42E097C4UL))) +#define bM4_CAN_TBSLOT_TBPTR2 (*((volatile unsigned int*)(0x42E097C8UL))) +#define bM4_CAN_TBSLOT_TBPTR3 (*((volatile unsigned int*)(0x42E097CCUL))) +#define bM4_CAN_TBSLOT_TBPTR4 (*((volatile unsigned int*)(0x42E097D0UL))) +#define bM4_CAN_TBSLOT_TBPTR5 (*((volatile unsigned int*)(0x42E097D4UL))) +#define bM4_CAN_TBSLOT_TBF (*((volatile unsigned int*)(0x42E097D8UL))) +#define bM4_CAN_TBSLOT_TBE (*((volatile unsigned int*)(0x42E097DCUL))) +#define bM4_CAN_TTCFG_TTEN (*((volatile unsigned int*)(0x42E097E0UL))) +#define bM4_CAN_TTCFG_T_PRESC0 (*((volatile unsigned int*)(0x42E097E4UL))) +#define bM4_CAN_TTCFG_T_PRESC1 (*((volatile unsigned int*)(0x42E097E8UL))) +#define bM4_CAN_TTCFG_TTIF (*((volatile unsigned int*)(0x42E097ECUL))) +#define bM4_CAN_TTCFG_TTIE (*((volatile unsigned int*)(0x42E097F0UL))) +#define bM4_CAN_TTCFG_TEIF (*((volatile unsigned int*)(0x42E097F4UL))) +#define bM4_CAN_TTCFG_WTIF (*((volatile unsigned int*)(0x42E097F8UL))) +#define bM4_CAN_TTCFG_WTIE (*((volatile unsigned int*)(0x42E097FCUL))) +#define bM4_CAN_REF_MSG_REF_ID0 (*((volatile unsigned int*)(0x42E09800UL))) +#define bM4_CAN_REF_MSG_REF_ID1 (*((volatile unsigned int*)(0x42E09804UL))) +#define bM4_CAN_REF_MSG_REF_ID2 (*((volatile unsigned int*)(0x42E09808UL))) +#define bM4_CAN_REF_MSG_REF_ID3 (*((volatile unsigned int*)(0x42E0980CUL))) +#define bM4_CAN_REF_MSG_REF_ID4 (*((volatile unsigned int*)(0x42E09810UL))) +#define bM4_CAN_REF_MSG_REF_ID5 (*((volatile unsigned int*)(0x42E09814UL))) +#define bM4_CAN_REF_MSG_REF_ID6 (*((volatile unsigned int*)(0x42E09818UL))) +#define bM4_CAN_REF_MSG_REF_ID7 (*((volatile unsigned int*)(0x42E0981CUL))) +#define bM4_CAN_REF_MSG_REF_ID8 (*((volatile unsigned int*)(0x42E09820UL))) +#define bM4_CAN_REF_MSG_REF_ID9 (*((volatile unsigned int*)(0x42E09824UL))) +#define bM4_CAN_REF_MSG_REF_ID10 (*((volatile unsigned int*)(0x42E09828UL))) +#define bM4_CAN_REF_MSG_REF_ID11 (*((volatile unsigned int*)(0x42E0982CUL))) +#define bM4_CAN_REF_MSG_REF_ID12 (*((volatile unsigned int*)(0x42E09830UL))) +#define bM4_CAN_REF_MSG_REF_ID13 (*((volatile unsigned int*)(0x42E09834UL))) +#define bM4_CAN_REF_MSG_REF_ID14 (*((volatile unsigned int*)(0x42E09838UL))) +#define bM4_CAN_REF_MSG_REF_ID15 (*((volatile unsigned int*)(0x42E0983CUL))) +#define bM4_CAN_REF_MSG_REF_ID16 (*((volatile unsigned int*)(0x42E09840UL))) +#define bM4_CAN_REF_MSG_REF_ID17 (*((volatile unsigned int*)(0x42E09844UL))) +#define bM4_CAN_REF_MSG_REF_ID18 (*((volatile unsigned int*)(0x42E09848UL))) +#define bM4_CAN_REF_MSG_REF_ID19 (*((volatile unsigned int*)(0x42E0984CUL))) +#define bM4_CAN_REF_MSG_REF_ID20 (*((volatile unsigned int*)(0x42E09850UL))) +#define bM4_CAN_REF_MSG_REF_ID21 (*((volatile unsigned int*)(0x42E09854UL))) +#define bM4_CAN_REF_MSG_REF_ID22 (*((volatile unsigned int*)(0x42E09858UL))) +#define bM4_CAN_REF_MSG_REF_ID23 (*((volatile unsigned int*)(0x42E0985CUL))) +#define bM4_CAN_REF_MSG_REF_ID24 (*((volatile unsigned int*)(0x42E09860UL))) +#define bM4_CAN_REF_MSG_REF_ID25 (*((volatile unsigned int*)(0x42E09864UL))) +#define bM4_CAN_REF_MSG_REF_ID26 (*((volatile unsigned int*)(0x42E09868UL))) +#define bM4_CAN_REF_MSG_REF_ID27 (*((volatile unsigned int*)(0x42E0986CUL))) +#define bM4_CAN_REF_MSG_REF_ID28 (*((volatile unsigned int*)(0x42E09870UL))) +#define bM4_CAN_REF_MSG_REF_IDE (*((volatile unsigned int*)(0x42E0987CUL))) +#define bM4_CAN_TRG_CFG_TTPTR0 (*((volatile unsigned int*)(0x42E09880UL))) +#define bM4_CAN_TRG_CFG_TTPTR1 (*((volatile unsigned int*)(0x42E09884UL))) +#define bM4_CAN_TRG_CFG_TTPTR2 (*((volatile unsigned int*)(0x42E09888UL))) +#define bM4_CAN_TRG_CFG_TTPTR3 (*((volatile unsigned int*)(0x42E0988CUL))) +#define bM4_CAN_TRG_CFG_TTPTR4 (*((volatile unsigned int*)(0x42E09890UL))) +#define bM4_CAN_TRG_CFG_TTPTR5 (*((volatile unsigned int*)(0x42E09894UL))) +#define bM4_CAN_TRG_CFG_TTYPE0 (*((volatile unsigned int*)(0x42E098A0UL))) +#define bM4_CAN_TRG_CFG_TTYPE1 (*((volatile unsigned int*)(0x42E098A4UL))) +#define bM4_CAN_TRG_CFG_TTYPE2 (*((volatile unsigned int*)(0x42E098A8UL))) +#define bM4_CAN_TRG_CFG_TEW0 (*((volatile unsigned int*)(0x42E098B0UL))) +#define bM4_CAN_TRG_CFG_TEW1 (*((volatile unsigned int*)(0x42E098B4UL))) +#define bM4_CAN_TRG_CFG_TEW2 (*((volatile unsigned int*)(0x42E098B8UL))) +#define bM4_CAN_TRG_CFG_TEW3 (*((volatile unsigned int*)(0x42E098BCUL))) +#define bM4_CMP1_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940000UL))) +#define bM4_CMP1_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940004UL))) +#define bM4_CMP1_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940008UL))) +#define bM4_CMP1_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940014UL))) +#define bM4_CMP1_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940018UL))) +#define bM4_CMP1_CTRL_IEN (*((volatile unsigned int*)(0x4294001CUL))) +#define bM4_CMP1_CTRL_CVSEN (*((volatile unsigned int*)(0x42940020UL))) +#define bM4_CMP1_CTRL_OUTEN (*((volatile unsigned int*)(0x42940030UL))) +#define bM4_CMP1_CTRL_INV (*((volatile unsigned int*)(0x42940034UL))) +#define bM4_CMP1_CTRL_CMPOE (*((volatile unsigned int*)(0x42940038UL))) +#define bM4_CMP1_CTRL_CMPON (*((volatile unsigned int*)(0x4294003CUL))) +#define bM4_CMP1_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940040UL))) +#define bM4_CMP1_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940044UL))) +#define bM4_CMP1_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940048UL))) +#define bM4_CMP1_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294004CUL))) +#define bM4_CMP1_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940060UL))) +#define bM4_CMP1_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940064UL))) +#define bM4_CMP1_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940068UL))) +#define bM4_CMP1_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294006CUL))) +#define bM4_CMP1_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940070UL))) +#define bM4_CMP1_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940074UL))) +#define bM4_CMP1_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940078UL))) +#define bM4_CMP1_OUTMON_OMON (*((volatile unsigned int*)(0x42940080UL))) +#define bM4_CMP1_OUTMON_CVST0 (*((volatile unsigned int*)(0x429400A0UL))) +#define bM4_CMP1_OUTMON_CVST1 (*((volatile unsigned int*)(0x429400A4UL))) +#define bM4_CMP1_OUTMON_CVST2 (*((volatile unsigned int*)(0x429400A8UL))) +#define bM4_CMP1_OUTMON_CVST3 (*((volatile unsigned int*)(0x429400ACUL))) +#define bM4_CMP1_CVSSTB_STB0 (*((volatile unsigned int*)(0x429400C0UL))) +#define bM4_CMP1_CVSSTB_STB1 (*((volatile unsigned int*)(0x429400C4UL))) +#define bM4_CMP1_CVSSTB_STB2 (*((volatile unsigned int*)(0x429400C8UL))) +#define bM4_CMP1_CVSSTB_STB3 (*((volatile unsigned int*)(0x429400CCUL))) +#define bM4_CMP1_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940100UL))) +#define bM4_CMP1_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940104UL))) +#define bM4_CMP1_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940108UL))) +#define bM4_CMP1_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294010CUL))) +#define bM4_CMP1_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940110UL))) +#define bM4_CMP1_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940114UL))) +#define bM4_CMP1_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940118UL))) +#define bM4_CMP1_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294011CUL))) +#define bM4_CMP2_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940200UL))) +#define bM4_CMP2_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940204UL))) +#define bM4_CMP2_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940208UL))) +#define bM4_CMP2_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940214UL))) +#define bM4_CMP2_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940218UL))) +#define bM4_CMP2_CTRL_IEN (*((volatile unsigned int*)(0x4294021CUL))) +#define bM4_CMP2_CTRL_CVSEN (*((volatile unsigned int*)(0x42940220UL))) +#define bM4_CMP2_CTRL_OUTEN (*((volatile unsigned int*)(0x42940230UL))) +#define bM4_CMP2_CTRL_INV (*((volatile unsigned int*)(0x42940234UL))) +#define bM4_CMP2_CTRL_CMPOE (*((volatile unsigned int*)(0x42940238UL))) +#define bM4_CMP2_CTRL_CMPON (*((volatile unsigned int*)(0x4294023CUL))) +#define bM4_CMP2_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940240UL))) +#define bM4_CMP2_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940244UL))) +#define bM4_CMP2_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940248UL))) +#define bM4_CMP2_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294024CUL))) +#define bM4_CMP2_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940260UL))) +#define bM4_CMP2_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940264UL))) +#define bM4_CMP2_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940268UL))) +#define bM4_CMP2_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294026CUL))) +#define bM4_CMP2_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940270UL))) +#define bM4_CMP2_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940274UL))) +#define bM4_CMP2_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940278UL))) +#define bM4_CMP2_OUTMON_OMON (*((volatile unsigned int*)(0x42940280UL))) +#define bM4_CMP2_OUTMON_CVST0 (*((volatile unsigned int*)(0x429402A0UL))) +#define bM4_CMP2_OUTMON_CVST1 (*((volatile unsigned int*)(0x429402A4UL))) +#define bM4_CMP2_OUTMON_CVST2 (*((volatile unsigned int*)(0x429402A8UL))) +#define bM4_CMP2_OUTMON_CVST3 (*((volatile unsigned int*)(0x429402ACUL))) +#define bM4_CMP2_CVSSTB_STB0 (*((volatile unsigned int*)(0x429402C0UL))) +#define bM4_CMP2_CVSSTB_STB1 (*((volatile unsigned int*)(0x429402C4UL))) +#define bM4_CMP2_CVSSTB_STB2 (*((volatile unsigned int*)(0x429402C8UL))) +#define bM4_CMP2_CVSSTB_STB3 (*((volatile unsigned int*)(0x429402CCUL))) +#define bM4_CMP2_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940300UL))) +#define bM4_CMP2_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940304UL))) +#define bM4_CMP2_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940308UL))) +#define bM4_CMP2_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294030CUL))) +#define bM4_CMP2_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940310UL))) +#define bM4_CMP2_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940314UL))) +#define bM4_CMP2_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940318UL))) +#define bM4_CMP2_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294031CUL))) +#define bM4_CMP3_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940400UL))) +#define bM4_CMP3_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940404UL))) +#define bM4_CMP3_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940408UL))) +#define bM4_CMP3_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940414UL))) +#define bM4_CMP3_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940418UL))) +#define bM4_CMP3_CTRL_IEN (*((volatile unsigned int*)(0x4294041CUL))) +#define bM4_CMP3_CTRL_CVSEN (*((volatile unsigned int*)(0x42940420UL))) +#define bM4_CMP3_CTRL_OUTEN (*((volatile unsigned int*)(0x42940430UL))) +#define bM4_CMP3_CTRL_INV (*((volatile unsigned int*)(0x42940434UL))) +#define bM4_CMP3_CTRL_CMPOE (*((volatile unsigned int*)(0x42940438UL))) +#define bM4_CMP3_CTRL_CMPON (*((volatile unsigned int*)(0x4294043CUL))) +#define bM4_CMP3_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940440UL))) +#define bM4_CMP3_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940444UL))) +#define bM4_CMP3_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940448UL))) +#define bM4_CMP3_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294044CUL))) +#define bM4_CMP3_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940460UL))) +#define bM4_CMP3_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940464UL))) +#define bM4_CMP3_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940468UL))) +#define bM4_CMP3_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294046CUL))) +#define bM4_CMP3_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940470UL))) +#define bM4_CMP3_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940474UL))) +#define bM4_CMP3_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940478UL))) +#define bM4_CMP3_OUTMON_OMON (*((volatile unsigned int*)(0x42940480UL))) +#define bM4_CMP3_OUTMON_CVST0 (*((volatile unsigned int*)(0x429404A0UL))) +#define bM4_CMP3_OUTMON_CVST1 (*((volatile unsigned int*)(0x429404A4UL))) +#define bM4_CMP3_OUTMON_CVST2 (*((volatile unsigned int*)(0x429404A8UL))) +#define bM4_CMP3_OUTMON_CVST3 (*((volatile unsigned int*)(0x429404ACUL))) +#define bM4_CMP3_CVSSTB_STB0 (*((volatile unsigned int*)(0x429404C0UL))) +#define bM4_CMP3_CVSSTB_STB1 (*((volatile unsigned int*)(0x429404C4UL))) +#define bM4_CMP3_CVSSTB_STB2 (*((volatile unsigned int*)(0x429404C8UL))) +#define bM4_CMP3_CVSSTB_STB3 (*((volatile unsigned int*)(0x429404CCUL))) +#define bM4_CMP3_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940500UL))) +#define bM4_CMP3_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940504UL))) +#define bM4_CMP3_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940508UL))) +#define bM4_CMP3_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294050CUL))) +#define bM4_CMP3_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940510UL))) +#define bM4_CMP3_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940514UL))) +#define bM4_CMP3_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940518UL))) +#define bM4_CMP3_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294051CUL))) +#define bM4_CMP_CR_DADR1_DATA0 (*((volatile unsigned int*)(0x42942000UL))) +#define bM4_CMP_CR_DADR1_DATA1 (*((volatile unsigned int*)(0x42942004UL))) +#define bM4_CMP_CR_DADR1_DATA2 (*((volatile unsigned int*)(0x42942008UL))) +#define bM4_CMP_CR_DADR1_DATA3 (*((volatile unsigned int*)(0x4294200CUL))) +#define bM4_CMP_CR_DADR1_DATA4 (*((volatile unsigned int*)(0x42942010UL))) +#define bM4_CMP_CR_DADR1_DATA5 (*((volatile unsigned int*)(0x42942014UL))) +#define bM4_CMP_CR_DADR1_DATA6 (*((volatile unsigned int*)(0x42942018UL))) +#define bM4_CMP_CR_DADR1_DATA7 (*((volatile unsigned int*)(0x4294201CUL))) +#define bM4_CMP_CR_DADR2_DATA0 (*((volatile unsigned int*)(0x42942040UL))) +#define bM4_CMP_CR_DADR2_DATA1 (*((volatile unsigned int*)(0x42942044UL))) +#define bM4_CMP_CR_DADR2_DATA2 (*((volatile unsigned int*)(0x42942048UL))) +#define bM4_CMP_CR_DADR2_DATA3 (*((volatile unsigned int*)(0x4294204CUL))) +#define bM4_CMP_CR_DADR2_DATA4 (*((volatile unsigned int*)(0x42942050UL))) +#define bM4_CMP_CR_DADR2_DATA5 (*((volatile unsigned int*)(0x42942054UL))) +#define bM4_CMP_CR_DADR2_DATA6 (*((volatile unsigned int*)(0x42942058UL))) +#define bM4_CMP_CR_DADR2_DATA7 (*((volatile unsigned int*)(0x4294205CUL))) +#define bM4_CMP_CR_DACR_DA1EN (*((volatile unsigned int*)(0x42942100UL))) +#define bM4_CMP_CR_DACR_DA2EN (*((volatile unsigned int*)(0x42942104UL))) +#define bM4_CMP_CR_RVADC_DA1SW (*((volatile unsigned int*)(0x42942180UL))) +#define bM4_CMP_CR_RVADC_DA2SW (*((volatile unsigned int*)(0x42942184UL))) +#define bM4_CMP_CR_RVADC_VREFSW (*((volatile unsigned int*)(0x42942190UL))) +#define bM4_CMP_CR_RVADC_WPRT0 (*((volatile unsigned int*)(0x429421A0UL))) +#define bM4_CMP_CR_RVADC_WPRT1 (*((volatile unsigned int*)(0x429421A4UL))) +#define bM4_CMP_CR_RVADC_WPRT2 (*((volatile unsigned int*)(0x429421A8UL))) +#define bM4_CMP_CR_RVADC_WPRT3 (*((volatile unsigned int*)(0x429421ACUL))) +#define bM4_CMP_CR_RVADC_WPRT4 (*((volatile unsigned int*)(0x429421B0UL))) +#define bM4_CMP_CR_RVADC_WPRT5 (*((volatile unsigned int*)(0x429421B4UL))) +#define bM4_CMP_CR_RVADC_WPRT6 (*((volatile unsigned int*)(0x429421B8UL))) +#define bM4_CMP_CR_RVADC_WPRT7 (*((volatile unsigned int*)(0x429421BCUL))) +#define bM4_CRC_CR_CRC_SEL (*((volatile unsigned int*)(0x42118004UL))) +#define bM4_CRC_CR_REFIN (*((volatile unsigned int*)(0x42118008UL))) +#define bM4_CRC_CR_REFOUT (*((volatile unsigned int*)(0x4211800CUL))) +#define bM4_CRC_CR_XOROUT (*((volatile unsigned int*)(0x42118010UL))) +#define bM4_CRC_RESLT_CRC_REG0 (*((volatile unsigned int*)(0x42118080UL))) +#define bM4_CRC_RESLT_CRC_REG1 (*((volatile unsigned int*)(0x42118084UL))) +#define bM4_CRC_RESLT_CRC_REG2 (*((volatile unsigned int*)(0x42118088UL))) +#define bM4_CRC_RESLT_CRC_REG3 (*((volatile unsigned int*)(0x4211808CUL))) +#define bM4_CRC_RESLT_CRC_REG4 (*((volatile unsigned int*)(0x42118090UL))) +#define bM4_CRC_RESLT_CRC_REG5 (*((volatile unsigned int*)(0x42118094UL))) +#define bM4_CRC_RESLT_CRC_REG6 (*((volatile unsigned int*)(0x42118098UL))) +#define bM4_CRC_RESLT_CRC_REG7 (*((volatile unsigned int*)(0x4211809CUL))) +#define bM4_CRC_RESLT_CRC_REG8 (*((volatile unsigned int*)(0x421180A0UL))) +#define bM4_CRC_RESLT_CRC_REG9 (*((volatile unsigned int*)(0x421180A4UL))) +#define bM4_CRC_RESLT_CRC_REG10 (*((volatile unsigned int*)(0x421180A8UL))) +#define bM4_CRC_RESLT_CRC_REG11 (*((volatile unsigned int*)(0x421180ACUL))) +#define bM4_CRC_RESLT_CRC_REG12 (*((volatile unsigned int*)(0x421180B0UL))) +#define bM4_CRC_RESLT_CRC_REG13 (*((volatile unsigned int*)(0x421180B4UL))) +#define bM4_CRC_RESLT_CRC_REG14 (*((volatile unsigned int*)(0x421180B8UL))) +#define bM4_CRC_RESLT_CRC_REG15 (*((volatile unsigned int*)(0x421180BCUL))) +#define bM4_CRC_RESLT_CRCFLAG_16 (*((volatile unsigned int*)(0x421180C0UL))) +#define bM4_CRC_FLG_FLAG (*((volatile unsigned int*)(0x42118180UL))) +#define bM4_DCU1_CTL_MODE0 (*((volatile unsigned int*)(0x42A40000UL))) +#define bM4_DCU1_CTL_MODE1 (*((volatile unsigned int*)(0x42A40004UL))) +#define bM4_DCU1_CTL_MODE2 (*((volatile unsigned int*)(0x42A40008UL))) +#define bM4_DCU1_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4000CUL))) +#define bM4_DCU1_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A40010UL))) +#define bM4_DCU1_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A40020UL))) +#define bM4_DCU1_CTL_INTEN (*((volatile unsigned int*)(0x42A4007CUL))) +#define bM4_DCU1_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A40080UL))) +#define bM4_DCU1_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A40084UL))) +#define bM4_DCU1_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A40088UL))) +#define bM4_DCU1_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4008CUL))) +#define bM4_DCU1_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A40090UL))) +#define bM4_DCU1_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A40094UL))) +#define bM4_DCU1_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A40098UL))) +#define bM4_DCU1_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A40280UL))) +#define bM4_DCU1_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A40284UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A40288UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4028CUL))) +#define bM4_DCU1_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A40290UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A40294UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A40298UL))) +#define bM4_DCU1_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A40300UL))) +#define bM4_DCU1_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A40304UL))) +#define bM4_DCU1_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A40308UL))) +#define bM4_DCU1_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4030CUL))) +#define bM4_DCU1_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A40310UL))) +#define bM4_DCU1_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A40314UL))) +#define bM4_DCU1_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A40318UL))) +#define bM4_DCU1_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4031CUL))) +#define bM4_DCU1_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A40320UL))) +#define bM4_DCU2_CTL_MODE0 (*((volatile unsigned int*)(0x42A48000UL))) +#define bM4_DCU2_CTL_MODE1 (*((volatile unsigned int*)(0x42A48004UL))) +#define bM4_DCU2_CTL_MODE2 (*((volatile unsigned int*)(0x42A48008UL))) +#define bM4_DCU2_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4800CUL))) +#define bM4_DCU2_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A48010UL))) +#define bM4_DCU2_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A48020UL))) +#define bM4_DCU2_CTL_INTEN (*((volatile unsigned int*)(0x42A4807CUL))) +#define bM4_DCU2_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A48080UL))) +#define bM4_DCU2_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A48084UL))) +#define bM4_DCU2_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A48088UL))) +#define bM4_DCU2_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4808CUL))) +#define bM4_DCU2_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A48090UL))) +#define bM4_DCU2_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A48094UL))) +#define bM4_DCU2_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A48098UL))) +#define bM4_DCU2_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A48280UL))) +#define bM4_DCU2_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A48284UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A48288UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4828CUL))) +#define bM4_DCU2_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A48290UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A48294UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A48298UL))) +#define bM4_DCU2_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A48300UL))) +#define bM4_DCU2_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A48304UL))) +#define bM4_DCU2_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A48308UL))) +#define bM4_DCU2_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4830CUL))) +#define bM4_DCU2_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A48310UL))) +#define bM4_DCU2_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A48314UL))) +#define bM4_DCU2_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A48318UL))) +#define bM4_DCU2_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4831CUL))) +#define bM4_DCU2_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A48320UL))) +#define bM4_DCU3_CTL_MODE0 (*((volatile unsigned int*)(0x42A50000UL))) +#define bM4_DCU3_CTL_MODE1 (*((volatile unsigned int*)(0x42A50004UL))) +#define bM4_DCU3_CTL_MODE2 (*((volatile unsigned int*)(0x42A50008UL))) +#define bM4_DCU3_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5000CUL))) +#define bM4_DCU3_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A50010UL))) +#define bM4_DCU3_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A50020UL))) +#define bM4_DCU3_CTL_INTEN (*((volatile unsigned int*)(0x42A5007CUL))) +#define bM4_DCU3_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A50080UL))) +#define bM4_DCU3_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A50084UL))) +#define bM4_DCU3_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A50088UL))) +#define bM4_DCU3_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5008CUL))) +#define bM4_DCU3_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A50090UL))) +#define bM4_DCU3_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A50094UL))) +#define bM4_DCU3_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A50098UL))) +#define bM4_DCU3_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A50280UL))) +#define bM4_DCU3_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A50284UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A50288UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5028CUL))) +#define bM4_DCU3_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A50290UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A50294UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A50298UL))) +#define bM4_DCU3_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A50300UL))) +#define bM4_DCU3_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A50304UL))) +#define bM4_DCU3_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A50308UL))) +#define bM4_DCU3_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5030CUL))) +#define bM4_DCU3_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A50310UL))) +#define bM4_DCU3_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A50314UL))) +#define bM4_DCU3_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A50318UL))) +#define bM4_DCU3_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5031CUL))) +#define bM4_DCU3_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A50320UL))) +#define bM4_DCU4_CTL_MODE0 (*((volatile unsigned int*)(0x42A58000UL))) +#define bM4_DCU4_CTL_MODE1 (*((volatile unsigned int*)(0x42A58004UL))) +#define bM4_DCU4_CTL_MODE2 (*((volatile unsigned int*)(0x42A58008UL))) +#define bM4_DCU4_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5800CUL))) +#define bM4_DCU4_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A58010UL))) +#define bM4_DCU4_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A58020UL))) +#define bM4_DCU4_CTL_INTEN (*((volatile unsigned int*)(0x42A5807CUL))) +#define bM4_DCU4_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A58080UL))) +#define bM4_DCU4_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A58084UL))) +#define bM4_DCU4_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A58088UL))) +#define bM4_DCU4_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5808CUL))) +#define bM4_DCU4_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A58090UL))) +#define bM4_DCU4_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A58094UL))) +#define bM4_DCU4_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A58098UL))) +#define bM4_DCU4_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A58280UL))) +#define bM4_DCU4_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A58284UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A58288UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5828CUL))) +#define bM4_DCU4_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A58290UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A58294UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A58298UL))) +#define bM4_DCU4_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A58300UL))) +#define bM4_DCU4_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A58304UL))) +#define bM4_DCU4_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A58308UL))) +#define bM4_DCU4_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5830CUL))) +#define bM4_DCU4_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A58310UL))) +#define bM4_DCU4_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A58314UL))) +#define bM4_DCU4_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A58318UL))) +#define bM4_DCU4_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5831CUL))) +#define bM4_DCU4_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A58320UL))) +#define bM4_DMA1_EN_EN (*((volatile unsigned int*)(0x42A60000UL))) +#define bM4_DMA1_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A60080UL))) +#define bM4_DMA1_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A60084UL))) +#define bM4_DMA1_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A60088UL))) +#define bM4_DMA1_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6008CUL))) +#define bM4_DMA1_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A600C0UL))) +#define bM4_DMA1_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A600C4UL))) +#define bM4_DMA1_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A600C8UL))) +#define bM4_DMA1_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A600CCUL))) +#define bM4_DMA1_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A60100UL))) +#define bM4_DMA1_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A60104UL))) +#define bM4_DMA1_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A60108UL))) +#define bM4_DMA1_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6010CUL))) +#define bM4_DMA1_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A60140UL))) +#define bM4_DMA1_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A60144UL))) +#define bM4_DMA1_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A60148UL))) +#define bM4_DMA1_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6014CUL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A60180UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A60184UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A60188UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6018CUL))) +#define bM4_DMA1_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A601C0UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A601C4UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A601C8UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A601CCUL))) +#define bM4_DMA1_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A60200UL))) +#define bM4_DMA1_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A60204UL))) +#define bM4_DMA1_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A60208UL))) +#define bM4_DMA1_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6020CUL))) +#define bM4_DMA1_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A60240UL))) +#define bM4_DMA1_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A60244UL))) +#define bM4_DMA1_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A60248UL))) +#define bM4_DMA1_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6024CUL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A60280UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A60284UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A60288UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6028CUL))) +#define bM4_DMA1_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A602C0UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A602C4UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A602C8UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A602CCUL))) +#define bM4_DMA1_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A60300UL))) +#define bM4_DMA1_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A60304UL))) +#define bM4_DMA1_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A60308UL))) +#define bM4_DMA1_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6030CUL))) +#define bM4_DMA1_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A60340UL))) +#define bM4_DMA1_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A60344UL))) +#define bM4_DMA1_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A60348UL))) +#define bM4_DMA1_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6034CUL))) +#define bM4_DMA1_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A60380UL))) +#define bM4_DMA1_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A60384UL))) +#define bM4_DMA1_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A60388UL))) +#define bM4_DMA1_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6038CUL))) +#define bM4_DMA1_REQSTAT_CHREQ0 (*((volatile unsigned int*)(0x42A60400UL))) +#define bM4_DMA1_REQSTAT_CHREQ1 (*((volatile unsigned int*)(0x42A60404UL))) +#define bM4_DMA1_REQSTAT_CHREQ2 (*((volatile unsigned int*)(0x42A60408UL))) +#define bM4_DMA1_REQSTAT_CHREQ3 (*((volatile unsigned int*)(0x42A6040CUL))) +#define bM4_DMA1_REQSTAT_RCFGREQ (*((volatile unsigned int*)(0x42A6043CUL))) +#define bM4_DMA1_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A60480UL))) +#define bM4_DMA1_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A60484UL))) +#define bM4_DMA1_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A604C0UL))) +#define bM4_DMA1_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A604C4UL))) +#define bM4_DMA1_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A604C8UL))) +#define bM4_DMA1_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A604CCUL))) +#define bM4_DMA1_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A60580UL))) +#define bM4_DMA1_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A60584UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A605A0UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A605A4UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A605A8UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A605ACUL))) +#define bM4_DMA1_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A605C0UL))) +#define bM4_DMA1_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A605C4UL))) +#define bM4_DMA1_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A605C8UL))) +#define bM4_DMA1_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A605CCUL))) +#define bM4_DMA1_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A605D0UL))) +#define bM4_DMA1_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A605D4UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60900UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60904UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60908UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6090CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60910UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60914UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60918UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6091CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60920UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60924UL))) +#define bM4_DMA1_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60940UL))) +#define bM4_DMA1_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60944UL))) +#define bM4_DMA1_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60948UL))) +#define bM4_DMA1_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6094CUL))) +#define bM4_DMA1_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60950UL))) +#define bM4_DMA1_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60954UL))) +#define bM4_DMA1_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60958UL))) +#define bM4_DMA1_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6095CUL))) +#define bM4_DMA1_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60960UL))) +#define bM4_DMA1_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60964UL))) +#define bM4_DMA1_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60968UL))) +#define bM4_DMA1_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6096CUL))) +#define bM4_DMA1_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60970UL))) +#define bM4_DMA1_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60974UL))) +#define bM4_DMA1_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60978UL))) +#define bM4_DMA1_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6097CUL))) +#define bM4_DMA1_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_LLP0_LLP0 (*((volatile unsigned int*)(0x42A60B08UL))) +#define bM4_DMA1_LLP0_LLP1 (*((volatile unsigned int*)(0x42A60B0CUL))) +#define bM4_DMA1_LLP0_LLP2 (*((volatile unsigned int*)(0x42A60B10UL))) +#define bM4_DMA1_LLP0_LLP3 (*((volatile unsigned int*)(0x42A60B14UL))) +#define bM4_DMA1_LLP0_LLP4 (*((volatile unsigned int*)(0x42A60B18UL))) +#define bM4_DMA1_LLP0_LLP5 (*((volatile unsigned int*)(0x42A60B1CUL))) +#define bM4_DMA1_LLP0_LLP6 (*((volatile unsigned int*)(0x42A60B20UL))) +#define bM4_DMA1_LLP0_LLP7 (*((volatile unsigned int*)(0x42A60B24UL))) +#define bM4_DMA1_LLP0_LLP8 (*((volatile unsigned int*)(0x42A60B28UL))) +#define bM4_DMA1_LLP0_LLP9 (*((volatile unsigned int*)(0x42A60B2CUL))) +#define bM4_DMA1_LLP0_LLP10 (*((volatile unsigned int*)(0x42A60B30UL))) +#define bM4_DMA1_LLP0_LLP11 (*((volatile unsigned int*)(0x42A60B34UL))) +#define bM4_DMA1_LLP0_LLP12 (*((volatile unsigned int*)(0x42A60B38UL))) +#define bM4_DMA1_LLP0_LLP13 (*((volatile unsigned int*)(0x42A60B3CUL))) +#define bM4_DMA1_LLP0_LLP14 (*((volatile unsigned int*)(0x42A60B40UL))) +#define bM4_DMA1_LLP0_LLP15 (*((volatile unsigned int*)(0x42A60B44UL))) +#define bM4_DMA1_LLP0_LLP16 (*((volatile unsigned int*)(0x42A60B48UL))) +#define bM4_DMA1_LLP0_LLP17 (*((volatile unsigned int*)(0x42A60B4CUL))) +#define bM4_DMA1_LLP0_LLP18 (*((volatile unsigned int*)(0x42A60B50UL))) +#define bM4_DMA1_LLP0_LLP19 (*((volatile unsigned int*)(0x42A60B54UL))) +#define bM4_DMA1_LLP0_LLP20 (*((volatile unsigned int*)(0x42A60B58UL))) +#define bM4_DMA1_LLP0_LLP21 (*((volatile unsigned int*)(0x42A60B5CUL))) +#define bM4_DMA1_LLP0_LLP22 (*((volatile unsigned int*)(0x42A60B60UL))) +#define bM4_DMA1_LLP0_LLP23 (*((volatile unsigned int*)(0x42A60B64UL))) +#define bM4_DMA1_LLP0_LLP24 (*((volatile unsigned int*)(0x42A60B68UL))) +#define bM4_DMA1_LLP0_LLP25 (*((volatile unsigned int*)(0x42A60B6CUL))) +#define bM4_DMA1_LLP0_LLP26 (*((volatile unsigned int*)(0x42A60B70UL))) +#define bM4_DMA1_LLP0_LLP27 (*((volatile unsigned int*)(0x42A60B74UL))) +#define bM4_DMA1_LLP0_LLP28 (*((volatile unsigned int*)(0x42A60B78UL))) +#define bM4_DMA1_LLP0_LLP29 (*((volatile unsigned int*)(0x42A60B7CUL))) +#define bM4_DMA1_CHCTL0_SINC0 (*((volatile unsigned int*)(0x42A60B80UL))) +#define bM4_DMA1_CHCTL0_SINC1 (*((volatile unsigned int*)(0x42A60B84UL))) +#define bM4_DMA1_CHCTL0_DINC0 (*((volatile unsigned int*)(0x42A60B88UL))) +#define bM4_DMA1_CHCTL0_DINC1 (*((volatile unsigned int*)(0x42A60B8CUL))) +#define bM4_DMA1_CHCTL0_SRPTEN (*((volatile unsigned int*)(0x42A60B90UL))) +#define bM4_DMA1_CHCTL0_DRPTEN (*((volatile unsigned int*)(0x42A60B94UL))) +#define bM4_DMA1_CHCTL0_SNSEQEN (*((volatile unsigned int*)(0x42A60B98UL))) +#define bM4_DMA1_CHCTL0_DNSEQEN (*((volatile unsigned int*)(0x42A60B9CUL))) +#define bM4_DMA1_CHCTL0_HSIZE0 (*((volatile unsigned int*)(0x42A60BA0UL))) +#define bM4_DMA1_CHCTL0_HSIZE1 (*((volatile unsigned int*)(0x42A60BA4UL))) +#define bM4_DMA1_CHCTL0_LLPEN (*((volatile unsigned int*)(0x42A60BA8UL))) +#define bM4_DMA1_CHCTL0_LLPRUN (*((volatile unsigned int*)(0x42A60BACUL))) +#define bM4_DMA1_CHCTL0_IE (*((volatile unsigned int*)(0x42A60BB0UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60D00UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60D04UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60D08UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A60D0CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60D10UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60D14UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60D18UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A60D1CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60D20UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60D24UL))) +#define bM4_DMA1_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60D40UL))) +#define bM4_DMA1_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60D44UL))) +#define bM4_DMA1_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60D48UL))) +#define bM4_DMA1_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A60D4CUL))) +#define bM4_DMA1_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60D50UL))) +#define bM4_DMA1_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60D54UL))) +#define bM4_DMA1_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60D58UL))) +#define bM4_DMA1_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A60D5CUL))) +#define bM4_DMA1_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60D60UL))) +#define bM4_DMA1_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60D64UL))) +#define bM4_DMA1_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60D68UL))) +#define bM4_DMA1_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A60D6CUL))) +#define bM4_DMA1_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60D70UL))) +#define bM4_DMA1_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60D74UL))) +#define bM4_DMA1_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60D78UL))) +#define bM4_DMA1_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A60D7CUL))) +#define bM4_DMA1_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A60D80UL))) +#define bM4_DMA1_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A60D84UL))) +#define bM4_DMA1_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A60D88UL))) +#define bM4_DMA1_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A60D8CUL))) +#define bM4_DMA1_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A60D90UL))) +#define bM4_DMA1_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A60D94UL))) +#define bM4_DMA1_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A60D98UL))) +#define bM4_DMA1_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A60D9CUL))) +#define bM4_DMA1_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A60DA0UL))) +#define bM4_DMA1_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A60DA4UL))) +#define bM4_DMA1_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A60DC0UL))) +#define bM4_DMA1_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A60DC4UL))) +#define bM4_DMA1_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A60DC8UL))) +#define bM4_DMA1_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A60DCCUL))) +#define bM4_DMA1_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A60DD0UL))) +#define bM4_DMA1_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A60DD4UL))) +#define bM4_DMA1_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A60DD8UL))) +#define bM4_DMA1_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A60DDCUL))) +#define bM4_DMA1_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A60DE0UL))) +#define bM4_DMA1_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A60DE4UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60E00UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60E04UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60E08UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60E0CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60E10UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60E14UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60E18UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60E1CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60E20UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60E24UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60E28UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60E2CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60E30UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60E34UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60E38UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60E3CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60E40UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60E44UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60E48UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60E4CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60E50UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60E54UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60E58UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60E5CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60E60UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60E64UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60E68UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60E6CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60E70UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60E74UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60E78UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60E7CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60E80UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60E84UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60E88UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60E8CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60E90UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60E94UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60E98UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60E9CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60EA0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60EA4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60EA8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60EACUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60EB0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60EB4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60EB8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60EBCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60EC0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60EC4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60EC8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ECCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60ED0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60ED4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60ED8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60EDCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60EE0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60EE4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60EE8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60EECUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60EF0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60EF4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60EF8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60EFCUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61100UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61104UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61108UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6110CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61110UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61114UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61118UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6111CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61120UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61124UL))) +#define bM4_DMA1_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61140UL))) +#define bM4_DMA1_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61144UL))) +#define bM4_DMA1_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61148UL))) +#define bM4_DMA1_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6114CUL))) +#define bM4_DMA1_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61150UL))) +#define bM4_DMA1_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61154UL))) +#define bM4_DMA1_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61158UL))) +#define bM4_DMA1_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6115CUL))) +#define bM4_DMA1_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61160UL))) +#define bM4_DMA1_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61164UL))) +#define bM4_DMA1_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61168UL))) +#define bM4_DMA1_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6116CUL))) +#define bM4_DMA1_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61170UL))) +#define bM4_DMA1_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61174UL))) +#define bM4_DMA1_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61178UL))) +#define bM4_DMA1_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6117CUL))) +#define bM4_DMA1_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_LLP1_LLP0 (*((volatile unsigned int*)(0x42A61308UL))) +#define bM4_DMA1_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6130CUL))) +#define bM4_DMA1_LLP1_LLP2 (*((volatile unsigned int*)(0x42A61310UL))) +#define bM4_DMA1_LLP1_LLP3 (*((volatile unsigned int*)(0x42A61314UL))) +#define bM4_DMA1_LLP1_LLP4 (*((volatile unsigned int*)(0x42A61318UL))) +#define bM4_DMA1_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6131CUL))) +#define bM4_DMA1_LLP1_LLP6 (*((volatile unsigned int*)(0x42A61320UL))) +#define bM4_DMA1_LLP1_LLP7 (*((volatile unsigned int*)(0x42A61324UL))) +#define bM4_DMA1_LLP1_LLP8 (*((volatile unsigned int*)(0x42A61328UL))) +#define bM4_DMA1_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6132CUL))) +#define bM4_DMA1_LLP1_LLP10 (*((volatile unsigned int*)(0x42A61330UL))) +#define bM4_DMA1_LLP1_LLP11 (*((volatile unsigned int*)(0x42A61334UL))) +#define bM4_DMA1_LLP1_LLP12 (*((volatile unsigned int*)(0x42A61338UL))) +#define bM4_DMA1_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6133CUL))) +#define bM4_DMA1_LLP1_LLP14 (*((volatile unsigned int*)(0x42A61340UL))) +#define bM4_DMA1_LLP1_LLP15 (*((volatile unsigned int*)(0x42A61344UL))) +#define bM4_DMA1_LLP1_LLP16 (*((volatile unsigned int*)(0x42A61348UL))) +#define bM4_DMA1_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6134CUL))) +#define bM4_DMA1_LLP1_LLP18 (*((volatile unsigned int*)(0x42A61350UL))) +#define bM4_DMA1_LLP1_LLP19 (*((volatile unsigned int*)(0x42A61354UL))) +#define bM4_DMA1_LLP1_LLP20 (*((volatile unsigned int*)(0x42A61358UL))) +#define bM4_DMA1_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6135CUL))) +#define bM4_DMA1_LLP1_LLP22 (*((volatile unsigned int*)(0x42A61360UL))) +#define bM4_DMA1_LLP1_LLP23 (*((volatile unsigned int*)(0x42A61364UL))) +#define bM4_DMA1_LLP1_LLP24 (*((volatile unsigned int*)(0x42A61368UL))) +#define bM4_DMA1_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6136CUL))) +#define bM4_DMA1_LLP1_LLP26 (*((volatile unsigned int*)(0x42A61370UL))) +#define bM4_DMA1_LLP1_LLP27 (*((volatile unsigned int*)(0x42A61374UL))) +#define bM4_DMA1_LLP1_LLP28 (*((volatile unsigned int*)(0x42A61378UL))) +#define bM4_DMA1_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6137CUL))) +#define bM4_DMA1_CHCTL1_SINC0 (*((volatile unsigned int*)(0x42A61380UL))) +#define bM4_DMA1_CHCTL1_SINC1 (*((volatile unsigned int*)(0x42A61384UL))) +#define bM4_DMA1_CHCTL1_DINC0 (*((volatile unsigned int*)(0x42A61388UL))) +#define bM4_DMA1_CHCTL1_DINC1 (*((volatile unsigned int*)(0x42A6138CUL))) +#define bM4_DMA1_CHCTL1_SRPTEN (*((volatile unsigned int*)(0x42A61390UL))) +#define bM4_DMA1_CHCTL1_DRPTEN (*((volatile unsigned int*)(0x42A61394UL))) +#define bM4_DMA1_CHCTL1_SNSEQEN (*((volatile unsigned int*)(0x42A61398UL))) +#define bM4_DMA1_CHCTL1_DNSEQEN (*((volatile unsigned int*)(0x42A6139CUL))) +#define bM4_DMA1_CHCTL1_HSIZE0 (*((volatile unsigned int*)(0x42A613A0UL))) +#define bM4_DMA1_CHCTL1_HSIZE1 (*((volatile unsigned int*)(0x42A613A4UL))) +#define bM4_DMA1_CHCTL1_LLPEN (*((volatile unsigned int*)(0x42A613A8UL))) +#define bM4_DMA1_CHCTL1_LLPRUN (*((volatile unsigned int*)(0x42A613ACUL))) +#define bM4_DMA1_CHCTL1_IE (*((volatile unsigned int*)(0x42A613B0UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61500UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61504UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61508UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6150CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61510UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61514UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61518UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6151CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61520UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61524UL))) +#define bM4_DMA1_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61540UL))) +#define bM4_DMA1_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61544UL))) +#define bM4_DMA1_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61548UL))) +#define bM4_DMA1_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6154CUL))) +#define bM4_DMA1_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61550UL))) +#define bM4_DMA1_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61554UL))) +#define bM4_DMA1_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61558UL))) +#define bM4_DMA1_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6155CUL))) +#define bM4_DMA1_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61560UL))) +#define bM4_DMA1_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61564UL))) +#define bM4_DMA1_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61568UL))) +#define bM4_DMA1_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6156CUL))) +#define bM4_DMA1_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61570UL))) +#define bM4_DMA1_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61574UL))) +#define bM4_DMA1_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61578UL))) +#define bM4_DMA1_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6157CUL))) +#define bM4_DMA1_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A61580UL))) +#define bM4_DMA1_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A61584UL))) +#define bM4_DMA1_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A61588UL))) +#define bM4_DMA1_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6158CUL))) +#define bM4_DMA1_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A61590UL))) +#define bM4_DMA1_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A61594UL))) +#define bM4_DMA1_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A61598UL))) +#define bM4_DMA1_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6159CUL))) +#define bM4_DMA1_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A615A0UL))) +#define bM4_DMA1_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A615A4UL))) +#define bM4_DMA1_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A615C0UL))) +#define bM4_DMA1_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A615C4UL))) +#define bM4_DMA1_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A615C8UL))) +#define bM4_DMA1_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A615CCUL))) +#define bM4_DMA1_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A615D0UL))) +#define bM4_DMA1_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A615D4UL))) +#define bM4_DMA1_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A615D8UL))) +#define bM4_DMA1_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A615DCUL))) +#define bM4_DMA1_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A615E0UL))) +#define bM4_DMA1_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A615E4UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61600UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61604UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61608UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6160CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61610UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61614UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61618UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6161CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61620UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61624UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61628UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6162CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61630UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61634UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61638UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6163CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61640UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61644UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61648UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6164CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61650UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61654UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61658UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6165CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61660UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61664UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61668UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6166CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61670UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61674UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61678UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6167CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61680UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61684UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61688UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6168CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61690UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61694UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61698UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6169CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A616A0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A616A4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A616A8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A616ACUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A616B0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A616B4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A616B8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A616BCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A616C0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A616C4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A616C8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A616CCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A616D0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A616D4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A616D8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A616DCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A616E0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A616E4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A616E8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A616ECUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A616F0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A616F4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A616F8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A616FCUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61900UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61904UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61908UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6190CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61910UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61914UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61918UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6191CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61920UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61924UL))) +#define bM4_DMA1_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61940UL))) +#define bM4_DMA1_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61944UL))) +#define bM4_DMA1_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61948UL))) +#define bM4_DMA1_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6194CUL))) +#define bM4_DMA1_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61950UL))) +#define bM4_DMA1_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61954UL))) +#define bM4_DMA1_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61958UL))) +#define bM4_DMA1_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6195CUL))) +#define bM4_DMA1_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61960UL))) +#define bM4_DMA1_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61964UL))) +#define bM4_DMA1_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61968UL))) +#define bM4_DMA1_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6196CUL))) +#define bM4_DMA1_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61970UL))) +#define bM4_DMA1_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61974UL))) +#define bM4_DMA1_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61978UL))) +#define bM4_DMA1_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6197CUL))) +#define bM4_DMA1_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_LLP2_LLP0 (*((volatile unsigned int*)(0x42A61B08UL))) +#define bM4_DMA1_LLP2_LLP1 (*((volatile unsigned int*)(0x42A61B0CUL))) +#define bM4_DMA1_LLP2_LLP2 (*((volatile unsigned int*)(0x42A61B10UL))) +#define bM4_DMA1_LLP2_LLP3 (*((volatile unsigned int*)(0x42A61B14UL))) +#define bM4_DMA1_LLP2_LLP4 (*((volatile unsigned int*)(0x42A61B18UL))) +#define bM4_DMA1_LLP2_LLP5 (*((volatile unsigned int*)(0x42A61B1CUL))) +#define bM4_DMA1_LLP2_LLP6 (*((volatile unsigned int*)(0x42A61B20UL))) +#define bM4_DMA1_LLP2_LLP7 (*((volatile unsigned int*)(0x42A61B24UL))) +#define bM4_DMA1_LLP2_LLP8 (*((volatile unsigned int*)(0x42A61B28UL))) +#define bM4_DMA1_LLP2_LLP9 (*((volatile unsigned int*)(0x42A61B2CUL))) +#define bM4_DMA1_LLP2_LLP10 (*((volatile unsigned int*)(0x42A61B30UL))) +#define bM4_DMA1_LLP2_LLP11 (*((volatile unsigned int*)(0x42A61B34UL))) +#define bM4_DMA1_LLP2_LLP12 (*((volatile unsigned int*)(0x42A61B38UL))) +#define bM4_DMA1_LLP2_LLP13 (*((volatile unsigned int*)(0x42A61B3CUL))) +#define bM4_DMA1_LLP2_LLP14 (*((volatile unsigned int*)(0x42A61B40UL))) +#define bM4_DMA1_LLP2_LLP15 (*((volatile unsigned int*)(0x42A61B44UL))) +#define bM4_DMA1_LLP2_LLP16 (*((volatile unsigned int*)(0x42A61B48UL))) +#define bM4_DMA1_LLP2_LLP17 (*((volatile unsigned int*)(0x42A61B4CUL))) +#define bM4_DMA1_LLP2_LLP18 (*((volatile unsigned int*)(0x42A61B50UL))) +#define bM4_DMA1_LLP2_LLP19 (*((volatile unsigned int*)(0x42A61B54UL))) +#define bM4_DMA1_LLP2_LLP20 (*((volatile unsigned int*)(0x42A61B58UL))) +#define bM4_DMA1_LLP2_LLP21 (*((volatile unsigned int*)(0x42A61B5CUL))) +#define bM4_DMA1_LLP2_LLP22 (*((volatile unsigned int*)(0x42A61B60UL))) +#define bM4_DMA1_LLP2_LLP23 (*((volatile unsigned int*)(0x42A61B64UL))) +#define bM4_DMA1_LLP2_LLP24 (*((volatile unsigned int*)(0x42A61B68UL))) +#define bM4_DMA1_LLP2_LLP25 (*((volatile unsigned int*)(0x42A61B6CUL))) +#define bM4_DMA1_LLP2_LLP26 (*((volatile unsigned int*)(0x42A61B70UL))) +#define bM4_DMA1_LLP2_LLP27 (*((volatile unsigned int*)(0x42A61B74UL))) +#define bM4_DMA1_LLP2_LLP28 (*((volatile unsigned int*)(0x42A61B78UL))) +#define bM4_DMA1_LLP2_LLP29 (*((volatile unsigned int*)(0x42A61B7CUL))) +#define bM4_DMA1_CHCTL2_SINC0 (*((volatile unsigned int*)(0x42A61B80UL))) +#define bM4_DMA1_CHCTL2_SINC1 (*((volatile unsigned int*)(0x42A61B84UL))) +#define bM4_DMA1_CHCTL2_DINC0 (*((volatile unsigned int*)(0x42A61B88UL))) +#define bM4_DMA1_CHCTL2_DINC1 (*((volatile unsigned int*)(0x42A61B8CUL))) +#define bM4_DMA1_CHCTL2_SRPTEN (*((volatile unsigned int*)(0x42A61B90UL))) +#define bM4_DMA1_CHCTL2_DRPTEN (*((volatile unsigned int*)(0x42A61B94UL))) +#define bM4_DMA1_CHCTL2_SNSEQEN (*((volatile unsigned int*)(0x42A61B98UL))) +#define bM4_DMA1_CHCTL2_DNSEQEN (*((volatile unsigned int*)(0x42A61B9CUL))) +#define bM4_DMA1_CHCTL2_HSIZE0 (*((volatile unsigned int*)(0x42A61BA0UL))) +#define bM4_DMA1_CHCTL2_HSIZE1 (*((volatile unsigned int*)(0x42A61BA4UL))) +#define bM4_DMA1_CHCTL2_LLPEN (*((volatile unsigned int*)(0x42A61BA8UL))) +#define bM4_DMA1_CHCTL2_LLPRUN (*((volatile unsigned int*)(0x42A61BACUL))) +#define bM4_DMA1_CHCTL2_IE (*((volatile unsigned int*)(0x42A61BB0UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61D00UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61D04UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61D08UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A61D0CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61D10UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61D14UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61D18UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A61D1CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61D20UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61D24UL))) +#define bM4_DMA1_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61D40UL))) +#define bM4_DMA1_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61D44UL))) +#define bM4_DMA1_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61D48UL))) +#define bM4_DMA1_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A61D4CUL))) +#define bM4_DMA1_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61D50UL))) +#define bM4_DMA1_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61D54UL))) +#define bM4_DMA1_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61D58UL))) +#define bM4_DMA1_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A61D5CUL))) +#define bM4_DMA1_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61D60UL))) +#define bM4_DMA1_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61D64UL))) +#define bM4_DMA1_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61D68UL))) +#define bM4_DMA1_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A61D6CUL))) +#define bM4_DMA1_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61D70UL))) +#define bM4_DMA1_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61D74UL))) +#define bM4_DMA1_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61D78UL))) +#define bM4_DMA1_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A61D7CUL))) +#define bM4_DMA1_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A61D80UL))) +#define bM4_DMA1_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A61D84UL))) +#define bM4_DMA1_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A61D88UL))) +#define bM4_DMA1_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A61D8CUL))) +#define bM4_DMA1_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A61D90UL))) +#define bM4_DMA1_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A61D94UL))) +#define bM4_DMA1_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A61D98UL))) +#define bM4_DMA1_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A61D9CUL))) +#define bM4_DMA1_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A61DA0UL))) +#define bM4_DMA1_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A61DA4UL))) +#define bM4_DMA1_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A61DC0UL))) +#define bM4_DMA1_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A61DC4UL))) +#define bM4_DMA1_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A61DC8UL))) +#define bM4_DMA1_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A61DCCUL))) +#define bM4_DMA1_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A61DD0UL))) +#define bM4_DMA1_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A61DD4UL))) +#define bM4_DMA1_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A61DD8UL))) +#define bM4_DMA1_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A61DDCUL))) +#define bM4_DMA1_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A61DE0UL))) +#define bM4_DMA1_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A61DE4UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61E00UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61E04UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61E08UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61E0CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61E10UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61E14UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61E18UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61E1CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61E20UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61E24UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61E28UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61E2CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61E30UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61E34UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61E38UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61E3CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61E40UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61E44UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61E48UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61E4CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61E50UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61E54UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61E58UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61E5CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61E60UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61E64UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61E68UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61E6CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61E70UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61E74UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61E78UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61E7CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61E80UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61E84UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61E88UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61E8CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61E90UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61E94UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61E98UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61E9CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61EA0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61EA4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61EA8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61EACUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61EB0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61EB4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61EB8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61EBCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61EC0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61EC4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61EC8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ECCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61ED0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61ED4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61ED8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61EDCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61EE0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61EE4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61EE8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61EECUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61EF0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61EF4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61EF8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61EFCUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62100UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62104UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62108UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6210CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62110UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62114UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62118UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6211CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62120UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62124UL))) +#define bM4_DMA1_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62140UL))) +#define bM4_DMA1_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62144UL))) +#define bM4_DMA1_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62148UL))) +#define bM4_DMA1_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6214CUL))) +#define bM4_DMA1_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62150UL))) +#define bM4_DMA1_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62154UL))) +#define bM4_DMA1_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62158UL))) +#define bM4_DMA1_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6215CUL))) +#define bM4_DMA1_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62160UL))) +#define bM4_DMA1_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62164UL))) +#define bM4_DMA1_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62168UL))) +#define bM4_DMA1_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6216CUL))) +#define bM4_DMA1_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62170UL))) +#define bM4_DMA1_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62174UL))) +#define bM4_DMA1_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62178UL))) +#define bM4_DMA1_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6217CUL))) +#define bM4_DMA1_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_LLP3_LLP0 (*((volatile unsigned int*)(0x42A62308UL))) +#define bM4_DMA1_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6230CUL))) +#define bM4_DMA1_LLP3_LLP2 (*((volatile unsigned int*)(0x42A62310UL))) +#define bM4_DMA1_LLP3_LLP3 (*((volatile unsigned int*)(0x42A62314UL))) +#define bM4_DMA1_LLP3_LLP4 (*((volatile unsigned int*)(0x42A62318UL))) +#define bM4_DMA1_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6231CUL))) +#define bM4_DMA1_LLP3_LLP6 (*((volatile unsigned int*)(0x42A62320UL))) +#define bM4_DMA1_LLP3_LLP7 (*((volatile unsigned int*)(0x42A62324UL))) +#define bM4_DMA1_LLP3_LLP8 (*((volatile unsigned int*)(0x42A62328UL))) +#define bM4_DMA1_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6232CUL))) +#define bM4_DMA1_LLP3_LLP10 (*((volatile unsigned int*)(0x42A62330UL))) +#define bM4_DMA1_LLP3_LLP11 (*((volatile unsigned int*)(0x42A62334UL))) +#define bM4_DMA1_LLP3_LLP12 (*((volatile unsigned int*)(0x42A62338UL))) +#define bM4_DMA1_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6233CUL))) +#define bM4_DMA1_LLP3_LLP14 (*((volatile unsigned int*)(0x42A62340UL))) +#define bM4_DMA1_LLP3_LLP15 (*((volatile unsigned int*)(0x42A62344UL))) +#define bM4_DMA1_LLP3_LLP16 (*((volatile unsigned int*)(0x42A62348UL))) +#define bM4_DMA1_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6234CUL))) +#define bM4_DMA1_LLP3_LLP18 (*((volatile unsigned int*)(0x42A62350UL))) +#define bM4_DMA1_LLP3_LLP19 (*((volatile unsigned int*)(0x42A62354UL))) +#define bM4_DMA1_LLP3_LLP20 (*((volatile unsigned int*)(0x42A62358UL))) +#define bM4_DMA1_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6235CUL))) +#define bM4_DMA1_LLP3_LLP22 (*((volatile unsigned int*)(0x42A62360UL))) +#define bM4_DMA1_LLP3_LLP23 (*((volatile unsigned int*)(0x42A62364UL))) +#define bM4_DMA1_LLP3_LLP24 (*((volatile unsigned int*)(0x42A62368UL))) +#define bM4_DMA1_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6236CUL))) +#define bM4_DMA1_LLP3_LLP26 (*((volatile unsigned int*)(0x42A62370UL))) +#define bM4_DMA1_LLP3_LLP27 (*((volatile unsigned int*)(0x42A62374UL))) +#define bM4_DMA1_LLP3_LLP28 (*((volatile unsigned int*)(0x42A62378UL))) +#define bM4_DMA1_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6237CUL))) +#define bM4_DMA1_CHCTL3_SINC0 (*((volatile unsigned int*)(0x42A62380UL))) +#define bM4_DMA1_CHCTL3_SINC1 (*((volatile unsigned int*)(0x42A62384UL))) +#define bM4_DMA1_CHCTL3_DINC0 (*((volatile unsigned int*)(0x42A62388UL))) +#define bM4_DMA1_CHCTL3_DINC1 (*((volatile unsigned int*)(0x42A6238CUL))) +#define bM4_DMA1_CHCTL3_SRPTEN (*((volatile unsigned int*)(0x42A62390UL))) +#define bM4_DMA1_CHCTL3_DRPTEN (*((volatile unsigned int*)(0x42A62394UL))) +#define bM4_DMA1_CHCTL3_SNSEQEN (*((volatile unsigned int*)(0x42A62398UL))) +#define bM4_DMA1_CHCTL3_DNSEQEN (*((volatile unsigned int*)(0x42A6239CUL))) +#define bM4_DMA1_CHCTL3_HSIZE0 (*((volatile unsigned int*)(0x42A623A0UL))) +#define bM4_DMA1_CHCTL3_HSIZE1 (*((volatile unsigned int*)(0x42A623A4UL))) +#define bM4_DMA1_CHCTL3_LLPEN (*((volatile unsigned int*)(0x42A623A8UL))) +#define bM4_DMA1_CHCTL3_LLPRUN (*((volatile unsigned int*)(0x42A623ACUL))) +#define bM4_DMA1_CHCTL3_IE (*((volatile unsigned int*)(0x42A623B0UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62500UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62504UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62508UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6250CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62510UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62514UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62518UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6251CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62520UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62524UL))) +#define bM4_DMA1_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62540UL))) +#define bM4_DMA1_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62544UL))) +#define bM4_DMA1_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62548UL))) +#define bM4_DMA1_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6254CUL))) +#define bM4_DMA1_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62550UL))) +#define bM4_DMA1_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62554UL))) +#define bM4_DMA1_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62558UL))) +#define bM4_DMA1_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6255CUL))) +#define bM4_DMA1_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62560UL))) +#define bM4_DMA1_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62564UL))) +#define bM4_DMA1_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62568UL))) +#define bM4_DMA1_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6256CUL))) +#define bM4_DMA1_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62570UL))) +#define bM4_DMA1_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62574UL))) +#define bM4_DMA1_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62578UL))) +#define bM4_DMA1_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6257CUL))) +#define bM4_DMA1_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A62580UL))) +#define bM4_DMA1_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A62584UL))) +#define bM4_DMA1_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A62588UL))) +#define bM4_DMA1_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6258CUL))) +#define bM4_DMA1_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A62590UL))) +#define bM4_DMA1_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A62594UL))) +#define bM4_DMA1_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A62598UL))) +#define bM4_DMA1_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6259CUL))) +#define bM4_DMA1_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A625A0UL))) +#define bM4_DMA1_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A625A4UL))) +#define bM4_DMA1_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A625C0UL))) +#define bM4_DMA1_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A625C4UL))) +#define bM4_DMA1_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A625C8UL))) +#define bM4_DMA1_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A625CCUL))) +#define bM4_DMA1_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A625D0UL))) +#define bM4_DMA1_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A625D4UL))) +#define bM4_DMA1_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A625D8UL))) +#define bM4_DMA1_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A625DCUL))) +#define bM4_DMA1_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A625E0UL))) +#define bM4_DMA1_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A625E4UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62600UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62604UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62608UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6260CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62610UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62614UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62618UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6261CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62620UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62624UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62628UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6262CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62630UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62634UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62638UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6263CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62640UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62644UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62648UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6264CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62650UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62654UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62658UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6265CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62660UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62664UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62668UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6266CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62670UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62674UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62678UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6267CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62680UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62684UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62688UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6268CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62690UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62694UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62698UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6269CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A626A0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A626A4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A626A8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A626ACUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A626B0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A626B4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A626B8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A626BCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A626C0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A626C4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A626C8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A626CCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A626D0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A626D4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A626D8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A626DCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A626E0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A626E4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A626E8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A626ECUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A626F0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A626F4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A626F8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A626FCUL))) +#define bM4_DMA2_EN_EN (*((volatile unsigned int*)(0x42A68000UL))) +#define bM4_DMA2_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A68080UL))) +#define bM4_DMA2_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A68084UL))) +#define bM4_DMA2_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A68088UL))) +#define bM4_DMA2_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6808CUL))) +#define bM4_DMA2_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A680C0UL))) +#define bM4_DMA2_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A680C4UL))) +#define bM4_DMA2_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A680C8UL))) +#define bM4_DMA2_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A680CCUL))) +#define bM4_DMA2_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A68100UL))) +#define bM4_DMA2_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A68104UL))) +#define bM4_DMA2_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A68108UL))) +#define bM4_DMA2_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6810CUL))) +#define bM4_DMA2_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A68140UL))) +#define bM4_DMA2_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A68144UL))) +#define bM4_DMA2_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A68148UL))) +#define bM4_DMA2_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6814CUL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A68180UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A68184UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A68188UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6818CUL))) +#define bM4_DMA2_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A681C0UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A681C4UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A681C8UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A681CCUL))) +#define bM4_DMA2_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A68200UL))) +#define bM4_DMA2_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A68204UL))) +#define bM4_DMA2_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A68208UL))) +#define bM4_DMA2_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6820CUL))) +#define bM4_DMA2_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A68240UL))) +#define bM4_DMA2_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A68244UL))) +#define bM4_DMA2_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A68248UL))) +#define bM4_DMA2_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6824CUL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A68280UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A68284UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A68288UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6828CUL))) +#define bM4_DMA2_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A682C0UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A682C4UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A682C8UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A682CCUL))) +#define bM4_DMA2_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A68300UL))) +#define bM4_DMA2_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A68304UL))) +#define bM4_DMA2_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A68308UL))) +#define bM4_DMA2_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6830CUL))) +#define bM4_DMA2_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A68340UL))) +#define bM4_DMA2_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A68344UL))) +#define bM4_DMA2_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A68348UL))) +#define bM4_DMA2_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6834CUL))) +#define bM4_DMA2_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A68380UL))) +#define bM4_DMA2_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A68384UL))) +#define bM4_DMA2_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A68388UL))) +#define bM4_DMA2_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6838CUL))) +#define bM4_DMA2_REQSTAT_CHREQ0 (*((volatile unsigned int*)(0x42A68400UL))) +#define bM4_DMA2_REQSTAT_CHREQ1 (*((volatile unsigned int*)(0x42A68404UL))) +#define bM4_DMA2_REQSTAT_CHREQ2 (*((volatile unsigned int*)(0x42A68408UL))) +#define bM4_DMA2_REQSTAT_CHREQ3 (*((volatile unsigned int*)(0x42A6840CUL))) +#define bM4_DMA2_REQSTAT_RCFGREQ (*((volatile unsigned int*)(0x42A6843CUL))) +#define bM4_DMA2_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A68480UL))) +#define bM4_DMA2_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A68484UL))) +#define bM4_DMA2_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A684C0UL))) +#define bM4_DMA2_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A684C4UL))) +#define bM4_DMA2_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A684C8UL))) +#define bM4_DMA2_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A684CCUL))) +#define bM4_DMA2_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A68580UL))) +#define bM4_DMA2_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A68584UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A685A0UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A685A4UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A685A8UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A685ACUL))) +#define bM4_DMA2_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A685C0UL))) +#define bM4_DMA2_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A685C4UL))) +#define bM4_DMA2_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A685C8UL))) +#define bM4_DMA2_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A685CCUL))) +#define bM4_DMA2_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A685D0UL))) +#define bM4_DMA2_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A685D4UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68900UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68904UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68908UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6890CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68910UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68914UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68918UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6891CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68920UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68924UL))) +#define bM4_DMA2_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68940UL))) +#define bM4_DMA2_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68944UL))) +#define bM4_DMA2_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68948UL))) +#define bM4_DMA2_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6894CUL))) +#define bM4_DMA2_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68950UL))) +#define bM4_DMA2_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68954UL))) +#define bM4_DMA2_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68958UL))) +#define bM4_DMA2_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6895CUL))) +#define bM4_DMA2_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68960UL))) +#define bM4_DMA2_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68964UL))) +#define bM4_DMA2_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68968UL))) +#define bM4_DMA2_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6896CUL))) +#define bM4_DMA2_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68970UL))) +#define bM4_DMA2_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68974UL))) +#define bM4_DMA2_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68978UL))) +#define bM4_DMA2_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6897CUL))) +#define bM4_DMA2_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_LLP0_LLP0 (*((volatile unsigned int*)(0x42A68B08UL))) +#define bM4_DMA2_LLP0_LLP1 (*((volatile unsigned int*)(0x42A68B0CUL))) +#define bM4_DMA2_LLP0_LLP2 (*((volatile unsigned int*)(0x42A68B10UL))) +#define bM4_DMA2_LLP0_LLP3 (*((volatile unsigned int*)(0x42A68B14UL))) +#define bM4_DMA2_LLP0_LLP4 (*((volatile unsigned int*)(0x42A68B18UL))) +#define bM4_DMA2_LLP0_LLP5 (*((volatile unsigned int*)(0x42A68B1CUL))) +#define bM4_DMA2_LLP0_LLP6 (*((volatile unsigned int*)(0x42A68B20UL))) +#define bM4_DMA2_LLP0_LLP7 (*((volatile unsigned int*)(0x42A68B24UL))) +#define bM4_DMA2_LLP0_LLP8 (*((volatile unsigned int*)(0x42A68B28UL))) +#define bM4_DMA2_LLP0_LLP9 (*((volatile unsigned int*)(0x42A68B2CUL))) +#define bM4_DMA2_LLP0_LLP10 (*((volatile unsigned int*)(0x42A68B30UL))) +#define bM4_DMA2_LLP0_LLP11 (*((volatile unsigned int*)(0x42A68B34UL))) +#define bM4_DMA2_LLP0_LLP12 (*((volatile unsigned int*)(0x42A68B38UL))) +#define bM4_DMA2_LLP0_LLP13 (*((volatile unsigned int*)(0x42A68B3CUL))) +#define bM4_DMA2_LLP0_LLP14 (*((volatile unsigned int*)(0x42A68B40UL))) +#define bM4_DMA2_LLP0_LLP15 (*((volatile unsigned int*)(0x42A68B44UL))) +#define bM4_DMA2_LLP0_LLP16 (*((volatile unsigned int*)(0x42A68B48UL))) +#define bM4_DMA2_LLP0_LLP17 (*((volatile unsigned int*)(0x42A68B4CUL))) +#define bM4_DMA2_LLP0_LLP18 (*((volatile unsigned int*)(0x42A68B50UL))) +#define bM4_DMA2_LLP0_LLP19 (*((volatile unsigned int*)(0x42A68B54UL))) +#define bM4_DMA2_LLP0_LLP20 (*((volatile unsigned int*)(0x42A68B58UL))) +#define bM4_DMA2_LLP0_LLP21 (*((volatile unsigned int*)(0x42A68B5CUL))) +#define bM4_DMA2_LLP0_LLP22 (*((volatile unsigned int*)(0x42A68B60UL))) +#define bM4_DMA2_LLP0_LLP23 (*((volatile unsigned int*)(0x42A68B64UL))) +#define bM4_DMA2_LLP0_LLP24 (*((volatile unsigned int*)(0x42A68B68UL))) +#define bM4_DMA2_LLP0_LLP25 (*((volatile unsigned int*)(0x42A68B6CUL))) +#define bM4_DMA2_LLP0_LLP26 (*((volatile unsigned int*)(0x42A68B70UL))) +#define bM4_DMA2_LLP0_LLP27 (*((volatile unsigned int*)(0x42A68B74UL))) +#define bM4_DMA2_LLP0_LLP28 (*((volatile unsigned int*)(0x42A68B78UL))) +#define bM4_DMA2_LLP0_LLP29 (*((volatile unsigned int*)(0x42A68B7CUL))) +#define bM4_DMA2_CHCTL0_SINC0 (*((volatile unsigned int*)(0x42A68B80UL))) +#define bM4_DMA2_CHCTL0_SINC1 (*((volatile unsigned int*)(0x42A68B84UL))) +#define bM4_DMA2_CHCTL0_DINC0 (*((volatile unsigned int*)(0x42A68B88UL))) +#define bM4_DMA2_CHCTL0_DINC1 (*((volatile unsigned int*)(0x42A68B8CUL))) +#define bM4_DMA2_CHCTL0_SRPTEN (*((volatile unsigned int*)(0x42A68B90UL))) +#define bM4_DMA2_CHCTL0_DRPTEN (*((volatile unsigned int*)(0x42A68B94UL))) +#define bM4_DMA2_CHCTL0_SNSEQEN (*((volatile unsigned int*)(0x42A68B98UL))) +#define bM4_DMA2_CHCTL0_DNSEQEN (*((volatile unsigned int*)(0x42A68B9CUL))) +#define bM4_DMA2_CHCTL0_HSIZE0 (*((volatile unsigned int*)(0x42A68BA0UL))) +#define bM4_DMA2_CHCTL0_HSIZE1 (*((volatile unsigned int*)(0x42A68BA4UL))) +#define bM4_DMA2_CHCTL0_LLPEN (*((volatile unsigned int*)(0x42A68BA8UL))) +#define bM4_DMA2_CHCTL0_LLPRUN (*((volatile unsigned int*)(0x42A68BACUL))) +#define bM4_DMA2_CHCTL0_IE (*((volatile unsigned int*)(0x42A68BB0UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68D00UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68D04UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68D08UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A68D0CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68D10UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68D14UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68D18UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A68D1CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68D20UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68D24UL))) +#define bM4_DMA2_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68D40UL))) +#define bM4_DMA2_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68D44UL))) +#define bM4_DMA2_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68D48UL))) +#define bM4_DMA2_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A68D4CUL))) +#define bM4_DMA2_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68D50UL))) +#define bM4_DMA2_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68D54UL))) +#define bM4_DMA2_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68D58UL))) +#define bM4_DMA2_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A68D5CUL))) +#define bM4_DMA2_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68D60UL))) +#define bM4_DMA2_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68D64UL))) +#define bM4_DMA2_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68D68UL))) +#define bM4_DMA2_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A68D6CUL))) +#define bM4_DMA2_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68D70UL))) +#define bM4_DMA2_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68D74UL))) +#define bM4_DMA2_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68D78UL))) +#define bM4_DMA2_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A68D7CUL))) +#define bM4_DMA2_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A68D80UL))) +#define bM4_DMA2_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A68D84UL))) +#define bM4_DMA2_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A68D88UL))) +#define bM4_DMA2_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A68D8CUL))) +#define bM4_DMA2_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A68D90UL))) +#define bM4_DMA2_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A68D94UL))) +#define bM4_DMA2_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A68D98UL))) +#define bM4_DMA2_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A68D9CUL))) +#define bM4_DMA2_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A68DA0UL))) +#define bM4_DMA2_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A68DA4UL))) +#define bM4_DMA2_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A68DC0UL))) +#define bM4_DMA2_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A68DC4UL))) +#define bM4_DMA2_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A68DC8UL))) +#define bM4_DMA2_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A68DCCUL))) +#define bM4_DMA2_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A68DD0UL))) +#define bM4_DMA2_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A68DD4UL))) +#define bM4_DMA2_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A68DD8UL))) +#define bM4_DMA2_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A68DDCUL))) +#define bM4_DMA2_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A68DE0UL))) +#define bM4_DMA2_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A68DE4UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68E00UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68E04UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68E08UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68E0CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68E10UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68E14UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68E18UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68E1CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68E20UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68E24UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68E28UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68E2CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68E30UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68E34UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68E38UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68E3CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68E40UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68E44UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68E48UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68E4CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68E50UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68E54UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68E58UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68E5CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68E60UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68E64UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68E68UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68E6CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68E70UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68E74UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68E78UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68E7CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68E80UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68E84UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68E88UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68E8CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68E90UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68E94UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68E98UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68E9CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68EA0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68EA4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68EA8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68EACUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68EB0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68EB4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68EB8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68EBCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68EC0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68EC4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68EC8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ECCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68ED0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68ED4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68ED8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68EDCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68EE0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68EE4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68EE8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68EECUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68EF0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68EF4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68EF8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68EFCUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69100UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69104UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69108UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6910CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69110UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69114UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69118UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6911CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69120UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69124UL))) +#define bM4_DMA2_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69140UL))) +#define bM4_DMA2_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69144UL))) +#define bM4_DMA2_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69148UL))) +#define bM4_DMA2_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6914CUL))) +#define bM4_DMA2_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69150UL))) +#define bM4_DMA2_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69154UL))) +#define bM4_DMA2_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69158UL))) +#define bM4_DMA2_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6915CUL))) +#define bM4_DMA2_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69160UL))) +#define bM4_DMA2_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69164UL))) +#define bM4_DMA2_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69168UL))) +#define bM4_DMA2_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6916CUL))) +#define bM4_DMA2_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69170UL))) +#define bM4_DMA2_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69174UL))) +#define bM4_DMA2_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69178UL))) +#define bM4_DMA2_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6917CUL))) +#define bM4_DMA2_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_LLP1_LLP0 (*((volatile unsigned int*)(0x42A69308UL))) +#define bM4_DMA2_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6930CUL))) +#define bM4_DMA2_LLP1_LLP2 (*((volatile unsigned int*)(0x42A69310UL))) +#define bM4_DMA2_LLP1_LLP3 (*((volatile unsigned int*)(0x42A69314UL))) +#define bM4_DMA2_LLP1_LLP4 (*((volatile unsigned int*)(0x42A69318UL))) +#define bM4_DMA2_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6931CUL))) +#define bM4_DMA2_LLP1_LLP6 (*((volatile unsigned int*)(0x42A69320UL))) +#define bM4_DMA2_LLP1_LLP7 (*((volatile unsigned int*)(0x42A69324UL))) +#define bM4_DMA2_LLP1_LLP8 (*((volatile unsigned int*)(0x42A69328UL))) +#define bM4_DMA2_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6932CUL))) +#define bM4_DMA2_LLP1_LLP10 (*((volatile unsigned int*)(0x42A69330UL))) +#define bM4_DMA2_LLP1_LLP11 (*((volatile unsigned int*)(0x42A69334UL))) +#define bM4_DMA2_LLP1_LLP12 (*((volatile unsigned int*)(0x42A69338UL))) +#define bM4_DMA2_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6933CUL))) +#define bM4_DMA2_LLP1_LLP14 (*((volatile unsigned int*)(0x42A69340UL))) +#define bM4_DMA2_LLP1_LLP15 (*((volatile unsigned int*)(0x42A69344UL))) +#define bM4_DMA2_LLP1_LLP16 (*((volatile unsigned int*)(0x42A69348UL))) +#define bM4_DMA2_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6934CUL))) +#define bM4_DMA2_LLP1_LLP18 (*((volatile unsigned int*)(0x42A69350UL))) +#define bM4_DMA2_LLP1_LLP19 (*((volatile unsigned int*)(0x42A69354UL))) +#define bM4_DMA2_LLP1_LLP20 (*((volatile unsigned int*)(0x42A69358UL))) +#define bM4_DMA2_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6935CUL))) +#define bM4_DMA2_LLP1_LLP22 (*((volatile unsigned int*)(0x42A69360UL))) +#define bM4_DMA2_LLP1_LLP23 (*((volatile unsigned int*)(0x42A69364UL))) +#define bM4_DMA2_LLP1_LLP24 (*((volatile unsigned int*)(0x42A69368UL))) +#define bM4_DMA2_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6936CUL))) +#define bM4_DMA2_LLP1_LLP26 (*((volatile unsigned int*)(0x42A69370UL))) +#define bM4_DMA2_LLP1_LLP27 (*((volatile unsigned int*)(0x42A69374UL))) +#define bM4_DMA2_LLP1_LLP28 (*((volatile unsigned int*)(0x42A69378UL))) +#define bM4_DMA2_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6937CUL))) +#define bM4_DMA2_CHCTL1_SINC0 (*((volatile unsigned int*)(0x42A69380UL))) +#define bM4_DMA2_CHCTL1_SINC1 (*((volatile unsigned int*)(0x42A69384UL))) +#define bM4_DMA2_CHCTL1_DINC0 (*((volatile unsigned int*)(0x42A69388UL))) +#define bM4_DMA2_CHCTL1_DINC1 (*((volatile unsigned int*)(0x42A6938CUL))) +#define bM4_DMA2_CHCTL1_SRPTEN (*((volatile unsigned int*)(0x42A69390UL))) +#define bM4_DMA2_CHCTL1_DRPTEN (*((volatile unsigned int*)(0x42A69394UL))) +#define bM4_DMA2_CHCTL1_SNSEQEN (*((volatile unsigned int*)(0x42A69398UL))) +#define bM4_DMA2_CHCTL1_DNSEQEN (*((volatile unsigned int*)(0x42A6939CUL))) +#define bM4_DMA2_CHCTL1_HSIZE0 (*((volatile unsigned int*)(0x42A693A0UL))) +#define bM4_DMA2_CHCTL1_HSIZE1 (*((volatile unsigned int*)(0x42A693A4UL))) +#define bM4_DMA2_CHCTL1_LLPEN (*((volatile unsigned int*)(0x42A693A8UL))) +#define bM4_DMA2_CHCTL1_LLPRUN (*((volatile unsigned int*)(0x42A693ACUL))) +#define bM4_DMA2_CHCTL1_IE (*((volatile unsigned int*)(0x42A693B0UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69500UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69504UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69508UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6950CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69510UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69514UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69518UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6951CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69520UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69524UL))) +#define bM4_DMA2_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69540UL))) +#define bM4_DMA2_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69544UL))) +#define bM4_DMA2_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69548UL))) +#define bM4_DMA2_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6954CUL))) +#define bM4_DMA2_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69550UL))) +#define bM4_DMA2_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69554UL))) +#define bM4_DMA2_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69558UL))) +#define bM4_DMA2_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6955CUL))) +#define bM4_DMA2_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69560UL))) +#define bM4_DMA2_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69564UL))) +#define bM4_DMA2_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69568UL))) +#define bM4_DMA2_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6956CUL))) +#define bM4_DMA2_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69570UL))) +#define bM4_DMA2_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69574UL))) +#define bM4_DMA2_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69578UL))) +#define bM4_DMA2_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6957CUL))) +#define bM4_DMA2_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A69580UL))) +#define bM4_DMA2_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A69584UL))) +#define bM4_DMA2_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A69588UL))) +#define bM4_DMA2_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6958CUL))) +#define bM4_DMA2_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A69590UL))) +#define bM4_DMA2_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A69594UL))) +#define bM4_DMA2_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A69598UL))) +#define bM4_DMA2_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6959CUL))) +#define bM4_DMA2_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A695A0UL))) +#define bM4_DMA2_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A695A4UL))) +#define bM4_DMA2_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A695C0UL))) +#define bM4_DMA2_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A695C4UL))) +#define bM4_DMA2_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A695C8UL))) +#define bM4_DMA2_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A695CCUL))) +#define bM4_DMA2_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A695D0UL))) +#define bM4_DMA2_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A695D4UL))) +#define bM4_DMA2_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A695D8UL))) +#define bM4_DMA2_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A695DCUL))) +#define bM4_DMA2_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A695E0UL))) +#define bM4_DMA2_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A695E4UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69600UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69604UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69608UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6960CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69610UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69614UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69618UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6961CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69620UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69624UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69628UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6962CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69630UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69634UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69638UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6963CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69640UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69644UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69648UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6964CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69650UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69654UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69658UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6965CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69660UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69664UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69668UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6966CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69670UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69674UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69678UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6967CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69680UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69684UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69688UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6968CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69690UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69694UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69698UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6969CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A696A0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A696A4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A696A8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A696ACUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A696B0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A696B4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A696B8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A696BCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A696C0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A696C4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A696C8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A696CCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A696D0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A696D4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A696D8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A696DCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A696E0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A696E4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A696E8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A696ECUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A696F0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A696F4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A696F8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A696FCUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69900UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69904UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69908UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6990CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69910UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69914UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69918UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6991CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69920UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69924UL))) +#define bM4_DMA2_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69940UL))) +#define bM4_DMA2_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69944UL))) +#define bM4_DMA2_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69948UL))) +#define bM4_DMA2_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6994CUL))) +#define bM4_DMA2_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69950UL))) +#define bM4_DMA2_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69954UL))) +#define bM4_DMA2_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69958UL))) +#define bM4_DMA2_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6995CUL))) +#define bM4_DMA2_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69960UL))) +#define bM4_DMA2_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69964UL))) +#define bM4_DMA2_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69968UL))) +#define bM4_DMA2_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6996CUL))) +#define bM4_DMA2_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69970UL))) +#define bM4_DMA2_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69974UL))) +#define bM4_DMA2_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69978UL))) +#define bM4_DMA2_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6997CUL))) +#define bM4_DMA2_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_LLP2_LLP0 (*((volatile unsigned int*)(0x42A69B08UL))) +#define bM4_DMA2_LLP2_LLP1 (*((volatile unsigned int*)(0x42A69B0CUL))) +#define bM4_DMA2_LLP2_LLP2 (*((volatile unsigned int*)(0x42A69B10UL))) +#define bM4_DMA2_LLP2_LLP3 (*((volatile unsigned int*)(0x42A69B14UL))) +#define bM4_DMA2_LLP2_LLP4 (*((volatile unsigned int*)(0x42A69B18UL))) +#define bM4_DMA2_LLP2_LLP5 (*((volatile unsigned int*)(0x42A69B1CUL))) +#define bM4_DMA2_LLP2_LLP6 (*((volatile unsigned int*)(0x42A69B20UL))) +#define bM4_DMA2_LLP2_LLP7 (*((volatile unsigned int*)(0x42A69B24UL))) +#define bM4_DMA2_LLP2_LLP8 (*((volatile unsigned int*)(0x42A69B28UL))) +#define bM4_DMA2_LLP2_LLP9 (*((volatile unsigned int*)(0x42A69B2CUL))) +#define bM4_DMA2_LLP2_LLP10 (*((volatile unsigned int*)(0x42A69B30UL))) +#define bM4_DMA2_LLP2_LLP11 (*((volatile unsigned int*)(0x42A69B34UL))) +#define bM4_DMA2_LLP2_LLP12 (*((volatile unsigned int*)(0x42A69B38UL))) +#define bM4_DMA2_LLP2_LLP13 (*((volatile unsigned int*)(0x42A69B3CUL))) +#define bM4_DMA2_LLP2_LLP14 (*((volatile unsigned int*)(0x42A69B40UL))) +#define bM4_DMA2_LLP2_LLP15 (*((volatile unsigned int*)(0x42A69B44UL))) +#define bM4_DMA2_LLP2_LLP16 (*((volatile unsigned int*)(0x42A69B48UL))) +#define bM4_DMA2_LLP2_LLP17 (*((volatile unsigned int*)(0x42A69B4CUL))) +#define bM4_DMA2_LLP2_LLP18 (*((volatile unsigned int*)(0x42A69B50UL))) +#define bM4_DMA2_LLP2_LLP19 (*((volatile unsigned int*)(0x42A69B54UL))) +#define bM4_DMA2_LLP2_LLP20 (*((volatile unsigned int*)(0x42A69B58UL))) +#define bM4_DMA2_LLP2_LLP21 (*((volatile unsigned int*)(0x42A69B5CUL))) +#define bM4_DMA2_LLP2_LLP22 (*((volatile unsigned int*)(0x42A69B60UL))) +#define bM4_DMA2_LLP2_LLP23 (*((volatile unsigned int*)(0x42A69B64UL))) +#define bM4_DMA2_LLP2_LLP24 (*((volatile unsigned int*)(0x42A69B68UL))) +#define bM4_DMA2_LLP2_LLP25 (*((volatile unsigned int*)(0x42A69B6CUL))) +#define bM4_DMA2_LLP2_LLP26 (*((volatile unsigned int*)(0x42A69B70UL))) +#define bM4_DMA2_LLP2_LLP27 (*((volatile unsigned int*)(0x42A69B74UL))) +#define bM4_DMA2_LLP2_LLP28 (*((volatile unsigned int*)(0x42A69B78UL))) +#define bM4_DMA2_LLP2_LLP29 (*((volatile unsigned int*)(0x42A69B7CUL))) +#define bM4_DMA2_CHCTL2_SINC0 (*((volatile unsigned int*)(0x42A69B80UL))) +#define bM4_DMA2_CHCTL2_SINC1 (*((volatile unsigned int*)(0x42A69B84UL))) +#define bM4_DMA2_CHCTL2_DINC0 (*((volatile unsigned int*)(0x42A69B88UL))) +#define bM4_DMA2_CHCTL2_DINC1 (*((volatile unsigned int*)(0x42A69B8CUL))) +#define bM4_DMA2_CHCTL2_SRPTEN (*((volatile unsigned int*)(0x42A69B90UL))) +#define bM4_DMA2_CHCTL2_DRPTEN (*((volatile unsigned int*)(0x42A69B94UL))) +#define bM4_DMA2_CHCTL2_SNSEQEN (*((volatile unsigned int*)(0x42A69B98UL))) +#define bM4_DMA2_CHCTL2_DNSEQEN (*((volatile unsigned int*)(0x42A69B9CUL))) +#define bM4_DMA2_CHCTL2_HSIZE0 (*((volatile unsigned int*)(0x42A69BA0UL))) +#define bM4_DMA2_CHCTL2_HSIZE1 (*((volatile unsigned int*)(0x42A69BA4UL))) +#define bM4_DMA2_CHCTL2_LLPEN (*((volatile unsigned int*)(0x42A69BA8UL))) +#define bM4_DMA2_CHCTL2_LLPRUN (*((volatile unsigned int*)(0x42A69BACUL))) +#define bM4_DMA2_CHCTL2_IE (*((volatile unsigned int*)(0x42A69BB0UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69D00UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69D04UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69D08UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A69D0CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69D10UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69D14UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69D18UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A69D1CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69D20UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69D24UL))) +#define bM4_DMA2_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69D40UL))) +#define bM4_DMA2_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69D44UL))) +#define bM4_DMA2_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69D48UL))) +#define bM4_DMA2_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A69D4CUL))) +#define bM4_DMA2_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69D50UL))) +#define bM4_DMA2_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69D54UL))) +#define bM4_DMA2_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69D58UL))) +#define bM4_DMA2_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A69D5CUL))) +#define bM4_DMA2_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69D60UL))) +#define bM4_DMA2_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69D64UL))) +#define bM4_DMA2_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69D68UL))) +#define bM4_DMA2_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A69D6CUL))) +#define bM4_DMA2_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69D70UL))) +#define bM4_DMA2_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69D74UL))) +#define bM4_DMA2_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69D78UL))) +#define bM4_DMA2_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A69D7CUL))) +#define bM4_DMA2_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A69D80UL))) +#define bM4_DMA2_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A69D84UL))) +#define bM4_DMA2_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A69D88UL))) +#define bM4_DMA2_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A69D8CUL))) +#define bM4_DMA2_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A69D90UL))) +#define bM4_DMA2_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A69D94UL))) +#define bM4_DMA2_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A69D98UL))) +#define bM4_DMA2_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A69D9CUL))) +#define bM4_DMA2_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A69DA0UL))) +#define bM4_DMA2_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A69DA4UL))) +#define bM4_DMA2_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A69DC0UL))) +#define bM4_DMA2_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A69DC4UL))) +#define bM4_DMA2_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A69DC8UL))) +#define bM4_DMA2_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A69DCCUL))) +#define bM4_DMA2_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A69DD0UL))) +#define bM4_DMA2_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A69DD4UL))) +#define bM4_DMA2_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A69DD8UL))) +#define bM4_DMA2_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A69DDCUL))) +#define bM4_DMA2_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A69DE0UL))) +#define bM4_DMA2_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A69DE4UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69E00UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69E04UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69E08UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69E0CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69E10UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69E14UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69E18UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69E1CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69E20UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69E24UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69E28UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69E2CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69E30UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69E34UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69E38UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69E3CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69E40UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69E44UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69E48UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69E4CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69E50UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69E54UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69E58UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69E5CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69E60UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69E64UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69E68UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69E6CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69E70UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69E74UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69E78UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69E7CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69E80UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69E84UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69E88UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69E8CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69E90UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69E94UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69E98UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69E9CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69EA0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69EA4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69EA8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69EACUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69EB0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69EB4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69EB8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69EBCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69EC0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69EC4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69EC8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ECCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69ED0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69ED4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69ED8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69EDCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69EE0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69EE4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69EE8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69EECUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69EF0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69EF4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69EF8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69EFCUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A100UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A104UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A108UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A10CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A110UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A114UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A118UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A11CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A120UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A124UL))) +#define bM4_DMA2_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A140UL))) +#define bM4_DMA2_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A144UL))) +#define bM4_DMA2_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A148UL))) +#define bM4_DMA2_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A14CUL))) +#define bM4_DMA2_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A150UL))) +#define bM4_DMA2_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A154UL))) +#define bM4_DMA2_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A158UL))) +#define bM4_DMA2_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A15CUL))) +#define bM4_DMA2_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A160UL))) +#define bM4_DMA2_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A164UL))) +#define bM4_DMA2_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A168UL))) +#define bM4_DMA2_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A16CUL))) +#define bM4_DMA2_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A170UL))) +#define bM4_DMA2_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A174UL))) +#define bM4_DMA2_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A178UL))) +#define bM4_DMA2_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A17CUL))) +#define bM4_DMA2_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_LLP3_LLP0 (*((volatile unsigned int*)(0x42A6A308UL))) +#define bM4_DMA2_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6A30CUL))) +#define bM4_DMA2_LLP3_LLP2 (*((volatile unsigned int*)(0x42A6A310UL))) +#define bM4_DMA2_LLP3_LLP3 (*((volatile unsigned int*)(0x42A6A314UL))) +#define bM4_DMA2_LLP3_LLP4 (*((volatile unsigned int*)(0x42A6A318UL))) +#define bM4_DMA2_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6A31CUL))) +#define bM4_DMA2_LLP3_LLP6 (*((volatile unsigned int*)(0x42A6A320UL))) +#define bM4_DMA2_LLP3_LLP7 (*((volatile unsigned int*)(0x42A6A324UL))) +#define bM4_DMA2_LLP3_LLP8 (*((volatile unsigned int*)(0x42A6A328UL))) +#define bM4_DMA2_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6A32CUL))) +#define bM4_DMA2_LLP3_LLP10 (*((volatile unsigned int*)(0x42A6A330UL))) +#define bM4_DMA2_LLP3_LLP11 (*((volatile unsigned int*)(0x42A6A334UL))) +#define bM4_DMA2_LLP3_LLP12 (*((volatile unsigned int*)(0x42A6A338UL))) +#define bM4_DMA2_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6A33CUL))) +#define bM4_DMA2_LLP3_LLP14 (*((volatile unsigned int*)(0x42A6A340UL))) +#define bM4_DMA2_LLP3_LLP15 (*((volatile unsigned int*)(0x42A6A344UL))) +#define bM4_DMA2_LLP3_LLP16 (*((volatile unsigned int*)(0x42A6A348UL))) +#define bM4_DMA2_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6A34CUL))) +#define bM4_DMA2_LLP3_LLP18 (*((volatile unsigned int*)(0x42A6A350UL))) +#define bM4_DMA2_LLP3_LLP19 (*((volatile unsigned int*)(0x42A6A354UL))) +#define bM4_DMA2_LLP3_LLP20 (*((volatile unsigned int*)(0x42A6A358UL))) +#define bM4_DMA2_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6A35CUL))) +#define bM4_DMA2_LLP3_LLP22 (*((volatile unsigned int*)(0x42A6A360UL))) +#define bM4_DMA2_LLP3_LLP23 (*((volatile unsigned int*)(0x42A6A364UL))) +#define bM4_DMA2_LLP3_LLP24 (*((volatile unsigned int*)(0x42A6A368UL))) +#define bM4_DMA2_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6A36CUL))) +#define bM4_DMA2_LLP3_LLP26 (*((volatile unsigned int*)(0x42A6A370UL))) +#define bM4_DMA2_LLP3_LLP27 (*((volatile unsigned int*)(0x42A6A374UL))) +#define bM4_DMA2_LLP3_LLP28 (*((volatile unsigned int*)(0x42A6A378UL))) +#define bM4_DMA2_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6A37CUL))) +#define bM4_DMA2_CHCTL3_SINC0 (*((volatile unsigned int*)(0x42A6A380UL))) +#define bM4_DMA2_CHCTL3_SINC1 (*((volatile unsigned int*)(0x42A6A384UL))) +#define bM4_DMA2_CHCTL3_DINC0 (*((volatile unsigned int*)(0x42A6A388UL))) +#define bM4_DMA2_CHCTL3_DINC1 (*((volatile unsigned int*)(0x42A6A38CUL))) +#define bM4_DMA2_CHCTL3_SRPTEN (*((volatile unsigned int*)(0x42A6A390UL))) +#define bM4_DMA2_CHCTL3_DRPTEN (*((volatile unsigned int*)(0x42A6A394UL))) +#define bM4_DMA2_CHCTL3_SNSEQEN (*((volatile unsigned int*)(0x42A6A398UL))) +#define bM4_DMA2_CHCTL3_DNSEQEN (*((volatile unsigned int*)(0x42A6A39CUL))) +#define bM4_DMA2_CHCTL3_HSIZE0 (*((volatile unsigned int*)(0x42A6A3A0UL))) +#define bM4_DMA2_CHCTL3_HSIZE1 (*((volatile unsigned int*)(0x42A6A3A4UL))) +#define bM4_DMA2_CHCTL3_LLPEN (*((volatile unsigned int*)(0x42A6A3A8UL))) +#define bM4_DMA2_CHCTL3_LLPRUN (*((volatile unsigned int*)(0x42A6A3ACUL))) +#define bM4_DMA2_CHCTL3_IE (*((volatile unsigned int*)(0x42A6A3B0UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A500UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A504UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A508UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A50CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A510UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A514UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A518UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A51CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A520UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A524UL))) +#define bM4_DMA2_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A540UL))) +#define bM4_DMA2_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A544UL))) +#define bM4_DMA2_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A548UL))) +#define bM4_DMA2_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A54CUL))) +#define bM4_DMA2_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A550UL))) +#define bM4_DMA2_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A554UL))) +#define bM4_DMA2_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A558UL))) +#define bM4_DMA2_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A55CUL))) +#define bM4_DMA2_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A560UL))) +#define bM4_DMA2_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A564UL))) +#define bM4_DMA2_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A568UL))) +#define bM4_DMA2_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A56CUL))) +#define bM4_DMA2_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A570UL))) +#define bM4_DMA2_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A574UL))) +#define bM4_DMA2_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A578UL))) +#define bM4_DMA2_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A57CUL))) +#define bM4_DMA2_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A580UL))) +#define bM4_DMA2_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A584UL))) +#define bM4_DMA2_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A588UL))) +#define bM4_DMA2_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A58CUL))) +#define bM4_DMA2_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A590UL))) +#define bM4_DMA2_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A594UL))) +#define bM4_DMA2_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A598UL))) +#define bM4_DMA2_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A59CUL))) +#define bM4_DMA2_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A5A0UL))) +#define bM4_DMA2_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A5A4UL))) +#define bM4_DMA2_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A5C0UL))) +#define bM4_DMA2_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A5C4UL))) +#define bM4_DMA2_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A5C8UL))) +#define bM4_DMA2_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A5CCUL))) +#define bM4_DMA2_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A5D0UL))) +#define bM4_DMA2_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A5D4UL))) +#define bM4_DMA2_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A5D8UL))) +#define bM4_DMA2_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A5DCUL))) +#define bM4_DMA2_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A5E0UL))) +#define bM4_DMA2_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A5E4UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A600UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A604UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A608UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A60CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A610UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A614UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A618UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A61CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A620UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A624UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A628UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A62CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A630UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A634UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A638UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A63CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A640UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A644UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A648UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A64CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A650UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A654UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A658UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A65CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A660UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A664UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A668UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A66CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A670UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A674UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A678UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A67CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A680UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A684UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A688UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A68CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A690UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A694UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A698UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A69CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A6A0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A6A4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A6A8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A6ACUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A6B0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A6B4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A6B8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A6BCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A6C0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A6C4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A6C8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A6CCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A6D0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A6D4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A6D8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A6DCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A6E0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A6E4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A6E8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A6ECUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A6F0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A6F4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A6F8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A6FCUL))) +#define bM4_EFM_FAPRT_FAPRT0 (*((volatile unsigned int*)(0x42208000UL))) +#define bM4_EFM_FAPRT_FAPRT1 (*((volatile unsigned int*)(0x42208004UL))) +#define bM4_EFM_FAPRT_FAPRT2 (*((volatile unsigned int*)(0x42208008UL))) +#define bM4_EFM_FAPRT_FAPRT3 (*((volatile unsigned int*)(0x4220800CUL))) +#define bM4_EFM_FAPRT_FAPRT4 (*((volatile unsigned int*)(0x42208010UL))) +#define bM4_EFM_FAPRT_FAPRT5 (*((volatile unsigned int*)(0x42208014UL))) +#define bM4_EFM_FAPRT_FAPRT6 (*((volatile unsigned int*)(0x42208018UL))) +#define bM4_EFM_FAPRT_FAPRT7 (*((volatile unsigned int*)(0x4220801CUL))) +#define bM4_EFM_FAPRT_FAPRT8 (*((volatile unsigned int*)(0x42208020UL))) +#define bM4_EFM_FAPRT_FAPRT9 (*((volatile unsigned int*)(0x42208024UL))) +#define bM4_EFM_FAPRT_FAPRT10 (*((volatile unsigned int*)(0x42208028UL))) +#define bM4_EFM_FAPRT_FAPRT11 (*((volatile unsigned int*)(0x4220802CUL))) +#define bM4_EFM_FAPRT_FAPRT12 (*((volatile unsigned int*)(0x42208030UL))) +#define bM4_EFM_FAPRT_FAPRT13 (*((volatile unsigned int*)(0x42208034UL))) +#define bM4_EFM_FAPRT_FAPRT14 (*((volatile unsigned int*)(0x42208038UL))) +#define bM4_EFM_FAPRT_FAPRT15 (*((volatile unsigned int*)(0x4220803CUL))) +#define bM4_EFM_FSTP_FSTP (*((volatile unsigned int*)(0x42208080UL))) +#define bM4_EFM_FRMC_SLPMD (*((volatile unsigned int*)(0x42208100UL))) +#define bM4_EFM_FRMC_FLWT0 (*((volatile unsigned int*)(0x42208110UL))) +#define bM4_EFM_FRMC_FLWT1 (*((volatile unsigned int*)(0x42208114UL))) +#define bM4_EFM_FRMC_FLWT2 (*((volatile unsigned int*)(0x42208118UL))) +#define bM4_EFM_FRMC_FLWT3 (*((volatile unsigned int*)(0x4220811CUL))) +#define bM4_EFM_FRMC_LVM (*((volatile unsigned int*)(0x42208120UL))) +#define bM4_EFM_FRMC_CACHE (*((volatile unsigned int*)(0x42208140UL))) +#define bM4_EFM_FRMC_CRST (*((volatile unsigned int*)(0x42208160UL))) +#define bM4_EFM_FWMC_PEMODE (*((volatile unsigned int*)(0x42208180UL))) +#define bM4_EFM_FWMC_PEMOD0 (*((volatile unsigned int*)(0x42208190UL))) +#define bM4_EFM_FWMC_PEMOD1 (*((volatile unsigned int*)(0x42208194UL))) +#define bM4_EFM_FWMC_PEMOD2 (*((volatile unsigned int*)(0x42208198UL))) +#define bM4_EFM_FWMC_BUSHLDCTL (*((volatile unsigned int*)(0x422081A0UL))) +#define bM4_EFM_FSR_PEWERR (*((volatile unsigned int*)(0x42208200UL))) +#define bM4_EFM_FSR_PEPRTERR (*((volatile unsigned int*)(0x42208204UL))) +#define bM4_EFM_FSR_PGSZERR (*((volatile unsigned int*)(0x42208208UL))) +#define bM4_EFM_FSR_PGMISMTCH (*((volatile unsigned int*)(0x4220820CUL))) +#define bM4_EFM_FSR_OPTEND (*((volatile unsigned int*)(0x42208210UL))) +#define bM4_EFM_FSR_COLERR (*((volatile unsigned int*)(0x42208214UL))) +#define bM4_EFM_FSR_RDY (*((volatile unsigned int*)(0x42208220UL))) +#define bM4_EFM_FSCLR_PEWERRCLR (*((volatile unsigned int*)(0x42208280UL))) +#define bM4_EFM_FSCLR_PEPRTERRCLR (*((volatile unsigned int*)(0x42208284UL))) +#define bM4_EFM_FSCLR_PGSZERRCLR (*((volatile unsigned int*)(0x42208288UL))) +#define bM4_EFM_FSCLR_PGMISMTCHCLR (*((volatile unsigned int*)(0x4220828CUL))) +#define bM4_EFM_FSCLR_OPTENDCLR (*((volatile unsigned int*)(0x42208290UL))) +#define bM4_EFM_FSCLR_COLERRCLR (*((volatile unsigned int*)(0x42208294UL))) +#define bM4_EFM_FITE_PEERRITE (*((volatile unsigned int*)(0x42208300UL))) +#define bM4_EFM_FITE_OPTENDITE (*((volatile unsigned int*)(0x42208304UL))) +#define bM4_EFM_FITE_COLERRITE (*((volatile unsigned int*)(0x42208308UL))) +#define bM4_EFM_FSWP_FSWP (*((volatile unsigned int*)(0x42208380UL))) +#define bM4_EFM_FPMTSW_FPMTSW0 (*((volatile unsigned int*)(0x42208400UL))) +#define bM4_EFM_FPMTSW_FPMTSW1 (*((volatile unsigned int*)(0x42208404UL))) +#define bM4_EFM_FPMTSW_FPMTSW2 (*((volatile unsigned int*)(0x42208408UL))) +#define bM4_EFM_FPMTSW_FPMTSW3 (*((volatile unsigned int*)(0x4220840CUL))) +#define bM4_EFM_FPMTSW_FPMTSW4 (*((volatile unsigned int*)(0x42208410UL))) +#define bM4_EFM_FPMTSW_FPMTSW5 (*((volatile unsigned int*)(0x42208414UL))) +#define bM4_EFM_FPMTSW_FPMTSW6 (*((volatile unsigned int*)(0x42208418UL))) +#define bM4_EFM_FPMTSW_FPMTSW7 (*((volatile unsigned int*)(0x4220841CUL))) +#define bM4_EFM_FPMTSW_FPMTSW8 (*((volatile unsigned int*)(0x42208420UL))) +#define bM4_EFM_FPMTSW_FPMTSW9 (*((volatile unsigned int*)(0x42208424UL))) +#define bM4_EFM_FPMTSW_FPMTSW10 (*((volatile unsigned int*)(0x42208428UL))) +#define bM4_EFM_FPMTSW_FPMTSW11 (*((volatile unsigned int*)(0x4220842CUL))) +#define bM4_EFM_FPMTSW_FPMTSW12 (*((volatile unsigned int*)(0x42208430UL))) +#define bM4_EFM_FPMTSW_FPMTSW13 (*((volatile unsigned int*)(0x42208434UL))) +#define bM4_EFM_FPMTSW_FPMTSW14 (*((volatile unsigned int*)(0x42208438UL))) +#define bM4_EFM_FPMTSW_FPMTSW15 (*((volatile unsigned int*)(0x4220843CUL))) +#define bM4_EFM_FPMTSW_FPMTSW16 (*((volatile unsigned int*)(0x42208440UL))) +#define bM4_EFM_FPMTSW_FPMTSW17 (*((volatile unsigned int*)(0x42208444UL))) +#define bM4_EFM_FPMTSW_FPMTSW18 (*((volatile unsigned int*)(0x42208448UL))) +#define bM4_EFM_FPMTEW_FPMTEW0 (*((volatile unsigned int*)(0x42208480UL))) +#define bM4_EFM_FPMTEW_FPMTEW1 (*((volatile unsigned int*)(0x42208484UL))) +#define bM4_EFM_FPMTEW_FPMTEW2 (*((volatile unsigned int*)(0x42208488UL))) +#define bM4_EFM_FPMTEW_FPMTEW3 (*((volatile unsigned int*)(0x4220848CUL))) +#define bM4_EFM_FPMTEW_FPMTEW4 (*((volatile unsigned int*)(0x42208490UL))) +#define bM4_EFM_FPMTEW_FPMTEW5 (*((volatile unsigned int*)(0x42208494UL))) +#define bM4_EFM_FPMTEW_FPMTEW6 (*((volatile unsigned int*)(0x42208498UL))) +#define bM4_EFM_FPMTEW_FPMTEW7 (*((volatile unsigned int*)(0x4220849CUL))) +#define bM4_EFM_FPMTEW_FPMTEW8 (*((volatile unsigned int*)(0x422084A0UL))) +#define bM4_EFM_FPMTEW_FPMTEW9 (*((volatile unsigned int*)(0x422084A4UL))) +#define bM4_EFM_FPMTEW_FPMTEW10 (*((volatile unsigned int*)(0x422084A8UL))) +#define bM4_EFM_FPMTEW_FPMTEW11 (*((volatile unsigned int*)(0x422084ACUL))) +#define bM4_EFM_FPMTEW_FPMTEW12 (*((volatile unsigned int*)(0x422084B0UL))) +#define bM4_EFM_FPMTEW_FPMTEW13 (*((volatile unsigned int*)(0x422084B4UL))) +#define bM4_EFM_FPMTEW_FPMTEW14 (*((volatile unsigned int*)(0x422084B8UL))) +#define bM4_EFM_FPMTEW_FPMTEW15 (*((volatile unsigned int*)(0x422084BCUL))) +#define bM4_EFM_FPMTEW_FPMTEW16 (*((volatile unsigned int*)(0x422084C0UL))) +#define bM4_EFM_FPMTEW_FPMTEW17 (*((volatile unsigned int*)(0x422084C4UL))) +#define bM4_EFM_FPMTEW_FPMTEW18 (*((volatile unsigned int*)(0x422084C8UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT0 (*((volatile unsigned int*)(0x4220A000UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT1 (*((volatile unsigned int*)(0x4220A004UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT2 (*((volatile unsigned int*)(0x4220A008UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT3 (*((volatile unsigned int*)(0x4220A00CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT4 (*((volatile unsigned int*)(0x4220A010UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT5 (*((volatile unsigned int*)(0x4220A014UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT6 (*((volatile unsigned int*)(0x4220A018UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT7 (*((volatile unsigned int*)(0x4220A01CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT8 (*((volatile unsigned int*)(0x4220A020UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT9 (*((volatile unsigned int*)(0x4220A024UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT10 (*((volatile unsigned int*)(0x4220A028UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT11 (*((volatile unsigned int*)(0x4220A02CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT12 (*((volatile unsigned int*)(0x4220A030UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT13 (*((volatile unsigned int*)(0x4220A034UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT14 (*((volatile unsigned int*)(0x4220A038UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT15 (*((volatile unsigned int*)(0x4220A03CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE0 (*((volatile unsigned int*)(0x4220A080UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE1 (*((volatile unsigned int*)(0x4220A084UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE2 (*((volatile unsigned int*)(0x4220A088UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE3 (*((volatile unsigned int*)(0x4220A08CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE4 (*((volatile unsigned int*)(0x4220A090UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR0 (*((volatile unsigned int*)(0x4220A0B0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR1 (*((volatile unsigned int*)(0x4220A0B4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR2 (*((volatile unsigned int*)(0x4220A0B8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR3 (*((volatile unsigned int*)(0x4220A0BCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR4 (*((volatile unsigned int*)(0x4220A0C0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR5 (*((volatile unsigned int*)(0x4220A0C4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR6 (*((volatile unsigned int*)(0x4220A0C8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR7 (*((volatile unsigned int*)(0x4220A0CCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR8 (*((volatile unsigned int*)(0x4220A0D0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR9 (*((volatile unsigned int*)(0x4220A0D4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR10 (*((volatile unsigned int*)(0x4220A0D8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR11 (*((volatile unsigned int*)(0x4220A0DCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR12 (*((volatile unsigned int*)(0x4220A0E0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR13 (*((volatile unsigned int*)(0x4220A0E4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR14 (*((volatile unsigned int*)(0x4220A0E8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR15 (*((volatile unsigned int*)(0x4220A0ECUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR16 (*((volatile unsigned int*)(0x4220A0F0UL))) +#define bM4_EFM_MMF_REMCR0_EN0 (*((volatile unsigned int*)(0x4220A0FCUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE0 (*((volatile unsigned int*)(0x4220A100UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE1 (*((volatile unsigned int*)(0x4220A104UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE2 (*((volatile unsigned int*)(0x4220A108UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE3 (*((volatile unsigned int*)(0x4220A10CUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE4 (*((volatile unsigned int*)(0x4220A110UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR0 (*((volatile unsigned int*)(0x4220A130UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR1 (*((volatile unsigned int*)(0x4220A134UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR2 (*((volatile unsigned int*)(0x4220A138UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR3 (*((volatile unsigned int*)(0x4220A13CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR4 (*((volatile unsigned int*)(0x4220A140UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR5 (*((volatile unsigned int*)(0x4220A144UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR6 (*((volatile unsigned int*)(0x4220A148UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR7 (*((volatile unsigned int*)(0x4220A14CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR8 (*((volatile unsigned int*)(0x4220A150UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR9 (*((volatile unsigned int*)(0x4220A154UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR10 (*((volatile unsigned int*)(0x4220A158UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR11 (*((volatile unsigned int*)(0x4220A15CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR12 (*((volatile unsigned int*)(0x4220A160UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR13 (*((volatile unsigned int*)(0x4220A164UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR14 (*((volatile unsigned int*)(0x4220A168UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR15 (*((volatile unsigned int*)(0x4220A16CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR16 (*((volatile unsigned int*)(0x4220A170UL))) +#define bM4_EFM_MMF_REMCR1_EN1 (*((volatile unsigned int*)(0x4220A17CUL))) +#define bM4_EFM_FRANDS_FRANDS0 (*((volatile unsigned int*)(0x4220C084UL))) +#define bM4_EFM_FRANDS_FRANDS1 (*((volatile unsigned int*)(0x4220C088UL))) +#define bM4_EFM_FRANDS_FRANDS2 (*((volatile unsigned int*)(0x4220C08CUL))) +#define bM4_EFM_FRANDS_FRANDS3 (*((volatile unsigned int*)(0x4220C090UL))) +#define bM4_EFM_FRANDS_FRANDS4 (*((volatile unsigned int*)(0x4220C094UL))) +#define bM4_EFM_FRANDS_FRANDS5 (*((volatile unsigned int*)(0x4220C098UL))) +#define bM4_EFM_FRANDS_FRANDS6 (*((volatile unsigned int*)(0x4220C09CUL))) +#define bM4_EFM_FRANDS_FRANDS7 (*((volatile unsigned int*)(0x4220C0A0UL))) +#define bM4_EFM_FRANDS_FRANDS8 (*((volatile unsigned int*)(0x4220C0A4UL))) +#define bM4_EFM_FRANDS_FRANDS9 (*((volatile unsigned int*)(0x4220C0A8UL))) +#define bM4_EFM_FRANDS_FRANDS10 (*((volatile unsigned int*)(0x4220C0ACUL))) +#define bM4_EFM_FRANDS_FRANDS11 (*((volatile unsigned int*)(0x4220C0B0UL))) +#define bM4_EFM_FRANDS_FRANDS12 (*((volatile unsigned int*)(0x4220C0B4UL))) +#define bM4_EFM_FRANDS_FRANDS13 (*((volatile unsigned int*)(0x4220C0B8UL))) +#define bM4_EFM_FRANDS_FRANDFG (*((volatile unsigned int*)(0x4220C0C0UL))) +#define bM4_EMB1_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8000UL))) +#define bM4_EMB1_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8004UL))) +#define bM4_EMB1_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8008UL))) +#define bM4_EMB1_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F800CUL))) +#define bM4_EMB1_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8014UL))) +#define bM4_EMB1_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8018UL))) +#define bM4_EMB1_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F801CUL))) +#define bM4_EMB1_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8020UL))) +#define bM4_EMB1_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8070UL))) +#define bM4_EMB1_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8074UL))) +#define bM4_EMB1_CTL_NFEN (*((volatile unsigned int*)(0x422F8078UL))) +#define bM4_EMB1_CTL_INVSEL (*((volatile unsigned int*)(0x422F807CUL))) +#define bM4_EMB1_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8080UL))) +#define bM4_EMB1_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8084UL))) +#define bM4_EMB1_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8088UL))) +#define bM4_EMB1_SOE_SOE (*((volatile unsigned int*)(0x422F8100UL))) +#define bM4_EMB1_STAT_PORTINF (*((volatile unsigned int*)(0x422F8180UL))) +#define bM4_EMB1_STAT_PWMSF (*((volatile unsigned int*)(0x422F8184UL))) +#define bM4_EMB1_STAT_CMPF (*((volatile unsigned int*)(0x422F8188UL))) +#define bM4_EMB1_STAT_OSF (*((volatile unsigned int*)(0x422F818CUL))) +#define bM4_EMB1_STAT_PORTINST (*((volatile unsigned int*)(0x422F8190UL))) +#define bM4_EMB1_STAT_PWMST (*((volatile unsigned int*)(0x422F8194UL))) +#define bM4_EMB1_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8200UL))) +#define bM4_EMB1_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8204UL))) +#define bM4_EMB1_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8208UL))) +#define bM4_EMB1_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F820CUL))) +#define bM4_EMB1_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8280UL))) +#define bM4_EMB1_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8284UL))) +#define bM4_EMB1_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8288UL))) +#define bM4_EMB1_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F828CUL))) +#define bM4_EMB2_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8400UL))) +#define bM4_EMB2_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8404UL))) +#define bM4_EMB2_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8408UL))) +#define bM4_EMB2_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F840CUL))) +#define bM4_EMB2_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8414UL))) +#define bM4_EMB2_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8418UL))) +#define bM4_EMB2_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F841CUL))) +#define bM4_EMB2_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8420UL))) +#define bM4_EMB2_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8470UL))) +#define bM4_EMB2_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8474UL))) +#define bM4_EMB2_CTL_NFEN (*((volatile unsigned int*)(0x422F8478UL))) +#define bM4_EMB2_CTL_INVSEL (*((volatile unsigned int*)(0x422F847CUL))) +#define bM4_EMB2_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8480UL))) +#define bM4_EMB2_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8484UL))) +#define bM4_EMB2_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8488UL))) +#define bM4_EMB2_SOE_SOE (*((volatile unsigned int*)(0x422F8500UL))) +#define bM4_EMB2_STAT_PORTINF (*((volatile unsigned int*)(0x422F8580UL))) +#define bM4_EMB2_STAT_PWMSF (*((volatile unsigned int*)(0x422F8584UL))) +#define bM4_EMB2_STAT_CMPF (*((volatile unsigned int*)(0x422F8588UL))) +#define bM4_EMB2_STAT_OSF (*((volatile unsigned int*)(0x422F858CUL))) +#define bM4_EMB2_STAT_PORTINST (*((volatile unsigned int*)(0x422F8590UL))) +#define bM4_EMB2_STAT_PWMST (*((volatile unsigned int*)(0x422F8594UL))) +#define bM4_EMB2_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8600UL))) +#define bM4_EMB2_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8604UL))) +#define bM4_EMB2_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8608UL))) +#define bM4_EMB2_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F860CUL))) +#define bM4_EMB2_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8680UL))) +#define bM4_EMB2_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8684UL))) +#define bM4_EMB2_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8688UL))) +#define bM4_EMB2_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F868CUL))) +#define bM4_EMB3_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8800UL))) +#define bM4_EMB3_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8804UL))) +#define bM4_EMB3_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8808UL))) +#define bM4_EMB3_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F880CUL))) +#define bM4_EMB3_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8814UL))) +#define bM4_EMB3_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8818UL))) +#define bM4_EMB3_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F881CUL))) +#define bM4_EMB3_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8820UL))) +#define bM4_EMB3_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8870UL))) +#define bM4_EMB3_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8874UL))) +#define bM4_EMB3_CTL_NFEN (*((volatile unsigned int*)(0x422F8878UL))) +#define bM4_EMB3_CTL_INVSEL (*((volatile unsigned int*)(0x422F887CUL))) +#define bM4_EMB3_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8880UL))) +#define bM4_EMB3_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8884UL))) +#define bM4_EMB3_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8888UL))) +#define bM4_EMB3_SOE_SOE (*((volatile unsigned int*)(0x422F8900UL))) +#define bM4_EMB3_STAT_PORTINF (*((volatile unsigned int*)(0x422F8980UL))) +#define bM4_EMB3_STAT_PWMSF (*((volatile unsigned int*)(0x422F8984UL))) +#define bM4_EMB3_STAT_CMPF (*((volatile unsigned int*)(0x422F8988UL))) +#define bM4_EMB3_STAT_OSF (*((volatile unsigned int*)(0x422F898CUL))) +#define bM4_EMB3_STAT_PORTINST (*((volatile unsigned int*)(0x422F8990UL))) +#define bM4_EMB3_STAT_PWMST (*((volatile unsigned int*)(0x422F8994UL))) +#define bM4_EMB3_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8A00UL))) +#define bM4_EMB3_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8A04UL))) +#define bM4_EMB3_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8A08UL))) +#define bM4_EMB3_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8A0CUL))) +#define bM4_EMB3_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8A80UL))) +#define bM4_EMB3_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8A84UL))) +#define bM4_EMB3_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8A88UL))) +#define bM4_EMB3_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8A8CUL))) +#define bM4_EMB4_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8C00UL))) +#define bM4_EMB4_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8C04UL))) +#define bM4_EMB4_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8C08UL))) +#define bM4_EMB4_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F8C0CUL))) +#define bM4_EMB4_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8C14UL))) +#define bM4_EMB4_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8C18UL))) +#define bM4_EMB4_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F8C1CUL))) +#define bM4_EMB4_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8C20UL))) +#define bM4_EMB4_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8C70UL))) +#define bM4_EMB4_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8C74UL))) +#define bM4_EMB4_CTL_NFEN (*((volatile unsigned int*)(0x422F8C78UL))) +#define bM4_EMB4_CTL_INVSEL (*((volatile unsigned int*)(0x422F8C7CUL))) +#define bM4_EMB4_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8C80UL))) +#define bM4_EMB4_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8C84UL))) +#define bM4_EMB4_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8C88UL))) +#define bM4_EMB4_SOE_SOE (*((volatile unsigned int*)(0x422F8D00UL))) +#define bM4_EMB4_STAT_PORTINF (*((volatile unsigned int*)(0x422F8D80UL))) +#define bM4_EMB4_STAT_PWMSF (*((volatile unsigned int*)(0x422F8D84UL))) +#define bM4_EMB4_STAT_CMPF (*((volatile unsigned int*)(0x422F8D88UL))) +#define bM4_EMB4_STAT_OSF (*((volatile unsigned int*)(0x422F8D8CUL))) +#define bM4_EMB4_STAT_PORTINST (*((volatile unsigned int*)(0x422F8D90UL))) +#define bM4_EMB4_STAT_PWMST (*((volatile unsigned int*)(0x422F8D94UL))) +#define bM4_EMB4_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8E00UL))) +#define bM4_EMB4_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8E04UL))) +#define bM4_EMB4_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8E08UL))) +#define bM4_EMB4_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8E0CUL))) +#define bM4_EMB4_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8E80UL))) +#define bM4_EMB4_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8E84UL))) +#define bM4_EMB4_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8E88UL))) +#define bM4_EMB4_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8E8CUL))) +#define bM4_FCM_LVR_LVR0 (*((volatile unsigned int*)(0x42908000UL))) +#define bM4_FCM_LVR_LVR1 (*((volatile unsigned int*)(0x42908004UL))) +#define bM4_FCM_LVR_LVR2 (*((volatile unsigned int*)(0x42908008UL))) +#define bM4_FCM_LVR_LVR3 (*((volatile unsigned int*)(0x4290800CUL))) +#define bM4_FCM_LVR_LVR4 (*((volatile unsigned int*)(0x42908010UL))) +#define bM4_FCM_LVR_LVR5 (*((volatile unsigned int*)(0x42908014UL))) +#define bM4_FCM_LVR_LVR6 (*((volatile unsigned int*)(0x42908018UL))) +#define bM4_FCM_LVR_LVR7 (*((volatile unsigned int*)(0x4290801CUL))) +#define bM4_FCM_LVR_LVR8 (*((volatile unsigned int*)(0x42908020UL))) +#define bM4_FCM_LVR_LVR9 (*((volatile unsigned int*)(0x42908024UL))) +#define bM4_FCM_LVR_LVR10 (*((volatile unsigned int*)(0x42908028UL))) +#define bM4_FCM_LVR_LVR11 (*((volatile unsigned int*)(0x4290802CUL))) +#define bM4_FCM_LVR_LVR12 (*((volatile unsigned int*)(0x42908030UL))) +#define bM4_FCM_LVR_LVR13 (*((volatile unsigned int*)(0x42908034UL))) +#define bM4_FCM_LVR_LVR14 (*((volatile unsigned int*)(0x42908038UL))) +#define bM4_FCM_LVR_LVR15 (*((volatile unsigned int*)(0x4290803CUL))) +#define bM4_FCM_UVR_UVR0 (*((volatile unsigned int*)(0x42908080UL))) +#define bM4_FCM_UVR_UVR1 (*((volatile unsigned int*)(0x42908084UL))) +#define bM4_FCM_UVR_UVR2 (*((volatile unsigned int*)(0x42908088UL))) +#define bM4_FCM_UVR_UVR3 (*((volatile unsigned int*)(0x4290808CUL))) +#define bM4_FCM_UVR_UVR4 (*((volatile unsigned int*)(0x42908090UL))) +#define bM4_FCM_UVR_UVR5 (*((volatile unsigned int*)(0x42908094UL))) +#define bM4_FCM_UVR_UVR6 (*((volatile unsigned int*)(0x42908098UL))) +#define bM4_FCM_UVR_UVR7 (*((volatile unsigned int*)(0x4290809CUL))) +#define bM4_FCM_UVR_UVR8 (*((volatile unsigned int*)(0x429080A0UL))) +#define bM4_FCM_UVR_UVR9 (*((volatile unsigned int*)(0x429080A4UL))) +#define bM4_FCM_UVR_UVR10 (*((volatile unsigned int*)(0x429080A8UL))) +#define bM4_FCM_UVR_UVR11 (*((volatile unsigned int*)(0x429080ACUL))) +#define bM4_FCM_UVR_UVR12 (*((volatile unsigned int*)(0x429080B0UL))) +#define bM4_FCM_UVR_UVR13 (*((volatile unsigned int*)(0x429080B4UL))) +#define bM4_FCM_UVR_UVR14 (*((volatile unsigned int*)(0x429080B8UL))) +#define bM4_FCM_UVR_UVR15 (*((volatile unsigned int*)(0x429080BCUL))) +#define bM4_FCM_CNTR_CNTR0 (*((volatile unsigned int*)(0x42908100UL))) +#define bM4_FCM_CNTR_CNTR1 (*((volatile unsigned int*)(0x42908104UL))) +#define bM4_FCM_CNTR_CNTR2 (*((volatile unsigned int*)(0x42908108UL))) +#define bM4_FCM_CNTR_CNTR3 (*((volatile unsigned int*)(0x4290810CUL))) +#define bM4_FCM_CNTR_CNTR4 (*((volatile unsigned int*)(0x42908110UL))) +#define bM4_FCM_CNTR_CNTR5 (*((volatile unsigned int*)(0x42908114UL))) +#define bM4_FCM_CNTR_CNTR6 (*((volatile unsigned int*)(0x42908118UL))) +#define bM4_FCM_CNTR_CNTR7 (*((volatile unsigned int*)(0x4290811CUL))) +#define bM4_FCM_CNTR_CNTR8 (*((volatile unsigned int*)(0x42908120UL))) +#define bM4_FCM_CNTR_CNTR9 (*((volatile unsigned int*)(0x42908124UL))) +#define bM4_FCM_CNTR_CNTR10 (*((volatile unsigned int*)(0x42908128UL))) +#define bM4_FCM_CNTR_CNTR11 (*((volatile unsigned int*)(0x4290812CUL))) +#define bM4_FCM_CNTR_CNTR12 (*((volatile unsigned int*)(0x42908130UL))) +#define bM4_FCM_CNTR_CNTR13 (*((volatile unsigned int*)(0x42908134UL))) +#define bM4_FCM_CNTR_CNTR14 (*((volatile unsigned int*)(0x42908138UL))) +#define bM4_FCM_CNTR_CNTR15 (*((volatile unsigned int*)(0x4290813CUL))) +#define bM4_FCM_STR_START (*((volatile unsigned int*)(0x42908180UL))) +#define bM4_FCM_MCCR_MDIVS0 (*((volatile unsigned int*)(0x42908200UL))) +#define bM4_FCM_MCCR_MDIVS1 (*((volatile unsigned int*)(0x42908204UL))) +#define bM4_FCM_MCCR_MCKS0 (*((volatile unsigned int*)(0x42908210UL))) +#define bM4_FCM_MCCR_MCKS1 (*((volatile unsigned int*)(0x42908214UL))) +#define bM4_FCM_MCCR_MCKS2 (*((volatile unsigned int*)(0x42908218UL))) +#define bM4_FCM_MCCR_MCKS3 (*((volatile unsigned int*)(0x4290821CUL))) +#define bM4_FCM_RCCR_RDIVS0 (*((volatile unsigned int*)(0x42908280UL))) +#define bM4_FCM_RCCR_RDIVS1 (*((volatile unsigned int*)(0x42908284UL))) +#define bM4_FCM_RCCR_RCKS0 (*((volatile unsigned int*)(0x4290828CUL))) +#define bM4_FCM_RCCR_RCKS1 (*((volatile unsigned int*)(0x42908290UL))) +#define bM4_FCM_RCCR_RCKS2 (*((volatile unsigned int*)(0x42908294UL))) +#define bM4_FCM_RCCR_RCKS3 (*((volatile unsigned int*)(0x42908298UL))) +#define bM4_FCM_RCCR_INEXS (*((volatile unsigned int*)(0x4290829CUL))) +#define bM4_FCM_RCCR_DNFS0 (*((volatile unsigned int*)(0x429082A0UL))) +#define bM4_FCM_RCCR_DNFS1 (*((volatile unsigned int*)(0x429082A4UL))) +#define bM4_FCM_RCCR_EDGES0 (*((volatile unsigned int*)(0x429082B0UL))) +#define bM4_FCM_RCCR_EDGES1 (*((volatile unsigned int*)(0x429082B4UL))) +#define bM4_FCM_RCCR_EXREFE (*((volatile unsigned int*)(0x429082BCUL))) +#define bM4_FCM_RIER_ERRIE (*((volatile unsigned int*)(0x42908300UL))) +#define bM4_FCM_RIER_MENDIE (*((volatile unsigned int*)(0x42908304UL))) +#define bM4_FCM_RIER_OVFIE (*((volatile unsigned int*)(0x42908308UL))) +#define bM4_FCM_RIER_ERRINTRS (*((volatile unsigned int*)(0x42908310UL))) +#define bM4_FCM_RIER_ERRE (*((volatile unsigned int*)(0x4290831CUL))) +#define bM4_FCM_SR_ERRF (*((volatile unsigned int*)(0x42908380UL))) +#define bM4_FCM_SR_MENDF (*((volatile unsigned int*)(0x42908384UL))) +#define bM4_FCM_SR_OVF (*((volatile unsigned int*)(0x42908388UL))) +#define bM4_FCM_CLR_ERRFCLR (*((volatile unsigned int*)(0x42908400UL))) +#define bM4_FCM_CLR_MENDFCLR (*((volatile unsigned int*)(0x42908404UL))) +#define bM4_FCM_CLR_OVFCLR (*((volatile unsigned int*)(0x42908408UL))) +#define bM4_HASH_CR_START (*((volatile unsigned int*)(0x42108000UL))) +#define bM4_HASH_CR_FST_GRP (*((volatile unsigned int*)(0x42108004UL))) +#define bM4_I2C1_CR1_PE (*((volatile unsigned int*)(0x429C0000UL))) +#define bM4_I2C1_CR1_SMBUS (*((volatile unsigned int*)(0x429C0004UL))) +#define bM4_I2C1_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C0008UL))) +#define bM4_I2C1_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C000CUL))) +#define bM4_I2C1_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C0010UL))) +#define bM4_I2C1_CR1_ENGC (*((volatile unsigned int*)(0x429C0018UL))) +#define bM4_I2C1_CR1_RESTART (*((volatile unsigned int*)(0x429C001CUL))) +#define bM4_I2C1_CR1_START (*((volatile unsigned int*)(0x429C0020UL))) +#define bM4_I2C1_CR1_STOP (*((volatile unsigned int*)(0x429C0024UL))) +#define bM4_I2C1_CR1_ACK (*((volatile unsigned int*)(0x429C0028UL))) +#define bM4_I2C1_CR1_SWRST (*((volatile unsigned int*)(0x429C003CUL))) +#define bM4_I2C1_CR2_STARTIE (*((volatile unsigned int*)(0x429C0080UL))) +#define bM4_I2C1_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C0084UL))) +#define bM4_I2C1_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C0088UL))) +#define bM4_I2C1_CR2_TENDIE (*((volatile unsigned int*)(0x429C008CUL))) +#define bM4_I2C1_CR2_STOPIE (*((volatile unsigned int*)(0x429C0090UL))) +#define bM4_I2C1_CR2_RFULLIE (*((volatile unsigned int*)(0x429C0098UL))) +#define bM4_I2C1_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C009CUL))) +#define bM4_I2C1_CR2_ARLOIE (*((volatile unsigned int*)(0x429C00A4UL))) +#define bM4_I2C1_CR2_NACKIE (*((volatile unsigned int*)(0x429C00B0UL))) +#define bM4_I2C1_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C00B8UL))) +#define bM4_I2C1_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C00D0UL))) +#define bM4_I2C1_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C00D4UL))) +#define bM4_I2C1_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C00D8UL))) +#define bM4_I2C1_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C00DCUL))) +#define bM4_I2C1_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C0100UL))) +#define bM4_I2C1_CR3_LTMOUT (*((volatile unsigned int*)(0x429C0104UL))) +#define bM4_I2C1_CR3_HTMOUT (*((volatile unsigned int*)(0x429C0108UL))) +#define bM4_I2C1_CR3_FACKEN (*((volatile unsigned int*)(0x429C011CUL))) +#define bM4_I2C1_CR4_BUSWAIT (*((volatile unsigned int*)(0x429C01A8UL))) +#define bM4_I2C1_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C0200UL))) +#define bM4_I2C1_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C0204UL))) +#define bM4_I2C1_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C0208UL))) +#define bM4_I2C1_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C020CUL))) +#define bM4_I2C1_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C0210UL))) +#define bM4_I2C1_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C0214UL))) +#define bM4_I2C1_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C0218UL))) +#define bM4_I2C1_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C021CUL))) +#define bM4_I2C1_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C0220UL))) +#define bM4_I2C1_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C0224UL))) +#define bM4_I2C1_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C0230UL))) +#define bM4_I2C1_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C023CUL))) +#define bM4_I2C1_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C0280UL))) +#define bM4_I2C1_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C0284UL))) +#define bM4_I2C1_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C0288UL))) +#define bM4_I2C1_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C028CUL))) +#define bM4_I2C1_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C0290UL))) +#define bM4_I2C1_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C0294UL))) +#define bM4_I2C1_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C0298UL))) +#define bM4_I2C1_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C029CUL))) +#define bM4_I2C1_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C02A0UL))) +#define bM4_I2C1_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C02A4UL))) +#define bM4_I2C1_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C02B0UL))) +#define bM4_I2C1_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C02BCUL))) +#define bM4_I2C1_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C0300UL))) +#define bM4_I2C1_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C0304UL))) +#define bM4_I2C1_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C0308UL))) +#define bM4_I2C1_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C030CUL))) +#define bM4_I2C1_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C0310UL))) +#define bM4_I2C1_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C0314UL))) +#define bM4_I2C1_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C0318UL))) +#define bM4_I2C1_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C031CUL))) +#define bM4_I2C1_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C0320UL))) +#define bM4_I2C1_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C0324UL))) +#define bM4_I2C1_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C0328UL))) +#define bM4_I2C1_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C032CUL))) +#define bM4_I2C1_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C0330UL))) +#define bM4_I2C1_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C0334UL))) +#define bM4_I2C1_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C0338UL))) +#define bM4_I2C1_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C033CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C0340UL))) +#define bM4_I2C1_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C0344UL))) +#define bM4_I2C1_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C0348UL))) +#define bM4_I2C1_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C034CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C0350UL))) +#define bM4_I2C1_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C0354UL))) +#define bM4_I2C1_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C0358UL))) +#define bM4_I2C1_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C035CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C0360UL))) +#define bM4_I2C1_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C0364UL))) +#define bM4_I2C1_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C0368UL))) +#define bM4_I2C1_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C036CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C0370UL))) +#define bM4_I2C1_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C0374UL))) +#define bM4_I2C1_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C0378UL))) +#define bM4_I2C1_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C037CUL))) +#define bM4_I2C1_SR_STARTF (*((volatile unsigned int*)(0x429C0380UL))) +#define bM4_I2C1_SR_SLADDR0F (*((volatile unsigned int*)(0x429C0384UL))) +#define bM4_I2C1_SR_SLADDR1F (*((volatile unsigned int*)(0x429C0388UL))) +#define bM4_I2C1_SR_TENDF (*((volatile unsigned int*)(0x429C038CUL))) +#define bM4_I2C1_SR_STOPF (*((volatile unsigned int*)(0x429C0390UL))) +#define bM4_I2C1_SR_RFULLF (*((volatile unsigned int*)(0x429C0398UL))) +#define bM4_I2C1_SR_TEMPTYF (*((volatile unsigned int*)(0x429C039CUL))) +#define bM4_I2C1_SR_ARLOF (*((volatile unsigned int*)(0x429C03A4UL))) +#define bM4_I2C1_SR_ACKRF (*((volatile unsigned int*)(0x429C03A8UL))) +#define bM4_I2C1_SR_NACKF (*((volatile unsigned int*)(0x429C03B0UL))) +#define bM4_I2C1_SR_TMOUTF (*((volatile unsigned int*)(0x429C03B8UL))) +#define bM4_I2C1_SR_MSL (*((volatile unsigned int*)(0x429C03C0UL))) +#define bM4_I2C1_SR_BUSY (*((volatile unsigned int*)(0x429C03C4UL))) +#define bM4_I2C1_SR_TRA (*((volatile unsigned int*)(0x429C03C8UL))) +#define bM4_I2C1_SR_GENCALLF (*((volatile unsigned int*)(0x429C03D0UL))) +#define bM4_I2C1_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C03D4UL))) +#define bM4_I2C1_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C03D8UL))) +#define bM4_I2C1_SR_SMBALRTF (*((volatile unsigned int*)(0x429C03DCUL))) +#define bM4_I2C1_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C0400UL))) +#define bM4_I2C1_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C0404UL))) +#define bM4_I2C1_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C0408UL))) +#define bM4_I2C1_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C040CUL))) +#define bM4_I2C1_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C0410UL))) +#define bM4_I2C1_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C0418UL))) +#define bM4_I2C1_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C041CUL))) +#define bM4_I2C1_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C0424UL))) +#define bM4_I2C1_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C0430UL))) +#define bM4_I2C1_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C0438UL))) +#define bM4_I2C1_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C0450UL))) +#define bM4_I2C1_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C0454UL))) +#define bM4_I2C1_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C0458UL))) +#define bM4_I2C1_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C045CUL))) +#define bM4_I2C1_DTR_DT0 (*((volatile unsigned int*)(0x429C0480UL))) +#define bM4_I2C1_DTR_DT1 (*((volatile unsigned int*)(0x429C0484UL))) +#define bM4_I2C1_DTR_DT2 (*((volatile unsigned int*)(0x429C0488UL))) +#define bM4_I2C1_DTR_DT3 (*((volatile unsigned int*)(0x429C048CUL))) +#define bM4_I2C1_DTR_DT4 (*((volatile unsigned int*)(0x429C0490UL))) +#define bM4_I2C1_DTR_DT5 (*((volatile unsigned int*)(0x429C0494UL))) +#define bM4_I2C1_DTR_DT6 (*((volatile unsigned int*)(0x429C0498UL))) +#define bM4_I2C1_DTR_DT7 (*((volatile unsigned int*)(0x429C049CUL))) +#define bM4_I2C1_DRR_DR0 (*((volatile unsigned int*)(0x429C0500UL))) +#define bM4_I2C1_DRR_DR1 (*((volatile unsigned int*)(0x429C0504UL))) +#define bM4_I2C1_DRR_DR2 (*((volatile unsigned int*)(0x429C0508UL))) +#define bM4_I2C1_DRR_DR3 (*((volatile unsigned int*)(0x429C050CUL))) +#define bM4_I2C1_DRR_DR4 (*((volatile unsigned int*)(0x429C0510UL))) +#define bM4_I2C1_DRR_DR5 (*((volatile unsigned int*)(0x429C0514UL))) +#define bM4_I2C1_DRR_DR6 (*((volatile unsigned int*)(0x429C0518UL))) +#define bM4_I2C1_DRR_DR7 (*((volatile unsigned int*)(0x429C051CUL))) +#define bM4_I2C1_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C0580UL))) +#define bM4_I2C1_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C0584UL))) +#define bM4_I2C1_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C0588UL))) +#define bM4_I2C1_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C058CUL))) +#define bM4_I2C1_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C0590UL))) +#define bM4_I2C1_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C05A0UL))) +#define bM4_I2C1_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C05A4UL))) +#define bM4_I2C1_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C05A8UL))) +#define bM4_I2C1_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C05ACUL))) +#define bM4_I2C1_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C05B0UL))) +#define bM4_I2C1_CCR_FREQ0 (*((volatile unsigned int*)(0x429C05C0UL))) +#define bM4_I2C1_CCR_FREQ1 (*((volatile unsigned int*)(0x429C05C4UL))) +#define bM4_I2C1_CCR_FREQ2 (*((volatile unsigned int*)(0x429C05C8UL))) +#define bM4_I2C1_FLTR_DNF0 (*((volatile unsigned int*)(0x429C0600UL))) +#define bM4_I2C1_FLTR_DNF1 (*((volatile unsigned int*)(0x429C0604UL))) +#define bM4_I2C1_FLTR_DNFEN (*((volatile unsigned int*)(0x429C0610UL))) +#define bM4_I2C1_FLTR_ANFEN (*((volatile unsigned int*)(0x429C0614UL))) +#define bM4_I2C2_CR1_PE (*((volatile unsigned int*)(0x429C8000UL))) +#define bM4_I2C2_CR1_SMBUS (*((volatile unsigned int*)(0x429C8004UL))) +#define bM4_I2C2_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C8008UL))) +#define bM4_I2C2_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C800CUL))) +#define bM4_I2C2_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C8010UL))) +#define bM4_I2C2_CR1_ENGC (*((volatile unsigned int*)(0x429C8018UL))) +#define bM4_I2C2_CR1_RESTART (*((volatile unsigned int*)(0x429C801CUL))) +#define bM4_I2C2_CR1_START (*((volatile unsigned int*)(0x429C8020UL))) +#define bM4_I2C2_CR1_STOP (*((volatile unsigned int*)(0x429C8024UL))) +#define bM4_I2C2_CR1_ACK (*((volatile unsigned int*)(0x429C8028UL))) +#define bM4_I2C2_CR1_SWRST (*((volatile unsigned int*)(0x429C803CUL))) +#define bM4_I2C2_CR2_STARTIE (*((volatile unsigned int*)(0x429C8080UL))) +#define bM4_I2C2_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C8084UL))) +#define bM4_I2C2_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C8088UL))) +#define bM4_I2C2_CR2_TENDIE (*((volatile unsigned int*)(0x429C808CUL))) +#define bM4_I2C2_CR2_STOPIE (*((volatile unsigned int*)(0x429C8090UL))) +#define bM4_I2C2_CR2_RFULLIE (*((volatile unsigned int*)(0x429C8098UL))) +#define bM4_I2C2_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C809CUL))) +#define bM4_I2C2_CR2_ARLOIE (*((volatile unsigned int*)(0x429C80A4UL))) +#define bM4_I2C2_CR2_NACKIE (*((volatile unsigned int*)(0x429C80B0UL))) +#define bM4_I2C2_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C80B8UL))) +#define bM4_I2C2_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C80D0UL))) +#define bM4_I2C2_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C80D4UL))) +#define bM4_I2C2_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C80D8UL))) +#define bM4_I2C2_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C80DCUL))) +#define bM4_I2C2_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C8100UL))) +#define bM4_I2C2_CR3_LTMOUT (*((volatile unsigned int*)(0x429C8104UL))) +#define bM4_I2C2_CR3_HTMOUT (*((volatile unsigned int*)(0x429C8108UL))) +#define bM4_I2C2_CR3_FACKEN (*((volatile unsigned int*)(0x429C811CUL))) +#define bM4_I2C2_CR4_BUSWAIT (*((volatile unsigned int*)(0x429C81A8UL))) +#define bM4_I2C2_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C8200UL))) +#define bM4_I2C2_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C8204UL))) +#define bM4_I2C2_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C8208UL))) +#define bM4_I2C2_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C820CUL))) +#define bM4_I2C2_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C8210UL))) +#define bM4_I2C2_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C8214UL))) +#define bM4_I2C2_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C8218UL))) +#define bM4_I2C2_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C821CUL))) +#define bM4_I2C2_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C8220UL))) +#define bM4_I2C2_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C8224UL))) +#define bM4_I2C2_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C8230UL))) +#define bM4_I2C2_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C823CUL))) +#define bM4_I2C2_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C8280UL))) +#define bM4_I2C2_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C8284UL))) +#define bM4_I2C2_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C8288UL))) +#define bM4_I2C2_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C828CUL))) +#define bM4_I2C2_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C8290UL))) +#define bM4_I2C2_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C8294UL))) +#define bM4_I2C2_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C8298UL))) +#define bM4_I2C2_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C829CUL))) +#define bM4_I2C2_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C82A0UL))) +#define bM4_I2C2_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C82A4UL))) +#define bM4_I2C2_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C82B0UL))) +#define bM4_I2C2_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C82BCUL))) +#define bM4_I2C2_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C8300UL))) +#define bM4_I2C2_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C8304UL))) +#define bM4_I2C2_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C8308UL))) +#define bM4_I2C2_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C830CUL))) +#define bM4_I2C2_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C8310UL))) +#define bM4_I2C2_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C8314UL))) +#define bM4_I2C2_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C8318UL))) +#define bM4_I2C2_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C831CUL))) +#define bM4_I2C2_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C8320UL))) +#define bM4_I2C2_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C8324UL))) +#define bM4_I2C2_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C8328UL))) +#define bM4_I2C2_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C832CUL))) +#define bM4_I2C2_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C8330UL))) +#define bM4_I2C2_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C8334UL))) +#define bM4_I2C2_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C8338UL))) +#define bM4_I2C2_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C833CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C8340UL))) +#define bM4_I2C2_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C8344UL))) +#define bM4_I2C2_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C8348UL))) +#define bM4_I2C2_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C834CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C8350UL))) +#define bM4_I2C2_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C8354UL))) +#define bM4_I2C2_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C8358UL))) +#define bM4_I2C2_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C835CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C8360UL))) +#define bM4_I2C2_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C8364UL))) +#define bM4_I2C2_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C8368UL))) +#define bM4_I2C2_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C836CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C8370UL))) +#define bM4_I2C2_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C8374UL))) +#define bM4_I2C2_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C8378UL))) +#define bM4_I2C2_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C837CUL))) +#define bM4_I2C2_SR_STARTF (*((volatile unsigned int*)(0x429C8380UL))) +#define bM4_I2C2_SR_SLADDR0F (*((volatile unsigned int*)(0x429C8384UL))) +#define bM4_I2C2_SR_SLADDR1F (*((volatile unsigned int*)(0x429C8388UL))) +#define bM4_I2C2_SR_TENDF (*((volatile unsigned int*)(0x429C838CUL))) +#define bM4_I2C2_SR_STOPF (*((volatile unsigned int*)(0x429C8390UL))) +#define bM4_I2C2_SR_RFULLF (*((volatile unsigned int*)(0x429C8398UL))) +#define bM4_I2C2_SR_TEMPTYF (*((volatile unsigned int*)(0x429C839CUL))) +#define bM4_I2C2_SR_ARLOF (*((volatile unsigned int*)(0x429C83A4UL))) +#define bM4_I2C2_SR_ACKRF (*((volatile unsigned int*)(0x429C83A8UL))) +#define bM4_I2C2_SR_NACKF (*((volatile unsigned int*)(0x429C83B0UL))) +#define bM4_I2C2_SR_TMOUTF (*((volatile unsigned int*)(0x429C83B8UL))) +#define bM4_I2C2_SR_MSL (*((volatile unsigned int*)(0x429C83C0UL))) +#define bM4_I2C2_SR_BUSY (*((volatile unsigned int*)(0x429C83C4UL))) +#define bM4_I2C2_SR_TRA (*((volatile unsigned int*)(0x429C83C8UL))) +#define bM4_I2C2_SR_GENCALLF (*((volatile unsigned int*)(0x429C83D0UL))) +#define bM4_I2C2_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C83D4UL))) +#define bM4_I2C2_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C83D8UL))) +#define bM4_I2C2_SR_SMBALRTF (*((volatile unsigned int*)(0x429C83DCUL))) +#define bM4_I2C2_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C8400UL))) +#define bM4_I2C2_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C8404UL))) +#define bM4_I2C2_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C8408UL))) +#define bM4_I2C2_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C840CUL))) +#define bM4_I2C2_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C8410UL))) +#define bM4_I2C2_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C8418UL))) +#define bM4_I2C2_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C841CUL))) +#define bM4_I2C2_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C8424UL))) +#define bM4_I2C2_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C8430UL))) +#define bM4_I2C2_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C8438UL))) +#define bM4_I2C2_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C8450UL))) +#define bM4_I2C2_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C8454UL))) +#define bM4_I2C2_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C8458UL))) +#define bM4_I2C2_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C845CUL))) +#define bM4_I2C2_DTR_DT0 (*((volatile unsigned int*)(0x429C8480UL))) +#define bM4_I2C2_DTR_DT1 (*((volatile unsigned int*)(0x429C8484UL))) +#define bM4_I2C2_DTR_DT2 (*((volatile unsigned int*)(0x429C8488UL))) +#define bM4_I2C2_DTR_DT3 (*((volatile unsigned int*)(0x429C848CUL))) +#define bM4_I2C2_DTR_DT4 (*((volatile unsigned int*)(0x429C8490UL))) +#define bM4_I2C2_DTR_DT5 (*((volatile unsigned int*)(0x429C8494UL))) +#define bM4_I2C2_DTR_DT6 (*((volatile unsigned int*)(0x429C8498UL))) +#define bM4_I2C2_DTR_DT7 (*((volatile unsigned int*)(0x429C849CUL))) +#define bM4_I2C2_DRR_DR0 (*((volatile unsigned int*)(0x429C8500UL))) +#define bM4_I2C2_DRR_DR1 (*((volatile unsigned int*)(0x429C8504UL))) +#define bM4_I2C2_DRR_DR2 (*((volatile unsigned int*)(0x429C8508UL))) +#define bM4_I2C2_DRR_DR3 (*((volatile unsigned int*)(0x429C850CUL))) +#define bM4_I2C2_DRR_DR4 (*((volatile unsigned int*)(0x429C8510UL))) +#define bM4_I2C2_DRR_DR5 (*((volatile unsigned int*)(0x429C8514UL))) +#define bM4_I2C2_DRR_DR6 (*((volatile unsigned int*)(0x429C8518UL))) +#define bM4_I2C2_DRR_DR7 (*((volatile unsigned int*)(0x429C851CUL))) +#define bM4_I2C2_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C8580UL))) +#define bM4_I2C2_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C8584UL))) +#define bM4_I2C2_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C8588UL))) +#define bM4_I2C2_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C858CUL))) +#define bM4_I2C2_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C8590UL))) +#define bM4_I2C2_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C85A0UL))) +#define bM4_I2C2_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C85A4UL))) +#define bM4_I2C2_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C85A8UL))) +#define bM4_I2C2_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C85ACUL))) +#define bM4_I2C2_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C85B0UL))) +#define bM4_I2C2_CCR_FREQ0 (*((volatile unsigned int*)(0x429C85C0UL))) +#define bM4_I2C2_CCR_FREQ1 (*((volatile unsigned int*)(0x429C85C4UL))) +#define bM4_I2C2_CCR_FREQ2 (*((volatile unsigned int*)(0x429C85C8UL))) +#define bM4_I2C2_FLTR_DNF0 (*((volatile unsigned int*)(0x429C8600UL))) +#define bM4_I2C2_FLTR_DNF1 (*((volatile unsigned int*)(0x429C8604UL))) +#define bM4_I2C2_FLTR_DNFEN (*((volatile unsigned int*)(0x429C8610UL))) +#define bM4_I2C2_FLTR_ANFEN (*((volatile unsigned int*)(0x429C8614UL))) +#define bM4_I2C3_CR1_PE (*((volatile unsigned int*)(0x429D0000UL))) +#define bM4_I2C3_CR1_SMBUS (*((volatile unsigned int*)(0x429D0004UL))) +#define bM4_I2C3_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429D0008UL))) +#define bM4_I2C3_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429D000CUL))) +#define bM4_I2C3_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429D0010UL))) +#define bM4_I2C3_CR1_ENGC (*((volatile unsigned int*)(0x429D0018UL))) +#define bM4_I2C3_CR1_RESTART (*((volatile unsigned int*)(0x429D001CUL))) +#define bM4_I2C3_CR1_START (*((volatile unsigned int*)(0x429D0020UL))) +#define bM4_I2C3_CR1_STOP (*((volatile unsigned int*)(0x429D0024UL))) +#define bM4_I2C3_CR1_ACK (*((volatile unsigned int*)(0x429D0028UL))) +#define bM4_I2C3_CR1_SWRST (*((volatile unsigned int*)(0x429D003CUL))) +#define bM4_I2C3_CR2_STARTIE (*((volatile unsigned int*)(0x429D0080UL))) +#define bM4_I2C3_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429D0084UL))) +#define bM4_I2C3_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429D0088UL))) +#define bM4_I2C3_CR2_TENDIE (*((volatile unsigned int*)(0x429D008CUL))) +#define bM4_I2C3_CR2_STOPIE (*((volatile unsigned int*)(0x429D0090UL))) +#define bM4_I2C3_CR2_RFULLIE (*((volatile unsigned int*)(0x429D0098UL))) +#define bM4_I2C3_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429D009CUL))) +#define bM4_I2C3_CR2_ARLOIE (*((volatile unsigned int*)(0x429D00A4UL))) +#define bM4_I2C3_CR2_NACKIE (*((volatile unsigned int*)(0x429D00B0UL))) +#define bM4_I2C3_CR2_TMOUTIE (*((volatile unsigned int*)(0x429D00B8UL))) +#define bM4_I2C3_CR2_GENCALLIE (*((volatile unsigned int*)(0x429D00D0UL))) +#define bM4_I2C3_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429D00D4UL))) +#define bM4_I2C3_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429D00D8UL))) +#define bM4_I2C3_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429D00DCUL))) +#define bM4_I2C3_CR3_TMOUTEN (*((volatile unsigned int*)(0x429D0100UL))) +#define bM4_I2C3_CR3_LTMOUT (*((volatile unsigned int*)(0x429D0104UL))) +#define bM4_I2C3_CR3_HTMOUT (*((volatile unsigned int*)(0x429D0108UL))) +#define bM4_I2C3_CR3_FACKEN (*((volatile unsigned int*)(0x429D011CUL))) +#define bM4_I2C3_CR4_BUSWAIT (*((volatile unsigned int*)(0x429D01A8UL))) +#define bM4_I2C3_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429D0200UL))) +#define bM4_I2C3_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429D0204UL))) +#define bM4_I2C3_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429D0208UL))) +#define bM4_I2C3_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429D020CUL))) +#define bM4_I2C3_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429D0210UL))) +#define bM4_I2C3_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429D0214UL))) +#define bM4_I2C3_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429D0218UL))) +#define bM4_I2C3_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429D021CUL))) +#define bM4_I2C3_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429D0220UL))) +#define bM4_I2C3_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429D0224UL))) +#define bM4_I2C3_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429D0230UL))) +#define bM4_I2C3_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429D023CUL))) +#define bM4_I2C3_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429D0280UL))) +#define bM4_I2C3_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429D0284UL))) +#define bM4_I2C3_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429D0288UL))) +#define bM4_I2C3_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429D028CUL))) +#define bM4_I2C3_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429D0290UL))) +#define bM4_I2C3_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429D0294UL))) +#define bM4_I2C3_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429D0298UL))) +#define bM4_I2C3_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429D029CUL))) +#define bM4_I2C3_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429D02A0UL))) +#define bM4_I2C3_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429D02A4UL))) +#define bM4_I2C3_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429D02B0UL))) +#define bM4_I2C3_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429D02BCUL))) +#define bM4_I2C3_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429D0300UL))) +#define bM4_I2C3_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429D0304UL))) +#define bM4_I2C3_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429D0308UL))) +#define bM4_I2C3_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429D030CUL))) +#define bM4_I2C3_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429D0310UL))) +#define bM4_I2C3_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429D0314UL))) +#define bM4_I2C3_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429D0318UL))) +#define bM4_I2C3_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429D031CUL))) +#define bM4_I2C3_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429D0320UL))) +#define bM4_I2C3_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429D0324UL))) +#define bM4_I2C3_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429D0328UL))) +#define bM4_I2C3_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429D032CUL))) +#define bM4_I2C3_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429D0330UL))) +#define bM4_I2C3_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429D0334UL))) +#define bM4_I2C3_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429D0338UL))) +#define bM4_I2C3_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429D033CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429D0340UL))) +#define bM4_I2C3_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429D0344UL))) +#define bM4_I2C3_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429D0348UL))) +#define bM4_I2C3_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429D034CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429D0350UL))) +#define bM4_I2C3_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429D0354UL))) +#define bM4_I2C3_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429D0358UL))) +#define bM4_I2C3_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429D035CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429D0360UL))) +#define bM4_I2C3_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429D0364UL))) +#define bM4_I2C3_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429D0368UL))) +#define bM4_I2C3_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429D036CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429D0370UL))) +#define bM4_I2C3_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429D0374UL))) +#define bM4_I2C3_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429D0378UL))) +#define bM4_I2C3_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429D037CUL))) +#define bM4_I2C3_SR_STARTF (*((volatile unsigned int*)(0x429D0380UL))) +#define bM4_I2C3_SR_SLADDR0F (*((volatile unsigned int*)(0x429D0384UL))) +#define bM4_I2C3_SR_SLADDR1F (*((volatile unsigned int*)(0x429D0388UL))) +#define bM4_I2C3_SR_TENDF (*((volatile unsigned int*)(0x429D038CUL))) +#define bM4_I2C3_SR_STOPF (*((volatile unsigned int*)(0x429D0390UL))) +#define bM4_I2C3_SR_RFULLF (*((volatile unsigned int*)(0x429D0398UL))) +#define bM4_I2C3_SR_TEMPTYF (*((volatile unsigned int*)(0x429D039CUL))) +#define bM4_I2C3_SR_ARLOF (*((volatile unsigned int*)(0x429D03A4UL))) +#define bM4_I2C3_SR_ACKRF (*((volatile unsigned int*)(0x429D03A8UL))) +#define bM4_I2C3_SR_NACKF (*((volatile unsigned int*)(0x429D03B0UL))) +#define bM4_I2C3_SR_TMOUTF (*((volatile unsigned int*)(0x429D03B8UL))) +#define bM4_I2C3_SR_MSL (*((volatile unsigned int*)(0x429D03C0UL))) +#define bM4_I2C3_SR_BUSY (*((volatile unsigned int*)(0x429D03C4UL))) +#define bM4_I2C3_SR_TRA (*((volatile unsigned int*)(0x429D03C8UL))) +#define bM4_I2C3_SR_GENCALLF (*((volatile unsigned int*)(0x429D03D0UL))) +#define bM4_I2C3_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429D03D4UL))) +#define bM4_I2C3_SR_SMBHOSTF (*((volatile unsigned int*)(0x429D03D8UL))) +#define bM4_I2C3_SR_SMBALRTF (*((volatile unsigned int*)(0x429D03DCUL))) +#define bM4_I2C3_CLR_STARTFCLR (*((volatile unsigned int*)(0x429D0400UL))) +#define bM4_I2C3_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429D0404UL))) +#define bM4_I2C3_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429D0408UL))) +#define bM4_I2C3_CLR_TENDFCLR (*((volatile unsigned int*)(0x429D040CUL))) +#define bM4_I2C3_CLR_STOPFCLR (*((volatile unsigned int*)(0x429D0410UL))) +#define bM4_I2C3_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429D0418UL))) +#define bM4_I2C3_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429D041CUL))) +#define bM4_I2C3_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429D0424UL))) +#define bM4_I2C3_CLR_NACKFCLR (*((volatile unsigned int*)(0x429D0430UL))) +#define bM4_I2C3_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429D0438UL))) +#define bM4_I2C3_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429D0450UL))) +#define bM4_I2C3_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429D0454UL))) +#define bM4_I2C3_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429D0458UL))) +#define bM4_I2C3_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429D045CUL))) +#define bM4_I2C3_DTR_DT0 (*((volatile unsigned int*)(0x429D0480UL))) +#define bM4_I2C3_DTR_DT1 (*((volatile unsigned int*)(0x429D0484UL))) +#define bM4_I2C3_DTR_DT2 (*((volatile unsigned int*)(0x429D0488UL))) +#define bM4_I2C3_DTR_DT3 (*((volatile unsigned int*)(0x429D048CUL))) +#define bM4_I2C3_DTR_DT4 (*((volatile unsigned int*)(0x429D0490UL))) +#define bM4_I2C3_DTR_DT5 (*((volatile unsigned int*)(0x429D0494UL))) +#define bM4_I2C3_DTR_DT6 (*((volatile unsigned int*)(0x429D0498UL))) +#define bM4_I2C3_DTR_DT7 (*((volatile unsigned int*)(0x429D049CUL))) +#define bM4_I2C3_DRR_DR0 (*((volatile unsigned int*)(0x429D0500UL))) +#define bM4_I2C3_DRR_DR1 (*((volatile unsigned int*)(0x429D0504UL))) +#define bM4_I2C3_DRR_DR2 (*((volatile unsigned int*)(0x429D0508UL))) +#define bM4_I2C3_DRR_DR3 (*((volatile unsigned int*)(0x429D050CUL))) +#define bM4_I2C3_DRR_DR4 (*((volatile unsigned int*)(0x429D0510UL))) +#define bM4_I2C3_DRR_DR5 (*((volatile unsigned int*)(0x429D0514UL))) +#define bM4_I2C3_DRR_DR6 (*((volatile unsigned int*)(0x429D0518UL))) +#define bM4_I2C3_DRR_DR7 (*((volatile unsigned int*)(0x429D051CUL))) +#define bM4_I2C3_CCR_SLOWW0 (*((volatile unsigned int*)(0x429D0580UL))) +#define bM4_I2C3_CCR_SLOWW1 (*((volatile unsigned int*)(0x429D0584UL))) +#define bM4_I2C3_CCR_SLOWW2 (*((volatile unsigned int*)(0x429D0588UL))) +#define bM4_I2C3_CCR_SLOWW3 (*((volatile unsigned int*)(0x429D058CUL))) +#define bM4_I2C3_CCR_SLOWW4 (*((volatile unsigned int*)(0x429D0590UL))) +#define bM4_I2C3_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429D05A0UL))) +#define bM4_I2C3_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429D05A4UL))) +#define bM4_I2C3_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429D05A8UL))) +#define bM4_I2C3_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429D05ACUL))) +#define bM4_I2C3_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429D05B0UL))) +#define bM4_I2C3_CCR_FREQ0 (*((volatile unsigned int*)(0x429D05C0UL))) +#define bM4_I2C3_CCR_FREQ1 (*((volatile unsigned int*)(0x429D05C4UL))) +#define bM4_I2C3_CCR_FREQ2 (*((volatile unsigned int*)(0x429D05C8UL))) +#define bM4_I2C3_FLTR_DNF0 (*((volatile unsigned int*)(0x429D0600UL))) +#define bM4_I2C3_FLTR_DNF1 (*((volatile unsigned int*)(0x429D0604UL))) +#define bM4_I2C3_FLTR_DNFEN (*((volatile unsigned int*)(0x429D0610UL))) +#define bM4_I2C3_FLTR_ANFEN (*((volatile unsigned int*)(0x429D0614UL))) +#define bM4_I2S1_CTRL_TXE (*((volatile unsigned int*)(0x423C0000UL))) +#define bM4_I2S1_CTRL_TXIE (*((volatile unsigned int*)(0x423C0004UL))) +#define bM4_I2S1_CTRL_RXE (*((volatile unsigned int*)(0x423C0008UL))) +#define bM4_I2S1_CTRL_RXIE (*((volatile unsigned int*)(0x423C000CUL))) +#define bM4_I2S1_CTRL_EIE (*((volatile unsigned int*)(0x423C0010UL))) +#define bM4_I2S1_CTRL_WMS (*((volatile unsigned int*)(0x423C0014UL))) +#define bM4_I2S1_CTRL_ODD (*((volatile unsigned int*)(0x423C0018UL))) +#define bM4_I2S1_CTRL_MCKOE (*((volatile unsigned int*)(0x423C001CUL))) +#define bM4_I2S1_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C0020UL))) +#define bM4_I2S1_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C0024UL))) +#define bM4_I2S1_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C0028UL))) +#define bM4_I2S1_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C0030UL))) +#define bM4_I2S1_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C0034UL))) +#define bM4_I2S1_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C0038UL))) +#define bM4_I2S1_CTRL_FIFOR (*((volatile unsigned int*)(0x423C0040UL))) +#define bM4_I2S1_CTRL_CODECRC (*((volatile unsigned int*)(0x423C0044UL))) +#define bM4_I2S1_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C0048UL))) +#define bM4_I2S1_CTRL_SDOE (*((volatile unsigned int*)(0x423C004CUL))) +#define bM4_I2S1_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C0050UL))) +#define bM4_I2S1_CTRL_CKOE (*((volatile unsigned int*)(0x423C0054UL))) +#define bM4_I2S1_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C0058UL))) +#define bM4_I2S1_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C005CUL))) +#define bM4_I2S1_SR_TXBA (*((volatile unsigned int*)(0x423C0080UL))) +#define bM4_I2S1_SR_RXBA (*((volatile unsigned int*)(0x423C0084UL))) +#define bM4_I2S1_SR_TXBE (*((volatile unsigned int*)(0x423C0088UL))) +#define bM4_I2S1_SR_TXBF (*((volatile unsigned int*)(0x423C008CUL))) +#define bM4_I2S1_SR_RXBE (*((volatile unsigned int*)(0x423C0090UL))) +#define bM4_I2S1_SR_RXBF (*((volatile unsigned int*)(0x423C0094UL))) +#define bM4_I2S1_ER_TXERR (*((volatile unsigned int*)(0x423C0100UL))) +#define bM4_I2S1_ER_RXERR (*((volatile unsigned int*)(0x423C0104UL))) +#define bM4_I2S1_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C0180UL))) +#define bM4_I2S1_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C0184UL))) +#define bM4_I2S1_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C0188UL))) +#define bM4_I2S1_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C018CUL))) +#define bM4_I2S1_CFGR_CHLEN (*((volatile unsigned int*)(0x423C0190UL))) +#define bM4_I2S1_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C0194UL))) +#define bM4_I2S1_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C0300UL))) +#define bM4_I2S1_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C0304UL))) +#define bM4_I2S1_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C0308UL))) +#define bM4_I2S1_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C030CUL))) +#define bM4_I2S1_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C0310UL))) +#define bM4_I2S1_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C0314UL))) +#define bM4_I2S1_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C0318UL))) +#define bM4_I2S1_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C031CUL))) +#define bM4_I2S2_CTRL_TXE (*((volatile unsigned int*)(0x423C8000UL))) +#define bM4_I2S2_CTRL_TXIE (*((volatile unsigned int*)(0x423C8004UL))) +#define bM4_I2S2_CTRL_RXE (*((volatile unsigned int*)(0x423C8008UL))) +#define bM4_I2S2_CTRL_RXIE (*((volatile unsigned int*)(0x423C800CUL))) +#define bM4_I2S2_CTRL_EIE (*((volatile unsigned int*)(0x423C8010UL))) +#define bM4_I2S2_CTRL_WMS (*((volatile unsigned int*)(0x423C8014UL))) +#define bM4_I2S2_CTRL_ODD (*((volatile unsigned int*)(0x423C8018UL))) +#define bM4_I2S2_CTRL_MCKOE (*((volatile unsigned int*)(0x423C801CUL))) +#define bM4_I2S2_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C8020UL))) +#define bM4_I2S2_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C8024UL))) +#define bM4_I2S2_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C8028UL))) +#define bM4_I2S2_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C8030UL))) +#define bM4_I2S2_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C8034UL))) +#define bM4_I2S2_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C8038UL))) +#define bM4_I2S2_CTRL_FIFOR (*((volatile unsigned int*)(0x423C8040UL))) +#define bM4_I2S2_CTRL_CODECRC (*((volatile unsigned int*)(0x423C8044UL))) +#define bM4_I2S2_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C8048UL))) +#define bM4_I2S2_CTRL_SDOE (*((volatile unsigned int*)(0x423C804CUL))) +#define bM4_I2S2_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C8050UL))) +#define bM4_I2S2_CTRL_CKOE (*((volatile unsigned int*)(0x423C8054UL))) +#define bM4_I2S2_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C8058UL))) +#define bM4_I2S2_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C805CUL))) +#define bM4_I2S2_SR_TXBA (*((volatile unsigned int*)(0x423C8080UL))) +#define bM4_I2S2_SR_RXBA (*((volatile unsigned int*)(0x423C8084UL))) +#define bM4_I2S2_SR_TXBE (*((volatile unsigned int*)(0x423C8088UL))) +#define bM4_I2S2_SR_TXBF (*((volatile unsigned int*)(0x423C808CUL))) +#define bM4_I2S2_SR_RXBE (*((volatile unsigned int*)(0x423C8090UL))) +#define bM4_I2S2_SR_RXBF (*((volatile unsigned int*)(0x423C8094UL))) +#define bM4_I2S2_ER_TXERR (*((volatile unsigned int*)(0x423C8100UL))) +#define bM4_I2S2_ER_RXERR (*((volatile unsigned int*)(0x423C8104UL))) +#define bM4_I2S2_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C8180UL))) +#define bM4_I2S2_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C8184UL))) +#define bM4_I2S2_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C8188UL))) +#define bM4_I2S2_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C818CUL))) +#define bM4_I2S2_CFGR_CHLEN (*((volatile unsigned int*)(0x423C8190UL))) +#define bM4_I2S2_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C8194UL))) +#define bM4_I2S2_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C8300UL))) +#define bM4_I2S2_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C8304UL))) +#define bM4_I2S2_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C8308UL))) +#define bM4_I2S2_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C830CUL))) +#define bM4_I2S2_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C8310UL))) +#define bM4_I2S2_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C8314UL))) +#define bM4_I2S2_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C8318UL))) +#define bM4_I2S2_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C831CUL))) +#define bM4_I2S3_CTRL_TXE (*((volatile unsigned int*)(0x42440000UL))) +#define bM4_I2S3_CTRL_TXIE (*((volatile unsigned int*)(0x42440004UL))) +#define bM4_I2S3_CTRL_RXE (*((volatile unsigned int*)(0x42440008UL))) +#define bM4_I2S3_CTRL_RXIE (*((volatile unsigned int*)(0x4244000CUL))) +#define bM4_I2S3_CTRL_EIE (*((volatile unsigned int*)(0x42440010UL))) +#define bM4_I2S3_CTRL_WMS (*((volatile unsigned int*)(0x42440014UL))) +#define bM4_I2S3_CTRL_ODD (*((volatile unsigned int*)(0x42440018UL))) +#define bM4_I2S3_CTRL_MCKOE (*((volatile unsigned int*)(0x4244001CUL))) +#define bM4_I2S3_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42440020UL))) +#define bM4_I2S3_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42440024UL))) +#define bM4_I2S3_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42440028UL))) +#define bM4_I2S3_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42440030UL))) +#define bM4_I2S3_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42440034UL))) +#define bM4_I2S3_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42440038UL))) +#define bM4_I2S3_CTRL_FIFOR (*((volatile unsigned int*)(0x42440040UL))) +#define bM4_I2S3_CTRL_CODECRC (*((volatile unsigned int*)(0x42440044UL))) +#define bM4_I2S3_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42440048UL))) +#define bM4_I2S3_CTRL_SDOE (*((volatile unsigned int*)(0x4244004CUL))) +#define bM4_I2S3_CTRL_LRCKOE (*((volatile unsigned int*)(0x42440050UL))) +#define bM4_I2S3_CTRL_CKOE (*((volatile unsigned int*)(0x42440054UL))) +#define bM4_I2S3_CTRL_DUPLEX (*((volatile unsigned int*)(0x42440058UL))) +#define bM4_I2S3_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244005CUL))) +#define bM4_I2S3_SR_TXBA (*((volatile unsigned int*)(0x42440080UL))) +#define bM4_I2S3_SR_RXBA (*((volatile unsigned int*)(0x42440084UL))) +#define bM4_I2S3_SR_TXBE (*((volatile unsigned int*)(0x42440088UL))) +#define bM4_I2S3_SR_TXBF (*((volatile unsigned int*)(0x4244008CUL))) +#define bM4_I2S3_SR_RXBE (*((volatile unsigned int*)(0x42440090UL))) +#define bM4_I2S3_SR_RXBF (*((volatile unsigned int*)(0x42440094UL))) +#define bM4_I2S3_ER_TXERR (*((volatile unsigned int*)(0x42440100UL))) +#define bM4_I2S3_ER_RXERR (*((volatile unsigned int*)(0x42440104UL))) +#define bM4_I2S3_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42440180UL))) +#define bM4_I2S3_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42440184UL))) +#define bM4_I2S3_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42440188UL))) +#define bM4_I2S3_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244018CUL))) +#define bM4_I2S3_CFGR_CHLEN (*((volatile unsigned int*)(0x42440190UL))) +#define bM4_I2S3_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42440194UL))) +#define bM4_I2S3_PR_I2SDIV0 (*((volatile unsigned int*)(0x42440300UL))) +#define bM4_I2S3_PR_I2SDIV1 (*((volatile unsigned int*)(0x42440304UL))) +#define bM4_I2S3_PR_I2SDIV2 (*((volatile unsigned int*)(0x42440308UL))) +#define bM4_I2S3_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244030CUL))) +#define bM4_I2S3_PR_I2SDIV4 (*((volatile unsigned int*)(0x42440310UL))) +#define bM4_I2S3_PR_I2SDIV5 (*((volatile unsigned int*)(0x42440314UL))) +#define bM4_I2S3_PR_I2SDIV6 (*((volatile unsigned int*)(0x42440318UL))) +#define bM4_I2S3_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244031CUL))) +#define bM4_I2S4_CTRL_TXE (*((volatile unsigned int*)(0x42448000UL))) +#define bM4_I2S4_CTRL_TXIE (*((volatile unsigned int*)(0x42448004UL))) +#define bM4_I2S4_CTRL_RXE (*((volatile unsigned int*)(0x42448008UL))) +#define bM4_I2S4_CTRL_RXIE (*((volatile unsigned int*)(0x4244800CUL))) +#define bM4_I2S4_CTRL_EIE (*((volatile unsigned int*)(0x42448010UL))) +#define bM4_I2S4_CTRL_WMS (*((volatile unsigned int*)(0x42448014UL))) +#define bM4_I2S4_CTRL_ODD (*((volatile unsigned int*)(0x42448018UL))) +#define bM4_I2S4_CTRL_MCKOE (*((volatile unsigned int*)(0x4244801CUL))) +#define bM4_I2S4_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42448020UL))) +#define bM4_I2S4_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42448024UL))) +#define bM4_I2S4_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42448028UL))) +#define bM4_I2S4_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42448030UL))) +#define bM4_I2S4_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42448034UL))) +#define bM4_I2S4_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42448038UL))) +#define bM4_I2S4_CTRL_FIFOR (*((volatile unsigned int*)(0x42448040UL))) +#define bM4_I2S4_CTRL_CODECRC (*((volatile unsigned int*)(0x42448044UL))) +#define bM4_I2S4_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42448048UL))) +#define bM4_I2S4_CTRL_SDOE (*((volatile unsigned int*)(0x4244804CUL))) +#define bM4_I2S4_CTRL_LRCKOE (*((volatile unsigned int*)(0x42448050UL))) +#define bM4_I2S4_CTRL_CKOE (*((volatile unsigned int*)(0x42448054UL))) +#define bM4_I2S4_CTRL_DUPLEX (*((volatile unsigned int*)(0x42448058UL))) +#define bM4_I2S4_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244805CUL))) +#define bM4_I2S4_SR_TXBA (*((volatile unsigned int*)(0x42448080UL))) +#define bM4_I2S4_SR_RXBA (*((volatile unsigned int*)(0x42448084UL))) +#define bM4_I2S4_SR_TXBE (*((volatile unsigned int*)(0x42448088UL))) +#define bM4_I2S4_SR_TXBF (*((volatile unsigned int*)(0x4244808CUL))) +#define bM4_I2S4_SR_RXBE (*((volatile unsigned int*)(0x42448090UL))) +#define bM4_I2S4_SR_RXBF (*((volatile unsigned int*)(0x42448094UL))) +#define bM4_I2S4_ER_TXERR (*((volatile unsigned int*)(0x42448100UL))) +#define bM4_I2S4_ER_RXERR (*((volatile unsigned int*)(0x42448104UL))) +#define bM4_I2S4_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42448180UL))) +#define bM4_I2S4_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42448184UL))) +#define bM4_I2S4_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42448188UL))) +#define bM4_I2S4_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244818CUL))) +#define bM4_I2S4_CFGR_CHLEN (*((volatile unsigned int*)(0x42448190UL))) +#define bM4_I2S4_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42448194UL))) +#define bM4_I2S4_PR_I2SDIV0 (*((volatile unsigned int*)(0x42448300UL))) +#define bM4_I2S4_PR_I2SDIV1 (*((volatile unsigned int*)(0x42448304UL))) +#define bM4_I2S4_PR_I2SDIV2 (*((volatile unsigned int*)(0x42448308UL))) +#define bM4_I2S4_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244830CUL))) +#define bM4_I2S4_PR_I2SDIV4 (*((volatile unsigned int*)(0x42448310UL))) +#define bM4_I2S4_PR_I2SDIV5 (*((volatile unsigned int*)(0x42448314UL))) +#define bM4_I2S4_PR_I2SDIV6 (*((volatile unsigned int*)(0x42448318UL))) +#define bM4_I2S4_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244831CUL))) +#define bM4_INTC_NMICR_NMITRG (*((volatile unsigned int*)(0x42A20000UL))) +#define bM4_INTC_NMICR_NSMPCLK0 (*((volatile unsigned int*)(0x42A20010UL))) +#define bM4_INTC_NMICR_NSMPCLK1 (*((volatile unsigned int*)(0x42A20014UL))) +#define bM4_INTC_NMICR_NFEN (*((volatile unsigned int*)(0x42A2001CUL))) +#define bM4_INTC_NMIENR_NMIENR (*((volatile unsigned int*)(0x42A20080UL))) +#define bM4_INTC_NMIENR_SWDTENR (*((volatile unsigned int*)(0x42A20084UL))) +#define bM4_INTC_NMIENR_PVD1ENR (*((volatile unsigned int*)(0x42A20088UL))) +#define bM4_INTC_NMIENR_PVD2ENR (*((volatile unsigned int*)(0x42A2008CUL))) +#define bM4_INTC_NMIENR_XTALSTPENR (*((volatile unsigned int*)(0x42A20094UL))) +#define bM4_INTC_NMIENR_REPENR (*((volatile unsigned int*)(0x42A200A0UL))) +#define bM4_INTC_NMIENR_RECCENR (*((volatile unsigned int*)(0x42A200A4UL))) +#define bM4_INTC_NMIENR_BUSMENR (*((volatile unsigned int*)(0x42A200A8UL))) +#define bM4_INTC_NMIENR_WDTENR (*((volatile unsigned int*)(0x42A200ACUL))) +#define bM4_INTC_NMIFR_NMIFR (*((volatile unsigned int*)(0x42A20100UL))) +#define bM4_INTC_NMIFR_SWDTFR (*((volatile unsigned int*)(0x42A20104UL))) +#define bM4_INTC_NMIFR_PVD1FR (*((volatile unsigned int*)(0x42A20108UL))) +#define bM4_INTC_NMIFR_PVD2FR (*((volatile unsigned int*)(0x42A2010CUL))) +#define bM4_INTC_NMIFR_XTALSTPFR (*((volatile unsigned int*)(0x42A20114UL))) +#define bM4_INTC_NMIFR_REPFR (*((volatile unsigned int*)(0x42A20120UL))) +#define bM4_INTC_NMIFR_RECCFR (*((volatile unsigned int*)(0x42A20124UL))) +#define bM4_INTC_NMIFR_BUSMFR (*((volatile unsigned int*)(0x42A20128UL))) +#define bM4_INTC_NMIFR_WDTFR (*((volatile unsigned int*)(0x42A2012CUL))) +#define bM4_INTC_NMICFR_NMICFR (*((volatile unsigned int*)(0x42A20180UL))) +#define bM4_INTC_NMICFR_SWDTCFR (*((volatile unsigned int*)(0x42A20184UL))) +#define bM4_INTC_NMICFR_PVD1CFR (*((volatile unsigned int*)(0x42A20188UL))) +#define bM4_INTC_NMICFR_PVD2CFR (*((volatile unsigned int*)(0x42A2018CUL))) +#define bM4_INTC_NMICFR_XTALSTPCFR (*((volatile unsigned int*)(0x42A20194UL))) +#define bM4_INTC_NMICFR_REPCFR (*((volatile unsigned int*)(0x42A201A0UL))) +#define bM4_INTC_NMICFR_RECCCFR (*((volatile unsigned int*)(0x42A201A4UL))) +#define bM4_INTC_NMICFR_BUSMCFR (*((volatile unsigned int*)(0x42A201A8UL))) +#define bM4_INTC_NMICFR_WDTCFR (*((volatile unsigned int*)(0x42A201ACUL))) +#define bM4_INTC_EIRQCR0_EIRQTRG0 (*((volatile unsigned int*)(0x42A20200UL))) +#define bM4_INTC_EIRQCR0_EIRQTRG1 (*((volatile unsigned int*)(0x42A20204UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK0 (*((volatile unsigned int*)(0x42A20210UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK1 (*((volatile unsigned int*)(0x42A20214UL))) +#define bM4_INTC_EIRQCR0_EFEN (*((volatile unsigned int*)(0x42A2021CUL))) +#define bM4_INTC_EIRQCR1_EIRQTRG0 (*((volatile unsigned int*)(0x42A20280UL))) +#define bM4_INTC_EIRQCR1_EIRQTRG1 (*((volatile unsigned int*)(0x42A20284UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK0 (*((volatile unsigned int*)(0x42A20290UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK1 (*((volatile unsigned int*)(0x42A20294UL))) +#define bM4_INTC_EIRQCR1_EFEN (*((volatile unsigned int*)(0x42A2029CUL))) +#define bM4_INTC_EIRQCR2_EIRQTRG0 (*((volatile unsigned int*)(0x42A20300UL))) +#define bM4_INTC_EIRQCR2_EIRQTRG1 (*((volatile unsigned int*)(0x42A20304UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK0 (*((volatile unsigned int*)(0x42A20310UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK1 (*((volatile unsigned int*)(0x42A20314UL))) +#define bM4_INTC_EIRQCR2_EFEN (*((volatile unsigned int*)(0x42A2031CUL))) +#define bM4_INTC_EIRQCR3_EIRQTRG0 (*((volatile unsigned int*)(0x42A20380UL))) +#define bM4_INTC_EIRQCR3_EIRQTRG1 (*((volatile unsigned int*)(0x42A20384UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK0 (*((volatile unsigned int*)(0x42A20390UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK1 (*((volatile unsigned int*)(0x42A20394UL))) +#define bM4_INTC_EIRQCR3_EFEN (*((volatile unsigned int*)(0x42A2039CUL))) +#define bM4_INTC_EIRQCR4_EIRQTRG0 (*((volatile unsigned int*)(0x42A20400UL))) +#define bM4_INTC_EIRQCR4_EIRQTRG1 (*((volatile unsigned int*)(0x42A20404UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK0 (*((volatile unsigned int*)(0x42A20410UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK1 (*((volatile unsigned int*)(0x42A20414UL))) +#define bM4_INTC_EIRQCR4_EFEN (*((volatile unsigned int*)(0x42A2041CUL))) +#define bM4_INTC_EIRQCR5_EIRQTRG0 (*((volatile unsigned int*)(0x42A20480UL))) +#define bM4_INTC_EIRQCR5_EIRQTRG1 (*((volatile unsigned int*)(0x42A20484UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK0 (*((volatile unsigned int*)(0x42A20490UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK1 (*((volatile unsigned int*)(0x42A20494UL))) +#define bM4_INTC_EIRQCR5_EFEN (*((volatile unsigned int*)(0x42A2049CUL))) +#define bM4_INTC_EIRQCR6_EIRQTRG0 (*((volatile unsigned int*)(0x42A20500UL))) +#define bM4_INTC_EIRQCR6_EIRQTRG1 (*((volatile unsigned int*)(0x42A20504UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK0 (*((volatile unsigned int*)(0x42A20510UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK1 (*((volatile unsigned int*)(0x42A20514UL))) +#define bM4_INTC_EIRQCR6_EFEN (*((volatile unsigned int*)(0x42A2051CUL))) +#define bM4_INTC_EIRQCR7_EIRQTRG0 (*((volatile unsigned int*)(0x42A20580UL))) +#define bM4_INTC_EIRQCR7_EIRQTRG1 (*((volatile unsigned int*)(0x42A20584UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK0 (*((volatile unsigned int*)(0x42A20590UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK1 (*((volatile unsigned int*)(0x42A20594UL))) +#define bM4_INTC_EIRQCR7_EFEN (*((volatile unsigned int*)(0x42A2059CUL))) +#define bM4_INTC_EIRQCR8_EIRQTRG0 (*((volatile unsigned int*)(0x42A20600UL))) +#define bM4_INTC_EIRQCR8_EIRQTRG1 (*((volatile unsigned int*)(0x42A20604UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK0 (*((volatile unsigned int*)(0x42A20610UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK1 (*((volatile unsigned int*)(0x42A20614UL))) +#define bM4_INTC_EIRQCR8_EFEN (*((volatile unsigned int*)(0x42A2061CUL))) +#define bM4_INTC_EIRQCR9_EIRQTRG0 (*((volatile unsigned int*)(0x42A20680UL))) +#define bM4_INTC_EIRQCR9_EIRQTRG1 (*((volatile unsigned int*)(0x42A20684UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK0 (*((volatile unsigned int*)(0x42A20690UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK1 (*((volatile unsigned int*)(0x42A20694UL))) +#define bM4_INTC_EIRQCR9_EFEN (*((volatile unsigned int*)(0x42A2069CUL))) +#define bM4_INTC_EIRQCR10_EIRQTRG0 (*((volatile unsigned int*)(0x42A20700UL))) +#define bM4_INTC_EIRQCR10_EIRQTRG1 (*((volatile unsigned int*)(0x42A20704UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK0 (*((volatile unsigned int*)(0x42A20710UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK1 (*((volatile unsigned int*)(0x42A20714UL))) +#define bM4_INTC_EIRQCR10_EFEN (*((volatile unsigned int*)(0x42A2071CUL))) +#define bM4_INTC_EIRQCR11_EIRQTRG0 (*((volatile unsigned int*)(0x42A20780UL))) +#define bM4_INTC_EIRQCR11_EIRQTRG1 (*((volatile unsigned int*)(0x42A20784UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK0 (*((volatile unsigned int*)(0x42A20790UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK1 (*((volatile unsigned int*)(0x42A20794UL))) +#define bM4_INTC_EIRQCR11_EFEN (*((volatile unsigned int*)(0x42A2079CUL))) +#define bM4_INTC_EIRQCR12_EIRQTRG0 (*((volatile unsigned int*)(0x42A20800UL))) +#define bM4_INTC_EIRQCR12_EIRQTRG1 (*((volatile unsigned int*)(0x42A20804UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK0 (*((volatile unsigned int*)(0x42A20810UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK1 (*((volatile unsigned int*)(0x42A20814UL))) +#define bM4_INTC_EIRQCR12_EFEN (*((volatile unsigned int*)(0x42A2081CUL))) +#define bM4_INTC_EIRQCR13_EIRQTRG0 (*((volatile unsigned int*)(0x42A20880UL))) +#define bM4_INTC_EIRQCR13_EIRQTRG1 (*((volatile unsigned int*)(0x42A20884UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK0 (*((volatile unsigned int*)(0x42A20890UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK1 (*((volatile unsigned int*)(0x42A20894UL))) +#define bM4_INTC_EIRQCR13_EFEN (*((volatile unsigned int*)(0x42A2089CUL))) +#define bM4_INTC_EIRQCR14_EIRQTRG0 (*((volatile unsigned int*)(0x42A20900UL))) +#define bM4_INTC_EIRQCR14_EIRQTRG1 (*((volatile unsigned int*)(0x42A20904UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK0 (*((volatile unsigned int*)(0x42A20910UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK1 (*((volatile unsigned int*)(0x42A20914UL))) +#define bM4_INTC_EIRQCR14_EFEN (*((volatile unsigned int*)(0x42A2091CUL))) +#define bM4_INTC_EIRQCR15_EIRQTRG0 (*((volatile unsigned int*)(0x42A20980UL))) +#define bM4_INTC_EIRQCR15_EIRQTRG1 (*((volatile unsigned int*)(0x42A20984UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK0 (*((volatile unsigned int*)(0x42A20990UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK1 (*((volatile unsigned int*)(0x42A20994UL))) +#define bM4_INTC_EIRQCR15_EFEN (*((volatile unsigned int*)(0x42A2099CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN0 (*((volatile unsigned int*)(0x42A20A00UL))) +#define bM4_INTC_WUPEN_EIRQWUEN1 (*((volatile unsigned int*)(0x42A20A04UL))) +#define bM4_INTC_WUPEN_EIRQWUEN2 (*((volatile unsigned int*)(0x42A20A08UL))) +#define bM4_INTC_WUPEN_EIRQWUEN3 (*((volatile unsigned int*)(0x42A20A0CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN4 (*((volatile unsigned int*)(0x42A20A10UL))) +#define bM4_INTC_WUPEN_EIRQWUEN5 (*((volatile unsigned int*)(0x42A20A14UL))) +#define bM4_INTC_WUPEN_EIRQWUEN6 (*((volatile unsigned int*)(0x42A20A18UL))) +#define bM4_INTC_WUPEN_EIRQWUEN7 (*((volatile unsigned int*)(0x42A20A1CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN8 (*((volatile unsigned int*)(0x42A20A20UL))) +#define bM4_INTC_WUPEN_EIRQWUEN9 (*((volatile unsigned int*)(0x42A20A24UL))) +#define bM4_INTC_WUPEN_EIRQWUEN10 (*((volatile unsigned int*)(0x42A20A28UL))) +#define bM4_INTC_WUPEN_EIRQWUEN11 (*((volatile unsigned int*)(0x42A20A2CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN12 (*((volatile unsigned int*)(0x42A20A30UL))) +#define bM4_INTC_WUPEN_EIRQWUEN13 (*((volatile unsigned int*)(0x42A20A34UL))) +#define bM4_INTC_WUPEN_EIRQWUEN14 (*((volatile unsigned int*)(0x42A20A38UL))) +#define bM4_INTC_WUPEN_EIRQWUEN15 (*((volatile unsigned int*)(0x42A20A3CUL))) +#define bM4_INTC_WUPEN_SWDTWUEN (*((volatile unsigned int*)(0x42A20A40UL))) +#define bM4_INTC_WUPEN_PVD1WUEN (*((volatile unsigned int*)(0x42A20A44UL))) +#define bM4_INTC_WUPEN_PVD2WUEN (*((volatile unsigned int*)(0x42A20A48UL))) +#define bM4_INTC_WUPEN_CMPI0WUEN (*((volatile unsigned int*)(0x42A20A4CUL))) +#define bM4_INTC_WUPEN_WKTMWUEN (*((volatile unsigned int*)(0x42A20A50UL))) +#define bM4_INTC_WUPEN_RTCALMWUEN (*((volatile unsigned int*)(0x42A20A54UL))) +#define bM4_INTC_WUPEN_RTCPRDWUEN (*((volatile unsigned int*)(0x42A20A58UL))) +#define bM4_INTC_WUPEN_TMR0WUEN (*((volatile unsigned int*)(0x42A20A5CUL))) +#define bM4_INTC_WUPEN_RXWUEN (*((volatile unsigned int*)(0x42A20A64UL))) +#define bM4_INTC_EIFR_EIFR0 (*((volatile unsigned int*)(0x42A20A80UL))) +#define bM4_INTC_EIFR_EIFR1 (*((volatile unsigned int*)(0x42A20A84UL))) +#define bM4_INTC_EIFR_EIFR2 (*((volatile unsigned int*)(0x42A20A88UL))) +#define bM4_INTC_EIFR_EIFR3 (*((volatile unsigned int*)(0x42A20A8CUL))) +#define bM4_INTC_EIFR_EIFR4 (*((volatile unsigned int*)(0x42A20A90UL))) +#define bM4_INTC_EIFR_EIFR5 (*((volatile unsigned int*)(0x42A20A94UL))) +#define bM4_INTC_EIFR_EIFR6 (*((volatile unsigned int*)(0x42A20A98UL))) +#define bM4_INTC_EIFR_EIFR7 (*((volatile unsigned int*)(0x42A20A9CUL))) +#define bM4_INTC_EIFR_EIFR8 (*((volatile unsigned int*)(0x42A20AA0UL))) +#define bM4_INTC_EIFR_EIFR9 (*((volatile unsigned int*)(0x42A20AA4UL))) +#define bM4_INTC_EIFR_EIFR10 (*((volatile unsigned int*)(0x42A20AA8UL))) +#define bM4_INTC_EIFR_EIFR11 (*((volatile unsigned int*)(0x42A20AACUL))) +#define bM4_INTC_EIFR_EIFR12 (*((volatile unsigned int*)(0x42A20AB0UL))) +#define bM4_INTC_EIFR_EIFR13 (*((volatile unsigned int*)(0x42A20AB4UL))) +#define bM4_INTC_EIFR_EIFR14 (*((volatile unsigned int*)(0x42A20AB8UL))) +#define bM4_INTC_EIFR_EIFR15 (*((volatile unsigned int*)(0x42A20ABCUL))) +#define bM4_INTC_EICFR_EICFR0 (*((volatile unsigned int*)(0x42A20B00UL))) +#define bM4_INTC_EICFR_EICFR1 (*((volatile unsigned int*)(0x42A20B04UL))) +#define bM4_INTC_EICFR_EICFR2 (*((volatile unsigned int*)(0x42A20B08UL))) +#define bM4_INTC_EICFR_EICFR3 (*((volatile unsigned int*)(0x42A20B0CUL))) +#define bM4_INTC_EICFR_EICFR4 (*((volatile unsigned int*)(0x42A20B10UL))) +#define bM4_INTC_EICFR_EICFR5 (*((volatile unsigned int*)(0x42A20B14UL))) +#define bM4_INTC_EICFR_EICFR6 (*((volatile unsigned int*)(0x42A20B18UL))) +#define bM4_INTC_EICFR_EICFR7 (*((volatile unsigned int*)(0x42A20B1CUL))) +#define bM4_INTC_EICFR_EICFR8 (*((volatile unsigned int*)(0x42A20B20UL))) +#define bM4_INTC_EICFR_EICFR9 (*((volatile unsigned int*)(0x42A20B24UL))) +#define bM4_INTC_EICFR_EICFR10 (*((volatile unsigned int*)(0x42A20B28UL))) +#define bM4_INTC_EICFR_EICFR11 (*((volatile unsigned int*)(0x42A20B2CUL))) +#define bM4_INTC_EICFR_EICFR12 (*((volatile unsigned int*)(0x42A20B30UL))) +#define bM4_INTC_EICFR_EICFR13 (*((volatile unsigned int*)(0x42A20B34UL))) +#define bM4_INTC_EICFR_EICFR14 (*((volatile unsigned int*)(0x42A20B38UL))) +#define bM4_INTC_EICFR_EICFR15 (*((volatile unsigned int*)(0x42A20B3CUL))) +#define bM4_INTC_SEL0_INTSEL0 (*((volatile unsigned int*)(0x42A20B80UL))) +#define bM4_INTC_SEL0_INTSEL1 (*((volatile unsigned int*)(0x42A20B84UL))) +#define bM4_INTC_SEL0_INTSEL2 (*((volatile unsigned int*)(0x42A20B88UL))) +#define bM4_INTC_SEL0_INTSEL3 (*((volatile unsigned int*)(0x42A20B8CUL))) +#define bM4_INTC_SEL0_INTSEL4 (*((volatile unsigned int*)(0x42A20B90UL))) +#define bM4_INTC_SEL0_INTSEL5 (*((volatile unsigned int*)(0x42A20B94UL))) +#define bM4_INTC_SEL0_INTSEL6 (*((volatile unsigned int*)(0x42A20B98UL))) +#define bM4_INTC_SEL0_INTSEL7 (*((volatile unsigned int*)(0x42A20B9CUL))) +#define bM4_INTC_SEL0_INTSEL8 (*((volatile unsigned int*)(0x42A20BA0UL))) +#define bM4_INTC_SEL1_INTSEL0 (*((volatile unsigned int*)(0x42A20C00UL))) +#define bM4_INTC_SEL1_INTSEL1 (*((volatile unsigned int*)(0x42A20C04UL))) +#define bM4_INTC_SEL1_INTSEL2 (*((volatile unsigned int*)(0x42A20C08UL))) +#define bM4_INTC_SEL1_INTSEL3 (*((volatile unsigned int*)(0x42A20C0CUL))) +#define bM4_INTC_SEL1_INTSEL4 (*((volatile unsigned int*)(0x42A20C10UL))) +#define bM4_INTC_SEL1_INTSEL5 (*((volatile unsigned int*)(0x42A20C14UL))) +#define bM4_INTC_SEL1_INTSEL6 (*((volatile unsigned int*)(0x42A20C18UL))) +#define bM4_INTC_SEL1_INTSEL7 (*((volatile unsigned int*)(0x42A20C1CUL))) +#define bM4_INTC_SEL1_INTSEL8 (*((volatile unsigned int*)(0x42A20C20UL))) +#define bM4_INTC_SEL2_INTSEL0 (*((volatile unsigned int*)(0x42A20C80UL))) +#define bM4_INTC_SEL2_INTSEL1 (*((volatile unsigned int*)(0x42A20C84UL))) +#define bM4_INTC_SEL2_INTSEL2 (*((volatile unsigned int*)(0x42A20C88UL))) +#define bM4_INTC_SEL2_INTSEL3 (*((volatile unsigned int*)(0x42A20C8CUL))) +#define bM4_INTC_SEL2_INTSEL4 (*((volatile unsigned int*)(0x42A20C90UL))) +#define bM4_INTC_SEL2_INTSEL5 (*((volatile unsigned int*)(0x42A20C94UL))) +#define bM4_INTC_SEL2_INTSEL6 (*((volatile unsigned int*)(0x42A20C98UL))) +#define bM4_INTC_SEL2_INTSEL7 (*((volatile unsigned int*)(0x42A20C9CUL))) +#define bM4_INTC_SEL2_INTSEL8 (*((volatile unsigned int*)(0x42A20CA0UL))) +#define bM4_INTC_SEL3_INTSEL0 (*((volatile unsigned int*)(0x42A20D00UL))) +#define bM4_INTC_SEL3_INTSEL1 (*((volatile unsigned int*)(0x42A20D04UL))) +#define bM4_INTC_SEL3_INTSEL2 (*((volatile unsigned int*)(0x42A20D08UL))) +#define bM4_INTC_SEL3_INTSEL3 (*((volatile unsigned int*)(0x42A20D0CUL))) +#define bM4_INTC_SEL3_INTSEL4 (*((volatile unsigned int*)(0x42A20D10UL))) +#define bM4_INTC_SEL3_INTSEL5 (*((volatile unsigned int*)(0x42A20D14UL))) +#define bM4_INTC_SEL3_INTSEL6 (*((volatile unsigned int*)(0x42A20D18UL))) +#define bM4_INTC_SEL3_INTSEL7 (*((volatile unsigned int*)(0x42A20D1CUL))) +#define bM4_INTC_SEL3_INTSEL8 (*((volatile unsigned int*)(0x42A20D20UL))) +#define bM4_INTC_SEL4_INTSEL0 (*((volatile unsigned int*)(0x42A20D80UL))) +#define bM4_INTC_SEL4_INTSEL1 (*((volatile unsigned int*)(0x42A20D84UL))) +#define bM4_INTC_SEL4_INTSEL2 (*((volatile unsigned int*)(0x42A20D88UL))) +#define bM4_INTC_SEL4_INTSEL3 (*((volatile unsigned int*)(0x42A20D8CUL))) +#define bM4_INTC_SEL4_INTSEL4 (*((volatile unsigned int*)(0x42A20D90UL))) +#define bM4_INTC_SEL4_INTSEL5 (*((volatile unsigned int*)(0x42A20D94UL))) +#define bM4_INTC_SEL4_INTSEL6 (*((volatile unsigned int*)(0x42A20D98UL))) +#define bM4_INTC_SEL4_INTSEL7 (*((volatile unsigned int*)(0x42A20D9CUL))) +#define bM4_INTC_SEL4_INTSEL8 (*((volatile unsigned int*)(0x42A20DA0UL))) +#define bM4_INTC_SEL5_INTSEL0 (*((volatile unsigned int*)(0x42A20E00UL))) +#define bM4_INTC_SEL5_INTSEL1 (*((volatile unsigned int*)(0x42A20E04UL))) +#define bM4_INTC_SEL5_INTSEL2 (*((volatile unsigned int*)(0x42A20E08UL))) +#define bM4_INTC_SEL5_INTSEL3 (*((volatile unsigned int*)(0x42A20E0CUL))) +#define bM4_INTC_SEL5_INTSEL4 (*((volatile unsigned int*)(0x42A20E10UL))) +#define bM4_INTC_SEL5_INTSEL5 (*((volatile unsigned int*)(0x42A20E14UL))) +#define bM4_INTC_SEL5_INTSEL6 (*((volatile unsigned int*)(0x42A20E18UL))) +#define bM4_INTC_SEL5_INTSEL7 (*((volatile unsigned int*)(0x42A20E1CUL))) +#define bM4_INTC_SEL5_INTSEL8 (*((volatile unsigned int*)(0x42A20E20UL))) +#define bM4_INTC_SEL6_INTSEL0 (*((volatile unsigned int*)(0x42A20E80UL))) +#define bM4_INTC_SEL6_INTSEL1 (*((volatile unsigned int*)(0x42A20E84UL))) +#define bM4_INTC_SEL6_INTSEL2 (*((volatile unsigned int*)(0x42A20E88UL))) +#define bM4_INTC_SEL6_INTSEL3 (*((volatile unsigned int*)(0x42A20E8CUL))) +#define bM4_INTC_SEL6_INTSEL4 (*((volatile unsigned int*)(0x42A20E90UL))) +#define bM4_INTC_SEL6_INTSEL5 (*((volatile unsigned int*)(0x42A20E94UL))) +#define bM4_INTC_SEL6_INTSEL6 (*((volatile unsigned int*)(0x42A20E98UL))) +#define bM4_INTC_SEL6_INTSEL7 (*((volatile unsigned int*)(0x42A20E9CUL))) +#define bM4_INTC_SEL6_INTSEL8 (*((volatile unsigned int*)(0x42A20EA0UL))) +#define bM4_INTC_SEL7_INTSEL0 (*((volatile unsigned int*)(0x42A20F00UL))) +#define bM4_INTC_SEL7_INTSEL1 (*((volatile unsigned int*)(0x42A20F04UL))) +#define bM4_INTC_SEL7_INTSEL2 (*((volatile unsigned int*)(0x42A20F08UL))) +#define bM4_INTC_SEL7_INTSEL3 (*((volatile unsigned int*)(0x42A20F0CUL))) +#define bM4_INTC_SEL7_INTSEL4 (*((volatile unsigned int*)(0x42A20F10UL))) +#define bM4_INTC_SEL7_INTSEL5 (*((volatile unsigned int*)(0x42A20F14UL))) +#define bM4_INTC_SEL7_INTSEL6 (*((volatile unsigned int*)(0x42A20F18UL))) +#define bM4_INTC_SEL7_INTSEL7 (*((volatile unsigned int*)(0x42A20F1CUL))) +#define bM4_INTC_SEL7_INTSEL8 (*((volatile unsigned int*)(0x42A20F20UL))) +#define bM4_INTC_SEL8_INTSEL0 (*((volatile unsigned int*)(0x42A20F80UL))) +#define bM4_INTC_SEL8_INTSEL1 (*((volatile unsigned int*)(0x42A20F84UL))) +#define bM4_INTC_SEL8_INTSEL2 (*((volatile unsigned int*)(0x42A20F88UL))) +#define bM4_INTC_SEL8_INTSEL3 (*((volatile unsigned int*)(0x42A20F8CUL))) +#define bM4_INTC_SEL8_INTSEL4 (*((volatile unsigned int*)(0x42A20F90UL))) +#define bM4_INTC_SEL8_INTSEL5 (*((volatile unsigned int*)(0x42A20F94UL))) +#define bM4_INTC_SEL8_INTSEL6 (*((volatile unsigned int*)(0x42A20F98UL))) +#define bM4_INTC_SEL8_INTSEL7 (*((volatile unsigned int*)(0x42A20F9CUL))) +#define bM4_INTC_SEL8_INTSEL8 (*((volatile unsigned int*)(0x42A20FA0UL))) +#define bM4_INTC_SEL9_INTSEL0 (*((volatile unsigned int*)(0x42A21000UL))) +#define bM4_INTC_SEL9_INTSEL1 (*((volatile unsigned int*)(0x42A21004UL))) +#define bM4_INTC_SEL9_INTSEL2 (*((volatile unsigned int*)(0x42A21008UL))) +#define bM4_INTC_SEL9_INTSEL3 (*((volatile unsigned int*)(0x42A2100CUL))) +#define bM4_INTC_SEL9_INTSEL4 (*((volatile unsigned int*)(0x42A21010UL))) +#define bM4_INTC_SEL9_INTSEL5 (*((volatile unsigned int*)(0x42A21014UL))) +#define bM4_INTC_SEL9_INTSEL6 (*((volatile unsigned int*)(0x42A21018UL))) +#define bM4_INTC_SEL9_INTSEL7 (*((volatile unsigned int*)(0x42A2101CUL))) +#define bM4_INTC_SEL9_INTSEL8 (*((volatile unsigned int*)(0x42A21020UL))) +#define bM4_INTC_SEL10_INTSEL0 (*((volatile unsigned int*)(0x42A21080UL))) +#define bM4_INTC_SEL10_INTSEL1 (*((volatile unsigned int*)(0x42A21084UL))) +#define bM4_INTC_SEL10_INTSEL2 (*((volatile unsigned int*)(0x42A21088UL))) +#define bM4_INTC_SEL10_INTSEL3 (*((volatile unsigned int*)(0x42A2108CUL))) +#define bM4_INTC_SEL10_INTSEL4 (*((volatile unsigned int*)(0x42A21090UL))) +#define bM4_INTC_SEL10_INTSEL5 (*((volatile unsigned int*)(0x42A21094UL))) +#define bM4_INTC_SEL10_INTSEL6 (*((volatile unsigned int*)(0x42A21098UL))) +#define bM4_INTC_SEL10_INTSEL7 (*((volatile unsigned int*)(0x42A2109CUL))) +#define bM4_INTC_SEL10_INTSEL8 (*((volatile unsigned int*)(0x42A210A0UL))) +#define bM4_INTC_SEL11_INTSEL0 (*((volatile unsigned int*)(0x42A21100UL))) +#define bM4_INTC_SEL11_INTSEL1 (*((volatile unsigned int*)(0x42A21104UL))) +#define bM4_INTC_SEL11_INTSEL2 (*((volatile unsigned int*)(0x42A21108UL))) +#define bM4_INTC_SEL11_INTSEL3 (*((volatile unsigned int*)(0x42A2110CUL))) +#define bM4_INTC_SEL11_INTSEL4 (*((volatile unsigned int*)(0x42A21110UL))) +#define bM4_INTC_SEL11_INTSEL5 (*((volatile unsigned int*)(0x42A21114UL))) +#define bM4_INTC_SEL11_INTSEL6 (*((volatile unsigned int*)(0x42A21118UL))) +#define bM4_INTC_SEL11_INTSEL7 (*((volatile unsigned int*)(0x42A2111CUL))) +#define bM4_INTC_SEL11_INTSEL8 (*((volatile unsigned int*)(0x42A21120UL))) +#define bM4_INTC_SEL12_INTSEL0 (*((volatile unsigned int*)(0x42A21180UL))) +#define bM4_INTC_SEL12_INTSEL1 (*((volatile unsigned int*)(0x42A21184UL))) +#define bM4_INTC_SEL12_INTSEL2 (*((volatile unsigned int*)(0x42A21188UL))) +#define bM4_INTC_SEL12_INTSEL3 (*((volatile unsigned int*)(0x42A2118CUL))) +#define bM4_INTC_SEL12_INTSEL4 (*((volatile unsigned int*)(0x42A21190UL))) +#define bM4_INTC_SEL12_INTSEL5 (*((volatile unsigned int*)(0x42A21194UL))) +#define bM4_INTC_SEL12_INTSEL6 (*((volatile unsigned int*)(0x42A21198UL))) +#define bM4_INTC_SEL12_INTSEL7 (*((volatile unsigned int*)(0x42A2119CUL))) +#define bM4_INTC_SEL12_INTSEL8 (*((volatile unsigned int*)(0x42A211A0UL))) +#define bM4_INTC_SEL13_INTSEL0 (*((volatile unsigned int*)(0x42A21200UL))) +#define bM4_INTC_SEL13_INTSEL1 (*((volatile unsigned int*)(0x42A21204UL))) +#define bM4_INTC_SEL13_INTSEL2 (*((volatile unsigned int*)(0x42A21208UL))) +#define bM4_INTC_SEL13_INTSEL3 (*((volatile unsigned int*)(0x42A2120CUL))) +#define bM4_INTC_SEL13_INTSEL4 (*((volatile unsigned int*)(0x42A21210UL))) +#define bM4_INTC_SEL13_INTSEL5 (*((volatile unsigned int*)(0x42A21214UL))) +#define bM4_INTC_SEL13_INTSEL6 (*((volatile unsigned int*)(0x42A21218UL))) +#define bM4_INTC_SEL13_INTSEL7 (*((volatile unsigned int*)(0x42A2121CUL))) +#define bM4_INTC_SEL13_INTSEL8 (*((volatile unsigned int*)(0x42A21220UL))) +#define bM4_INTC_SEL14_INTSEL0 (*((volatile unsigned int*)(0x42A21280UL))) +#define bM4_INTC_SEL14_INTSEL1 (*((volatile unsigned int*)(0x42A21284UL))) +#define bM4_INTC_SEL14_INTSEL2 (*((volatile unsigned int*)(0x42A21288UL))) +#define bM4_INTC_SEL14_INTSEL3 (*((volatile unsigned int*)(0x42A2128CUL))) +#define bM4_INTC_SEL14_INTSEL4 (*((volatile unsigned int*)(0x42A21290UL))) +#define bM4_INTC_SEL14_INTSEL5 (*((volatile unsigned int*)(0x42A21294UL))) +#define bM4_INTC_SEL14_INTSEL6 (*((volatile unsigned int*)(0x42A21298UL))) +#define bM4_INTC_SEL14_INTSEL7 (*((volatile unsigned int*)(0x42A2129CUL))) +#define bM4_INTC_SEL14_INTSEL8 (*((volatile unsigned int*)(0x42A212A0UL))) +#define bM4_INTC_SEL15_INTSEL0 (*((volatile unsigned int*)(0x42A21300UL))) +#define bM4_INTC_SEL15_INTSEL1 (*((volatile unsigned int*)(0x42A21304UL))) +#define bM4_INTC_SEL15_INTSEL2 (*((volatile unsigned int*)(0x42A21308UL))) +#define bM4_INTC_SEL15_INTSEL3 (*((volatile unsigned int*)(0x42A2130CUL))) +#define bM4_INTC_SEL15_INTSEL4 (*((volatile unsigned int*)(0x42A21310UL))) +#define bM4_INTC_SEL15_INTSEL5 (*((volatile unsigned int*)(0x42A21314UL))) +#define bM4_INTC_SEL15_INTSEL6 (*((volatile unsigned int*)(0x42A21318UL))) +#define bM4_INTC_SEL15_INTSEL7 (*((volatile unsigned int*)(0x42A2131CUL))) +#define bM4_INTC_SEL15_INTSEL8 (*((volatile unsigned int*)(0x42A21320UL))) +#define bM4_INTC_SEL16_INTSEL0 (*((volatile unsigned int*)(0x42A21380UL))) +#define bM4_INTC_SEL16_INTSEL1 (*((volatile unsigned int*)(0x42A21384UL))) +#define bM4_INTC_SEL16_INTSEL2 (*((volatile unsigned int*)(0x42A21388UL))) +#define bM4_INTC_SEL16_INTSEL3 (*((volatile unsigned int*)(0x42A2138CUL))) +#define bM4_INTC_SEL16_INTSEL4 (*((volatile unsigned int*)(0x42A21390UL))) +#define bM4_INTC_SEL16_INTSEL5 (*((volatile unsigned int*)(0x42A21394UL))) +#define bM4_INTC_SEL16_INTSEL6 (*((volatile unsigned int*)(0x42A21398UL))) +#define bM4_INTC_SEL16_INTSEL7 (*((volatile unsigned int*)(0x42A2139CUL))) +#define bM4_INTC_SEL16_INTSEL8 (*((volatile unsigned int*)(0x42A213A0UL))) +#define bM4_INTC_SEL17_INTSEL0 (*((volatile unsigned int*)(0x42A21400UL))) +#define bM4_INTC_SEL17_INTSEL1 (*((volatile unsigned int*)(0x42A21404UL))) +#define bM4_INTC_SEL17_INTSEL2 (*((volatile unsigned int*)(0x42A21408UL))) +#define bM4_INTC_SEL17_INTSEL3 (*((volatile unsigned int*)(0x42A2140CUL))) +#define bM4_INTC_SEL17_INTSEL4 (*((volatile unsigned int*)(0x42A21410UL))) +#define bM4_INTC_SEL17_INTSEL5 (*((volatile unsigned int*)(0x42A21414UL))) +#define bM4_INTC_SEL17_INTSEL6 (*((volatile unsigned int*)(0x42A21418UL))) +#define bM4_INTC_SEL17_INTSEL7 (*((volatile unsigned int*)(0x42A2141CUL))) +#define bM4_INTC_SEL17_INTSEL8 (*((volatile unsigned int*)(0x42A21420UL))) +#define bM4_INTC_SEL18_INTSEL0 (*((volatile unsigned int*)(0x42A21480UL))) +#define bM4_INTC_SEL18_INTSEL1 (*((volatile unsigned int*)(0x42A21484UL))) +#define bM4_INTC_SEL18_INTSEL2 (*((volatile unsigned int*)(0x42A21488UL))) +#define bM4_INTC_SEL18_INTSEL3 (*((volatile unsigned int*)(0x42A2148CUL))) +#define bM4_INTC_SEL18_INTSEL4 (*((volatile unsigned int*)(0x42A21490UL))) +#define bM4_INTC_SEL18_INTSEL5 (*((volatile unsigned int*)(0x42A21494UL))) +#define bM4_INTC_SEL18_INTSEL6 (*((volatile unsigned int*)(0x42A21498UL))) +#define bM4_INTC_SEL18_INTSEL7 (*((volatile unsigned int*)(0x42A2149CUL))) +#define bM4_INTC_SEL18_INTSEL8 (*((volatile unsigned int*)(0x42A214A0UL))) +#define bM4_INTC_SEL19_INTSEL0 (*((volatile unsigned int*)(0x42A21500UL))) +#define bM4_INTC_SEL19_INTSEL1 (*((volatile unsigned int*)(0x42A21504UL))) +#define bM4_INTC_SEL19_INTSEL2 (*((volatile unsigned int*)(0x42A21508UL))) +#define bM4_INTC_SEL19_INTSEL3 (*((volatile unsigned int*)(0x42A2150CUL))) +#define bM4_INTC_SEL19_INTSEL4 (*((volatile unsigned int*)(0x42A21510UL))) +#define bM4_INTC_SEL19_INTSEL5 (*((volatile unsigned int*)(0x42A21514UL))) +#define bM4_INTC_SEL19_INTSEL6 (*((volatile unsigned int*)(0x42A21518UL))) +#define bM4_INTC_SEL19_INTSEL7 (*((volatile unsigned int*)(0x42A2151CUL))) +#define bM4_INTC_SEL19_INTSEL8 (*((volatile unsigned int*)(0x42A21520UL))) +#define bM4_INTC_SEL20_INTSEL0 (*((volatile unsigned int*)(0x42A21580UL))) +#define bM4_INTC_SEL20_INTSEL1 (*((volatile unsigned int*)(0x42A21584UL))) +#define bM4_INTC_SEL20_INTSEL2 (*((volatile unsigned int*)(0x42A21588UL))) +#define bM4_INTC_SEL20_INTSEL3 (*((volatile unsigned int*)(0x42A2158CUL))) +#define bM4_INTC_SEL20_INTSEL4 (*((volatile unsigned int*)(0x42A21590UL))) +#define bM4_INTC_SEL20_INTSEL5 (*((volatile unsigned int*)(0x42A21594UL))) +#define bM4_INTC_SEL20_INTSEL6 (*((volatile unsigned int*)(0x42A21598UL))) +#define bM4_INTC_SEL20_INTSEL7 (*((volatile unsigned int*)(0x42A2159CUL))) +#define bM4_INTC_SEL20_INTSEL8 (*((volatile unsigned int*)(0x42A215A0UL))) +#define bM4_INTC_SEL21_INTSEL0 (*((volatile unsigned int*)(0x42A21600UL))) +#define bM4_INTC_SEL21_INTSEL1 (*((volatile unsigned int*)(0x42A21604UL))) +#define bM4_INTC_SEL21_INTSEL2 (*((volatile unsigned int*)(0x42A21608UL))) +#define bM4_INTC_SEL21_INTSEL3 (*((volatile unsigned int*)(0x42A2160CUL))) +#define bM4_INTC_SEL21_INTSEL4 (*((volatile unsigned int*)(0x42A21610UL))) +#define bM4_INTC_SEL21_INTSEL5 (*((volatile unsigned int*)(0x42A21614UL))) +#define bM4_INTC_SEL21_INTSEL6 (*((volatile unsigned int*)(0x42A21618UL))) +#define bM4_INTC_SEL21_INTSEL7 (*((volatile unsigned int*)(0x42A2161CUL))) +#define bM4_INTC_SEL21_INTSEL8 (*((volatile unsigned int*)(0x42A21620UL))) +#define bM4_INTC_SEL22_INTSEL0 (*((volatile unsigned int*)(0x42A21680UL))) +#define bM4_INTC_SEL22_INTSEL1 (*((volatile unsigned int*)(0x42A21684UL))) +#define bM4_INTC_SEL22_INTSEL2 (*((volatile unsigned int*)(0x42A21688UL))) +#define bM4_INTC_SEL22_INTSEL3 (*((volatile unsigned int*)(0x42A2168CUL))) +#define bM4_INTC_SEL22_INTSEL4 (*((volatile unsigned int*)(0x42A21690UL))) +#define bM4_INTC_SEL22_INTSEL5 (*((volatile unsigned int*)(0x42A21694UL))) +#define bM4_INTC_SEL22_INTSEL6 (*((volatile unsigned int*)(0x42A21698UL))) +#define bM4_INTC_SEL22_INTSEL7 (*((volatile unsigned int*)(0x42A2169CUL))) +#define bM4_INTC_SEL22_INTSEL8 (*((volatile unsigned int*)(0x42A216A0UL))) +#define bM4_INTC_SEL23_INTSEL0 (*((volatile unsigned int*)(0x42A21700UL))) +#define bM4_INTC_SEL23_INTSEL1 (*((volatile unsigned int*)(0x42A21704UL))) +#define bM4_INTC_SEL23_INTSEL2 (*((volatile unsigned int*)(0x42A21708UL))) +#define bM4_INTC_SEL23_INTSEL3 (*((volatile unsigned int*)(0x42A2170CUL))) +#define bM4_INTC_SEL23_INTSEL4 (*((volatile unsigned int*)(0x42A21710UL))) +#define bM4_INTC_SEL23_INTSEL5 (*((volatile unsigned int*)(0x42A21714UL))) +#define bM4_INTC_SEL23_INTSEL6 (*((volatile unsigned int*)(0x42A21718UL))) +#define bM4_INTC_SEL23_INTSEL7 (*((volatile unsigned int*)(0x42A2171CUL))) +#define bM4_INTC_SEL23_INTSEL8 (*((volatile unsigned int*)(0x42A21720UL))) +#define bM4_INTC_SEL24_INTSEL0 (*((volatile unsigned int*)(0x42A21780UL))) +#define bM4_INTC_SEL24_INTSEL1 (*((volatile unsigned int*)(0x42A21784UL))) +#define bM4_INTC_SEL24_INTSEL2 (*((volatile unsigned int*)(0x42A21788UL))) +#define bM4_INTC_SEL24_INTSEL3 (*((volatile unsigned int*)(0x42A2178CUL))) +#define bM4_INTC_SEL24_INTSEL4 (*((volatile unsigned int*)(0x42A21790UL))) +#define bM4_INTC_SEL24_INTSEL5 (*((volatile unsigned int*)(0x42A21794UL))) +#define bM4_INTC_SEL24_INTSEL6 (*((volatile unsigned int*)(0x42A21798UL))) +#define bM4_INTC_SEL24_INTSEL7 (*((volatile unsigned int*)(0x42A2179CUL))) +#define bM4_INTC_SEL24_INTSEL8 (*((volatile unsigned int*)(0x42A217A0UL))) +#define bM4_INTC_SEL25_INTSEL0 (*((volatile unsigned int*)(0x42A21800UL))) +#define bM4_INTC_SEL25_INTSEL1 (*((volatile unsigned int*)(0x42A21804UL))) +#define bM4_INTC_SEL25_INTSEL2 (*((volatile unsigned int*)(0x42A21808UL))) +#define bM4_INTC_SEL25_INTSEL3 (*((volatile unsigned int*)(0x42A2180CUL))) +#define bM4_INTC_SEL25_INTSEL4 (*((volatile unsigned int*)(0x42A21810UL))) +#define bM4_INTC_SEL25_INTSEL5 (*((volatile unsigned int*)(0x42A21814UL))) +#define bM4_INTC_SEL25_INTSEL6 (*((volatile unsigned int*)(0x42A21818UL))) +#define bM4_INTC_SEL25_INTSEL7 (*((volatile unsigned int*)(0x42A2181CUL))) +#define bM4_INTC_SEL25_INTSEL8 (*((volatile unsigned int*)(0x42A21820UL))) +#define bM4_INTC_SEL26_INTSEL0 (*((volatile unsigned int*)(0x42A21880UL))) +#define bM4_INTC_SEL26_INTSEL1 (*((volatile unsigned int*)(0x42A21884UL))) +#define bM4_INTC_SEL26_INTSEL2 (*((volatile unsigned int*)(0x42A21888UL))) +#define bM4_INTC_SEL26_INTSEL3 (*((volatile unsigned int*)(0x42A2188CUL))) +#define bM4_INTC_SEL26_INTSEL4 (*((volatile unsigned int*)(0x42A21890UL))) +#define bM4_INTC_SEL26_INTSEL5 (*((volatile unsigned int*)(0x42A21894UL))) +#define bM4_INTC_SEL26_INTSEL6 (*((volatile unsigned int*)(0x42A21898UL))) +#define bM4_INTC_SEL26_INTSEL7 (*((volatile unsigned int*)(0x42A2189CUL))) +#define bM4_INTC_SEL26_INTSEL8 (*((volatile unsigned int*)(0x42A218A0UL))) +#define bM4_INTC_SEL27_INTSEL0 (*((volatile unsigned int*)(0x42A21900UL))) +#define bM4_INTC_SEL27_INTSEL1 (*((volatile unsigned int*)(0x42A21904UL))) +#define bM4_INTC_SEL27_INTSEL2 (*((volatile unsigned int*)(0x42A21908UL))) +#define bM4_INTC_SEL27_INTSEL3 (*((volatile unsigned int*)(0x42A2190CUL))) +#define bM4_INTC_SEL27_INTSEL4 (*((volatile unsigned int*)(0x42A21910UL))) +#define bM4_INTC_SEL27_INTSEL5 (*((volatile unsigned int*)(0x42A21914UL))) +#define bM4_INTC_SEL27_INTSEL6 (*((volatile unsigned int*)(0x42A21918UL))) +#define bM4_INTC_SEL27_INTSEL7 (*((volatile unsigned int*)(0x42A2191CUL))) +#define bM4_INTC_SEL27_INTSEL8 (*((volatile unsigned int*)(0x42A21920UL))) +#define bM4_INTC_SEL28_INTSEL0 (*((volatile unsigned int*)(0x42A21980UL))) +#define bM4_INTC_SEL28_INTSEL1 (*((volatile unsigned int*)(0x42A21984UL))) +#define bM4_INTC_SEL28_INTSEL2 (*((volatile unsigned int*)(0x42A21988UL))) +#define bM4_INTC_SEL28_INTSEL3 (*((volatile unsigned int*)(0x42A2198CUL))) +#define bM4_INTC_SEL28_INTSEL4 (*((volatile unsigned int*)(0x42A21990UL))) +#define bM4_INTC_SEL28_INTSEL5 (*((volatile unsigned int*)(0x42A21994UL))) +#define bM4_INTC_SEL28_INTSEL6 (*((volatile unsigned int*)(0x42A21998UL))) +#define bM4_INTC_SEL28_INTSEL7 (*((volatile unsigned int*)(0x42A2199CUL))) +#define bM4_INTC_SEL28_INTSEL8 (*((volatile unsigned int*)(0x42A219A0UL))) +#define bM4_INTC_SEL29_INTSEL0 (*((volatile unsigned int*)(0x42A21A00UL))) +#define bM4_INTC_SEL29_INTSEL1 (*((volatile unsigned int*)(0x42A21A04UL))) +#define bM4_INTC_SEL29_INTSEL2 (*((volatile unsigned int*)(0x42A21A08UL))) +#define bM4_INTC_SEL29_INTSEL3 (*((volatile unsigned int*)(0x42A21A0CUL))) +#define bM4_INTC_SEL29_INTSEL4 (*((volatile unsigned int*)(0x42A21A10UL))) +#define bM4_INTC_SEL29_INTSEL5 (*((volatile unsigned int*)(0x42A21A14UL))) +#define bM4_INTC_SEL29_INTSEL6 (*((volatile unsigned int*)(0x42A21A18UL))) +#define bM4_INTC_SEL29_INTSEL7 (*((volatile unsigned int*)(0x42A21A1CUL))) +#define bM4_INTC_SEL29_INTSEL8 (*((volatile unsigned int*)(0x42A21A20UL))) +#define bM4_INTC_SEL30_INTSEL0 (*((volatile unsigned int*)(0x42A21A80UL))) +#define bM4_INTC_SEL30_INTSEL1 (*((volatile unsigned int*)(0x42A21A84UL))) +#define bM4_INTC_SEL30_INTSEL2 (*((volatile unsigned int*)(0x42A21A88UL))) +#define bM4_INTC_SEL30_INTSEL3 (*((volatile unsigned int*)(0x42A21A8CUL))) +#define bM4_INTC_SEL30_INTSEL4 (*((volatile unsigned int*)(0x42A21A90UL))) +#define bM4_INTC_SEL30_INTSEL5 (*((volatile unsigned int*)(0x42A21A94UL))) +#define bM4_INTC_SEL30_INTSEL6 (*((volatile unsigned int*)(0x42A21A98UL))) +#define bM4_INTC_SEL30_INTSEL7 (*((volatile unsigned int*)(0x42A21A9CUL))) +#define bM4_INTC_SEL30_INTSEL8 (*((volatile unsigned int*)(0x42A21AA0UL))) +#define bM4_INTC_SEL31_INTSEL0 (*((volatile unsigned int*)(0x42A21B00UL))) +#define bM4_INTC_SEL31_INTSEL1 (*((volatile unsigned int*)(0x42A21B04UL))) +#define bM4_INTC_SEL31_INTSEL2 (*((volatile unsigned int*)(0x42A21B08UL))) +#define bM4_INTC_SEL31_INTSEL3 (*((volatile unsigned int*)(0x42A21B0CUL))) +#define bM4_INTC_SEL31_INTSEL4 (*((volatile unsigned int*)(0x42A21B10UL))) +#define bM4_INTC_SEL31_INTSEL5 (*((volatile unsigned int*)(0x42A21B14UL))) +#define bM4_INTC_SEL31_INTSEL6 (*((volatile unsigned int*)(0x42A21B18UL))) +#define bM4_INTC_SEL31_INTSEL7 (*((volatile unsigned int*)(0x42A21B1CUL))) +#define bM4_INTC_SEL31_INTSEL8 (*((volatile unsigned int*)(0x42A21B20UL))) +#define bM4_INTC_SEL32_INTSEL0 (*((volatile unsigned int*)(0x42A21B80UL))) +#define bM4_INTC_SEL32_INTSEL1 (*((volatile unsigned int*)(0x42A21B84UL))) +#define bM4_INTC_SEL32_INTSEL2 (*((volatile unsigned int*)(0x42A21B88UL))) +#define bM4_INTC_SEL32_INTSEL3 (*((volatile unsigned int*)(0x42A21B8CUL))) +#define bM4_INTC_SEL32_INTSEL4 (*((volatile unsigned int*)(0x42A21B90UL))) +#define bM4_INTC_SEL32_INTSEL5 (*((volatile unsigned int*)(0x42A21B94UL))) +#define bM4_INTC_SEL32_INTSEL6 (*((volatile unsigned int*)(0x42A21B98UL))) +#define bM4_INTC_SEL32_INTSEL7 (*((volatile unsigned int*)(0x42A21B9CUL))) +#define bM4_INTC_SEL32_INTSEL8 (*((volatile unsigned int*)(0x42A21BA0UL))) +#define bM4_INTC_SEL33_INTSEL0 (*((volatile unsigned int*)(0x42A21C00UL))) +#define bM4_INTC_SEL33_INTSEL1 (*((volatile unsigned int*)(0x42A21C04UL))) +#define bM4_INTC_SEL33_INTSEL2 (*((volatile unsigned int*)(0x42A21C08UL))) +#define bM4_INTC_SEL33_INTSEL3 (*((volatile unsigned int*)(0x42A21C0CUL))) +#define bM4_INTC_SEL33_INTSEL4 (*((volatile unsigned int*)(0x42A21C10UL))) +#define bM4_INTC_SEL33_INTSEL5 (*((volatile unsigned int*)(0x42A21C14UL))) +#define bM4_INTC_SEL33_INTSEL6 (*((volatile unsigned int*)(0x42A21C18UL))) +#define bM4_INTC_SEL33_INTSEL7 (*((volatile unsigned int*)(0x42A21C1CUL))) +#define bM4_INTC_SEL33_INTSEL8 (*((volatile unsigned int*)(0x42A21C20UL))) +#define bM4_INTC_SEL34_INTSEL0 (*((volatile unsigned int*)(0x42A21C80UL))) +#define bM4_INTC_SEL34_INTSEL1 (*((volatile unsigned int*)(0x42A21C84UL))) +#define bM4_INTC_SEL34_INTSEL2 (*((volatile unsigned int*)(0x42A21C88UL))) +#define bM4_INTC_SEL34_INTSEL3 (*((volatile unsigned int*)(0x42A21C8CUL))) +#define bM4_INTC_SEL34_INTSEL4 (*((volatile unsigned int*)(0x42A21C90UL))) +#define bM4_INTC_SEL34_INTSEL5 (*((volatile unsigned int*)(0x42A21C94UL))) +#define bM4_INTC_SEL34_INTSEL6 (*((volatile unsigned int*)(0x42A21C98UL))) +#define bM4_INTC_SEL34_INTSEL7 (*((volatile unsigned int*)(0x42A21C9CUL))) +#define bM4_INTC_SEL34_INTSEL8 (*((volatile unsigned int*)(0x42A21CA0UL))) +#define bM4_INTC_SEL35_INTSEL0 (*((volatile unsigned int*)(0x42A21D00UL))) +#define bM4_INTC_SEL35_INTSEL1 (*((volatile unsigned int*)(0x42A21D04UL))) +#define bM4_INTC_SEL35_INTSEL2 (*((volatile unsigned int*)(0x42A21D08UL))) +#define bM4_INTC_SEL35_INTSEL3 (*((volatile unsigned int*)(0x42A21D0CUL))) +#define bM4_INTC_SEL35_INTSEL4 (*((volatile unsigned int*)(0x42A21D10UL))) +#define bM4_INTC_SEL35_INTSEL5 (*((volatile unsigned int*)(0x42A21D14UL))) +#define bM4_INTC_SEL35_INTSEL6 (*((volatile unsigned int*)(0x42A21D18UL))) +#define bM4_INTC_SEL35_INTSEL7 (*((volatile unsigned int*)(0x42A21D1CUL))) +#define bM4_INTC_SEL35_INTSEL8 (*((volatile unsigned int*)(0x42A21D20UL))) +#define bM4_INTC_SEL36_INTSEL0 (*((volatile unsigned int*)(0x42A21D80UL))) +#define bM4_INTC_SEL36_INTSEL1 (*((volatile unsigned int*)(0x42A21D84UL))) +#define bM4_INTC_SEL36_INTSEL2 (*((volatile unsigned int*)(0x42A21D88UL))) +#define bM4_INTC_SEL36_INTSEL3 (*((volatile unsigned int*)(0x42A21D8CUL))) +#define bM4_INTC_SEL36_INTSEL4 (*((volatile unsigned int*)(0x42A21D90UL))) +#define bM4_INTC_SEL36_INTSEL5 (*((volatile unsigned int*)(0x42A21D94UL))) +#define bM4_INTC_SEL36_INTSEL6 (*((volatile unsigned int*)(0x42A21D98UL))) +#define bM4_INTC_SEL36_INTSEL7 (*((volatile unsigned int*)(0x42A21D9CUL))) +#define bM4_INTC_SEL36_INTSEL8 (*((volatile unsigned int*)(0x42A21DA0UL))) +#define bM4_INTC_SEL37_INTSEL0 (*((volatile unsigned int*)(0x42A21E00UL))) +#define bM4_INTC_SEL37_INTSEL1 (*((volatile unsigned int*)(0x42A21E04UL))) +#define bM4_INTC_SEL37_INTSEL2 (*((volatile unsigned int*)(0x42A21E08UL))) +#define bM4_INTC_SEL37_INTSEL3 (*((volatile unsigned int*)(0x42A21E0CUL))) +#define bM4_INTC_SEL37_INTSEL4 (*((volatile unsigned int*)(0x42A21E10UL))) +#define bM4_INTC_SEL37_INTSEL5 (*((volatile unsigned int*)(0x42A21E14UL))) +#define bM4_INTC_SEL37_INTSEL6 (*((volatile unsigned int*)(0x42A21E18UL))) +#define bM4_INTC_SEL37_INTSEL7 (*((volatile unsigned int*)(0x42A21E1CUL))) +#define bM4_INTC_SEL37_INTSEL8 (*((volatile unsigned int*)(0x42A21E20UL))) +#define bM4_INTC_SEL38_INTSEL0 (*((volatile unsigned int*)(0x42A21E80UL))) +#define bM4_INTC_SEL38_INTSEL1 (*((volatile unsigned int*)(0x42A21E84UL))) +#define bM4_INTC_SEL38_INTSEL2 (*((volatile unsigned int*)(0x42A21E88UL))) +#define bM4_INTC_SEL38_INTSEL3 (*((volatile unsigned int*)(0x42A21E8CUL))) +#define bM4_INTC_SEL38_INTSEL4 (*((volatile unsigned int*)(0x42A21E90UL))) +#define bM4_INTC_SEL38_INTSEL5 (*((volatile unsigned int*)(0x42A21E94UL))) +#define bM4_INTC_SEL38_INTSEL6 (*((volatile unsigned int*)(0x42A21E98UL))) +#define bM4_INTC_SEL38_INTSEL7 (*((volatile unsigned int*)(0x42A21E9CUL))) +#define bM4_INTC_SEL38_INTSEL8 (*((volatile unsigned int*)(0x42A21EA0UL))) +#define bM4_INTC_SEL39_INTSEL0 (*((volatile unsigned int*)(0x42A21F00UL))) +#define bM4_INTC_SEL39_INTSEL1 (*((volatile unsigned int*)(0x42A21F04UL))) +#define bM4_INTC_SEL39_INTSEL2 (*((volatile unsigned int*)(0x42A21F08UL))) +#define bM4_INTC_SEL39_INTSEL3 (*((volatile unsigned int*)(0x42A21F0CUL))) +#define bM4_INTC_SEL39_INTSEL4 (*((volatile unsigned int*)(0x42A21F10UL))) +#define bM4_INTC_SEL39_INTSEL5 (*((volatile unsigned int*)(0x42A21F14UL))) +#define bM4_INTC_SEL39_INTSEL6 (*((volatile unsigned int*)(0x42A21F18UL))) +#define bM4_INTC_SEL39_INTSEL7 (*((volatile unsigned int*)(0x42A21F1CUL))) +#define bM4_INTC_SEL39_INTSEL8 (*((volatile unsigned int*)(0x42A21F20UL))) +#define bM4_INTC_SEL40_INTSEL0 (*((volatile unsigned int*)(0x42A21F80UL))) +#define bM4_INTC_SEL40_INTSEL1 (*((volatile unsigned int*)(0x42A21F84UL))) +#define bM4_INTC_SEL40_INTSEL2 (*((volatile unsigned int*)(0x42A21F88UL))) +#define bM4_INTC_SEL40_INTSEL3 (*((volatile unsigned int*)(0x42A21F8CUL))) +#define bM4_INTC_SEL40_INTSEL4 (*((volatile unsigned int*)(0x42A21F90UL))) +#define bM4_INTC_SEL40_INTSEL5 (*((volatile unsigned int*)(0x42A21F94UL))) +#define bM4_INTC_SEL40_INTSEL6 (*((volatile unsigned int*)(0x42A21F98UL))) +#define bM4_INTC_SEL40_INTSEL7 (*((volatile unsigned int*)(0x42A21F9CUL))) +#define bM4_INTC_SEL40_INTSEL8 (*((volatile unsigned int*)(0x42A21FA0UL))) +#define bM4_INTC_SEL41_INTSEL0 (*((volatile unsigned int*)(0x42A22000UL))) +#define bM4_INTC_SEL41_INTSEL1 (*((volatile unsigned int*)(0x42A22004UL))) +#define bM4_INTC_SEL41_INTSEL2 (*((volatile unsigned int*)(0x42A22008UL))) +#define bM4_INTC_SEL41_INTSEL3 (*((volatile unsigned int*)(0x42A2200CUL))) +#define bM4_INTC_SEL41_INTSEL4 (*((volatile unsigned int*)(0x42A22010UL))) +#define bM4_INTC_SEL41_INTSEL5 (*((volatile unsigned int*)(0x42A22014UL))) +#define bM4_INTC_SEL41_INTSEL6 (*((volatile unsigned int*)(0x42A22018UL))) +#define bM4_INTC_SEL41_INTSEL7 (*((volatile unsigned int*)(0x42A2201CUL))) +#define bM4_INTC_SEL41_INTSEL8 (*((volatile unsigned int*)(0x42A22020UL))) +#define bM4_INTC_SEL42_INTSEL0 (*((volatile unsigned int*)(0x42A22080UL))) +#define bM4_INTC_SEL42_INTSEL1 (*((volatile unsigned int*)(0x42A22084UL))) +#define bM4_INTC_SEL42_INTSEL2 (*((volatile unsigned int*)(0x42A22088UL))) +#define bM4_INTC_SEL42_INTSEL3 (*((volatile unsigned int*)(0x42A2208CUL))) +#define bM4_INTC_SEL42_INTSEL4 (*((volatile unsigned int*)(0x42A22090UL))) +#define bM4_INTC_SEL42_INTSEL5 (*((volatile unsigned int*)(0x42A22094UL))) +#define bM4_INTC_SEL42_INTSEL6 (*((volatile unsigned int*)(0x42A22098UL))) +#define bM4_INTC_SEL42_INTSEL7 (*((volatile unsigned int*)(0x42A2209CUL))) +#define bM4_INTC_SEL42_INTSEL8 (*((volatile unsigned int*)(0x42A220A0UL))) +#define bM4_INTC_SEL43_INTSEL0 (*((volatile unsigned int*)(0x42A22100UL))) +#define bM4_INTC_SEL43_INTSEL1 (*((volatile unsigned int*)(0x42A22104UL))) +#define bM4_INTC_SEL43_INTSEL2 (*((volatile unsigned int*)(0x42A22108UL))) +#define bM4_INTC_SEL43_INTSEL3 (*((volatile unsigned int*)(0x42A2210CUL))) +#define bM4_INTC_SEL43_INTSEL4 (*((volatile unsigned int*)(0x42A22110UL))) +#define bM4_INTC_SEL43_INTSEL5 (*((volatile unsigned int*)(0x42A22114UL))) +#define bM4_INTC_SEL43_INTSEL6 (*((volatile unsigned int*)(0x42A22118UL))) +#define bM4_INTC_SEL43_INTSEL7 (*((volatile unsigned int*)(0x42A2211CUL))) +#define bM4_INTC_SEL43_INTSEL8 (*((volatile unsigned int*)(0x42A22120UL))) +#define bM4_INTC_SEL44_INTSEL0 (*((volatile unsigned int*)(0x42A22180UL))) +#define bM4_INTC_SEL44_INTSEL1 (*((volatile unsigned int*)(0x42A22184UL))) +#define bM4_INTC_SEL44_INTSEL2 (*((volatile unsigned int*)(0x42A22188UL))) +#define bM4_INTC_SEL44_INTSEL3 (*((volatile unsigned int*)(0x42A2218CUL))) +#define bM4_INTC_SEL44_INTSEL4 (*((volatile unsigned int*)(0x42A22190UL))) +#define bM4_INTC_SEL44_INTSEL5 (*((volatile unsigned int*)(0x42A22194UL))) +#define bM4_INTC_SEL44_INTSEL6 (*((volatile unsigned int*)(0x42A22198UL))) +#define bM4_INTC_SEL44_INTSEL7 (*((volatile unsigned int*)(0x42A2219CUL))) +#define bM4_INTC_SEL44_INTSEL8 (*((volatile unsigned int*)(0x42A221A0UL))) +#define bM4_INTC_SEL45_INTSEL0 (*((volatile unsigned int*)(0x42A22200UL))) +#define bM4_INTC_SEL45_INTSEL1 (*((volatile unsigned int*)(0x42A22204UL))) +#define bM4_INTC_SEL45_INTSEL2 (*((volatile unsigned int*)(0x42A22208UL))) +#define bM4_INTC_SEL45_INTSEL3 (*((volatile unsigned int*)(0x42A2220CUL))) +#define bM4_INTC_SEL45_INTSEL4 (*((volatile unsigned int*)(0x42A22210UL))) +#define bM4_INTC_SEL45_INTSEL5 (*((volatile unsigned int*)(0x42A22214UL))) +#define bM4_INTC_SEL45_INTSEL6 (*((volatile unsigned int*)(0x42A22218UL))) +#define bM4_INTC_SEL45_INTSEL7 (*((volatile unsigned int*)(0x42A2221CUL))) +#define bM4_INTC_SEL45_INTSEL8 (*((volatile unsigned int*)(0x42A22220UL))) +#define bM4_INTC_SEL46_INTSEL0 (*((volatile unsigned int*)(0x42A22280UL))) +#define bM4_INTC_SEL46_INTSEL1 (*((volatile unsigned int*)(0x42A22284UL))) +#define bM4_INTC_SEL46_INTSEL2 (*((volatile unsigned int*)(0x42A22288UL))) +#define bM4_INTC_SEL46_INTSEL3 (*((volatile unsigned int*)(0x42A2228CUL))) +#define bM4_INTC_SEL46_INTSEL4 (*((volatile unsigned int*)(0x42A22290UL))) +#define bM4_INTC_SEL46_INTSEL5 (*((volatile unsigned int*)(0x42A22294UL))) +#define bM4_INTC_SEL46_INTSEL6 (*((volatile unsigned int*)(0x42A22298UL))) +#define bM4_INTC_SEL46_INTSEL7 (*((volatile unsigned int*)(0x42A2229CUL))) +#define bM4_INTC_SEL46_INTSEL8 (*((volatile unsigned int*)(0x42A222A0UL))) +#define bM4_INTC_SEL47_INTSEL0 (*((volatile unsigned int*)(0x42A22300UL))) +#define bM4_INTC_SEL47_INTSEL1 (*((volatile unsigned int*)(0x42A22304UL))) +#define bM4_INTC_SEL47_INTSEL2 (*((volatile unsigned int*)(0x42A22308UL))) +#define bM4_INTC_SEL47_INTSEL3 (*((volatile unsigned int*)(0x42A2230CUL))) +#define bM4_INTC_SEL47_INTSEL4 (*((volatile unsigned int*)(0x42A22310UL))) +#define bM4_INTC_SEL47_INTSEL5 (*((volatile unsigned int*)(0x42A22314UL))) +#define bM4_INTC_SEL47_INTSEL6 (*((volatile unsigned int*)(0x42A22318UL))) +#define bM4_INTC_SEL47_INTSEL7 (*((volatile unsigned int*)(0x42A2231CUL))) +#define bM4_INTC_SEL47_INTSEL8 (*((volatile unsigned int*)(0x42A22320UL))) +#define bM4_INTC_SEL48_INTSEL0 (*((volatile unsigned int*)(0x42A22380UL))) +#define bM4_INTC_SEL48_INTSEL1 (*((volatile unsigned int*)(0x42A22384UL))) +#define bM4_INTC_SEL48_INTSEL2 (*((volatile unsigned int*)(0x42A22388UL))) +#define bM4_INTC_SEL48_INTSEL3 (*((volatile unsigned int*)(0x42A2238CUL))) +#define bM4_INTC_SEL48_INTSEL4 (*((volatile unsigned int*)(0x42A22390UL))) +#define bM4_INTC_SEL48_INTSEL5 (*((volatile unsigned int*)(0x42A22394UL))) +#define bM4_INTC_SEL48_INTSEL6 (*((volatile unsigned int*)(0x42A22398UL))) +#define bM4_INTC_SEL48_INTSEL7 (*((volatile unsigned int*)(0x42A2239CUL))) +#define bM4_INTC_SEL48_INTSEL8 (*((volatile unsigned int*)(0x42A223A0UL))) +#define bM4_INTC_SEL49_INTSEL0 (*((volatile unsigned int*)(0x42A22400UL))) +#define bM4_INTC_SEL49_INTSEL1 (*((volatile unsigned int*)(0x42A22404UL))) +#define bM4_INTC_SEL49_INTSEL2 (*((volatile unsigned int*)(0x42A22408UL))) +#define bM4_INTC_SEL49_INTSEL3 (*((volatile unsigned int*)(0x42A2240CUL))) +#define bM4_INTC_SEL49_INTSEL4 (*((volatile unsigned int*)(0x42A22410UL))) +#define bM4_INTC_SEL49_INTSEL5 (*((volatile unsigned int*)(0x42A22414UL))) +#define bM4_INTC_SEL49_INTSEL6 (*((volatile unsigned int*)(0x42A22418UL))) +#define bM4_INTC_SEL49_INTSEL7 (*((volatile unsigned int*)(0x42A2241CUL))) +#define bM4_INTC_SEL49_INTSEL8 (*((volatile unsigned int*)(0x42A22420UL))) +#define bM4_INTC_SEL50_INTSEL0 (*((volatile unsigned int*)(0x42A22480UL))) +#define bM4_INTC_SEL50_INTSEL1 (*((volatile unsigned int*)(0x42A22484UL))) +#define bM4_INTC_SEL50_INTSEL2 (*((volatile unsigned int*)(0x42A22488UL))) +#define bM4_INTC_SEL50_INTSEL3 (*((volatile unsigned int*)(0x42A2248CUL))) +#define bM4_INTC_SEL50_INTSEL4 (*((volatile unsigned int*)(0x42A22490UL))) +#define bM4_INTC_SEL50_INTSEL5 (*((volatile unsigned int*)(0x42A22494UL))) +#define bM4_INTC_SEL50_INTSEL6 (*((volatile unsigned int*)(0x42A22498UL))) +#define bM4_INTC_SEL50_INTSEL7 (*((volatile unsigned int*)(0x42A2249CUL))) +#define bM4_INTC_SEL50_INTSEL8 (*((volatile unsigned int*)(0x42A224A0UL))) +#define bM4_INTC_SEL51_INTSEL0 (*((volatile unsigned int*)(0x42A22500UL))) +#define bM4_INTC_SEL51_INTSEL1 (*((volatile unsigned int*)(0x42A22504UL))) +#define bM4_INTC_SEL51_INTSEL2 (*((volatile unsigned int*)(0x42A22508UL))) +#define bM4_INTC_SEL51_INTSEL3 (*((volatile unsigned int*)(0x42A2250CUL))) +#define bM4_INTC_SEL51_INTSEL4 (*((volatile unsigned int*)(0x42A22510UL))) +#define bM4_INTC_SEL51_INTSEL5 (*((volatile unsigned int*)(0x42A22514UL))) +#define bM4_INTC_SEL51_INTSEL6 (*((volatile unsigned int*)(0x42A22518UL))) +#define bM4_INTC_SEL51_INTSEL7 (*((volatile unsigned int*)(0x42A2251CUL))) +#define bM4_INTC_SEL51_INTSEL8 (*((volatile unsigned int*)(0x42A22520UL))) +#define bM4_INTC_SEL52_INTSEL0 (*((volatile unsigned int*)(0x42A22580UL))) +#define bM4_INTC_SEL52_INTSEL1 (*((volatile unsigned int*)(0x42A22584UL))) +#define bM4_INTC_SEL52_INTSEL2 (*((volatile unsigned int*)(0x42A22588UL))) +#define bM4_INTC_SEL52_INTSEL3 (*((volatile unsigned int*)(0x42A2258CUL))) +#define bM4_INTC_SEL52_INTSEL4 (*((volatile unsigned int*)(0x42A22590UL))) +#define bM4_INTC_SEL52_INTSEL5 (*((volatile unsigned int*)(0x42A22594UL))) +#define bM4_INTC_SEL52_INTSEL6 (*((volatile unsigned int*)(0x42A22598UL))) +#define bM4_INTC_SEL52_INTSEL7 (*((volatile unsigned int*)(0x42A2259CUL))) +#define bM4_INTC_SEL52_INTSEL8 (*((volatile unsigned int*)(0x42A225A0UL))) +#define bM4_INTC_SEL53_INTSEL0 (*((volatile unsigned int*)(0x42A22600UL))) +#define bM4_INTC_SEL53_INTSEL1 (*((volatile unsigned int*)(0x42A22604UL))) +#define bM4_INTC_SEL53_INTSEL2 (*((volatile unsigned int*)(0x42A22608UL))) +#define bM4_INTC_SEL53_INTSEL3 (*((volatile unsigned int*)(0x42A2260CUL))) +#define bM4_INTC_SEL53_INTSEL4 (*((volatile unsigned int*)(0x42A22610UL))) +#define bM4_INTC_SEL53_INTSEL5 (*((volatile unsigned int*)(0x42A22614UL))) +#define bM4_INTC_SEL53_INTSEL6 (*((volatile unsigned int*)(0x42A22618UL))) +#define bM4_INTC_SEL53_INTSEL7 (*((volatile unsigned int*)(0x42A2261CUL))) +#define bM4_INTC_SEL53_INTSEL8 (*((volatile unsigned int*)(0x42A22620UL))) +#define bM4_INTC_SEL54_INTSEL0 (*((volatile unsigned int*)(0x42A22680UL))) +#define bM4_INTC_SEL54_INTSEL1 (*((volatile unsigned int*)(0x42A22684UL))) +#define bM4_INTC_SEL54_INTSEL2 (*((volatile unsigned int*)(0x42A22688UL))) +#define bM4_INTC_SEL54_INTSEL3 (*((volatile unsigned int*)(0x42A2268CUL))) +#define bM4_INTC_SEL54_INTSEL4 (*((volatile unsigned int*)(0x42A22690UL))) +#define bM4_INTC_SEL54_INTSEL5 (*((volatile unsigned int*)(0x42A22694UL))) +#define bM4_INTC_SEL54_INTSEL6 (*((volatile unsigned int*)(0x42A22698UL))) +#define bM4_INTC_SEL54_INTSEL7 (*((volatile unsigned int*)(0x42A2269CUL))) +#define bM4_INTC_SEL54_INTSEL8 (*((volatile unsigned int*)(0x42A226A0UL))) +#define bM4_INTC_SEL55_INTSEL0 (*((volatile unsigned int*)(0x42A22700UL))) +#define bM4_INTC_SEL55_INTSEL1 (*((volatile unsigned int*)(0x42A22704UL))) +#define bM4_INTC_SEL55_INTSEL2 (*((volatile unsigned int*)(0x42A22708UL))) +#define bM4_INTC_SEL55_INTSEL3 (*((volatile unsigned int*)(0x42A2270CUL))) +#define bM4_INTC_SEL55_INTSEL4 (*((volatile unsigned int*)(0x42A22710UL))) +#define bM4_INTC_SEL55_INTSEL5 (*((volatile unsigned int*)(0x42A22714UL))) +#define bM4_INTC_SEL55_INTSEL6 (*((volatile unsigned int*)(0x42A22718UL))) +#define bM4_INTC_SEL55_INTSEL7 (*((volatile unsigned int*)(0x42A2271CUL))) +#define bM4_INTC_SEL55_INTSEL8 (*((volatile unsigned int*)(0x42A22720UL))) +#define bM4_INTC_SEL56_INTSEL0 (*((volatile unsigned int*)(0x42A22780UL))) +#define bM4_INTC_SEL56_INTSEL1 (*((volatile unsigned int*)(0x42A22784UL))) +#define bM4_INTC_SEL56_INTSEL2 (*((volatile unsigned int*)(0x42A22788UL))) +#define bM4_INTC_SEL56_INTSEL3 (*((volatile unsigned int*)(0x42A2278CUL))) +#define bM4_INTC_SEL56_INTSEL4 (*((volatile unsigned int*)(0x42A22790UL))) +#define bM4_INTC_SEL56_INTSEL5 (*((volatile unsigned int*)(0x42A22794UL))) +#define bM4_INTC_SEL56_INTSEL6 (*((volatile unsigned int*)(0x42A22798UL))) +#define bM4_INTC_SEL56_INTSEL7 (*((volatile unsigned int*)(0x42A2279CUL))) +#define bM4_INTC_SEL56_INTSEL8 (*((volatile unsigned int*)(0x42A227A0UL))) +#define bM4_INTC_SEL57_INTSEL0 (*((volatile unsigned int*)(0x42A22800UL))) +#define bM4_INTC_SEL57_INTSEL1 (*((volatile unsigned int*)(0x42A22804UL))) +#define bM4_INTC_SEL57_INTSEL2 (*((volatile unsigned int*)(0x42A22808UL))) +#define bM4_INTC_SEL57_INTSEL3 (*((volatile unsigned int*)(0x42A2280CUL))) +#define bM4_INTC_SEL57_INTSEL4 (*((volatile unsigned int*)(0x42A22810UL))) +#define bM4_INTC_SEL57_INTSEL5 (*((volatile unsigned int*)(0x42A22814UL))) +#define bM4_INTC_SEL57_INTSEL6 (*((volatile unsigned int*)(0x42A22818UL))) +#define bM4_INTC_SEL57_INTSEL7 (*((volatile unsigned int*)(0x42A2281CUL))) +#define bM4_INTC_SEL57_INTSEL8 (*((volatile unsigned int*)(0x42A22820UL))) +#define bM4_INTC_SEL58_INTSEL0 (*((volatile unsigned int*)(0x42A22880UL))) +#define bM4_INTC_SEL58_INTSEL1 (*((volatile unsigned int*)(0x42A22884UL))) +#define bM4_INTC_SEL58_INTSEL2 (*((volatile unsigned int*)(0x42A22888UL))) +#define bM4_INTC_SEL58_INTSEL3 (*((volatile unsigned int*)(0x42A2288CUL))) +#define bM4_INTC_SEL58_INTSEL4 (*((volatile unsigned int*)(0x42A22890UL))) +#define bM4_INTC_SEL58_INTSEL5 (*((volatile unsigned int*)(0x42A22894UL))) +#define bM4_INTC_SEL58_INTSEL6 (*((volatile unsigned int*)(0x42A22898UL))) +#define bM4_INTC_SEL58_INTSEL7 (*((volatile unsigned int*)(0x42A2289CUL))) +#define bM4_INTC_SEL58_INTSEL8 (*((volatile unsigned int*)(0x42A228A0UL))) +#define bM4_INTC_SEL59_INTSEL0 (*((volatile unsigned int*)(0x42A22900UL))) +#define bM4_INTC_SEL59_INTSEL1 (*((volatile unsigned int*)(0x42A22904UL))) +#define bM4_INTC_SEL59_INTSEL2 (*((volatile unsigned int*)(0x42A22908UL))) +#define bM4_INTC_SEL59_INTSEL3 (*((volatile unsigned int*)(0x42A2290CUL))) +#define bM4_INTC_SEL59_INTSEL4 (*((volatile unsigned int*)(0x42A22910UL))) +#define bM4_INTC_SEL59_INTSEL5 (*((volatile unsigned int*)(0x42A22914UL))) +#define bM4_INTC_SEL59_INTSEL6 (*((volatile unsigned int*)(0x42A22918UL))) +#define bM4_INTC_SEL59_INTSEL7 (*((volatile unsigned int*)(0x42A2291CUL))) +#define bM4_INTC_SEL59_INTSEL8 (*((volatile unsigned int*)(0x42A22920UL))) +#define bM4_INTC_SEL60_INTSEL0 (*((volatile unsigned int*)(0x42A22980UL))) +#define bM4_INTC_SEL60_INTSEL1 (*((volatile unsigned int*)(0x42A22984UL))) +#define bM4_INTC_SEL60_INTSEL2 (*((volatile unsigned int*)(0x42A22988UL))) +#define bM4_INTC_SEL60_INTSEL3 (*((volatile unsigned int*)(0x42A2298CUL))) +#define bM4_INTC_SEL60_INTSEL4 (*((volatile unsigned int*)(0x42A22990UL))) +#define bM4_INTC_SEL60_INTSEL5 (*((volatile unsigned int*)(0x42A22994UL))) +#define bM4_INTC_SEL60_INTSEL6 (*((volatile unsigned int*)(0x42A22998UL))) +#define bM4_INTC_SEL60_INTSEL7 (*((volatile unsigned int*)(0x42A2299CUL))) +#define bM4_INTC_SEL60_INTSEL8 (*((volatile unsigned int*)(0x42A229A0UL))) +#define bM4_INTC_SEL61_INTSEL0 (*((volatile unsigned int*)(0x42A22A00UL))) +#define bM4_INTC_SEL61_INTSEL1 (*((volatile unsigned int*)(0x42A22A04UL))) +#define bM4_INTC_SEL61_INTSEL2 (*((volatile unsigned int*)(0x42A22A08UL))) +#define bM4_INTC_SEL61_INTSEL3 (*((volatile unsigned int*)(0x42A22A0CUL))) +#define bM4_INTC_SEL61_INTSEL4 (*((volatile unsigned int*)(0x42A22A10UL))) +#define bM4_INTC_SEL61_INTSEL5 (*((volatile unsigned int*)(0x42A22A14UL))) +#define bM4_INTC_SEL61_INTSEL6 (*((volatile unsigned int*)(0x42A22A18UL))) +#define bM4_INTC_SEL61_INTSEL7 (*((volatile unsigned int*)(0x42A22A1CUL))) +#define bM4_INTC_SEL61_INTSEL8 (*((volatile unsigned int*)(0x42A22A20UL))) +#define bM4_INTC_SEL62_INTSEL0 (*((volatile unsigned int*)(0x42A22A80UL))) +#define bM4_INTC_SEL62_INTSEL1 (*((volatile unsigned int*)(0x42A22A84UL))) +#define bM4_INTC_SEL62_INTSEL2 (*((volatile unsigned int*)(0x42A22A88UL))) +#define bM4_INTC_SEL62_INTSEL3 (*((volatile unsigned int*)(0x42A22A8CUL))) +#define bM4_INTC_SEL62_INTSEL4 (*((volatile unsigned int*)(0x42A22A90UL))) +#define bM4_INTC_SEL62_INTSEL5 (*((volatile unsigned int*)(0x42A22A94UL))) +#define bM4_INTC_SEL62_INTSEL6 (*((volatile unsigned int*)(0x42A22A98UL))) +#define bM4_INTC_SEL62_INTSEL7 (*((volatile unsigned int*)(0x42A22A9CUL))) +#define bM4_INTC_SEL62_INTSEL8 (*((volatile unsigned int*)(0x42A22AA0UL))) +#define bM4_INTC_SEL63_INTSEL0 (*((volatile unsigned int*)(0x42A22B00UL))) +#define bM4_INTC_SEL63_INTSEL1 (*((volatile unsigned int*)(0x42A22B04UL))) +#define bM4_INTC_SEL63_INTSEL2 (*((volatile unsigned int*)(0x42A22B08UL))) +#define bM4_INTC_SEL63_INTSEL3 (*((volatile unsigned int*)(0x42A22B0CUL))) +#define bM4_INTC_SEL63_INTSEL4 (*((volatile unsigned int*)(0x42A22B10UL))) +#define bM4_INTC_SEL63_INTSEL5 (*((volatile unsigned int*)(0x42A22B14UL))) +#define bM4_INTC_SEL63_INTSEL6 (*((volatile unsigned int*)(0x42A22B18UL))) +#define bM4_INTC_SEL63_INTSEL7 (*((volatile unsigned int*)(0x42A22B1CUL))) +#define bM4_INTC_SEL63_INTSEL8 (*((volatile unsigned int*)(0x42A22B20UL))) +#define bM4_INTC_SEL64_INTSEL0 (*((volatile unsigned int*)(0x42A22B80UL))) +#define bM4_INTC_SEL64_INTSEL1 (*((volatile unsigned int*)(0x42A22B84UL))) +#define bM4_INTC_SEL64_INTSEL2 (*((volatile unsigned int*)(0x42A22B88UL))) +#define bM4_INTC_SEL64_INTSEL3 (*((volatile unsigned int*)(0x42A22B8CUL))) +#define bM4_INTC_SEL64_INTSEL4 (*((volatile unsigned int*)(0x42A22B90UL))) +#define bM4_INTC_SEL64_INTSEL5 (*((volatile unsigned int*)(0x42A22B94UL))) +#define bM4_INTC_SEL64_INTSEL6 (*((volatile unsigned int*)(0x42A22B98UL))) +#define bM4_INTC_SEL64_INTSEL7 (*((volatile unsigned int*)(0x42A22B9CUL))) +#define bM4_INTC_SEL64_INTSEL8 (*((volatile unsigned int*)(0x42A22BA0UL))) +#define bM4_INTC_SEL65_INTSEL0 (*((volatile unsigned int*)(0x42A22C00UL))) +#define bM4_INTC_SEL65_INTSEL1 (*((volatile unsigned int*)(0x42A22C04UL))) +#define bM4_INTC_SEL65_INTSEL2 (*((volatile unsigned int*)(0x42A22C08UL))) +#define bM4_INTC_SEL65_INTSEL3 (*((volatile unsigned int*)(0x42A22C0CUL))) +#define bM4_INTC_SEL65_INTSEL4 (*((volatile unsigned int*)(0x42A22C10UL))) +#define bM4_INTC_SEL65_INTSEL5 (*((volatile unsigned int*)(0x42A22C14UL))) +#define bM4_INTC_SEL65_INTSEL6 (*((volatile unsigned int*)(0x42A22C18UL))) +#define bM4_INTC_SEL65_INTSEL7 (*((volatile unsigned int*)(0x42A22C1CUL))) +#define bM4_INTC_SEL65_INTSEL8 (*((volatile unsigned int*)(0x42A22C20UL))) +#define bM4_INTC_SEL66_INTSEL0 (*((volatile unsigned int*)(0x42A22C80UL))) +#define bM4_INTC_SEL66_INTSEL1 (*((volatile unsigned int*)(0x42A22C84UL))) +#define bM4_INTC_SEL66_INTSEL2 (*((volatile unsigned int*)(0x42A22C88UL))) +#define bM4_INTC_SEL66_INTSEL3 (*((volatile unsigned int*)(0x42A22C8CUL))) +#define bM4_INTC_SEL66_INTSEL4 (*((volatile unsigned int*)(0x42A22C90UL))) +#define bM4_INTC_SEL66_INTSEL5 (*((volatile unsigned int*)(0x42A22C94UL))) +#define bM4_INTC_SEL66_INTSEL6 (*((volatile unsigned int*)(0x42A22C98UL))) +#define bM4_INTC_SEL66_INTSEL7 (*((volatile unsigned int*)(0x42A22C9CUL))) +#define bM4_INTC_SEL66_INTSEL8 (*((volatile unsigned int*)(0x42A22CA0UL))) +#define bM4_INTC_SEL67_INTSEL0 (*((volatile unsigned int*)(0x42A22D00UL))) +#define bM4_INTC_SEL67_INTSEL1 (*((volatile unsigned int*)(0x42A22D04UL))) +#define bM4_INTC_SEL67_INTSEL2 (*((volatile unsigned int*)(0x42A22D08UL))) +#define bM4_INTC_SEL67_INTSEL3 (*((volatile unsigned int*)(0x42A22D0CUL))) +#define bM4_INTC_SEL67_INTSEL4 (*((volatile unsigned int*)(0x42A22D10UL))) +#define bM4_INTC_SEL67_INTSEL5 (*((volatile unsigned int*)(0x42A22D14UL))) +#define bM4_INTC_SEL67_INTSEL6 (*((volatile unsigned int*)(0x42A22D18UL))) +#define bM4_INTC_SEL67_INTSEL7 (*((volatile unsigned int*)(0x42A22D1CUL))) +#define bM4_INTC_SEL67_INTSEL8 (*((volatile unsigned int*)(0x42A22D20UL))) +#define bM4_INTC_SEL68_INTSEL0 (*((volatile unsigned int*)(0x42A22D80UL))) +#define bM4_INTC_SEL68_INTSEL1 (*((volatile unsigned int*)(0x42A22D84UL))) +#define bM4_INTC_SEL68_INTSEL2 (*((volatile unsigned int*)(0x42A22D88UL))) +#define bM4_INTC_SEL68_INTSEL3 (*((volatile unsigned int*)(0x42A22D8CUL))) +#define bM4_INTC_SEL68_INTSEL4 (*((volatile unsigned int*)(0x42A22D90UL))) +#define bM4_INTC_SEL68_INTSEL5 (*((volatile unsigned int*)(0x42A22D94UL))) +#define bM4_INTC_SEL68_INTSEL6 (*((volatile unsigned int*)(0x42A22D98UL))) +#define bM4_INTC_SEL68_INTSEL7 (*((volatile unsigned int*)(0x42A22D9CUL))) +#define bM4_INTC_SEL68_INTSEL8 (*((volatile unsigned int*)(0x42A22DA0UL))) +#define bM4_INTC_SEL69_INTSEL0 (*((volatile unsigned int*)(0x42A22E00UL))) +#define bM4_INTC_SEL69_INTSEL1 (*((volatile unsigned int*)(0x42A22E04UL))) +#define bM4_INTC_SEL69_INTSEL2 (*((volatile unsigned int*)(0x42A22E08UL))) +#define bM4_INTC_SEL69_INTSEL3 (*((volatile unsigned int*)(0x42A22E0CUL))) +#define bM4_INTC_SEL69_INTSEL4 (*((volatile unsigned int*)(0x42A22E10UL))) +#define bM4_INTC_SEL69_INTSEL5 (*((volatile unsigned int*)(0x42A22E14UL))) +#define bM4_INTC_SEL69_INTSEL6 (*((volatile unsigned int*)(0x42A22E18UL))) +#define bM4_INTC_SEL69_INTSEL7 (*((volatile unsigned int*)(0x42A22E1CUL))) +#define bM4_INTC_SEL69_INTSEL8 (*((volatile unsigned int*)(0x42A22E20UL))) +#define bM4_INTC_SEL70_INTSEL0 (*((volatile unsigned int*)(0x42A22E80UL))) +#define bM4_INTC_SEL70_INTSEL1 (*((volatile unsigned int*)(0x42A22E84UL))) +#define bM4_INTC_SEL70_INTSEL2 (*((volatile unsigned int*)(0x42A22E88UL))) +#define bM4_INTC_SEL70_INTSEL3 (*((volatile unsigned int*)(0x42A22E8CUL))) +#define bM4_INTC_SEL70_INTSEL4 (*((volatile unsigned int*)(0x42A22E90UL))) +#define bM4_INTC_SEL70_INTSEL5 (*((volatile unsigned int*)(0x42A22E94UL))) +#define bM4_INTC_SEL70_INTSEL6 (*((volatile unsigned int*)(0x42A22E98UL))) +#define bM4_INTC_SEL70_INTSEL7 (*((volatile unsigned int*)(0x42A22E9CUL))) +#define bM4_INTC_SEL70_INTSEL8 (*((volatile unsigned int*)(0x42A22EA0UL))) +#define bM4_INTC_SEL71_INTSEL0 (*((volatile unsigned int*)(0x42A22F00UL))) +#define bM4_INTC_SEL71_INTSEL1 (*((volatile unsigned int*)(0x42A22F04UL))) +#define bM4_INTC_SEL71_INTSEL2 (*((volatile unsigned int*)(0x42A22F08UL))) +#define bM4_INTC_SEL71_INTSEL3 (*((volatile unsigned int*)(0x42A22F0CUL))) +#define bM4_INTC_SEL71_INTSEL4 (*((volatile unsigned int*)(0x42A22F10UL))) +#define bM4_INTC_SEL71_INTSEL5 (*((volatile unsigned int*)(0x42A22F14UL))) +#define bM4_INTC_SEL71_INTSEL6 (*((volatile unsigned int*)(0x42A22F18UL))) +#define bM4_INTC_SEL71_INTSEL7 (*((volatile unsigned int*)(0x42A22F1CUL))) +#define bM4_INTC_SEL71_INTSEL8 (*((volatile unsigned int*)(0x42A22F20UL))) +#define bM4_INTC_SEL72_INTSEL0 (*((volatile unsigned int*)(0x42A22F80UL))) +#define bM4_INTC_SEL72_INTSEL1 (*((volatile unsigned int*)(0x42A22F84UL))) +#define bM4_INTC_SEL72_INTSEL2 (*((volatile unsigned int*)(0x42A22F88UL))) +#define bM4_INTC_SEL72_INTSEL3 (*((volatile unsigned int*)(0x42A22F8CUL))) +#define bM4_INTC_SEL72_INTSEL4 (*((volatile unsigned int*)(0x42A22F90UL))) +#define bM4_INTC_SEL72_INTSEL5 (*((volatile unsigned int*)(0x42A22F94UL))) +#define bM4_INTC_SEL72_INTSEL6 (*((volatile unsigned int*)(0x42A22F98UL))) +#define bM4_INTC_SEL72_INTSEL7 (*((volatile unsigned int*)(0x42A22F9CUL))) +#define bM4_INTC_SEL72_INTSEL8 (*((volatile unsigned int*)(0x42A22FA0UL))) +#define bM4_INTC_SEL73_INTSEL0 (*((volatile unsigned int*)(0x42A23000UL))) +#define bM4_INTC_SEL73_INTSEL1 (*((volatile unsigned int*)(0x42A23004UL))) +#define bM4_INTC_SEL73_INTSEL2 (*((volatile unsigned int*)(0x42A23008UL))) +#define bM4_INTC_SEL73_INTSEL3 (*((volatile unsigned int*)(0x42A2300CUL))) +#define bM4_INTC_SEL73_INTSEL4 (*((volatile unsigned int*)(0x42A23010UL))) +#define bM4_INTC_SEL73_INTSEL5 (*((volatile unsigned int*)(0x42A23014UL))) +#define bM4_INTC_SEL73_INTSEL6 (*((volatile unsigned int*)(0x42A23018UL))) +#define bM4_INTC_SEL73_INTSEL7 (*((volatile unsigned int*)(0x42A2301CUL))) +#define bM4_INTC_SEL73_INTSEL8 (*((volatile unsigned int*)(0x42A23020UL))) +#define bM4_INTC_SEL74_INTSEL0 (*((volatile unsigned int*)(0x42A23080UL))) +#define bM4_INTC_SEL74_INTSEL1 (*((volatile unsigned int*)(0x42A23084UL))) +#define bM4_INTC_SEL74_INTSEL2 (*((volatile unsigned int*)(0x42A23088UL))) +#define bM4_INTC_SEL74_INTSEL3 (*((volatile unsigned int*)(0x42A2308CUL))) +#define bM4_INTC_SEL74_INTSEL4 (*((volatile unsigned int*)(0x42A23090UL))) +#define bM4_INTC_SEL74_INTSEL5 (*((volatile unsigned int*)(0x42A23094UL))) +#define bM4_INTC_SEL74_INTSEL6 (*((volatile unsigned int*)(0x42A23098UL))) +#define bM4_INTC_SEL74_INTSEL7 (*((volatile unsigned int*)(0x42A2309CUL))) +#define bM4_INTC_SEL74_INTSEL8 (*((volatile unsigned int*)(0x42A230A0UL))) +#define bM4_INTC_SEL75_INTSEL0 (*((volatile unsigned int*)(0x42A23100UL))) +#define bM4_INTC_SEL75_INTSEL1 (*((volatile unsigned int*)(0x42A23104UL))) +#define bM4_INTC_SEL75_INTSEL2 (*((volatile unsigned int*)(0x42A23108UL))) +#define bM4_INTC_SEL75_INTSEL3 (*((volatile unsigned int*)(0x42A2310CUL))) +#define bM4_INTC_SEL75_INTSEL4 (*((volatile unsigned int*)(0x42A23110UL))) +#define bM4_INTC_SEL75_INTSEL5 (*((volatile unsigned int*)(0x42A23114UL))) +#define bM4_INTC_SEL75_INTSEL6 (*((volatile unsigned int*)(0x42A23118UL))) +#define bM4_INTC_SEL75_INTSEL7 (*((volatile unsigned int*)(0x42A2311CUL))) +#define bM4_INTC_SEL75_INTSEL8 (*((volatile unsigned int*)(0x42A23120UL))) +#define bM4_INTC_SEL76_INTSEL0 (*((volatile unsigned int*)(0x42A23180UL))) +#define bM4_INTC_SEL76_INTSEL1 (*((volatile unsigned int*)(0x42A23184UL))) +#define bM4_INTC_SEL76_INTSEL2 (*((volatile unsigned int*)(0x42A23188UL))) +#define bM4_INTC_SEL76_INTSEL3 (*((volatile unsigned int*)(0x42A2318CUL))) +#define bM4_INTC_SEL76_INTSEL4 (*((volatile unsigned int*)(0x42A23190UL))) +#define bM4_INTC_SEL76_INTSEL5 (*((volatile unsigned int*)(0x42A23194UL))) +#define bM4_INTC_SEL76_INTSEL6 (*((volatile unsigned int*)(0x42A23198UL))) +#define bM4_INTC_SEL76_INTSEL7 (*((volatile unsigned int*)(0x42A2319CUL))) +#define bM4_INTC_SEL76_INTSEL8 (*((volatile unsigned int*)(0x42A231A0UL))) +#define bM4_INTC_SEL77_INTSEL0 (*((volatile unsigned int*)(0x42A23200UL))) +#define bM4_INTC_SEL77_INTSEL1 (*((volatile unsigned int*)(0x42A23204UL))) +#define bM4_INTC_SEL77_INTSEL2 (*((volatile unsigned int*)(0x42A23208UL))) +#define bM4_INTC_SEL77_INTSEL3 (*((volatile unsigned int*)(0x42A2320CUL))) +#define bM4_INTC_SEL77_INTSEL4 (*((volatile unsigned int*)(0x42A23210UL))) +#define bM4_INTC_SEL77_INTSEL5 (*((volatile unsigned int*)(0x42A23214UL))) +#define bM4_INTC_SEL77_INTSEL6 (*((volatile unsigned int*)(0x42A23218UL))) +#define bM4_INTC_SEL77_INTSEL7 (*((volatile unsigned int*)(0x42A2321CUL))) +#define bM4_INTC_SEL77_INTSEL8 (*((volatile unsigned int*)(0x42A23220UL))) +#define bM4_INTC_SEL78_INTSEL0 (*((volatile unsigned int*)(0x42A23280UL))) +#define bM4_INTC_SEL78_INTSEL1 (*((volatile unsigned int*)(0x42A23284UL))) +#define bM4_INTC_SEL78_INTSEL2 (*((volatile unsigned int*)(0x42A23288UL))) +#define bM4_INTC_SEL78_INTSEL3 (*((volatile unsigned int*)(0x42A2328CUL))) +#define bM4_INTC_SEL78_INTSEL4 (*((volatile unsigned int*)(0x42A23290UL))) +#define bM4_INTC_SEL78_INTSEL5 (*((volatile unsigned int*)(0x42A23294UL))) +#define bM4_INTC_SEL78_INTSEL6 (*((volatile unsigned int*)(0x42A23298UL))) +#define bM4_INTC_SEL78_INTSEL7 (*((volatile unsigned int*)(0x42A2329CUL))) +#define bM4_INTC_SEL78_INTSEL8 (*((volatile unsigned int*)(0x42A232A0UL))) +#define bM4_INTC_SEL79_INTSEL0 (*((volatile unsigned int*)(0x42A23300UL))) +#define bM4_INTC_SEL79_INTSEL1 (*((volatile unsigned int*)(0x42A23304UL))) +#define bM4_INTC_SEL79_INTSEL2 (*((volatile unsigned int*)(0x42A23308UL))) +#define bM4_INTC_SEL79_INTSEL3 (*((volatile unsigned int*)(0x42A2330CUL))) +#define bM4_INTC_SEL79_INTSEL4 (*((volatile unsigned int*)(0x42A23310UL))) +#define bM4_INTC_SEL79_INTSEL5 (*((volatile unsigned int*)(0x42A23314UL))) +#define bM4_INTC_SEL79_INTSEL6 (*((volatile unsigned int*)(0x42A23318UL))) +#define bM4_INTC_SEL79_INTSEL7 (*((volatile unsigned int*)(0x42A2331CUL))) +#define bM4_INTC_SEL79_INTSEL8 (*((volatile unsigned int*)(0x42A23320UL))) +#define bM4_INTC_SEL80_INTSEL0 (*((volatile unsigned int*)(0x42A23380UL))) +#define bM4_INTC_SEL80_INTSEL1 (*((volatile unsigned int*)(0x42A23384UL))) +#define bM4_INTC_SEL80_INTSEL2 (*((volatile unsigned int*)(0x42A23388UL))) +#define bM4_INTC_SEL80_INTSEL3 (*((volatile unsigned int*)(0x42A2338CUL))) +#define bM4_INTC_SEL80_INTSEL4 (*((volatile unsigned int*)(0x42A23390UL))) +#define bM4_INTC_SEL80_INTSEL5 (*((volatile unsigned int*)(0x42A23394UL))) +#define bM4_INTC_SEL80_INTSEL6 (*((volatile unsigned int*)(0x42A23398UL))) +#define bM4_INTC_SEL80_INTSEL7 (*((volatile unsigned int*)(0x42A2339CUL))) +#define bM4_INTC_SEL80_INTSEL8 (*((volatile unsigned int*)(0x42A233A0UL))) +#define bM4_INTC_SEL81_INTSEL0 (*((volatile unsigned int*)(0x42A23400UL))) +#define bM4_INTC_SEL81_INTSEL1 (*((volatile unsigned int*)(0x42A23404UL))) +#define bM4_INTC_SEL81_INTSEL2 (*((volatile unsigned int*)(0x42A23408UL))) +#define bM4_INTC_SEL81_INTSEL3 (*((volatile unsigned int*)(0x42A2340CUL))) +#define bM4_INTC_SEL81_INTSEL4 (*((volatile unsigned int*)(0x42A23410UL))) +#define bM4_INTC_SEL81_INTSEL5 (*((volatile unsigned int*)(0x42A23414UL))) +#define bM4_INTC_SEL81_INTSEL6 (*((volatile unsigned int*)(0x42A23418UL))) +#define bM4_INTC_SEL81_INTSEL7 (*((volatile unsigned int*)(0x42A2341CUL))) +#define bM4_INTC_SEL81_INTSEL8 (*((volatile unsigned int*)(0x42A23420UL))) +#define bM4_INTC_SEL82_INTSEL0 (*((volatile unsigned int*)(0x42A23480UL))) +#define bM4_INTC_SEL82_INTSEL1 (*((volatile unsigned int*)(0x42A23484UL))) +#define bM4_INTC_SEL82_INTSEL2 (*((volatile unsigned int*)(0x42A23488UL))) +#define bM4_INTC_SEL82_INTSEL3 (*((volatile unsigned int*)(0x42A2348CUL))) +#define bM4_INTC_SEL82_INTSEL4 (*((volatile unsigned int*)(0x42A23490UL))) +#define bM4_INTC_SEL82_INTSEL5 (*((volatile unsigned int*)(0x42A23494UL))) +#define bM4_INTC_SEL82_INTSEL6 (*((volatile unsigned int*)(0x42A23498UL))) +#define bM4_INTC_SEL82_INTSEL7 (*((volatile unsigned int*)(0x42A2349CUL))) +#define bM4_INTC_SEL82_INTSEL8 (*((volatile unsigned int*)(0x42A234A0UL))) +#define bM4_INTC_SEL83_INTSEL0 (*((volatile unsigned int*)(0x42A23500UL))) +#define bM4_INTC_SEL83_INTSEL1 (*((volatile unsigned int*)(0x42A23504UL))) +#define bM4_INTC_SEL83_INTSEL2 (*((volatile unsigned int*)(0x42A23508UL))) +#define bM4_INTC_SEL83_INTSEL3 (*((volatile unsigned int*)(0x42A2350CUL))) +#define bM4_INTC_SEL83_INTSEL4 (*((volatile unsigned int*)(0x42A23510UL))) +#define bM4_INTC_SEL83_INTSEL5 (*((volatile unsigned int*)(0x42A23514UL))) +#define bM4_INTC_SEL83_INTSEL6 (*((volatile unsigned int*)(0x42A23518UL))) +#define bM4_INTC_SEL83_INTSEL7 (*((volatile unsigned int*)(0x42A2351CUL))) +#define bM4_INTC_SEL83_INTSEL8 (*((volatile unsigned int*)(0x42A23520UL))) +#define bM4_INTC_SEL84_INTSEL0 (*((volatile unsigned int*)(0x42A23580UL))) +#define bM4_INTC_SEL84_INTSEL1 (*((volatile unsigned int*)(0x42A23584UL))) +#define bM4_INTC_SEL84_INTSEL2 (*((volatile unsigned int*)(0x42A23588UL))) +#define bM4_INTC_SEL84_INTSEL3 (*((volatile unsigned int*)(0x42A2358CUL))) +#define bM4_INTC_SEL84_INTSEL4 (*((volatile unsigned int*)(0x42A23590UL))) +#define bM4_INTC_SEL84_INTSEL5 (*((volatile unsigned int*)(0x42A23594UL))) +#define bM4_INTC_SEL84_INTSEL6 (*((volatile unsigned int*)(0x42A23598UL))) +#define bM4_INTC_SEL84_INTSEL7 (*((volatile unsigned int*)(0x42A2359CUL))) +#define bM4_INTC_SEL84_INTSEL8 (*((volatile unsigned int*)(0x42A235A0UL))) +#define bM4_INTC_SEL85_INTSEL0 (*((volatile unsigned int*)(0x42A23600UL))) +#define bM4_INTC_SEL85_INTSEL1 (*((volatile unsigned int*)(0x42A23604UL))) +#define bM4_INTC_SEL85_INTSEL2 (*((volatile unsigned int*)(0x42A23608UL))) +#define bM4_INTC_SEL85_INTSEL3 (*((volatile unsigned int*)(0x42A2360CUL))) +#define bM4_INTC_SEL85_INTSEL4 (*((volatile unsigned int*)(0x42A23610UL))) +#define bM4_INTC_SEL85_INTSEL5 (*((volatile unsigned int*)(0x42A23614UL))) +#define bM4_INTC_SEL85_INTSEL6 (*((volatile unsigned int*)(0x42A23618UL))) +#define bM4_INTC_SEL85_INTSEL7 (*((volatile unsigned int*)(0x42A2361CUL))) +#define bM4_INTC_SEL85_INTSEL8 (*((volatile unsigned int*)(0x42A23620UL))) +#define bM4_INTC_SEL86_INTSEL0 (*((volatile unsigned int*)(0x42A23680UL))) +#define bM4_INTC_SEL86_INTSEL1 (*((volatile unsigned int*)(0x42A23684UL))) +#define bM4_INTC_SEL86_INTSEL2 (*((volatile unsigned int*)(0x42A23688UL))) +#define bM4_INTC_SEL86_INTSEL3 (*((volatile unsigned int*)(0x42A2368CUL))) +#define bM4_INTC_SEL86_INTSEL4 (*((volatile unsigned int*)(0x42A23690UL))) +#define bM4_INTC_SEL86_INTSEL5 (*((volatile unsigned int*)(0x42A23694UL))) +#define bM4_INTC_SEL86_INTSEL6 (*((volatile unsigned int*)(0x42A23698UL))) +#define bM4_INTC_SEL86_INTSEL7 (*((volatile unsigned int*)(0x42A2369CUL))) +#define bM4_INTC_SEL86_INTSEL8 (*((volatile unsigned int*)(0x42A236A0UL))) +#define bM4_INTC_SEL87_INTSEL0 (*((volatile unsigned int*)(0x42A23700UL))) +#define bM4_INTC_SEL87_INTSEL1 (*((volatile unsigned int*)(0x42A23704UL))) +#define bM4_INTC_SEL87_INTSEL2 (*((volatile unsigned int*)(0x42A23708UL))) +#define bM4_INTC_SEL87_INTSEL3 (*((volatile unsigned int*)(0x42A2370CUL))) +#define bM4_INTC_SEL87_INTSEL4 (*((volatile unsigned int*)(0x42A23710UL))) +#define bM4_INTC_SEL87_INTSEL5 (*((volatile unsigned int*)(0x42A23714UL))) +#define bM4_INTC_SEL87_INTSEL6 (*((volatile unsigned int*)(0x42A23718UL))) +#define bM4_INTC_SEL87_INTSEL7 (*((volatile unsigned int*)(0x42A2371CUL))) +#define bM4_INTC_SEL87_INTSEL8 (*((volatile unsigned int*)(0x42A23720UL))) +#define bM4_INTC_SEL88_INTSEL0 (*((volatile unsigned int*)(0x42A23780UL))) +#define bM4_INTC_SEL88_INTSEL1 (*((volatile unsigned int*)(0x42A23784UL))) +#define bM4_INTC_SEL88_INTSEL2 (*((volatile unsigned int*)(0x42A23788UL))) +#define bM4_INTC_SEL88_INTSEL3 (*((volatile unsigned int*)(0x42A2378CUL))) +#define bM4_INTC_SEL88_INTSEL4 (*((volatile unsigned int*)(0x42A23790UL))) +#define bM4_INTC_SEL88_INTSEL5 (*((volatile unsigned int*)(0x42A23794UL))) +#define bM4_INTC_SEL88_INTSEL6 (*((volatile unsigned int*)(0x42A23798UL))) +#define bM4_INTC_SEL88_INTSEL7 (*((volatile unsigned int*)(0x42A2379CUL))) +#define bM4_INTC_SEL88_INTSEL8 (*((volatile unsigned int*)(0x42A237A0UL))) +#define bM4_INTC_SEL89_INTSEL0 (*((volatile unsigned int*)(0x42A23800UL))) +#define bM4_INTC_SEL89_INTSEL1 (*((volatile unsigned int*)(0x42A23804UL))) +#define bM4_INTC_SEL89_INTSEL2 (*((volatile unsigned int*)(0x42A23808UL))) +#define bM4_INTC_SEL89_INTSEL3 (*((volatile unsigned int*)(0x42A2380CUL))) +#define bM4_INTC_SEL89_INTSEL4 (*((volatile unsigned int*)(0x42A23810UL))) +#define bM4_INTC_SEL89_INTSEL5 (*((volatile unsigned int*)(0x42A23814UL))) +#define bM4_INTC_SEL89_INTSEL6 (*((volatile unsigned int*)(0x42A23818UL))) +#define bM4_INTC_SEL89_INTSEL7 (*((volatile unsigned int*)(0x42A2381CUL))) +#define bM4_INTC_SEL89_INTSEL8 (*((volatile unsigned int*)(0x42A23820UL))) +#define bM4_INTC_SEL90_INTSEL0 (*((volatile unsigned int*)(0x42A23880UL))) +#define bM4_INTC_SEL90_INTSEL1 (*((volatile unsigned int*)(0x42A23884UL))) +#define bM4_INTC_SEL90_INTSEL2 (*((volatile unsigned int*)(0x42A23888UL))) +#define bM4_INTC_SEL90_INTSEL3 (*((volatile unsigned int*)(0x42A2388CUL))) +#define bM4_INTC_SEL90_INTSEL4 (*((volatile unsigned int*)(0x42A23890UL))) +#define bM4_INTC_SEL90_INTSEL5 (*((volatile unsigned int*)(0x42A23894UL))) +#define bM4_INTC_SEL90_INTSEL6 (*((volatile unsigned int*)(0x42A23898UL))) +#define bM4_INTC_SEL90_INTSEL7 (*((volatile unsigned int*)(0x42A2389CUL))) +#define bM4_INTC_SEL90_INTSEL8 (*((volatile unsigned int*)(0x42A238A0UL))) +#define bM4_INTC_SEL91_INTSEL0 (*((volatile unsigned int*)(0x42A23900UL))) +#define bM4_INTC_SEL91_INTSEL1 (*((volatile unsigned int*)(0x42A23904UL))) +#define bM4_INTC_SEL91_INTSEL2 (*((volatile unsigned int*)(0x42A23908UL))) +#define bM4_INTC_SEL91_INTSEL3 (*((volatile unsigned int*)(0x42A2390CUL))) +#define bM4_INTC_SEL91_INTSEL4 (*((volatile unsigned int*)(0x42A23910UL))) +#define bM4_INTC_SEL91_INTSEL5 (*((volatile unsigned int*)(0x42A23914UL))) +#define bM4_INTC_SEL91_INTSEL6 (*((volatile unsigned int*)(0x42A23918UL))) +#define bM4_INTC_SEL91_INTSEL7 (*((volatile unsigned int*)(0x42A2391CUL))) +#define bM4_INTC_SEL91_INTSEL8 (*((volatile unsigned int*)(0x42A23920UL))) +#define bM4_INTC_SEL92_INTSEL0 (*((volatile unsigned int*)(0x42A23980UL))) +#define bM4_INTC_SEL92_INTSEL1 (*((volatile unsigned int*)(0x42A23984UL))) +#define bM4_INTC_SEL92_INTSEL2 (*((volatile unsigned int*)(0x42A23988UL))) +#define bM4_INTC_SEL92_INTSEL3 (*((volatile unsigned int*)(0x42A2398CUL))) +#define bM4_INTC_SEL92_INTSEL4 (*((volatile unsigned int*)(0x42A23990UL))) +#define bM4_INTC_SEL92_INTSEL5 (*((volatile unsigned int*)(0x42A23994UL))) +#define bM4_INTC_SEL92_INTSEL6 (*((volatile unsigned int*)(0x42A23998UL))) +#define bM4_INTC_SEL92_INTSEL7 (*((volatile unsigned int*)(0x42A2399CUL))) +#define bM4_INTC_SEL92_INTSEL8 (*((volatile unsigned int*)(0x42A239A0UL))) +#define bM4_INTC_SEL93_INTSEL0 (*((volatile unsigned int*)(0x42A23A00UL))) +#define bM4_INTC_SEL93_INTSEL1 (*((volatile unsigned int*)(0x42A23A04UL))) +#define bM4_INTC_SEL93_INTSEL2 (*((volatile unsigned int*)(0x42A23A08UL))) +#define bM4_INTC_SEL93_INTSEL3 (*((volatile unsigned int*)(0x42A23A0CUL))) +#define bM4_INTC_SEL93_INTSEL4 (*((volatile unsigned int*)(0x42A23A10UL))) +#define bM4_INTC_SEL93_INTSEL5 (*((volatile unsigned int*)(0x42A23A14UL))) +#define bM4_INTC_SEL93_INTSEL6 (*((volatile unsigned int*)(0x42A23A18UL))) +#define bM4_INTC_SEL93_INTSEL7 (*((volatile unsigned int*)(0x42A23A1CUL))) +#define bM4_INTC_SEL93_INTSEL8 (*((volatile unsigned int*)(0x42A23A20UL))) +#define bM4_INTC_SEL94_INTSEL0 (*((volatile unsigned int*)(0x42A23A80UL))) +#define bM4_INTC_SEL94_INTSEL1 (*((volatile unsigned int*)(0x42A23A84UL))) +#define bM4_INTC_SEL94_INTSEL2 (*((volatile unsigned int*)(0x42A23A88UL))) +#define bM4_INTC_SEL94_INTSEL3 (*((volatile unsigned int*)(0x42A23A8CUL))) +#define bM4_INTC_SEL94_INTSEL4 (*((volatile unsigned int*)(0x42A23A90UL))) +#define bM4_INTC_SEL94_INTSEL5 (*((volatile unsigned int*)(0x42A23A94UL))) +#define bM4_INTC_SEL94_INTSEL6 (*((volatile unsigned int*)(0x42A23A98UL))) +#define bM4_INTC_SEL94_INTSEL7 (*((volatile unsigned int*)(0x42A23A9CUL))) +#define bM4_INTC_SEL94_INTSEL8 (*((volatile unsigned int*)(0x42A23AA0UL))) +#define bM4_INTC_SEL95_INTSEL0 (*((volatile unsigned int*)(0x42A23B00UL))) +#define bM4_INTC_SEL95_INTSEL1 (*((volatile unsigned int*)(0x42A23B04UL))) +#define bM4_INTC_SEL95_INTSEL2 (*((volatile unsigned int*)(0x42A23B08UL))) +#define bM4_INTC_SEL95_INTSEL3 (*((volatile unsigned int*)(0x42A23B0CUL))) +#define bM4_INTC_SEL95_INTSEL4 (*((volatile unsigned int*)(0x42A23B10UL))) +#define bM4_INTC_SEL95_INTSEL5 (*((volatile unsigned int*)(0x42A23B14UL))) +#define bM4_INTC_SEL95_INTSEL6 (*((volatile unsigned int*)(0x42A23B18UL))) +#define bM4_INTC_SEL95_INTSEL7 (*((volatile unsigned int*)(0x42A23B1CUL))) +#define bM4_INTC_SEL95_INTSEL8 (*((volatile unsigned int*)(0x42A23B20UL))) +#define bM4_INTC_SEL96_INTSEL0 (*((volatile unsigned int*)(0x42A23B80UL))) +#define bM4_INTC_SEL96_INTSEL1 (*((volatile unsigned int*)(0x42A23B84UL))) +#define bM4_INTC_SEL96_INTSEL2 (*((volatile unsigned int*)(0x42A23B88UL))) +#define bM4_INTC_SEL96_INTSEL3 (*((volatile unsigned int*)(0x42A23B8CUL))) +#define bM4_INTC_SEL96_INTSEL4 (*((volatile unsigned int*)(0x42A23B90UL))) +#define bM4_INTC_SEL96_INTSEL5 (*((volatile unsigned int*)(0x42A23B94UL))) +#define bM4_INTC_SEL96_INTSEL6 (*((volatile unsigned int*)(0x42A23B98UL))) +#define bM4_INTC_SEL96_INTSEL7 (*((volatile unsigned int*)(0x42A23B9CUL))) +#define bM4_INTC_SEL96_INTSEL8 (*((volatile unsigned int*)(0x42A23BA0UL))) +#define bM4_INTC_SEL97_INTSEL0 (*((volatile unsigned int*)(0x42A23C00UL))) +#define bM4_INTC_SEL97_INTSEL1 (*((volatile unsigned int*)(0x42A23C04UL))) +#define bM4_INTC_SEL97_INTSEL2 (*((volatile unsigned int*)(0x42A23C08UL))) +#define bM4_INTC_SEL97_INTSEL3 (*((volatile unsigned int*)(0x42A23C0CUL))) +#define bM4_INTC_SEL97_INTSEL4 (*((volatile unsigned int*)(0x42A23C10UL))) +#define bM4_INTC_SEL97_INTSEL5 (*((volatile unsigned int*)(0x42A23C14UL))) +#define bM4_INTC_SEL97_INTSEL6 (*((volatile unsigned int*)(0x42A23C18UL))) +#define bM4_INTC_SEL97_INTSEL7 (*((volatile unsigned int*)(0x42A23C1CUL))) +#define bM4_INTC_SEL97_INTSEL8 (*((volatile unsigned int*)(0x42A23C20UL))) +#define bM4_INTC_SEL98_INTSEL0 (*((volatile unsigned int*)(0x42A23C80UL))) +#define bM4_INTC_SEL98_INTSEL1 (*((volatile unsigned int*)(0x42A23C84UL))) +#define bM4_INTC_SEL98_INTSEL2 (*((volatile unsigned int*)(0x42A23C88UL))) +#define bM4_INTC_SEL98_INTSEL3 (*((volatile unsigned int*)(0x42A23C8CUL))) +#define bM4_INTC_SEL98_INTSEL4 (*((volatile unsigned int*)(0x42A23C90UL))) +#define bM4_INTC_SEL98_INTSEL5 (*((volatile unsigned int*)(0x42A23C94UL))) +#define bM4_INTC_SEL98_INTSEL6 (*((volatile unsigned int*)(0x42A23C98UL))) +#define bM4_INTC_SEL98_INTSEL7 (*((volatile unsigned int*)(0x42A23C9CUL))) +#define bM4_INTC_SEL98_INTSEL8 (*((volatile unsigned int*)(0x42A23CA0UL))) +#define bM4_INTC_SEL99_INTSEL0 (*((volatile unsigned int*)(0x42A23D00UL))) +#define bM4_INTC_SEL99_INTSEL1 (*((volatile unsigned int*)(0x42A23D04UL))) +#define bM4_INTC_SEL99_INTSEL2 (*((volatile unsigned int*)(0x42A23D08UL))) +#define bM4_INTC_SEL99_INTSEL3 (*((volatile unsigned int*)(0x42A23D0CUL))) +#define bM4_INTC_SEL99_INTSEL4 (*((volatile unsigned int*)(0x42A23D10UL))) +#define bM4_INTC_SEL99_INTSEL5 (*((volatile unsigned int*)(0x42A23D14UL))) +#define bM4_INTC_SEL99_INTSEL6 (*((volatile unsigned int*)(0x42A23D18UL))) +#define bM4_INTC_SEL99_INTSEL7 (*((volatile unsigned int*)(0x42A23D1CUL))) +#define bM4_INTC_SEL99_INTSEL8 (*((volatile unsigned int*)(0x42A23D20UL))) +#define bM4_INTC_SEL100_INTSEL0 (*((volatile unsigned int*)(0x42A23D80UL))) +#define bM4_INTC_SEL100_INTSEL1 (*((volatile unsigned int*)(0x42A23D84UL))) +#define bM4_INTC_SEL100_INTSEL2 (*((volatile unsigned int*)(0x42A23D88UL))) +#define bM4_INTC_SEL100_INTSEL3 (*((volatile unsigned int*)(0x42A23D8CUL))) +#define bM4_INTC_SEL100_INTSEL4 (*((volatile unsigned int*)(0x42A23D90UL))) +#define bM4_INTC_SEL100_INTSEL5 (*((volatile unsigned int*)(0x42A23D94UL))) +#define bM4_INTC_SEL100_INTSEL6 (*((volatile unsigned int*)(0x42A23D98UL))) +#define bM4_INTC_SEL100_INTSEL7 (*((volatile unsigned int*)(0x42A23D9CUL))) +#define bM4_INTC_SEL100_INTSEL8 (*((volatile unsigned int*)(0x42A23DA0UL))) +#define bM4_INTC_SEL101_INTSEL0 (*((volatile unsigned int*)(0x42A23E00UL))) +#define bM4_INTC_SEL101_INTSEL1 (*((volatile unsigned int*)(0x42A23E04UL))) +#define bM4_INTC_SEL101_INTSEL2 (*((volatile unsigned int*)(0x42A23E08UL))) +#define bM4_INTC_SEL101_INTSEL3 (*((volatile unsigned int*)(0x42A23E0CUL))) +#define bM4_INTC_SEL101_INTSEL4 (*((volatile unsigned int*)(0x42A23E10UL))) +#define bM4_INTC_SEL101_INTSEL5 (*((volatile unsigned int*)(0x42A23E14UL))) +#define bM4_INTC_SEL101_INTSEL6 (*((volatile unsigned int*)(0x42A23E18UL))) +#define bM4_INTC_SEL101_INTSEL7 (*((volatile unsigned int*)(0x42A23E1CUL))) +#define bM4_INTC_SEL101_INTSEL8 (*((volatile unsigned int*)(0x42A23E20UL))) +#define bM4_INTC_SEL102_INTSEL0 (*((volatile unsigned int*)(0x42A23E80UL))) +#define bM4_INTC_SEL102_INTSEL1 (*((volatile unsigned int*)(0x42A23E84UL))) +#define bM4_INTC_SEL102_INTSEL2 (*((volatile unsigned int*)(0x42A23E88UL))) +#define bM4_INTC_SEL102_INTSEL3 (*((volatile unsigned int*)(0x42A23E8CUL))) +#define bM4_INTC_SEL102_INTSEL4 (*((volatile unsigned int*)(0x42A23E90UL))) +#define bM4_INTC_SEL102_INTSEL5 (*((volatile unsigned int*)(0x42A23E94UL))) +#define bM4_INTC_SEL102_INTSEL6 (*((volatile unsigned int*)(0x42A23E98UL))) +#define bM4_INTC_SEL102_INTSEL7 (*((volatile unsigned int*)(0x42A23E9CUL))) +#define bM4_INTC_SEL102_INTSEL8 (*((volatile unsigned int*)(0x42A23EA0UL))) +#define bM4_INTC_SEL103_INTSEL0 (*((volatile unsigned int*)(0x42A23F00UL))) +#define bM4_INTC_SEL103_INTSEL1 (*((volatile unsigned int*)(0x42A23F04UL))) +#define bM4_INTC_SEL103_INTSEL2 (*((volatile unsigned int*)(0x42A23F08UL))) +#define bM4_INTC_SEL103_INTSEL3 (*((volatile unsigned int*)(0x42A23F0CUL))) +#define bM4_INTC_SEL103_INTSEL4 (*((volatile unsigned int*)(0x42A23F10UL))) +#define bM4_INTC_SEL103_INTSEL5 (*((volatile unsigned int*)(0x42A23F14UL))) +#define bM4_INTC_SEL103_INTSEL6 (*((volatile unsigned int*)(0x42A23F18UL))) +#define bM4_INTC_SEL103_INTSEL7 (*((volatile unsigned int*)(0x42A23F1CUL))) +#define bM4_INTC_SEL103_INTSEL8 (*((volatile unsigned int*)(0x42A23F20UL))) +#define bM4_INTC_SEL104_INTSEL0 (*((volatile unsigned int*)(0x42A23F80UL))) +#define bM4_INTC_SEL104_INTSEL1 (*((volatile unsigned int*)(0x42A23F84UL))) +#define bM4_INTC_SEL104_INTSEL2 (*((volatile unsigned int*)(0x42A23F88UL))) +#define bM4_INTC_SEL104_INTSEL3 (*((volatile unsigned int*)(0x42A23F8CUL))) +#define bM4_INTC_SEL104_INTSEL4 (*((volatile unsigned int*)(0x42A23F90UL))) +#define bM4_INTC_SEL104_INTSEL5 (*((volatile unsigned int*)(0x42A23F94UL))) +#define bM4_INTC_SEL104_INTSEL6 (*((volatile unsigned int*)(0x42A23F98UL))) +#define bM4_INTC_SEL104_INTSEL7 (*((volatile unsigned int*)(0x42A23F9CUL))) +#define bM4_INTC_SEL104_INTSEL8 (*((volatile unsigned int*)(0x42A23FA0UL))) +#define bM4_INTC_SEL105_INTSEL0 (*((volatile unsigned int*)(0x42A24000UL))) +#define bM4_INTC_SEL105_INTSEL1 (*((volatile unsigned int*)(0x42A24004UL))) +#define bM4_INTC_SEL105_INTSEL2 (*((volatile unsigned int*)(0x42A24008UL))) +#define bM4_INTC_SEL105_INTSEL3 (*((volatile unsigned int*)(0x42A2400CUL))) +#define bM4_INTC_SEL105_INTSEL4 (*((volatile unsigned int*)(0x42A24010UL))) +#define bM4_INTC_SEL105_INTSEL5 (*((volatile unsigned int*)(0x42A24014UL))) +#define bM4_INTC_SEL105_INTSEL6 (*((volatile unsigned int*)(0x42A24018UL))) +#define bM4_INTC_SEL105_INTSEL7 (*((volatile unsigned int*)(0x42A2401CUL))) +#define bM4_INTC_SEL105_INTSEL8 (*((volatile unsigned int*)(0x42A24020UL))) +#define bM4_INTC_SEL106_INTSEL0 (*((volatile unsigned int*)(0x42A24080UL))) +#define bM4_INTC_SEL106_INTSEL1 (*((volatile unsigned int*)(0x42A24084UL))) +#define bM4_INTC_SEL106_INTSEL2 (*((volatile unsigned int*)(0x42A24088UL))) +#define bM4_INTC_SEL106_INTSEL3 (*((volatile unsigned int*)(0x42A2408CUL))) +#define bM4_INTC_SEL106_INTSEL4 (*((volatile unsigned int*)(0x42A24090UL))) +#define bM4_INTC_SEL106_INTSEL5 (*((volatile unsigned int*)(0x42A24094UL))) +#define bM4_INTC_SEL106_INTSEL6 (*((volatile unsigned int*)(0x42A24098UL))) +#define bM4_INTC_SEL106_INTSEL7 (*((volatile unsigned int*)(0x42A2409CUL))) +#define bM4_INTC_SEL106_INTSEL8 (*((volatile unsigned int*)(0x42A240A0UL))) +#define bM4_INTC_SEL107_INTSEL0 (*((volatile unsigned int*)(0x42A24100UL))) +#define bM4_INTC_SEL107_INTSEL1 (*((volatile unsigned int*)(0x42A24104UL))) +#define bM4_INTC_SEL107_INTSEL2 (*((volatile unsigned int*)(0x42A24108UL))) +#define bM4_INTC_SEL107_INTSEL3 (*((volatile unsigned int*)(0x42A2410CUL))) +#define bM4_INTC_SEL107_INTSEL4 (*((volatile unsigned int*)(0x42A24110UL))) +#define bM4_INTC_SEL107_INTSEL5 (*((volatile unsigned int*)(0x42A24114UL))) +#define bM4_INTC_SEL107_INTSEL6 (*((volatile unsigned int*)(0x42A24118UL))) +#define bM4_INTC_SEL107_INTSEL7 (*((volatile unsigned int*)(0x42A2411CUL))) +#define bM4_INTC_SEL107_INTSEL8 (*((volatile unsigned int*)(0x42A24120UL))) +#define bM4_INTC_SEL108_INTSEL0 (*((volatile unsigned int*)(0x42A24180UL))) +#define bM4_INTC_SEL108_INTSEL1 (*((volatile unsigned int*)(0x42A24184UL))) +#define bM4_INTC_SEL108_INTSEL2 (*((volatile unsigned int*)(0x42A24188UL))) +#define bM4_INTC_SEL108_INTSEL3 (*((volatile unsigned int*)(0x42A2418CUL))) +#define bM4_INTC_SEL108_INTSEL4 (*((volatile unsigned int*)(0x42A24190UL))) +#define bM4_INTC_SEL108_INTSEL5 (*((volatile unsigned int*)(0x42A24194UL))) +#define bM4_INTC_SEL108_INTSEL6 (*((volatile unsigned int*)(0x42A24198UL))) +#define bM4_INTC_SEL108_INTSEL7 (*((volatile unsigned int*)(0x42A2419CUL))) +#define bM4_INTC_SEL108_INTSEL8 (*((volatile unsigned int*)(0x42A241A0UL))) +#define bM4_INTC_SEL109_INTSEL0 (*((volatile unsigned int*)(0x42A24200UL))) +#define bM4_INTC_SEL109_INTSEL1 (*((volatile unsigned int*)(0x42A24204UL))) +#define bM4_INTC_SEL109_INTSEL2 (*((volatile unsigned int*)(0x42A24208UL))) +#define bM4_INTC_SEL109_INTSEL3 (*((volatile unsigned int*)(0x42A2420CUL))) +#define bM4_INTC_SEL109_INTSEL4 (*((volatile unsigned int*)(0x42A24210UL))) +#define bM4_INTC_SEL109_INTSEL5 (*((volatile unsigned int*)(0x42A24214UL))) +#define bM4_INTC_SEL109_INTSEL6 (*((volatile unsigned int*)(0x42A24218UL))) +#define bM4_INTC_SEL109_INTSEL7 (*((volatile unsigned int*)(0x42A2421CUL))) +#define bM4_INTC_SEL109_INTSEL8 (*((volatile unsigned int*)(0x42A24220UL))) +#define bM4_INTC_SEL110_INTSEL0 (*((volatile unsigned int*)(0x42A24280UL))) +#define bM4_INTC_SEL110_INTSEL1 (*((volatile unsigned int*)(0x42A24284UL))) +#define bM4_INTC_SEL110_INTSEL2 (*((volatile unsigned int*)(0x42A24288UL))) +#define bM4_INTC_SEL110_INTSEL3 (*((volatile unsigned int*)(0x42A2428CUL))) +#define bM4_INTC_SEL110_INTSEL4 (*((volatile unsigned int*)(0x42A24290UL))) +#define bM4_INTC_SEL110_INTSEL5 (*((volatile unsigned int*)(0x42A24294UL))) +#define bM4_INTC_SEL110_INTSEL6 (*((volatile unsigned int*)(0x42A24298UL))) +#define bM4_INTC_SEL110_INTSEL7 (*((volatile unsigned int*)(0x42A2429CUL))) +#define bM4_INTC_SEL110_INTSEL8 (*((volatile unsigned int*)(0x42A242A0UL))) +#define bM4_INTC_SEL111_INTSEL0 (*((volatile unsigned int*)(0x42A24300UL))) +#define bM4_INTC_SEL111_INTSEL1 (*((volatile unsigned int*)(0x42A24304UL))) +#define bM4_INTC_SEL111_INTSEL2 (*((volatile unsigned int*)(0x42A24308UL))) +#define bM4_INTC_SEL111_INTSEL3 (*((volatile unsigned int*)(0x42A2430CUL))) +#define bM4_INTC_SEL111_INTSEL4 (*((volatile unsigned int*)(0x42A24310UL))) +#define bM4_INTC_SEL111_INTSEL5 (*((volatile unsigned int*)(0x42A24314UL))) +#define bM4_INTC_SEL111_INTSEL6 (*((volatile unsigned int*)(0x42A24318UL))) +#define bM4_INTC_SEL111_INTSEL7 (*((volatile unsigned int*)(0x42A2431CUL))) +#define bM4_INTC_SEL111_INTSEL8 (*((volatile unsigned int*)(0x42A24320UL))) +#define bM4_INTC_SEL112_INTSEL0 (*((volatile unsigned int*)(0x42A24380UL))) +#define bM4_INTC_SEL112_INTSEL1 (*((volatile unsigned int*)(0x42A24384UL))) +#define bM4_INTC_SEL112_INTSEL2 (*((volatile unsigned int*)(0x42A24388UL))) +#define bM4_INTC_SEL112_INTSEL3 (*((volatile unsigned int*)(0x42A2438CUL))) +#define bM4_INTC_SEL112_INTSEL4 (*((volatile unsigned int*)(0x42A24390UL))) +#define bM4_INTC_SEL112_INTSEL5 (*((volatile unsigned int*)(0x42A24394UL))) +#define bM4_INTC_SEL112_INTSEL6 (*((volatile unsigned int*)(0x42A24398UL))) +#define bM4_INTC_SEL112_INTSEL7 (*((volatile unsigned int*)(0x42A2439CUL))) +#define bM4_INTC_SEL112_INTSEL8 (*((volatile unsigned int*)(0x42A243A0UL))) +#define bM4_INTC_SEL113_INTSEL0 (*((volatile unsigned int*)(0x42A24400UL))) +#define bM4_INTC_SEL113_INTSEL1 (*((volatile unsigned int*)(0x42A24404UL))) +#define bM4_INTC_SEL113_INTSEL2 (*((volatile unsigned int*)(0x42A24408UL))) +#define bM4_INTC_SEL113_INTSEL3 (*((volatile unsigned int*)(0x42A2440CUL))) +#define bM4_INTC_SEL113_INTSEL4 (*((volatile unsigned int*)(0x42A24410UL))) +#define bM4_INTC_SEL113_INTSEL5 (*((volatile unsigned int*)(0x42A24414UL))) +#define bM4_INTC_SEL113_INTSEL6 (*((volatile unsigned int*)(0x42A24418UL))) +#define bM4_INTC_SEL113_INTSEL7 (*((volatile unsigned int*)(0x42A2441CUL))) +#define bM4_INTC_SEL113_INTSEL8 (*((volatile unsigned int*)(0x42A24420UL))) +#define bM4_INTC_SEL114_INTSEL0 (*((volatile unsigned int*)(0x42A24480UL))) +#define bM4_INTC_SEL114_INTSEL1 (*((volatile unsigned int*)(0x42A24484UL))) +#define bM4_INTC_SEL114_INTSEL2 (*((volatile unsigned int*)(0x42A24488UL))) +#define bM4_INTC_SEL114_INTSEL3 (*((volatile unsigned int*)(0x42A2448CUL))) +#define bM4_INTC_SEL114_INTSEL4 (*((volatile unsigned int*)(0x42A24490UL))) +#define bM4_INTC_SEL114_INTSEL5 (*((volatile unsigned int*)(0x42A24494UL))) +#define bM4_INTC_SEL114_INTSEL6 (*((volatile unsigned int*)(0x42A24498UL))) +#define bM4_INTC_SEL114_INTSEL7 (*((volatile unsigned int*)(0x42A2449CUL))) +#define bM4_INTC_SEL114_INTSEL8 (*((volatile unsigned int*)(0x42A244A0UL))) +#define bM4_INTC_SEL115_INTSEL0 (*((volatile unsigned int*)(0x42A24500UL))) +#define bM4_INTC_SEL115_INTSEL1 (*((volatile unsigned int*)(0x42A24504UL))) +#define bM4_INTC_SEL115_INTSEL2 (*((volatile unsigned int*)(0x42A24508UL))) +#define bM4_INTC_SEL115_INTSEL3 (*((volatile unsigned int*)(0x42A2450CUL))) +#define bM4_INTC_SEL115_INTSEL4 (*((volatile unsigned int*)(0x42A24510UL))) +#define bM4_INTC_SEL115_INTSEL5 (*((volatile unsigned int*)(0x42A24514UL))) +#define bM4_INTC_SEL115_INTSEL6 (*((volatile unsigned int*)(0x42A24518UL))) +#define bM4_INTC_SEL115_INTSEL7 (*((volatile unsigned int*)(0x42A2451CUL))) +#define bM4_INTC_SEL115_INTSEL8 (*((volatile unsigned int*)(0x42A24520UL))) +#define bM4_INTC_SEL116_INTSEL0 (*((volatile unsigned int*)(0x42A24580UL))) +#define bM4_INTC_SEL116_INTSEL1 (*((volatile unsigned int*)(0x42A24584UL))) +#define bM4_INTC_SEL116_INTSEL2 (*((volatile unsigned int*)(0x42A24588UL))) +#define bM4_INTC_SEL116_INTSEL3 (*((volatile unsigned int*)(0x42A2458CUL))) +#define bM4_INTC_SEL116_INTSEL4 (*((volatile unsigned int*)(0x42A24590UL))) +#define bM4_INTC_SEL116_INTSEL5 (*((volatile unsigned int*)(0x42A24594UL))) +#define bM4_INTC_SEL116_INTSEL6 (*((volatile unsigned int*)(0x42A24598UL))) +#define bM4_INTC_SEL116_INTSEL7 (*((volatile unsigned int*)(0x42A2459CUL))) +#define bM4_INTC_SEL116_INTSEL8 (*((volatile unsigned int*)(0x42A245A0UL))) +#define bM4_INTC_SEL117_INTSEL0 (*((volatile unsigned int*)(0x42A24600UL))) +#define bM4_INTC_SEL117_INTSEL1 (*((volatile unsigned int*)(0x42A24604UL))) +#define bM4_INTC_SEL117_INTSEL2 (*((volatile unsigned int*)(0x42A24608UL))) +#define bM4_INTC_SEL117_INTSEL3 (*((volatile unsigned int*)(0x42A2460CUL))) +#define bM4_INTC_SEL117_INTSEL4 (*((volatile unsigned int*)(0x42A24610UL))) +#define bM4_INTC_SEL117_INTSEL5 (*((volatile unsigned int*)(0x42A24614UL))) +#define bM4_INTC_SEL117_INTSEL6 (*((volatile unsigned int*)(0x42A24618UL))) +#define bM4_INTC_SEL117_INTSEL7 (*((volatile unsigned int*)(0x42A2461CUL))) +#define bM4_INTC_SEL117_INTSEL8 (*((volatile unsigned int*)(0x42A24620UL))) +#define bM4_INTC_SEL118_INTSEL0 (*((volatile unsigned int*)(0x42A24680UL))) +#define bM4_INTC_SEL118_INTSEL1 (*((volatile unsigned int*)(0x42A24684UL))) +#define bM4_INTC_SEL118_INTSEL2 (*((volatile unsigned int*)(0x42A24688UL))) +#define bM4_INTC_SEL118_INTSEL3 (*((volatile unsigned int*)(0x42A2468CUL))) +#define bM4_INTC_SEL118_INTSEL4 (*((volatile unsigned int*)(0x42A24690UL))) +#define bM4_INTC_SEL118_INTSEL5 (*((volatile unsigned int*)(0x42A24694UL))) +#define bM4_INTC_SEL118_INTSEL6 (*((volatile unsigned int*)(0x42A24698UL))) +#define bM4_INTC_SEL118_INTSEL7 (*((volatile unsigned int*)(0x42A2469CUL))) +#define bM4_INTC_SEL118_INTSEL8 (*((volatile unsigned int*)(0x42A246A0UL))) +#define bM4_INTC_SEL119_INTSEL0 (*((volatile unsigned int*)(0x42A24700UL))) +#define bM4_INTC_SEL119_INTSEL1 (*((volatile unsigned int*)(0x42A24704UL))) +#define bM4_INTC_SEL119_INTSEL2 (*((volatile unsigned int*)(0x42A24708UL))) +#define bM4_INTC_SEL119_INTSEL3 (*((volatile unsigned int*)(0x42A2470CUL))) +#define bM4_INTC_SEL119_INTSEL4 (*((volatile unsigned int*)(0x42A24710UL))) +#define bM4_INTC_SEL119_INTSEL5 (*((volatile unsigned int*)(0x42A24714UL))) +#define bM4_INTC_SEL119_INTSEL6 (*((volatile unsigned int*)(0x42A24718UL))) +#define bM4_INTC_SEL119_INTSEL7 (*((volatile unsigned int*)(0x42A2471CUL))) +#define bM4_INTC_SEL119_INTSEL8 (*((volatile unsigned int*)(0x42A24720UL))) +#define bM4_INTC_SEL120_INTSEL0 (*((volatile unsigned int*)(0x42A24780UL))) +#define bM4_INTC_SEL120_INTSEL1 (*((volatile unsigned int*)(0x42A24784UL))) +#define bM4_INTC_SEL120_INTSEL2 (*((volatile unsigned int*)(0x42A24788UL))) +#define bM4_INTC_SEL120_INTSEL3 (*((volatile unsigned int*)(0x42A2478CUL))) +#define bM4_INTC_SEL120_INTSEL4 (*((volatile unsigned int*)(0x42A24790UL))) +#define bM4_INTC_SEL120_INTSEL5 (*((volatile unsigned int*)(0x42A24794UL))) +#define bM4_INTC_SEL120_INTSEL6 (*((volatile unsigned int*)(0x42A24798UL))) +#define bM4_INTC_SEL120_INTSEL7 (*((volatile unsigned int*)(0x42A2479CUL))) +#define bM4_INTC_SEL120_INTSEL8 (*((volatile unsigned int*)(0x42A247A0UL))) +#define bM4_INTC_SEL121_INTSEL0 (*((volatile unsigned int*)(0x42A24800UL))) +#define bM4_INTC_SEL121_INTSEL1 (*((volatile unsigned int*)(0x42A24804UL))) +#define bM4_INTC_SEL121_INTSEL2 (*((volatile unsigned int*)(0x42A24808UL))) +#define bM4_INTC_SEL121_INTSEL3 (*((volatile unsigned int*)(0x42A2480CUL))) +#define bM4_INTC_SEL121_INTSEL4 (*((volatile unsigned int*)(0x42A24810UL))) +#define bM4_INTC_SEL121_INTSEL5 (*((volatile unsigned int*)(0x42A24814UL))) +#define bM4_INTC_SEL121_INTSEL6 (*((volatile unsigned int*)(0x42A24818UL))) +#define bM4_INTC_SEL121_INTSEL7 (*((volatile unsigned int*)(0x42A2481CUL))) +#define bM4_INTC_SEL121_INTSEL8 (*((volatile unsigned int*)(0x42A24820UL))) +#define bM4_INTC_SEL122_INTSEL0 (*((volatile unsigned int*)(0x42A24880UL))) +#define bM4_INTC_SEL122_INTSEL1 (*((volatile unsigned int*)(0x42A24884UL))) +#define bM4_INTC_SEL122_INTSEL2 (*((volatile unsigned int*)(0x42A24888UL))) +#define bM4_INTC_SEL122_INTSEL3 (*((volatile unsigned int*)(0x42A2488CUL))) +#define bM4_INTC_SEL122_INTSEL4 (*((volatile unsigned int*)(0x42A24890UL))) +#define bM4_INTC_SEL122_INTSEL5 (*((volatile unsigned int*)(0x42A24894UL))) +#define bM4_INTC_SEL122_INTSEL6 (*((volatile unsigned int*)(0x42A24898UL))) +#define bM4_INTC_SEL122_INTSEL7 (*((volatile unsigned int*)(0x42A2489CUL))) +#define bM4_INTC_SEL122_INTSEL8 (*((volatile unsigned int*)(0x42A248A0UL))) +#define bM4_INTC_SEL123_INTSEL0 (*((volatile unsigned int*)(0x42A24900UL))) +#define bM4_INTC_SEL123_INTSEL1 (*((volatile unsigned int*)(0x42A24904UL))) +#define bM4_INTC_SEL123_INTSEL2 (*((volatile unsigned int*)(0x42A24908UL))) +#define bM4_INTC_SEL123_INTSEL3 (*((volatile unsigned int*)(0x42A2490CUL))) +#define bM4_INTC_SEL123_INTSEL4 (*((volatile unsigned int*)(0x42A24910UL))) +#define bM4_INTC_SEL123_INTSEL5 (*((volatile unsigned int*)(0x42A24914UL))) +#define bM4_INTC_SEL123_INTSEL6 (*((volatile unsigned int*)(0x42A24918UL))) +#define bM4_INTC_SEL123_INTSEL7 (*((volatile unsigned int*)(0x42A2491CUL))) +#define bM4_INTC_SEL123_INTSEL8 (*((volatile unsigned int*)(0x42A24920UL))) +#define bM4_INTC_SEL124_INTSEL0 (*((volatile unsigned int*)(0x42A24980UL))) +#define bM4_INTC_SEL124_INTSEL1 (*((volatile unsigned int*)(0x42A24984UL))) +#define bM4_INTC_SEL124_INTSEL2 (*((volatile unsigned int*)(0x42A24988UL))) +#define bM4_INTC_SEL124_INTSEL3 (*((volatile unsigned int*)(0x42A2498CUL))) +#define bM4_INTC_SEL124_INTSEL4 (*((volatile unsigned int*)(0x42A24990UL))) +#define bM4_INTC_SEL124_INTSEL5 (*((volatile unsigned int*)(0x42A24994UL))) +#define bM4_INTC_SEL124_INTSEL6 (*((volatile unsigned int*)(0x42A24998UL))) +#define bM4_INTC_SEL124_INTSEL7 (*((volatile unsigned int*)(0x42A2499CUL))) +#define bM4_INTC_SEL124_INTSEL8 (*((volatile unsigned int*)(0x42A249A0UL))) +#define bM4_INTC_SEL125_INTSEL0 (*((volatile unsigned int*)(0x42A24A00UL))) +#define bM4_INTC_SEL125_INTSEL1 (*((volatile unsigned int*)(0x42A24A04UL))) +#define bM4_INTC_SEL125_INTSEL2 (*((volatile unsigned int*)(0x42A24A08UL))) +#define bM4_INTC_SEL125_INTSEL3 (*((volatile unsigned int*)(0x42A24A0CUL))) +#define bM4_INTC_SEL125_INTSEL4 (*((volatile unsigned int*)(0x42A24A10UL))) +#define bM4_INTC_SEL125_INTSEL5 (*((volatile unsigned int*)(0x42A24A14UL))) +#define bM4_INTC_SEL125_INTSEL6 (*((volatile unsigned int*)(0x42A24A18UL))) +#define bM4_INTC_SEL125_INTSEL7 (*((volatile unsigned int*)(0x42A24A1CUL))) +#define bM4_INTC_SEL125_INTSEL8 (*((volatile unsigned int*)(0x42A24A20UL))) +#define bM4_INTC_SEL126_INTSEL0 (*((volatile unsigned int*)(0x42A24A80UL))) +#define bM4_INTC_SEL126_INTSEL1 (*((volatile unsigned int*)(0x42A24A84UL))) +#define bM4_INTC_SEL126_INTSEL2 (*((volatile unsigned int*)(0x42A24A88UL))) +#define bM4_INTC_SEL126_INTSEL3 (*((volatile unsigned int*)(0x42A24A8CUL))) +#define bM4_INTC_SEL126_INTSEL4 (*((volatile unsigned int*)(0x42A24A90UL))) +#define bM4_INTC_SEL126_INTSEL5 (*((volatile unsigned int*)(0x42A24A94UL))) +#define bM4_INTC_SEL126_INTSEL6 (*((volatile unsigned int*)(0x42A24A98UL))) +#define bM4_INTC_SEL126_INTSEL7 (*((volatile unsigned int*)(0x42A24A9CUL))) +#define bM4_INTC_SEL126_INTSEL8 (*((volatile unsigned int*)(0x42A24AA0UL))) +#define bM4_INTC_SEL127_INTSEL0 (*((volatile unsigned int*)(0x42A24B00UL))) +#define bM4_INTC_SEL127_INTSEL1 (*((volatile unsigned int*)(0x42A24B04UL))) +#define bM4_INTC_SEL127_INTSEL2 (*((volatile unsigned int*)(0x42A24B08UL))) +#define bM4_INTC_SEL127_INTSEL3 (*((volatile unsigned int*)(0x42A24B0CUL))) +#define bM4_INTC_SEL127_INTSEL4 (*((volatile unsigned int*)(0x42A24B10UL))) +#define bM4_INTC_SEL127_INTSEL5 (*((volatile unsigned int*)(0x42A24B14UL))) +#define bM4_INTC_SEL127_INTSEL6 (*((volatile unsigned int*)(0x42A24B18UL))) +#define bM4_INTC_SEL127_INTSEL7 (*((volatile unsigned int*)(0x42A24B1CUL))) +#define bM4_INTC_SEL127_INTSEL8 (*((volatile unsigned int*)(0x42A24B20UL))) +#define bM4_INTC_VSSEL128_VSEL0 (*((volatile unsigned int*)(0x42A24B80UL))) +#define bM4_INTC_VSSEL128_VSEL1 (*((volatile unsigned int*)(0x42A24B84UL))) +#define bM4_INTC_VSSEL128_VSEL2 (*((volatile unsigned int*)(0x42A24B88UL))) +#define bM4_INTC_VSSEL128_VSEL3 (*((volatile unsigned int*)(0x42A24B8CUL))) +#define bM4_INTC_VSSEL128_VSEL4 (*((volatile unsigned int*)(0x42A24B90UL))) +#define bM4_INTC_VSSEL128_VSEL5 (*((volatile unsigned int*)(0x42A24B94UL))) +#define bM4_INTC_VSSEL128_VSEL6 (*((volatile unsigned int*)(0x42A24B98UL))) +#define bM4_INTC_VSSEL128_VSEL7 (*((volatile unsigned int*)(0x42A24B9CUL))) +#define bM4_INTC_VSSEL128_VSEL8 (*((volatile unsigned int*)(0x42A24BA0UL))) +#define bM4_INTC_VSSEL128_VSEL9 (*((volatile unsigned int*)(0x42A24BA4UL))) +#define bM4_INTC_VSSEL128_VSEL10 (*((volatile unsigned int*)(0x42A24BA8UL))) +#define bM4_INTC_VSSEL128_VSEL11 (*((volatile unsigned int*)(0x42A24BACUL))) +#define bM4_INTC_VSSEL128_VSEL12 (*((volatile unsigned int*)(0x42A24BB0UL))) +#define bM4_INTC_VSSEL128_VSEL13 (*((volatile unsigned int*)(0x42A24BB4UL))) +#define bM4_INTC_VSSEL128_VSEL14 (*((volatile unsigned int*)(0x42A24BB8UL))) +#define bM4_INTC_VSSEL128_VSEL15 (*((volatile unsigned int*)(0x42A24BBCUL))) +#define bM4_INTC_VSSEL128_VSEL16 (*((volatile unsigned int*)(0x42A24BC0UL))) +#define bM4_INTC_VSSEL128_VSEL17 (*((volatile unsigned int*)(0x42A24BC4UL))) +#define bM4_INTC_VSSEL128_VSEL18 (*((volatile unsigned int*)(0x42A24BC8UL))) +#define bM4_INTC_VSSEL128_VSEL19 (*((volatile unsigned int*)(0x42A24BCCUL))) +#define bM4_INTC_VSSEL128_VSEL20 (*((volatile unsigned int*)(0x42A24BD0UL))) +#define bM4_INTC_VSSEL128_VSEL21 (*((volatile unsigned int*)(0x42A24BD4UL))) +#define bM4_INTC_VSSEL128_VSEL22 (*((volatile unsigned int*)(0x42A24BD8UL))) +#define bM4_INTC_VSSEL128_VSEL23 (*((volatile unsigned int*)(0x42A24BDCUL))) +#define bM4_INTC_VSSEL128_VSEL24 (*((volatile unsigned int*)(0x42A24BE0UL))) +#define bM4_INTC_VSSEL128_VSEL25 (*((volatile unsigned int*)(0x42A24BE4UL))) +#define bM4_INTC_VSSEL128_VSEL26 (*((volatile unsigned int*)(0x42A24BE8UL))) +#define bM4_INTC_VSSEL128_VSEL27 (*((volatile unsigned int*)(0x42A24BECUL))) +#define bM4_INTC_VSSEL128_VSEL28 (*((volatile unsigned int*)(0x42A24BF0UL))) +#define bM4_INTC_VSSEL128_VSEL29 (*((volatile unsigned int*)(0x42A24BF4UL))) +#define bM4_INTC_VSSEL128_VSEL30 (*((volatile unsigned int*)(0x42A24BF8UL))) +#define bM4_INTC_VSSEL128_VSEL31 (*((volatile unsigned int*)(0x42A24BFCUL))) +#define bM4_INTC_VSSEL129_VSEL0 (*((volatile unsigned int*)(0x42A24C00UL))) +#define bM4_INTC_VSSEL129_VSEL1 (*((volatile unsigned int*)(0x42A24C04UL))) +#define bM4_INTC_VSSEL129_VSEL2 (*((volatile unsigned int*)(0x42A24C08UL))) +#define bM4_INTC_VSSEL129_VSEL3 (*((volatile unsigned int*)(0x42A24C0CUL))) +#define bM4_INTC_VSSEL129_VSEL4 (*((volatile unsigned int*)(0x42A24C10UL))) +#define bM4_INTC_VSSEL129_VSEL5 (*((volatile unsigned int*)(0x42A24C14UL))) +#define bM4_INTC_VSSEL129_VSEL6 (*((volatile unsigned int*)(0x42A24C18UL))) +#define bM4_INTC_VSSEL129_VSEL7 (*((volatile unsigned int*)(0x42A24C1CUL))) +#define bM4_INTC_VSSEL129_VSEL8 (*((volatile unsigned int*)(0x42A24C20UL))) +#define bM4_INTC_VSSEL129_VSEL9 (*((volatile unsigned int*)(0x42A24C24UL))) +#define bM4_INTC_VSSEL129_VSEL10 (*((volatile unsigned int*)(0x42A24C28UL))) +#define bM4_INTC_VSSEL129_VSEL11 (*((volatile unsigned int*)(0x42A24C2CUL))) +#define bM4_INTC_VSSEL129_VSEL12 (*((volatile unsigned int*)(0x42A24C30UL))) +#define bM4_INTC_VSSEL129_VSEL13 (*((volatile unsigned int*)(0x42A24C34UL))) +#define bM4_INTC_VSSEL129_VSEL14 (*((volatile unsigned int*)(0x42A24C38UL))) +#define bM4_INTC_VSSEL129_VSEL15 (*((volatile unsigned int*)(0x42A24C3CUL))) +#define bM4_INTC_VSSEL129_VSEL16 (*((volatile unsigned int*)(0x42A24C40UL))) +#define bM4_INTC_VSSEL129_VSEL17 (*((volatile unsigned int*)(0x42A24C44UL))) +#define bM4_INTC_VSSEL129_VSEL18 (*((volatile unsigned int*)(0x42A24C48UL))) +#define bM4_INTC_VSSEL129_VSEL19 (*((volatile unsigned int*)(0x42A24C4CUL))) +#define bM4_INTC_VSSEL129_VSEL20 (*((volatile unsigned int*)(0x42A24C50UL))) +#define bM4_INTC_VSSEL129_VSEL21 (*((volatile unsigned int*)(0x42A24C54UL))) +#define bM4_INTC_VSSEL129_VSEL22 (*((volatile unsigned int*)(0x42A24C58UL))) +#define bM4_INTC_VSSEL129_VSEL23 (*((volatile unsigned int*)(0x42A24C5CUL))) +#define bM4_INTC_VSSEL129_VSEL24 (*((volatile unsigned int*)(0x42A24C60UL))) +#define bM4_INTC_VSSEL129_VSEL25 (*((volatile unsigned int*)(0x42A24C64UL))) +#define bM4_INTC_VSSEL129_VSEL26 (*((volatile unsigned int*)(0x42A24C68UL))) +#define bM4_INTC_VSSEL129_VSEL27 (*((volatile unsigned int*)(0x42A24C6CUL))) +#define bM4_INTC_VSSEL129_VSEL28 (*((volatile unsigned int*)(0x42A24C70UL))) +#define bM4_INTC_VSSEL129_VSEL29 (*((volatile unsigned int*)(0x42A24C74UL))) +#define bM4_INTC_VSSEL129_VSEL30 (*((volatile unsigned int*)(0x42A24C78UL))) +#define bM4_INTC_VSSEL129_VSEL31 (*((volatile unsigned int*)(0x42A24C7CUL))) +#define bM4_INTC_VSSEL130_VSEL0 (*((volatile unsigned int*)(0x42A24C80UL))) +#define bM4_INTC_VSSEL130_VSEL1 (*((volatile unsigned int*)(0x42A24C84UL))) +#define bM4_INTC_VSSEL130_VSEL2 (*((volatile unsigned int*)(0x42A24C88UL))) +#define bM4_INTC_VSSEL130_VSEL3 (*((volatile unsigned int*)(0x42A24C8CUL))) +#define bM4_INTC_VSSEL130_VSEL4 (*((volatile unsigned int*)(0x42A24C90UL))) +#define bM4_INTC_VSSEL130_VSEL5 (*((volatile unsigned int*)(0x42A24C94UL))) +#define bM4_INTC_VSSEL130_VSEL6 (*((volatile unsigned int*)(0x42A24C98UL))) +#define bM4_INTC_VSSEL130_VSEL7 (*((volatile unsigned int*)(0x42A24C9CUL))) +#define bM4_INTC_VSSEL130_VSEL8 (*((volatile unsigned int*)(0x42A24CA0UL))) +#define bM4_INTC_VSSEL130_VSEL9 (*((volatile unsigned int*)(0x42A24CA4UL))) +#define bM4_INTC_VSSEL130_VSEL10 (*((volatile unsigned int*)(0x42A24CA8UL))) +#define bM4_INTC_VSSEL130_VSEL11 (*((volatile unsigned int*)(0x42A24CACUL))) +#define bM4_INTC_VSSEL130_VSEL12 (*((volatile unsigned int*)(0x42A24CB0UL))) +#define bM4_INTC_VSSEL130_VSEL13 (*((volatile unsigned int*)(0x42A24CB4UL))) +#define bM4_INTC_VSSEL130_VSEL14 (*((volatile unsigned int*)(0x42A24CB8UL))) +#define bM4_INTC_VSSEL130_VSEL15 (*((volatile unsigned int*)(0x42A24CBCUL))) +#define bM4_INTC_VSSEL130_VSEL16 (*((volatile unsigned int*)(0x42A24CC0UL))) +#define bM4_INTC_VSSEL130_VSEL17 (*((volatile unsigned int*)(0x42A24CC4UL))) +#define bM4_INTC_VSSEL130_VSEL18 (*((volatile unsigned int*)(0x42A24CC8UL))) +#define bM4_INTC_VSSEL130_VSEL19 (*((volatile unsigned int*)(0x42A24CCCUL))) +#define bM4_INTC_VSSEL130_VSEL20 (*((volatile unsigned int*)(0x42A24CD0UL))) +#define bM4_INTC_VSSEL130_VSEL21 (*((volatile unsigned int*)(0x42A24CD4UL))) +#define bM4_INTC_VSSEL130_VSEL22 (*((volatile unsigned int*)(0x42A24CD8UL))) +#define bM4_INTC_VSSEL130_VSEL23 (*((volatile unsigned int*)(0x42A24CDCUL))) +#define bM4_INTC_VSSEL130_VSEL24 (*((volatile unsigned int*)(0x42A24CE0UL))) +#define bM4_INTC_VSSEL130_VSEL25 (*((volatile unsigned int*)(0x42A24CE4UL))) +#define bM4_INTC_VSSEL130_VSEL26 (*((volatile unsigned int*)(0x42A24CE8UL))) +#define bM4_INTC_VSSEL130_VSEL27 (*((volatile unsigned int*)(0x42A24CECUL))) +#define bM4_INTC_VSSEL130_VSEL28 (*((volatile unsigned int*)(0x42A24CF0UL))) +#define bM4_INTC_VSSEL130_VSEL29 (*((volatile unsigned int*)(0x42A24CF4UL))) +#define bM4_INTC_VSSEL130_VSEL30 (*((volatile unsigned int*)(0x42A24CF8UL))) +#define bM4_INTC_VSSEL130_VSEL31 (*((volatile unsigned int*)(0x42A24CFCUL))) +#define bM4_INTC_VSSEL131_VSEL0 (*((volatile unsigned int*)(0x42A24D00UL))) +#define bM4_INTC_VSSEL131_VSEL1 (*((volatile unsigned int*)(0x42A24D04UL))) +#define bM4_INTC_VSSEL131_VSEL2 (*((volatile unsigned int*)(0x42A24D08UL))) +#define bM4_INTC_VSSEL131_VSEL3 (*((volatile unsigned int*)(0x42A24D0CUL))) +#define bM4_INTC_VSSEL131_VSEL4 (*((volatile unsigned int*)(0x42A24D10UL))) +#define bM4_INTC_VSSEL131_VSEL5 (*((volatile unsigned int*)(0x42A24D14UL))) +#define bM4_INTC_VSSEL131_VSEL6 (*((volatile unsigned int*)(0x42A24D18UL))) +#define bM4_INTC_VSSEL131_VSEL7 (*((volatile unsigned int*)(0x42A24D1CUL))) +#define bM4_INTC_VSSEL131_VSEL8 (*((volatile unsigned int*)(0x42A24D20UL))) +#define bM4_INTC_VSSEL131_VSEL9 (*((volatile unsigned int*)(0x42A24D24UL))) +#define bM4_INTC_VSSEL131_VSEL10 (*((volatile unsigned int*)(0x42A24D28UL))) +#define bM4_INTC_VSSEL131_VSEL11 (*((volatile unsigned int*)(0x42A24D2CUL))) +#define bM4_INTC_VSSEL131_VSEL12 (*((volatile unsigned int*)(0x42A24D30UL))) +#define bM4_INTC_VSSEL131_VSEL13 (*((volatile unsigned int*)(0x42A24D34UL))) +#define bM4_INTC_VSSEL131_VSEL14 (*((volatile unsigned int*)(0x42A24D38UL))) +#define bM4_INTC_VSSEL131_VSEL15 (*((volatile unsigned int*)(0x42A24D3CUL))) +#define bM4_INTC_VSSEL131_VSEL16 (*((volatile unsigned int*)(0x42A24D40UL))) +#define bM4_INTC_VSSEL131_VSEL17 (*((volatile unsigned int*)(0x42A24D44UL))) +#define bM4_INTC_VSSEL131_VSEL18 (*((volatile unsigned int*)(0x42A24D48UL))) +#define bM4_INTC_VSSEL131_VSEL19 (*((volatile unsigned int*)(0x42A24D4CUL))) +#define bM4_INTC_VSSEL131_VSEL20 (*((volatile unsigned int*)(0x42A24D50UL))) +#define bM4_INTC_VSSEL131_VSEL21 (*((volatile unsigned int*)(0x42A24D54UL))) +#define bM4_INTC_VSSEL131_VSEL22 (*((volatile unsigned int*)(0x42A24D58UL))) +#define bM4_INTC_VSSEL131_VSEL23 (*((volatile unsigned int*)(0x42A24D5CUL))) +#define bM4_INTC_VSSEL131_VSEL24 (*((volatile unsigned int*)(0x42A24D60UL))) +#define bM4_INTC_VSSEL131_VSEL25 (*((volatile unsigned int*)(0x42A24D64UL))) +#define bM4_INTC_VSSEL131_VSEL26 (*((volatile unsigned int*)(0x42A24D68UL))) +#define bM4_INTC_VSSEL131_VSEL27 (*((volatile unsigned int*)(0x42A24D6CUL))) +#define bM4_INTC_VSSEL131_VSEL28 (*((volatile unsigned int*)(0x42A24D70UL))) +#define bM4_INTC_VSSEL131_VSEL29 (*((volatile unsigned int*)(0x42A24D74UL))) +#define bM4_INTC_VSSEL131_VSEL30 (*((volatile unsigned int*)(0x42A24D78UL))) +#define bM4_INTC_VSSEL131_VSEL31 (*((volatile unsigned int*)(0x42A24D7CUL))) +#define bM4_INTC_VSSEL132_VSEL0 (*((volatile unsigned int*)(0x42A24D80UL))) +#define bM4_INTC_VSSEL132_VSEL1 (*((volatile unsigned int*)(0x42A24D84UL))) +#define bM4_INTC_VSSEL132_VSEL2 (*((volatile unsigned int*)(0x42A24D88UL))) +#define bM4_INTC_VSSEL132_VSEL3 (*((volatile unsigned int*)(0x42A24D8CUL))) +#define bM4_INTC_VSSEL132_VSEL4 (*((volatile unsigned int*)(0x42A24D90UL))) +#define bM4_INTC_VSSEL132_VSEL5 (*((volatile unsigned int*)(0x42A24D94UL))) +#define bM4_INTC_VSSEL132_VSEL6 (*((volatile unsigned int*)(0x42A24D98UL))) +#define bM4_INTC_VSSEL132_VSEL7 (*((volatile unsigned int*)(0x42A24D9CUL))) +#define bM4_INTC_VSSEL132_VSEL8 (*((volatile unsigned int*)(0x42A24DA0UL))) +#define bM4_INTC_VSSEL132_VSEL9 (*((volatile unsigned int*)(0x42A24DA4UL))) +#define bM4_INTC_VSSEL132_VSEL10 (*((volatile unsigned int*)(0x42A24DA8UL))) +#define bM4_INTC_VSSEL132_VSEL11 (*((volatile unsigned int*)(0x42A24DACUL))) +#define bM4_INTC_VSSEL132_VSEL12 (*((volatile unsigned int*)(0x42A24DB0UL))) +#define bM4_INTC_VSSEL132_VSEL13 (*((volatile unsigned int*)(0x42A24DB4UL))) +#define bM4_INTC_VSSEL132_VSEL14 (*((volatile unsigned int*)(0x42A24DB8UL))) +#define bM4_INTC_VSSEL132_VSEL15 (*((volatile unsigned int*)(0x42A24DBCUL))) +#define bM4_INTC_VSSEL132_VSEL16 (*((volatile unsigned int*)(0x42A24DC0UL))) +#define bM4_INTC_VSSEL132_VSEL17 (*((volatile unsigned int*)(0x42A24DC4UL))) +#define bM4_INTC_VSSEL132_VSEL18 (*((volatile unsigned int*)(0x42A24DC8UL))) +#define bM4_INTC_VSSEL132_VSEL19 (*((volatile unsigned int*)(0x42A24DCCUL))) +#define bM4_INTC_VSSEL132_VSEL20 (*((volatile unsigned int*)(0x42A24DD0UL))) +#define bM4_INTC_VSSEL132_VSEL21 (*((volatile unsigned int*)(0x42A24DD4UL))) +#define bM4_INTC_VSSEL132_VSEL22 (*((volatile unsigned int*)(0x42A24DD8UL))) +#define bM4_INTC_VSSEL132_VSEL23 (*((volatile unsigned int*)(0x42A24DDCUL))) +#define bM4_INTC_VSSEL132_VSEL24 (*((volatile unsigned int*)(0x42A24DE0UL))) +#define bM4_INTC_VSSEL132_VSEL25 (*((volatile unsigned int*)(0x42A24DE4UL))) +#define bM4_INTC_VSSEL132_VSEL26 (*((volatile unsigned int*)(0x42A24DE8UL))) +#define bM4_INTC_VSSEL132_VSEL27 (*((volatile unsigned int*)(0x42A24DECUL))) +#define bM4_INTC_VSSEL132_VSEL28 (*((volatile unsigned int*)(0x42A24DF0UL))) +#define bM4_INTC_VSSEL132_VSEL29 (*((volatile unsigned int*)(0x42A24DF4UL))) +#define bM4_INTC_VSSEL132_VSEL30 (*((volatile unsigned int*)(0x42A24DF8UL))) +#define bM4_INTC_VSSEL132_VSEL31 (*((volatile unsigned int*)(0x42A24DFCUL))) +#define bM4_INTC_VSSEL133_VSEL0 (*((volatile unsigned int*)(0x42A24E00UL))) +#define bM4_INTC_VSSEL133_VSEL1 (*((volatile unsigned int*)(0x42A24E04UL))) +#define bM4_INTC_VSSEL133_VSEL2 (*((volatile unsigned int*)(0x42A24E08UL))) +#define bM4_INTC_VSSEL133_VSEL3 (*((volatile unsigned int*)(0x42A24E0CUL))) +#define bM4_INTC_VSSEL133_VSEL4 (*((volatile unsigned int*)(0x42A24E10UL))) +#define bM4_INTC_VSSEL133_VSEL5 (*((volatile unsigned int*)(0x42A24E14UL))) +#define bM4_INTC_VSSEL133_VSEL6 (*((volatile unsigned int*)(0x42A24E18UL))) +#define bM4_INTC_VSSEL133_VSEL7 (*((volatile unsigned int*)(0x42A24E1CUL))) +#define bM4_INTC_VSSEL133_VSEL8 (*((volatile unsigned int*)(0x42A24E20UL))) +#define bM4_INTC_VSSEL133_VSEL9 (*((volatile unsigned int*)(0x42A24E24UL))) +#define bM4_INTC_VSSEL133_VSEL10 (*((volatile unsigned int*)(0x42A24E28UL))) +#define bM4_INTC_VSSEL133_VSEL11 (*((volatile unsigned int*)(0x42A24E2CUL))) +#define bM4_INTC_VSSEL133_VSEL12 (*((volatile unsigned int*)(0x42A24E30UL))) +#define bM4_INTC_VSSEL133_VSEL13 (*((volatile unsigned int*)(0x42A24E34UL))) +#define bM4_INTC_VSSEL133_VSEL14 (*((volatile unsigned int*)(0x42A24E38UL))) +#define bM4_INTC_VSSEL133_VSEL15 (*((volatile unsigned int*)(0x42A24E3CUL))) +#define bM4_INTC_VSSEL133_VSEL16 (*((volatile unsigned int*)(0x42A24E40UL))) +#define bM4_INTC_VSSEL133_VSEL17 (*((volatile unsigned int*)(0x42A24E44UL))) +#define bM4_INTC_VSSEL133_VSEL18 (*((volatile unsigned int*)(0x42A24E48UL))) +#define bM4_INTC_VSSEL133_VSEL19 (*((volatile unsigned int*)(0x42A24E4CUL))) +#define bM4_INTC_VSSEL133_VSEL20 (*((volatile unsigned int*)(0x42A24E50UL))) +#define bM4_INTC_VSSEL133_VSEL21 (*((volatile unsigned int*)(0x42A24E54UL))) +#define bM4_INTC_VSSEL133_VSEL22 (*((volatile unsigned int*)(0x42A24E58UL))) +#define bM4_INTC_VSSEL133_VSEL23 (*((volatile unsigned int*)(0x42A24E5CUL))) +#define bM4_INTC_VSSEL133_VSEL24 (*((volatile unsigned int*)(0x42A24E60UL))) +#define bM4_INTC_VSSEL133_VSEL25 (*((volatile unsigned int*)(0x42A24E64UL))) +#define bM4_INTC_VSSEL133_VSEL26 (*((volatile unsigned int*)(0x42A24E68UL))) +#define bM4_INTC_VSSEL133_VSEL27 (*((volatile unsigned int*)(0x42A24E6CUL))) +#define bM4_INTC_VSSEL133_VSEL28 (*((volatile unsigned int*)(0x42A24E70UL))) +#define bM4_INTC_VSSEL133_VSEL29 (*((volatile unsigned int*)(0x42A24E74UL))) +#define bM4_INTC_VSSEL133_VSEL30 (*((volatile unsigned int*)(0x42A24E78UL))) +#define bM4_INTC_VSSEL133_VSEL31 (*((volatile unsigned int*)(0x42A24E7CUL))) +#define bM4_INTC_VSSEL134_VSEL0 (*((volatile unsigned int*)(0x42A24E80UL))) +#define bM4_INTC_VSSEL134_VSEL1 (*((volatile unsigned int*)(0x42A24E84UL))) +#define bM4_INTC_VSSEL134_VSEL2 (*((volatile unsigned int*)(0x42A24E88UL))) +#define bM4_INTC_VSSEL134_VSEL3 (*((volatile unsigned int*)(0x42A24E8CUL))) +#define bM4_INTC_VSSEL134_VSEL4 (*((volatile unsigned int*)(0x42A24E90UL))) +#define bM4_INTC_VSSEL134_VSEL5 (*((volatile unsigned int*)(0x42A24E94UL))) +#define bM4_INTC_VSSEL134_VSEL6 (*((volatile unsigned int*)(0x42A24E98UL))) +#define bM4_INTC_VSSEL134_VSEL7 (*((volatile unsigned int*)(0x42A24E9CUL))) +#define bM4_INTC_VSSEL134_VSEL8 (*((volatile unsigned int*)(0x42A24EA0UL))) +#define bM4_INTC_VSSEL134_VSEL9 (*((volatile unsigned int*)(0x42A24EA4UL))) +#define bM4_INTC_VSSEL134_VSEL10 (*((volatile unsigned int*)(0x42A24EA8UL))) +#define bM4_INTC_VSSEL134_VSEL11 (*((volatile unsigned int*)(0x42A24EACUL))) +#define bM4_INTC_VSSEL134_VSEL12 (*((volatile unsigned int*)(0x42A24EB0UL))) +#define bM4_INTC_VSSEL134_VSEL13 (*((volatile unsigned int*)(0x42A24EB4UL))) +#define bM4_INTC_VSSEL134_VSEL14 (*((volatile unsigned int*)(0x42A24EB8UL))) +#define bM4_INTC_VSSEL134_VSEL15 (*((volatile unsigned int*)(0x42A24EBCUL))) +#define bM4_INTC_VSSEL134_VSEL16 (*((volatile unsigned int*)(0x42A24EC0UL))) +#define bM4_INTC_VSSEL134_VSEL17 (*((volatile unsigned int*)(0x42A24EC4UL))) +#define bM4_INTC_VSSEL134_VSEL18 (*((volatile unsigned int*)(0x42A24EC8UL))) +#define bM4_INTC_VSSEL134_VSEL19 (*((volatile unsigned int*)(0x42A24ECCUL))) +#define bM4_INTC_VSSEL134_VSEL20 (*((volatile unsigned int*)(0x42A24ED0UL))) +#define bM4_INTC_VSSEL134_VSEL21 (*((volatile unsigned int*)(0x42A24ED4UL))) +#define bM4_INTC_VSSEL134_VSEL22 (*((volatile unsigned int*)(0x42A24ED8UL))) +#define bM4_INTC_VSSEL134_VSEL23 (*((volatile unsigned int*)(0x42A24EDCUL))) +#define bM4_INTC_VSSEL134_VSEL24 (*((volatile unsigned int*)(0x42A24EE0UL))) +#define bM4_INTC_VSSEL134_VSEL25 (*((volatile unsigned int*)(0x42A24EE4UL))) +#define bM4_INTC_VSSEL134_VSEL26 (*((volatile unsigned int*)(0x42A24EE8UL))) +#define bM4_INTC_VSSEL134_VSEL27 (*((volatile unsigned int*)(0x42A24EECUL))) +#define bM4_INTC_VSSEL134_VSEL28 (*((volatile unsigned int*)(0x42A24EF0UL))) +#define bM4_INTC_VSSEL134_VSEL29 (*((volatile unsigned int*)(0x42A24EF4UL))) +#define bM4_INTC_VSSEL134_VSEL30 (*((volatile unsigned int*)(0x42A24EF8UL))) +#define bM4_INTC_VSSEL134_VSEL31 (*((volatile unsigned int*)(0x42A24EFCUL))) +#define bM4_INTC_VSSEL135_VSEL0 (*((volatile unsigned int*)(0x42A24F00UL))) +#define bM4_INTC_VSSEL135_VSEL1 (*((volatile unsigned int*)(0x42A24F04UL))) +#define bM4_INTC_VSSEL135_VSEL2 (*((volatile unsigned int*)(0x42A24F08UL))) +#define bM4_INTC_VSSEL135_VSEL3 (*((volatile unsigned int*)(0x42A24F0CUL))) +#define bM4_INTC_VSSEL135_VSEL4 (*((volatile unsigned int*)(0x42A24F10UL))) +#define bM4_INTC_VSSEL135_VSEL5 (*((volatile unsigned int*)(0x42A24F14UL))) +#define bM4_INTC_VSSEL135_VSEL6 (*((volatile unsigned int*)(0x42A24F18UL))) +#define bM4_INTC_VSSEL135_VSEL7 (*((volatile unsigned int*)(0x42A24F1CUL))) +#define bM4_INTC_VSSEL135_VSEL8 (*((volatile unsigned int*)(0x42A24F20UL))) +#define bM4_INTC_VSSEL135_VSEL9 (*((volatile unsigned int*)(0x42A24F24UL))) +#define bM4_INTC_VSSEL135_VSEL10 (*((volatile unsigned int*)(0x42A24F28UL))) +#define bM4_INTC_VSSEL135_VSEL11 (*((volatile unsigned int*)(0x42A24F2CUL))) +#define bM4_INTC_VSSEL135_VSEL12 (*((volatile unsigned int*)(0x42A24F30UL))) +#define bM4_INTC_VSSEL135_VSEL13 (*((volatile unsigned int*)(0x42A24F34UL))) +#define bM4_INTC_VSSEL135_VSEL14 (*((volatile unsigned int*)(0x42A24F38UL))) +#define bM4_INTC_VSSEL135_VSEL15 (*((volatile unsigned int*)(0x42A24F3CUL))) +#define bM4_INTC_VSSEL135_VSEL16 (*((volatile unsigned int*)(0x42A24F40UL))) +#define bM4_INTC_VSSEL135_VSEL17 (*((volatile unsigned int*)(0x42A24F44UL))) +#define bM4_INTC_VSSEL135_VSEL18 (*((volatile unsigned int*)(0x42A24F48UL))) +#define bM4_INTC_VSSEL135_VSEL19 (*((volatile unsigned int*)(0x42A24F4CUL))) +#define bM4_INTC_VSSEL135_VSEL20 (*((volatile unsigned int*)(0x42A24F50UL))) +#define bM4_INTC_VSSEL135_VSEL21 (*((volatile unsigned int*)(0x42A24F54UL))) +#define bM4_INTC_VSSEL135_VSEL22 (*((volatile unsigned int*)(0x42A24F58UL))) +#define bM4_INTC_VSSEL135_VSEL23 (*((volatile unsigned int*)(0x42A24F5CUL))) +#define bM4_INTC_VSSEL135_VSEL24 (*((volatile unsigned int*)(0x42A24F60UL))) +#define bM4_INTC_VSSEL135_VSEL25 (*((volatile unsigned int*)(0x42A24F64UL))) +#define bM4_INTC_VSSEL135_VSEL26 (*((volatile unsigned int*)(0x42A24F68UL))) +#define bM4_INTC_VSSEL135_VSEL27 (*((volatile unsigned int*)(0x42A24F6CUL))) +#define bM4_INTC_VSSEL135_VSEL28 (*((volatile unsigned int*)(0x42A24F70UL))) +#define bM4_INTC_VSSEL135_VSEL29 (*((volatile unsigned int*)(0x42A24F74UL))) +#define bM4_INTC_VSSEL135_VSEL30 (*((volatile unsigned int*)(0x42A24F78UL))) +#define bM4_INTC_VSSEL135_VSEL31 (*((volatile unsigned int*)(0x42A24F7CUL))) +#define bM4_INTC_VSSEL136_VSEL0 (*((volatile unsigned int*)(0x42A24F80UL))) +#define bM4_INTC_VSSEL136_VSEL1 (*((volatile unsigned int*)(0x42A24F84UL))) +#define bM4_INTC_VSSEL136_VSEL2 (*((volatile unsigned int*)(0x42A24F88UL))) +#define bM4_INTC_VSSEL136_VSEL3 (*((volatile unsigned int*)(0x42A24F8CUL))) +#define bM4_INTC_VSSEL136_VSEL4 (*((volatile unsigned int*)(0x42A24F90UL))) +#define bM4_INTC_VSSEL136_VSEL5 (*((volatile unsigned int*)(0x42A24F94UL))) +#define bM4_INTC_VSSEL136_VSEL6 (*((volatile unsigned int*)(0x42A24F98UL))) +#define bM4_INTC_VSSEL136_VSEL7 (*((volatile unsigned int*)(0x42A24F9CUL))) +#define bM4_INTC_VSSEL136_VSEL8 (*((volatile unsigned int*)(0x42A24FA0UL))) +#define bM4_INTC_VSSEL136_VSEL9 (*((volatile unsigned int*)(0x42A24FA4UL))) +#define bM4_INTC_VSSEL136_VSEL10 (*((volatile unsigned int*)(0x42A24FA8UL))) +#define bM4_INTC_VSSEL136_VSEL11 (*((volatile unsigned int*)(0x42A24FACUL))) +#define bM4_INTC_VSSEL136_VSEL12 (*((volatile unsigned int*)(0x42A24FB0UL))) +#define bM4_INTC_VSSEL136_VSEL13 (*((volatile unsigned int*)(0x42A24FB4UL))) +#define bM4_INTC_VSSEL136_VSEL14 (*((volatile unsigned int*)(0x42A24FB8UL))) +#define bM4_INTC_VSSEL136_VSEL15 (*((volatile unsigned int*)(0x42A24FBCUL))) +#define bM4_INTC_VSSEL136_VSEL16 (*((volatile unsigned int*)(0x42A24FC0UL))) +#define bM4_INTC_VSSEL136_VSEL17 (*((volatile unsigned int*)(0x42A24FC4UL))) +#define bM4_INTC_VSSEL136_VSEL18 (*((volatile unsigned int*)(0x42A24FC8UL))) +#define bM4_INTC_VSSEL136_VSEL19 (*((volatile unsigned int*)(0x42A24FCCUL))) +#define bM4_INTC_VSSEL136_VSEL20 (*((volatile unsigned int*)(0x42A24FD0UL))) +#define bM4_INTC_VSSEL136_VSEL21 (*((volatile unsigned int*)(0x42A24FD4UL))) +#define bM4_INTC_VSSEL136_VSEL22 (*((volatile unsigned int*)(0x42A24FD8UL))) +#define bM4_INTC_VSSEL136_VSEL23 (*((volatile unsigned int*)(0x42A24FDCUL))) +#define bM4_INTC_VSSEL136_VSEL24 (*((volatile unsigned int*)(0x42A24FE0UL))) +#define bM4_INTC_VSSEL136_VSEL25 (*((volatile unsigned int*)(0x42A24FE4UL))) +#define bM4_INTC_VSSEL136_VSEL26 (*((volatile unsigned int*)(0x42A24FE8UL))) +#define bM4_INTC_VSSEL136_VSEL27 (*((volatile unsigned int*)(0x42A24FECUL))) +#define bM4_INTC_VSSEL136_VSEL28 (*((volatile unsigned int*)(0x42A24FF0UL))) +#define bM4_INTC_VSSEL136_VSEL29 (*((volatile unsigned int*)(0x42A24FF4UL))) +#define bM4_INTC_VSSEL136_VSEL30 (*((volatile unsigned int*)(0x42A24FF8UL))) +#define bM4_INTC_VSSEL136_VSEL31 (*((volatile unsigned int*)(0x42A24FFCUL))) +#define bM4_INTC_VSSEL137_VSEL0 (*((volatile unsigned int*)(0x42A25000UL))) +#define bM4_INTC_VSSEL137_VSEL1 (*((volatile unsigned int*)(0x42A25004UL))) +#define bM4_INTC_VSSEL137_VSEL2 (*((volatile unsigned int*)(0x42A25008UL))) +#define bM4_INTC_VSSEL137_VSEL3 (*((volatile unsigned int*)(0x42A2500CUL))) +#define bM4_INTC_VSSEL137_VSEL4 (*((volatile unsigned int*)(0x42A25010UL))) +#define bM4_INTC_VSSEL137_VSEL5 (*((volatile unsigned int*)(0x42A25014UL))) +#define bM4_INTC_VSSEL137_VSEL6 (*((volatile unsigned int*)(0x42A25018UL))) +#define bM4_INTC_VSSEL137_VSEL7 (*((volatile unsigned int*)(0x42A2501CUL))) +#define bM4_INTC_VSSEL137_VSEL8 (*((volatile unsigned int*)(0x42A25020UL))) +#define bM4_INTC_VSSEL137_VSEL9 (*((volatile unsigned int*)(0x42A25024UL))) +#define bM4_INTC_VSSEL137_VSEL10 (*((volatile unsigned int*)(0x42A25028UL))) +#define bM4_INTC_VSSEL137_VSEL11 (*((volatile unsigned int*)(0x42A2502CUL))) +#define bM4_INTC_VSSEL137_VSEL12 (*((volatile unsigned int*)(0x42A25030UL))) +#define bM4_INTC_VSSEL137_VSEL13 (*((volatile unsigned int*)(0x42A25034UL))) +#define bM4_INTC_VSSEL137_VSEL14 (*((volatile unsigned int*)(0x42A25038UL))) +#define bM4_INTC_VSSEL137_VSEL15 (*((volatile unsigned int*)(0x42A2503CUL))) +#define bM4_INTC_VSSEL137_VSEL16 (*((volatile unsigned int*)(0x42A25040UL))) +#define bM4_INTC_VSSEL137_VSEL17 (*((volatile unsigned int*)(0x42A25044UL))) +#define bM4_INTC_VSSEL137_VSEL18 (*((volatile unsigned int*)(0x42A25048UL))) +#define bM4_INTC_VSSEL137_VSEL19 (*((volatile unsigned int*)(0x42A2504CUL))) +#define bM4_INTC_VSSEL137_VSEL20 (*((volatile unsigned int*)(0x42A25050UL))) +#define bM4_INTC_VSSEL137_VSEL21 (*((volatile unsigned int*)(0x42A25054UL))) +#define bM4_INTC_VSSEL137_VSEL22 (*((volatile unsigned int*)(0x42A25058UL))) +#define bM4_INTC_VSSEL137_VSEL23 (*((volatile unsigned int*)(0x42A2505CUL))) +#define bM4_INTC_VSSEL137_VSEL24 (*((volatile unsigned int*)(0x42A25060UL))) +#define bM4_INTC_VSSEL137_VSEL25 (*((volatile unsigned int*)(0x42A25064UL))) +#define bM4_INTC_VSSEL137_VSEL26 (*((volatile unsigned int*)(0x42A25068UL))) +#define bM4_INTC_VSSEL137_VSEL27 (*((volatile unsigned int*)(0x42A2506CUL))) +#define bM4_INTC_VSSEL137_VSEL28 (*((volatile unsigned int*)(0x42A25070UL))) +#define bM4_INTC_VSSEL137_VSEL29 (*((volatile unsigned int*)(0x42A25074UL))) +#define bM4_INTC_VSSEL137_VSEL30 (*((volatile unsigned int*)(0x42A25078UL))) +#define bM4_INTC_VSSEL137_VSEL31 (*((volatile unsigned int*)(0x42A2507CUL))) +#define bM4_INTC_VSSEL138_VSEL0 (*((volatile unsigned int*)(0x42A25080UL))) +#define bM4_INTC_VSSEL138_VSEL1 (*((volatile unsigned int*)(0x42A25084UL))) +#define bM4_INTC_VSSEL138_VSEL2 (*((volatile unsigned int*)(0x42A25088UL))) +#define bM4_INTC_VSSEL138_VSEL3 (*((volatile unsigned int*)(0x42A2508CUL))) +#define bM4_INTC_VSSEL138_VSEL4 (*((volatile unsigned int*)(0x42A25090UL))) +#define bM4_INTC_VSSEL138_VSEL5 (*((volatile unsigned int*)(0x42A25094UL))) +#define bM4_INTC_VSSEL138_VSEL6 (*((volatile unsigned int*)(0x42A25098UL))) +#define bM4_INTC_VSSEL138_VSEL7 (*((volatile unsigned int*)(0x42A2509CUL))) +#define bM4_INTC_VSSEL138_VSEL8 (*((volatile unsigned int*)(0x42A250A0UL))) +#define bM4_INTC_VSSEL138_VSEL9 (*((volatile unsigned int*)(0x42A250A4UL))) +#define bM4_INTC_VSSEL138_VSEL10 (*((volatile unsigned int*)(0x42A250A8UL))) +#define bM4_INTC_VSSEL138_VSEL11 (*((volatile unsigned int*)(0x42A250ACUL))) +#define bM4_INTC_VSSEL138_VSEL12 (*((volatile unsigned int*)(0x42A250B0UL))) +#define bM4_INTC_VSSEL138_VSEL13 (*((volatile unsigned int*)(0x42A250B4UL))) +#define bM4_INTC_VSSEL138_VSEL14 (*((volatile unsigned int*)(0x42A250B8UL))) +#define bM4_INTC_VSSEL138_VSEL15 (*((volatile unsigned int*)(0x42A250BCUL))) +#define bM4_INTC_VSSEL138_VSEL16 (*((volatile unsigned int*)(0x42A250C0UL))) +#define bM4_INTC_VSSEL138_VSEL17 (*((volatile unsigned int*)(0x42A250C4UL))) +#define bM4_INTC_VSSEL138_VSEL18 (*((volatile unsigned int*)(0x42A250C8UL))) +#define bM4_INTC_VSSEL138_VSEL19 (*((volatile unsigned int*)(0x42A250CCUL))) +#define bM4_INTC_VSSEL138_VSEL20 (*((volatile unsigned int*)(0x42A250D0UL))) +#define bM4_INTC_VSSEL138_VSEL21 (*((volatile unsigned int*)(0x42A250D4UL))) +#define bM4_INTC_VSSEL138_VSEL22 (*((volatile unsigned int*)(0x42A250D8UL))) +#define bM4_INTC_VSSEL138_VSEL23 (*((volatile unsigned int*)(0x42A250DCUL))) +#define bM4_INTC_VSSEL138_VSEL24 (*((volatile unsigned int*)(0x42A250E0UL))) +#define bM4_INTC_VSSEL138_VSEL25 (*((volatile unsigned int*)(0x42A250E4UL))) +#define bM4_INTC_VSSEL138_VSEL26 (*((volatile unsigned int*)(0x42A250E8UL))) +#define bM4_INTC_VSSEL138_VSEL27 (*((volatile unsigned int*)(0x42A250ECUL))) +#define bM4_INTC_VSSEL138_VSEL28 (*((volatile unsigned int*)(0x42A250F0UL))) +#define bM4_INTC_VSSEL138_VSEL29 (*((volatile unsigned int*)(0x42A250F4UL))) +#define bM4_INTC_VSSEL138_VSEL30 (*((volatile unsigned int*)(0x42A250F8UL))) +#define bM4_INTC_VSSEL138_VSEL31 (*((volatile unsigned int*)(0x42A250FCUL))) +#define bM4_INTC_VSSEL139_VSEL0 (*((volatile unsigned int*)(0x42A25100UL))) +#define bM4_INTC_VSSEL139_VSEL1 (*((volatile unsigned int*)(0x42A25104UL))) +#define bM4_INTC_VSSEL139_VSEL2 (*((volatile unsigned int*)(0x42A25108UL))) +#define bM4_INTC_VSSEL139_VSEL3 (*((volatile unsigned int*)(0x42A2510CUL))) +#define bM4_INTC_VSSEL139_VSEL4 (*((volatile unsigned int*)(0x42A25110UL))) +#define bM4_INTC_VSSEL139_VSEL5 (*((volatile unsigned int*)(0x42A25114UL))) +#define bM4_INTC_VSSEL139_VSEL6 (*((volatile unsigned int*)(0x42A25118UL))) +#define bM4_INTC_VSSEL139_VSEL7 (*((volatile unsigned int*)(0x42A2511CUL))) +#define bM4_INTC_VSSEL139_VSEL8 (*((volatile unsigned int*)(0x42A25120UL))) +#define bM4_INTC_VSSEL139_VSEL9 (*((volatile unsigned int*)(0x42A25124UL))) +#define bM4_INTC_VSSEL139_VSEL10 (*((volatile unsigned int*)(0x42A25128UL))) +#define bM4_INTC_VSSEL139_VSEL11 (*((volatile unsigned int*)(0x42A2512CUL))) +#define bM4_INTC_VSSEL139_VSEL12 (*((volatile unsigned int*)(0x42A25130UL))) +#define bM4_INTC_VSSEL139_VSEL13 (*((volatile unsigned int*)(0x42A25134UL))) +#define bM4_INTC_VSSEL139_VSEL14 (*((volatile unsigned int*)(0x42A25138UL))) +#define bM4_INTC_VSSEL139_VSEL15 (*((volatile unsigned int*)(0x42A2513CUL))) +#define bM4_INTC_VSSEL139_VSEL16 (*((volatile unsigned int*)(0x42A25140UL))) +#define bM4_INTC_VSSEL139_VSEL17 (*((volatile unsigned int*)(0x42A25144UL))) +#define bM4_INTC_VSSEL139_VSEL18 (*((volatile unsigned int*)(0x42A25148UL))) +#define bM4_INTC_VSSEL139_VSEL19 (*((volatile unsigned int*)(0x42A2514CUL))) +#define bM4_INTC_VSSEL139_VSEL20 (*((volatile unsigned int*)(0x42A25150UL))) +#define bM4_INTC_VSSEL139_VSEL21 (*((volatile unsigned int*)(0x42A25154UL))) +#define bM4_INTC_VSSEL139_VSEL22 (*((volatile unsigned int*)(0x42A25158UL))) +#define bM4_INTC_VSSEL139_VSEL23 (*((volatile unsigned int*)(0x42A2515CUL))) +#define bM4_INTC_VSSEL139_VSEL24 (*((volatile unsigned int*)(0x42A25160UL))) +#define bM4_INTC_VSSEL139_VSEL25 (*((volatile unsigned int*)(0x42A25164UL))) +#define bM4_INTC_VSSEL139_VSEL26 (*((volatile unsigned int*)(0x42A25168UL))) +#define bM4_INTC_VSSEL139_VSEL27 (*((volatile unsigned int*)(0x42A2516CUL))) +#define bM4_INTC_VSSEL139_VSEL28 (*((volatile unsigned int*)(0x42A25170UL))) +#define bM4_INTC_VSSEL139_VSEL29 (*((volatile unsigned int*)(0x42A25174UL))) +#define bM4_INTC_VSSEL139_VSEL30 (*((volatile unsigned int*)(0x42A25178UL))) +#define bM4_INTC_VSSEL139_VSEL31 (*((volatile unsigned int*)(0x42A2517CUL))) +#define bM4_INTC_VSSEL140_VSEL0 (*((volatile unsigned int*)(0x42A25180UL))) +#define bM4_INTC_VSSEL140_VSEL1 (*((volatile unsigned int*)(0x42A25184UL))) +#define bM4_INTC_VSSEL140_VSEL2 (*((volatile unsigned int*)(0x42A25188UL))) +#define bM4_INTC_VSSEL140_VSEL3 (*((volatile unsigned int*)(0x42A2518CUL))) +#define bM4_INTC_VSSEL140_VSEL4 (*((volatile unsigned int*)(0x42A25190UL))) +#define bM4_INTC_VSSEL140_VSEL5 (*((volatile unsigned int*)(0x42A25194UL))) +#define bM4_INTC_VSSEL140_VSEL6 (*((volatile unsigned int*)(0x42A25198UL))) +#define bM4_INTC_VSSEL140_VSEL7 (*((volatile unsigned int*)(0x42A2519CUL))) +#define bM4_INTC_VSSEL140_VSEL8 (*((volatile unsigned int*)(0x42A251A0UL))) +#define bM4_INTC_VSSEL140_VSEL9 (*((volatile unsigned int*)(0x42A251A4UL))) +#define bM4_INTC_VSSEL140_VSEL10 (*((volatile unsigned int*)(0x42A251A8UL))) +#define bM4_INTC_VSSEL140_VSEL11 (*((volatile unsigned int*)(0x42A251ACUL))) +#define bM4_INTC_VSSEL140_VSEL12 (*((volatile unsigned int*)(0x42A251B0UL))) +#define bM4_INTC_VSSEL140_VSEL13 (*((volatile unsigned int*)(0x42A251B4UL))) +#define bM4_INTC_VSSEL140_VSEL14 (*((volatile unsigned int*)(0x42A251B8UL))) +#define bM4_INTC_VSSEL140_VSEL15 (*((volatile unsigned int*)(0x42A251BCUL))) +#define bM4_INTC_VSSEL140_VSEL16 (*((volatile unsigned int*)(0x42A251C0UL))) +#define bM4_INTC_VSSEL140_VSEL17 (*((volatile unsigned int*)(0x42A251C4UL))) +#define bM4_INTC_VSSEL140_VSEL18 (*((volatile unsigned int*)(0x42A251C8UL))) +#define bM4_INTC_VSSEL140_VSEL19 (*((volatile unsigned int*)(0x42A251CCUL))) +#define bM4_INTC_VSSEL140_VSEL20 (*((volatile unsigned int*)(0x42A251D0UL))) +#define bM4_INTC_VSSEL140_VSEL21 (*((volatile unsigned int*)(0x42A251D4UL))) +#define bM4_INTC_VSSEL140_VSEL22 (*((volatile unsigned int*)(0x42A251D8UL))) +#define bM4_INTC_VSSEL140_VSEL23 (*((volatile unsigned int*)(0x42A251DCUL))) +#define bM4_INTC_VSSEL140_VSEL24 (*((volatile unsigned int*)(0x42A251E0UL))) +#define bM4_INTC_VSSEL140_VSEL25 (*((volatile unsigned int*)(0x42A251E4UL))) +#define bM4_INTC_VSSEL140_VSEL26 (*((volatile unsigned int*)(0x42A251E8UL))) +#define bM4_INTC_VSSEL140_VSEL27 (*((volatile unsigned int*)(0x42A251ECUL))) +#define bM4_INTC_VSSEL140_VSEL28 (*((volatile unsigned int*)(0x42A251F0UL))) +#define bM4_INTC_VSSEL140_VSEL29 (*((volatile unsigned int*)(0x42A251F4UL))) +#define bM4_INTC_VSSEL140_VSEL30 (*((volatile unsigned int*)(0x42A251F8UL))) +#define bM4_INTC_VSSEL140_VSEL31 (*((volatile unsigned int*)(0x42A251FCUL))) +#define bM4_INTC_VSSEL141_VSEL0 (*((volatile unsigned int*)(0x42A25200UL))) +#define bM4_INTC_VSSEL141_VSEL1 (*((volatile unsigned int*)(0x42A25204UL))) +#define bM4_INTC_VSSEL141_VSEL2 (*((volatile unsigned int*)(0x42A25208UL))) +#define bM4_INTC_VSSEL141_VSEL3 (*((volatile unsigned int*)(0x42A2520CUL))) +#define bM4_INTC_VSSEL141_VSEL4 (*((volatile unsigned int*)(0x42A25210UL))) +#define bM4_INTC_VSSEL141_VSEL5 (*((volatile unsigned int*)(0x42A25214UL))) +#define bM4_INTC_VSSEL141_VSEL6 (*((volatile unsigned int*)(0x42A25218UL))) +#define bM4_INTC_VSSEL141_VSEL7 (*((volatile unsigned int*)(0x42A2521CUL))) +#define bM4_INTC_VSSEL141_VSEL8 (*((volatile unsigned int*)(0x42A25220UL))) +#define bM4_INTC_VSSEL141_VSEL9 (*((volatile unsigned int*)(0x42A25224UL))) +#define bM4_INTC_VSSEL141_VSEL10 (*((volatile unsigned int*)(0x42A25228UL))) +#define bM4_INTC_VSSEL141_VSEL11 (*((volatile unsigned int*)(0x42A2522CUL))) +#define bM4_INTC_VSSEL141_VSEL12 (*((volatile unsigned int*)(0x42A25230UL))) +#define bM4_INTC_VSSEL141_VSEL13 (*((volatile unsigned int*)(0x42A25234UL))) +#define bM4_INTC_VSSEL141_VSEL14 (*((volatile unsigned int*)(0x42A25238UL))) +#define bM4_INTC_VSSEL141_VSEL15 (*((volatile unsigned int*)(0x42A2523CUL))) +#define bM4_INTC_VSSEL141_VSEL16 (*((volatile unsigned int*)(0x42A25240UL))) +#define bM4_INTC_VSSEL141_VSEL17 (*((volatile unsigned int*)(0x42A25244UL))) +#define bM4_INTC_VSSEL141_VSEL18 (*((volatile unsigned int*)(0x42A25248UL))) +#define bM4_INTC_VSSEL141_VSEL19 (*((volatile unsigned int*)(0x42A2524CUL))) +#define bM4_INTC_VSSEL141_VSEL20 (*((volatile unsigned int*)(0x42A25250UL))) +#define bM4_INTC_VSSEL141_VSEL21 (*((volatile unsigned int*)(0x42A25254UL))) +#define bM4_INTC_VSSEL141_VSEL22 (*((volatile unsigned int*)(0x42A25258UL))) +#define bM4_INTC_VSSEL141_VSEL23 (*((volatile unsigned int*)(0x42A2525CUL))) +#define bM4_INTC_VSSEL141_VSEL24 (*((volatile unsigned int*)(0x42A25260UL))) +#define bM4_INTC_VSSEL141_VSEL25 (*((volatile unsigned int*)(0x42A25264UL))) +#define bM4_INTC_VSSEL141_VSEL26 (*((volatile unsigned int*)(0x42A25268UL))) +#define bM4_INTC_VSSEL141_VSEL27 (*((volatile unsigned int*)(0x42A2526CUL))) +#define bM4_INTC_VSSEL141_VSEL28 (*((volatile unsigned int*)(0x42A25270UL))) +#define bM4_INTC_VSSEL141_VSEL29 (*((volatile unsigned int*)(0x42A25274UL))) +#define bM4_INTC_VSSEL141_VSEL30 (*((volatile unsigned int*)(0x42A25278UL))) +#define bM4_INTC_VSSEL141_VSEL31 (*((volatile unsigned int*)(0x42A2527CUL))) +#define bM4_INTC_VSSEL142_VSEL0 (*((volatile unsigned int*)(0x42A25280UL))) +#define bM4_INTC_VSSEL142_VSEL1 (*((volatile unsigned int*)(0x42A25284UL))) +#define bM4_INTC_VSSEL142_VSEL2 (*((volatile unsigned int*)(0x42A25288UL))) +#define bM4_INTC_VSSEL142_VSEL3 (*((volatile unsigned int*)(0x42A2528CUL))) +#define bM4_INTC_VSSEL142_VSEL4 (*((volatile unsigned int*)(0x42A25290UL))) +#define bM4_INTC_VSSEL142_VSEL5 (*((volatile unsigned int*)(0x42A25294UL))) +#define bM4_INTC_VSSEL142_VSEL6 (*((volatile unsigned int*)(0x42A25298UL))) +#define bM4_INTC_VSSEL142_VSEL7 (*((volatile unsigned int*)(0x42A2529CUL))) +#define bM4_INTC_VSSEL142_VSEL8 (*((volatile unsigned int*)(0x42A252A0UL))) +#define bM4_INTC_VSSEL142_VSEL9 (*((volatile unsigned int*)(0x42A252A4UL))) +#define bM4_INTC_VSSEL142_VSEL10 (*((volatile unsigned int*)(0x42A252A8UL))) +#define bM4_INTC_VSSEL142_VSEL11 (*((volatile unsigned int*)(0x42A252ACUL))) +#define bM4_INTC_VSSEL142_VSEL12 (*((volatile unsigned int*)(0x42A252B0UL))) +#define bM4_INTC_VSSEL142_VSEL13 (*((volatile unsigned int*)(0x42A252B4UL))) +#define bM4_INTC_VSSEL142_VSEL14 (*((volatile unsigned int*)(0x42A252B8UL))) +#define bM4_INTC_VSSEL142_VSEL15 (*((volatile unsigned int*)(0x42A252BCUL))) +#define bM4_INTC_VSSEL142_VSEL16 (*((volatile unsigned int*)(0x42A252C0UL))) +#define bM4_INTC_VSSEL142_VSEL17 (*((volatile unsigned int*)(0x42A252C4UL))) +#define bM4_INTC_VSSEL142_VSEL18 (*((volatile unsigned int*)(0x42A252C8UL))) +#define bM4_INTC_VSSEL142_VSEL19 (*((volatile unsigned int*)(0x42A252CCUL))) +#define bM4_INTC_VSSEL142_VSEL20 (*((volatile unsigned int*)(0x42A252D0UL))) +#define bM4_INTC_VSSEL142_VSEL21 (*((volatile unsigned int*)(0x42A252D4UL))) +#define bM4_INTC_VSSEL142_VSEL22 (*((volatile unsigned int*)(0x42A252D8UL))) +#define bM4_INTC_VSSEL142_VSEL23 (*((volatile unsigned int*)(0x42A252DCUL))) +#define bM4_INTC_VSSEL142_VSEL24 (*((volatile unsigned int*)(0x42A252E0UL))) +#define bM4_INTC_VSSEL142_VSEL25 (*((volatile unsigned int*)(0x42A252E4UL))) +#define bM4_INTC_VSSEL142_VSEL26 (*((volatile unsigned int*)(0x42A252E8UL))) +#define bM4_INTC_VSSEL142_VSEL27 (*((volatile unsigned int*)(0x42A252ECUL))) +#define bM4_INTC_VSSEL142_VSEL28 (*((volatile unsigned int*)(0x42A252F0UL))) +#define bM4_INTC_VSSEL142_VSEL29 (*((volatile unsigned int*)(0x42A252F4UL))) +#define bM4_INTC_VSSEL142_VSEL30 (*((volatile unsigned int*)(0x42A252F8UL))) +#define bM4_INTC_VSSEL142_VSEL31 (*((volatile unsigned int*)(0x42A252FCUL))) +#define bM4_INTC_VSSEL143_VSEL0 (*((volatile unsigned int*)(0x42A25300UL))) +#define bM4_INTC_VSSEL143_VSEL1 (*((volatile unsigned int*)(0x42A25304UL))) +#define bM4_INTC_VSSEL143_VSEL2 (*((volatile unsigned int*)(0x42A25308UL))) +#define bM4_INTC_VSSEL143_VSEL3 (*((volatile unsigned int*)(0x42A2530CUL))) +#define bM4_INTC_VSSEL143_VSEL4 (*((volatile unsigned int*)(0x42A25310UL))) +#define bM4_INTC_VSSEL143_VSEL5 (*((volatile unsigned int*)(0x42A25314UL))) +#define bM4_INTC_VSSEL143_VSEL6 (*((volatile unsigned int*)(0x42A25318UL))) +#define bM4_INTC_VSSEL143_VSEL7 (*((volatile unsigned int*)(0x42A2531CUL))) +#define bM4_INTC_VSSEL143_VSEL8 (*((volatile unsigned int*)(0x42A25320UL))) +#define bM4_INTC_VSSEL143_VSEL9 (*((volatile unsigned int*)(0x42A25324UL))) +#define bM4_INTC_VSSEL143_VSEL10 (*((volatile unsigned int*)(0x42A25328UL))) +#define bM4_INTC_VSSEL143_VSEL11 (*((volatile unsigned int*)(0x42A2532CUL))) +#define bM4_INTC_VSSEL143_VSEL12 (*((volatile unsigned int*)(0x42A25330UL))) +#define bM4_INTC_VSSEL143_VSEL13 (*((volatile unsigned int*)(0x42A25334UL))) +#define bM4_INTC_VSSEL143_VSEL14 (*((volatile unsigned int*)(0x42A25338UL))) +#define bM4_INTC_VSSEL143_VSEL15 (*((volatile unsigned int*)(0x42A2533CUL))) +#define bM4_INTC_VSSEL143_VSEL16 (*((volatile unsigned int*)(0x42A25340UL))) +#define bM4_INTC_VSSEL143_VSEL17 (*((volatile unsigned int*)(0x42A25344UL))) +#define bM4_INTC_VSSEL143_VSEL18 (*((volatile unsigned int*)(0x42A25348UL))) +#define bM4_INTC_VSSEL143_VSEL19 (*((volatile unsigned int*)(0x42A2534CUL))) +#define bM4_INTC_VSSEL143_VSEL20 (*((volatile unsigned int*)(0x42A25350UL))) +#define bM4_INTC_VSSEL143_VSEL21 (*((volatile unsigned int*)(0x42A25354UL))) +#define bM4_INTC_VSSEL143_VSEL22 (*((volatile unsigned int*)(0x42A25358UL))) +#define bM4_INTC_VSSEL143_VSEL23 (*((volatile unsigned int*)(0x42A2535CUL))) +#define bM4_INTC_VSSEL143_VSEL24 (*((volatile unsigned int*)(0x42A25360UL))) +#define bM4_INTC_VSSEL143_VSEL25 (*((volatile unsigned int*)(0x42A25364UL))) +#define bM4_INTC_VSSEL143_VSEL26 (*((volatile unsigned int*)(0x42A25368UL))) +#define bM4_INTC_VSSEL143_VSEL27 (*((volatile unsigned int*)(0x42A2536CUL))) +#define bM4_INTC_VSSEL143_VSEL28 (*((volatile unsigned int*)(0x42A25370UL))) +#define bM4_INTC_VSSEL143_VSEL29 (*((volatile unsigned int*)(0x42A25374UL))) +#define bM4_INTC_VSSEL143_VSEL30 (*((volatile unsigned int*)(0x42A25378UL))) +#define bM4_INTC_VSSEL143_VSEL31 (*((volatile unsigned int*)(0x42A2537CUL))) +#define bM4_INTC_SWIER_SWIE0 (*((volatile unsigned int*)(0x42A25380UL))) +#define bM4_INTC_SWIER_SWIE1 (*((volatile unsigned int*)(0x42A25384UL))) +#define bM4_INTC_SWIER_SWIE2 (*((volatile unsigned int*)(0x42A25388UL))) +#define bM4_INTC_SWIER_SWIE3 (*((volatile unsigned int*)(0x42A2538CUL))) +#define bM4_INTC_SWIER_SWIE4 (*((volatile unsigned int*)(0x42A25390UL))) +#define bM4_INTC_SWIER_SWIE5 (*((volatile unsigned int*)(0x42A25394UL))) +#define bM4_INTC_SWIER_SWIE6 (*((volatile unsigned int*)(0x42A25398UL))) +#define bM4_INTC_SWIER_SWIE7 (*((volatile unsigned int*)(0x42A2539CUL))) +#define bM4_INTC_SWIER_SWIE8 (*((volatile unsigned int*)(0x42A253A0UL))) +#define bM4_INTC_SWIER_SWIE9 (*((volatile unsigned int*)(0x42A253A4UL))) +#define bM4_INTC_SWIER_SWIE10 (*((volatile unsigned int*)(0x42A253A8UL))) +#define bM4_INTC_SWIER_SWIE11 (*((volatile unsigned int*)(0x42A253ACUL))) +#define bM4_INTC_SWIER_SWIE12 (*((volatile unsigned int*)(0x42A253B0UL))) +#define bM4_INTC_SWIER_SWIE13 (*((volatile unsigned int*)(0x42A253B4UL))) +#define bM4_INTC_SWIER_SWIE14 (*((volatile unsigned int*)(0x42A253B8UL))) +#define bM4_INTC_SWIER_SWIE15 (*((volatile unsigned int*)(0x42A253BCUL))) +#define bM4_INTC_SWIER_SWIE16 (*((volatile unsigned int*)(0x42A253C0UL))) +#define bM4_INTC_SWIER_SWIE17 (*((volatile unsigned int*)(0x42A253C4UL))) +#define bM4_INTC_SWIER_SWIE18 (*((volatile unsigned int*)(0x42A253C8UL))) +#define bM4_INTC_SWIER_SWIE19 (*((volatile unsigned int*)(0x42A253CCUL))) +#define bM4_INTC_SWIER_SWIE20 (*((volatile unsigned int*)(0x42A253D0UL))) +#define bM4_INTC_SWIER_SWIE21 (*((volatile unsigned int*)(0x42A253D4UL))) +#define bM4_INTC_SWIER_SWIE22 (*((volatile unsigned int*)(0x42A253D8UL))) +#define bM4_INTC_SWIER_SWIE23 (*((volatile unsigned int*)(0x42A253DCUL))) +#define bM4_INTC_SWIER_SWIE24 (*((volatile unsigned int*)(0x42A253E0UL))) +#define bM4_INTC_SWIER_SWIE25 (*((volatile unsigned int*)(0x42A253E4UL))) +#define bM4_INTC_SWIER_SWIE26 (*((volatile unsigned int*)(0x42A253E8UL))) +#define bM4_INTC_SWIER_SWIE27 (*((volatile unsigned int*)(0x42A253ECUL))) +#define bM4_INTC_SWIER_SWIE28 (*((volatile unsigned int*)(0x42A253F0UL))) +#define bM4_INTC_SWIER_SWIE29 (*((volatile unsigned int*)(0x42A253F4UL))) +#define bM4_INTC_SWIER_SWIE30 (*((volatile unsigned int*)(0x42A253F8UL))) +#define bM4_INTC_SWIER_SWIE31 (*((volatile unsigned int*)(0x42A253FCUL))) +#define bM4_INTC_EVTER_EVTE0 (*((volatile unsigned int*)(0x42A25400UL))) +#define bM4_INTC_EVTER_EVTE1 (*((volatile unsigned int*)(0x42A25404UL))) +#define bM4_INTC_EVTER_EVTE2 (*((volatile unsigned int*)(0x42A25408UL))) +#define bM4_INTC_EVTER_EVTE3 (*((volatile unsigned int*)(0x42A2540CUL))) +#define bM4_INTC_EVTER_EVTE4 (*((volatile unsigned int*)(0x42A25410UL))) +#define bM4_INTC_EVTER_EVTE5 (*((volatile unsigned int*)(0x42A25414UL))) +#define bM4_INTC_EVTER_EVTE6 (*((volatile unsigned int*)(0x42A25418UL))) +#define bM4_INTC_EVTER_EVTE7 (*((volatile unsigned int*)(0x42A2541CUL))) +#define bM4_INTC_EVTER_EVTE8 (*((volatile unsigned int*)(0x42A25420UL))) +#define bM4_INTC_EVTER_EVTE9 (*((volatile unsigned int*)(0x42A25424UL))) +#define bM4_INTC_EVTER_EVTE10 (*((volatile unsigned int*)(0x42A25428UL))) +#define bM4_INTC_EVTER_EVTE11 (*((volatile unsigned int*)(0x42A2542CUL))) +#define bM4_INTC_EVTER_EVTE12 (*((volatile unsigned int*)(0x42A25430UL))) +#define bM4_INTC_EVTER_EVTE13 (*((volatile unsigned int*)(0x42A25434UL))) +#define bM4_INTC_EVTER_EVTE14 (*((volatile unsigned int*)(0x42A25438UL))) +#define bM4_INTC_EVTER_EVTE15 (*((volatile unsigned int*)(0x42A2543CUL))) +#define bM4_INTC_EVTER_EVTE16 (*((volatile unsigned int*)(0x42A25440UL))) +#define bM4_INTC_EVTER_EVTE17 (*((volatile unsigned int*)(0x42A25444UL))) +#define bM4_INTC_EVTER_EVTE18 (*((volatile unsigned int*)(0x42A25448UL))) +#define bM4_INTC_EVTER_EVTE19 (*((volatile unsigned int*)(0x42A2544CUL))) +#define bM4_INTC_EVTER_EVTE20 (*((volatile unsigned int*)(0x42A25450UL))) +#define bM4_INTC_EVTER_EVTE21 (*((volatile unsigned int*)(0x42A25454UL))) +#define bM4_INTC_EVTER_EVTE22 (*((volatile unsigned int*)(0x42A25458UL))) +#define bM4_INTC_EVTER_EVTE23 (*((volatile unsigned int*)(0x42A2545CUL))) +#define bM4_INTC_EVTER_EVTE24 (*((volatile unsigned int*)(0x42A25460UL))) +#define bM4_INTC_EVTER_EVTE25 (*((volatile unsigned int*)(0x42A25464UL))) +#define bM4_INTC_EVTER_EVTE26 (*((volatile unsigned int*)(0x42A25468UL))) +#define bM4_INTC_EVTER_EVTE27 (*((volatile unsigned int*)(0x42A2546CUL))) +#define bM4_INTC_EVTER_EVTE28 (*((volatile unsigned int*)(0x42A25470UL))) +#define bM4_INTC_EVTER_EVTE29 (*((volatile unsigned int*)(0x42A25474UL))) +#define bM4_INTC_EVTER_EVTE30 (*((volatile unsigned int*)(0x42A25478UL))) +#define bM4_INTC_EVTER_EVTE31 (*((volatile unsigned int*)(0x42A2547CUL))) +#define bM4_INTC_IER_IER0 (*((volatile unsigned int*)(0x42A25480UL))) +#define bM4_INTC_IER_IER1 (*((volatile unsigned int*)(0x42A25484UL))) +#define bM4_INTC_IER_IER2 (*((volatile unsigned int*)(0x42A25488UL))) +#define bM4_INTC_IER_IER3 (*((volatile unsigned int*)(0x42A2548CUL))) +#define bM4_INTC_IER_IER4 (*((volatile unsigned int*)(0x42A25490UL))) +#define bM4_INTC_IER_IER5 (*((volatile unsigned int*)(0x42A25494UL))) +#define bM4_INTC_IER_IER6 (*((volatile unsigned int*)(0x42A25498UL))) +#define bM4_INTC_IER_IER7 (*((volatile unsigned int*)(0x42A2549CUL))) +#define bM4_INTC_IER_IER8 (*((volatile unsigned int*)(0x42A254A0UL))) +#define bM4_INTC_IER_IER9 (*((volatile unsigned int*)(0x42A254A4UL))) +#define bM4_INTC_IER_IER10 (*((volatile unsigned int*)(0x42A254A8UL))) +#define bM4_INTC_IER_IER11 (*((volatile unsigned int*)(0x42A254ACUL))) +#define bM4_INTC_IER_IER12 (*((volatile unsigned int*)(0x42A254B0UL))) +#define bM4_INTC_IER_IER13 (*((volatile unsigned int*)(0x42A254B4UL))) +#define bM4_INTC_IER_IER14 (*((volatile unsigned int*)(0x42A254B8UL))) +#define bM4_INTC_IER_IER15 (*((volatile unsigned int*)(0x42A254BCUL))) +#define bM4_INTC_IER_IER16 (*((volatile unsigned int*)(0x42A254C0UL))) +#define bM4_INTC_IER_IER17 (*((volatile unsigned int*)(0x42A254C4UL))) +#define bM4_INTC_IER_IER18 (*((volatile unsigned int*)(0x42A254C8UL))) +#define bM4_INTC_IER_IER19 (*((volatile unsigned int*)(0x42A254CCUL))) +#define bM4_INTC_IER_IER20 (*((volatile unsigned int*)(0x42A254D0UL))) +#define bM4_INTC_IER_IER21 (*((volatile unsigned int*)(0x42A254D4UL))) +#define bM4_INTC_IER_IER22 (*((volatile unsigned int*)(0x42A254D8UL))) +#define bM4_INTC_IER_IER23 (*((volatile unsigned int*)(0x42A254DCUL))) +#define bM4_INTC_IER_IER24 (*((volatile unsigned int*)(0x42A254E0UL))) +#define bM4_INTC_IER_IER25 (*((volatile unsigned int*)(0x42A254E4UL))) +#define bM4_INTC_IER_IER26 (*((volatile unsigned int*)(0x42A254E8UL))) +#define bM4_INTC_IER_IER27 (*((volatile unsigned int*)(0x42A254ECUL))) +#define bM4_INTC_IER_IER28 (*((volatile unsigned int*)(0x42A254F0UL))) +#define bM4_INTC_IER_IER29 (*((volatile unsigned int*)(0x42A254F4UL))) +#define bM4_INTC_IER_IER30 (*((volatile unsigned int*)(0x42A254F8UL))) +#define bM4_INTC_IER_IER31 (*((volatile unsigned int*)(0x42A254FCUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL0 (*((volatile unsigned int*)(0x42A18000UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL1 (*((volatile unsigned int*)(0x42A18004UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL2 (*((volatile unsigned int*)(0x42A18008UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL3 (*((volatile unsigned int*)(0x42A1800CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL4 (*((volatile unsigned int*)(0x42A18010UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL5 (*((volatile unsigned int*)(0x42A18014UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL6 (*((volatile unsigned int*)(0x42A18018UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL7 (*((volatile unsigned int*)(0x42A1801CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL8 (*((volatile unsigned int*)(0x42A18020UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL9 (*((volatile unsigned int*)(0x42A18024UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL10 (*((volatile unsigned int*)(0x42A18028UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL11 (*((volatile unsigned int*)(0x42A1802CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL12 (*((volatile unsigned int*)(0x42A18030UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL13 (*((volatile unsigned int*)(0x42A18034UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL14 (*((volatile unsigned int*)(0x42A18038UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL15 (*((volatile unsigned int*)(0x42A1803CUL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL0 (*((volatile unsigned int*)(0x42A18040UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL1 (*((volatile unsigned int*)(0x42A18044UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL2 (*((volatile unsigned int*)(0x42A18048UL))) +#define bM4_KEYSCAN_SCR_CKSEL0 (*((volatile unsigned int*)(0x42A18050UL))) +#define bM4_KEYSCAN_SCR_CKSEL1 (*((volatile unsigned int*)(0x42A18054UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL0 (*((volatile unsigned int*)(0x42A18060UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL1 (*((volatile unsigned int*)(0x42A18064UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL2 (*((volatile unsigned int*)(0x42A18068UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL3 (*((volatile unsigned int*)(0x42A1806CUL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL4 (*((volatile unsigned int*)(0x42A18070UL))) +#define bM4_KEYSCAN_SCR_T_HIZ0 (*((volatile unsigned int*)(0x42A18074UL))) +#define bM4_KEYSCAN_SCR_T_HIZ1 (*((volatile unsigned int*)(0x42A18078UL))) +#define bM4_KEYSCAN_SCR_T_HIZ2 (*((volatile unsigned int*)(0x42A1807CUL))) +#define bM4_KEYSCAN_SER_SEN (*((volatile unsigned int*)(0x42A18080UL))) +#define bM4_KEYSCAN_SSR_INDEX0 (*((volatile unsigned int*)(0x42A18100UL))) +#define bM4_KEYSCAN_SSR_INDEX1 (*((volatile unsigned int*)(0x42A18104UL))) +#define bM4_KEYSCAN_SSR_INDEX2 (*((volatile unsigned int*)(0x42A18108UL))) +#define bM4_MPU_RGD0_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00000UL))) +#define bM4_MPU_RGD0_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00004UL))) +#define bM4_MPU_RGD0_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00008UL))) +#define bM4_MPU_RGD0_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0000CUL))) +#define bM4_MPU_RGD0_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00010UL))) +#define bM4_MPU_RGD0_MPURGADDR0 (*((volatile unsigned int*)(0x42A00014UL))) +#define bM4_MPU_RGD0_MPURGADDR1 (*((volatile unsigned int*)(0x42A00018UL))) +#define bM4_MPU_RGD0_MPURGADDR2 (*((volatile unsigned int*)(0x42A0001CUL))) +#define bM4_MPU_RGD0_MPURGADDR3 (*((volatile unsigned int*)(0x42A00020UL))) +#define bM4_MPU_RGD0_MPURGADDR4 (*((volatile unsigned int*)(0x42A00024UL))) +#define bM4_MPU_RGD0_MPURGADDR5 (*((volatile unsigned int*)(0x42A00028UL))) +#define bM4_MPU_RGD0_MPURGADDR6 (*((volatile unsigned int*)(0x42A0002CUL))) +#define bM4_MPU_RGD0_MPURGADDR7 (*((volatile unsigned int*)(0x42A00030UL))) +#define bM4_MPU_RGD0_MPURGADDR8 (*((volatile unsigned int*)(0x42A00034UL))) +#define bM4_MPU_RGD0_MPURGADDR9 (*((volatile unsigned int*)(0x42A00038UL))) +#define bM4_MPU_RGD0_MPURGADDR10 (*((volatile unsigned int*)(0x42A0003CUL))) +#define bM4_MPU_RGD0_MPURGADDR11 (*((volatile unsigned int*)(0x42A00040UL))) +#define bM4_MPU_RGD0_MPURGADDR12 (*((volatile unsigned int*)(0x42A00044UL))) +#define bM4_MPU_RGD0_MPURGADDR13 (*((volatile unsigned int*)(0x42A00048UL))) +#define bM4_MPU_RGD0_MPURGADDR14 (*((volatile unsigned int*)(0x42A0004CUL))) +#define bM4_MPU_RGD0_MPURGADDR15 (*((volatile unsigned int*)(0x42A00050UL))) +#define bM4_MPU_RGD0_MPURGADDR16 (*((volatile unsigned int*)(0x42A00054UL))) +#define bM4_MPU_RGD0_MPURGADDR17 (*((volatile unsigned int*)(0x42A00058UL))) +#define bM4_MPU_RGD0_MPURGADDR18 (*((volatile unsigned int*)(0x42A0005CUL))) +#define bM4_MPU_RGD0_MPURGADDR19 (*((volatile unsigned int*)(0x42A00060UL))) +#define bM4_MPU_RGD0_MPURGADDR20 (*((volatile unsigned int*)(0x42A00064UL))) +#define bM4_MPU_RGD0_MPURGADDR21 (*((volatile unsigned int*)(0x42A00068UL))) +#define bM4_MPU_RGD0_MPURGADDR22 (*((volatile unsigned int*)(0x42A0006CUL))) +#define bM4_MPU_RGD0_MPURGADDR23 (*((volatile unsigned int*)(0x42A00070UL))) +#define bM4_MPU_RGD0_MPURGADDR24 (*((volatile unsigned int*)(0x42A00074UL))) +#define bM4_MPU_RGD0_MPURGADDR25 (*((volatile unsigned int*)(0x42A00078UL))) +#define bM4_MPU_RGD0_MPURGADDR26 (*((volatile unsigned int*)(0x42A0007CUL))) +#define bM4_MPU_RGD1_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00080UL))) +#define bM4_MPU_RGD1_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00084UL))) +#define bM4_MPU_RGD1_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00088UL))) +#define bM4_MPU_RGD1_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0008CUL))) +#define bM4_MPU_RGD1_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00090UL))) +#define bM4_MPU_RGD1_MPURGADDR0 (*((volatile unsigned int*)(0x42A00094UL))) +#define bM4_MPU_RGD1_MPURGADDR1 (*((volatile unsigned int*)(0x42A00098UL))) +#define bM4_MPU_RGD1_MPURGADDR2 (*((volatile unsigned int*)(0x42A0009CUL))) +#define bM4_MPU_RGD1_MPURGADDR3 (*((volatile unsigned int*)(0x42A000A0UL))) +#define bM4_MPU_RGD1_MPURGADDR4 (*((volatile unsigned int*)(0x42A000A4UL))) +#define bM4_MPU_RGD1_MPURGADDR5 (*((volatile unsigned int*)(0x42A000A8UL))) +#define bM4_MPU_RGD1_MPURGADDR6 (*((volatile unsigned int*)(0x42A000ACUL))) +#define bM4_MPU_RGD1_MPURGADDR7 (*((volatile unsigned int*)(0x42A000B0UL))) +#define bM4_MPU_RGD1_MPURGADDR8 (*((volatile unsigned int*)(0x42A000B4UL))) +#define bM4_MPU_RGD1_MPURGADDR9 (*((volatile unsigned int*)(0x42A000B8UL))) +#define bM4_MPU_RGD1_MPURGADDR10 (*((volatile unsigned int*)(0x42A000BCUL))) +#define bM4_MPU_RGD1_MPURGADDR11 (*((volatile unsigned int*)(0x42A000C0UL))) +#define bM4_MPU_RGD1_MPURGADDR12 (*((volatile unsigned int*)(0x42A000C4UL))) +#define bM4_MPU_RGD1_MPURGADDR13 (*((volatile unsigned int*)(0x42A000C8UL))) +#define bM4_MPU_RGD1_MPURGADDR14 (*((volatile unsigned int*)(0x42A000CCUL))) +#define bM4_MPU_RGD1_MPURGADDR15 (*((volatile unsigned int*)(0x42A000D0UL))) +#define bM4_MPU_RGD1_MPURGADDR16 (*((volatile unsigned int*)(0x42A000D4UL))) +#define bM4_MPU_RGD1_MPURGADDR17 (*((volatile unsigned int*)(0x42A000D8UL))) +#define bM4_MPU_RGD1_MPURGADDR18 (*((volatile unsigned int*)(0x42A000DCUL))) +#define bM4_MPU_RGD1_MPURGADDR19 (*((volatile unsigned int*)(0x42A000E0UL))) +#define bM4_MPU_RGD1_MPURGADDR20 (*((volatile unsigned int*)(0x42A000E4UL))) +#define bM4_MPU_RGD1_MPURGADDR21 (*((volatile unsigned int*)(0x42A000E8UL))) +#define bM4_MPU_RGD1_MPURGADDR22 (*((volatile unsigned int*)(0x42A000ECUL))) +#define bM4_MPU_RGD1_MPURGADDR23 (*((volatile unsigned int*)(0x42A000F0UL))) +#define bM4_MPU_RGD1_MPURGADDR24 (*((volatile unsigned int*)(0x42A000F4UL))) +#define bM4_MPU_RGD1_MPURGADDR25 (*((volatile unsigned int*)(0x42A000F8UL))) +#define bM4_MPU_RGD1_MPURGADDR26 (*((volatile unsigned int*)(0x42A000FCUL))) +#define bM4_MPU_RGD2_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00100UL))) +#define bM4_MPU_RGD2_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00104UL))) +#define bM4_MPU_RGD2_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00108UL))) +#define bM4_MPU_RGD2_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0010CUL))) +#define bM4_MPU_RGD2_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00110UL))) +#define bM4_MPU_RGD2_MPURGADDR0 (*((volatile unsigned int*)(0x42A00114UL))) +#define bM4_MPU_RGD2_MPURGADDR1 (*((volatile unsigned int*)(0x42A00118UL))) +#define bM4_MPU_RGD2_MPURGADDR2 (*((volatile unsigned int*)(0x42A0011CUL))) +#define bM4_MPU_RGD2_MPURGADDR3 (*((volatile unsigned int*)(0x42A00120UL))) +#define bM4_MPU_RGD2_MPURGADDR4 (*((volatile unsigned int*)(0x42A00124UL))) +#define bM4_MPU_RGD2_MPURGADDR5 (*((volatile unsigned int*)(0x42A00128UL))) +#define bM4_MPU_RGD2_MPURGADDR6 (*((volatile unsigned int*)(0x42A0012CUL))) +#define bM4_MPU_RGD2_MPURGADDR7 (*((volatile unsigned int*)(0x42A00130UL))) +#define bM4_MPU_RGD2_MPURGADDR8 (*((volatile unsigned int*)(0x42A00134UL))) +#define bM4_MPU_RGD2_MPURGADDR9 (*((volatile unsigned int*)(0x42A00138UL))) +#define bM4_MPU_RGD2_MPURGADDR10 (*((volatile unsigned int*)(0x42A0013CUL))) +#define bM4_MPU_RGD2_MPURGADDR11 (*((volatile unsigned int*)(0x42A00140UL))) +#define bM4_MPU_RGD2_MPURGADDR12 (*((volatile unsigned int*)(0x42A00144UL))) +#define bM4_MPU_RGD2_MPURGADDR13 (*((volatile unsigned int*)(0x42A00148UL))) +#define bM4_MPU_RGD2_MPURGADDR14 (*((volatile unsigned int*)(0x42A0014CUL))) +#define bM4_MPU_RGD2_MPURGADDR15 (*((volatile unsigned int*)(0x42A00150UL))) +#define bM4_MPU_RGD2_MPURGADDR16 (*((volatile unsigned int*)(0x42A00154UL))) +#define bM4_MPU_RGD2_MPURGADDR17 (*((volatile unsigned int*)(0x42A00158UL))) +#define bM4_MPU_RGD2_MPURGADDR18 (*((volatile unsigned int*)(0x42A0015CUL))) +#define bM4_MPU_RGD2_MPURGADDR19 (*((volatile unsigned int*)(0x42A00160UL))) +#define bM4_MPU_RGD2_MPURGADDR20 (*((volatile unsigned int*)(0x42A00164UL))) +#define bM4_MPU_RGD2_MPURGADDR21 (*((volatile unsigned int*)(0x42A00168UL))) +#define bM4_MPU_RGD2_MPURGADDR22 (*((volatile unsigned int*)(0x42A0016CUL))) +#define bM4_MPU_RGD2_MPURGADDR23 (*((volatile unsigned int*)(0x42A00170UL))) +#define bM4_MPU_RGD2_MPURGADDR24 (*((volatile unsigned int*)(0x42A00174UL))) +#define bM4_MPU_RGD2_MPURGADDR25 (*((volatile unsigned int*)(0x42A00178UL))) +#define bM4_MPU_RGD2_MPURGADDR26 (*((volatile unsigned int*)(0x42A0017CUL))) +#define bM4_MPU_RGD3_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00180UL))) +#define bM4_MPU_RGD3_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00184UL))) +#define bM4_MPU_RGD3_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00188UL))) +#define bM4_MPU_RGD3_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0018CUL))) +#define bM4_MPU_RGD3_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00190UL))) +#define bM4_MPU_RGD3_MPURGADDR0 (*((volatile unsigned int*)(0x42A00194UL))) +#define bM4_MPU_RGD3_MPURGADDR1 (*((volatile unsigned int*)(0x42A00198UL))) +#define bM4_MPU_RGD3_MPURGADDR2 (*((volatile unsigned int*)(0x42A0019CUL))) +#define bM4_MPU_RGD3_MPURGADDR3 (*((volatile unsigned int*)(0x42A001A0UL))) +#define bM4_MPU_RGD3_MPURGADDR4 (*((volatile unsigned int*)(0x42A001A4UL))) +#define bM4_MPU_RGD3_MPURGADDR5 (*((volatile unsigned int*)(0x42A001A8UL))) +#define bM4_MPU_RGD3_MPURGADDR6 (*((volatile unsigned int*)(0x42A001ACUL))) +#define bM4_MPU_RGD3_MPURGADDR7 (*((volatile unsigned int*)(0x42A001B0UL))) +#define bM4_MPU_RGD3_MPURGADDR8 (*((volatile unsigned int*)(0x42A001B4UL))) +#define bM4_MPU_RGD3_MPURGADDR9 (*((volatile unsigned int*)(0x42A001B8UL))) +#define bM4_MPU_RGD3_MPURGADDR10 (*((volatile unsigned int*)(0x42A001BCUL))) +#define bM4_MPU_RGD3_MPURGADDR11 (*((volatile unsigned int*)(0x42A001C0UL))) +#define bM4_MPU_RGD3_MPURGADDR12 (*((volatile unsigned int*)(0x42A001C4UL))) +#define bM4_MPU_RGD3_MPURGADDR13 (*((volatile unsigned int*)(0x42A001C8UL))) +#define bM4_MPU_RGD3_MPURGADDR14 (*((volatile unsigned int*)(0x42A001CCUL))) +#define bM4_MPU_RGD3_MPURGADDR15 (*((volatile unsigned int*)(0x42A001D0UL))) +#define bM4_MPU_RGD3_MPURGADDR16 (*((volatile unsigned int*)(0x42A001D4UL))) +#define bM4_MPU_RGD3_MPURGADDR17 (*((volatile unsigned int*)(0x42A001D8UL))) +#define bM4_MPU_RGD3_MPURGADDR18 (*((volatile unsigned int*)(0x42A001DCUL))) +#define bM4_MPU_RGD3_MPURGADDR19 (*((volatile unsigned int*)(0x42A001E0UL))) +#define bM4_MPU_RGD3_MPURGADDR20 (*((volatile unsigned int*)(0x42A001E4UL))) +#define bM4_MPU_RGD3_MPURGADDR21 (*((volatile unsigned int*)(0x42A001E8UL))) +#define bM4_MPU_RGD3_MPURGADDR22 (*((volatile unsigned int*)(0x42A001ECUL))) +#define bM4_MPU_RGD3_MPURGADDR23 (*((volatile unsigned int*)(0x42A001F0UL))) +#define bM4_MPU_RGD3_MPURGADDR24 (*((volatile unsigned int*)(0x42A001F4UL))) +#define bM4_MPU_RGD3_MPURGADDR25 (*((volatile unsigned int*)(0x42A001F8UL))) +#define bM4_MPU_RGD3_MPURGADDR26 (*((volatile unsigned int*)(0x42A001FCUL))) +#define bM4_MPU_RGD4_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00200UL))) +#define bM4_MPU_RGD4_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00204UL))) +#define bM4_MPU_RGD4_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00208UL))) +#define bM4_MPU_RGD4_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0020CUL))) +#define bM4_MPU_RGD4_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00210UL))) +#define bM4_MPU_RGD4_MPURGADDR0 (*((volatile unsigned int*)(0x42A00214UL))) +#define bM4_MPU_RGD4_MPURGADDR1 (*((volatile unsigned int*)(0x42A00218UL))) +#define bM4_MPU_RGD4_MPURGADDR2 (*((volatile unsigned int*)(0x42A0021CUL))) +#define bM4_MPU_RGD4_MPURGADDR3 (*((volatile unsigned int*)(0x42A00220UL))) +#define bM4_MPU_RGD4_MPURGADDR4 (*((volatile unsigned int*)(0x42A00224UL))) +#define bM4_MPU_RGD4_MPURGADDR5 (*((volatile unsigned int*)(0x42A00228UL))) +#define bM4_MPU_RGD4_MPURGADDR6 (*((volatile unsigned int*)(0x42A0022CUL))) +#define bM4_MPU_RGD4_MPURGADDR7 (*((volatile unsigned int*)(0x42A00230UL))) +#define bM4_MPU_RGD4_MPURGADDR8 (*((volatile unsigned int*)(0x42A00234UL))) +#define bM4_MPU_RGD4_MPURGADDR9 (*((volatile unsigned int*)(0x42A00238UL))) +#define bM4_MPU_RGD4_MPURGADDR10 (*((volatile unsigned int*)(0x42A0023CUL))) +#define bM4_MPU_RGD4_MPURGADDR11 (*((volatile unsigned int*)(0x42A00240UL))) +#define bM4_MPU_RGD4_MPURGADDR12 (*((volatile unsigned int*)(0x42A00244UL))) +#define bM4_MPU_RGD4_MPURGADDR13 (*((volatile unsigned int*)(0x42A00248UL))) +#define bM4_MPU_RGD4_MPURGADDR14 (*((volatile unsigned int*)(0x42A0024CUL))) +#define bM4_MPU_RGD4_MPURGADDR15 (*((volatile unsigned int*)(0x42A00250UL))) +#define bM4_MPU_RGD4_MPURGADDR16 (*((volatile unsigned int*)(0x42A00254UL))) +#define bM4_MPU_RGD4_MPURGADDR17 (*((volatile unsigned int*)(0x42A00258UL))) +#define bM4_MPU_RGD4_MPURGADDR18 (*((volatile unsigned int*)(0x42A0025CUL))) +#define bM4_MPU_RGD4_MPURGADDR19 (*((volatile unsigned int*)(0x42A00260UL))) +#define bM4_MPU_RGD4_MPURGADDR20 (*((volatile unsigned int*)(0x42A00264UL))) +#define bM4_MPU_RGD4_MPURGADDR21 (*((volatile unsigned int*)(0x42A00268UL))) +#define bM4_MPU_RGD4_MPURGADDR22 (*((volatile unsigned int*)(0x42A0026CUL))) +#define bM4_MPU_RGD4_MPURGADDR23 (*((volatile unsigned int*)(0x42A00270UL))) +#define bM4_MPU_RGD4_MPURGADDR24 (*((volatile unsigned int*)(0x42A00274UL))) +#define bM4_MPU_RGD4_MPURGADDR25 (*((volatile unsigned int*)(0x42A00278UL))) +#define bM4_MPU_RGD4_MPURGADDR26 (*((volatile unsigned int*)(0x42A0027CUL))) +#define bM4_MPU_RGD5_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00280UL))) +#define bM4_MPU_RGD5_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00284UL))) +#define bM4_MPU_RGD5_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00288UL))) +#define bM4_MPU_RGD5_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0028CUL))) +#define bM4_MPU_RGD5_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00290UL))) +#define bM4_MPU_RGD5_MPURGADDR0 (*((volatile unsigned int*)(0x42A00294UL))) +#define bM4_MPU_RGD5_MPURGADDR1 (*((volatile unsigned int*)(0x42A00298UL))) +#define bM4_MPU_RGD5_MPURGADDR2 (*((volatile unsigned int*)(0x42A0029CUL))) +#define bM4_MPU_RGD5_MPURGADDR3 (*((volatile unsigned int*)(0x42A002A0UL))) +#define bM4_MPU_RGD5_MPURGADDR4 (*((volatile unsigned int*)(0x42A002A4UL))) +#define bM4_MPU_RGD5_MPURGADDR5 (*((volatile unsigned int*)(0x42A002A8UL))) +#define bM4_MPU_RGD5_MPURGADDR6 (*((volatile unsigned int*)(0x42A002ACUL))) +#define bM4_MPU_RGD5_MPURGADDR7 (*((volatile unsigned int*)(0x42A002B0UL))) +#define bM4_MPU_RGD5_MPURGADDR8 (*((volatile unsigned int*)(0x42A002B4UL))) +#define bM4_MPU_RGD5_MPURGADDR9 (*((volatile unsigned int*)(0x42A002B8UL))) +#define bM4_MPU_RGD5_MPURGADDR10 (*((volatile unsigned int*)(0x42A002BCUL))) +#define bM4_MPU_RGD5_MPURGADDR11 (*((volatile unsigned int*)(0x42A002C0UL))) +#define bM4_MPU_RGD5_MPURGADDR12 (*((volatile unsigned int*)(0x42A002C4UL))) +#define bM4_MPU_RGD5_MPURGADDR13 (*((volatile unsigned int*)(0x42A002C8UL))) +#define bM4_MPU_RGD5_MPURGADDR14 (*((volatile unsigned int*)(0x42A002CCUL))) +#define bM4_MPU_RGD5_MPURGADDR15 (*((volatile unsigned int*)(0x42A002D0UL))) +#define bM4_MPU_RGD5_MPURGADDR16 (*((volatile unsigned int*)(0x42A002D4UL))) +#define bM4_MPU_RGD5_MPURGADDR17 (*((volatile unsigned int*)(0x42A002D8UL))) +#define bM4_MPU_RGD5_MPURGADDR18 (*((volatile unsigned int*)(0x42A002DCUL))) +#define bM4_MPU_RGD5_MPURGADDR19 (*((volatile unsigned int*)(0x42A002E0UL))) +#define bM4_MPU_RGD5_MPURGADDR20 (*((volatile unsigned int*)(0x42A002E4UL))) +#define bM4_MPU_RGD5_MPURGADDR21 (*((volatile unsigned int*)(0x42A002E8UL))) +#define bM4_MPU_RGD5_MPURGADDR22 (*((volatile unsigned int*)(0x42A002ECUL))) +#define bM4_MPU_RGD5_MPURGADDR23 (*((volatile unsigned int*)(0x42A002F0UL))) +#define bM4_MPU_RGD5_MPURGADDR24 (*((volatile unsigned int*)(0x42A002F4UL))) +#define bM4_MPU_RGD5_MPURGADDR25 (*((volatile unsigned int*)(0x42A002F8UL))) +#define bM4_MPU_RGD5_MPURGADDR26 (*((volatile unsigned int*)(0x42A002FCUL))) +#define bM4_MPU_RGD6_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00300UL))) +#define bM4_MPU_RGD6_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00304UL))) +#define bM4_MPU_RGD6_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00308UL))) +#define bM4_MPU_RGD6_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0030CUL))) +#define bM4_MPU_RGD6_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00310UL))) +#define bM4_MPU_RGD6_MPURGADDR0 (*((volatile unsigned int*)(0x42A00314UL))) +#define bM4_MPU_RGD6_MPURGADDR1 (*((volatile unsigned int*)(0x42A00318UL))) +#define bM4_MPU_RGD6_MPURGADDR2 (*((volatile unsigned int*)(0x42A0031CUL))) +#define bM4_MPU_RGD6_MPURGADDR3 (*((volatile unsigned int*)(0x42A00320UL))) +#define bM4_MPU_RGD6_MPURGADDR4 (*((volatile unsigned int*)(0x42A00324UL))) +#define bM4_MPU_RGD6_MPURGADDR5 (*((volatile unsigned int*)(0x42A00328UL))) +#define bM4_MPU_RGD6_MPURGADDR6 (*((volatile unsigned int*)(0x42A0032CUL))) +#define bM4_MPU_RGD6_MPURGADDR7 (*((volatile unsigned int*)(0x42A00330UL))) +#define bM4_MPU_RGD6_MPURGADDR8 (*((volatile unsigned int*)(0x42A00334UL))) +#define bM4_MPU_RGD6_MPURGADDR9 (*((volatile unsigned int*)(0x42A00338UL))) +#define bM4_MPU_RGD6_MPURGADDR10 (*((volatile unsigned int*)(0x42A0033CUL))) +#define bM4_MPU_RGD6_MPURGADDR11 (*((volatile unsigned int*)(0x42A00340UL))) +#define bM4_MPU_RGD6_MPURGADDR12 (*((volatile unsigned int*)(0x42A00344UL))) +#define bM4_MPU_RGD6_MPURGADDR13 (*((volatile unsigned int*)(0x42A00348UL))) +#define bM4_MPU_RGD6_MPURGADDR14 (*((volatile unsigned int*)(0x42A0034CUL))) +#define bM4_MPU_RGD6_MPURGADDR15 (*((volatile unsigned int*)(0x42A00350UL))) +#define bM4_MPU_RGD6_MPURGADDR16 (*((volatile unsigned int*)(0x42A00354UL))) +#define bM4_MPU_RGD6_MPURGADDR17 (*((volatile unsigned int*)(0x42A00358UL))) +#define bM4_MPU_RGD6_MPURGADDR18 (*((volatile unsigned int*)(0x42A0035CUL))) +#define bM4_MPU_RGD6_MPURGADDR19 (*((volatile unsigned int*)(0x42A00360UL))) +#define bM4_MPU_RGD6_MPURGADDR20 (*((volatile unsigned int*)(0x42A00364UL))) +#define bM4_MPU_RGD6_MPURGADDR21 (*((volatile unsigned int*)(0x42A00368UL))) +#define bM4_MPU_RGD6_MPURGADDR22 (*((volatile unsigned int*)(0x42A0036CUL))) +#define bM4_MPU_RGD6_MPURGADDR23 (*((volatile unsigned int*)(0x42A00370UL))) +#define bM4_MPU_RGD6_MPURGADDR24 (*((volatile unsigned int*)(0x42A00374UL))) +#define bM4_MPU_RGD6_MPURGADDR25 (*((volatile unsigned int*)(0x42A00378UL))) +#define bM4_MPU_RGD6_MPURGADDR26 (*((volatile unsigned int*)(0x42A0037CUL))) +#define bM4_MPU_RGD7_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00380UL))) +#define bM4_MPU_RGD7_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00384UL))) +#define bM4_MPU_RGD7_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00388UL))) +#define bM4_MPU_RGD7_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0038CUL))) +#define bM4_MPU_RGD7_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00390UL))) +#define bM4_MPU_RGD7_MPURGADDR0 (*((volatile unsigned int*)(0x42A00394UL))) +#define bM4_MPU_RGD7_MPURGADDR1 (*((volatile unsigned int*)(0x42A00398UL))) +#define bM4_MPU_RGD7_MPURGADDR2 (*((volatile unsigned int*)(0x42A0039CUL))) +#define bM4_MPU_RGD7_MPURGADDR3 (*((volatile unsigned int*)(0x42A003A0UL))) +#define bM4_MPU_RGD7_MPURGADDR4 (*((volatile unsigned int*)(0x42A003A4UL))) +#define bM4_MPU_RGD7_MPURGADDR5 (*((volatile unsigned int*)(0x42A003A8UL))) +#define bM4_MPU_RGD7_MPURGADDR6 (*((volatile unsigned int*)(0x42A003ACUL))) +#define bM4_MPU_RGD7_MPURGADDR7 (*((volatile unsigned int*)(0x42A003B0UL))) +#define bM4_MPU_RGD7_MPURGADDR8 (*((volatile unsigned int*)(0x42A003B4UL))) +#define bM4_MPU_RGD7_MPURGADDR9 (*((volatile unsigned int*)(0x42A003B8UL))) +#define bM4_MPU_RGD7_MPURGADDR10 (*((volatile unsigned int*)(0x42A003BCUL))) +#define bM4_MPU_RGD7_MPURGADDR11 (*((volatile unsigned int*)(0x42A003C0UL))) +#define bM4_MPU_RGD7_MPURGADDR12 (*((volatile unsigned int*)(0x42A003C4UL))) +#define bM4_MPU_RGD7_MPURGADDR13 (*((volatile unsigned int*)(0x42A003C8UL))) +#define bM4_MPU_RGD7_MPURGADDR14 (*((volatile unsigned int*)(0x42A003CCUL))) +#define bM4_MPU_RGD7_MPURGADDR15 (*((volatile unsigned int*)(0x42A003D0UL))) +#define bM4_MPU_RGD7_MPURGADDR16 (*((volatile unsigned int*)(0x42A003D4UL))) +#define bM4_MPU_RGD7_MPURGADDR17 (*((volatile unsigned int*)(0x42A003D8UL))) +#define bM4_MPU_RGD7_MPURGADDR18 (*((volatile unsigned int*)(0x42A003DCUL))) +#define bM4_MPU_RGD7_MPURGADDR19 (*((volatile unsigned int*)(0x42A003E0UL))) +#define bM4_MPU_RGD7_MPURGADDR20 (*((volatile unsigned int*)(0x42A003E4UL))) +#define bM4_MPU_RGD7_MPURGADDR21 (*((volatile unsigned int*)(0x42A003E8UL))) +#define bM4_MPU_RGD7_MPURGADDR22 (*((volatile unsigned int*)(0x42A003ECUL))) +#define bM4_MPU_RGD7_MPURGADDR23 (*((volatile unsigned int*)(0x42A003F0UL))) +#define bM4_MPU_RGD7_MPURGADDR24 (*((volatile unsigned int*)(0x42A003F4UL))) +#define bM4_MPU_RGD7_MPURGADDR25 (*((volatile unsigned int*)(0x42A003F8UL))) +#define bM4_MPU_RGD7_MPURGADDR26 (*((volatile unsigned int*)(0x42A003FCUL))) +#define bM4_MPU_RGD8_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00400UL))) +#define bM4_MPU_RGD8_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00404UL))) +#define bM4_MPU_RGD8_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00408UL))) +#define bM4_MPU_RGD8_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0040CUL))) +#define bM4_MPU_RGD8_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00410UL))) +#define bM4_MPU_RGD8_MPURGADDR0 (*((volatile unsigned int*)(0x42A00414UL))) +#define bM4_MPU_RGD8_MPURGADDR1 (*((volatile unsigned int*)(0x42A00418UL))) +#define bM4_MPU_RGD8_MPURGADDR2 (*((volatile unsigned int*)(0x42A0041CUL))) +#define bM4_MPU_RGD8_MPURGADDR3 (*((volatile unsigned int*)(0x42A00420UL))) +#define bM4_MPU_RGD8_MPURGADDR4 (*((volatile unsigned int*)(0x42A00424UL))) +#define bM4_MPU_RGD8_MPURGADDR5 (*((volatile unsigned int*)(0x42A00428UL))) +#define bM4_MPU_RGD8_MPURGADDR6 (*((volatile unsigned int*)(0x42A0042CUL))) +#define bM4_MPU_RGD8_MPURGADDR7 (*((volatile unsigned int*)(0x42A00430UL))) +#define bM4_MPU_RGD8_MPURGADDR8 (*((volatile unsigned int*)(0x42A00434UL))) +#define bM4_MPU_RGD8_MPURGADDR9 (*((volatile unsigned int*)(0x42A00438UL))) +#define bM4_MPU_RGD8_MPURGADDR10 (*((volatile unsigned int*)(0x42A0043CUL))) +#define bM4_MPU_RGD8_MPURGADDR11 (*((volatile unsigned int*)(0x42A00440UL))) +#define bM4_MPU_RGD8_MPURGADDR12 (*((volatile unsigned int*)(0x42A00444UL))) +#define bM4_MPU_RGD8_MPURGADDR13 (*((volatile unsigned int*)(0x42A00448UL))) +#define bM4_MPU_RGD8_MPURGADDR14 (*((volatile unsigned int*)(0x42A0044CUL))) +#define bM4_MPU_RGD8_MPURGADDR15 (*((volatile unsigned int*)(0x42A00450UL))) +#define bM4_MPU_RGD8_MPURGADDR16 (*((volatile unsigned int*)(0x42A00454UL))) +#define bM4_MPU_RGD8_MPURGADDR17 (*((volatile unsigned int*)(0x42A00458UL))) +#define bM4_MPU_RGD8_MPURGADDR18 (*((volatile unsigned int*)(0x42A0045CUL))) +#define bM4_MPU_RGD8_MPURGADDR19 (*((volatile unsigned int*)(0x42A00460UL))) +#define bM4_MPU_RGD8_MPURGADDR20 (*((volatile unsigned int*)(0x42A00464UL))) +#define bM4_MPU_RGD8_MPURGADDR21 (*((volatile unsigned int*)(0x42A00468UL))) +#define bM4_MPU_RGD8_MPURGADDR22 (*((volatile unsigned int*)(0x42A0046CUL))) +#define bM4_MPU_RGD8_MPURGADDR23 (*((volatile unsigned int*)(0x42A00470UL))) +#define bM4_MPU_RGD8_MPURGADDR24 (*((volatile unsigned int*)(0x42A00474UL))) +#define bM4_MPU_RGD8_MPURGADDR25 (*((volatile unsigned int*)(0x42A00478UL))) +#define bM4_MPU_RGD8_MPURGADDR26 (*((volatile unsigned int*)(0x42A0047CUL))) +#define bM4_MPU_RGD9_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00480UL))) +#define bM4_MPU_RGD9_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00484UL))) +#define bM4_MPU_RGD9_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00488UL))) +#define bM4_MPU_RGD9_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0048CUL))) +#define bM4_MPU_RGD9_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00490UL))) +#define bM4_MPU_RGD9_MPURGADDR0 (*((volatile unsigned int*)(0x42A00494UL))) +#define bM4_MPU_RGD9_MPURGADDR1 (*((volatile unsigned int*)(0x42A00498UL))) +#define bM4_MPU_RGD9_MPURGADDR2 (*((volatile unsigned int*)(0x42A0049CUL))) +#define bM4_MPU_RGD9_MPURGADDR3 (*((volatile unsigned int*)(0x42A004A0UL))) +#define bM4_MPU_RGD9_MPURGADDR4 (*((volatile unsigned int*)(0x42A004A4UL))) +#define bM4_MPU_RGD9_MPURGADDR5 (*((volatile unsigned int*)(0x42A004A8UL))) +#define bM4_MPU_RGD9_MPURGADDR6 (*((volatile unsigned int*)(0x42A004ACUL))) +#define bM4_MPU_RGD9_MPURGADDR7 (*((volatile unsigned int*)(0x42A004B0UL))) +#define bM4_MPU_RGD9_MPURGADDR8 (*((volatile unsigned int*)(0x42A004B4UL))) +#define bM4_MPU_RGD9_MPURGADDR9 (*((volatile unsigned int*)(0x42A004B8UL))) +#define bM4_MPU_RGD9_MPURGADDR10 (*((volatile unsigned int*)(0x42A004BCUL))) +#define bM4_MPU_RGD9_MPURGADDR11 (*((volatile unsigned int*)(0x42A004C0UL))) +#define bM4_MPU_RGD9_MPURGADDR12 (*((volatile unsigned int*)(0x42A004C4UL))) +#define bM4_MPU_RGD9_MPURGADDR13 (*((volatile unsigned int*)(0x42A004C8UL))) +#define bM4_MPU_RGD9_MPURGADDR14 (*((volatile unsigned int*)(0x42A004CCUL))) +#define bM4_MPU_RGD9_MPURGADDR15 (*((volatile unsigned int*)(0x42A004D0UL))) +#define bM4_MPU_RGD9_MPURGADDR16 (*((volatile unsigned int*)(0x42A004D4UL))) +#define bM4_MPU_RGD9_MPURGADDR17 (*((volatile unsigned int*)(0x42A004D8UL))) +#define bM4_MPU_RGD9_MPURGADDR18 (*((volatile unsigned int*)(0x42A004DCUL))) +#define bM4_MPU_RGD9_MPURGADDR19 (*((volatile unsigned int*)(0x42A004E0UL))) +#define bM4_MPU_RGD9_MPURGADDR20 (*((volatile unsigned int*)(0x42A004E4UL))) +#define bM4_MPU_RGD9_MPURGADDR21 (*((volatile unsigned int*)(0x42A004E8UL))) +#define bM4_MPU_RGD9_MPURGADDR22 (*((volatile unsigned int*)(0x42A004ECUL))) +#define bM4_MPU_RGD9_MPURGADDR23 (*((volatile unsigned int*)(0x42A004F0UL))) +#define bM4_MPU_RGD9_MPURGADDR24 (*((volatile unsigned int*)(0x42A004F4UL))) +#define bM4_MPU_RGD9_MPURGADDR25 (*((volatile unsigned int*)(0x42A004F8UL))) +#define bM4_MPU_RGD9_MPURGADDR26 (*((volatile unsigned int*)(0x42A004FCUL))) +#define bM4_MPU_RGD10_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00500UL))) +#define bM4_MPU_RGD10_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00504UL))) +#define bM4_MPU_RGD10_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00508UL))) +#define bM4_MPU_RGD10_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0050CUL))) +#define bM4_MPU_RGD10_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00510UL))) +#define bM4_MPU_RGD10_MPURGADDR0 (*((volatile unsigned int*)(0x42A00514UL))) +#define bM4_MPU_RGD10_MPURGADDR1 (*((volatile unsigned int*)(0x42A00518UL))) +#define bM4_MPU_RGD10_MPURGADDR2 (*((volatile unsigned int*)(0x42A0051CUL))) +#define bM4_MPU_RGD10_MPURGADDR3 (*((volatile unsigned int*)(0x42A00520UL))) +#define bM4_MPU_RGD10_MPURGADDR4 (*((volatile unsigned int*)(0x42A00524UL))) +#define bM4_MPU_RGD10_MPURGADDR5 (*((volatile unsigned int*)(0x42A00528UL))) +#define bM4_MPU_RGD10_MPURGADDR6 (*((volatile unsigned int*)(0x42A0052CUL))) +#define bM4_MPU_RGD10_MPURGADDR7 (*((volatile unsigned int*)(0x42A00530UL))) +#define bM4_MPU_RGD10_MPURGADDR8 (*((volatile unsigned int*)(0x42A00534UL))) +#define bM4_MPU_RGD10_MPURGADDR9 (*((volatile unsigned int*)(0x42A00538UL))) +#define bM4_MPU_RGD10_MPURGADDR10 (*((volatile unsigned int*)(0x42A0053CUL))) +#define bM4_MPU_RGD10_MPURGADDR11 (*((volatile unsigned int*)(0x42A00540UL))) +#define bM4_MPU_RGD10_MPURGADDR12 (*((volatile unsigned int*)(0x42A00544UL))) +#define bM4_MPU_RGD10_MPURGADDR13 (*((volatile unsigned int*)(0x42A00548UL))) +#define bM4_MPU_RGD10_MPURGADDR14 (*((volatile unsigned int*)(0x42A0054CUL))) +#define bM4_MPU_RGD10_MPURGADDR15 (*((volatile unsigned int*)(0x42A00550UL))) +#define bM4_MPU_RGD10_MPURGADDR16 (*((volatile unsigned int*)(0x42A00554UL))) +#define bM4_MPU_RGD10_MPURGADDR17 (*((volatile unsigned int*)(0x42A00558UL))) +#define bM4_MPU_RGD10_MPURGADDR18 (*((volatile unsigned int*)(0x42A0055CUL))) +#define bM4_MPU_RGD10_MPURGADDR19 (*((volatile unsigned int*)(0x42A00560UL))) +#define bM4_MPU_RGD10_MPURGADDR20 (*((volatile unsigned int*)(0x42A00564UL))) +#define bM4_MPU_RGD10_MPURGADDR21 (*((volatile unsigned int*)(0x42A00568UL))) +#define bM4_MPU_RGD10_MPURGADDR22 (*((volatile unsigned int*)(0x42A0056CUL))) +#define bM4_MPU_RGD10_MPURGADDR23 (*((volatile unsigned int*)(0x42A00570UL))) +#define bM4_MPU_RGD10_MPURGADDR24 (*((volatile unsigned int*)(0x42A00574UL))) +#define bM4_MPU_RGD10_MPURGADDR25 (*((volatile unsigned int*)(0x42A00578UL))) +#define bM4_MPU_RGD10_MPURGADDR26 (*((volatile unsigned int*)(0x42A0057CUL))) +#define bM4_MPU_RGD11_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00580UL))) +#define bM4_MPU_RGD11_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00584UL))) +#define bM4_MPU_RGD11_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00588UL))) +#define bM4_MPU_RGD11_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0058CUL))) +#define bM4_MPU_RGD11_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00590UL))) +#define bM4_MPU_RGD11_MPURGADDR0 (*((volatile unsigned int*)(0x42A00594UL))) +#define bM4_MPU_RGD11_MPURGADDR1 (*((volatile unsigned int*)(0x42A00598UL))) +#define bM4_MPU_RGD11_MPURGADDR2 (*((volatile unsigned int*)(0x42A0059CUL))) +#define bM4_MPU_RGD11_MPURGADDR3 (*((volatile unsigned int*)(0x42A005A0UL))) +#define bM4_MPU_RGD11_MPURGADDR4 (*((volatile unsigned int*)(0x42A005A4UL))) +#define bM4_MPU_RGD11_MPURGADDR5 (*((volatile unsigned int*)(0x42A005A8UL))) +#define bM4_MPU_RGD11_MPURGADDR6 (*((volatile unsigned int*)(0x42A005ACUL))) +#define bM4_MPU_RGD11_MPURGADDR7 (*((volatile unsigned int*)(0x42A005B0UL))) +#define bM4_MPU_RGD11_MPURGADDR8 (*((volatile unsigned int*)(0x42A005B4UL))) +#define bM4_MPU_RGD11_MPURGADDR9 (*((volatile unsigned int*)(0x42A005B8UL))) +#define bM4_MPU_RGD11_MPURGADDR10 (*((volatile unsigned int*)(0x42A005BCUL))) +#define bM4_MPU_RGD11_MPURGADDR11 (*((volatile unsigned int*)(0x42A005C0UL))) +#define bM4_MPU_RGD11_MPURGADDR12 (*((volatile unsigned int*)(0x42A005C4UL))) +#define bM4_MPU_RGD11_MPURGADDR13 (*((volatile unsigned int*)(0x42A005C8UL))) +#define bM4_MPU_RGD11_MPURGADDR14 (*((volatile unsigned int*)(0x42A005CCUL))) +#define bM4_MPU_RGD11_MPURGADDR15 (*((volatile unsigned int*)(0x42A005D0UL))) +#define bM4_MPU_RGD11_MPURGADDR16 (*((volatile unsigned int*)(0x42A005D4UL))) +#define bM4_MPU_RGD11_MPURGADDR17 (*((volatile unsigned int*)(0x42A005D8UL))) +#define bM4_MPU_RGD11_MPURGADDR18 (*((volatile unsigned int*)(0x42A005DCUL))) +#define bM4_MPU_RGD11_MPURGADDR19 (*((volatile unsigned int*)(0x42A005E0UL))) +#define bM4_MPU_RGD11_MPURGADDR20 (*((volatile unsigned int*)(0x42A005E4UL))) +#define bM4_MPU_RGD11_MPURGADDR21 (*((volatile unsigned int*)(0x42A005E8UL))) +#define bM4_MPU_RGD11_MPURGADDR22 (*((volatile unsigned int*)(0x42A005ECUL))) +#define bM4_MPU_RGD11_MPURGADDR23 (*((volatile unsigned int*)(0x42A005F0UL))) +#define bM4_MPU_RGD11_MPURGADDR24 (*((volatile unsigned int*)(0x42A005F4UL))) +#define bM4_MPU_RGD11_MPURGADDR25 (*((volatile unsigned int*)(0x42A005F8UL))) +#define bM4_MPU_RGD11_MPURGADDR26 (*((volatile unsigned int*)(0x42A005FCUL))) +#define bM4_MPU_RGD12_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00600UL))) +#define bM4_MPU_RGD12_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00604UL))) +#define bM4_MPU_RGD12_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00608UL))) +#define bM4_MPU_RGD12_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0060CUL))) +#define bM4_MPU_RGD12_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00610UL))) +#define bM4_MPU_RGD12_MPURGADDR0 (*((volatile unsigned int*)(0x42A00614UL))) +#define bM4_MPU_RGD12_MPURGADDR1 (*((volatile unsigned int*)(0x42A00618UL))) +#define bM4_MPU_RGD12_MPURGADDR2 (*((volatile unsigned int*)(0x42A0061CUL))) +#define bM4_MPU_RGD12_MPURGADDR3 (*((volatile unsigned int*)(0x42A00620UL))) +#define bM4_MPU_RGD12_MPURGADDR4 (*((volatile unsigned int*)(0x42A00624UL))) +#define bM4_MPU_RGD12_MPURGADDR5 (*((volatile unsigned int*)(0x42A00628UL))) +#define bM4_MPU_RGD12_MPURGADDR6 (*((volatile unsigned int*)(0x42A0062CUL))) +#define bM4_MPU_RGD12_MPURGADDR7 (*((volatile unsigned int*)(0x42A00630UL))) +#define bM4_MPU_RGD12_MPURGADDR8 (*((volatile unsigned int*)(0x42A00634UL))) +#define bM4_MPU_RGD12_MPURGADDR9 (*((volatile unsigned int*)(0x42A00638UL))) +#define bM4_MPU_RGD12_MPURGADDR10 (*((volatile unsigned int*)(0x42A0063CUL))) +#define bM4_MPU_RGD12_MPURGADDR11 (*((volatile unsigned int*)(0x42A00640UL))) +#define bM4_MPU_RGD12_MPURGADDR12 (*((volatile unsigned int*)(0x42A00644UL))) +#define bM4_MPU_RGD12_MPURGADDR13 (*((volatile unsigned int*)(0x42A00648UL))) +#define bM4_MPU_RGD12_MPURGADDR14 (*((volatile unsigned int*)(0x42A0064CUL))) +#define bM4_MPU_RGD12_MPURGADDR15 (*((volatile unsigned int*)(0x42A00650UL))) +#define bM4_MPU_RGD12_MPURGADDR16 (*((volatile unsigned int*)(0x42A00654UL))) +#define bM4_MPU_RGD12_MPURGADDR17 (*((volatile unsigned int*)(0x42A00658UL))) +#define bM4_MPU_RGD12_MPURGADDR18 (*((volatile unsigned int*)(0x42A0065CUL))) +#define bM4_MPU_RGD12_MPURGADDR19 (*((volatile unsigned int*)(0x42A00660UL))) +#define bM4_MPU_RGD12_MPURGADDR20 (*((volatile unsigned int*)(0x42A00664UL))) +#define bM4_MPU_RGD12_MPURGADDR21 (*((volatile unsigned int*)(0x42A00668UL))) +#define bM4_MPU_RGD12_MPURGADDR22 (*((volatile unsigned int*)(0x42A0066CUL))) +#define bM4_MPU_RGD12_MPURGADDR23 (*((volatile unsigned int*)(0x42A00670UL))) +#define bM4_MPU_RGD12_MPURGADDR24 (*((volatile unsigned int*)(0x42A00674UL))) +#define bM4_MPU_RGD12_MPURGADDR25 (*((volatile unsigned int*)(0x42A00678UL))) +#define bM4_MPU_RGD12_MPURGADDR26 (*((volatile unsigned int*)(0x42A0067CUL))) +#define bM4_MPU_RGD13_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00680UL))) +#define bM4_MPU_RGD13_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00684UL))) +#define bM4_MPU_RGD13_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00688UL))) +#define bM4_MPU_RGD13_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0068CUL))) +#define bM4_MPU_RGD13_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00690UL))) +#define bM4_MPU_RGD13_MPURGADDR0 (*((volatile unsigned int*)(0x42A00694UL))) +#define bM4_MPU_RGD13_MPURGADDR1 (*((volatile unsigned int*)(0x42A00698UL))) +#define bM4_MPU_RGD13_MPURGADDR2 (*((volatile unsigned int*)(0x42A0069CUL))) +#define bM4_MPU_RGD13_MPURGADDR3 (*((volatile unsigned int*)(0x42A006A0UL))) +#define bM4_MPU_RGD13_MPURGADDR4 (*((volatile unsigned int*)(0x42A006A4UL))) +#define bM4_MPU_RGD13_MPURGADDR5 (*((volatile unsigned int*)(0x42A006A8UL))) +#define bM4_MPU_RGD13_MPURGADDR6 (*((volatile unsigned int*)(0x42A006ACUL))) +#define bM4_MPU_RGD13_MPURGADDR7 (*((volatile unsigned int*)(0x42A006B0UL))) +#define bM4_MPU_RGD13_MPURGADDR8 (*((volatile unsigned int*)(0x42A006B4UL))) +#define bM4_MPU_RGD13_MPURGADDR9 (*((volatile unsigned int*)(0x42A006B8UL))) +#define bM4_MPU_RGD13_MPURGADDR10 (*((volatile unsigned int*)(0x42A006BCUL))) +#define bM4_MPU_RGD13_MPURGADDR11 (*((volatile unsigned int*)(0x42A006C0UL))) +#define bM4_MPU_RGD13_MPURGADDR12 (*((volatile unsigned int*)(0x42A006C4UL))) +#define bM4_MPU_RGD13_MPURGADDR13 (*((volatile unsigned int*)(0x42A006C8UL))) +#define bM4_MPU_RGD13_MPURGADDR14 (*((volatile unsigned int*)(0x42A006CCUL))) +#define bM4_MPU_RGD13_MPURGADDR15 (*((volatile unsigned int*)(0x42A006D0UL))) +#define bM4_MPU_RGD13_MPURGADDR16 (*((volatile unsigned int*)(0x42A006D4UL))) +#define bM4_MPU_RGD13_MPURGADDR17 (*((volatile unsigned int*)(0x42A006D8UL))) +#define bM4_MPU_RGD13_MPURGADDR18 (*((volatile unsigned int*)(0x42A006DCUL))) +#define bM4_MPU_RGD13_MPURGADDR19 (*((volatile unsigned int*)(0x42A006E0UL))) +#define bM4_MPU_RGD13_MPURGADDR20 (*((volatile unsigned int*)(0x42A006E4UL))) +#define bM4_MPU_RGD13_MPURGADDR21 (*((volatile unsigned int*)(0x42A006E8UL))) +#define bM4_MPU_RGD13_MPURGADDR22 (*((volatile unsigned int*)(0x42A006ECUL))) +#define bM4_MPU_RGD13_MPURGADDR23 (*((volatile unsigned int*)(0x42A006F0UL))) +#define bM4_MPU_RGD13_MPURGADDR24 (*((volatile unsigned int*)(0x42A006F4UL))) +#define bM4_MPU_RGD13_MPURGADDR25 (*((volatile unsigned int*)(0x42A006F8UL))) +#define bM4_MPU_RGD13_MPURGADDR26 (*((volatile unsigned int*)(0x42A006FCUL))) +#define bM4_MPU_RGD14_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00700UL))) +#define bM4_MPU_RGD14_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00704UL))) +#define bM4_MPU_RGD14_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00708UL))) +#define bM4_MPU_RGD14_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0070CUL))) +#define bM4_MPU_RGD14_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00710UL))) +#define bM4_MPU_RGD14_MPURGADDR0 (*((volatile unsigned int*)(0x42A00714UL))) +#define bM4_MPU_RGD14_MPURGADDR1 (*((volatile unsigned int*)(0x42A00718UL))) +#define bM4_MPU_RGD14_MPURGADDR2 (*((volatile unsigned int*)(0x42A0071CUL))) +#define bM4_MPU_RGD14_MPURGADDR3 (*((volatile unsigned int*)(0x42A00720UL))) +#define bM4_MPU_RGD14_MPURGADDR4 (*((volatile unsigned int*)(0x42A00724UL))) +#define bM4_MPU_RGD14_MPURGADDR5 (*((volatile unsigned int*)(0x42A00728UL))) +#define bM4_MPU_RGD14_MPURGADDR6 (*((volatile unsigned int*)(0x42A0072CUL))) +#define bM4_MPU_RGD14_MPURGADDR7 (*((volatile unsigned int*)(0x42A00730UL))) +#define bM4_MPU_RGD14_MPURGADDR8 (*((volatile unsigned int*)(0x42A00734UL))) +#define bM4_MPU_RGD14_MPURGADDR9 (*((volatile unsigned int*)(0x42A00738UL))) +#define bM4_MPU_RGD14_MPURGADDR10 (*((volatile unsigned int*)(0x42A0073CUL))) +#define bM4_MPU_RGD14_MPURGADDR11 (*((volatile unsigned int*)(0x42A00740UL))) +#define bM4_MPU_RGD14_MPURGADDR12 (*((volatile unsigned int*)(0x42A00744UL))) +#define bM4_MPU_RGD14_MPURGADDR13 (*((volatile unsigned int*)(0x42A00748UL))) +#define bM4_MPU_RGD14_MPURGADDR14 (*((volatile unsigned int*)(0x42A0074CUL))) +#define bM4_MPU_RGD14_MPURGADDR15 (*((volatile unsigned int*)(0x42A00750UL))) +#define bM4_MPU_RGD14_MPURGADDR16 (*((volatile unsigned int*)(0x42A00754UL))) +#define bM4_MPU_RGD14_MPURGADDR17 (*((volatile unsigned int*)(0x42A00758UL))) +#define bM4_MPU_RGD14_MPURGADDR18 (*((volatile unsigned int*)(0x42A0075CUL))) +#define bM4_MPU_RGD14_MPURGADDR19 (*((volatile unsigned int*)(0x42A00760UL))) +#define bM4_MPU_RGD14_MPURGADDR20 (*((volatile unsigned int*)(0x42A00764UL))) +#define bM4_MPU_RGD14_MPURGADDR21 (*((volatile unsigned int*)(0x42A00768UL))) +#define bM4_MPU_RGD14_MPURGADDR22 (*((volatile unsigned int*)(0x42A0076CUL))) +#define bM4_MPU_RGD14_MPURGADDR23 (*((volatile unsigned int*)(0x42A00770UL))) +#define bM4_MPU_RGD14_MPURGADDR24 (*((volatile unsigned int*)(0x42A00774UL))) +#define bM4_MPU_RGD14_MPURGADDR25 (*((volatile unsigned int*)(0x42A00778UL))) +#define bM4_MPU_RGD14_MPURGADDR26 (*((volatile unsigned int*)(0x42A0077CUL))) +#define bM4_MPU_RGD15_MPURGSIZE0 (*((volatile unsigned int*)(0x42A00780UL))) +#define bM4_MPU_RGD15_MPURGSIZE1 (*((volatile unsigned int*)(0x42A00784UL))) +#define bM4_MPU_RGD15_MPURGSIZE2 (*((volatile unsigned int*)(0x42A00788UL))) +#define bM4_MPU_RGD15_MPURGSIZE3 (*((volatile unsigned int*)(0x42A0078CUL))) +#define bM4_MPU_RGD15_MPURGSIZE4 (*((volatile unsigned int*)(0x42A00790UL))) +#define bM4_MPU_RGD15_MPURGADDR0 (*((volatile unsigned int*)(0x42A00794UL))) +#define bM4_MPU_RGD15_MPURGADDR1 (*((volatile unsigned int*)(0x42A00798UL))) +#define bM4_MPU_RGD15_MPURGADDR2 (*((volatile unsigned int*)(0x42A0079CUL))) +#define bM4_MPU_RGD15_MPURGADDR3 (*((volatile unsigned int*)(0x42A007A0UL))) +#define bM4_MPU_RGD15_MPURGADDR4 (*((volatile unsigned int*)(0x42A007A4UL))) +#define bM4_MPU_RGD15_MPURGADDR5 (*((volatile unsigned int*)(0x42A007A8UL))) +#define bM4_MPU_RGD15_MPURGADDR6 (*((volatile unsigned int*)(0x42A007ACUL))) +#define bM4_MPU_RGD15_MPURGADDR7 (*((volatile unsigned int*)(0x42A007B0UL))) +#define bM4_MPU_RGD15_MPURGADDR8 (*((volatile unsigned int*)(0x42A007B4UL))) +#define bM4_MPU_RGD15_MPURGADDR9 (*((volatile unsigned int*)(0x42A007B8UL))) +#define bM4_MPU_RGD15_MPURGADDR10 (*((volatile unsigned int*)(0x42A007BCUL))) +#define bM4_MPU_RGD15_MPURGADDR11 (*((volatile unsigned int*)(0x42A007C0UL))) +#define bM4_MPU_RGD15_MPURGADDR12 (*((volatile unsigned int*)(0x42A007C4UL))) +#define bM4_MPU_RGD15_MPURGADDR13 (*((volatile unsigned int*)(0x42A007C8UL))) +#define bM4_MPU_RGD15_MPURGADDR14 (*((volatile unsigned int*)(0x42A007CCUL))) +#define bM4_MPU_RGD15_MPURGADDR15 (*((volatile unsigned int*)(0x42A007D0UL))) +#define bM4_MPU_RGD15_MPURGADDR16 (*((volatile unsigned int*)(0x42A007D4UL))) +#define bM4_MPU_RGD15_MPURGADDR17 (*((volatile unsigned int*)(0x42A007D8UL))) +#define bM4_MPU_RGD15_MPURGADDR18 (*((volatile unsigned int*)(0x42A007DCUL))) +#define bM4_MPU_RGD15_MPURGADDR19 (*((volatile unsigned int*)(0x42A007E0UL))) +#define bM4_MPU_RGD15_MPURGADDR20 (*((volatile unsigned int*)(0x42A007E4UL))) +#define bM4_MPU_RGD15_MPURGADDR21 (*((volatile unsigned int*)(0x42A007E8UL))) +#define bM4_MPU_RGD15_MPURGADDR22 (*((volatile unsigned int*)(0x42A007ECUL))) +#define bM4_MPU_RGD15_MPURGADDR23 (*((volatile unsigned int*)(0x42A007F0UL))) +#define bM4_MPU_RGD15_MPURGADDR24 (*((volatile unsigned int*)(0x42A007F4UL))) +#define bM4_MPU_RGD15_MPURGADDR25 (*((volatile unsigned int*)(0x42A007F8UL))) +#define bM4_MPU_RGD15_MPURGADDR26 (*((volatile unsigned int*)(0x42A007FCUL))) +#define bM4_MPU_RGCR0_S2RG0RP (*((volatile unsigned int*)(0x42A00800UL))) +#define bM4_MPU_RGCR0_S2RG0WP (*((volatile unsigned int*)(0x42A00804UL))) +#define bM4_MPU_RGCR0_S2RG0E (*((volatile unsigned int*)(0x42A0081CUL))) +#define bM4_MPU_RGCR0_S1RG0RP (*((volatile unsigned int*)(0x42A00820UL))) +#define bM4_MPU_RGCR0_S1RG0WP (*((volatile unsigned int*)(0x42A00824UL))) +#define bM4_MPU_RGCR0_S1RG0E (*((volatile unsigned int*)(0x42A0083CUL))) +#define bM4_MPU_RGCR0_FRG0RP (*((volatile unsigned int*)(0x42A00840UL))) +#define bM4_MPU_RGCR0_FRG0WP (*((volatile unsigned int*)(0x42A00844UL))) +#define bM4_MPU_RGCR0_FRG0E (*((volatile unsigned int*)(0x42A0085CUL))) +#define bM4_MPU_RGCR1_S2RG1RP (*((volatile unsigned int*)(0x42A00880UL))) +#define bM4_MPU_RGCR1_S2RG1WP (*((volatile unsigned int*)(0x42A00884UL))) +#define bM4_MPU_RGCR1_S2RG1E (*((volatile unsigned int*)(0x42A0089CUL))) +#define bM4_MPU_RGCR1_S1RG1RP (*((volatile unsigned int*)(0x42A008A0UL))) +#define bM4_MPU_RGCR1_S1RG1WP (*((volatile unsigned int*)(0x42A008A4UL))) +#define bM4_MPU_RGCR1_S1RG1E (*((volatile unsigned int*)(0x42A008BCUL))) +#define bM4_MPU_RGCR1_FRG1RP (*((volatile unsigned int*)(0x42A008C0UL))) +#define bM4_MPU_RGCR1_FRG1WP (*((volatile unsigned int*)(0x42A008C4UL))) +#define bM4_MPU_RGCR1_FRG1E (*((volatile unsigned int*)(0x42A008DCUL))) +#define bM4_MPU_RGCR2_S2RG2RP (*((volatile unsigned int*)(0x42A00900UL))) +#define bM4_MPU_RGCR2_S2RG2WP (*((volatile unsigned int*)(0x42A00904UL))) +#define bM4_MPU_RGCR2_S2RG2E (*((volatile unsigned int*)(0x42A0091CUL))) +#define bM4_MPU_RGCR2_S1RG2RP (*((volatile unsigned int*)(0x42A00920UL))) +#define bM4_MPU_RGCR2_S1RG2WP (*((volatile unsigned int*)(0x42A00924UL))) +#define bM4_MPU_RGCR2_S1RG2E (*((volatile unsigned int*)(0x42A0093CUL))) +#define bM4_MPU_RGCR2_FRG2RP (*((volatile unsigned int*)(0x42A00940UL))) +#define bM4_MPU_RGCR2_FRG2WP (*((volatile unsigned int*)(0x42A00944UL))) +#define bM4_MPU_RGCR2_FRG2E (*((volatile unsigned int*)(0x42A0095CUL))) +#define bM4_MPU_RGCR3_S2RG3RP (*((volatile unsigned int*)(0x42A00980UL))) +#define bM4_MPU_RGCR3_S2RG3WP (*((volatile unsigned int*)(0x42A00984UL))) +#define bM4_MPU_RGCR3_S2RG3E (*((volatile unsigned int*)(0x42A0099CUL))) +#define bM4_MPU_RGCR3_S1RG3RP (*((volatile unsigned int*)(0x42A009A0UL))) +#define bM4_MPU_RGCR3_S1RG3WP (*((volatile unsigned int*)(0x42A009A4UL))) +#define bM4_MPU_RGCR3_S1RG3E (*((volatile unsigned int*)(0x42A009BCUL))) +#define bM4_MPU_RGCR3_FRG3RP (*((volatile unsigned int*)(0x42A009C0UL))) +#define bM4_MPU_RGCR3_FRG3WP (*((volatile unsigned int*)(0x42A009C4UL))) +#define bM4_MPU_RGCR3_FRG3E (*((volatile unsigned int*)(0x42A009DCUL))) +#define bM4_MPU_RGCR4_S2RG4RP (*((volatile unsigned int*)(0x42A00A00UL))) +#define bM4_MPU_RGCR4_S2RG4WP (*((volatile unsigned int*)(0x42A00A04UL))) +#define bM4_MPU_RGCR4_S2RG4E (*((volatile unsigned int*)(0x42A00A1CUL))) +#define bM4_MPU_RGCR4_S1RG4RP (*((volatile unsigned int*)(0x42A00A20UL))) +#define bM4_MPU_RGCR4_S1RG4WP (*((volatile unsigned int*)(0x42A00A24UL))) +#define bM4_MPU_RGCR4_S1RG4E (*((volatile unsigned int*)(0x42A00A3CUL))) +#define bM4_MPU_RGCR4_FRG4RP (*((volatile unsigned int*)(0x42A00A40UL))) +#define bM4_MPU_RGCR4_FRG4WP (*((volatile unsigned int*)(0x42A00A44UL))) +#define bM4_MPU_RGCR4_FRG4E (*((volatile unsigned int*)(0x42A00A5CUL))) +#define bM4_MPU_RGCR5_S2RG5RP (*((volatile unsigned int*)(0x42A00A80UL))) +#define bM4_MPU_RGCR5_S2RG5WP (*((volatile unsigned int*)(0x42A00A84UL))) +#define bM4_MPU_RGCR5_S2RG5E (*((volatile unsigned int*)(0x42A00A9CUL))) +#define bM4_MPU_RGCR5_S1RG5RP (*((volatile unsigned int*)(0x42A00AA0UL))) +#define bM4_MPU_RGCR5_S1RG5WP (*((volatile unsigned int*)(0x42A00AA4UL))) +#define bM4_MPU_RGCR5_S1RG5E (*((volatile unsigned int*)(0x42A00ABCUL))) +#define bM4_MPU_RGCR5_FRG5RP (*((volatile unsigned int*)(0x42A00AC0UL))) +#define bM4_MPU_RGCR5_FRG5WP (*((volatile unsigned int*)(0x42A00AC4UL))) +#define bM4_MPU_RGCR5_FRG5E (*((volatile unsigned int*)(0x42A00ADCUL))) +#define bM4_MPU_RGCR6_S2RG6RP (*((volatile unsigned int*)(0x42A00B00UL))) +#define bM4_MPU_RGCR6_S2RG6WP (*((volatile unsigned int*)(0x42A00B04UL))) +#define bM4_MPU_RGCR6_S2RG6E (*((volatile unsigned int*)(0x42A00B1CUL))) +#define bM4_MPU_RGCR6_S1RG6RP (*((volatile unsigned int*)(0x42A00B20UL))) +#define bM4_MPU_RGCR6_S1RG6WP (*((volatile unsigned int*)(0x42A00B24UL))) +#define bM4_MPU_RGCR6_S1RG6E (*((volatile unsigned int*)(0x42A00B3CUL))) +#define bM4_MPU_RGCR6_FRG6RP (*((volatile unsigned int*)(0x42A00B40UL))) +#define bM4_MPU_RGCR6_FRG6WP (*((volatile unsigned int*)(0x42A00B44UL))) +#define bM4_MPU_RGCR6_FRG6E (*((volatile unsigned int*)(0x42A00B5CUL))) +#define bM4_MPU_RGCR7_S2RG7RP (*((volatile unsigned int*)(0x42A00B80UL))) +#define bM4_MPU_RGCR7_S2RG7WP (*((volatile unsigned int*)(0x42A00B84UL))) +#define bM4_MPU_RGCR7_S2RG7E (*((volatile unsigned int*)(0x42A00B9CUL))) +#define bM4_MPU_RGCR7_S1RG7RP (*((volatile unsigned int*)(0x42A00BA0UL))) +#define bM4_MPU_RGCR7_S1RG7WP (*((volatile unsigned int*)(0x42A00BA4UL))) +#define bM4_MPU_RGCR7_S1RG7E (*((volatile unsigned int*)(0x42A00BBCUL))) +#define bM4_MPU_RGCR7_FRG7RP (*((volatile unsigned int*)(0x42A00BC0UL))) +#define bM4_MPU_RGCR7_FRG7WP (*((volatile unsigned int*)(0x42A00BC4UL))) +#define bM4_MPU_RGCR7_FRG7E (*((volatile unsigned int*)(0x42A00BDCUL))) +#define bM4_MPU_RGCR8_S2RG8RP (*((volatile unsigned int*)(0x42A00C00UL))) +#define bM4_MPU_RGCR8_S2RG8WP (*((volatile unsigned int*)(0x42A00C04UL))) +#define bM4_MPU_RGCR8_S2RG8E (*((volatile unsigned int*)(0x42A00C1CUL))) +#define bM4_MPU_RGCR8_S1RG8RP (*((volatile unsigned int*)(0x42A00C20UL))) +#define bM4_MPU_RGCR8_S1RG8WP (*((volatile unsigned int*)(0x42A00C24UL))) +#define bM4_MPU_RGCR8_S1RG8E (*((volatile unsigned int*)(0x42A00C3CUL))) +#define bM4_MPU_RGCR9_S2RG9RP (*((volatile unsigned int*)(0x42A00C80UL))) +#define bM4_MPU_RGCR9_S2RG9WP (*((volatile unsigned int*)(0x42A00C84UL))) +#define bM4_MPU_RGCR9_S2RG9E (*((volatile unsigned int*)(0x42A00C9CUL))) +#define bM4_MPU_RGCR9_S1RG9RP (*((volatile unsigned int*)(0x42A00CA0UL))) +#define bM4_MPU_RGCR9_S1RG9WP (*((volatile unsigned int*)(0x42A00CA4UL))) +#define bM4_MPU_RGCR9_S1RG9E (*((volatile unsigned int*)(0x42A00CBCUL))) +#define bM4_MPU_RGCR10_S2RG10RP (*((volatile unsigned int*)(0x42A00D00UL))) +#define bM4_MPU_RGCR10_S2RG10WP (*((volatile unsigned int*)(0x42A00D04UL))) +#define bM4_MPU_RGCR10_S2RG10E (*((volatile unsigned int*)(0x42A00D1CUL))) +#define bM4_MPU_RGCR10_S1RG10RP (*((volatile unsigned int*)(0x42A00D20UL))) +#define bM4_MPU_RGCR10_S1RG10WP (*((volatile unsigned int*)(0x42A00D24UL))) +#define bM4_MPU_RGCR10_S1RG10E (*((volatile unsigned int*)(0x42A00D3CUL))) +#define bM4_MPU_RGCR11_S2RG11RP (*((volatile unsigned int*)(0x42A00D80UL))) +#define bM4_MPU_RGCR11_S2RG11WP (*((volatile unsigned int*)(0x42A00D84UL))) +#define bM4_MPU_RGCR11_S2RG11E (*((volatile unsigned int*)(0x42A00D9CUL))) +#define bM4_MPU_RGCR11_S1RG11RP (*((volatile unsigned int*)(0x42A00DA0UL))) +#define bM4_MPU_RGCR11_S1RG11WP (*((volatile unsigned int*)(0x42A00DA4UL))) +#define bM4_MPU_RGCR11_S1RG11E (*((volatile unsigned int*)(0x42A00DBCUL))) +#define bM4_MPU_RGCR12_S2RG12RP (*((volatile unsigned int*)(0x42A00E00UL))) +#define bM4_MPU_RGCR12_S2RG12WP (*((volatile unsigned int*)(0x42A00E04UL))) +#define bM4_MPU_RGCR12_S2RG12E (*((volatile unsigned int*)(0x42A00E1CUL))) +#define bM4_MPU_RGCR12_S1RG12RP (*((volatile unsigned int*)(0x42A00E20UL))) +#define bM4_MPU_RGCR12_S1RG12WP (*((volatile unsigned int*)(0x42A00E24UL))) +#define bM4_MPU_RGCR12_S1RG12E (*((volatile unsigned int*)(0x42A00E3CUL))) +#define bM4_MPU_RGCR13_S2RG13RP (*((volatile unsigned int*)(0x42A00E80UL))) +#define bM4_MPU_RGCR13_S2RG13WP (*((volatile unsigned int*)(0x42A00E84UL))) +#define bM4_MPU_RGCR13_S2RG13E (*((volatile unsigned int*)(0x42A00E9CUL))) +#define bM4_MPU_RGCR13_S1RG13RP (*((volatile unsigned int*)(0x42A00EA0UL))) +#define bM4_MPU_RGCR13_S1RG13WP (*((volatile unsigned int*)(0x42A00EA4UL))) +#define bM4_MPU_RGCR13_S1RG13E (*((volatile unsigned int*)(0x42A00EBCUL))) +#define bM4_MPU_RGCR14_S2RG14RP (*((volatile unsigned int*)(0x42A00F00UL))) +#define bM4_MPU_RGCR14_S2RG14WP (*((volatile unsigned int*)(0x42A00F04UL))) +#define bM4_MPU_RGCR14_S2RG14E (*((volatile unsigned int*)(0x42A00F1CUL))) +#define bM4_MPU_RGCR14_S1RG14RP (*((volatile unsigned int*)(0x42A00F20UL))) +#define bM4_MPU_RGCR14_S1RG14WP (*((volatile unsigned int*)(0x42A00F24UL))) +#define bM4_MPU_RGCR14_S1RG14E (*((volatile unsigned int*)(0x42A00F3CUL))) +#define bM4_MPU_RGCR15_S2RG15RP (*((volatile unsigned int*)(0x42A00F80UL))) +#define bM4_MPU_RGCR15_S2RG15WP (*((volatile unsigned int*)(0x42A00F84UL))) +#define bM4_MPU_RGCR15_S2RG15E (*((volatile unsigned int*)(0x42A00F9CUL))) +#define bM4_MPU_RGCR15_S1RG15RP (*((volatile unsigned int*)(0x42A00FA0UL))) +#define bM4_MPU_RGCR15_S1RG15WP (*((volatile unsigned int*)(0x42A00FA4UL))) +#define bM4_MPU_RGCR15_S1RG15E (*((volatile unsigned int*)(0x42A00FBCUL))) +#define bM4_MPU_CR_SMPU2BRP (*((volatile unsigned int*)(0x42A01000UL))) +#define bM4_MPU_CR_SMPU2BWP (*((volatile unsigned int*)(0x42A01004UL))) +#define bM4_MPU_CR_SMPU2ACT0 (*((volatile unsigned int*)(0x42A01008UL))) +#define bM4_MPU_CR_SMPU2ACT1 (*((volatile unsigned int*)(0x42A0100CUL))) +#define bM4_MPU_CR_SMPU2E (*((volatile unsigned int*)(0x42A0101CUL))) +#define bM4_MPU_CR_SMPU1BRP (*((volatile unsigned int*)(0x42A01020UL))) +#define bM4_MPU_CR_SMPU1BWP (*((volatile unsigned int*)(0x42A01024UL))) +#define bM4_MPU_CR_SMPU1ACT0 (*((volatile unsigned int*)(0x42A01028UL))) +#define bM4_MPU_CR_SMPU1ACT1 (*((volatile unsigned int*)(0x42A0102CUL))) +#define bM4_MPU_CR_SMPU1E (*((volatile unsigned int*)(0x42A0103CUL))) +#define bM4_MPU_CR_FMPUBRP (*((volatile unsigned int*)(0x42A01040UL))) +#define bM4_MPU_CR_FMPUBWP (*((volatile unsigned int*)(0x42A01044UL))) +#define bM4_MPU_CR_FMPUACT0 (*((volatile unsigned int*)(0x42A01048UL))) +#define bM4_MPU_CR_FMPUACT1 (*((volatile unsigned int*)(0x42A0104CUL))) +#define bM4_MPU_CR_FMPUE (*((volatile unsigned int*)(0x42A0105CUL))) +#define bM4_MPU_SR_SMPU2EAF (*((volatile unsigned int*)(0x42A01080UL))) +#define bM4_MPU_SR_SMPU1EAF (*((volatile unsigned int*)(0x42A010A0UL))) +#define bM4_MPU_SR_FMPUEAF (*((volatile unsigned int*)(0x42A010C0UL))) +#define bM4_MPU_ECLR_SMPU2ECLR (*((volatile unsigned int*)(0x42A01100UL))) +#define bM4_MPU_ECLR_SMPU1ECLR (*((volatile unsigned int*)(0x42A01120UL))) +#define bM4_MPU_ECLR_FMPUECLR (*((volatile unsigned int*)(0x42A01140UL))) +#define bM4_MPU_WP_MPUWE (*((volatile unsigned int*)(0x42A01180UL))) +#define bM4_MPU_WP_WKEY0 (*((volatile unsigned int*)(0x42A01184UL))) +#define bM4_MPU_WP_WKEY1 (*((volatile unsigned int*)(0x42A01188UL))) +#define bM4_MPU_WP_WKEY2 (*((volatile unsigned int*)(0x42A0118CUL))) +#define bM4_MPU_WP_WKEY3 (*((volatile unsigned int*)(0x42A01190UL))) +#define bM4_MPU_WP_WKEY4 (*((volatile unsigned int*)(0x42A01194UL))) +#define bM4_MPU_WP_WKEY5 (*((volatile unsigned int*)(0x42A01198UL))) +#define bM4_MPU_WP_WKEY6 (*((volatile unsigned int*)(0x42A0119CUL))) +#define bM4_MPU_WP_WKEY7 (*((volatile unsigned int*)(0x42A011A0UL))) +#define bM4_MPU_WP_WKEY8 (*((volatile unsigned int*)(0x42A011A4UL))) +#define bM4_MPU_WP_WKEY9 (*((volatile unsigned int*)(0x42A011A8UL))) +#define bM4_MPU_WP_WKEY10 (*((volatile unsigned int*)(0x42A011ACUL))) +#define bM4_MPU_WP_WKEY11 (*((volatile unsigned int*)(0x42A011B0UL))) +#define bM4_MPU_WP_WKEY12 (*((volatile unsigned int*)(0x42A011B4UL))) +#define bM4_MPU_WP_WKEY13 (*((volatile unsigned int*)(0x42A011B8UL))) +#define bM4_MPU_WP_WKEY14 (*((volatile unsigned int*)(0x42A011BCUL))) +#define bM4_MSTP_FCG0_SRAMH (*((volatile unsigned int*)(0x42900000UL))) +#define bM4_MSTP_FCG0_SRAM12 (*((volatile unsigned int*)(0x42900010UL))) +#define bM4_MSTP_FCG0_SRAM3 (*((volatile unsigned int*)(0x42900020UL))) +#define bM4_MSTP_FCG0_SRAMRET (*((volatile unsigned int*)(0x42900028UL))) +#define bM4_MSTP_FCG0_DMA1 (*((volatile unsigned int*)(0x42900038UL))) +#define bM4_MSTP_FCG0_DMA2 (*((volatile unsigned int*)(0x4290003CUL))) +#define bM4_MSTP_FCG0_FCM (*((volatile unsigned int*)(0x42900040UL))) +#define bM4_MSTP_FCG0_AOS (*((volatile unsigned int*)(0x42900044UL))) +#define bM4_MSTP_FCG0_AES (*((volatile unsigned int*)(0x42900050UL))) +#define bM4_MSTP_FCG0_HASH (*((volatile unsigned int*)(0x42900054UL))) +#define bM4_MSTP_FCG0_TRNG (*((volatile unsigned int*)(0x42900058UL))) +#define bM4_MSTP_FCG0_CRC (*((volatile unsigned int*)(0x4290005CUL))) +#define bM4_MSTP_FCG0_DCU1 (*((volatile unsigned int*)(0x42900060UL))) +#define bM4_MSTP_FCG0_DCU2 (*((volatile unsigned int*)(0x42900064UL))) +#define bM4_MSTP_FCG0_DCU3 (*((volatile unsigned int*)(0x42900068UL))) +#define bM4_MSTP_FCG0_DCU4 (*((volatile unsigned int*)(0x4290006CUL))) +#define bM4_MSTP_FCG0_KEY (*((volatile unsigned int*)(0x4290007CUL))) +#define bM4_MSTP_FCG1_CAN (*((volatile unsigned int*)(0x42900080UL))) +#define bM4_MSTP_FCG1_QSPI (*((volatile unsigned int*)(0x4290008CUL))) +#define bM4_MSTP_FCG1_IIC1 (*((volatile unsigned int*)(0x42900090UL))) +#define bM4_MSTP_FCG1_IIC2 (*((volatile unsigned int*)(0x42900094UL))) +#define bM4_MSTP_FCG1_IIC3 (*((volatile unsigned int*)(0x42900098UL))) +#define bM4_MSTP_FCG1_USBFS (*((volatile unsigned int*)(0x429000A0UL))) +#define bM4_MSTP_FCG1_SDIOC1 (*((volatile unsigned int*)(0x429000A8UL))) +#define bM4_MSTP_FCG1_SDIOC2 (*((volatile unsigned int*)(0x429000ACUL))) +#define bM4_MSTP_FCG1_I2S1 (*((volatile unsigned int*)(0x429000B0UL))) +#define bM4_MSTP_FCG1_I2S2 (*((volatile unsigned int*)(0x429000B4UL))) +#define bM4_MSTP_FCG1_I2S3 (*((volatile unsigned int*)(0x429000B8UL))) +#define bM4_MSTP_FCG1_I2S4 (*((volatile unsigned int*)(0x429000BCUL))) +#define bM4_MSTP_FCG1_SPI1 (*((volatile unsigned int*)(0x429000C0UL))) +#define bM4_MSTP_FCG1_SPI2 (*((volatile unsigned int*)(0x429000C4UL))) +#define bM4_MSTP_FCG1_SPI3 (*((volatile unsigned int*)(0x429000C8UL))) +#define bM4_MSTP_FCG1_SPI4 (*((volatile unsigned int*)(0x429000CCUL))) +#define bM4_MSTP_FCG1_USART1 (*((volatile unsigned int*)(0x429000E0UL))) +#define bM4_MSTP_FCG1_USART2 (*((volatile unsigned int*)(0x429000E4UL))) +#define bM4_MSTP_FCG1_USART3 (*((volatile unsigned int*)(0x429000E8UL))) +#define bM4_MSTP_FCG1_USART4 (*((volatile unsigned int*)(0x429000ECUL))) +#define bM4_MSTP_FCG2_TIMER0_1 (*((volatile unsigned int*)(0x42900100UL))) +#define bM4_MSTP_FCG2_TIMER0_2 (*((volatile unsigned int*)(0x42900104UL))) +#define bM4_MSTP_FCG2_TIMERA_1 (*((volatile unsigned int*)(0x42900108UL))) +#define bM4_MSTP_FCG2_TIMERA_2 (*((volatile unsigned int*)(0x4290010CUL))) +#define bM4_MSTP_FCG2_TIMERA_3 (*((volatile unsigned int*)(0x42900110UL))) +#define bM4_MSTP_FCG2_TIMERA_4 (*((volatile unsigned int*)(0x42900114UL))) +#define bM4_MSTP_FCG2_TIMERA_5 (*((volatile unsigned int*)(0x42900118UL))) +#define bM4_MSTP_FCG2_TIMERA_6 (*((volatile unsigned int*)(0x4290011CUL))) +#define bM4_MSTP_FCG2_TIMER4_1 (*((volatile unsigned int*)(0x42900120UL))) +#define bM4_MSTP_FCG2_TIMER4_2 (*((volatile unsigned int*)(0x42900124UL))) +#define bM4_MSTP_FCG2_TIMER4_3 (*((volatile unsigned int*)(0x42900128UL))) +#define bM4_MSTP_FCG2_EMB (*((volatile unsigned int*)(0x4290013CUL))) +#define bM4_MSTP_FCG2_TIMER6_1 (*((volatile unsigned int*)(0x42900140UL))) +#define bM4_MSTP_FCG2_TIMER6_2 (*((volatile unsigned int*)(0x42900144UL))) +#define bM4_MSTP_FCG2_TIMER6_3 (*((volatile unsigned int*)(0x42900148UL))) +#define bM4_MSTP_FCG3_ADC1 (*((volatile unsigned int*)(0x42900180UL))) +#define bM4_MSTP_FCG3_ADC2 (*((volatile unsigned int*)(0x42900184UL))) +#define bM4_MSTP_FCG3_CMP (*((volatile unsigned int*)(0x429001A0UL))) +#define bM4_MSTP_FCG3_OTS (*((volatile unsigned int*)(0x429001B0UL))) +#define bM4_MSTP_FCG0PC_PRT0 (*((volatile unsigned int*)(0x42900200UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE0 (*((volatile unsigned int*)(0x42900240UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE1 (*((volatile unsigned int*)(0x42900244UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE2 (*((volatile unsigned int*)(0x42900248UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE3 (*((volatile unsigned int*)(0x4290024CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE4 (*((volatile unsigned int*)(0x42900250UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE5 (*((volatile unsigned int*)(0x42900254UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE6 (*((volatile unsigned int*)(0x42900258UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE7 (*((volatile unsigned int*)(0x4290025CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE8 (*((volatile unsigned int*)(0x42900260UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE9 (*((volatile unsigned int*)(0x42900264UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE10 (*((volatile unsigned int*)(0x42900268UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE11 (*((volatile unsigned int*)(0x4290026CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE12 (*((volatile unsigned int*)(0x42900270UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE13 (*((volatile unsigned int*)(0x42900274UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE14 (*((volatile unsigned int*)(0x42900278UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE15 (*((volatile unsigned int*)(0x4290027CUL))) +#define bM4_OTS_CTL_OTSST (*((volatile unsigned int*)(0x42948000UL))) +#define bM4_OTS_CTL_OTSCK (*((volatile unsigned int*)(0x42948004UL))) +#define bM4_OTS_CTL_OTSIE (*((volatile unsigned int*)(0x42948008UL))) +#define bM4_OTS_CTL_TSSTP (*((volatile unsigned int*)(0x4294800CUL))) +#define bM4_OTS_LPR_TSOFS0 (*((volatile unsigned int*)(0x42948100UL))) +#define bM4_OTS_LPR_TSOFS1 (*((volatile unsigned int*)(0x42948104UL))) +#define bM4_OTS_LPR_TSOFS2 (*((volatile unsigned int*)(0x42948108UL))) +#define bM4_OTS_LPR_TSOFS3 (*((volatile unsigned int*)(0x4294810CUL))) +#define bM4_OTS_LPR_TSOFS4 (*((volatile unsigned int*)(0x42948110UL))) +#define bM4_OTS_LPR_TSOFS5 (*((volatile unsigned int*)(0x42948114UL))) +#define bM4_OTS_LPR_TSOFS6 (*((volatile unsigned int*)(0x42948118UL))) +#define bM4_OTS_LPR_TSOFS7 (*((volatile unsigned int*)(0x4294811CUL))) +#define bM4_OTS_LPR_TSSLP0 (*((volatile unsigned int*)(0x42948120UL))) +#define bM4_OTS_LPR_TSSLP1 (*((volatile unsigned int*)(0x42948124UL))) +#define bM4_OTS_LPR_TSSLP2 (*((volatile unsigned int*)(0x42948128UL))) +#define bM4_OTS_LPR_TSSLP3 (*((volatile unsigned int*)(0x4294812CUL))) +#define bM4_OTS_LPR_TSSLP4 (*((volatile unsigned int*)(0x42948130UL))) +#define bM4_OTS_LPR_TSSLP5 (*((volatile unsigned int*)(0x42948134UL))) +#define bM4_OTS_LPR_TSSLP6 (*((volatile unsigned int*)(0x42948138UL))) +#define bM4_OTS_LPR_TSSLP7 (*((volatile unsigned int*)(0x4294813CUL))) +#define bM4_OTS_LPR_TSSLP8 (*((volatile unsigned int*)(0x42948140UL))) +#define bM4_OTS_LPR_TSSLP9 (*((volatile unsigned int*)(0x42948144UL))) +#define bM4_OTS_LPR_TSSLP10 (*((volatile unsigned int*)(0x42948148UL))) +#define bM4_OTS_LPR_TSSLP11 (*((volatile unsigned int*)(0x4294814CUL))) +#define bM4_OTS_LPR_TSSLP12 (*((volatile unsigned int*)(0x42948150UL))) +#define bM4_OTS_LPR_TSSLP13 (*((volatile unsigned int*)(0x42948154UL))) +#define bM4_OTS_LPR_TSSLP14 (*((volatile unsigned int*)(0x42948158UL))) +#define bM4_OTS_LPR_TSSLP15 (*((volatile unsigned int*)(0x4294815CUL))) +#define bM4_OTS_LPR_TSSLP16 (*((volatile unsigned int*)(0x42948160UL))) +#define bM4_OTS_LPR_TSSLP17 (*((volatile unsigned int*)(0x42948164UL))) +#define bM4_OTS_LPR_TSSLP18 (*((volatile unsigned int*)(0x42948168UL))) +#define bM4_OTS_LPR_TSSLP19 (*((volatile unsigned int*)(0x4294816CUL))) +#define bM4_OTS_LPR_TSSLP20 (*((volatile unsigned int*)(0x42948170UL))) +#define bM4_OTS_LPR_TSSLP21 (*((volatile unsigned int*)(0x42948174UL))) +#define bM4_OTS_LPR_TSSLP22 (*((volatile unsigned int*)(0x42948178UL))) +#define bM4_OTS_LPR_TSSLP23 (*((volatile unsigned int*)(0x4294817CUL))) +#define bM4_PERIC_USBFS_SYCTLREG_DFB (*((volatile unsigned int*)(0x42AA8000UL))) +#define bM4_PERIC_USBFS_SYCTLREG_SOFEN (*((volatile unsigned int*)(0x42AA8004UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC1 (*((volatile unsigned int*)(0x42AA8084UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC2 (*((volatile unsigned int*)(0x42AA808CUL))) +#define bM4_PORT_PIDRA_PIN00 (*((volatile unsigned int*)(0x42A70000UL))) +#define bM4_PORT_PIDRA_PIN01 (*((volatile unsigned int*)(0x42A70004UL))) +#define bM4_PORT_PIDRA_PIN02 (*((volatile unsigned int*)(0x42A70008UL))) +#define bM4_PORT_PIDRA_PIN03 (*((volatile unsigned int*)(0x42A7000CUL))) +#define bM4_PORT_PIDRA_PIN04 (*((volatile unsigned int*)(0x42A70010UL))) +#define bM4_PORT_PIDRA_PIN05 (*((volatile unsigned int*)(0x42A70014UL))) +#define bM4_PORT_PIDRA_PIN06 (*((volatile unsigned int*)(0x42A70018UL))) +#define bM4_PORT_PIDRA_PIN07 (*((volatile unsigned int*)(0x42A7001CUL))) +#define bM4_PORT_PIDRA_PIN08 (*((volatile unsigned int*)(0x42A70020UL))) +#define bM4_PORT_PIDRA_PIN09 (*((volatile unsigned int*)(0x42A70024UL))) +#define bM4_PORT_PIDRA_PIN10 (*((volatile unsigned int*)(0x42A70028UL))) +#define bM4_PORT_PIDRA_PIN11 (*((volatile unsigned int*)(0x42A7002CUL))) +#define bM4_PORT_PIDRA_PIN12 (*((volatile unsigned int*)(0x42A70030UL))) +#define bM4_PORT_PIDRA_PIN13 (*((volatile unsigned int*)(0x42A70034UL))) +#define bM4_PORT_PIDRA_PIN14 (*((volatile unsigned int*)(0x42A70038UL))) +#define bM4_PORT_PIDRA_PIN15 (*((volatile unsigned int*)(0x42A7003CUL))) +#define bM4_PORT_PODRA_POUT00 (*((volatile unsigned int*)(0x42A70080UL))) +#define bM4_PORT_PODRA_POUT01 (*((volatile unsigned int*)(0x42A70084UL))) +#define bM4_PORT_PODRA_POUT02 (*((volatile unsigned int*)(0x42A70088UL))) +#define bM4_PORT_PODRA_POUT03 (*((volatile unsigned int*)(0x42A7008CUL))) +#define bM4_PORT_PODRA_POUT04 (*((volatile unsigned int*)(0x42A70090UL))) +#define bM4_PORT_PODRA_POUT05 (*((volatile unsigned int*)(0x42A70094UL))) +#define bM4_PORT_PODRA_POUT06 (*((volatile unsigned int*)(0x42A70098UL))) +#define bM4_PORT_PODRA_POUT07 (*((volatile unsigned int*)(0x42A7009CUL))) +#define bM4_PORT_PODRA_POUT08 (*((volatile unsigned int*)(0x42A700A0UL))) +#define bM4_PORT_PODRA_POUT09 (*((volatile unsigned int*)(0x42A700A4UL))) +#define bM4_PORT_PODRA_POUT10 (*((volatile unsigned int*)(0x42A700A8UL))) +#define bM4_PORT_PODRA_POUT11 (*((volatile unsigned int*)(0x42A700ACUL))) +#define bM4_PORT_PODRA_POUT12 (*((volatile unsigned int*)(0x42A700B0UL))) +#define bM4_PORT_PODRA_POUT13 (*((volatile unsigned int*)(0x42A700B4UL))) +#define bM4_PORT_PODRA_POUT14 (*((volatile unsigned int*)(0x42A700B8UL))) +#define bM4_PORT_PODRA_POUT15 (*((volatile unsigned int*)(0x42A700BCUL))) +#define bM4_PORT_POERA_POUTE00 (*((volatile unsigned int*)(0x42A700C0UL))) +#define bM4_PORT_POERA_POUTE01 (*((volatile unsigned int*)(0x42A700C4UL))) +#define bM4_PORT_POERA_POUTE02 (*((volatile unsigned int*)(0x42A700C8UL))) +#define bM4_PORT_POERA_POUTE03 (*((volatile unsigned int*)(0x42A700CCUL))) +#define bM4_PORT_POERA_POUTE04 (*((volatile unsigned int*)(0x42A700D0UL))) +#define bM4_PORT_POERA_POUTE05 (*((volatile unsigned int*)(0x42A700D4UL))) +#define bM4_PORT_POERA_POUTE06 (*((volatile unsigned int*)(0x42A700D8UL))) +#define bM4_PORT_POERA_POUTE07 (*((volatile unsigned int*)(0x42A700DCUL))) +#define bM4_PORT_POERA_POUTE08 (*((volatile unsigned int*)(0x42A700E0UL))) +#define bM4_PORT_POERA_POUTE09 (*((volatile unsigned int*)(0x42A700E4UL))) +#define bM4_PORT_POERA_POUTE10 (*((volatile unsigned int*)(0x42A700E8UL))) +#define bM4_PORT_POERA_POUTE11 (*((volatile unsigned int*)(0x42A700ECUL))) +#define bM4_PORT_POERA_POUTE12 (*((volatile unsigned int*)(0x42A700F0UL))) +#define bM4_PORT_POERA_POUTE13 (*((volatile unsigned int*)(0x42A700F4UL))) +#define bM4_PORT_POERA_POUTE14 (*((volatile unsigned int*)(0x42A700F8UL))) +#define bM4_PORT_POERA_POUTE15 (*((volatile unsigned int*)(0x42A700FCUL))) +#define bM4_PORT_POSRA_POS00 (*((volatile unsigned int*)(0x42A70100UL))) +#define bM4_PORT_POSRA_POS01 (*((volatile unsigned int*)(0x42A70104UL))) +#define bM4_PORT_POSRA_POS02 (*((volatile unsigned int*)(0x42A70108UL))) +#define bM4_PORT_POSRA_POS03 (*((volatile unsigned int*)(0x42A7010CUL))) +#define bM4_PORT_POSRA_POS04 (*((volatile unsigned int*)(0x42A70110UL))) +#define bM4_PORT_POSRA_POS05 (*((volatile unsigned int*)(0x42A70114UL))) +#define bM4_PORT_POSRA_POS06 (*((volatile unsigned int*)(0x42A70118UL))) +#define bM4_PORT_POSRA_POS07 (*((volatile unsigned int*)(0x42A7011CUL))) +#define bM4_PORT_POSRA_POS08 (*((volatile unsigned int*)(0x42A70120UL))) +#define bM4_PORT_POSRA_POS09 (*((volatile unsigned int*)(0x42A70124UL))) +#define bM4_PORT_POSRA_POS10 (*((volatile unsigned int*)(0x42A70128UL))) +#define bM4_PORT_POSRA_POS11 (*((volatile unsigned int*)(0x42A7012CUL))) +#define bM4_PORT_POSRA_POS12 (*((volatile unsigned int*)(0x42A70130UL))) +#define bM4_PORT_POSRA_POS13 (*((volatile unsigned int*)(0x42A70134UL))) +#define bM4_PORT_POSRA_POS14 (*((volatile unsigned int*)(0x42A70138UL))) +#define bM4_PORT_POSRA_POS15 (*((volatile unsigned int*)(0x42A7013CUL))) +#define bM4_PORT_PORRA_POR00 (*((volatile unsigned int*)(0x42A70140UL))) +#define bM4_PORT_PORRA_POR01 (*((volatile unsigned int*)(0x42A70144UL))) +#define bM4_PORT_PORRA_POR02 (*((volatile unsigned int*)(0x42A70148UL))) +#define bM4_PORT_PORRA_POR03 (*((volatile unsigned int*)(0x42A7014CUL))) +#define bM4_PORT_PORRA_POR04 (*((volatile unsigned int*)(0x42A70150UL))) +#define bM4_PORT_PORRA_POR05 (*((volatile unsigned int*)(0x42A70154UL))) +#define bM4_PORT_PORRA_POR06 (*((volatile unsigned int*)(0x42A70158UL))) +#define bM4_PORT_PORRA_POR07 (*((volatile unsigned int*)(0x42A7015CUL))) +#define bM4_PORT_PORRA_POR08 (*((volatile unsigned int*)(0x42A70160UL))) +#define bM4_PORT_PORRA_POR09 (*((volatile unsigned int*)(0x42A70164UL))) +#define bM4_PORT_PORRA_POR10 (*((volatile unsigned int*)(0x42A70168UL))) +#define bM4_PORT_PORRA_POR11 (*((volatile unsigned int*)(0x42A7016CUL))) +#define bM4_PORT_PORRA_POR12 (*((volatile unsigned int*)(0x42A70170UL))) +#define bM4_PORT_PORRA_POR13 (*((volatile unsigned int*)(0x42A70174UL))) +#define bM4_PORT_PORRA_POR14 (*((volatile unsigned int*)(0x42A70178UL))) +#define bM4_PORT_PORRA_POR15 (*((volatile unsigned int*)(0x42A7017CUL))) +#define bM4_PORT_POTRA_POT00 (*((volatile unsigned int*)(0x42A70180UL))) +#define bM4_PORT_POTRA_POT01 (*((volatile unsigned int*)(0x42A70184UL))) +#define bM4_PORT_POTRA_POT02 (*((volatile unsigned int*)(0x42A70188UL))) +#define bM4_PORT_POTRA_POT03 (*((volatile unsigned int*)(0x42A7018CUL))) +#define bM4_PORT_POTRA_POT04 (*((volatile unsigned int*)(0x42A70190UL))) +#define bM4_PORT_POTRA_POT05 (*((volatile unsigned int*)(0x42A70194UL))) +#define bM4_PORT_POTRA_POT06 (*((volatile unsigned int*)(0x42A70198UL))) +#define bM4_PORT_POTRA_POT07 (*((volatile unsigned int*)(0x42A7019CUL))) +#define bM4_PORT_POTRA_POT08 (*((volatile unsigned int*)(0x42A701A0UL))) +#define bM4_PORT_POTRA_POT09 (*((volatile unsigned int*)(0x42A701A4UL))) +#define bM4_PORT_POTRA_POT10 (*((volatile unsigned int*)(0x42A701A8UL))) +#define bM4_PORT_POTRA_POT11 (*((volatile unsigned int*)(0x42A701ACUL))) +#define bM4_PORT_POTRA_POT12 (*((volatile unsigned int*)(0x42A701B0UL))) +#define bM4_PORT_POTRA_POT13 (*((volatile unsigned int*)(0x42A701B4UL))) +#define bM4_PORT_POTRA_POT14 (*((volatile unsigned int*)(0x42A701B8UL))) +#define bM4_PORT_POTRA_POT15 (*((volatile unsigned int*)(0x42A701BCUL))) +#define bM4_PORT_PIDRB_PIN00 (*((volatile unsigned int*)(0x42A70200UL))) +#define bM4_PORT_PIDRB_PIN01 (*((volatile unsigned int*)(0x42A70204UL))) +#define bM4_PORT_PIDRB_PIN02 (*((volatile unsigned int*)(0x42A70208UL))) +#define bM4_PORT_PIDRB_PIN03 (*((volatile unsigned int*)(0x42A7020CUL))) +#define bM4_PORT_PIDRB_PIN04 (*((volatile unsigned int*)(0x42A70210UL))) +#define bM4_PORT_PIDRB_PIN05 (*((volatile unsigned int*)(0x42A70214UL))) +#define bM4_PORT_PIDRB_PIN06 (*((volatile unsigned int*)(0x42A70218UL))) +#define bM4_PORT_PIDRB_PIN07 (*((volatile unsigned int*)(0x42A7021CUL))) +#define bM4_PORT_PIDRB_PIN08 (*((volatile unsigned int*)(0x42A70220UL))) +#define bM4_PORT_PIDRB_PIN09 (*((volatile unsigned int*)(0x42A70224UL))) +#define bM4_PORT_PIDRB_PIN10 (*((volatile unsigned int*)(0x42A70228UL))) +#define bM4_PORT_PIDRB_PIN11 (*((volatile unsigned int*)(0x42A7022CUL))) +#define bM4_PORT_PIDRB_PIN12 (*((volatile unsigned int*)(0x42A70230UL))) +#define bM4_PORT_PIDRB_PIN13 (*((volatile unsigned int*)(0x42A70234UL))) +#define bM4_PORT_PIDRB_PIN14 (*((volatile unsigned int*)(0x42A70238UL))) +#define bM4_PORT_PIDRB_PIN15 (*((volatile unsigned int*)(0x42A7023CUL))) +#define bM4_PORT_PODRB_POUT00 (*((volatile unsigned int*)(0x42A70280UL))) +#define bM4_PORT_PODRB_POUT01 (*((volatile unsigned int*)(0x42A70284UL))) +#define bM4_PORT_PODRB_POUT02 (*((volatile unsigned int*)(0x42A70288UL))) +#define bM4_PORT_PODRB_POUT03 (*((volatile unsigned int*)(0x42A7028CUL))) +#define bM4_PORT_PODRB_POUT04 (*((volatile unsigned int*)(0x42A70290UL))) +#define bM4_PORT_PODRB_POUT05 (*((volatile unsigned int*)(0x42A70294UL))) +#define bM4_PORT_PODRB_POUT06 (*((volatile unsigned int*)(0x42A70298UL))) +#define bM4_PORT_PODRB_POUT07 (*((volatile unsigned int*)(0x42A7029CUL))) +#define bM4_PORT_PODRB_POUT08 (*((volatile unsigned int*)(0x42A702A0UL))) +#define bM4_PORT_PODRB_POUT09 (*((volatile unsigned int*)(0x42A702A4UL))) +#define bM4_PORT_PODRB_POUT10 (*((volatile unsigned int*)(0x42A702A8UL))) +#define bM4_PORT_PODRB_POUT11 (*((volatile unsigned int*)(0x42A702ACUL))) +#define bM4_PORT_PODRB_POUT12 (*((volatile unsigned int*)(0x42A702B0UL))) +#define bM4_PORT_PODRB_POUT13 (*((volatile unsigned int*)(0x42A702B4UL))) +#define bM4_PORT_PODRB_POUT14 (*((volatile unsigned int*)(0x42A702B8UL))) +#define bM4_PORT_PODRB_POUT15 (*((volatile unsigned int*)(0x42A702BCUL))) +#define bM4_PORT_POERB_POUTE00 (*((volatile unsigned int*)(0x42A702C0UL))) +#define bM4_PORT_POERB_POUTE01 (*((volatile unsigned int*)(0x42A702C4UL))) +#define bM4_PORT_POERB_POUTE02 (*((volatile unsigned int*)(0x42A702C8UL))) +#define bM4_PORT_POERB_POUTE03 (*((volatile unsigned int*)(0x42A702CCUL))) +#define bM4_PORT_POERB_POUTE04 (*((volatile unsigned int*)(0x42A702D0UL))) +#define bM4_PORT_POERB_POUTE05 (*((volatile unsigned int*)(0x42A702D4UL))) +#define bM4_PORT_POERB_POUTE06 (*((volatile unsigned int*)(0x42A702D8UL))) +#define bM4_PORT_POERB_POUTE07 (*((volatile unsigned int*)(0x42A702DCUL))) +#define bM4_PORT_POERB_POUTE08 (*((volatile unsigned int*)(0x42A702E0UL))) +#define bM4_PORT_POERB_POUTE09 (*((volatile unsigned int*)(0x42A702E4UL))) +#define bM4_PORT_POERB_POUTE10 (*((volatile unsigned int*)(0x42A702E8UL))) +#define bM4_PORT_POERB_POUTE11 (*((volatile unsigned int*)(0x42A702ECUL))) +#define bM4_PORT_POERB_POUTE12 (*((volatile unsigned int*)(0x42A702F0UL))) +#define bM4_PORT_POERB_POUTE13 (*((volatile unsigned int*)(0x42A702F4UL))) +#define bM4_PORT_POERB_POUTE14 (*((volatile unsigned int*)(0x42A702F8UL))) +#define bM4_PORT_POERB_POUTE15 (*((volatile unsigned int*)(0x42A702FCUL))) +#define bM4_PORT_POSRB_POS00 (*((volatile unsigned int*)(0x42A70300UL))) +#define bM4_PORT_POSRB_POS01 (*((volatile unsigned int*)(0x42A70304UL))) +#define bM4_PORT_POSRB_POS02 (*((volatile unsigned int*)(0x42A70308UL))) +#define bM4_PORT_POSRB_POS03 (*((volatile unsigned int*)(0x42A7030CUL))) +#define bM4_PORT_POSRB_POS04 (*((volatile unsigned int*)(0x42A70310UL))) +#define bM4_PORT_POSRB_POS05 (*((volatile unsigned int*)(0x42A70314UL))) +#define bM4_PORT_POSRB_POS06 (*((volatile unsigned int*)(0x42A70318UL))) +#define bM4_PORT_POSRB_POS07 (*((volatile unsigned int*)(0x42A7031CUL))) +#define bM4_PORT_POSRB_POS08 (*((volatile unsigned int*)(0x42A70320UL))) +#define bM4_PORT_POSRB_POS09 (*((volatile unsigned int*)(0x42A70324UL))) +#define bM4_PORT_POSRB_POS10 (*((volatile unsigned int*)(0x42A70328UL))) +#define bM4_PORT_POSRB_POS11 (*((volatile unsigned int*)(0x42A7032CUL))) +#define bM4_PORT_POSRB_POS12 (*((volatile unsigned int*)(0x42A70330UL))) +#define bM4_PORT_POSRB_POS13 (*((volatile unsigned int*)(0x42A70334UL))) +#define bM4_PORT_POSRB_POS14 (*((volatile unsigned int*)(0x42A70338UL))) +#define bM4_PORT_POSRB_POS15 (*((volatile unsigned int*)(0x42A7033CUL))) +#define bM4_PORT_PORRB_POR00 (*((volatile unsigned int*)(0x42A70340UL))) +#define bM4_PORT_PORRB_POR01 (*((volatile unsigned int*)(0x42A70344UL))) +#define bM4_PORT_PORRB_POR02 (*((volatile unsigned int*)(0x42A70348UL))) +#define bM4_PORT_PORRB_POR03 (*((volatile unsigned int*)(0x42A7034CUL))) +#define bM4_PORT_PORRB_POR04 (*((volatile unsigned int*)(0x42A70350UL))) +#define bM4_PORT_PORRB_POR05 (*((volatile unsigned int*)(0x42A70354UL))) +#define bM4_PORT_PORRB_POR06 (*((volatile unsigned int*)(0x42A70358UL))) +#define bM4_PORT_PORRB_POR07 (*((volatile unsigned int*)(0x42A7035CUL))) +#define bM4_PORT_PORRB_POR08 (*((volatile unsigned int*)(0x42A70360UL))) +#define bM4_PORT_PORRB_POR09 (*((volatile unsigned int*)(0x42A70364UL))) +#define bM4_PORT_PORRB_POR10 (*((volatile unsigned int*)(0x42A70368UL))) +#define bM4_PORT_PORRB_POR11 (*((volatile unsigned int*)(0x42A7036CUL))) +#define bM4_PORT_PORRB_POR12 (*((volatile unsigned int*)(0x42A70370UL))) +#define bM4_PORT_PORRB_POR13 (*((volatile unsigned int*)(0x42A70374UL))) +#define bM4_PORT_PORRB_POR14 (*((volatile unsigned int*)(0x42A70378UL))) +#define bM4_PORT_PORRB_POR15 (*((volatile unsigned int*)(0x42A7037CUL))) +#define bM4_PORT_POTRB_POT00 (*((volatile unsigned int*)(0x42A70380UL))) +#define bM4_PORT_POTRB_POT01 (*((volatile unsigned int*)(0x42A70384UL))) +#define bM4_PORT_POTRB_POT02 (*((volatile unsigned int*)(0x42A70388UL))) +#define bM4_PORT_POTRB_POT03 (*((volatile unsigned int*)(0x42A7038CUL))) +#define bM4_PORT_POTRB_POT04 (*((volatile unsigned int*)(0x42A70390UL))) +#define bM4_PORT_POTRB_POT05 (*((volatile unsigned int*)(0x42A70394UL))) +#define bM4_PORT_POTRB_POT06 (*((volatile unsigned int*)(0x42A70398UL))) +#define bM4_PORT_POTRB_POT07 (*((volatile unsigned int*)(0x42A7039CUL))) +#define bM4_PORT_POTRB_POT08 (*((volatile unsigned int*)(0x42A703A0UL))) +#define bM4_PORT_POTRB_POT09 (*((volatile unsigned int*)(0x42A703A4UL))) +#define bM4_PORT_POTRB_POT10 (*((volatile unsigned int*)(0x42A703A8UL))) +#define bM4_PORT_POTRB_POT11 (*((volatile unsigned int*)(0x42A703ACUL))) +#define bM4_PORT_POTRB_POT12 (*((volatile unsigned int*)(0x42A703B0UL))) +#define bM4_PORT_POTRB_POT13 (*((volatile unsigned int*)(0x42A703B4UL))) +#define bM4_PORT_POTRB_POT14 (*((volatile unsigned int*)(0x42A703B8UL))) +#define bM4_PORT_POTRB_POT15 (*((volatile unsigned int*)(0x42A703BCUL))) +#define bM4_PORT_PIDRC_PIN00 (*((volatile unsigned int*)(0x42A70400UL))) +#define bM4_PORT_PIDRC_PIN01 (*((volatile unsigned int*)(0x42A70404UL))) +#define bM4_PORT_PIDRC_PIN02 (*((volatile unsigned int*)(0x42A70408UL))) +#define bM4_PORT_PIDRC_PIN03 (*((volatile unsigned int*)(0x42A7040CUL))) +#define bM4_PORT_PIDRC_PIN04 (*((volatile unsigned int*)(0x42A70410UL))) +#define bM4_PORT_PIDRC_PIN05 (*((volatile unsigned int*)(0x42A70414UL))) +#define bM4_PORT_PIDRC_PIN06 (*((volatile unsigned int*)(0x42A70418UL))) +#define bM4_PORT_PIDRC_PIN07 (*((volatile unsigned int*)(0x42A7041CUL))) +#define bM4_PORT_PIDRC_PIN08 (*((volatile unsigned int*)(0x42A70420UL))) +#define bM4_PORT_PIDRC_PIN09 (*((volatile unsigned int*)(0x42A70424UL))) +#define bM4_PORT_PIDRC_PIN10 (*((volatile unsigned int*)(0x42A70428UL))) +#define bM4_PORT_PIDRC_PIN11 (*((volatile unsigned int*)(0x42A7042CUL))) +#define bM4_PORT_PIDRC_PIN12 (*((volatile unsigned int*)(0x42A70430UL))) +#define bM4_PORT_PIDRC_PIN13 (*((volatile unsigned int*)(0x42A70434UL))) +#define bM4_PORT_PIDRC_PIN14 (*((volatile unsigned int*)(0x42A70438UL))) +#define bM4_PORT_PIDRC_PIN15 (*((volatile unsigned int*)(0x42A7043CUL))) +#define bM4_PORT_PODRC_POUT00 (*((volatile unsigned int*)(0x42A70480UL))) +#define bM4_PORT_PODRC_POUT01 (*((volatile unsigned int*)(0x42A70484UL))) +#define bM4_PORT_PODRC_POUT02 (*((volatile unsigned int*)(0x42A70488UL))) +#define bM4_PORT_PODRC_POUT03 (*((volatile unsigned int*)(0x42A7048CUL))) +#define bM4_PORT_PODRC_POUT04 (*((volatile unsigned int*)(0x42A70490UL))) +#define bM4_PORT_PODRC_POUT05 (*((volatile unsigned int*)(0x42A70494UL))) +#define bM4_PORT_PODRC_POUT06 (*((volatile unsigned int*)(0x42A70498UL))) +#define bM4_PORT_PODRC_POUT07 (*((volatile unsigned int*)(0x42A7049CUL))) +#define bM4_PORT_PODRC_POUT08 (*((volatile unsigned int*)(0x42A704A0UL))) +#define bM4_PORT_PODRC_POUT09 (*((volatile unsigned int*)(0x42A704A4UL))) +#define bM4_PORT_PODRC_POUT10 (*((volatile unsigned int*)(0x42A704A8UL))) +#define bM4_PORT_PODRC_POUT11 (*((volatile unsigned int*)(0x42A704ACUL))) +#define bM4_PORT_PODRC_POUT12 (*((volatile unsigned int*)(0x42A704B0UL))) +#define bM4_PORT_PODRC_POUT13 (*((volatile unsigned int*)(0x42A704B4UL))) +#define bM4_PORT_PODRC_POUT14 (*((volatile unsigned int*)(0x42A704B8UL))) +#define bM4_PORT_PODRC_POUT15 (*((volatile unsigned int*)(0x42A704BCUL))) +#define bM4_PORT_POERC_POUTE00 (*((volatile unsigned int*)(0x42A704C0UL))) +#define bM4_PORT_POERC_POUTE01 (*((volatile unsigned int*)(0x42A704C4UL))) +#define bM4_PORT_POERC_POUTE02 (*((volatile unsigned int*)(0x42A704C8UL))) +#define bM4_PORT_POERC_POUTE03 (*((volatile unsigned int*)(0x42A704CCUL))) +#define bM4_PORT_POERC_POUTE04 (*((volatile unsigned int*)(0x42A704D0UL))) +#define bM4_PORT_POERC_POUTE05 (*((volatile unsigned int*)(0x42A704D4UL))) +#define bM4_PORT_POERC_POUTE06 (*((volatile unsigned int*)(0x42A704D8UL))) +#define bM4_PORT_POERC_POUTE07 (*((volatile unsigned int*)(0x42A704DCUL))) +#define bM4_PORT_POERC_POUTE08 (*((volatile unsigned int*)(0x42A704E0UL))) +#define bM4_PORT_POERC_POUTE09 (*((volatile unsigned int*)(0x42A704E4UL))) +#define bM4_PORT_POERC_POUTE10 (*((volatile unsigned int*)(0x42A704E8UL))) +#define bM4_PORT_POERC_POUTE11 (*((volatile unsigned int*)(0x42A704ECUL))) +#define bM4_PORT_POERC_POUTE12 (*((volatile unsigned int*)(0x42A704F0UL))) +#define bM4_PORT_POERC_POUTE13 (*((volatile unsigned int*)(0x42A704F4UL))) +#define bM4_PORT_POERC_POUTE14 (*((volatile unsigned int*)(0x42A704F8UL))) +#define bM4_PORT_POERC_POUTE15 (*((volatile unsigned int*)(0x42A704FCUL))) +#define bM4_PORT_POSRC_POS00 (*((volatile unsigned int*)(0x42A70500UL))) +#define bM4_PORT_POSRC_POS01 (*((volatile unsigned int*)(0x42A70504UL))) +#define bM4_PORT_POSRC_POS02 (*((volatile unsigned int*)(0x42A70508UL))) +#define bM4_PORT_POSRC_POS03 (*((volatile unsigned int*)(0x42A7050CUL))) +#define bM4_PORT_POSRC_POS04 (*((volatile unsigned int*)(0x42A70510UL))) +#define bM4_PORT_POSRC_POS05 (*((volatile unsigned int*)(0x42A70514UL))) +#define bM4_PORT_POSRC_POS06 (*((volatile unsigned int*)(0x42A70518UL))) +#define bM4_PORT_POSRC_POS07 (*((volatile unsigned int*)(0x42A7051CUL))) +#define bM4_PORT_POSRC_POS08 (*((volatile unsigned int*)(0x42A70520UL))) +#define bM4_PORT_POSRC_POS09 (*((volatile unsigned int*)(0x42A70524UL))) +#define bM4_PORT_POSRC_POS10 (*((volatile unsigned int*)(0x42A70528UL))) +#define bM4_PORT_POSRC_POS11 (*((volatile unsigned int*)(0x42A7052CUL))) +#define bM4_PORT_POSRC_POS12 (*((volatile unsigned int*)(0x42A70530UL))) +#define bM4_PORT_POSRC_POS13 (*((volatile unsigned int*)(0x42A70534UL))) +#define bM4_PORT_POSRC_POS14 (*((volatile unsigned int*)(0x42A70538UL))) +#define bM4_PORT_POSRC_POS15 (*((volatile unsigned int*)(0x42A7053CUL))) +#define bM4_PORT_PORRC_POR00 (*((volatile unsigned int*)(0x42A70540UL))) +#define bM4_PORT_PORRC_POR01 (*((volatile unsigned int*)(0x42A70544UL))) +#define bM4_PORT_PORRC_POR02 (*((volatile unsigned int*)(0x42A70548UL))) +#define bM4_PORT_PORRC_POR03 (*((volatile unsigned int*)(0x42A7054CUL))) +#define bM4_PORT_PORRC_POR04 (*((volatile unsigned int*)(0x42A70550UL))) +#define bM4_PORT_PORRC_POR05 (*((volatile unsigned int*)(0x42A70554UL))) +#define bM4_PORT_PORRC_POR06 (*((volatile unsigned int*)(0x42A70558UL))) +#define bM4_PORT_PORRC_POR07 (*((volatile unsigned int*)(0x42A7055CUL))) +#define bM4_PORT_PORRC_POR08 (*((volatile unsigned int*)(0x42A70560UL))) +#define bM4_PORT_PORRC_POR09 (*((volatile unsigned int*)(0x42A70564UL))) +#define bM4_PORT_PORRC_POR10 (*((volatile unsigned int*)(0x42A70568UL))) +#define bM4_PORT_PORRC_POR11 (*((volatile unsigned int*)(0x42A7056CUL))) +#define bM4_PORT_PORRC_POR12 (*((volatile unsigned int*)(0x42A70570UL))) +#define bM4_PORT_PORRC_POR13 (*((volatile unsigned int*)(0x42A70574UL))) +#define bM4_PORT_PORRC_POR14 (*((volatile unsigned int*)(0x42A70578UL))) +#define bM4_PORT_PORRC_POR15 (*((volatile unsigned int*)(0x42A7057CUL))) +#define bM4_PORT_POTRC_POT00 (*((volatile unsigned int*)(0x42A70580UL))) +#define bM4_PORT_POTRC_POT01 (*((volatile unsigned int*)(0x42A70584UL))) +#define bM4_PORT_POTRC_POT02 (*((volatile unsigned int*)(0x42A70588UL))) +#define bM4_PORT_POTRC_POT03 (*((volatile unsigned int*)(0x42A7058CUL))) +#define bM4_PORT_POTRC_POT04 (*((volatile unsigned int*)(0x42A70590UL))) +#define bM4_PORT_POTRC_POT05 (*((volatile unsigned int*)(0x42A70594UL))) +#define bM4_PORT_POTRC_POT06 (*((volatile unsigned int*)(0x42A70598UL))) +#define bM4_PORT_POTRC_POT07 (*((volatile unsigned int*)(0x42A7059CUL))) +#define bM4_PORT_POTRC_POT08 (*((volatile unsigned int*)(0x42A705A0UL))) +#define bM4_PORT_POTRC_POT09 (*((volatile unsigned int*)(0x42A705A4UL))) +#define bM4_PORT_POTRC_POT10 (*((volatile unsigned int*)(0x42A705A8UL))) +#define bM4_PORT_POTRC_POT11 (*((volatile unsigned int*)(0x42A705ACUL))) +#define bM4_PORT_POTRC_POT12 (*((volatile unsigned int*)(0x42A705B0UL))) +#define bM4_PORT_POTRC_POT13 (*((volatile unsigned int*)(0x42A705B4UL))) +#define bM4_PORT_POTRC_POT14 (*((volatile unsigned int*)(0x42A705B8UL))) +#define bM4_PORT_POTRC_POT15 (*((volatile unsigned int*)(0x42A705BCUL))) +#define bM4_PORT_PIDRD_PIN00 (*((volatile unsigned int*)(0x42A70600UL))) +#define bM4_PORT_PIDRD_PIN01 (*((volatile unsigned int*)(0x42A70604UL))) +#define bM4_PORT_PIDRD_PIN02 (*((volatile unsigned int*)(0x42A70608UL))) +#define bM4_PORT_PIDRD_PIN03 (*((volatile unsigned int*)(0x42A7060CUL))) +#define bM4_PORT_PIDRD_PIN04 (*((volatile unsigned int*)(0x42A70610UL))) +#define bM4_PORT_PIDRD_PIN05 (*((volatile unsigned int*)(0x42A70614UL))) +#define bM4_PORT_PIDRD_PIN06 (*((volatile unsigned int*)(0x42A70618UL))) +#define bM4_PORT_PIDRD_PIN07 (*((volatile unsigned int*)(0x42A7061CUL))) +#define bM4_PORT_PIDRD_PIN08 (*((volatile unsigned int*)(0x42A70620UL))) +#define bM4_PORT_PIDRD_PIN09 (*((volatile unsigned int*)(0x42A70624UL))) +#define bM4_PORT_PIDRD_PIN10 (*((volatile unsigned int*)(0x42A70628UL))) +#define bM4_PORT_PIDRD_PIN11 (*((volatile unsigned int*)(0x42A7062CUL))) +#define bM4_PORT_PIDRD_PIN12 (*((volatile unsigned int*)(0x42A70630UL))) +#define bM4_PORT_PIDRD_PIN13 (*((volatile unsigned int*)(0x42A70634UL))) +#define bM4_PORT_PIDRD_PIN14 (*((volatile unsigned int*)(0x42A70638UL))) +#define bM4_PORT_PIDRD_PIN15 (*((volatile unsigned int*)(0x42A7063CUL))) +#define bM4_PORT_PODRD_POUT00 (*((volatile unsigned int*)(0x42A70680UL))) +#define bM4_PORT_PODRD_POUT01 (*((volatile unsigned int*)(0x42A70684UL))) +#define bM4_PORT_PODRD_POUT02 (*((volatile unsigned int*)(0x42A70688UL))) +#define bM4_PORT_PODRD_POUT03 (*((volatile unsigned int*)(0x42A7068CUL))) +#define bM4_PORT_PODRD_POUT04 (*((volatile unsigned int*)(0x42A70690UL))) +#define bM4_PORT_PODRD_POUT05 (*((volatile unsigned int*)(0x42A70694UL))) +#define bM4_PORT_PODRD_POUT06 (*((volatile unsigned int*)(0x42A70698UL))) +#define bM4_PORT_PODRD_POUT07 (*((volatile unsigned int*)(0x42A7069CUL))) +#define bM4_PORT_PODRD_POUT08 (*((volatile unsigned int*)(0x42A706A0UL))) +#define bM4_PORT_PODRD_POUT09 (*((volatile unsigned int*)(0x42A706A4UL))) +#define bM4_PORT_PODRD_POUT10 (*((volatile unsigned int*)(0x42A706A8UL))) +#define bM4_PORT_PODRD_POUT11 (*((volatile unsigned int*)(0x42A706ACUL))) +#define bM4_PORT_PODRD_POUT12 (*((volatile unsigned int*)(0x42A706B0UL))) +#define bM4_PORT_PODRD_POUT13 (*((volatile unsigned int*)(0x42A706B4UL))) +#define bM4_PORT_PODRD_POUT14 (*((volatile unsigned int*)(0x42A706B8UL))) +#define bM4_PORT_PODRD_POUT15 (*((volatile unsigned int*)(0x42A706BCUL))) +#define bM4_PORT_POERD_POUTE00 (*((volatile unsigned int*)(0x42A706C0UL))) +#define bM4_PORT_POERD_POUTE01 (*((volatile unsigned int*)(0x42A706C4UL))) +#define bM4_PORT_POERD_POUTE02 (*((volatile unsigned int*)(0x42A706C8UL))) +#define bM4_PORT_POERD_POUTE03 (*((volatile unsigned int*)(0x42A706CCUL))) +#define bM4_PORT_POERD_POUTE04 (*((volatile unsigned int*)(0x42A706D0UL))) +#define bM4_PORT_POERD_POUTE05 (*((volatile unsigned int*)(0x42A706D4UL))) +#define bM4_PORT_POERD_POUTE06 (*((volatile unsigned int*)(0x42A706D8UL))) +#define bM4_PORT_POERD_POUTE07 (*((volatile unsigned int*)(0x42A706DCUL))) +#define bM4_PORT_POERD_POUTE08 (*((volatile unsigned int*)(0x42A706E0UL))) +#define bM4_PORT_POERD_POUTE09 (*((volatile unsigned int*)(0x42A706E4UL))) +#define bM4_PORT_POERD_POUTE10 (*((volatile unsigned int*)(0x42A706E8UL))) +#define bM4_PORT_POERD_POUTE11 (*((volatile unsigned int*)(0x42A706ECUL))) +#define bM4_PORT_POERD_POUTE12 (*((volatile unsigned int*)(0x42A706F0UL))) +#define bM4_PORT_POERD_POUTE13 (*((volatile unsigned int*)(0x42A706F4UL))) +#define bM4_PORT_POERD_POUTE14 (*((volatile unsigned int*)(0x42A706F8UL))) +#define bM4_PORT_POERD_POUTE15 (*((volatile unsigned int*)(0x42A706FCUL))) +#define bM4_PORT_POSRD_POS00 (*((volatile unsigned int*)(0x42A70700UL))) +#define bM4_PORT_POSRD_POS01 (*((volatile unsigned int*)(0x42A70704UL))) +#define bM4_PORT_POSRD_POS02 (*((volatile unsigned int*)(0x42A70708UL))) +#define bM4_PORT_POSRD_POS03 (*((volatile unsigned int*)(0x42A7070CUL))) +#define bM4_PORT_POSRD_POS04 (*((volatile unsigned int*)(0x42A70710UL))) +#define bM4_PORT_POSRD_POS05 (*((volatile unsigned int*)(0x42A70714UL))) +#define bM4_PORT_POSRD_POS06 (*((volatile unsigned int*)(0x42A70718UL))) +#define bM4_PORT_POSRD_POS07 (*((volatile unsigned int*)(0x42A7071CUL))) +#define bM4_PORT_POSRD_POS08 (*((volatile unsigned int*)(0x42A70720UL))) +#define bM4_PORT_POSRD_POS09 (*((volatile unsigned int*)(0x42A70724UL))) +#define bM4_PORT_POSRD_POS10 (*((volatile unsigned int*)(0x42A70728UL))) +#define bM4_PORT_POSRD_POS11 (*((volatile unsigned int*)(0x42A7072CUL))) +#define bM4_PORT_POSRD_POS12 (*((volatile unsigned int*)(0x42A70730UL))) +#define bM4_PORT_POSRD_POS13 (*((volatile unsigned int*)(0x42A70734UL))) +#define bM4_PORT_POSRD_POS14 (*((volatile unsigned int*)(0x42A70738UL))) +#define bM4_PORT_POSRD_POS15 (*((volatile unsigned int*)(0x42A7073CUL))) +#define bM4_PORT_PORRD_POR00 (*((volatile unsigned int*)(0x42A70740UL))) +#define bM4_PORT_PORRD_POR01 (*((volatile unsigned int*)(0x42A70744UL))) +#define bM4_PORT_PORRD_POR02 (*((volatile unsigned int*)(0x42A70748UL))) +#define bM4_PORT_PORRD_POR03 (*((volatile unsigned int*)(0x42A7074CUL))) +#define bM4_PORT_PORRD_POR04 (*((volatile unsigned int*)(0x42A70750UL))) +#define bM4_PORT_PORRD_POR05 (*((volatile unsigned int*)(0x42A70754UL))) +#define bM4_PORT_PORRD_POR06 (*((volatile unsigned int*)(0x42A70758UL))) +#define bM4_PORT_PORRD_POR07 (*((volatile unsigned int*)(0x42A7075CUL))) +#define bM4_PORT_PORRD_POR08 (*((volatile unsigned int*)(0x42A70760UL))) +#define bM4_PORT_PORRD_POR09 (*((volatile unsigned int*)(0x42A70764UL))) +#define bM4_PORT_PORRD_POR10 (*((volatile unsigned int*)(0x42A70768UL))) +#define bM4_PORT_PORRD_POR11 (*((volatile unsigned int*)(0x42A7076CUL))) +#define bM4_PORT_PORRD_POR12 (*((volatile unsigned int*)(0x42A70770UL))) +#define bM4_PORT_PORRD_POR13 (*((volatile unsigned int*)(0x42A70774UL))) +#define bM4_PORT_PORRD_POR14 (*((volatile unsigned int*)(0x42A70778UL))) +#define bM4_PORT_PORRD_POR15 (*((volatile unsigned int*)(0x42A7077CUL))) +#define bM4_PORT_POTRD_POT00 (*((volatile unsigned int*)(0x42A70780UL))) +#define bM4_PORT_POTRD_POT01 (*((volatile unsigned int*)(0x42A70784UL))) +#define bM4_PORT_POTRD_POT02 (*((volatile unsigned int*)(0x42A70788UL))) +#define bM4_PORT_POTRD_POT03 (*((volatile unsigned int*)(0x42A7078CUL))) +#define bM4_PORT_POTRD_POT04 (*((volatile unsigned int*)(0x42A70790UL))) +#define bM4_PORT_POTRD_POT05 (*((volatile unsigned int*)(0x42A70794UL))) +#define bM4_PORT_POTRD_POT06 (*((volatile unsigned int*)(0x42A70798UL))) +#define bM4_PORT_POTRD_POT07 (*((volatile unsigned int*)(0x42A7079CUL))) +#define bM4_PORT_POTRD_POT08 (*((volatile unsigned int*)(0x42A707A0UL))) +#define bM4_PORT_POTRD_POT09 (*((volatile unsigned int*)(0x42A707A4UL))) +#define bM4_PORT_POTRD_POT10 (*((volatile unsigned int*)(0x42A707A8UL))) +#define bM4_PORT_POTRD_POT11 (*((volatile unsigned int*)(0x42A707ACUL))) +#define bM4_PORT_POTRD_POT12 (*((volatile unsigned int*)(0x42A707B0UL))) +#define bM4_PORT_POTRD_POT13 (*((volatile unsigned int*)(0x42A707B4UL))) +#define bM4_PORT_POTRD_POT14 (*((volatile unsigned int*)(0x42A707B8UL))) +#define bM4_PORT_POTRD_POT15 (*((volatile unsigned int*)(0x42A707BCUL))) +#define bM4_PORT_PIDRE_PIN00 (*((volatile unsigned int*)(0x42A70800UL))) +#define bM4_PORT_PIDRE_PIN01 (*((volatile unsigned int*)(0x42A70804UL))) +#define bM4_PORT_PIDRE_PIN02 (*((volatile unsigned int*)(0x42A70808UL))) +#define bM4_PORT_PIDRE_PIN03 (*((volatile unsigned int*)(0x42A7080CUL))) +#define bM4_PORT_PIDRE_PIN04 (*((volatile unsigned int*)(0x42A70810UL))) +#define bM4_PORT_PIDRE_PIN05 (*((volatile unsigned int*)(0x42A70814UL))) +#define bM4_PORT_PIDRE_PIN06 (*((volatile unsigned int*)(0x42A70818UL))) +#define bM4_PORT_PIDRE_PIN07 (*((volatile unsigned int*)(0x42A7081CUL))) +#define bM4_PORT_PIDRE_PIN08 (*((volatile unsigned int*)(0x42A70820UL))) +#define bM4_PORT_PIDRE_PIN09 (*((volatile unsigned int*)(0x42A70824UL))) +#define bM4_PORT_PIDRE_PIN10 (*((volatile unsigned int*)(0x42A70828UL))) +#define bM4_PORT_PIDRE_PIN11 (*((volatile unsigned int*)(0x42A7082CUL))) +#define bM4_PORT_PIDRE_PIN12 (*((volatile unsigned int*)(0x42A70830UL))) +#define bM4_PORT_PIDRE_PIN13 (*((volatile unsigned int*)(0x42A70834UL))) +#define bM4_PORT_PIDRE_PIN14 (*((volatile unsigned int*)(0x42A70838UL))) +#define bM4_PORT_PIDRE_PIN15 (*((volatile unsigned int*)(0x42A7083CUL))) +#define bM4_PORT_PODRE_POUT00 (*((volatile unsigned int*)(0x42A70880UL))) +#define bM4_PORT_PODRE_POUT01 (*((volatile unsigned int*)(0x42A70884UL))) +#define bM4_PORT_PODRE_POUT02 (*((volatile unsigned int*)(0x42A70888UL))) +#define bM4_PORT_PODRE_POUT03 (*((volatile unsigned int*)(0x42A7088CUL))) +#define bM4_PORT_PODRE_POUT04 (*((volatile unsigned int*)(0x42A70890UL))) +#define bM4_PORT_PODRE_POUT05 (*((volatile unsigned int*)(0x42A70894UL))) +#define bM4_PORT_PODRE_POUT06 (*((volatile unsigned int*)(0x42A70898UL))) +#define bM4_PORT_PODRE_POUT07 (*((volatile unsigned int*)(0x42A7089CUL))) +#define bM4_PORT_PODRE_POUT08 (*((volatile unsigned int*)(0x42A708A0UL))) +#define bM4_PORT_PODRE_POUT09 (*((volatile unsigned int*)(0x42A708A4UL))) +#define bM4_PORT_PODRE_POUT10 (*((volatile unsigned int*)(0x42A708A8UL))) +#define bM4_PORT_PODRE_POUT11 (*((volatile unsigned int*)(0x42A708ACUL))) +#define bM4_PORT_PODRE_POUT12 (*((volatile unsigned int*)(0x42A708B0UL))) +#define bM4_PORT_PODRE_POUT13 (*((volatile unsigned int*)(0x42A708B4UL))) +#define bM4_PORT_PODRE_POUT14 (*((volatile unsigned int*)(0x42A708B8UL))) +#define bM4_PORT_PODRE_POUT15 (*((volatile unsigned int*)(0x42A708BCUL))) +#define bM4_PORT_POERE_POUTE00 (*((volatile unsigned int*)(0x42A708C0UL))) +#define bM4_PORT_POERE_POUTE01 (*((volatile unsigned int*)(0x42A708C4UL))) +#define bM4_PORT_POERE_POUTE02 (*((volatile unsigned int*)(0x42A708C8UL))) +#define bM4_PORT_POERE_POUTE03 (*((volatile unsigned int*)(0x42A708CCUL))) +#define bM4_PORT_POERE_POUTE04 (*((volatile unsigned int*)(0x42A708D0UL))) +#define bM4_PORT_POERE_POUTE05 (*((volatile unsigned int*)(0x42A708D4UL))) +#define bM4_PORT_POERE_POUTE06 (*((volatile unsigned int*)(0x42A708D8UL))) +#define bM4_PORT_POERE_POUTE07 (*((volatile unsigned int*)(0x42A708DCUL))) +#define bM4_PORT_POERE_POUTE08 (*((volatile unsigned int*)(0x42A708E0UL))) +#define bM4_PORT_POERE_POUTE09 (*((volatile unsigned int*)(0x42A708E4UL))) +#define bM4_PORT_POERE_POUTE10 (*((volatile unsigned int*)(0x42A708E8UL))) +#define bM4_PORT_POERE_POUTE11 (*((volatile unsigned int*)(0x42A708ECUL))) +#define bM4_PORT_POERE_POUTE12 (*((volatile unsigned int*)(0x42A708F0UL))) +#define bM4_PORT_POERE_POUTE13 (*((volatile unsigned int*)(0x42A708F4UL))) +#define bM4_PORT_POERE_POUTE14 (*((volatile unsigned int*)(0x42A708F8UL))) +#define bM4_PORT_POERE_POUTE15 (*((volatile unsigned int*)(0x42A708FCUL))) +#define bM4_PORT_POSRE_POS00 (*((volatile unsigned int*)(0x42A70900UL))) +#define bM4_PORT_POSRE_POS01 (*((volatile unsigned int*)(0x42A70904UL))) +#define bM4_PORT_POSRE_POS02 (*((volatile unsigned int*)(0x42A70908UL))) +#define bM4_PORT_POSRE_POS03 (*((volatile unsigned int*)(0x42A7090CUL))) +#define bM4_PORT_POSRE_POS04 (*((volatile unsigned int*)(0x42A70910UL))) +#define bM4_PORT_POSRE_POS05 (*((volatile unsigned int*)(0x42A70914UL))) +#define bM4_PORT_POSRE_POS06 (*((volatile unsigned int*)(0x42A70918UL))) +#define bM4_PORT_POSRE_POS07 (*((volatile unsigned int*)(0x42A7091CUL))) +#define bM4_PORT_POSRE_POS08 (*((volatile unsigned int*)(0x42A70920UL))) +#define bM4_PORT_POSRE_POS09 (*((volatile unsigned int*)(0x42A70924UL))) +#define bM4_PORT_POSRE_POS10 (*((volatile unsigned int*)(0x42A70928UL))) +#define bM4_PORT_POSRE_POS11 (*((volatile unsigned int*)(0x42A7092CUL))) +#define bM4_PORT_POSRE_POS12 (*((volatile unsigned int*)(0x42A70930UL))) +#define bM4_PORT_POSRE_POS13 (*((volatile unsigned int*)(0x42A70934UL))) +#define bM4_PORT_POSRE_POS14 (*((volatile unsigned int*)(0x42A70938UL))) +#define bM4_PORT_POSRE_POS15 (*((volatile unsigned int*)(0x42A7093CUL))) +#define bM4_PORT_PORRE_POR00 (*((volatile unsigned int*)(0x42A70940UL))) +#define bM4_PORT_PORRE_POR01 (*((volatile unsigned int*)(0x42A70944UL))) +#define bM4_PORT_PORRE_POR02 (*((volatile unsigned int*)(0x42A70948UL))) +#define bM4_PORT_PORRE_POR03 (*((volatile unsigned int*)(0x42A7094CUL))) +#define bM4_PORT_PORRE_POR04 (*((volatile unsigned int*)(0x42A70950UL))) +#define bM4_PORT_PORRE_POR05 (*((volatile unsigned int*)(0x42A70954UL))) +#define bM4_PORT_PORRE_POR06 (*((volatile unsigned int*)(0x42A70958UL))) +#define bM4_PORT_PORRE_POR07 (*((volatile unsigned int*)(0x42A7095CUL))) +#define bM4_PORT_PORRE_POR08 (*((volatile unsigned int*)(0x42A70960UL))) +#define bM4_PORT_PORRE_POR09 (*((volatile unsigned int*)(0x42A70964UL))) +#define bM4_PORT_PORRE_POR10 (*((volatile unsigned int*)(0x42A70968UL))) +#define bM4_PORT_PORRE_POR11 (*((volatile unsigned int*)(0x42A7096CUL))) +#define bM4_PORT_PORRE_POR12 (*((volatile unsigned int*)(0x42A70970UL))) +#define bM4_PORT_PORRE_POR13 (*((volatile unsigned int*)(0x42A70974UL))) +#define bM4_PORT_PORRE_POR14 (*((volatile unsigned int*)(0x42A70978UL))) +#define bM4_PORT_PORRE_POR15 (*((volatile unsigned int*)(0x42A7097CUL))) +#define bM4_PORT_POTRE_POT00 (*((volatile unsigned int*)(0x42A70980UL))) +#define bM4_PORT_POTRE_POT01 (*((volatile unsigned int*)(0x42A70984UL))) +#define bM4_PORT_POTRE_POT02 (*((volatile unsigned int*)(0x42A70988UL))) +#define bM4_PORT_POTRE_POT03 (*((volatile unsigned int*)(0x42A7098CUL))) +#define bM4_PORT_POTRE_POT04 (*((volatile unsigned int*)(0x42A70990UL))) +#define bM4_PORT_POTRE_POT05 (*((volatile unsigned int*)(0x42A70994UL))) +#define bM4_PORT_POTRE_POT06 (*((volatile unsigned int*)(0x42A70998UL))) +#define bM4_PORT_POTRE_POT07 (*((volatile unsigned int*)(0x42A7099CUL))) +#define bM4_PORT_POTRE_POT08 (*((volatile unsigned int*)(0x42A709A0UL))) +#define bM4_PORT_POTRE_POT09 (*((volatile unsigned int*)(0x42A709A4UL))) +#define bM4_PORT_POTRE_POT10 (*((volatile unsigned int*)(0x42A709A8UL))) +#define bM4_PORT_POTRE_POT11 (*((volatile unsigned int*)(0x42A709ACUL))) +#define bM4_PORT_POTRE_POT12 (*((volatile unsigned int*)(0x42A709B0UL))) +#define bM4_PORT_POTRE_POT13 (*((volatile unsigned int*)(0x42A709B4UL))) +#define bM4_PORT_POTRE_POT14 (*((volatile unsigned int*)(0x42A709B8UL))) +#define bM4_PORT_POTRE_POT15 (*((volatile unsigned int*)(0x42A709BCUL))) +#define bM4_PORT_PIDRH_PIN00 (*((volatile unsigned int*)(0x42A70A00UL))) +#define bM4_PORT_PIDRH_PIN01 (*((volatile unsigned int*)(0x42A70A04UL))) +#define bM4_PORT_PIDRH_PIN02 (*((volatile unsigned int*)(0x42A70A08UL))) +#define bM4_PORT_PODRH_POUT00 (*((volatile unsigned int*)(0x42A70A80UL))) +#define bM4_PORT_PODRH_POUT01 (*((volatile unsigned int*)(0x42A70A84UL))) +#define bM4_PORT_PODRH_POUT02 (*((volatile unsigned int*)(0x42A70A88UL))) +#define bM4_PORT_POERH_POUTE00 (*((volatile unsigned int*)(0x42A70AC0UL))) +#define bM4_PORT_POERH_POUTE01 (*((volatile unsigned int*)(0x42A70AC4UL))) +#define bM4_PORT_POERH_POUTE02 (*((volatile unsigned int*)(0x42A70AC8UL))) +#define bM4_PORT_POSRH_POS00 (*((volatile unsigned int*)(0x42A70B00UL))) +#define bM4_PORT_POSRH_POS01 (*((volatile unsigned int*)(0x42A70B04UL))) +#define bM4_PORT_POSRH_POS02 (*((volatile unsigned int*)(0x42A70B08UL))) +#define bM4_PORT_PORRH_POR00 (*((volatile unsigned int*)(0x42A70B40UL))) +#define bM4_PORT_PORRH_POR01 (*((volatile unsigned int*)(0x42A70B44UL))) +#define bM4_PORT_PORRH_POR02 (*((volatile unsigned int*)(0x42A70B48UL))) +#define bM4_PORT_POTRH_POT00 (*((volatile unsigned int*)(0x42A70B80UL))) +#define bM4_PORT_POTRH_POT01 (*((volatile unsigned int*)(0x42A70B84UL))) +#define bM4_PORT_POTRH_POT02 (*((volatile unsigned int*)(0x42A70B88UL))) +#define bM4_PORT_PSPCR_SPFE0 (*((volatile unsigned int*)(0x42A77E80UL))) +#define bM4_PORT_PSPCR_SPFE1 (*((volatile unsigned int*)(0x42A77E84UL))) +#define bM4_PORT_PSPCR_SPFE2 (*((volatile unsigned int*)(0x42A77E88UL))) +#define bM4_PORT_PSPCR_SPFE3 (*((volatile unsigned int*)(0x42A77E8CUL))) +#define bM4_PORT_PSPCR_SPFE4 (*((volatile unsigned int*)(0x42A77E90UL))) +#define bM4_PORT_PCCR_BFSEL0 (*((volatile unsigned int*)(0x42A77F00UL))) +#define bM4_PORT_PCCR_BFSEL1 (*((volatile unsigned int*)(0x42A77F04UL))) +#define bM4_PORT_PCCR_BFSEL2 (*((volatile unsigned int*)(0x42A77F08UL))) +#define bM4_PORT_PCCR_BFSEL3 (*((volatile unsigned int*)(0x42A77F0CUL))) +#define bM4_PORT_PCCR_RDWT0 (*((volatile unsigned int*)(0x42A77F38UL))) +#define bM4_PORT_PCCR_RDWT1 (*((volatile unsigned int*)(0x42A77F3CUL))) +#define bM4_PORT_PINAER_PINAE0 (*((volatile unsigned int*)(0x42A77F40UL))) +#define bM4_PORT_PINAER_PINAE1 (*((volatile unsigned int*)(0x42A77F44UL))) +#define bM4_PORT_PINAER_PINAE2 (*((volatile unsigned int*)(0x42A77F48UL))) +#define bM4_PORT_PINAER_PINAE3 (*((volatile unsigned int*)(0x42A77F4CUL))) +#define bM4_PORT_PINAER_PINAE4 (*((volatile unsigned int*)(0x42A77F50UL))) +#define bM4_PORT_PINAER_PINAE5 (*((volatile unsigned int*)(0x42A77F54UL))) +#define bM4_PORT_PWPR_WE (*((volatile unsigned int*)(0x42A77F80UL))) +#define bM4_PORT_PWPR_WP0 (*((volatile unsigned int*)(0x42A77FA0UL))) +#define bM4_PORT_PWPR_WP1 (*((volatile unsigned int*)(0x42A77FA4UL))) +#define bM4_PORT_PWPR_WP2 (*((volatile unsigned int*)(0x42A77FA8UL))) +#define bM4_PORT_PWPR_WP3 (*((volatile unsigned int*)(0x42A77FACUL))) +#define bM4_PORT_PWPR_WP4 (*((volatile unsigned int*)(0x42A77FB0UL))) +#define bM4_PORT_PWPR_WP5 (*((volatile unsigned int*)(0x42A77FB4UL))) +#define bM4_PORT_PWPR_WP6 (*((volatile unsigned int*)(0x42A77FB8UL))) +#define bM4_PORT_PWPR_WP7 (*((volatile unsigned int*)(0x42A77FBCUL))) +#define bM4_PORT_PCRA0_POUT (*((volatile unsigned int*)(0x42A78000UL))) +#define bM4_PORT_PCRA0_POUTE (*((volatile unsigned int*)(0x42A78004UL))) +#define bM4_PORT_PCRA0_NOD (*((volatile unsigned int*)(0x42A78008UL))) +#define bM4_PORT_PCRA0_DRV0 (*((volatile unsigned int*)(0x42A78010UL))) +#define bM4_PORT_PCRA0_DRV1 (*((volatile unsigned int*)(0x42A78014UL))) +#define bM4_PORT_PCRA0_PUU (*((volatile unsigned int*)(0x42A78018UL))) +#define bM4_PORT_PCRA0_PIN (*((volatile unsigned int*)(0x42A78020UL))) +#define bM4_PORT_PCRA0_INVE (*((volatile unsigned int*)(0x42A78024UL))) +#define bM4_PORT_PCRA0_INTE (*((volatile unsigned int*)(0x42A78030UL))) +#define bM4_PORT_PCRA0_LTE (*((volatile unsigned int*)(0x42A78038UL))) +#define bM4_PORT_PCRA0_DDIS (*((volatile unsigned int*)(0x42A7803CUL))) +#define bM4_PORT_PFSRA0_FSEL0 (*((volatile unsigned int*)(0x42A78040UL))) +#define bM4_PORT_PFSRA0_FSEL1 (*((volatile unsigned int*)(0x42A78044UL))) +#define bM4_PORT_PFSRA0_FSEL2 (*((volatile unsigned int*)(0x42A78048UL))) +#define bM4_PORT_PFSRA0_FSEL3 (*((volatile unsigned int*)(0x42A7804CUL))) +#define bM4_PORT_PFSRA0_FSEL4 (*((volatile unsigned int*)(0x42A78050UL))) +#define bM4_PORT_PFSRA0_FSEL5 (*((volatile unsigned int*)(0x42A78054UL))) +#define bM4_PORT_PFSRA0_BFE (*((volatile unsigned int*)(0x42A78060UL))) +#define bM4_PORT_PCRA1_POUT (*((volatile unsigned int*)(0x42A78080UL))) +#define bM4_PORT_PCRA1_POUTE (*((volatile unsigned int*)(0x42A78084UL))) +#define bM4_PORT_PCRA1_NOD (*((volatile unsigned int*)(0x42A78088UL))) +#define bM4_PORT_PCRA1_DRV0 (*((volatile unsigned int*)(0x42A78090UL))) +#define bM4_PORT_PCRA1_DRV1 (*((volatile unsigned int*)(0x42A78094UL))) +#define bM4_PORT_PCRA1_PUU (*((volatile unsigned int*)(0x42A78098UL))) +#define bM4_PORT_PCRA1_PIN (*((volatile unsigned int*)(0x42A780A0UL))) +#define bM4_PORT_PCRA1_INVE (*((volatile unsigned int*)(0x42A780A4UL))) +#define bM4_PORT_PCRA1_INTE (*((volatile unsigned int*)(0x42A780B0UL))) +#define bM4_PORT_PCRA1_LTE (*((volatile unsigned int*)(0x42A780B8UL))) +#define bM4_PORT_PCRA1_DDIS (*((volatile unsigned int*)(0x42A780BCUL))) +#define bM4_PORT_PFSRA1_FSEL0 (*((volatile unsigned int*)(0x42A780C0UL))) +#define bM4_PORT_PFSRA1_FSEL1 (*((volatile unsigned int*)(0x42A780C4UL))) +#define bM4_PORT_PFSRA1_FSEL2 (*((volatile unsigned int*)(0x42A780C8UL))) +#define bM4_PORT_PFSRA1_FSEL3 (*((volatile unsigned int*)(0x42A780CCUL))) +#define bM4_PORT_PFSRA1_FSEL4 (*((volatile unsigned int*)(0x42A780D0UL))) +#define bM4_PORT_PFSRA1_FSEL5 (*((volatile unsigned int*)(0x42A780D4UL))) +#define bM4_PORT_PFSRA1_BFE (*((volatile unsigned int*)(0x42A780E0UL))) +#define bM4_PORT_PCRA2_POUT (*((volatile unsigned int*)(0x42A78100UL))) +#define bM4_PORT_PCRA2_POUTE (*((volatile unsigned int*)(0x42A78104UL))) +#define bM4_PORT_PCRA2_NOD (*((volatile unsigned int*)(0x42A78108UL))) +#define bM4_PORT_PCRA2_DRV0 (*((volatile unsigned int*)(0x42A78110UL))) +#define bM4_PORT_PCRA2_DRV1 (*((volatile unsigned int*)(0x42A78114UL))) +#define bM4_PORT_PCRA2_PUU (*((volatile unsigned int*)(0x42A78118UL))) +#define bM4_PORT_PCRA2_PIN (*((volatile unsigned int*)(0x42A78120UL))) +#define bM4_PORT_PCRA2_INVE (*((volatile unsigned int*)(0x42A78124UL))) +#define bM4_PORT_PCRA2_INTE (*((volatile unsigned int*)(0x42A78130UL))) +#define bM4_PORT_PCRA2_LTE (*((volatile unsigned int*)(0x42A78138UL))) +#define bM4_PORT_PCRA2_DDIS (*((volatile unsigned int*)(0x42A7813CUL))) +#define bM4_PORT_PFSRA2_FSEL0 (*((volatile unsigned int*)(0x42A78140UL))) +#define bM4_PORT_PFSRA2_FSEL1 (*((volatile unsigned int*)(0x42A78144UL))) +#define bM4_PORT_PFSRA2_FSEL2 (*((volatile unsigned int*)(0x42A78148UL))) +#define bM4_PORT_PFSRA2_FSEL3 (*((volatile unsigned int*)(0x42A7814CUL))) +#define bM4_PORT_PFSRA2_FSEL4 (*((volatile unsigned int*)(0x42A78150UL))) +#define bM4_PORT_PFSRA2_FSEL5 (*((volatile unsigned int*)(0x42A78154UL))) +#define bM4_PORT_PFSRA2_BFE (*((volatile unsigned int*)(0x42A78160UL))) +#define bM4_PORT_PCRA3_POUT (*((volatile unsigned int*)(0x42A78180UL))) +#define bM4_PORT_PCRA3_POUTE (*((volatile unsigned int*)(0x42A78184UL))) +#define bM4_PORT_PCRA3_NOD (*((volatile unsigned int*)(0x42A78188UL))) +#define bM4_PORT_PCRA3_DRV0 (*((volatile unsigned int*)(0x42A78190UL))) +#define bM4_PORT_PCRA3_DRV1 (*((volatile unsigned int*)(0x42A78194UL))) +#define bM4_PORT_PCRA3_PUU (*((volatile unsigned int*)(0x42A78198UL))) +#define bM4_PORT_PCRA3_PIN (*((volatile unsigned int*)(0x42A781A0UL))) +#define bM4_PORT_PCRA3_INVE (*((volatile unsigned int*)(0x42A781A4UL))) +#define bM4_PORT_PCRA3_INTE (*((volatile unsigned int*)(0x42A781B0UL))) +#define bM4_PORT_PCRA3_LTE (*((volatile unsigned int*)(0x42A781B8UL))) +#define bM4_PORT_PCRA3_DDIS (*((volatile unsigned int*)(0x42A781BCUL))) +#define bM4_PORT_PFSRA3_FSEL0 (*((volatile unsigned int*)(0x42A781C0UL))) +#define bM4_PORT_PFSRA3_FSEL1 (*((volatile unsigned int*)(0x42A781C4UL))) +#define bM4_PORT_PFSRA3_FSEL2 (*((volatile unsigned int*)(0x42A781C8UL))) +#define bM4_PORT_PFSRA3_FSEL3 (*((volatile unsigned int*)(0x42A781CCUL))) +#define bM4_PORT_PFSRA3_FSEL4 (*((volatile unsigned int*)(0x42A781D0UL))) +#define bM4_PORT_PFSRA3_FSEL5 (*((volatile unsigned int*)(0x42A781D4UL))) +#define bM4_PORT_PFSRA3_BFE (*((volatile unsigned int*)(0x42A781E0UL))) +#define bM4_PORT_PCRA4_POUT (*((volatile unsigned int*)(0x42A78200UL))) +#define bM4_PORT_PCRA4_POUTE (*((volatile unsigned int*)(0x42A78204UL))) +#define bM4_PORT_PCRA4_NOD (*((volatile unsigned int*)(0x42A78208UL))) +#define bM4_PORT_PCRA4_DRV0 (*((volatile unsigned int*)(0x42A78210UL))) +#define bM4_PORT_PCRA4_DRV1 (*((volatile unsigned int*)(0x42A78214UL))) +#define bM4_PORT_PCRA4_PUU (*((volatile unsigned int*)(0x42A78218UL))) +#define bM4_PORT_PCRA4_PIN (*((volatile unsigned int*)(0x42A78220UL))) +#define bM4_PORT_PCRA4_INVE (*((volatile unsigned int*)(0x42A78224UL))) +#define bM4_PORT_PCRA4_INTE (*((volatile unsigned int*)(0x42A78230UL))) +#define bM4_PORT_PCRA4_LTE (*((volatile unsigned int*)(0x42A78238UL))) +#define bM4_PORT_PCRA4_DDIS (*((volatile unsigned int*)(0x42A7823CUL))) +#define bM4_PORT_PFSRA4_FSEL0 (*((volatile unsigned int*)(0x42A78240UL))) +#define bM4_PORT_PFSRA4_FSEL1 (*((volatile unsigned int*)(0x42A78244UL))) +#define bM4_PORT_PFSRA4_FSEL2 (*((volatile unsigned int*)(0x42A78248UL))) +#define bM4_PORT_PFSRA4_FSEL3 (*((volatile unsigned int*)(0x42A7824CUL))) +#define bM4_PORT_PFSRA4_FSEL4 (*((volatile unsigned int*)(0x42A78250UL))) +#define bM4_PORT_PFSRA4_FSEL5 (*((volatile unsigned int*)(0x42A78254UL))) +#define bM4_PORT_PFSRA4_BFE (*((volatile unsigned int*)(0x42A78260UL))) +#define bM4_PORT_PCRA5_POUT (*((volatile unsigned int*)(0x42A78280UL))) +#define bM4_PORT_PCRA5_POUTE (*((volatile unsigned int*)(0x42A78284UL))) +#define bM4_PORT_PCRA5_NOD (*((volatile unsigned int*)(0x42A78288UL))) +#define bM4_PORT_PCRA5_DRV0 (*((volatile unsigned int*)(0x42A78290UL))) +#define bM4_PORT_PCRA5_DRV1 (*((volatile unsigned int*)(0x42A78294UL))) +#define bM4_PORT_PCRA5_PUU (*((volatile unsigned int*)(0x42A78298UL))) +#define bM4_PORT_PCRA5_PIN (*((volatile unsigned int*)(0x42A782A0UL))) +#define bM4_PORT_PCRA5_INVE (*((volatile unsigned int*)(0x42A782A4UL))) +#define bM4_PORT_PCRA5_INTE (*((volatile unsigned int*)(0x42A782B0UL))) +#define bM4_PORT_PCRA5_LTE (*((volatile unsigned int*)(0x42A782B8UL))) +#define bM4_PORT_PCRA5_DDIS (*((volatile unsigned int*)(0x42A782BCUL))) +#define bM4_PORT_PFSRA5_FSEL0 (*((volatile unsigned int*)(0x42A782C0UL))) +#define bM4_PORT_PFSRA5_FSEL1 (*((volatile unsigned int*)(0x42A782C4UL))) +#define bM4_PORT_PFSRA5_FSEL2 (*((volatile unsigned int*)(0x42A782C8UL))) +#define bM4_PORT_PFSRA5_FSEL3 (*((volatile unsigned int*)(0x42A782CCUL))) +#define bM4_PORT_PFSRA5_FSEL4 (*((volatile unsigned int*)(0x42A782D0UL))) +#define bM4_PORT_PFSRA5_FSEL5 (*((volatile unsigned int*)(0x42A782D4UL))) +#define bM4_PORT_PFSRA5_BFE (*((volatile unsigned int*)(0x42A782E0UL))) +#define bM4_PORT_PCRA6_POUT (*((volatile unsigned int*)(0x42A78300UL))) +#define bM4_PORT_PCRA6_POUTE (*((volatile unsigned int*)(0x42A78304UL))) +#define bM4_PORT_PCRA6_NOD (*((volatile unsigned int*)(0x42A78308UL))) +#define bM4_PORT_PCRA6_DRV0 (*((volatile unsigned int*)(0x42A78310UL))) +#define bM4_PORT_PCRA6_DRV1 (*((volatile unsigned int*)(0x42A78314UL))) +#define bM4_PORT_PCRA6_PUU (*((volatile unsigned int*)(0x42A78318UL))) +#define bM4_PORT_PCRA6_PIN (*((volatile unsigned int*)(0x42A78320UL))) +#define bM4_PORT_PCRA6_INVE (*((volatile unsigned int*)(0x42A78324UL))) +#define bM4_PORT_PCRA6_INTE (*((volatile unsigned int*)(0x42A78330UL))) +#define bM4_PORT_PCRA6_LTE (*((volatile unsigned int*)(0x42A78338UL))) +#define bM4_PORT_PCRA6_DDIS (*((volatile unsigned int*)(0x42A7833CUL))) +#define bM4_PORT_PFSRA6_FSEL0 (*((volatile unsigned int*)(0x42A78340UL))) +#define bM4_PORT_PFSRA6_FSEL1 (*((volatile unsigned int*)(0x42A78344UL))) +#define bM4_PORT_PFSRA6_FSEL2 (*((volatile unsigned int*)(0x42A78348UL))) +#define bM4_PORT_PFSRA6_FSEL3 (*((volatile unsigned int*)(0x42A7834CUL))) +#define bM4_PORT_PFSRA6_FSEL4 (*((volatile unsigned int*)(0x42A78350UL))) +#define bM4_PORT_PFSRA6_FSEL5 (*((volatile unsigned int*)(0x42A78354UL))) +#define bM4_PORT_PFSRA6_BFE (*((volatile unsigned int*)(0x42A78360UL))) +#define bM4_PORT_PCRA7_POUT (*((volatile unsigned int*)(0x42A78380UL))) +#define bM4_PORT_PCRA7_POUTE (*((volatile unsigned int*)(0x42A78384UL))) +#define bM4_PORT_PCRA7_NOD (*((volatile unsigned int*)(0x42A78388UL))) +#define bM4_PORT_PCRA7_DRV0 (*((volatile unsigned int*)(0x42A78390UL))) +#define bM4_PORT_PCRA7_DRV1 (*((volatile unsigned int*)(0x42A78394UL))) +#define bM4_PORT_PCRA7_PUU (*((volatile unsigned int*)(0x42A78398UL))) +#define bM4_PORT_PCRA7_PIN (*((volatile unsigned int*)(0x42A783A0UL))) +#define bM4_PORT_PCRA7_INVE (*((volatile unsigned int*)(0x42A783A4UL))) +#define bM4_PORT_PCRA7_INTE (*((volatile unsigned int*)(0x42A783B0UL))) +#define bM4_PORT_PCRA7_LTE (*((volatile unsigned int*)(0x42A783B8UL))) +#define bM4_PORT_PCRA7_DDIS (*((volatile unsigned int*)(0x42A783BCUL))) +#define bM4_PORT_PFSRA7_FSEL0 (*((volatile unsigned int*)(0x42A783C0UL))) +#define bM4_PORT_PFSRA7_FSEL1 (*((volatile unsigned int*)(0x42A783C4UL))) +#define bM4_PORT_PFSRA7_FSEL2 (*((volatile unsigned int*)(0x42A783C8UL))) +#define bM4_PORT_PFSRA7_FSEL3 (*((volatile unsigned int*)(0x42A783CCUL))) +#define bM4_PORT_PFSRA7_FSEL4 (*((volatile unsigned int*)(0x42A783D0UL))) +#define bM4_PORT_PFSRA7_FSEL5 (*((volatile unsigned int*)(0x42A783D4UL))) +#define bM4_PORT_PFSRA7_BFE (*((volatile unsigned int*)(0x42A783E0UL))) +#define bM4_PORT_PCRA8_POUT (*((volatile unsigned int*)(0x42A78400UL))) +#define bM4_PORT_PCRA8_POUTE (*((volatile unsigned int*)(0x42A78404UL))) +#define bM4_PORT_PCRA8_NOD (*((volatile unsigned int*)(0x42A78408UL))) +#define bM4_PORT_PCRA8_DRV0 (*((volatile unsigned int*)(0x42A78410UL))) +#define bM4_PORT_PCRA8_DRV1 (*((volatile unsigned int*)(0x42A78414UL))) +#define bM4_PORT_PCRA8_PUU (*((volatile unsigned int*)(0x42A78418UL))) +#define bM4_PORT_PCRA8_PIN (*((volatile unsigned int*)(0x42A78420UL))) +#define bM4_PORT_PCRA8_INVE (*((volatile unsigned int*)(0x42A78424UL))) +#define bM4_PORT_PCRA8_INTE (*((volatile unsigned int*)(0x42A78430UL))) +#define bM4_PORT_PCRA8_LTE (*((volatile unsigned int*)(0x42A78438UL))) +#define bM4_PORT_PCRA8_DDIS (*((volatile unsigned int*)(0x42A7843CUL))) +#define bM4_PORT_PFSRA8_FSEL0 (*((volatile unsigned int*)(0x42A78440UL))) +#define bM4_PORT_PFSRA8_FSEL1 (*((volatile unsigned int*)(0x42A78444UL))) +#define bM4_PORT_PFSRA8_FSEL2 (*((volatile unsigned int*)(0x42A78448UL))) +#define bM4_PORT_PFSRA8_FSEL3 (*((volatile unsigned int*)(0x42A7844CUL))) +#define bM4_PORT_PFSRA8_FSEL4 (*((volatile unsigned int*)(0x42A78450UL))) +#define bM4_PORT_PFSRA8_FSEL5 (*((volatile unsigned int*)(0x42A78454UL))) +#define bM4_PORT_PFSRA8_BFE (*((volatile unsigned int*)(0x42A78460UL))) +#define bM4_PORT_PCRA9_POUT (*((volatile unsigned int*)(0x42A78480UL))) +#define bM4_PORT_PCRA9_POUTE (*((volatile unsigned int*)(0x42A78484UL))) +#define bM4_PORT_PCRA9_NOD (*((volatile unsigned int*)(0x42A78488UL))) +#define bM4_PORT_PCRA9_DRV0 (*((volatile unsigned int*)(0x42A78490UL))) +#define bM4_PORT_PCRA9_DRV1 (*((volatile unsigned int*)(0x42A78494UL))) +#define bM4_PORT_PCRA9_PUU (*((volatile unsigned int*)(0x42A78498UL))) +#define bM4_PORT_PCRA9_PIN (*((volatile unsigned int*)(0x42A784A0UL))) +#define bM4_PORT_PCRA9_INVE (*((volatile unsigned int*)(0x42A784A4UL))) +#define bM4_PORT_PCRA9_INTE (*((volatile unsigned int*)(0x42A784B0UL))) +#define bM4_PORT_PCRA9_LTE (*((volatile unsigned int*)(0x42A784B8UL))) +#define bM4_PORT_PCRA9_DDIS (*((volatile unsigned int*)(0x42A784BCUL))) +#define bM4_PORT_PFSRA9_FSEL0 (*((volatile unsigned int*)(0x42A784C0UL))) +#define bM4_PORT_PFSRA9_FSEL1 (*((volatile unsigned int*)(0x42A784C4UL))) +#define bM4_PORT_PFSRA9_FSEL2 (*((volatile unsigned int*)(0x42A784C8UL))) +#define bM4_PORT_PFSRA9_FSEL3 (*((volatile unsigned int*)(0x42A784CCUL))) +#define bM4_PORT_PFSRA9_FSEL4 (*((volatile unsigned int*)(0x42A784D0UL))) +#define bM4_PORT_PFSRA9_FSEL5 (*((volatile unsigned int*)(0x42A784D4UL))) +#define bM4_PORT_PFSRA9_BFE (*((volatile unsigned int*)(0x42A784E0UL))) +#define bM4_PORT_PCRA10_POUT (*((volatile unsigned int*)(0x42A78500UL))) +#define bM4_PORT_PCRA10_POUTE (*((volatile unsigned int*)(0x42A78504UL))) +#define bM4_PORT_PCRA10_NOD (*((volatile unsigned int*)(0x42A78508UL))) +#define bM4_PORT_PCRA10_DRV0 (*((volatile unsigned int*)(0x42A78510UL))) +#define bM4_PORT_PCRA10_DRV1 (*((volatile unsigned int*)(0x42A78514UL))) +#define bM4_PORT_PCRA10_PUU (*((volatile unsigned int*)(0x42A78518UL))) +#define bM4_PORT_PCRA10_PIN (*((volatile unsigned int*)(0x42A78520UL))) +#define bM4_PORT_PCRA10_INVE (*((volatile unsigned int*)(0x42A78524UL))) +#define bM4_PORT_PCRA10_INTE (*((volatile unsigned int*)(0x42A78530UL))) +#define bM4_PORT_PCRA10_LTE (*((volatile unsigned int*)(0x42A78538UL))) +#define bM4_PORT_PCRA10_DDIS (*((volatile unsigned int*)(0x42A7853CUL))) +#define bM4_PORT_PFSRA10_FSEL0 (*((volatile unsigned int*)(0x42A78540UL))) +#define bM4_PORT_PFSRA10_FSEL1 (*((volatile unsigned int*)(0x42A78544UL))) +#define bM4_PORT_PFSRA10_FSEL2 (*((volatile unsigned int*)(0x42A78548UL))) +#define bM4_PORT_PFSRA10_FSEL3 (*((volatile unsigned int*)(0x42A7854CUL))) +#define bM4_PORT_PFSRA10_FSEL4 (*((volatile unsigned int*)(0x42A78550UL))) +#define bM4_PORT_PFSRA10_FSEL5 (*((volatile unsigned int*)(0x42A78554UL))) +#define bM4_PORT_PFSRA10_BFE (*((volatile unsigned int*)(0x42A78560UL))) +#define bM4_PORT_PCRA11_POUT (*((volatile unsigned int*)(0x42A78580UL))) +#define bM4_PORT_PCRA11_POUTE (*((volatile unsigned int*)(0x42A78584UL))) +#define bM4_PORT_PCRA11_NOD (*((volatile unsigned int*)(0x42A78588UL))) +#define bM4_PORT_PCRA11_DRV0 (*((volatile unsigned int*)(0x42A78590UL))) +#define bM4_PORT_PCRA11_DRV1 (*((volatile unsigned int*)(0x42A78594UL))) +#define bM4_PORT_PCRA11_PUU (*((volatile unsigned int*)(0x42A78598UL))) +#define bM4_PORT_PCRA11_PIN (*((volatile unsigned int*)(0x42A785A0UL))) +#define bM4_PORT_PCRA11_INVE (*((volatile unsigned int*)(0x42A785A4UL))) +#define bM4_PORT_PCRA11_INTE (*((volatile unsigned int*)(0x42A785B0UL))) +#define bM4_PORT_PCRA11_LTE (*((volatile unsigned int*)(0x42A785B8UL))) +#define bM4_PORT_PCRA11_DDIS (*((volatile unsigned int*)(0x42A785BCUL))) +#define bM4_PORT_PFSRA11_FSEL0 (*((volatile unsigned int*)(0x42A785C0UL))) +#define bM4_PORT_PFSRA11_FSEL1 (*((volatile unsigned int*)(0x42A785C4UL))) +#define bM4_PORT_PFSRA11_FSEL2 (*((volatile unsigned int*)(0x42A785C8UL))) +#define bM4_PORT_PFSRA11_FSEL3 (*((volatile unsigned int*)(0x42A785CCUL))) +#define bM4_PORT_PFSRA11_FSEL4 (*((volatile unsigned int*)(0x42A785D0UL))) +#define bM4_PORT_PFSRA11_FSEL5 (*((volatile unsigned int*)(0x42A785D4UL))) +#define bM4_PORT_PFSRA11_BFE (*((volatile unsigned int*)(0x42A785E0UL))) +#define bM4_PORT_PCRA12_POUT (*((volatile unsigned int*)(0x42A78600UL))) +#define bM4_PORT_PCRA12_POUTE (*((volatile unsigned int*)(0x42A78604UL))) +#define bM4_PORT_PCRA12_NOD (*((volatile unsigned int*)(0x42A78608UL))) +#define bM4_PORT_PCRA12_DRV0 (*((volatile unsigned int*)(0x42A78610UL))) +#define bM4_PORT_PCRA12_DRV1 (*((volatile unsigned int*)(0x42A78614UL))) +#define bM4_PORT_PCRA12_PUU (*((volatile unsigned int*)(0x42A78618UL))) +#define bM4_PORT_PCRA12_PIN (*((volatile unsigned int*)(0x42A78620UL))) +#define bM4_PORT_PCRA12_INVE (*((volatile unsigned int*)(0x42A78624UL))) +#define bM4_PORT_PCRA12_INTE (*((volatile unsigned int*)(0x42A78630UL))) +#define bM4_PORT_PCRA12_LTE (*((volatile unsigned int*)(0x42A78638UL))) +#define bM4_PORT_PCRA12_DDIS (*((volatile unsigned int*)(0x42A7863CUL))) +#define bM4_PORT_PFSRA12_FSEL0 (*((volatile unsigned int*)(0x42A78640UL))) +#define bM4_PORT_PFSRA12_FSEL1 (*((volatile unsigned int*)(0x42A78644UL))) +#define bM4_PORT_PFSRA12_FSEL2 (*((volatile unsigned int*)(0x42A78648UL))) +#define bM4_PORT_PFSRA12_FSEL3 (*((volatile unsigned int*)(0x42A7864CUL))) +#define bM4_PORT_PFSRA12_FSEL4 (*((volatile unsigned int*)(0x42A78650UL))) +#define bM4_PORT_PFSRA12_FSEL5 (*((volatile unsigned int*)(0x42A78654UL))) +#define bM4_PORT_PFSRA12_BFE (*((volatile unsigned int*)(0x42A78660UL))) +#define bM4_PORT_PCRA13_POUT (*((volatile unsigned int*)(0x42A78680UL))) +#define bM4_PORT_PCRA13_POUTE (*((volatile unsigned int*)(0x42A78684UL))) +#define bM4_PORT_PCRA13_NOD (*((volatile unsigned int*)(0x42A78688UL))) +#define bM4_PORT_PCRA13_DRV0 (*((volatile unsigned int*)(0x42A78690UL))) +#define bM4_PORT_PCRA13_DRV1 (*((volatile unsigned int*)(0x42A78694UL))) +#define bM4_PORT_PCRA13_PUU (*((volatile unsigned int*)(0x42A78698UL))) +#define bM4_PORT_PCRA13_PIN (*((volatile unsigned int*)(0x42A786A0UL))) +#define bM4_PORT_PCRA13_INVE (*((volatile unsigned int*)(0x42A786A4UL))) +#define bM4_PORT_PCRA13_INTE (*((volatile unsigned int*)(0x42A786B0UL))) +#define bM4_PORT_PCRA13_LTE (*((volatile unsigned int*)(0x42A786B8UL))) +#define bM4_PORT_PCRA13_DDIS (*((volatile unsigned int*)(0x42A786BCUL))) +#define bM4_PORT_PFSRA13_FSEL0 (*((volatile unsigned int*)(0x42A786C0UL))) +#define bM4_PORT_PFSRA13_FSEL1 (*((volatile unsigned int*)(0x42A786C4UL))) +#define bM4_PORT_PFSRA13_FSEL2 (*((volatile unsigned int*)(0x42A786C8UL))) +#define bM4_PORT_PFSRA13_FSEL3 (*((volatile unsigned int*)(0x42A786CCUL))) +#define bM4_PORT_PFSRA13_FSEL4 (*((volatile unsigned int*)(0x42A786D0UL))) +#define bM4_PORT_PFSRA13_FSEL5 (*((volatile unsigned int*)(0x42A786D4UL))) +#define bM4_PORT_PFSRA13_BFE (*((volatile unsigned int*)(0x42A786E0UL))) +#define bM4_PORT_PCRA14_POUT (*((volatile unsigned int*)(0x42A78700UL))) +#define bM4_PORT_PCRA14_POUTE (*((volatile unsigned int*)(0x42A78704UL))) +#define bM4_PORT_PCRA14_NOD (*((volatile unsigned int*)(0x42A78708UL))) +#define bM4_PORT_PCRA14_DRV0 (*((volatile unsigned int*)(0x42A78710UL))) +#define bM4_PORT_PCRA14_DRV1 (*((volatile unsigned int*)(0x42A78714UL))) +#define bM4_PORT_PCRA14_PUU (*((volatile unsigned int*)(0x42A78718UL))) +#define bM4_PORT_PCRA14_PIN (*((volatile unsigned int*)(0x42A78720UL))) +#define bM4_PORT_PCRA14_INVE (*((volatile unsigned int*)(0x42A78724UL))) +#define bM4_PORT_PCRA14_INTE (*((volatile unsigned int*)(0x42A78730UL))) +#define bM4_PORT_PCRA14_LTE (*((volatile unsigned int*)(0x42A78738UL))) +#define bM4_PORT_PCRA14_DDIS (*((volatile unsigned int*)(0x42A7873CUL))) +#define bM4_PORT_PFSRA14_FSEL0 (*((volatile unsigned int*)(0x42A78740UL))) +#define bM4_PORT_PFSRA14_FSEL1 (*((volatile unsigned int*)(0x42A78744UL))) +#define bM4_PORT_PFSRA14_FSEL2 (*((volatile unsigned int*)(0x42A78748UL))) +#define bM4_PORT_PFSRA14_FSEL3 (*((volatile unsigned int*)(0x42A7874CUL))) +#define bM4_PORT_PFSRA14_FSEL4 (*((volatile unsigned int*)(0x42A78750UL))) +#define bM4_PORT_PFSRA14_FSEL5 (*((volatile unsigned int*)(0x42A78754UL))) +#define bM4_PORT_PFSRA14_BFE (*((volatile unsigned int*)(0x42A78760UL))) +#define bM4_PORT_PCRA15_POUT (*((volatile unsigned int*)(0x42A78780UL))) +#define bM4_PORT_PCRA15_POUTE (*((volatile unsigned int*)(0x42A78784UL))) +#define bM4_PORT_PCRA15_NOD (*((volatile unsigned int*)(0x42A78788UL))) +#define bM4_PORT_PCRA15_DRV0 (*((volatile unsigned int*)(0x42A78790UL))) +#define bM4_PORT_PCRA15_DRV1 (*((volatile unsigned int*)(0x42A78794UL))) +#define bM4_PORT_PCRA15_PUU (*((volatile unsigned int*)(0x42A78798UL))) +#define bM4_PORT_PCRA15_PIN (*((volatile unsigned int*)(0x42A787A0UL))) +#define bM4_PORT_PCRA15_INVE (*((volatile unsigned int*)(0x42A787A4UL))) +#define bM4_PORT_PCRA15_INTE (*((volatile unsigned int*)(0x42A787B0UL))) +#define bM4_PORT_PCRA15_LTE (*((volatile unsigned int*)(0x42A787B8UL))) +#define bM4_PORT_PCRA15_DDIS (*((volatile unsigned int*)(0x42A787BCUL))) +#define bM4_PORT_PFSRA15_FSEL0 (*((volatile unsigned int*)(0x42A787C0UL))) +#define bM4_PORT_PFSRA15_FSEL1 (*((volatile unsigned int*)(0x42A787C4UL))) +#define bM4_PORT_PFSRA15_FSEL2 (*((volatile unsigned int*)(0x42A787C8UL))) +#define bM4_PORT_PFSRA15_FSEL3 (*((volatile unsigned int*)(0x42A787CCUL))) +#define bM4_PORT_PFSRA15_FSEL4 (*((volatile unsigned int*)(0x42A787D0UL))) +#define bM4_PORT_PFSRA15_FSEL5 (*((volatile unsigned int*)(0x42A787D4UL))) +#define bM4_PORT_PFSRA15_BFE (*((volatile unsigned int*)(0x42A787E0UL))) +#define bM4_PORT_PCRB0_POUT (*((volatile unsigned int*)(0x42A78800UL))) +#define bM4_PORT_PCRB0_POUTE (*((volatile unsigned int*)(0x42A78804UL))) +#define bM4_PORT_PCRB0_NOD (*((volatile unsigned int*)(0x42A78808UL))) +#define bM4_PORT_PCRB0_DRV0 (*((volatile unsigned int*)(0x42A78810UL))) +#define bM4_PORT_PCRB0_DRV1 (*((volatile unsigned int*)(0x42A78814UL))) +#define bM4_PORT_PCRB0_PUU (*((volatile unsigned int*)(0x42A78818UL))) +#define bM4_PORT_PCRB0_PIN (*((volatile unsigned int*)(0x42A78820UL))) +#define bM4_PORT_PCRB0_INVE (*((volatile unsigned int*)(0x42A78824UL))) +#define bM4_PORT_PCRB0_INTE (*((volatile unsigned int*)(0x42A78830UL))) +#define bM4_PORT_PCRB0_LTE (*((volatile unsigned int*)(0x42A78838UL))) +#define bM4_PORT_PCRB0_DDIS (*((volatile unsigned int*)(0x42A7883CUL))) +#define bM4_PORT_PFSRB0_FSEL0 (*((volatile unsigned int*)(0x42A78840UL))) +#define bM4_PORT_PFSRB0_FSEL1 (*((volatile unsigned int*)(0x42A78844UL))) +#define bM4_PORT_PFSRB0_FSEL2 (*((volatile unsigned int*)(0x42A78848UL))) +#define bM4_PORT_PFSRB0_FSEL3 (*((volatile unsigned int*)(0x42A7884CUL))) +#define bM4_PORT_PFSRB0_FSEL4 (*((volatile unsigned int*)(0x42A78850UL))) +#define bM4_PORT_PFSRB0_FSEL5 (*((volatile unsigned int*)(0x42A78854UL))) +#define bM4_PORT_PFSRB0_BFE (*((volatile unsigned int*)(0x42A78860UL))) +#define bM4_PORT_PCRB1_POUT (*((volatile unsigned int*)(0x42A78880UL))) +#define bM4_PORT_PCRB1_POUTE (*((volatile unsigned int*)(0x42A78884UL))) +#define bM4_PORT_PCRB1_NOD (*((volatile unsigned int*)(0x42A78888UL))) +#define bM4_PORT_PCRB1_DRV0 (*((volatile unsigned int*)(0x42A78890UL))) +#define bM4_PORT_PCRB1_DRV1 (*((volatile unsigned int*)(0x42A78894UL))) +#define bM4_PORT_PCRB1_PUU (*((volatile unsigned int*)(0x42A78898UL))) +#define bM4_PORT_PCRB1_PIN (*((volatile unsigned int*)(0x42A788A0UL))) +#define bM4_PORT_PCRB1_INVE (*((volatile unsigned int*)(0x42A788A4UL))) +#define bM4_PORT_PCRB1_INTE (*((volatile unsigned int*)(0x42A788B0UL))) +#define bM4_PORT_PCRB1_LTE (*((volatile unsigned int*)(0x42A788B8UL))) +#define bM4_PORT_PCRB1_DDIS (*((volatile unsigned int*)(0x42A788BCUL))) +#define bM4_PORT_PFSRB1_FSEL0 (*((volatile unsigned int*)(0x42A788C0UL))) +#define bM4_PORT_PFSRB1_FSEL1 (*((volatile unsigned int*)(0x42A788C4UL))) +#define bM4_PORT_PFSRB1_FSEL2 (*((volatile unsigned int*)(0x42A788C8UL))) +#define bM4_PORT_PFSRB1_FSEL3 (*((volatile unsigned int*)(0x42A788CCUL))) +#define bM4_PORT_PFSRB1_FSEL4 (*((volatile unsigned int*)(0x42A788D0UL))) +#define bM4_PORT_PFSRB1_FSEL5 (*((volatile unsigned int*)(0x42A788D4UL))) +#define bM4_PORT_PFSRB1_BFE (*((volatile unsigned int*)(0x42A788E0UL))) +#define bM4_PORT_PCRB2_POUT (*((volatile unsigned int*)(0x42A78900UL))) +#define bM4_PORT_PCRB2_POUTE (*((volatile unsigned int*)(0x42A78904UL))) +#define bM4_PORT_PCRB2_NOD (*((volatile unsigned int*)(0x42A78908UL))) +#define bM4_PORT_PCRB2_DRV0 (*((volatile unsigned int*)(0x42A78910UL))) +#define bM4_PORT_PCRB2_DRV1 (*((volatile unsigned int*)(0x42A78914UL))) +#define bM4_PORT_PCRB2_PUU (*((volatile unsigned int*)(0x42A78918UL))) +#define bM4_PORT_PCRB2_PIN (*((volatile unsigned int*)(0x42A78920UL))) +#define bM4_PORT_PCRB2_INVE (*((volatile unsigned int*)(0x42A78924UL))) +#define bM4_PORT_PCRB2_INTE (*((volatile unsigned int*)(0x42A78930UL))) +#define bM4_PORT_PCRB2_LTE (*((volatile unsigned int*)(0x42A78938UL))) +#define bM4_PORT_PCRB2_DDIS (*((volatile unsigned int*)(0x42A7893CUL))) +#define bM4_PORT_PFSRB2_FSEL0 (*((volatile unsigned int*)(0x42A78940UL))) +#define bM4_PORT_PFSRB2_FSEL1 (*((volatile unsigned int*)(0x42A78944UL))) +#define bM4_PORT_PFSRB2_FSEL2 (*((volatile unsigned int*)(0x42A78948UL))) +#define bM4_PORT_PFSRB2_FSEL3 (*((volatile unsigned int*)(0x42A7894CUL))) +#define bM4_PORT_PFSRB2_FSEL4 (*((volatile unsigned int*)(0x42A78950UL))) +#define bM4_PORT_PFSRB2_FSEL5 (*((volatile unsigned int*)(0x42A78954UL))) +#define bM4_PORT_PFSRB2_BFE (*((volatile unsigned int*)(0x42A78960UL))) +#define bM4_PORT_PCRB3_POUT (*((volatile unsigned int*)(0x42A78980UL))) +#define bM4_PORT_PCRB3_POUTE (*((volatile unsigned int*)(0x42A78984UL))) +#define bM4_PORT_PCRB3_NOD (*((volatile unsigned int*)(0x42A78988UL))) +#define bM4_PORT_PCRB3_DRV0 (*((volatile unsigned int*)(0x42A78990UL))) +#define bM4_PORT_PCRB3_DRV1 (*((volatile unsigned int*)(0x42A78994UL))) +#define bM4_PORT_PCRB3_PUU (*((volatile unsigned int*)(0x42A78998UL))) +#define bM4_PORT_PCRB3_PIN (*((volatile unsigned int*)(0x42A789A0UL))) +#define bM4_PORT_PCRB3_INVE (*((volatile unsigned int*)(0x42A789A4UL))) +#define bM4_PORT_PCRB3_INTE (*((volatile unsigned int*)(0x42A789B0UL))) +#define bM4_PORT_PCRB3_LTE (*((volatile unsigned int*)(0x42A789B8UL))) +#define bM4_PORT_PCRB3_DDIS (*((volatile unsigned int*)(0x42A789BCUL))) +#define bM4_PORT_PFSRB3_FSEL0 (*((volatile unsigned int*)(0x42A789C0UL))) +#define bM4_PORT_PFSRB3_FSEL1 (*((volatile unsigned int*)(0x42A789C4UL))) +#define bM4_PORT_PFSRB3_FSEL2 (*((volatile unsigned int*)(0x42A789C8UL))) +#define bM4_PORT_PFSRB3_FSEL3 (*((volatile unsigned int*)(0x42A789CCUL))) +#define bM4_PORT_PFSRB3_FSEL4 (*((volatile unsigned int*)(0x42A789D0UL))) +#define bM4_PORT_PFSRB3_FSEL5 (*((volatile unsigned int*)(0x42A789D4UL))) +#define bM4_PORT_PFSRB3_BFE (*((volatile unsigned int*)(0x42A789E0UL))) +#define bM4_PORT_PCRB4_POUT (*((volatile unsigned int*)(0x42A78A00UL))) +#define bM4_PORT_PCRB4_POUTE (*((volatile unsigned int*)(0x42A78A04UL))) +#define bM4_PORT_PCRB4_NOD (*((volatile unsigned int*)(0x42A78A08UL))) +#define bM4_PORT_PCRB4_DRV0 (*((volatile unsigned int*)(0x42A78A10UL))) +#define bM4_PORT_PCRB4_DRV1 (*((volatile unsigned int*)(0x42A78A14UL))) +#define bM4_PORT_PCRB4_PUU (*((volatile unsigned int*)(0x42A78A18UL))) +#define bM4_PORT_PCRB4_PIN (*((volatile unsigned int*)(0x42A78A20UL))) +#define bM4_PORT_PCRB4_INVE (*((volatile unsigned int*)(0x42A78A24UL))) +#define bM4_PORT_PCRB4_INTE (*((volatile unsigned int*)(0x42A78A30UL))) +#define bM4_PORT_PCRB4_LTE (*((volatile unsigned int*)(0x42A78A38UL))) +#define bM4_PORT_PCRB4_DDIS (*((volatile unsigned int*)(0x42A78A3CUL))) +#define bM4_PORT_PFSRB4_FSEL0 (*((volatile unsigned int*)(0x42A78A40UL))) +#define bM4_PORT_PFSRB4_FSEL1 (*((volatile unsigned int*)(0x42A78A44UL))) +#define bM4_PORT_PFSRB4_FSEL2 (*((volatile unsigned int*)(0x42A78A48UL))) +#define bM4_PORT_PFSRB4_FSEL3 (*((volatile unsigned int*)(0x42A78A4CUL))) +#define bM4_PORT_PFSRB4_FSEL4 (*((volatile unsigned int*)(0x42A78A50UL))) +#define bM4_PORT_PFSRB4_FSEL5 (*((volatile unsigned int*)(0x42A78A54UL))) +#define bM4_PORT_PFSRB4_BFE (*((volatile unsigned int*)(0x42A78A60UL))) +#define bM4_PORT_PCRB5_POUT (*((volatile unsigned int*)(0x42A78A80UL))) +#define bM4_PORT_PCRB5_POUTE (*((volatile unsigned int*)(0x42A78A84UL))) +#define bM4_PORT_PCRB5_NOD (*((volatile unsigned int*)(0x42A78A88UL))) +#define bM4_PORT_PCRB5_DRV0 (*((volatile unsigned int*)(0x42A78A90UL))) +#define bM4_PORT_PCRB5_DRV1 (*((volatile unsigned int*)(0x42A78A94UL))) +#define bM4_PORT_PCRB5_PUU (*((volatile unsigned int*)(0x42A78A98UL))) +#define bM4_PORT_PCRB5_PIN (*((volatile unsigned int*)(0x42A78AA0UL))) +#define bM4_PORT_PCRB5_INVE (*((volatile unsigned int*)(0x42A78AA4UL))) +#define bM4_PORT_PCRB5_INTE (*((volatile unsigned int*)(0x42A78AB0UL))) +#define bM4_PORT_PCRB5_LTE (*((volatile unsigned int*)(0x42A78AB8UL))) +#define bM4_PORT_PCRB5_DDIS (*((volatile unsigned int*)(0x42A78ABCUL))) +#define bM4_PORT_PFSRB5_FSEL0 (*((volatile unsigned int*)(0x42A78AC0UL))) +#define bM4_PORT_PFSRB5_FSEL1 (*((volatile unsigned int*)(0x42A78AC4UL))) +#define bM4_PORT_PFSRB5_FSEL2 (*((volatile unsigned int*)(0x42A78AC8UL))) +#define bM4_PORT_PFSRB5_FSEL3 (*((volatile unsigned int*)(0x42A78ACCUL))) +#define bM4_PORT_PFSRB5_FSEL4 (*((volatile unsigned int*)(0x42A78AD0UL))) +#define bM4_PORT_PFSRB5_FSEL5 (*((volatile unsigned int*)(0x42A78AD4UL))) +#define bM4_PORT_PFSRB5_BFE (*((volatile unsigned int*)(0x42A78AE0UL))) +#define bM4_PORT_PCRB6_POUT (*((volatile unsigned int*)(0x42A78B00UL))) +#define bM4_PORT_PCRB6_POUTE (*((volatile unsigned int*)(0x42A78B04UL))) +#define bM4_PORT_PCRB6_NOD (*((volatile unsigned int*)(0x42A78B08UL))) +#define bM4_PORT_PCRB6_DRV0 (*((volatile unsigned int*)(0x42A78B10UL))) +#define bM4_PORT_PCRB6_DRV1 (*((volatile unsigned int*)(0x42A78B14UL))) +#define bM4_PORT_PCRB6_PUU (*((volatile unsigned int*)(0x42A78B18UL))) +#define bM4_PORT_PCRB6_PIN (*((volatile unsigned int*)(0x42A78B20UL))) +#define bM4_PORT_PCRB6_INVE (*((volatile unsigned int*)(0x42A78B24UL))) +#define bM4_PORT_PCRB6_INTE (*((volatile unsigned int*)(0x42A78B30UL))) +#define bM4_PORT_PCRB6_LTE (*((volatile unsigned int*)(0x42A78B38UL))) +#define bM4_PORT_PCRB6_DDIS (*((volatile unsigned int*)(0x42A78B3CUL))) +#define bM4_PORT_PFSRB6_FSEL0 (*((volatile unsigned int*)(0x42A78B40UL))) +#define bM4_PORT_PFSRB6_FSEL1 (*((volatile unsigned int*)(0x42A78B44UL))) +#define bM4_PORT_PFSRB6_FSEL2 (*((volatile unsigned int*)(0x42A78B48UL))) +#define bM4_PORT_PFSRB6_FSEL3 (*((volatile unsigned int*)(0x42A78B4CUL))) +#define bM4_PORT_PFSRB6_FSEL4 (*((volatile unsigned int*)(0x42A78B50UL))) +#define bM4_PORT_PFSRB6_FSEL5 (*((volatile unsigned int*)(0x42A78B54UL))) +#define bM4_PORT_PFSRB6_BFE (*((volatile unsigned int*)(0x42A78B60UL))) +#define bM4_PORT_PCRB7_POUT (*((volatile unsigned int*)(0x42A78B80UL))) +#define bM4_PORT_PCRB7_POUTE (*((volatile unsigned int*)(0x42A78B84UL))) +#define bM4_PORT_PCRB7_NOD (*((volatile unsigned int*)(0x42A78B88UL))) +#define bM4_PORT_PCRB7_DRV0 (*((volatile unsigned int*)(0x42A78B90UL))) +#define bM4_PORT_PCRB7_DRV1 (*((volatile unsigned int*)(0x42A78B94UL))) +#define bM4_PORT_PCRB7_PUU (*((volatile unsigned int*)(0x42A78B98UL))) +#define bM4_PORT_PCRB7_PIN (*((volatile unsigned int*)(0x42A78BA0UL))) +#define bM4_PORT_PCRB7_INVE (*((volatile unsigned int*)(0x42A78BA4UL))) +#define bM4_PORT_PCRB7_INTE (*((volatile unsigned int*)(0x42A78BB0UL))) +#define bM4_PORT_PCRB7_LTE (*((volatile unsigned int*)(0x42A78BB8UL))) +#define bM4_PORT_PCRB7_DDIS (*((volatile unsigned int*)(0x42A78BBCUL))) +#define bM4_PORT_PFSRB7_FSEL0 (*((volatile unsigned int*)(0x42A78BC0UL))) +#define bM4_PORT_PFSRB7_FSEL1 (*((volatile unsigned int*)(0x42A78BC4UL))) +#define bM4_PORT_PFSRB7_FSEL2 (*((volatile unsigned int*)(0x42A78BC8UL))) +#define bM4_PORT_PFSRB7_FSEL3 (*((volatile unsigned int*)(0x42A78BCCUL))) +#define bM4_PORT_PFSRB7_FSEL4 (*((volatile unsigned int*)(0x42A78BD0UL))) +#define bM4_PORT_PFSRB7_FSEL5 (*((volatile unsigned int*)(0x42A78BD4UL))) +#define bM4_PORT_PFSRB7_BFE (*((volatile unsigned int*)(0x42A78BE0UL))) +#define bM4_PORT_PCRB8_POUT (*((volatile unsigned int*)(0x42A78C00UL))) +#define bM4_PORT_PCRB8_POUTE (*((volatile unsigned int*)(0x42A78C04UL))) +#define bM4_PORT_PCRB8_NOD (*((volatile unsigned int*)(0x42A78C08UL))) +#define bM4_PORT_PCRB8_DRV0 (*((volatile unsigned int*)(0x42A78C10UL))) +#define bM4_PORT_PCRB8_DRV1 (*((volatile unsigned int*)(0x42A78C14UL))) +#define bM4_PORT_PCRB8_PUU (*((volatile unsigned int*)(0x42A78C18UL))) +#define bM4_PORT_PCRB8_PIN (*((volatile unsigned int*)(0x42A78C20UL))) +#define bM4_PORT_PCRB8_INVE (*((volatile unsigned int*)(0x42A78C24UL))) +#define bM4_PORT_PCRB8_INTE (*((volatile unsigned int*)(0x42A78C30UL))) +#define bM4_PORT_PCRB8_LTE (*((volatile unsigned int*)(0x42A78C38UL))) +#define bM4_PORT_PCRB8_DDIS (*((volatile unsigned int*)(0x42A78C3CUL))) +#define bM4_PORT_PFSRB8_FSEL0 (*((volatile unsigned int*)(0x42A78C40UL))) +#define bM4_PORT_PFSRB8_FSEL1 (*((volatile unsigned int*)(0x42A78C44UL))) +#define bM4_PORT_PFSRB8_FSEL2 (*((volatile unsigned int*)(0x42A78C48UL))) +#define bM4_PORT_PFSRB8_FSEL3 (*((volatile unsigned int*)(0x42A78C4CUL))) +#define bM4_PORT_PFSRB8_FSEL4 (*((volatile unsigned int*)(0x42A78C50UL))) +#define bM4_PORT_PFSRB8_FSEL5 (*((volatile unsigned int*)(0x42A78C54UL))) +#define bM4_PORT_PFSRB8_BFE (*((volatile unsigned int*)(0x42A78C60UL))) +#define bM4_PORT_PCRB9_POUT (*((volatile unsigned int*)(0x42A78C80UL))) +#define bM4_PORT_PCRB9_POUTE (*((volatile unsigned int*)(0x42A78C84UL))) +#define bM4_PORT_PCRB9_NOD (*((volatile unsigned int*)(0x42A78C88UL))) +#define bM4_PORT_PCRB9_DRV0 (*((volatile unsigned int*)(0x42A78C90UL))) +#define bM4_PORT_PCRB9_DRV1 (*((volatile unsigned int*)(0x42A78C94UL))) +#define bM4_PORT_PCRB9_PUU (*((volatile unsigned int*)(0x42A78C98UL))) +#define bM4_PORT_PCRB9_PIN (*((volatile unsigned int*)(0x42A78CA0UL))) +#define bM4_PORT_PCRB9_INVE (*((volatile unsigned int*)(0x42A78CA4UL))) +#define bM4_PORT_PCRB9_INTE (*((volatile unsigned int*)(0x42A78CB0UL))) +#define bM4_PORT_PCRB9_LTE (*((volatile unsigned int*)(0x42A78CB8UL))) +#define bM4_PORT_PCRB9_DDIS (*((volatile unsigned int*)(0x42A78CBCUL))) +#define bM4_PORT_PFSRB9_FSEL0 (*((volatile unsigned int*)(0x42A78CC0UL))) +#define bM4_PORT_PFSRB9_FSEL1 (*((volatile unsigned int*)(0x42A78CC4UL))) +#define bM4_PORT_PFSRB9_FSEL2 (*((volatile unsigned int*)(0x42A78CC8UL))) +#define bM4_PORT_PFSRB9_FSEL3 (*((volatile unsigned int*)(0x42A78CCCUL))) +#define bM4_PORT_PFSRB9_FSEL4 (*((volatile unsigned int*)(0x42A78CD0UL))) +#define bM4_PORT_PFSRB9_FSEL5 (*((volatile unsigned int*)(0x42A78CD4UL))) +#define bM4_PORT_PFSRB9_BFE (*((volatile unsigned int*)(0x42A78CE0UL))) +#define bM4_PORT_PCRB10_POUT (*((volatile unsigned int*)(0x42A78D00UL))) +#define bM4_PORT_PCRB10_POUTE (*((volatile unsigned int*)(0x42A78D04UL))) +#define bM4_PORT_PCRB10_NOD (*((volatile unsigned int*)(0x42A78D08UL))) +#define bM4_PORT_PCRB10_DRV0 (*((volatile unsigned int*)(0x42A78D10UL))) +#define bM4_PORT_PCRB10_DRV1 (*((volatile unsigned int*)(0x42A78D14UL))) +#define bM4_PORT_PCRB10_PUU (*((volatile unsigned int*)(0x42A78D18UL))) +#define bM4_PORT_PCRB10_PIN (*((volatile unsigned int*)(0x42A78D20UL))) +#define bM4_PORT_PCRB10_INVE (*((volatile unsigned int*)(0x42A78D24UL))) +#define bM4_PORT_PCRB10_INTE (*((volatile unsigned int*)(0x42A78D30UL))) +#define bM4_PORT_PCRB10_LTE (*((volatile unsigned int*)(0x42A78D38UL))) +#define bM4_PORT_PCRB10_DDIS (*((volatile unsigned int*)(0x42A78D3CUL))) +#define bM4_PORT_PFSRB10_FSEL0 (*((volatile unsigned int*)(0x42A78D40UL))) +#define bM4_PORT_PFSRB10_FSEL1 (*((volatile unsigned int*)(0x42A78D44UL))) +#define bM4_PORT_PFSRB10_FSEL2 (*((volatile unsigned int*)(0x42A78D48UL))) +#define bM4_PORT_PFSRB10_FSEL3 (*((volatile unsigned int*)(0x42A78D4CUL))) +#define bM4_PORT_PFSRB10_FSEL4 (*((volatile unsigned int*)(0x42A78D50UL))) +#define bM4_PORT_PFSRB10_FSEL5 (*((volatile unsigned int*)(0x42A78D54UL))) +#define bM4_PORT_PFSRB10_BFE (*((volatile unsigned int*)(0x42A78D60UL))) +#define bM4_PORT_PCRB11_POUT (*((volatile unsigned int*)(0x42A78D80UL))) +#define bM4_PORT_PCRB11_POUTE (*((volatile unsigned int*)(0x42A78D84UL))) +#define bM4_PORT_PCRB11_NOD (*((volatile unsigned int*)(0x42A78D88UL))) +#define bM4_PORT_PCRB11_DRV0 (*((volatile unsigned int*)(0x42A78D90UL))) +#define bM4_PORT_PCRB11_DRV1 (*((volatile unsigned int*)(0x42A78D94UL))) +#define bM4_PORT_PCRB11_PUU (*((volatile unsigned int*)(0x42A78D98UL))) +#define bM4_PORT_PCRB11_PIN (*((volatile unsigned int*)(0x42A78DA0UL))) +#define bM4_PORT_PCRB11_INVE (*((volatile unsigned int*)(0x42A78DA4UL))) +#define bM4_PORT_PCRB11_INTE (*((volatile unsigned int*)(0x42A78DB0UL))) +#define bM4_PORT_PCRB11_LTE (*((volatile unsigned int*)(0x42A78DB8UL))) +#define bM4_PORT_PCRB11_DDIS (*((volatile unsigned int*)(0x42A78DBCUL))) +#define bM4_PORT_PFSRB11_FSEL0 (*((volatile unsigned int*)(0x42A78DC0UL))) +#define bM4_PORT_PFSRB11_FSEL1 (*((volatile unsigned int*)(0x42A78DC4UL))) +#define bM4_PORT_PFSRB11_FSEL2 (*((volatile unsigned int*)(0x42A78DC8UL))) +#define bM4_PORT_PFSRB11_FSEL3 (*((volatile unsigned int*)(0x42A78DCCUL))) +#define bM4_PORT_PFSRB11_FSEL4 (*((volatile unsigned int*)(0x42A78DD0UL))) +#define bM4_PORT_PFSRB11_FSEL5 (*((volatile unsigned int*)(0x42A78DD4UL))) +#define bM4_PORT_PFSRB11_BFE (*((volatile unsigned int*)(0x42A78DE0UL))) +#define bM4_PORT_PCRB12_POUT (*((volatile unsigned int*)(0x42A78E00UL))) +#define bM4_PORT_PCRB12_POUTE (*((volatile unsigned int*)(0x42A78E04UL))) +#define bM4_PORT_PCRB12_NOD (*((volatile unsigned int*)(0x42A78E08UL))) +#define bM4_PORT_PCRB12_DRV0 (*((volatile unsigned int*)(0x42A78E10UL))) +#define bM4_PORT_PCRB12_DRV1 (*((volatile unsigned int*)(0x42A78E14UL))) +#define bM4_PORT_PCRB12_PUU (*((volatile unsigned int*)(0x42A78E18UL))) +#define bM4_PORT_PCRB12_PIN (*((volatile unsigned int*)(0x42A78E20UL))) +#define bM4_PORT_PCRB12_INVE (*((volatile unsigned int*)(0x42A78E24UL))) +#define bM4_PORT_PCRB12_INTE (*((volatile unsigned int*)(0x42A78E30UL))) +#define bM4_PORT_PCRB12_LTE (*((volatile unsigned int*)(0x42A78E38UL))) +#define bM4_PORT_PCRB12_DDIS (*((volatile unsigned int*)(0x42A78E3CUL))) +#define bM4_PORT_PFSRB12_FSEL0 (*((volatile unsigned int*)(0x42A78E40UL))) +#define bM4_PORT_PFSRB12_FSEL1 (*((volatile unsigned int*)(0x42A78E44UL))) +#define bM4_PORT_PFSRB12_FSEL2 (*((volatile unsigned int*)(0x42A78E48UL))) +#define bM4_PORT_PFSRB12_FSEL3 (*((volatile unsigned int*)(0x42A78E4CUL))) +#define bM4_PORT_PFSRB12_FSEL4 (*((volatile unsigned int*)(0x42A78E50UL))) +#define bM4_PORT_PFSRB12_FSEL5 (*((volatile unsigned int*)(0x42A78E54UL))) +#define bM4_PORT_PFSRB12_BFE (*((volatile unsigned int*)(0x42A78E60UL))) +#define bM4_PORT_PCRB13_POUT (*((volatile unsigned int*)(0x42A78E80UL))) +#define bM4_PORT_PCRB13_POUTE (*((volatile unsigned int*)(0x42A78E84UL))) +#define bM4_PORT_PCRB13_NOD (*((volatile unsigned int*)(0x42A78E88UL))) +#define bM4_PORT_PCRB13_DRV0 (*((volatile unsigned int*)(0x42A78E90UL))) +#define bM4_PORT_PCRB13_DRV1 (*((volatile unsigned int*)(0x42A78E94UL))) +#define bM4_PORT_PCRB13_PUU (*((volatile unsigned int*)(0x42A78E98UL))) +#define bM4_PORT_PCRB13_PIN (*((volatile unsigned int*)(0x42A78EA0UL))) +#define bM4_PORT_PCRB13_INVE (*((volatile unsigned int*)(0x42A78EA4UL))) +#define bM4_PORT_PCRB13_INTE (*((volatile unsigned int*)(0x42A78EB0UL))) +#define bM4_PORT_PCRB13_LTE (*((volatile unsigned int*)(0x42A78EB8UL))) +#define bM4_PORT_PCRB13_DDIS (*((volatile unsigned int*)(0x42A78EBCUL))) +#define bM4_PORT_PFSRB13_FSEL0 (*((volatile unsigned int*)(0x42A78EC0UL))) +#define bM4_PORT_PFSRB13_FSEL1 (*((volatile unsigned int*)(0x42A78EC4UL))) +#define bM4_PORT_PFSRB13_FSEL2 (*((volatile unsigned int*)(0x42A78EC8UL))) +#define bM4_PORT_PFSRB13_FSEL3 (*((volatile unsigned int*)(0x42A78ECCUL))) +#define bM4_PORT_PFSRB13_FSEL4 (*((volatile unsigned int*)(0x42A78ED0UL))) +#define bM4_PORT_PFSRB13_FSEL5 (*((volatile unsigned int*)(0x42A78ED4UL))) +#define bM4_PORT_PFSRB13_BFE (*((volatile unsigned int*)(0x42A78EE0UL))) +#define bM4_PORT_PCRB14_POUT (*((volatile unsigned int*)(0x42A78F00UL))) +#define bM4_PORT_PCRB14_POUTE (*((volatile unsigned int*)(0x42A78F04UL))) +#define bM4_PORT_PCRB14_NOD (*((volatile unsigned int*)(0x42A78F08UL))) +#define bM4_PORT_PCRB14_DRV0 (*((volatile unsigned int*)(0x42A78F10UL))) +#define bM4_PORT_PCRB14_DRV1 (*((volatile unsigned int*)(0x42A78F14UL))) +#define bM4_PORT_PCRB14_PUU (*((volatile unsigned int*)(0x42A78F18UL))) +#define bM4_PORT_PCRB14_PIN (*((volatile unsigned int*)(0x42A78F20UL))) +#define bM4_PORT_PCRB14_INVE (*((volatile unsigned int*)(0x42A78F24UL))) +#define bM4_PORT_PCRB14_INTE (*((volatile unsigned int*)(0x42A78F30UL))) +#define bM4_PORT_PCRB14_LTE (*((volatile unsigned int*)(0x42A78F38UL))) +#define bM4_PORT_PCRB14_DDIS (*((volatile unsigned int*)(0x42A78F3CUL))) +#define bM4_PORT_PFSRB14_FSEL0 (*((volatile unsigned int*)(0x42A78F40UL))) +#define bM4_PORT_PFSRB14_FSEL1 (*((volatile unsigned int*)(0x42A78F44UL))) +#define bM4_PORT_PFSRB14_FSEL2 (*((volatile unsigned int*)(0x42A78F48UL))) +#define bM4_PORT_PFSRB14_FSEL3 (*((volatile unsigned int*)(0x42A78F4CUL))) +#define bM4_PORT_PFSRB14_FSEL4 (*((volatile unsigned int*)(0x42A78F50UL))) +#define bM4_PORT_PFSRB14_FSEL5 (*((volatile unsigned int*)(0x42A78F54UL))) +#define bM4_PORT_PFSRB14_BFE (*((volatile unsigned int*)(0x42A78F60UL))) +#define bM4_PORT_PCRB15_POUT (*((volatile unsigned int*)(0x42A78F80UL))) +#define bM4_PORT_PCRB15_POUTE (*((volatile unsigned int*)(0x42A78F84UL))) +#define bM4_PORT_PCRB15_NOD (*((volatile unsigned int*)(0x42A78F88UL))) +#define bM4_PORT_PCRB15_DRV0 (*((volatile unsigned int*)(0x42A78F90UL))) +#define bM4_PORT_PCRB15_DRV1 (*((volatile unsigned int*)(0x42A78F94UL))) +#define bM4_PORT_PCRB15_PUU (*((volatile unsigned int*)(0x42A78F98UL))) +#define bM4_PORT_PCRB15_PIN (*((volatile unsigned int*)(0x42A78FA0UL))) +#define bM4_PORT_PCRB15_INVE (*((volatile unsigned int*)(0x42A78FA4UL))) +#define bM4_PORT_PCRB15_INTE (*((volatile unsigned int*)(0x42A78FB0UL))) +#define bM4_PORT_PCRB15_LTE (*((volatile unsigned int*)(0x42A78FB8UL))) +#define bM4_PORT_PCRB15_DDIS (*((volatile unsigned int*)(0x42A78FBCUL))) +#define bM4_PORT_PFSRB15_FSEL0 (*((volatile unsigned int*)(0x42A78FC0UL))) +#define bM4_PORT_PFSRB15_FSEL1 (*((volatile unsigned int*)(0x42A78FC4UL))) +#define bM4_PORT_PFSRB15_FSEL2 (*((volatile unsigned int*)(0x42A78FC8UL))) +#define bM4_PORT_PFSRB15_FSEL3 (*((volatile unsigned int*)(0x42A78FCCUL))) +#define bM4_PORT_PFSRB15_FSEL4 (*((volatile unsigned int*)(0x42A78FD0UL))) +#define bM4_PORT_PFSRB15_FSEL5 (*((volatile unsigned int*)(0x42A78FD4UL))) +#define bM4_PORT_PFSRB15_BFE (*((volatile unsigned int*)(0x42A78FE0UL))) +#define bM4_PORT_PCRC0_POUT (*((volatile unsigned int*)(0x42A79000UL))) +#define bM4_PORT_PCRC0_POUTE (*((volatile unsigned int*)(0x42A79004UL))) +#define bM4_PORT_PCRC0_NOD (*((volatile unsigned int*)(0x42A79008UL))) +#define bM4_PORT_PCRC0_DRV0 (*((volatile unsigned int*)(0x42A79010UL))) +#define bM4_PORT_PCRC0_DRV1 (*((volatile unsigned int*)(0x42A79014UL))) +#define bM4_PORT_PCRC0_PUU (*((volatile unsigned int*)(0x42A79018UL))) +#define bM4_PORT_PCRC0_PIN (*((volatile unsigned int*)(0x42A79020UL))) +#define bM4_PORT_PCRC0_INVE (*((volatile unsigned int*)(0x42A79024UL))) +#define bM4_PORT_PCRC0_INTE (*((volatile unsigned int*)(0x42A79030UL))) +#define bM4_PORT_PCRC0_LTE (*((volatile unsigned int*)(0x42A79038UL))) +#define bM4_PORT_PCRC0_DDIS (*((volatile unsigned int*)(0x42A7903CUL))) +#define bM4_PORT_PFSRC0_FSEL0 (*((volatile unsigned int*)(0x42A79040UL))) +#define bM4_PORT_PFSRC0_FSEL1 (*((volatile unsigned int*)(0x42A79044UL))) +#define bM4_PORT_PFSRC0_FSEL2 (*((volatile unsigned int*)(0x42A79048UL))) +#define bM4_PORT_PFSRC0_FSEL3 (*((volatile unsigned int*)(0x42A7904CUL))) +#define bM4_PORT_PFSRC0_FSEL4 (*((volatile unsigned int*)(0x42A79050UL))) +#define bM4_PORT_PFSRC0_FSEL5 (*((volatile unsigned int*)(0x42A79054UL))) +#define bM4_PORT_PFSRC0_BFE (*((volatile unsigned int*)(0x42A79060UL))) +#define bM4_PORT_PCRC1_POUT (*((volatile unsigned int*)(0x42A79080UL))) +#define bM4_PORT_PCRC1_POUTE (*((volatile unsigned int*)(0x42A79084UL))) +#define bM4_PORT_PCRC1_NOD (*((volatile unsigned int*)(0x42A79088UL))) +#define bM4_PORT_PCRC1_DRV0 (*((volatile unsigned int*)(0x42A79090UL))) +#define bM4_PORT_PCRC1_DRV1 (*((volatile unsigned int*)(0x42A79094UL))) +#define bM4_PORT_PCRC1_PUU (*((volatile unsigned int*)(0x42A79098UL))) +#define bM4_PORT_PCRC1_PIN (*((volatile unsigned int*)(0x42A790A0UL))) +#define bM4_PORT_PCRC1_INVE (*((volatile unsigned int*)(0x42A790A4UL))) +#define bM4_PORT_PCRC1_INTE (*((volatile unsigned int*)(0x42A790B0UL))) +#define bM4_PORT_PCRC1_LTE (*((volatile unsigned int*)(0x42A790B8UL))) +#define bM4_PORT_PCRC1_DDIS (*((volatile unsigned int*)(0x42A790BCUL))) +#define bM4_PORT_PFSRC1_FSEL0 (*((volatile unsigned int*)(0x42A790C0UL))) +#define bM4_PORT_PFSRC1_FSEL1 (*((volatile unsigned int*)(0x42A790C4UL))) +#define bM4_PORT_PFSRC1_FSEL2 (*((volatile unsigned int*)(0x42A790C8UL))) +#define bM4_PORT_PFSRC1_FSEL3 (*((volatile unsigned int*)(0x42A790CCUL))) +#define bM4_PORT_PFSRC1_FSEL4 (*((volatile unsigned int*)(0x42A790D0UL))) +#define bM4_PORT_PFSRC1_FSEL5 (*((volatile unsigned int*)(0x42A790D4UL))) +#define bM4_PORT_PFSRC1_BFE (*((volatile unsigned int*)(0x42A790E0UL))) +#define bM4_PORT_PCRC2_POUT (*((volatile unsigned int*)(0x42A79100UL))) +#define bM4_PORT_PCRC2_POUTE (*((volatile unsigned int*)(0x42A79104UL))) +#define bM4_PORT_PCRC2_NOD (*((volatile unsigned int*)(0x42A79108UL))) +#define bM4_PORT_PCRC2_DRV0 (*((volatile unsigned int*)(0x42A79110UL))) +#define bM4_PORT_PCRC2_DRV1 (*((volatile unsigned int*)(0x42A79114UL))) +#define bM4_PORT_PCRC2_PUU (*((volatile unsigned int*)(0x42A79118UL))) +#define bM4_PORT_PCRC2_PIN (*((volatile unsigned int*)(0x42A79120UL))) +#define bM4_PORT_PCRC2_INVE (*((volatile unsigned int*)(0x42A79124UL))) +#define bM4_PORT_PCRC2_INTE (*((volatile unsigned int*)(0x42A79130UL))) +#define bM4_PORT_PCRC2_LTE (*((volatile unsigned int*)(0x42A79138UL))) +#define bM4_PORT_PCRC2_DDIS (*((volatile unsigned int*)(0x42A7913CUL))) +#define bM4_PORT_PFSRC2_FSEL0 (*((volatile unsigned int*)(0x42A79140UL))) +#define bM4_PORT_PFSRC2_FSEL1 (*((volatile unsigned int*)(0x42A79144UL))) +#define bM4_PORT_PFSRC2_FSEL2 (*((volatile unsigned int*)(0x42A79148UL))) +#define bM4_PORT_PFSRC2_FSEL3 (*((volatile unsigned int*)(0x42A7914CUL))) +#define bM4_PORT_PFSRC2_FSEL4 (*((volatile unsigned int*)(0x42A79150UL))) +#define bM4_PORT_PFSRC2_FSEL5 (*((volatile unsigned int*)(0x42A79154UL))) +#define bM4_PORT_PFSRC2_BFE (*((volatile unsigned int*)(0x42A79160UL))) +#define bM4_PORT_PCRC3_POUT (*((volatile unsigned int*)(0x42A79180UL))) +#define bM4_PORT_PCRC3_POUTE (*((volatile unsigned int*)(0x42A79184UL))) +#define bM4_PORT_PCRC3_NOD (*((volatile unsigned int*)(0x42A79188UL))) +#define bM4_PORT_PCRC3_DRV0 (*((volatile unsigned int*)(0x42A79190UL))) +#define bM4_PORT_PCRC3_DRV1 (*((volatile unsigned int*)(0x42A79194UL))) +#define bM4_PORT_PCRC3_PUU (*((volatile unsigned int*)(0x42A79198UL))) +#define bM4_PORT_PCRC3_PIN (*((volatile unsigned int*)(0x42A791A0UL))) +#define bM4_PORT_PCRC3_INVE (*((volatile unsigned int*)(0x42A791A4UL))) +#define bM4_PORT_PCRC3_INTE (*((volatile unsigned int*)(0x42A791B0UL))) +#define bM4_PORT_PCRC3_LTE (*((volatile unsigned int*)(0x42A791B8UL))) +#define bM4_PORT_PCRC3_DDIS (*((volatile unsigned int*)(0x42A791BCUL))) +#define bM4_PORT_PFSRC3_FSEL0 (*((volatile unsigned int*)(0x42A791C0UL))) +#define bM4_PORT_PFSRC3_FSEL1 (*((volatile unsigned int*)(0x42A791C4UL))) +#define bM4_PORT_PFSRC3_FSEL2 (*((volatile unsigned int*)(0x42A791C8UL))) +#define bM4_PORT_PFSRC3_FSEL3 (*((volatile unsigned int*)(0x42A791CCUL))) +#define bM4_PORT_PFSRC3_FSEL4 (*((volatile unsigned int*)(0x42A791D0UL))) +#define bM4_PORT_PFSRC3_FSEL5 (*((volatile unsigned int*)(0x42A791D4UL))) +#define bM4_PORT_PFSRC3_BFE (*((volatile unsigned int*)(0x42A791E0UL))) +#define bM4_PORT_PCRC4_POUT (*((volatile unsigned int*)(0x42A79200UL))) +#define bM4_PORT_PCRC4_POUTE (*((volatile unsigned int*)(0x42A79204UL))) +#define bM4_PORT_PCRC4_NOD (*((volatile unsigned int*)(0x42A79208UL))) +#define bM4_PORT_PCRC4_DRV0 (*((volatile unsigned int*)(0x42A79210UL))) +#define bM4_PORT_PCRC4_DRV1 (*((volatile unsigned int*)(0x42A79214UL))) +#define bM4_PORT_PCRC4_PUU (*((volatile unsigned int*)(0x42A79218UL))) +#define bM4_PORT_PCRC4_PIN (*((volatile unsigned int*)(0x42A79220UL))) +#define bM4_PORT_PCRC4_INVE (*((volatile unsigned int*)(0x42A79224UL))) +#define bM4_PORT_PCRC4_INTE (*((volatile unsigned int*)(0x42A79230UL))) +#define bM4_PORT_PCRC4_LTE (*((volatile unsigned int*)(0x42A79238UL))) +#define bM4_PORT_PCRC4_DDIS (*((volatile unsigned int*)(0x42A7923CUL))) +#define bM4_PORT_PFSRC4_FSEL0 (*((volatile unsigned int*)(0x42A79240UL))) +#define bM4_PORT_PFSRC4_FSEL1 (*((volatile unsigned int*)(0x42A79244UL))) +#define bM4_PORT_PFSRC4_FSEL2 (*((volatile unsigned int*)(0x42A79248UL))) +#define bM4_PORT_PFSRC4_FSEL3 (*((volatile unsigned int*)(0x42A7924CUL))) +#define bM4_PORT_PFSRC4_FSEL4 (*((volatile unsigned int*)(0x42A79250UL))) +#define bM4_PORT_PFSRC4_FSEL5 (*((volatile unsigned int*)(0x42A79254UL))) +#define bM4_PORT_PFSRC4_BFE (*((volatile unsigned int*)(0x42A79260UL))) +#define bM4_PORT_PCRC5_POUT (*((volatile unsigned int*)(0x42A79280UL))) +#define bM4_PORT_PCRC5_POUTE (*((volatile unsigned int*)(0x42A79284UL))) +#define bM4_PORT_PCRC5_NOD (*((volatile unsigned int*)(0x42A79288UL))) +#define bM4_PORT_PCRC5_DRV0 (*((volatile unsigned int*)(0x42A79290UL))) +#define bM4_PORT_PCRC5_DRV1 (*((volatile unsigned int*)(0x42A79294UL))) +#define bM4_PORT_PCRC5_PUU (*((volatile unsigned int*)(0x42A79298UL))) +#define bM4_PORT_PCRC5_PIN (*((volatile unsigned int*)(0x42A792A0UL))) +#define bM4_PORT_PCRC5_INVE (*((volatile unsigned int*)(0x42A792A4UL))) +#define bM4_PORT_PCRC5_INTE (*((volatile unsigned int*)(0x42A792B0UL))) +#define bM4_PORT_PCRC5_LTE (*((volatile unsigned int*)(0x42A792B8UL))) +#define bM4_PORT_PCRC5_DDIS (*((volatile unsigned int*)(0x42A792BCUL))) +#define bM4_PORT_PFSRC5_FSEL0 (*((volatile unsigned int*)(0x42A792C0UL))) +#define bM4_PORT_PFSRC5_FSEL1 (*((volatile unsigned int*)(0x42A792C4UL))) +#define bM4_PORT_PFSRC5_FSEL2 (*((volatile unsigned int*)(0x42A792C8UL))) +#define bM4_PORT_PFSRC5_FSEL3 (*((volatile unsigned int*)(0x42A792CCUL))) +#define bM4_PORT_PFSRC5_FSEL4 (*((volatile unsigned int*)(0x42A792D0UL))) +#define bM4_PORT_PFSRC5_FSEL5 (*((volatile unsigned int*)(0x42A792D4UL))) +#define bM4_PORT_PFSRC5_BFE (*((volatile unsigned int*)(0x42A792E0UL))) +#define bM4_PORT_PCRC6_POUT (*((volatile unsigned int*)(0x42A79300UL))) +#define bM4_PORT_PCRC6_POUTE (*((volatile unsigned int*)(0x42A79304UL))) +#define bM4_PORT_PCRC6_NOD (*((volatile unsigned int*)(0x42A79308UL))) +#define bM4_PORT_PCRC6_DRV0 (*((volatile unsigned int*)(0x42A79310UL))) +#define bM4_PORT_PCRC6_DRV1 (*((volatile unsigned int*)(0x42A79314UL))) +#define bM4_PORT_PCRC6_PUU (*((volatile unsigned int*)(0x42A79318UL))) +#define bM4_PORT_PCRC6_PIN (*((volatile unsigned int*)(0x42A79320UL))) +#define bM4_PORT_PCRC6_INVE (*((volatile unsigned int*)(0x42A79324UL))) +#define bM4_PORT_PCRC6_INTE (*((volatile unsigned int*)(0x42A79330UL))) +#define bM4_PORT_PCRC6_LTE (*((volatile unsigned int*)(0x42A79338UL))) +#define bM4_PORT_PCRC6_DDIS (*((volatile unsigned int*)(0x42A7933CUL))) +#define bM4_PORT_PFSRC6_FSEL0 (*((volatile unsigned int*)(0x42A79340UL))) +#define bM4_PORT_PFSRC6_FSEL1 (*((volatile unsigned int*)(0x42A79344UL))) +#define bM4_PORT_PFSRC6_FSEL2 (*((volatile unsigned int*)(0x42A79348UL))) +#define bM4_PORT_PFSRC6_FSEL3 (*((volatile unsigned int*)(0x42A7934CUL))) +#define bM4_PORT_PFSRC6_FSEL4 (*((volatile unsigned int*)(0x42A79350UL))) +#define bM4_PORT_PFSRC6_FSEL5 (*((volatile unsigned int*)(0x42A79354UL))) +#define bM4_PORT_PFSRC6_BFE (*((volatile unsigned int*)(0x42A79360UL))) +#define bM4_PORT_PCRC7_POUT (*((volatile unsigned int*)(0x42A79380UL))) +#define bM4_PORT_PCRC7_POUTE (*((volatile unsigned int*)(0x42A79384UL))) +#define bM4_PORT_PCRC7_NOD (*((volatile unsigned int*)(0x42A79388UL))) +#define bM4_PORT_PCRC7_DRV0 (*((volatile unsigned int*)(0x42A79390UL))) +#define bM4_PORT_PCRC7_DRV1 (*((volatile unsigned int*)(0x42A79394UL))) +#define bM4_PORT_PCRC7_PUU (*((volatile unsigned int*)(0x42A79398UL))) +#define bM4_PORT_PCRC7_PIN (*((volatile unsigned int*)(0x42A793A0UL))) +#define bM4_PORT_PCRC7_INVE (*((volatile unsigned int*)(0x42A793A4UL))) +#define bM4_PORT_PCRC7_INTE (*((volatile unsigned int*)(0x42A793B0UL))) +#define bM4_PORT_PCRC7_LTE (*((volatile unsigned int*)(0x42A793B8UL))) +#define bM4_PORT_PCRC7_DDIS (*((volatile unsigned int*)(0x42A793BCUL))) +#define bM4_PORT_PFSRC7_FSEL0 (*((volatile unsigned int*)(0x42A793C0UL))) +#define bM4_PORT_PFSRC7_FSEL1 (*((volatile unsigned int*)(0x42A793C4UL))) +#define bM4_PORT_PFSRC7_FSEL2 (*((volatile unsigned int*)(0x42A793C8UL))) +#define bM4_PORT_PFSRC7_FSEL3 (*((volatile unsigned int*)(0x42A793CCUL))) +#define bM4_PORT_PFSRC7_FSEL4 (*((volatile unsigned int*)(0x42A793D0UL))) +#define bM4_PORT_PFSRC7_FSEL5 (*((volatile unsigned int*)(0x42A793D4UL))) +#define bM4_PORT_PFSRC7_BFE (*((volatile unsigned int*)(0x42A793E0UL))) +#define bM4_PORT_PCRC8_POUT (*((volatile unsigned int*)(0x42A79400UL))) +#define bM4_PORT_PCRC8_POUTE (*((volatile unsigned int*)(0x42A79404UL))) +#define bM4_PORT_PCRC8_NOD (*((volatile unsigned int*)(0x42A79408UL))) +#define bM4_PORT_PCRC8_DRV0 (*((volatile unsigned int*)(0x42A79410UL))) +#define bM4_PORT_PCRC8_DRV1 (*((volatile unsigned int*)(0x42A79414UL))) +#define bM4_PORT_PCRC8_PUU (*((volatile unsigned int*)(0x42A79418UL))) +#define bM4_PORT_PCRC8_PIN (*((volatile unsigned int*)(0x42A79420UL))) +#define bM4_PORT_PCRC8_INVE (*((volatile unsigned int*)(0x42A79424UL))) +#define bM4_PORT_PCRC8_INTE (*((volatile unsigned int*)(0x42A79430UL))) +#define bM4_PORT_PCRC8_LTE (*((volatile unsigned int*)(0x42A79438UL))) +#define bM4_PORT_PCRC8_DDIS (*((volatile unsigned int*)(0x42A7943CUL))) +#define bM4_PORT_PFSRC8_FSEL0 (*((volatile unsigned int*)(0x42A79440UL))) +#define bM4_PORT_PFSRC8_FSEL1 (*((volatile unsigned int*)(0x42A79444UL))) +#define bM4_PORT_PFSRC8_FSEL2 (*((volatile unsigned int*)(0x42A79448UL))) +#define bM4_PORT_PFSRC8_FSEL3 (*((volatile unsigned int*)(0x42A7944CUL))) +#define bM4_PORT_PFSRC8_FSEL4 (*((volatile unsigned int*)(0x42A79450UL))) +#define bM4_PORT_PFSRC8_FSEL5 (*((volatile unsigned int*)(0x42A79454UL))) +#define bM4_PORT_PFSRC8_BFE (*((volatile unsigned int*)(0x42A79460UL))) +#define bM4_PORT_PCRC9_POUT (*((volatile unsigned int*)(0x42A79480UL))) +#define bM4_PORT_PCRC9_POUTE (*((volatile unsigned int*)(0x42A79484UL))) +#define bM4_PORT_PCRC9_NOD (*((volatile unsigned int*)(0x42A79488UL))) +#define bM4_PORT_PCRC9_DRV0 (*((volatile unsigned int*)(0x42A79490UL))) +#define bM4_PORT_PCRC9_DRV1 (*((volatile unsigned int*)(0x42A79494UL))) +#define bM4_PORT_PCRC9_PUU (*((volatile unsigned int*)(0x42A79498UL))) +#define bM4_PORT_PCRC9_PIN (*((volatile unsigned int*)(0x42A794A0UL))) +#define bM4_PORT_PCRC9_INVE (*((volatile unsigned int*)(0x42A794A4UL))) +#define bM4_PORT_PCRC9_INTE (*((volatile unsigned int*)(0x42A794B0UL))) +#define bM4_PORT_PCRC9_LTE (*((volatile unsigned int*)(0x42A794B8UL))) +#define bM4_PORT_PCRC9_DDIS (*((volatile unsigned int*)(0x42A794BCUL))) +#define bM4_PORT_PFSRC9_FSEL0 (*((volatile unsigned int*)(0x42A794C0UL))) +#define bM4_PORT_PFSRC9_FSEL1 (*((volatile unsigned int*)(0x42A794C4UL))) +#define bM4_PORT_PFSRC9_FSEL2 (*((volatile unsigned int*)(0x42A794C8UL))) +#define bM4_PORT_PFSRC9_FSEL3 (*((volatile unsigned int*)(0x42A794CCUL))) +#define bM4_PORT_PFSRC9_FSEL4 (*((volatile unsigned int*)(0x42A794D0UL))) +#define bM4_PORT_PFSRC9_FSEL5 (*((volatile unsigned int*)(0x42A794D4UL))) +#define bM4_PORT_PFSRC9_BFE (*((volatile unsigned int*)(0x42A794E0UL))) +#define bM4_PORT_PCRC10_POUT (*((volatile unsigned int*)(0x42A79500UL))) +#define bM4_PORT_PCRC10_POUTE (*((volatile unsigned int*)(0x42A79504UL))) +#define bM4_PORT_PCRC10_NOD (*((volatile unsigned int*)(0x42A79508UL))) +#define bM4_PORT_PCRC10_DRV0 (*((volatile unsigned int*)(0x42A79510UL))) +#define bM4_PORT_PCRC10_DRV1 (*((volatile unsigned int*)(0x42A79514UL))) +#define bM4_PORT_PCRC10_PUU (*((volatile unsigned int*)(0x42A79518UL))) +#define bM4_PORT_PCRC10_PIN (*((volatile unsigned int*)(0x42A79520UL))) +#define bM4_PORT_PCRC10_INVE (*((volatile unsigned int*)(0x42A79524UL))) +#define bM4_PORT_PCRC10_INTE (*((volatile unsigned int*)(0x42A79530UL))) +#define bM4_PORT_PCRC10_LTE (*((volatile unsigned int*)(0x42A79538UL))) +#define bM4_PORT_PCRC10_DDIS (*((volatile unsigned int*)(0x42A7953CUL))) +#define bM4_PORT_PFSRC10_FSEL0 (*((volatile unsigned int*)(0x42A79540UL))) +#define bM4_PORT_PFSRC10_FSEL1 (*((volatile unsigned int*)(0x42A79544UL))) +#define bM4_PORT_PFSRC10_FSEL2 (*((volatile unsigned int*)(0x42A79548UL))) +#define bM4_PORT_PFSRC10_FSEL3 (*((volatile unsigned int*)(0x42A7954CUL))) +#define bM4_PORT_PFSRC10_FSEL4 (*((volatile unsigned int*)(0x42A79550UL))) +#define bM4_PORT_PFSRC10_FSEL5 (*((volatile unsigned int*)(0x42A79554UL))) +#define bM4_PORT_PFSRC10_BFE (*((volatile unsigned int*)(0x42A79560UL))) +#define bM4_PORT_PCRC11_POUT (*((volatile unsigned int*)(0x42A79580UL))) +#define bM4_PORT_PCRC11_POUTE (*((volatile unsigned int*)(0x42A79584UL))) +#define bM4_PORT_PCRC11_NOD (*((volatile unsigned int*)(0x42A79588UL))) +#define bM4_PORT_PCRC11_DRV0 (*((volatile unsigned int*)(0x42A79590UL))) +#define bM4_PORT_PCRC11_DRV1 (*((volatile unsigned int*)(0x42A79594UL))) +#define bM4_PORT_PCRC11_PUU (*((volatile unsigned int*)(0x42A79598UL))) +#define bM4_PORT_PCRC11_PIN (*((volatile unsigned int*)(0x42A795A0UL))) +#define bM4_PORT_PCRC11_INVE (*((volatile unsigned int*)(0x42A795A4UL))) +#define bM4_PORT_PCRC11_INTE (*((volatile unsigned int*)(0x42A795B0UL))) +#define bM4_PORT_PCRC11_LTE (*((volatile unsigned int*)(0x42A795B8UL))) +#define bM4_PORT_PCRC11_DDIS (*((volatile unsigned int*)(0x42A795BCUL))) +#define bM4_PORT_PFSRC11_FSEL0 (*((volatile unsigned int*)(0x42A795C0UL))) +#define bM4_PORT_PFSRC11_FSEL1 (*((volatile unsigned int*)(0x42A795C4UL))) +#define bM4_PORT_PFSRC11_FSEL2 (*((volatile unsigned int*)(0x42A795C8UL))) +#define bM4_PORT_PFSRC11_FSEL3 (*((volatile unsigned int*)(0x42A795CCUL))) +#define bM4_PORT_PFSRC11_FSEL4 (*((volatile unsigned int*)(0x42A795D0UL))) +#define bM4_PORT_PFSRC11_FSEL5 (*((volatile unsigned int*)(0x42A795D4UL))) +#define bM4_PORT_PFSRC11_BFE (*((volatile unsigned int*)(0x42A795E0UL))) +#define bM4_PORT_PCRC12_POUT (*((volatile unsigned int*)(0x42A79600UL))) +#define bM4_PORT_PCRC12_POUTE (*((volatile unsigned int*)(0x42A79604UL))) +#define bM4_PORT_PCRC12_NOD (*((volatile unsigned int*)(0x42A79608UL))) +#define bM4_PORT_PCRC12_DRV0 (*((volatile unsigned int*)(0x42A79610UL))) +#define bM4_PORT_PCRC12_DRV1 (*((volatile unsigned int*)(0x42A79614UL))) +#define bM4_PORT_PCRC12_PUU (*((volatile unsigned int*)(0x42A79618UL))) +#define bM4_PORT_PCRC12_PIN (*((volatile unsigned int*)(0x42A79620UL))) +#define bM4_PORT_PCRC12_INVE (*((volatile unsigned int*)(0x42A79624UL))) +#define bM4_PORT_PCRC12_INTE (*((volatile unsigned int*)(0x42A79630UL))) +#define bM4_PORT_PCRC12_LTE (*((volatile unsigned int*)(0x42A79638UL))) +#define bM4_PORT_PCRC12_DDIS (*((volatile unsigned int*)(0x42A7963CUL))) +#define bM4_PORT_PFSRC12_FSEL0 (*((volatile unsigned int*)(0x42A79640UL))) +#define bM4_PORT_PFSRC12_FSEL1 (*((volatile unsigned int*)(0x42A79644UL))) +#define bM4_PORT_PFSRC12_FSEL2 (*((volatile unsigned int*)(0x42A79648UL))) +#define bM4_PORT_PFSRC12_FSEL3 (*((volatile unsigned int*)(0x42A7964CUL))) +#define bM4_PORT_PFSRC12_FSEL4 (*((volatile unsigned int*)(0x42A79650UL))) +#define bM4_PORT_PFSRC12_FSEL5 (*((volatile unsigned int*)(0x42A79654UL))) +#define bM4_PORT_PFSRC12_BFE (*((volatile unsigned int*)(0x42A79660UL))) +#define bM4_PORT_PCRC13_POUT (*((volatile unsigned int*)(0x42A79680UL))) +#define bM4_PORT_PCRC13_POUTE (*((volatile unsigned int*)(0x42A79684UL))) +#define bM4_PORT_PCRC13_NOD (*((volatile unsigned int*)(0x42A79688UL))) +#define bM4_PORT_PCRC13_DRV0 (*((volatile unsigned int*)(0x42A79690UL))) +#define bM4_PORT_PCRC13_DRV1 (*((volatile unsigned int*)(0x42A79694UL))) +#define bM4_PORT_PCRC13_PUU (*((volatile unsigned int*)(0x42A79698UL))) +#define bM4_PORT_PCRC13_PIN (*((volatile unsigned int*)(0x42A796A0UL))) +#define bM4_PORT_PCRC13_INVE (*((volatile unsigned int*)(0x42A796A4UL))) +#define bM4_PORT_PCRC13_INTE (*((volatile unsigned int*)(0x42A796B0UL))) +#define bM4_PORT_PCRC13_LTE (*((volatile unsigned int*)(0x42A796B8UL))) +#define bM4_PORT_PCRC13_DDIS (*((volatile unsigned int*)(0x42A796BCUL))) +#define bM4_PORT_PFSRC13_FSEL0 (*((volatile unsigned int*)(0x42A796C0UL))) +#define bM4_PORT_PFSRC13_FSEL1 (*((volatile unsigned int*)(0x42A796C4UL))) +#define bM4_PORT_PFSRC13_FSEL2 (*((volatile unsigned int*)(0x42A796C8UL))) +#define bM4_PORT_PFSRC13_FSEL3 (*((volatile unsigned int*)(0x42A796CCUL))) +#define bM4_PORT_PFSRC13_FSEL4 (*((volatile unsigned int*)(0x42A796D0UL))) +#define bM4_PORT_PFSRC13_FSEL5 (*((volatile unsigned int*)(0x42A796D4UL))) +#define bM4_PORT_PFSRC13_BFE (*((volatile unsigned int*)(0x42A796E0UL))) +#define bM4_PORT_PCRC14_POUT (*((volatile unsigned int*)(0x42A79700UL))) +#define bM4_PORT_PCRC14_POUTE (*((volatile unsigned int*)(0x42A79704UL))) +#define bM4_PORT_PCRC14_NOD (*((volatile unsigned int*)(0x42A79708UL))) +#define bM4_PORT_PCRC14_DRV0 (*((volatile unsigned int*)(0x42A79710UL))) +#define bM4_PORT_PCRC14_DRV1 (*((volatile unsigned int*)(0x42A79714UL))) +#define bM4_PORT_PCRC14_PUU (*((volatile unsigned int*)(0x42A79718UL))) +#define bM4_PORT_PCRC14_PIN (*((volatile unsigned int*)(0x42A79720UL))) +#define bM4_PORT_PCRC14_INVE (*((volatile unsigned int*)(0x42A79724UL))) +#define bM4_PORT_PCRC14_INTE (*((volatile unsigned int*)(0x42A79730UL))) +#define bM4_PORT_PCRC14_LTE (*((volatile unsigned int*)(0x42A79738UL))) +#define bM4_PORT_PCRC14_DDIS (*((volatile unsigned int*)(0x42A7973CUL))) +#define bM4_PORT_PFSRC14_FSEL0 (*((volatile unsigned int*)(0x42A79740UL))) +#define bM4_PORT_PFSRC14_FSEL1 (*((volatile unsigned int*)(0x42A79744UL))) +#define bM4_PORT_PFSRC14_FSEL2 (*((volatile unsigned int*)(0x42A79748UL))) +#define bM4_PORT_PFSRC14_FSEL3 (*((volatile unsigned int*)(0x42A7974CUL))) +#define bM4_PORT_PFSRC14_FSEL4 (*((volatile unsigned int*)(0x42A79750UL))) +#define bM4_PORT_PFSRC14_FSEL5 (*((volatile unsigned int*)(0x42A79754UL))) +#define bM4_PORT_PFSRC14_BFE (*((volatile unsigned int*)(0x42A79760UL))) +#define bM4_PORT_PCRC15_POUT (*((volatile unsigned int*)(0x42A79780UL))) +#define bM4_PORT_PCRC15_POUTE (*((volatile unsigned int*)(0x42A79784UL))) +#define bM4_PORT_PCRC15_NOD (*((volatile unsigned int*)(0x42A79788UL))) +#define bM4_PORT_PCRC15_DRV0 (*((volatile unsigned int*)(0x42A79790UL))) +#define bM4_PORT_PCRC15_DRV1 (*((volatile unsigned int*)(0x42A79794UL))) +#define bM4_PORT_PCRC15_PUU (*((volatile unsigned int*)(0x42A79798UL))) +#define bM4_PORT_PCRC15_PIN (*((volatile unsigned int*)(0x42A797A0UL))) +#define bM4_PORT_PCRC15_INVE (*((volatile unsigned int*)(0x42A797A4UL))) +#define bM4_PORT_PCRC15_INTE (*((volatile unsigned int*)(0x42A797B0UL))) +#define bM4_PORT_PCRC15_LTE (*((volatile unsigned int*)(0x42A797B8UL))) +#define bM4_PORT_PCRC15_DDIS (*((volatile unsigned int*)(0x42A797BCUL))) +#define bM4_PORT_PFSRC15_FSEL0 (*((volatile unsigned int*)(0x42A797C0UL))) +#define bM4_PORT_PFSRC15_FSEL1 (*((volatile unsigned int*)(0x42A797C4UL))) +#define bM4_PORT_PFSRC15_FSEL2 (*((volatile unsigned int*)(0x42A797C8UL))) +#define bM4_PORT_PFSRC15_FSEL3 (*((volatile unsigned int*)(0x42A797CCUL))) +#define bM4_PORT_PFSRC15_FSEL4 (*((volatile unsigned int*)(0x42A797D0UL))) +#define bM4_PORT_PFSRC15_FSEL5 (*((volatile unsigned int*)(0x42A797D4UL))) +#define bM4_PORT_PFSRC15_BFE (*((volatile unsigned int*)(0x42A797E0UL))) +#define bM4_PORT_PCRD0_POUT (*((volatile unsigned int*)(0x42A79800UL))) +#define bM4_PORT_PCRD0_POUTE (*((volatile unsigned int*)(0x42A79804UL))) +#define bM4_PORT_PCRD0_NOD (*((volatile unsigned int*)(0x42A79808UL))) +#define bM4_PORT_PCRD0_DRV0 (*((volatile unsigned int*)(0x42A79810UL))) +#define bM4_PORT_PCRD0_DRV1 (*((volatile unsigned int*)(0x42A79814UL))) +#define bM4_PORT_PCRD0_PUU (*((volatile unsigned int*)(0x42A79818UL))) +#define bM4_PORT_PCRD0_PIN (*((volatile unsigned int*)(0x42A79820UL))) +#define bM4_PORT_PCRD0_INVE (*((volatile unsigned int*)(0x42A79824UL))) +#define bM4_PORT_PCRD0_INTE (*((volatile unsigned int*)(0x42A79830UL))) +#define bM4_PORT_PCRD0_LTE (*((volatile unsigned int*)(0x42A79838UL))) +#define bM4_PORT_PCRD0_DDIS (*((volatile unsigned int*)(0x42A7983CUL))) +#define bM4_PORT_PFSRD0_FSEL0 (*((volatile unsigned int*)(0x42A79840UL))) +#define bM4_PORT_PFSRD0_FSEL1 (*((volatile unsigned int*)(0x42A79844UL))) +#define bM4_PORT_PFSRD0_FSEL2 (*((volatile unsigned int*)(0x42A79848UL))) +#define bM4_PORT_PFSRD0_FSEL3 (*((volatile unsigned int*)(0x42A7984CUL))) +#define bM4_PORT_PFSRD0_FSEL4 (*((volatile unsigned int*)(0x42A79850UL))) +#define bM4_PORT_PFSRD0_FSEL5 (*((volatile unsigned int*)(0x42A79854UL))) +#define bM4_PORT_PFSRD0_BFE (*((volatile unsigned int*)(0x42A79860UL))) +#define bM4_PORT_PCRD1_POUT (*((volatile unsigned int*)(0x42A79880UL))) +#define bM4_PORT_PCRD1_POUTE (*((volatile unsigned int*)(0x42A79884UL))) +#define bM4_PORT_PCRD1_NOD (*((volatile unsigned int*)(0x42A79888UL))) +#define bM4_PORT_PCRD1_DRV0 (*((volatile unsigned int*)(0x42A79890UL))) +#define bM4_PORT_PCRD1_DRV1 (*((volatile unsigned int*)(0x42A79894UL))) +#define bM4_PORT_PCRD1_PUU (*((volatile unsigned int*)(0x42A79898UL))) +#define bM4_PORT_PCRD1_PIN (*((volatile unsigned int*)(0x42A798A0UL))) +#define bM4_PORT_PCRD1_INVE (*((volatile unsigned int*)(0x42A798A4UL))) +#define bM4_PORT_PCRD1_INTE (*((volatile unsigned int*)(0x42A798B0UL))) +#define bM4_PORT_PCRD1_LTE (*((volatile unsigned int*)(0x42A798B8UL))) +#define bM4_PORT_PCRD1_DDIS (*((volatile unsigned int*)(0x42A798BCUL))) +#define bM4_PORT_PFSRD1_FSEL0 (*((volatile unsigned int*)(0x42A798C0UL))) +#define bM4_PORT_PFSRD1_FSEL1 (*((volatile unsigned int*)(0x42A798C4UL))) +#define bM4_PORT_PFSRD1_FSEL2 (*((volatile unsigned int*)(0x42A798C8UL))) +#define bM4_PORT_PFSRD1_FSEL3 (*((volatile unsigned int*)(0x42A798CCUL))) +#define bM4_PORT_PFSRD1_FSEL4 (*((volatile unsigned int*)(0x42A798D0UL))) +#define bM4_PORT_PFSRD1_FSEL5 (*((volatile unsigned int*)(0x42A798D4UL))) +#define bM4_PORT_PFSRD1_BFE (*((volatile unsigned int*)(0x42A798E0UL))) +#define bM4_PORT_PCRD2_POUT (*((volatile unsigned int*)(0x42A79900UL))) +#define bM4_PORT_PCRD2_POUTE (*((volatile unsigned int*)(0x42A79904UL))) +#define bM4_PORT_PCRD2_NOD (*((volatile unsigned int*)(0x42A79908UL))) +#define bM4_PORT_PCRD2_DRV0 (*((volatile unsigned int*)(0x42A79910UL))) +#define bM4_PORT_PCRD2_DRV1 (*((volatile unsigned int*)(0x42A79914UL))) +#define bM4_PORT_PCRD2_PUU (*((volatile unsigned int*)(0x42A79918UL))) +#define bM4_PORT_PCRD2_PIN (*((volatile unsigned int*)(0x42A79920UL))) +#define bM4_PORT_PCRD2_INVE (*((volatile unsigned int*)(0x42A79924UL))) +#define bM4_PORT_PCRD2_INTE (*((volatile unsigned int*)(0x42A79930UL))) +#define bM4_PORT_PCRD2_LTE (*((volatile unsigned int*)(0x42A79938UL))) +#define bM4_PORT_PCRD2_DDIS (*((volatile unsigned int*)(0x42A7993CUL))) +#define bM4_PORT_PFSRD2_FSEL0 (*((volatile unsigned int*)(0x42A79940UL))) +#define bM4_PORT_PFSRD2_FSEL1 (*((volatile unsigned int*)(0x42A79944UL))) +#define bM4_PORT_PFSRD2_FSEL2 (*((volatile unsigned int*)(0x42A79948UL))) +#define bM4_PORT_PFSRD2_FSEL3 (*((volatile unsigned int*)(0x42A7994CUL))) +#define bM4_PORT_PFSRD2_FSEL4 (*((volatile unsigned int*)(0x42A79950UL))) +#define bM4_PORT_PFSRD2_FSEL5 (*((volatile unsigned int*)(0x42A79954UL))) +#define bM4_PORT_PFSRD2_BFE (*((volatile unsigned int*)(0x42A79960UL))) +#define bM4_PORT_PCRD3_POUT (*((volatile unsigned int*)(0x42A79980UL))) +#define bM4_PORT_PCRD3_POUTE (*((volatile unsigned int*)(0x42A79984UL))) +#define bM4_PORT_PCRD3_NOD (*((volatile unsigned int*)(0x42A79988UL))) +#define bM4_PORT_PCRD3_DRV0 (*((volatile unsigned int*)(0x42A79990UL))) +#define bM4_PORT_PCRD3_DRV1 (*((volatile unsigned int*)(0x42A79994UL))) +#define bM4_PORT_PCRD3_PUU (*((volatile unsigned int*)(0x42A79998UL))) +#define bM4_PORT_PCRD3_PIN (*((volatile unsigned int*)(0x42A799A0UL))) +#define bM4_PORT_PCRD3_INVE (*((volatile unsigned int*)(0x42A799A4UL))) +#define bM4_PORT_PCRD3_INTE (*((volatile unsigned int*)(0x42A799B0UL))) +#define bM4_PORT_PCRD3_LTE (*((volatile unsigned int*)(0x42A799B8UL))) +#define bM4_PORT_PCRD3_DDIS (*((volatile unsigned int*)(0x42A799BCUL))) +#define bM4_PORT_PFSRD3_FSEL0 (*((volatile unsigned int*)(0x42A799C0UL))) +#define bM4_PORT_PFSRD3_FSEL1 (*((volatile unsigned int*)(0x42A799C4UL))) +#define bM4_PORT_PFSRD3_FSEL2 (*((volatile unsigned int*)(0x42A799C8UL))) +#define bM4_PORT_PFSRD3_FSEL3 (*((volatile unsigned int*)(0x42A799CCUL))) +#define bM4_PORT_PFSRD3_FSEL4 (*((volatile unsigned int*)(0x42A799D0UL))) +#define bM4_PORT_PFSRD3_FSEL5 (*((volatile unsigned int*)(0x42A799D4UL))) +#define bM4_PORT_PFSRD3_BFE (*((volatile unsigned int*)(0x42A799E0UL))) +#define bM4_PORT_PCRD4_POUT (*((volatile unsigned int*)(0x42A79A00UL))) +#define bM4_PORT_PCRD4_POUTE (*((volatile unsigned int*)(0x42A79A04UL))) +#define bM4_PORT_PCRD4_NOD (*((volatile unsigned int*)(0x42A79A08UL))) +#define bM4_PORT_PCRD4_DRV0 (*((volatile unsigned int*)(0x42A79A10UL))) +#define bM4_PORT_PCRD4_DRV1 (*((volatile unsigned int*)(0x42A79A14UL))) +#define bM4_PORT_PCRD4_PUU (*((volatile unsigned int*)(0x42A79A18UL))) +#define bM4_PORT_PCRD4_PIN (*((volatile unsigned int*)(0x42A79A20UL))) +#define bM4_PORT_PCRD4_INVE (*((volatile unsigned int*)(0x42A79A24UL))) +#define bM4_PORT_PCRD4_INTE (*((volatile unsigned int*)(0x42A79A30UL))) +#define bM4_PORT_PCRD4_LTE (*((volatile unsigned int*)(0x42A79A38UL))) +#define bM4_PORT_PCRD4_DDIS (*((volatile unsigned int*)(0x42A79A3CUL))) +#define bM4_PORT_PFSRD4_FSEL0 (*((volatile unsigned int*)(0x42A79A40UL))) +#define bM4_PORT_PFSRD4_FSEL1 (*((volatile unsigned int*)(0x42A79A44UL))) +#define bM4_PORT_PFSRD4_FSEL2 (*((volatile unsigned int*)(0x42A79A48UL))) +#define bM4_PORT_PFSRD4_FSEL3 (*((volatile unsigned int*)(0x42A79A4CUL))) +#define bM4_PORT_PFSRD4_FSEL4 (*((volatile unsigned int*)(0x42A79A50UL))) +#define bM4_PORT_PFSRD4_FSEL5 (*((volatile unsigned int*)(0x42A79A54UL))) +#define bM4_PORT_PFSRD4_BFE (*((volatile unsigned int*)(0x42A79A60UL))) +#define bM4_PORT_PCRD5_POUT (*((volatile unsigned int*)(0x42A79A80UL))) +#define bM4_PORT_PCRD5_POUTE (*((volatile unsigned int*)(0x42A79A84UL))) +#define bM4_PORT_PCRD5_NOD (*((volatile unsigned int*)(0x42A79A88UL))) +#define bM4_PORT_PCRD5_DRV0 (*((volatile unsigned int*)(0x42A79A90UL))) +#define bM4_PORT_PCRD5_DRV1 (*((volatile unsigned int*)(0x42A79A94UL))) +#define bM4_PORT_PCRD5_PUU (*((volatile unsigned int*)(0x42A79A98UL))) +#define bM4_PORT_PCRD5_PIN (*((volatile unsigned int*)(0x42A79AA0UL))) +#define bM4_PORT_PCRD5_INVE (*((volatile unsigned int*)(0x42A79AA4UL))) +#define bM4_PORT_PCRD5_INTE (*((volatile unsigned int*)(0x42A79AB0UL))) +#define bM4_PORT_PCRD5_LTE (*((volatile unsigned int*)(0x42A79AB8UL))) +#define bM4_PORT_PCRD5_DDIS (*((volatile unsigned int*)(0x42A79ABCUL))) +#define bM4_PORT_PFSRD5_FSEL0 (*((volatile unsigned int*)(0x42A79AC0UL))) +#define bM4_PORT_PFSRD5_FSEL1 (*((volatile unsigned int*)(0x42A79AC4UL))) +#define bM4_PORT_PFSRD5_FSEL2 (*((volatile unsigned int*)(0x42A79AC8UL))) +#define bM4_PORT_PFSRD5_FSEL3 (*((volatile unsigned int*)(0x42A79ACCUL))) +#define bM4_PORT_PFSRD5_FSEL4 (*((volatile unsigned int*)(0x42A79AD0UL))) +#define bM4_PORT_PFSRD5_FSEL5 (*((volatile unsigned int*)(0x42A79AD4UL))) +#define bM4_PORT_PFSRD5_BFE (*((volatile unsigned int*)(0x42A79AE0UL))) +#define bM4_PORT_PCRD6_POUT (*((volatile unsigned int*)(0x42A79B00UL))) +#define bM4_PORT_PCRD6_POUTE (*((volatile unsigned int*)(0x42A79B04UL))) +#define bM4_PORT_PCRD6_NOD (*((volatile unsigned int*)(0x42A79B08UL))) +#define bM4_PORT_PCRD6_DRV0 (*((volatile unsigned int*)(0x42A79B10UL))) +#define bM4_PORT_PCRD6_DRV1 (*((volatile unsigned int*)(0x42A79B14UL))) +#define bM4_PORT_PCRD6_PUU (*((volatile unsigned int*)(0x42A79B18UL))) +#define bM4_PORT_PCRD6_PIN (*((volatile unsigned int*)(0x42A79B20UL))) +#define bM4_PORT_PCRD6_INVE (*((volatile unsigned int*)(0x42A79B24UL))) +#define bM4_PORT_PCRD6_INTE (*((volatile unsigned int*)(0x42A79B30UL))) +#define bM4_PORT_PCRD6_LTE (*((volatile unsigned int*)(0x42A79B38UL))) +#define bM4_PORT_PCRD6_DDIS (*((volatile unsigned int*)(0x42A79B3CUL))) +#define bM4_PORT_PFSRD6_FSEL0 (*((volatile unsigned int*)(0x42A79B40UL))) +#define bM4_PORT_PFSRD6_FSEL1 (*((volatile unsigned int*)(0x42A79B44UL))) +#define bM4_PORT_PFSRD6_FSEL2 (*((volatile unsigned int*)(0x42A79B48UL))) +#define bM4_PORT_PFSRD6_FSEL3 (*((volatile unsigned int*)(0x42A79B4CUL))) +#define bM4_PORT_PFSRD6_FSEL4 (*((volatile unsigned int*)(0x42A79B50UL))) +#define bM4_PORT_PFSRD6_FSEL5 (*((volatile unsigned int*)(0x42A79B54UL))) +#define bM4_PORT_PFSRD6_BFE (*((volatile unsigned int*)(0x42A79B60UL))) +#define bM4_PORT_PCRD7_POUT (*((volatile unsigned int*)(0x42A79B80UL))) +#define bM4_PORT_PCRD7_POUTE (*((volatile unsigned int*)(0x42A79B84UL))) +#define bM4_PORT_PCRD7_NOD (*((volatile unsigned int*)(0x42A79B88UL))) +#define bM4_PORT_PCRD7_DRV0 (*((volatile unsigned int*)(0x42A79B90UL))) +#define bM4_PORT_PCRD7_DRV1 (*((volatile unsigned int*)(0x42A79B94UL))) +#define bM4_PORT_PCRD7_PUU (*((volatile unsigned int*)(0x42A79B98UL))) +#define bM4_PORT_PCRD7_PIN (*((volatile unsigned int*)(0x42A79BA0UL))) +#define bM4_PORT_PCRD7_INVE (*((volatile unsigned int*)(0x42A79BA4UL))) +#define bM4_PORT_PCRD7_INTE (*((volatile unsigned int*)(0x42A79BB0UL))) +#define bM4_PORT_PCRD7_LTE (*((volatile unsigned int*)(0x42A79BB8UL))) +#define bM4_PORT_PCRD7_DDIS (*((volatile unsigned int*)(0x42A79BBCUL))) +#define bM4_PORT_PFSRD7_FSEL0 (*((volatile unsigned int*)(0x42A79BC0UL))) +#define bM4_PORT_PFSRD7_FSEL1 (*((volatile unsigned int*)(0x42A79BC4UL))) +#define bM4_PORT_PFSRD7_FSEL2 (*((volatile unsigned int*)(0x42A79BC8UL))) +#define bM4_PORT_PFSRD7_FSEL3 (*((volatile unsigned int*)(0x42A79BCCUL))) +#define bM4_PORT_PFSRD7_FSEL4 (*((volatile unsigned int*)(0x42A79BD0UL))) +#define bM4_PORT_PFSRD7_FSEL5 (*((volatile unsigned int*)(0x42A79BD4UL))) +#define bM4_PORT_PFSRD7_BFE (*((volatile unsigned int*)(0x42A79BE0UL))) +#define bM4_PORT_PCRD8_POUT (*((volatile unsigned int*)(0x42A79C00UL))) +#define bM4_PORT_PCRD8_POUTE (*((volatile unsigned int*)(0x42A79C04UL))) +#define bM4_PORT_PCRD8_NOD (*((volatile unsigned int*)(0x42A79C08UL))) +#define bM4_PORT_PCRD8_DRV0 (*((volatile unsigned int*)(0x42A79C10UL))) +#define bM4_PORT_PCRD8_DRV1 (*((volatile unsigned int*)(0x42A79C14UL))) +#define bM4_PORT_PCRD8_PUU (*((volatile unsigned int*)(0x42A79C18UL))) +#define bM4_PORT_PCRD8_PIN (*((volatile unsigned int*)(0x42A79C20UL))) +#define bM4_PORT_PCRD8_INVE (*((volatile unsigned int*)(0x42A79C24UL))) +#define bM4_PORT_PCRD8_INTE (*((volatile unsigned int*)(0x42A79C30UL))) +#define bM4_PORT_PCRD8_LTE (*((volatile unsigned int*)(0x42A79C38UL))) +#define bM4_PORT_PCRD8_DDIS (*((volatile unsigned int*)(0x42A79C3CUL))) +#define bM4_PORT_PFSRD8_FSEL0 (*((volatile unsigned int*)(0x42A79C40UL))) +#define bM4_PORT_PFSRD8_FSEL1 (*((volatile unsigned int*)(0x42A79C44UL))) +#define bM4_PORT_PFSRD8_FSEL2 (*((volatile unsigned int*)(0x42A79C48UL))) +#define bM4_PORT_PFSRD8_FSEL3 (*((volatile unsigned int*)(0x42A79C4CUL))) +#define bM4_PORT_PFSRD8_FSEL4 (*((volatile unsigned int*)(0x42A79C50UL))) +#define bM4_PORT_PFSRD8_FSEL5 (*((volatile unsigned int*)(0x42A79C54UL))) +#define bM4_PORT_PFSRD8_BFE (*((volatile unsigned int*)(0x42A79C60UL))) +#define bM4_PORT_PCRD9_POUT (*((volatile unsigned int*)(0x42A79C80UL))) +#define bM4_PORT_PCRD9_POUTE (*((volatile unsigned int*)(0x42A79C84UL))) +#define bM4_PORT_PCRD9_NOD (*((volatile unsigned int*)(0x42A79C88UL))) +#define bM4_PORT_PCRD9_DRV0 (*((volatile unsigned int*)(0x42A79C90UL))) +#define bM4_PORT_PCRD9_DRV1 (*((volatile unsigned int*)(0x42A79C94UL))) +#define bM4_PORT_PCRD9_PUU (*((volatile unsigned int*)(0x42A79C98UL))) +#define bM4_PORT_PCRD9_PIN (*((volatile unsigned int*)(0x42A79CA0UL))) +#define bM4_PORT_PCRD9_INVE (*((volatile unsigned int*)(0x42A79CA4UL))) +#define bM4_PORT_PCRD9_INTE (*((volatile unsigned int*)(0x42A79CB0UL))) +#define bM4_PORT_PCRD9_LTE (*((volatile unsigned int*)(0x42A79CB8UL))) +#define bM4_PORT_PCRD9_DDIS (*((volatile unsigned int*)(0x42A79CBCUL))) +#define bM4_PORT_PFSRD9_FSEL0 (*((volatile unsigned int*)(0x42A79CC0UL))) +#define bM4_PORT_PFSRD9_FSEL1 (*((volatile unsigned int*)(0x42A79CC4UL))) +#define bM4_PORT_PFSRD9_FSEL2 (*((volatile unsigned int*)(0x42A79CC8UL))) +#define bM4_PORT_PFSRD9_FSEL3 (*((volatile unsigned int*)(0x42A79CCCUL))) +#define bM4_PORT_PFSRD9_FSEL4 (*((volatile unsigned int*)(0x42A79CD0UL))) +#define bM4_PORT_PFSRD9_FSEL5 (*((volatile unsigned int*)(0x42A79CD4UL))) +#define bM4_PORT_PFSRD9_BFE (*((volatile unsigned int*)(0x42A79CE0UL))) +#define bM4_PORT_PCRD10_POUT (*((volatile unsigned int*)(0x42A79D00UL))) +#define bM4_PORT_PCRD10_POUTE (*((volatile unsigned int*)(0x42A79D04UL))) +#define bM4_PORT_PCRD10_NOD (*((volatile unsigned int*)(0x42A79D08UL))) +#define bM4_PORT_PCRD10_DRV0 (*((volatile unsigned int*)(0x42A79D10UL))) +#define bM4_PORT_PCRD10_DRV1 (*((volatile unsigned int*)(0x42A79D14UL))) +#define bM4_PORT_PCRD10_PUU (*((volatile unsigned int*)(0x42A79D18UL))) +#define bM4_PORT_PCRD10_PIN (*((volatile unsigned int*)(0x42A79D20UL))) +#define bM4_PORT_PCRD10_INVE (*((volatile unsigned int*)(0x42A79D24UL))) +#define bM4_PORT_PCRD10_INTE (*((volatile unsigned int*)(0x42A79D30UL))) +#define bM4_PORT_PCRD10_LTE (*((volatile unsigned int*)(0x42A79D38UL))) +#define bM4_PORT_PCRD10_DDIS (*((volatile unsigned int*)(0x42A79D3CUL))) +#define bM4_PORT_PFSRD10_FSEL0 (*((volatile unsigned int*)(0x42A79D40UL))) +#define bM4_PORT_PFSRD10_FSEL1 (*((volatile unsigned int*)(0x42A79D44UL))) +#define bM4_PORT_PFSRD10_FSEL2 (*((volatile unsigned int*)(0x42A79D48UL))) +#define bM4_PORT_PFSRD10_FSEL3 (*((volatile unsigned int*)(0x42A79D4CUL))) +#define bM4_PORT_PFSRD10_FSEL4 (*((volatile unsigned int*)(0x42A79D50UL))) +#define bM4_PORT_PFSRD10_FSEL5 (*((volatile unsigned int*)(0x42A79D54UL))) +#define bM4_PORT_PFSRD10_BFE (*((volatile unsigned int*)(0x42A79D60UL))) +#define bM4_PORT_PCRD11_POUT (*((volatile unsigned int*)(0x42A79D80UL))) +#define bM4_PORT_PCRD11_POUTE (*((volatile unsigned int*)(0x42A79D84UL))) +#define bM4_PORT_PCRD11_NOD (*((volatile unsigned int*)(0x42A79D88UL))) +#define bM4_PORT_PCRD11_DRV0 (*((volatile unsigned int*)(0x42A79D90UL))) +#define bM4_PORT_PCRD11_DRV1 (*((volatile unsigned int*)(0x42A79D94UL))) +#define bM4_PORT_PCRD11_PUU (*((volatile unsigned int*)(0x42A79D98UL))) +#define bM4_PORT_PCRD11_PIN (*((volatile unsigned int*)(0x42A79DA0UL))) +#define bM4_PORT_PCRD11_INVE (*((volatile unsigned int*)(0x42A79DA4UL))) +#define bM4_PORT_PCRD11_INTE (*((volatile unsigned int*)(0x42A79DB0UL))) +#define bM4_PORT_PCRD11_LTE (*((volatile unsigned int*)(0x42A79DB8UL))) +#define bM4_PORT_PCRD11_DDIS (*((volatile unsigned int*)(0x42A79DBCUL))) +#define bM4_PORT_PFSRD11_FSEL0 (*((volatile unsigned int*)(0x42A79DC0UL))) +#define bM4_PORT_PFSRD11_FSEL1 (*((volatile unsigned int*)(0x42A79DC4UL))) +#define bM4_PORT_PFSRD11_FSEL2 (*((volatile unsigned int*)(0x42A79DC8UL))) +#define bM4_PORT_PFSRD11_FSEL3 (*((volatile unsigned int*)(0x42A79DCCUL))) +#define bM4_PORT_PFSRD11_FSEL4 (*((volatile unsigned int*)(0x42A79DD0UL))) +#define bM4_PORT_PFSRD11_FSEL5 (*((volatile unsigned int*)(0x42A79DD4UL))) +#define bM4_PORT_PFSRD11_BFE (*((volatile unsigned int*)(0x42A79DE0UL))) +#define bM4_PORT_PCRD12_POUT (*((volatile unsigned int*)(0x42A79E00UL))) +#define bM4_PORT_PCRD12_POUTE (*((volatile unsigned int*)(0x42A79E04UL))) +#define bM4_PORT_PCRD12_NOD (*((volatile unsigned int*)(0x42A79E08UL))) +#define bM4_PORT_PCRD12_DRV0 (*((volatile unsigned int*)(0x42A79E10UL))) +#define bM4_PORT_PCRD12_DRV1 (*((volatile unsigned int*)(0x42A79E14UL))) +#define bM4_PORT_PCRD12_PUU (*((volatile unsigned int*)(0x42A79E18UL))) +#define bM4_PORT_PCRD12_PIN (*((volatile unsigned int*)(0x42A79E20UL))) +#define bM4_PORT_PCRD12_INVE (*((volatile unsigned int*)(0x42A79E24UL))) +#define bM4_PORT_PCRD12_INTE (*((volatile unsigned int*)(0x42A79E30UL))) +#define bM4_PORT_PCRD12_LTE (*((volatile unsigned int*)(0x42A79E38UL))) +#define bM4_PORT_PCRD12_DDIS (*((volatile unsigned int*)(0x42A79E3CUL))) +#define bM4_PORT_PFSRD12_FSEL0 (*((volatile unsigned int*)(0x42A79E40UL))) +#define bM4_PORT_PFSRD12_FSEL1 (*((volatile unsigned int*)(0x42A79E44UL))) +#define bM4_PORT_PFSRD12_FSEL2 (*((volatile unsigned int*)(0x42A79E48UL))) +#define bM4_PORT_PFSRD12_FSEL3 (*((volatile unsigned int*)(0x42A79E4CUL))) +#define bM4_PORT_PFSRD12_FSEL4 (*((volatile unsigned int*)(0x42A79E50UL))) +#define bM4_PORT_PFSRD12_FSEL5 (*((volatile unsigned int*)(0x42A79E54UL))) +#define bM4_PORT_PFSRD12_BFE (*((volatile unsigned int*)(0x42A79E60UL))) +#define bM4_PORT_PCRD13_POUT (*((volatile unsigned int*)(0x42A79E80UL))) +#define bM4_PORT_PCRD13_POUTE (*((volatile unsigned int*)(0x42A79E84UL))) +#define bM4_PORT_PCRD13_NOD (*((volatile unsigned int*)(0x42A79E88UL))) +#define bM4_PORT_PCRD13_DRV0 (*((volatile unsigned int*)(0x42A79E90UL))) +#define bM4_PORT_PCRD13_DRV1 (*((volatile unsigned int*)(0x42A79E94UL))) +#define bM4_PORT_PCRD13_PUU (*((volatile unsigned int*)(0x42A79E98UL))) +#define bM4_PORT_PCRD13_PIN (*((volatile unsigned int*)(0x42A79EA0UL))) +#define bM4_PORT_PCRD13_INVE (*((volatile unsigned int*)(0x42A79EA4UL))) +#define bM4_PORT_PCRD13_INTE (*((volatile unsigned int*)(0x42A79EB0UL))) +#define bM4_PORT_PCRD13_LTE (*((volatile unsigned int*)(0x42A79EB8UL))) +#define bM4_PORT_PCRD13_DDIS (*((volatile unsigned int*)(0x42A79EBCUL))) +#define bM4_PORT_PFSRD13_FSEL0 (*((volatile unsigned int*)(0x42A79EC0UL))) +#define bM4_PORT_PFSRD13_FSEL1 (*((volatile unsigned int*)(0x42A79EC4UL))) +#define bM4_PORT_PFSRD13_FSEL2 (*((volatile unsigned int*)(0x42A79EC8UL))) +#define bM4_PORT_PFSRD13_FSEL3 (*((volatile unsigned int*)(0x42A79ECCUL))) +#define bM4_PORT_PFSRD13_FSEL4 (*((volatile unsigned int*)(0x42A79ED0UL))) +#define bM4_PORT_PFSRD13_FSEL5 (*((volatile unsigned int*)(0x42A79ED4UL))) +#define bM4_PORT_PFSRD13_BFE (*((volatile unsigned int*)(0x42A79EE0UL))) +#define bM4_PORT_PCRD14_POUT (*((volatile unsigned int*)(0x42A79F00UL))) +#define bM4_PORT_PCRD14_POUTE (*((volatile unsigned int*)(0x42A79F04UL))) +#define bM4_PORT_PCRD14_NOD (*((volatile unsigned int*)(0x42A79F08UL))) +#define bM4_PORT_PCRD14_DRV0 (*((volatile unsigned int*)(0x42A79F10UL))) +#define bM4_PORT_PCRD14_DRV1 (*((volatile unsigned int*)(0x42A79F14UL))) +#define bM4_PORT_PCRD14_PUU (*((volatile unsigned int*)(0x42A79F18UL))) +#define bM4_PORT_PCRD14_PIN (*((volatile unsigned int*)(0x42A79F20UL))) +#define bM4_PORT_PCRD14_INVE (*((volatile unsigned int*)(0x42A79F24UL))) +#define bM4_PORT_PCRD14_INTE (*((volatile unsigned int*)(0x42A79F30UL))) +#define bM4_PORT_PCRD14_LTE (*((volatile unsigned int*)(0x42A79F38UL))) +#define bM4_PORT_PCRD14_DDIS (*((volatile unsigned int*)(0x42A79F3CUL))) +#define bM4_PORT_PFSRD14_FSEL0 (*((volatile unsigned int*)(0x42A79F40UL))) +#define bM4_PORT_PFSRD14_FSEL1 (*((volatile unsigned int*)(0x42A79F44UL))) +#define bM4_PORT_PFSRD14_FSEL2 (*((volatile unsigned int*)(0x42A79F48UL))) +#define bM4_PORT_PFSRD14_FSEL3 (*((volatile unsigned int*)(0x42A79F4CUL))) +#define bM4_PORT_PFSRD14_FSEL4 (*((volatile unsigned int*)(0x42A79F50UL))) +#define bM4_PORT_PFSRD14_FSEL5 (*((volatile unsigned int*)(0x42A79F54UL))) +#define bM4_PORT_PFSRD14_BFE (*((volatile unsigned int*)(0x42A79F60UL))) +#define bM4_PORT_PCRD15_POUT (*((volatile unsigned int*)(0x42A79F80UL))) +#define bM4_PORT_PCRD15_POUTE (*((volatile unsigned int*)(0x42A79F84UL))) +#define bM4_PORT_PCRD15_NOD (*((volatile unsigned int*)(0x42A79F88UL))) +#define bM4_PORT_PCRD15_DRV0 (*((volatile unsigned int*)(0x42A79F90UL))) +#define bM4_PORT_PCRD15_DRV1 (*((volatile unsigned int*)(0x42A79F94UL))) +#define bM4_PORT_PCRD15_PUU (*((volatile unsigned int*)(0x42A79F98UL))) +#define bM4_PORT_PCRD15_PIN (*((volatile unsigned int*)(0x42A79FA0UL))) +#define bM4_PORT_PCRD15_INVE (*((volatile unsigned int*)(0x42A79FA4UL))) +#define bM4_PORT_PCRD15_INTE (*((volatile unsigned int*)(0x42A79FB0UL))) +#define bM4_PORT_PCRD15_LTE (*((volatile unsigned int*)(0x42A79FB8UL))) +#define bM4_PORT_PCRD15_DDIS (*((volatile unsigned int*)(0x42A79FBCUL))) +#define bM4_PORT_PFSRD15_FSEL0 (*((volatile unsigned int*)(0x42A79FC0UL))) +#define bM4_PORT_PFSRD15_FSEL1 (*((volatile unsigned int*)(0x42A79FC4UL))) +#define bM4_PORT_PFSRD15_FSEL2 (*((volatile unsigned int*)(0x42A79FC8UL))) +#define bM4_PORT_PFSRD15_FSEL3 (*((volatile unsigned int*)(0x42A79FCCUL))) +#define bM4_PORT_PFSRD15_FSEL4 (*((volatile unsigned int*)(0x42A79FD0UL))) +#define bM4_PORT_PFSRD15_FSEL5 (*((volatile unsigned int*)(0x42A79FD4UL))) +#define bM4_PORT_PFSRD15_BFE (*((volatile unsigned int*)(0x42A79FE0UL))) +#define bM4_PORT_PCRE0_POUT (*((volatile unsigned int*)(0x42A7A000UL))) +#define bM4_PORT_PCRE0_POUTE (*((volatile unsigned int*)(0x42A7A004UL))) +#define bM4_PORT_PCRE0_NOD (*((volatile unsigned int*)(0x42A7A008UL))) +#define bM4_PORT_PCRE0_DRV0 (*((volatile unsigned int*)(0x42A7A010UL))) +#define bM4_PORT_PCRE0_DRV1 (*((volatile unsigned int*)(0x42A7A014UL))) +#define bM4_PORT_PCRE0_PUU (*((volatile unsigned int*)(0x42A7A018UL))) +#define bM4_PORT_PCRE0_PIN (*((volatile unsigned int*)(0x42A7A020UL))) +#define bM4_PORT_PCRE0_INVE (*((volatile unsigned int*)(0x42A7A024UL))) +#define bM4_PORT_PCRE0_INTE (*((volatile unsigned int*)(0x42A7A030UL))) +#define bM4_PORT_PCRE0_LTE (*((volatile unsigned int*)(0x42A7A038UL))) +#define bM4_PORT_PCRE0_DDIS (*((volatile unsigned int*)(0x42A7A03CUL))) +#define bM4_PORT_PFSRE0_FSEL0 (*((volatile unsigned int*)(0x42A7A040UL))) +#define bM4_PORT_PFSRE0_FSEL1 (*((volatile unsigned int*)(0x42A7A044UL))) +#define bM4_PORT_PFSRE0_FSEL2 (*((volatile unsigned int*)(0x42A7A048UL))) +#define bM4_PORT_PFSRE0_FSEL3 (*((volatile unsigned int*)(0x42A7A04CUL))) +#define bM4_PORT_PFSRE0_FSEL4 (*((volatile unsigned int*)(0x42A7A050UL))) +#define bM4_PORT_PFSRE0_FSEL5 (*((volatile unsigned int*)(0x42A7A054UL))) +#define bM4_PORT_PFSRE0_BFE (*((volatile unsigned int*)(0x42A7A060UL))) +#define bM4_PORT_PCRE1_POUT (*((volatile unsigned int*)(0x42A7A080UL))) +#define bM4_PORT_PCRE1_POUTE (*((volatile unsigned int*)(0x42A7A084UL))) +#define bM4_PORT_PCRE1_NOD (*((volatile unsigned int*)(0x42A7A088UL))) +#define bM4_PORT_PCRE1_DRV0 (*((volatile unsigned int*)(0x42A7A090UL))) +#define bM4_PORT_PCRE1_DRV1 (*((volatile unsigned int*)(0x42A7A094UL))) +#define bM4_PORT_PCRE1_PUU (*((volatile unsigned int*)(0x42A7A098UL))) +#define bM4_PORT_PCRE1_PIN (*((volatile unsigned int*)(0x42A7A0A0UL))) +#define bM4_PORT_PCRE1_INVE (*((volatile unsigned int*)(0x42A7A0A4UL))) +#define bM4_PORT_PCRE1_INTE (*((volatile unsigned int*)(0x42A7A0B0UL))) +#define bM4_PORT_PCRE1_LTE (*((volatile unsigned int*)(0x42A7A0B8UL))) +#define bM4_PORT_PCRE1_DDIS (*((volatile unsigned int*)(0x42A7A0BCUL))) +#define bM4_PORT_PFSRE1_FSEL0 (*((volatile unsigned int*)(0x42A7A0C0UL))) +#define bM4_PORT_PFSRE1_FSEL1 (*((volatile unsigned int*)(0x42A7A0C4UL))) +#define bM4_PORT_PFSRE1_FSEL2 (*((volatile unsigned int*)(0x42A7A0C8UL))) +#define bM4_PORT_PFSRE1_FSEL3 (*((volatile unsigned int*)(0x42A7A0CCUL))) +#define bM4_PORT_PFSRE1_FSEL4 (*((volatile unsigned int*)(0x42A7A0D0UL))) +#define bM4_PORT_PFSRE1_FSEL5 (*((volatile unsigned int*)(0x42A7A0D4UL))) +#define bM4_PORT_PFSRE1_BFE (*((volatile unsigned int*)(0x42A7A0E0UL))) +#define bM4_PORT_PCRE2_POUT (*((volatile unsigned int*)(0x42A7A100UL))) +#define bM4_PORT_PCRE2_POUTE (*((volatile unsigned int*)(0x42A7A104UL))) +#define bM4_PORT_PCRE2_NOD (*((volatile unsigned int*)(0x42A7A108UL))) +#define bM4_PORT_PCRE2_DRV0 (*((volatile unsigned int*)(0x42A7A110UL))) +#define bM4_PORT_PCRE2_DRV1 (*((volatile unsigned int*)(0x42A7A114UL))) +#define bM4_PORT_PCRE2_PUU (*((volatile unsigned int*)(0x42A7A118UL))) +#define bM4_PORT_PCRE2_PIN (*((volatile unsigned int*)(0x42A7A120UL))) +#define bM4_PORT_PCRE2_INVE (*((volatile unsigned int*)(0x42A7A124UL))) +#define bM4_PORT_PCRE2_INTE (*((volatile unsigned int*)(0x42A7A130UL))) +#define bM4_PORT_PCRE2_LTE (*((volatile unsigned int*)(0x42A7A138UL))) +#define bM4_PORT_PCRE2_DDIS (*((volatile unsigned int*)(0x42A7A13CUL))) +#define bM4_PORT_PFSRE2_FSEL0 (*((volatile unsigned int*)(0x42A7A140UL))) +#define bM4_PORT_PFSRE2_FSEL1 (*((volatile unsigned int*)(0x42A7A144UL))) +#define bM4_PORT_PFSRE2_FSEL2 (*((volatile unsigned int*)(0x42A7A148UL))) +#define bM4_PORT_PFSRE2_FSEL3 (*((volatile unsigned int*)(0x42A7A14CUL))) +#define bM4_PORT_PFSRE2_FSEL4 (*((volatile unsigned int*)(0x42A7A150UL))) +#define bM4_PORT_PFSRE2_FSEL5 (*((volatile unsigned int*)(0x42A7A154UL))) +#define bM4_PORT_PFSRE2_BFE (*((volatile unsigned int*)(0x42A7A160UL))) +#define bM4_PORT_PCRE3_POUT (*((volatile unsigned int*)(0x42A7A180UL))) +#define bM4_PORT_PCRE3_POUTE (*((volatile unsigned int*)(0x42A7A184UL))) +#define bM4_PORT_PCRE3_NOD (*((volatile unsigned int*)(0x42A7A188UL))) +#define bM4_PORT_PCRE3_DRV0 (*((volatile unsigned int*)(0x42A7A190UL))) +#define bM4_PORT_PCRE3_DRV1 (*((volatile unsigned int*)(0x42A7A194UL))) +#define bM4_PORT_PCRE3_PUU (*((volatile unsigned int*)(0x42A7A198UL))) +#define bM4_PORT_PCRE3_PIN (*((volatile unsigned int*)(0x42A7A1A0UL))) +#define bM4_PORT_PCRE3_INVE (*((volatile unsigned int*)(0x42A7A1A4UL))) +#define bM4_PORT_PCRE3_INTE (*((volatile unsigned int*)(0x42A7A1B0UL))) +#define bM4_PORT_PCRE3_LTE (*((volatile unsigned int*)(0x42A7A1B8UL))) +#define bM4_PORT_PCRE3_DDIS (*((volatile unsigned int*)(0x42A7A1BCUL))) +#define bM4_PORT_PFSRE3_FSEL0 (*((volatile unsigned int*)(0x42A7A1C0UL))) +#define bM4_PORT_PFSRE3_FSEL1 (*((volatile unsigned int*)(0x42A7A1C4UL))) +#define bM4_PORT_PFSRE3_FSEL2 (*((volatile unsigned int*)(0x42A7A1C8UL))) +#define bM4_PORT_PFSRE3_FSEL3 (*((volatile unsigned int*)(0x42A7A1CCUL))) +#define bM4_PORT_PFSRE3_FSEL4 (*((volatile unsigned int*)(0x42A7A1D0UL))) +#define bM4_PORT_PFSRE3_FSEL5 (*((volatile unsigned int*)(0x42A7A1D4UL))) +#define bM4_PORT_PFSRE3_BFE (*((volatile unsigned int*)(0x42A7A1E0UL))) +#define bM4_PORT_PCRE4_POUT (*((volatile unsigned int*)(0x42A7A200UL))) +#define bM4_PORT_PCRE4_POUTE (*((volatile unsigned int*)(0x42A7A204UL))) +#define bM4_PORT_PCRE4_NOD (*((volatile unsigned int*)(0x42A7A208UL))) +#define bM4_PORT_PCRE4_DRV0 (*((volatile unsigned int*)(0x42A7A210UL))) +#define bM4_PORT_PCRE4_DRV1 (*((volatile unsigned int*)(0x42A7A214UL))) +#define bM4_PORT_PCRE4_PUU (*((volatile unsigned int*)(0x42A7A218UL))) +#define bM4_PORT_PCRE4_PIN (*((volatile unsigned int*)(0x42A7A220UL))) +#define bM4_PORT_PCRE4_INVE (*((volatile unsigned int*)(0x42A7A224UL))) +#define bM4_PORT_PCRE4_INTE (*((volatile unsigned int*)(0x42A7A230UL))) +#define bM4_PORT_PCRE4_LTE (*((volatile unsigned int*)(0x42A7A238UL))) +#define bM4_PORT_PCRE4_DDIS (*((volatile unsigned int*)(0x42A7A23CUL))) +#define bM4_PORT_PFSRE4_FSEL0 (*((volatile unsigned int*)(0x42A7A240UL))) +#define bM4_PORT_PFSRE4_FSEL1 (*((volatile unsigned int*)(0x42A7A244UL))) +#define bM4_PORT_PFSRE4_FSEL2 (*((volatile unsigned int*)(0x42A7A248UL))) +#define bM4_PORT_PFSRE4_FSEL3 (*((volatile unsigned int*)(0x42A7A24CUL))) +#define bM4_PORT_PFSRE4_FSEL4 (*((volatile unsigned int*)(0x42A7A250UL))) +#define bM4_PORT_PFSRE4_FSEL5 (*((volatile unsigned int*)(0x42A7A254UL))) +#define bM4_PORT_PFSRE4_BFE (*((volatile unsigned int*)(0x42A7A260UL))) +#define bM4_PORT_PCRE5_POUT (*((volatile unsigned int*)(0x42A7A280UL))) +#define bM4_PORT_PCRE5_POUTE (*((volatile unsigned int*)(0x42A7A284UL))) +#define bM4_PORT_PCRE5_NOD (*((volatile unsigned int*)(0x42A7A288UL))) +#define bM4_PORT_PCRE5_DRV0 (*((volatile unsigned int*)(0x42A7A290UL))) +#define bM4_PORT_PCRE5_DRV1 (*((volatile unsigned int*)(0x42A7A294UL))) +#define bM4_PORT_PCRE5_PUU (*((volatile unsigned int*)(0x42A7A298UL))) +#define bM4_PORT_PCRE5_PIN (*((volatile unsigned int*)(0x42A7A2A0UL))) +#define bM4_PORT_PCRE5_INVE (*((volatile unsigned int*)(0x42A7A2A4UL))) +#define bM4_PORT_PCRE5_INTE (*((volatile unsigned int*)(0x42A7A2B0UL))) +#define bM4_PORT_PCRE5_LTE (*((volatile unsigned int*)(0x42A7A2B8UL))) +#define bM4_PORT_PCRE5_DDIS (*((volatile unsigned int*)(0x42A7A2BCUL))) +#define bM4_PORT_PFSRE5_FSEL0 (*((volatile unsigned int*)(0x42A7A2C0UL))) +#define bM4_PORT_PFSRE5_FSEL1 (*((volatile unsigned int*)(0x42A7A2C4UL))) +#define bM4_PORT_PFSRE5_FSEL2 (*((volatile unsigned int*)(0x42A7A2C8UL))) +#define bM4_PORT_PFSRE5_FSEL3 (*((volatile unsigned int*)(0x42A7A2CCUL))) +#define bM4_PORT_PFSRE5_FSEL4 (*((volatile unsigned int*)(0x42A7A2D0UL))) +#define bM4_PORT_PFSRE5_FSEL5 (*((volatile unsigned int*)(0x42A7A2D4UL))) +#define bM4_PORT_PFSRE5_BFE (*((volatile unsigned int*)(0x42A7A2E0UL))) +#define bM4_PORT_PCRE6_POUT (*((volatile unsigned int*)(0x42A7A300UL))) +#define bM4_PORT_PCRE6_POUTE (*((volatile unsigned int*)(0x42A7A304UL))) +#define bM4_PORT_PCRE6_NOD (*((volatile unsigned int*)(0x42A7A308UL))) +#define bM4_PORT_PCRE6_DRV0 (*((volatile unsigned int*)(0x42A7A310UL))) +#define bM4_PORT_PCRE6_DRV1 (*((volatile unsigned int*)(0x42A7A314UL))) +#define bM4_PORT_PCRE6_PUU (*((volatile unsigned int*)(0x42A7A318UL))) +#define bM4_PORT_PCRE6_PIN (*((volatile unsigned int*)(0x42A7A320UL))) +#define bM4_PORT_PCRE6_INVE (*((volatile unsigned int*)(0x42A7A324UL))) +#define bM4_PORT_PCRE6_INTE (*((volatile unsigned int*)(0x42A7A330UL))) +#define bM4_PORT_PCRE6_LTE (*((volatile unsigned int*)(0x42A7A338UL))) +#define bM4_PORT_PCRE6_DDIS (*((volatile unsigned int*)(0x42A7A33CUL))) +#define bM4_PORT_PFSRE6_FSEL0 (*((volatile unsigned int*)(0x42A7A340UL))) +#define bM4_PORT_PFSRE6_FSEL1 (*((volatile unsigned int*)(0x42A7A344UL))) +#define bM4_PORT_PFSRE6_FSEL2 (*((volatile unsigned int*)(0x42A7A348UL))) +#define bM4_PORT_PFSRE6_FSEL3 (*((volatile unsigned int*)(0x42A7A34CUL))) +#define bM4_PORT_PFSRE6_FSEL4 (*((volatile unsigned int*)(0x42A7A350UL))) +#define bM4_PORT_PFSRE6_FSEL5 (*((volatile unsigned int*)(0x42A7A354UL))) +#define bM4_PORT_PFSRE6_BFE (*((volatile unsigned int*)(0x42A7A360UL))) +#define bM4_PORT_PCRE7_POUT (*((volatile unsigned int*)(0x42A7A380UL))) +#define bM4_PORT_PCRE7_POUTE (*((volatile unsigned int*)(0x42A7A384UL))) +#define bM4_PORT_PCRE7_NOD (*((volatile unsigned int*)(0x42A7A388UL))) +#define bM4_PORT_PCRE7_DRV0 (*((volatile unsigned int*)(0x42A7A390UL))) +#define bM4_PORT_PCRE7_DRV1 (*((volatile unsigned int*)(0x42A7A394UL))) +#define bM4_PORT_PCRE7_PUU (*((volatile unsigned int*)(0x42A7A398UL))) +#define bM4_PORT_PCRE7_PIN (*((volatile unsigned int*)(0x42A7A3A0UL))) +#define bM4_PORT_PCRE7_INVE (*((volatile unsigned int*)(0x42A7A3A4UL))) +#define bM4_PORT_PCRE7_INTE (*((volatile unsigned int*)(0x42A7A3B0UL))) +#define bM4_PORT_PCRE7_LTE (*((volatile unsigned int*)(0x42A7A3B8UL))) +#define bM4_PORT_PCRE7_DDIS (*((volatile unsigned int*)(0x42A7A3BCUL))) +#define bM4_PORT_PFSRE7_FSEL0 (*((volatile unsigned int*)(0x42A7A3C0UL))) +#define bM4_PORT_PFSRE7_FSEL1 (*((volatile unsigned int*)(0x42A7A3C4UL))) +#define bM4_PORT_PFSRE7_FSEL2 (*((volatile unsigned int*)(0x42A7A3C8UL))) +#define bM4_PORT_PFSRE7_FSEL3 (*((volatile unsigned int*)(0x42A7A3CCUL))) +#define bM4_PORT_PFSRE7_FSEL4 (*((volatile unsigned int*)(0x42A7A3D0UL))) +#define bM4_PORT_PFSRE7_FSEL5 (*((volatile unsigned int*)(0x42A7A3D4UL))) +#define bM4_PORT_PFSRE7_BFE (*((volatile unsigned int*)(0x42A7A3E0UL))) +#define bM4_PORT_PCRE8_POUT (*((volatile unsigned int*)(0x42A7A400UL))) +#define bM4_PORT_PCRE8_POUTE (*((volatile unsigned int*)(0x42A7A404UL))) +#define bM4_PORT_PCRE8_NOD (*((volatile unsigned int*)(0x42A7A408UL))) +#define bM4_PORT_PCRE8_DRV0 (*((volatile unsigned int*)(0x42A7A410UL))) +#define bM4_PORT_PCRE8_DRV1 (*((volatile unsigned int*)(0x42A7A414UL))) +#define bM4_PORT_PCRE8_PUU (*((volatile unsigned int*)(0x42A7A418UL))) +#define bM4_PORT_PCRE8_PIN (*((volatile unsigned int*)(0x42A7A420UL))) +#define bM4_PORT_PCRE8_INVE (*((volatile unsigned int*)(0x42A7A424UL))) +#define bM4_PORT_PCRE8_INTE (*((volatile unsigned int*)(0x42A7A430UL))) +#define bM4_PORT_PCRE8_LTE (*((volatile unsigned int*)(0x42A7A438UL))) +#define bM4_PORT_PCRE8_DDIS (*((volatile unsigned int*)(0x42A7A43CUL))) +#define bM4_PORT_PFSRE8_FSEL0 (*((volatile unsigned int*)(0x42A7A440UL))) +#define bM4_PORT_PFSRE8_FSEL1 (*((volatile unsigned int*)(0x42A7A444UL))) +#define bM4_PORT_PFSRE8_FSEL2 (*((volatile unsigned int*)(0x42A7A448UL))) +#define bM4_PORT_PFSRE8_FSEL3 (*((volatile unsigned int*)(0x42A7A44CUL))) +#define bM4_PORT_PFSRE8_FSEL4 (*((volatile unsigned int*)(0x42A7A450UL))) +#define bM4_PORT_PFSRE8_FSEL5 (*((volatile unsigned int*)(0x42A7A454UL))) +#define bM4_PORT_PFSRE8_BFE (*((volatile unsigned int*)(0x42A7A460UL))) +#define bM4_PORT_PCRE9_POUT (*((volatile unsigned int*)(0x42A7A480UL))) +#define bM4_PORT_PCRE9_POUTE (*((volatile unsigned int*)(0x42A7A484UL))) +#define bM4_PORT_PCRE9_NOD (*((volatile unsigned int*)(0x42A7A488UL))) +#define bM4_PORT_PCRE9_DRV0 (*((volatile unsigned int*)(0x42A7A490UL))) +#define bM4_PORT_PCRE9_DRV1 (*((volatile unsigned int*)(0x42A7A494UL))) +#define bM4_PORT_PCRE9_PUU (*((volatile unsigned int*)(0x42A7A498UL))) +#define bM4_PORT_PCRE9_PIN (*((volatile unsigned int*)(0x42A7A4A0UL))) +#define bM4_PORT_PCRE9_INVE (*((volatile unsigned int*)(0x42A7A4A4UL))) +#define bM4_PORT_PCRE9_INTE (*((volatile unsigned int*)(0x42A7A4B0UL))) +#define bM4_PORT_PCRE9_LTE (*((volatile unsigned int*)(0x42A7A4B8UL))) +#define bM4_PORT_PCRE9_DDIS (*((volatile unsigned int*)(0x42A7A4BCUL))) +#define bM4_PORT_PFSRE9_FSEL0 (*((volatile unsigned int*)(0x42A7A4C0UL))) +#define bM4_PORT_PFSRE9_FSEL1 (*((volatile unsigned int*)(0x42A7A4C4UL))) +#define bM4_PORT_PFSRE9_FSEL2 (*((volatile unsigned int*)(0x42A7A4C8UL))) +#define bM4_PORT_PFSRE9_FSEL3 (*((volatile unsigned int*)(0x42A7A4CCUL))) +#define bM4_PORT_PFSRE9_FSEL4 (*((volatile unsigned int*)(0x42A7A4D0UL))) +#define bM4_PORT_PFSRE9_FSEL5 (*((volatile unsigned int*)(0x42A7A4D4UL))) +#define bM4_PORT_PFSRE9_BFE (*((volatile unsigned int*)(0x42A7A4E0UL))) +#define bM4_PORT_PCRE10_POUT (*((volatile unsigned int*)(0x42A7A500UL))) +#define bM4_PORT_PCRE10_POUTE (*((volatile unsigned int*)(0x42A7A504UL))) +#define bM4_PORT_PCRE10_NOD (*((volatile unsigned int*)(0x42A7A508UL))) +#define bM4_PORT_PCRE10_DRV0 (*((volatile unsigned int*)(0x42A7A510UL))) +#define bM4_PORT_PCRE10_DRV1 (*((volatile unsigned int*)(0x42A7A514UL))) +#define bM4_PORT_PCRE10_PUU (*((volatile unsigned int*)(0x42A7A518UL))) +#define bM4_PORT_PCRE10_PIN (*((volatile unsigned int*)(0x42A7A520UL))) +#define bM4_PORT_PCRE10_INVE (*((volatile unsigned int*)(0x42A7A524UL))) +#define bM4_PORT_PCRE10_INTE (*((volatile unsigned int*)(0x42A7A530UL))) +#define bM4_PORT_PCRE10_LTE (*((volatile unsigned int*)(0x42A7A538UL))) +#define bM4_PORT_PCRE10_DDIS (*((volatile unsigned int*)(0x42A7A53CUL))) +#define bM4_PORT_PFSRE10_FSEL0 (*((volatile unsigned int*)(0x42A7A540UL))) +#define bM4_PORT_PFSRE10_FSEL1 (*((volatile unsigned int*)(0x42A7A544UL))) +#define bM4_PORT_PFSRE10_FSEL2 (*((volatile unsigned int*)(0x42A7A548UL))) +#define bM4_PORT_PFSRE10_FSEL3 (*((volatile unsigned int*)(0x42A7A54CUL))) +#define bM4_PORT_PFSRE10_FSEL4 (*((volatile unsigned int*)(0x42A7A550UL))) +#define bM4_PORT_PFSRE10_FSEL5 (*((volatile unsigned int*)(0x42A7A554UL))) +#define bM4_PORT_PFSRE10_BFE (*((volatile unsigned int*)(0x42A7A560UL))) +#define bM4_PORT_PCRE11_POUT (*((volatile unsigned int*)(0x42A7A580UL))) +#define bM4_PORT_PCRE11_POUTE (*((volatile unsigned int*)(0x42A7A584UL))) +#define bM4_PORT_PCRE11_NOD (*((volatile unsigned int*)(0x42A7A588UL))) +#define bM4_PORT_PCRE11_DRV0 (*((volatile unsigned int*)(0x42A7A590UL))) +#define bM4_PORT_PCRE11_DRV1 (*((volatile unsigned int*)(0x42A7A594UL))) +#define bM4_PORT_PCRE11_PUU (*((volatile unsigned int*)(0x42A7A598UL))) +#define bM4_PORT_PCRE11_PIN (*((volatile unsigned int*)(0x42A7A5A0UL))) +#define bM4_PORT_PCRE11_INVE (*((volatile unsigned int*)(0x42A7A5A4UL))) +#define bM4_PORT_PCRE11_INTE (*((volatile unsigned int*)(0x42A7A5B0UL))) +#define bM4_PORT_PCRE11_LTE (*((volatile unsigned int*)(0x42A7A5B8UL))) +#define bM4_PORT_PCRE11_DDIS (*((volatile unsigned int*)(0x42A7A5BCUL))) +#define bM4_PORT_PFSRE11_FSEL0 (*((volatile unsigned int*)(0x42A7A5C0UL))) +#define bM4_PORT_PFSRE11_FSEL1 (*((volatile unsigned int*)(0x42A7A5C4UL))) +#define bM4_PORT_PFSRE11_FSEL2 (*((volatile unsigned int*)(0x42A7A5C8UL))) +#define bM4_PORT_PFSRE11_FSEL3 (*((volatile unsigned int*)(0x42A7A5CCUL))) +#define bM4_PORT_PFSRE11_FSEL4 (*((volatile unsigned int*)(0x42A7A5D0UL))) +#define bM4_PORT_PFSRE11_FSEL5 (*((volatile unsigned int*)(0x42A7A5D4UL))) +#define bM4_PORT_PFSRE11_BFE (*((volatile unsigned int*)(0x42A7A5E0UL))) +#define bM4_PORT_PCRE12_POUT (*((volatile unsigned int*)(0x42A7A600UL))) +#define bM4_PORT_PCRE12_POUTE (*((volatile unsigned int*)(0x42A7A604UL))) +#define bM4_PORT_PCRE12_NOD (*((volatile unsigned int*)(0x42A7A608UL))) +#define bM4_PORT_PCRE12_DRV0 (*((volatile unsigned int*)(0x42A7A610UL))) +#define bM4_PORT_PCRE12_DRV1 (*((volatile unsigned int*)(0x42A7A614UL))) +#define bM4_PORT_PCRE12_PUU (*((volatile unsigned int*)(0x42A7A618UL))) +#define bM4_PORT_PCRE12_PIN (*((volatile unsigned int*)(0x42A7A620UL))) +#define bM4_PORT_PCRE12_INVE (*((volatile unsigned int*)(0x42A7A624UL))) +#define bM4_PORT_PCRE12_INTE (*((volatile unsigned int*)(0x42A7A630UL))) +#define bM4_PORT_PCRE12_LTE (*((volatile unsigned int*)(0x42A7A638UL))) +#define bM4_PORT_PCRE12_DDIS (*((volatile unsigned int*)(0x42A7A63CUL))) +#define bM4_PORT_PFSRE12_FSEL0 (*((volatile unsigned int*)(0x42A7A640UL))) +#define bM4_PORT_PFSRE12_FSEL1 (*((volatile unsigned int*)(0x42A7A644UL))) +#define bM4_PORT_PFSRE12_FSEL2 (*((volatile unsigned int*)(0x42A7A648UL))) +#define bM4_PORT_PFSRE12_FSEL3 (*((volatile unsigned int*)(0x42A7A64CUL))) +#define bM4_PORT_PFSRE12_FSEL4 (*((volatile unsigned int*)(0x42A7A650UL))) +#define bM4_PORT_PFSRE12_FSEL5 (*((volatile unsigned int*)(0x42A7A654UL))) +#define bM4_PORT_PFSRE12_BFE (*((volatile unsigned int*)(0x42A7A660UL))) +#define bM4_PORT_PCRE13_POUT (*((volatile unsigned int*)(0x42A7A680UL))) +#define bM4_PORT_PCRE13_POUTE (*((volatile unsigned int*)(0x42A7A684UL))) +#define bM4_PORT_PCRE13_NOD (*((volatile unsigned int*)(0x42A7A688UL))) +#define bM4_PORT_PCRE13_DRV0 (*((volatile unsigned int*)(0x42A7A690UL))) +#define bM4_PORT_PCRE13_DRV1 (*((volatile unsigned int*)(0x42A7A694UL))) +#define bM4_PORT_PCRE13_PUU (*((volatile unsigned int*)(0x42A7A698UL))) +#define bM4_PORT_PCRE13_PIN (*((volatile unsigned int*)(0x42A7A6A0UL))) +#define bM4_PORT_PCRE13_INVE (*((volatile unsigned int*)(0x42A7A6A4UL))) +#define bM4_PORT_PCRE13_INTE (*((volatile unsigned int*)(0x42A7A6B0UL))) +#define bM4_PORT_PCRE13_LTE (*((volatile unsigned int*)(0x42A7A6B8UL))) +#define bM4_PORT_PCRE13_DDIS (*((volatile unsigned int*)(0x42A7A6BCUL))) +#define bM4_PORT_PFSRE13_FSEL0 (*((volatile unsigned int*)(0x42A7A6C0UL))) +#define bM4_PORT_PFSRE13_FSEL1 (*((volatile unsigned int*)(0x42A7A6C4UL))) +#define bM4_PORT_PFSRE13_FSEL2 (*((volatile unsigned int*)(0x42A7A6C8UL))) +#define bM4_PORT_PFSRE13_FSEL3 (*((volatile unsigned int*)(0x42A7A6CCUL))) +#define bM4_PORT_PFSRE13_FSEL4 (*((volatile unsigned int*)(0x42A7A6D0UL))) +#define bM4_PORT_PFSRE13_FSEL5 (*((volatile unsigned int*)(0x42A7A6D4UL))) +#define bM4_PORT_PFSRE13_BFE (*((volatile unsigned int*)(0x42A7A6E0UL))) +#define bM4_PORT_PCRE14_POUT (*((volatile unsigned int*)(0x42A7A700UL))) +#define bM4_PORT_PCRE14_POUTE (*((volatile unsigned int*)(0x42A7A704UL))) +#define bM4_PORT_PCRE14_NOD (*((volatile unsigned int*)(0x42A7A708UL))) +#define bM4_PORT_PCRE14_DRV0 (*((volatile unsigned int*)(0x42A7A710UL))) +#define bM4_PORT_PCRE14_DRV1 (*((volatile unsigned int*)(0x42A7A714UL))) +#define bM4_PORT_PCRE14_PUU (*((volatile unsigned int*)(0x42A7A718UL))) +#define bM4_PORT_PCRE14_PIN (*((volatile unsigned int*)(0x42A7A720UL))) +#define bM4_PORT_PCRE14_INVE (*((volatile unsigned int*)(0x42A7A724UL))) +#define bM4_PORT_PCRE14_INTE (*((volatile unsigned int*)(0x42A7A730UL))) +#define bM4_PORT_PCRE14_LTE (*((volatile unsigned int*)(0x42A7A738UL))) +#define bM4_PORT_PCRE14_DDIS (*((volatile unsigned int*)(0x42A7A73CUL))) +#define bM4_PORT_PFSRE14_FSEL0 (*((volatile unsigned int*)(0x42A7A740UL))) +#define bM4_PORT_PFSRE14_FSEL1 (*((volatile unsigned int*)(0x42A7A744UL))) +#define bM4_PORT_PFSRE14_FSEL2 (*((volatile unsigned int*)(0x42A7A748UL))) +#define bM4_PORT_PFSRE14_FSEL3 (*((volatile unsigned int*)(0x42A7A74CUL))) +#define bM4_PORT_PFSRE14_FSEL4 (*((volatile unsigned int*)(0x42A7A750UL))) +#define bM4_PORT_PFSRE14_FSEL5 (*((volatile unsigned int*)(0x42A7A754UL))) +#define bM4_PORT_PFSRE14_BFE (*((volatile unsigned int*)(0x42A7A760UL))) +#define bM4_PORT_PCRE15_POUT (*((volatile unsigned int*)(0x42A7A780UL))) +#define bM4_PORT_PCRE15_POUTE (*((volatile unsigned int*)(0x42A7A784UL))) +#define bM4_PORT_PCRE15_NOD (*((volatile unsigned int*)(0x42A7A788UL))) +#define bM4_PORT_PCRE15_DRV0 (*((volatile unsigned int*)(0x42A7A790UL))) +#define bM4_PORT_PCRE15_DRV1 (*((volatile unsigned int*)(0x42A7A794UL))) +#define bM4_PORT_PCRE15_PUU (*((volatile unsigned int*)(0x42A7A798UL))) +#define bM4_PORT_PCRE15_PIN (*((volatile unsigned int*)(0x42A7A7A0UL))) +#define bM4_PORT_PCRE15_INVE (*((volatile unsigned int*)(0x42A7A7A4UL))) +#define bM4_PORT_PCRE15_INTE (*((volatile unsigned int*)(0x42A7A7B0UL))) +#define bM4_PORT_PCRE15_LTE (*((volatile unsigned int*)(0x42A7A7B8UL))) +#define bM4_PORT_PCRE15_DDIS (*((volatile unsigned int*)(0x42A7A7BCUL))) +#define bM4_PORT_PFSRE15_FSEL0 (*((volatile unsigned int*)(0x42A7A7C0UL))) +#define bM4_PORT_PFSRE15_FSEL1 (*((volatile unsigned int*)(0x42A7A7C4UL))) +#define bM4_PORT_PFSRE15_FSEL2 (*((volatile unsigned int*)(0x42A7A7C8UL))) +#define bM4_PORT_PFSRE15_FSEL3 (*((volatile unsigned int*)(0x42A7A7CCUL))) +#define bM4_PORT_PFSRE15_FSEL4 (*((volatile unsigned int*)(0x42A7A7D0UL))) +#define bM4_PORT_PFSRE15_FSEL5 (*((volatile unsigned int*)(0x42A7A7D4UL))) +#define bM4_PORT_PFSRE15_BFE (*((volatile unsigned int*)(0x42A7A7E0UL))) +#define bM4_PORT_PCRH0_POUT (*((volatile unsigned int*)(0x42A7A800UL))) +#define bM4_PORT_PCRH0_POUTE (*((volatile unsigned int*)(0x42A7A804UL))) +#define bM4_PORT_PCRH0_NOD (*((volatile unsigned int*)(0x42A7A808UL))) +#define bM4_PORT_PCRH0_DRV0 (*((volatile unsigned int*)(0x42A7A810UL))) +#define bM4_PORT_PCRH0_DRV1 (*((volatile unsigned int*)(0x42A7A814UL))) +#define bM4_PORT_PCRH0_PUU (*((volatile unsigned int*)(0x42A7A818UL))) +#define bM4_PORT_PCRH0_PIN (*((volatile unsigned int*)(0x42A7A820UL))) +#define bM4_PORT_PCRH0_INVE (*((volatile unsigned int*)(0x42A7A824UL))) +#define bM4_PORT_PCRH0_INTE (*((volatile unsigned int*)(0x42A7A830UL))) +#define bM4_PORT_PCRH0_LTE (*((volatile unsigned int*)(0x42A7A838UL))) +#define bM4_PORT_PCRH0_DDIS (*((volatile unsigned int*)(0x42A7A83CUL))) +#define bM4_PORT_PFSRH0_FSEL0 (*((volatile unsigned int*)(0x42A7A840UL))) +#define bM4_PORT_PFSRH0_FSEL1 (*((volatile unsigned int*)(0x42A7A844UL))) +#define bM4_PORT_PFSRH0_FSEL2 (*((volatile unsigned int*)(0x42A7A848UL))) +#define bM4_PORT_PFSRH0_FSEL3 (*((volatile unsigned int*)(0x42A7A84CUL))) +#define bM4_PORT_PFSRH0_FSEL4 (*((volatile unsigned int*)(0x42A7A850UL))) +#define bM4_PORT_PFSRH0_FSEL5 (*((volatile unsigned int*)(0x42A7A854UL))) +#define bM4_PORT_PFSRH0_BFE (*((volatile unsigned int*)(0x42A7A860UL))) +#define bM4_PORT_PCRH1_POUT (*((volatile unsigned int*)(0x42A7A880UL))) +#define bM4_PORT_PCRH1_POUTE (*((volatile unsigned int*)(0x42A7A884UL))) +#define bM4_PORT_PCRH1_NOD (*((volatile unsigned int*)(0x42A7A888UL))) +#define bM4_PORT_PCRH1_DRV0 (*((volatile unsigned int*)(0x42A7A890UL))) +#define bM4_PORT_PCRH1_DRV1 (*((volatile unsigned int*)(0x42A7A894UL))) +#define bM4_PORT_PCRH1_PUU (*((volatile unsigned int*)(0x42A7A898UL))) +#define bM4_PORT_PCRH1_PIN (*((volatile unsigned int*)(0x42A7A8A0UL))) +#define bM4_PORT_PCRH1_INVE (*((volatile unsigned int*)(0x42A7A8A4UL))) +#define bM4_PORT_PCRH1_INTE (*((volatile unsigned int*)(0x42A7A8B0UL))) +#define bM4_PORT_PCRH1_LTE (*((volatile unsigned int*)(0x42A7A8B8UL))) +#define bM4_PORT_PCRH1_DDIS (*((volatile unsigned int*)(0x42A7A8BCUL))) +#define bM4_PORT_PFSRH1_FSEL0 (*((volatile unsigned int*)(0x42A7A8C0UL))) +#define bM4_PORT_PFSRH1_FSEL1 (*((volatile unsigned int*)(0x42A7A8C4UL))) +#define bM4_PORT_PFSRH1_FSEL2 (*((volatile unsigned int*)(0x42A7A8C8UL))) +#define bM4_PORT_PFSRH1_FSEL3 (*((volatile unsigned int*)(0x42A7A8CCUL))) +#define bM4_PORT_PFSRH1_FSEL4 (*((volatile unsigned int*)(0x42A7A8D0UL))) +#define bM4_PORT_PFSRH1_FSEL5 (*((volatile unsigned int*)(0x42A7A8D4UL))) +#define bM4_PORT_PFSRH1_BFE (*((volatile unsigned int*)(0x42A7A8E0UL))) +#define bM4_PORT_PCRH2_POUT (*((volatile unsigned int*)(0x42A7A900UL))) +#define bM4_PORT_PCRH2_POUTE (*((volatile unsigned int*)(0x42A7A904UL))) +#define bM4_PORT_PCRH2_NOD (*((volatile unsigned int*)(0x42A7A908UL))) +#define bM4_PORT_PCRH2_DRV0 (*((volatile unsigned int*)(0x42A7A910UL))) +#define bM4_PORT_PCRH2_DRV1 (*((volatile unsigned int*)(0x42A7A914UL))) +#define bM4_PORT_PCRH2_PUU (*((volatile unsigned int*)(0x42A7A918UL))) +#define bM4_PORT_PCRH2_PIN (*((volatile unsigned int*)(0x42A7A920UL))) +#define bM4_PORT_PCRH2_INVE (*((volatile unsigned int*)(0x42A7A924UL))) +#define bM4_PORT_PCRH2_INTE (*((volatile unsigned int*)(0x42A7A930UL))) +#define bM4_PORT_PCRH2_LTE (*((volatile unsigned int*)(0x42A7A938UL))) +#define bM4_PORT_PCRH2_DDIS (*((volatile unsigned int*)(0x42A7A93CUL))) +#define bM4_PORT_PFSRH2_FSEL0 (*((volatile unsigned int*)(0x42A7A940UL))) +#define bM4_PORT_PFSRH2_FSEL1 (*((volatile unsigned int*)(0x42A7A944UL))) +#define bM4_PORT_PFSRH2_FSEL2 (*((volatile unsigned int*)(0x42A7A948UL))) +#define bM4_PORT_PFSRH2_FSEL3 (*((volatile unsigned int*)(0x42A7A94CUL))) +#define bM4_PORT_PFSRH2_FSEL4 (*((volatile unsigned int*)(0x42A7A950UL))) +#define bM4_PORT_PFSRH2_FSEL5 (*((volatile unsigned int*)(0x42A7A954UL))) +#define bM4_PORT_PFSRH2_BFE (*((volatile unsigned int*)(0x42A7A960UL))) +#define bM4_RTC_CR0_RESET (*((volatile unsigned int*)(0x42980000UL))) +#define bM4_RTC_CR1_PRDS0 (*((volatile unsigned int*)(0x42980080UL))) +#define bM4_RTC_CR1_PRDS1 (*((volatile unsigned int*)(0x42980084UL))) +#define bM4_RTC_CR1_PRDS2 (*((volatile unsigned int*)(0x42980088UL))) +#define bM4_RTC_CR1_AMPM (*((volatile unsigned int*)(0x4298008CUL))) +#define bM4_RTC_CR1_ALMFCLR (*((volatile unsigned int*)(0x42980090UL))) +#define bM4_RTC_CR1_ONEHZOE (*((volatile unsigned int*)(0x42980094UL))) +#define bM4_RTC_CR1_ONEHZSEL (*((volatile unsigned int*)(0x42980098UL))) +#define bM4_RTC_CR1_START (*((volatile unsigned int*)(0x4298009CUL))) +#define bM4_RTC_CR2_RWREQ (*((volatile unsigned int*)(0x42980100UL))) +#define bM4_RTC_CR2_RWEN (*((volatile unsigned int*)(0x42980104UL))) +#define bM4_RTC_CR2_ALMF (*((volatile unsigned int*)(0x4298010CUL))) +#define bM4_RTC_CR2_PRDIE (*((volatile unsigned int*)(0x42980114UL))) +#define bM4_RTC_CR2_ALMIE (*((volatile unsigned int*)(0x42980118UL))) +#define bM4_RTC_CR2_ALME (*((volatile unsigned int*)(0x4298011CUL))) +#define bM4_RTC_CR3_LRCEN (*((volatile unsigned int*)(0x42980190UL))) +#define bM4_RTC_CR3_RCKSEL (*((volatile unsigned int*)(0x4298019CUL))) +#define bM4_RTC_SEC_SECU0 (*((volatile unsigned int*)(0x42980200UL))) +#define bM4_RTC_SEC_SECU1 (*((volatile unsigned int*)(0x42980204UL))) +#define bM4_RTC_SEC_SECU2 (*((volatile unsigned int*)(0x42980208UL))) +#define bM4_RTC_SEC_SECU3 (*((volatile unsigned int*)(0x4298020CUL))) +#define bM4_RTC_SEC_SECD0 (*((volatile unsigned int*)(0x42980210UL))) +#define bM4_RTC_SEC_SECD1 (*((volatile unsigned int*)(0x42980214UL))) +#define bM4_RTC_SEC_SECD2 (*((volatile unsigned int*)(0x42980218UL))) +#define bM4_RTC_MIN_MINU0 (*((volatile unsigned int*)(0x42980280UL))) +#define bM4_RTC_MIN_MINU1 (*((volatile unsigned int*)(0x42980284UL))) +#define bM4_RTC_MIN_MINU2 (*((volatile unsigned int*)(0x42980288UL))) +#define bM4_RTC_MIN_MINU3 (*((volatile unsigned int*)(0x4298028CUL))) +#define bM4_RTC_MIN_MIND0 (*((volatile unsigned int*)(0x42980290UL))) +#define bM4_RTC_MIN_MIND1 (*((volatile unsigned int*)(0x42980294UL))) +#define bM4_RTC_MIN_MIND2 (*((volatile unsigned int*)(0x42980298UL))) +#define bM4_RTC_HOUR_HOURU0 (*((volatile unsigned int*)(0x42980300UL))) +#define bM4_RTC_HOUR_HOURU1 (*((volatile unsigned int*)(0x42980304UL))) +#define bM4_RTC_HOUR_HOURU2 (*((volatile unsigned int*)(0x42980308UL))) +#define bM4_RTC_HOUR_HOURU3 (*((volatile unsigned int*)(0x4298030CUL))) +#define bM4_RTC_HOUR_HOURD0 (*((volatile unsigned int*)(0x42980310UL))) +#define bM4_RTC_HOUR_HOURD1 (*((volatile unsigned int*)(0x42980314UL))) +#define bM4_RTC_WEEK_WEEK0 (*((volatile unsigned int*)(0x42980380UL))) +#define bM4_RTC_WEEK_WEEK1 (*((volatile unsigned int*)(0x42980384UL))) +#define bM4_RTC_WEEK_WEEK2 (*((volatile unsigned int*)(0x42980388UL))) +#define bM4_RTC_DAY_DAYU0 (*((volatile unsigned int*)(0x42980400UL))) +#define bM4_RTC_DAY_DAYU1 (*((volatile unsigned int*)(0x42980404UL))) +#define bM4_RTC_DAY_DAYU2 (*((volatile unsigned int*)(0x42980408UL))) +#define bM4_RTC_DAY_DAYU3 (*((volatile unsigned int*)(0x4298040CUL))) +#define bM4_RTC_DAY_DAYD0 (*((volatile unsigned int*)(0x42980410UL))) +#define bM4_RTC_DAY_DAYD1 (*((volatile unsigned int*)(0x42980414UL))) +#define bM4_RTC_MON_MON0 (*((volatile unsigned int*)(0x42980480UL))) +#define bM4_RTC_MON_MON1 (*((volatile unsigned int*)(0x42980484UL))) +#define bM4_RTC_MON_MON2 (*((volatile unsigned int*)(0x42980488UL))) +#define bM4_RTC_MON_MON3 (*((volatile unsigned int*)(0x4298048CUL))) +#define bM4_RTC_MON_MON4 (*((volatile unsigned int*)(0x42980490UL))) +#define bM4_RTC_YEAR_YEARU0 (*((volatile unsigned int*)(0x42980500UL))) +#define bM4_RTC_YEAR_YEARU1 (*((volatile unsigned int*)(0x42980504UL))) +#define bM4_RTC_YEAR_YEARU2 (*((volatile unsigned int*)(0x42980508UL))) +#define bM4_RTC_YEAR_YEARU3 (*((volatile unsigned int*)(0x4298050CUL))) +#define bM4_RTC_YEAR_YEARD0 (*((volatile unsigned int*)(0x42980510UL))) +#define bM4_RTC_YEAR_YEARD1 (*((volatile unsigned int*)(0x42980514UL))) +#define bM4_RTC_YEAR_YEARD2 (*((volatile unsigned int*)(0x42980518UL))) +#define bM4_RTC_YEAR_YEARD3 (*((volatile unsigned int*)(0x4298051CUL))) +#define bM4_RTC_ALMMIN_ALMMINU0 (*((volatile unsigned int*)(0x42980580UL))) +#define bM4_RTC_ALMMIN_ALMMINU1 (*((volatile unsigned int*)(0x42980584UL))) +#define bM4_RTC_ALMMIN_ALMMINU2 (*((volatile unsigned int*)(0x42980588UL))) +#define bM4_RTC_ALMMIN_ALMMINU3 (*((volatile unsigned int*)(0x4298058CUL))) +#define bM4_RTC_ALMMIN_ALMMIND0 (*((volatile unsigned int*)(0x42980590UL))) +#define bM4_RTC_ALMMIN_ALMMIND1 (*((volatile unsigned int*)(0x42980594UL))) +#define bM4_RTC_ALMMIN_ALMMIND2 (*((volatile unsigned int*)(0x42980598UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU0 (*((volatile unsigned int*)(0x42980600UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU1 (*((volatile unsigned int*)(0x42980604UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU2 (*((volatile unsigned int*)(0x42980608UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU3 (*((volatile unsigned int*)(0x4298060CUL))) +#define bM4_RTC_ALMHOUR_ALMHOURD0 (*((volatile unsigned int*)(0x42980610UL))) +#define bM4_RTC_ALMHOUR_ALMHOURD1 (*((volatile unsigned int*)(0x42980614UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK0 (*((volatile unsigned int*)(0x42980680UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK1 (*((volatile unsigned int*)(0x42980684UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK2 (*((volatile unsigned int*)(0x42980688UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK3 (*((volatile unsigned int*)(0x4298068CUL))) +#define bM4_RTC_ALMWEEK_ALMWEEK4 (*((volatile unsigned int*)(0x42980690UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK5 (*((volatile unsigned int*)(0x42980694UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK6 (*((volatile unsigned int*)(0x42980698UL))) +#define bM4_RTC_ERRCRH_COMP8 (*((volatile unsigned int*)(0x42980700UL))) +#define bM4_RTC_ERRCRH_COMPEN (*((volatile unsigned int*)(0x4298071CUL))) +#define bM4_RTC_ERRCRL_COMP0 (*((volatile unsigned int*)(0x42980780UL))) +#define bM4_RTC_ERRCRL_COMP1 (*((volatile unsigned int*)(0x42980784UL))) +#define bM4_RTC_ERRCRL_COMP2 (*((volatile unsigned int*)(0x42980788UL))) +#define bM4_RTC_ERRCRL_COMP3 (*((volatile unsigned int*)(0x4298078CUL))) +#define bM4_RTC_ERRCRL_COMP4 (*((volatile unsigned int*)(0x42980790UL))) +#define bM4_RTC_ERRCRL_COMP5 (*((volatile unsigned int*)(0x42980794UL))) +#define bM4_RTC_ERRCRL_COMP6 (*((volatile unsigned int*)(0x42980798UL))) +#define bM4_RTC_ERRCRL_COMP7 (*((volatile unsigned int*)(0x4298079CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42DF8080UL))) +#define bM4_SDIOC1_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42DF8084UL))) +#define bM4_SDIOC1_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42DF8088UL))) +#define bM4_SDIOC1_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42DF808CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42DF8090UL))) +#define bM4_SDIOC1_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42DF8094UL))) +#define bM4_SDIOC1_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42DF8098UL))) +#define bM4_SDIOC1_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42DF809CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42DF80A0UL))) +#define bM4_SDIOC1_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42DF80A4UL))) +#define bM4_SDIOC1_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42DF80A8UL))) +#define bM4_SDIOC1_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42DF80ACUL))) +#define bM4_SDIOC1_TRANSMODE_BCE (*((volatile unsigned int*)(0x42DF8184UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42DF8188UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42DF818CUL))) +#define bM4_SDIOC1_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42DF8190UL))) +#define bM4_SDIOC1_TRANSMODE_MULB (*((volatile unsigned int*)(0x42DF8194UL))) +#define bM4_SDIOC1_CMD_RESTYP0 (*((volatile unsigned int*)(0x42DF81C0UL))) +#define bM4_SDIOC1_CMD_RESTYP1 (*((volatile unsigned int*)(0x42DF81C4UL))) +#define bM4_SDIOC1_CMD_CCE (*((volatile unsigned int*)(0x42DF81CCUL))) +#define bM4_SDIOC1_CMD_ICE (*((volatile unsigned int*)(0x42DF81D0UL))) +#define bM4_SDIOC1_CMD_DAT (*((volatile unsigned int*)(0x42DF81D4UL))) +#define bM4_SDIOC1_CMD_TYP0 (*((volatile unsigned int*)(0x42DF81D8UL))) +#define bM4_SDIOC1_CMD_TYP1 (*((volatile unsigned int*)(0x42DF81DCUL))) +#define bM4_SDIOC1_CMD_IDX0 (*((volatile unsigned int*)(0x42DF81E0UL))) +#define bM4_SDIOC1_CMD_IDX1 (*((volatile unsigned int*)(0x42DF81E4UL))) +#define bM4_SDIOC1_CMD_IDX2 (*((volatile unsigned int*)(0x42DF81E8UL))) +#define bM4_SDIOC1_CMD_IDX3 (*((volatile unsigned int*)(0x42DF81ECUL))) +#define bM4_SDIOC1_CMD_IDX4 (*((volatile unsigned int*)(0x42DF81F0UL))) +#define bM4_SDIOC1_CMD_IDX5 (*((volatile unsigned int*)(0x42DF81F4UL))) +#define bM4_SDIOC1_PSTAT_CIC (*((volatile unsigned int*)(0x42DF8480UL))) +#define bM4_SDIOC1_PSTAT_CID (*((volatile unsigned int*)(0x42DF8484UL))) +#define bM4_SDIOC1_PSTAT_DA (*((volatile unsigned int*)(0x42DF8488UL))) +#define bM4_SDIOC1_PSTAT_WTA (*((volatile unsigned int*)(0x42DF84A0UL))) +#define bM4_SDIOC1_PSTAT_RTA (*((volatile unsigned int*)(0x42DF84A4UL))) +#define bM4_SDIOC1_PSTAT_BWE (*((volatile unsigned int*)(0x42DF84A8UL))) +#define bM4_SDIOC1_PSTAT_BRE (*((volatile unsigned int*)(0x42DF84ACUL))) +#define bM4_SDIOC1_PSTAT_CIN (*((volatile unsigned int*)(0x42DF84C0UL))) +#define bM4_SDIOC1_PSTAT_CSS (*((volatile unsigned int*)(0x42DF84C4UL))) +#define bM4_SDIOC1_PSTAT_CDL (*((volatile unsigned int*)(0x42DF84C8UL))) +#define bM4_SDIOC1_PSTAT_WPL (*((volatile unsigned int*)(0x42DF84CCUL))) +#define bM4_SDIOC1_PSTAT_DATL0 (*((volatile unsigned int*)(0x42DF84D0UL))) +#define bM4_SDIOC1_PSTAT_DATL1 (*((volatile unsigned int*)(0x42DF84D4UL))) +#define bM4_SDIOC1_PSTAT_DATL2 (*((volatile unsigned int*)(0x42DF84D8UL))) +#define bM4_SDIOC1_PSTAT_DATL3 (*((volatile unsigned int*)(0x42DF84DCUL))) +#define bM4_SDIOC1_PSTAT_CMDL (*((volatile unsigned int*)(0x42DF84E0UL))) +#define bM4_SDIOC1_HOSTCON_DW (*((volatile unsigned int*)(0x42DF8504UL))) +#define bM4_SDIOC1_HOSTCON_HSEN (*((volatile unsigned int*)(0x42DF8508UL))) +#define bM4_SDIOC1_HOSTCON_EXDW (*((volatile unsigned int*)(0x42DF8514UL))) +#define bM4_SDIOC1_HOSTCON_CDTL (*((volatile unsigned int*)(0x42DF8518UL))) +#define bM4_SDIOC1_HOSTCON_CDSS (*((volatile unsigned int*)(0x42DF851CUL))) +#define bM4_SDIOC1_PWRCON_PWON (*((volatile unsigned int*)(0x42DF8520UL))) +#define bM4_SDIOC1_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42DF8540UL))) +#define bM4_SDIOC1_BLKGPCON_CR (*((volatile unsigned int*)(0x42DF8544UL))) +#define bM4_SDIOC1_BLKGPCON_RWC (*((volatile unsigned int*)(0x42DF8548UL))) +#define bM4_SDIOC1_BLKGPCON_IABG (*((volatile unsigned int*)(0x42DF854CUL))) +#define bM4_SDIOC1_CLKCON_ICE (*((volatile unsigned int*)(0x42DF8580UL))) +#define bM4_SDIOC1_CLKCON_CE (*((volatile unsigned int*)(0x42DF8588UL))) +#define bM4_SDIOC1_CLKCON_FS0 (*((volatile unsigned int*)(0x42DF85A0UL))) +#define bM4_SDIOC1_CLKCON_FS1 (*((volatile unsigned int*)(0x42DF85A4UL))) +#define bM4_SDIOC1_CLKCON_FS2 (*((volatile unsigned int*)(0x42DF85A8UL))) +#define bM4_SDIOC1_CLKCON_FS3 (*((volatile unsigned int*)(0x42DF85ACUL))) +#define bM4_SDIOC1_CLKCON_FS4 (*((volatile unsigned int*)(0x42DF85B0UL))) +#define bM4_SDIOC1_CLKCON_FS5 (*((volatile unsigned int*)(0x42DF85B4UL))) +#define bM4_SDIOC1_CLKCON_FS6 (*((volatile unsigned int*)(0x42DF85B8UL))) +#define bM4_SDIOC1_CLKCON_FS7 (*((volatile unsigned int*)(0x42DF85BCUL))) +#define bM4_SDIOC1_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42DF85C0UL))) +#define bM4_SDIOC1_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42DF85C4UL))) +#define bM4_SDIOC1_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42DF85C8UL))) +#define bM4_SDIOC1_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42DF85CCUL))) +#define bM4_SDIOC1_SFTRST_RSTA (*((volatile unsigned int*)(0x42DF85E0UL))) +#define bM4_SDIOC1_SFTRST_RSTC (*((volatile unsigned int*)(0x42DF85E4UL))) +#define bM4_SDIOC1_SFTRST_RSTD (*((volatile unsigned int*)(0x42DF85E8UL))) +#define bM4_SDIOC1_NORINTST_CC (*((volatile unsigned int*)(0x42DF8600UL))) +#define bM4_SDIOC1_NORINTST_TC (*((volatile unsigned int*)(0x42DF8604UL))) +#define bM4_SDIOC1_NORINTST_BGE (*((volatile unsigned int*)(0x42DF8608UL))) +#define bM4_SDIOC1_NORINTST_BWR (*((volatile unsigned int*)(0x42DF8610UL))) +#define bM4_SDIOC1_NORINTST_BRR (*((volatile unsigned int*)(0x42DF8614UL))) +#define bM4_SDIOC1_NORINTST_CIST (*((volatile unsigned int*)(0x42DF8618UL))) +#define bM4_SDIOC1_NORINTST_CRM (*((volatile unsigned int*)(0x42DF861CUL))) +#define bM4_SDIOC1_NORINTST_CINT (*((volatile unsigned int*)(0x42DF8620UL))) +#define bM4_SDIOC1_NORINTST_EI (*((volatile unsigned int*)(0x42DF863CUL))) +#define bM4_SDIOC1_ERRINTST_CTOE (*((volatile unsigned int*)(0x42DF8640UL))) +#define bM4_SDIOC1_ERRINTST_CCE (*((volatile unsigned int*)(0x42DF8644UL))) +#define bM4_SDIOC1_ERRINTST_CEBE (*((volatile unsigned int*)(0x42DF8648UL))) +#define bM4_SDIOC1_ERRINTST_CIE (*((volatile unsigned int*)(0x42DF864CUL))) +#define bM4_SDIOC1_ERRINTST_DTOE (*((volatile unsigned int*)(0x42DF8650UL))) +#define bM4_SDIOC1_ERRINTST_DCE (*((volatile unsigned int*)(0x42DF8654UL))) +#define bM4_SDIOC1_ERRINTST_DEBE (*((volatile unsigned int*)(0x42DF8658UL))) +#define bM4_SDIOC1_ERRINTST_ACE (*((volatile unsigned int*)(0x42DF8660UL))) +#define bM4_SDIOC1_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42DF8680UL))) +#define bM4_SDIOC1_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42DF8684UL))) +#define bM4_SDIOC1_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42DF8688UL))) +#define bM4_SDIOC1_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42DF8690UL))) +#define bM4_SDIOC1_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42DF8694UL))) +#define bM4_SDIOC1_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42DF8698UL))) +#define bM4_SDIOC1_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42DF869CUL))) +#define bM4_SDIOC1_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42DF86A0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42DF86C0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42DF86C4UL))) +#define bM4_SDIOC1_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42DF86C8UL))) +#define bM4_SDIOC1_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42DF86CCUL))) +#define bM4_SDIOC1_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42DF86D0UL))) +#define bM4_SDIOC1_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42DF86D4UL))) +#define bM4_SDIOC1_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42DF86D8UL))) +#define bM4_SDIOC1_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42DF86E0UL))) +#define bM4_SDIOC1_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42DF8700UL))) +#define bM4_SDIOC1_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42DF8704UL))) +#define bM4_SDIOC1_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42DF8708UL))) +#define bM4_SDIOC1_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42DF8710UL))) +#define bM4_SDIOC1_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42DF8714UL))) +#define bM4_SDIOC1_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42DF8718UL))) +#define bM4_SDIOC1_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42DF871CUL))) +#define bM4_SDIOC1_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42DF8720UL))) +#define bM4_SDIOC1_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42DF8740UL))) +#define bM4_SDIOC1_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42DF8744UL))) +#define bM4_SDIOC1_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42DF8748UL))) +#define bM4_SDIOC1_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42DF874CUL))) +#define bM4_SDIOC1_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42DF8750UL))) +#define bM4_SDIOC1_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42DF8754UL))) +#define bM4_SDIOC1_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42DF8758UL))) +#define bM4_SDIOC1_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42DF8760UL))) +#define bM4_SDIOC1_ATCERRST_NE (*((volatile unsigned int*)(0x42DF8780UL))) +#define bM4_SDIOC1_ATCERRST_TOE (*((volatile unsigned int*)(0x42DF8784UL))) +#define bM4_SDIOC1_ATCERRST_CE (*((volatile unsigned int*)(0x42DF8788UL))) +#define bM4_SDIOC1_ATCERRST_EBE (*((volatile unsigned int*)(0x42DF878CUL))) +#define bM4_SDIOC1_ATCERRST_IE (*((volatile unsigned int*)(0x42DF8790UL))) +#define bM4_SDIOC1_ATCERRST_CMDE (*((volatile unsigned int*)(0x42DF879CUL))) +#define bM4_SDIOC1_FEA_FNE (*((volatile unsigned int*)(0x42DF8A00UL))) +#define bM4_SDIOC1_FEA_FTOE (*((volatile unsigned int*)(0x42DF8A04UL))) +#define bM4_SDIOC1_FEA_FCE (*((volatile unsigned int*)(0x42DF8A08UL))) +#define bM4_SDIOC1_FEA_FEBE (*((volatile unsigned int*)(0x42DF8A0CUL))) +#define bM4_SDIOC1_FEA_FIE (*((volatile unsigned int*)(0x42DF8A10UL))) +#define bM4_SDIOC1_FEA_FCMDE (*((volatile unsigned int*)(0x42DF8A1CUL))) +#define bM4_SDIOC1_FEE_FCTOE (*((volatile unsigned int*)(0x42DF8A40UL))) +#define bM4_SDIOC1_FEE_FCCE (*((volatile unsigned int*)(0x42DF8A44UL))) +#define bM4_SDIOC1_FEE_FCEBE (*((volatile unsigned int*)(0x42DF8A48UL))) +#define bM4_SDIOC1_FEE_FCIE (*((volatile unsigned int*)(0x42DF8A4CUL))) +#define bM4_SDIOC1_FEE_FDTOE (*((volatile unsigned int*)(0x42DF8A50UL))) +#define bM4_SDIOC1_FEE_FDCE (*((volatile unsigned int*)(0x42DF8A54UL))) +#define bM4_SDIOC1_FEE_FDEBE (*((volatile unsigned int*)(0x42DF8A58UL))) +#define bM4_SDIOC1_FEE_FACE (*((volatile unsigned int*)(0x42DF8A60UL))) +#define bM4_SDIOC2_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42E00080UL))) +#define bM4_SDIOC2_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42E00084UL))) +#define bM4_SDIOC2_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42E00088UL))) +#define bM4_SDIOC2_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42E0008CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42E00090UL))) +#define bM4_SDIOC2_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42E00094UL))) +#define bM4_SDIOC2_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42E00098UL))) +#define bM4_SDIOC2_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42E0009CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42E000A0UL))) +#define bM4_SDIOC2_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42E000A4UL))) +#define bM4_SDIOC2_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42E000A8UL))) +#define bM4_SDIOC2_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42E000ACUL))) +#define bM4_SDIOC2_TRANSMODE_BCE (*((volatile unsigned int*)(0x42E00184UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42E00188UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42E0018CUL))) +#define bM4_SDIOC2_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42E00190UL))) +#define bM4_SDIOC2_TRANSMODE_MULB (*((volatile unsigned int*)(0x42E00194UL))) +#define bM4_SDIOC2_CMD_RESTYP0 (*((volatile unsigned int*)(0x42E001C0UL))) +#define bM4_SDIOC2_CMD_RESTYP1 (*((volatile unsigned int*)(0x42E001C4UL))) +#define bM4_SDIOC2_CMD_CCE (*((volatile unsigned int*)(0x42E001CCUL))) +#define bM4_SDIOC2_CMD_ICE (*((volatile unsigned int*)(0x42E001D0UL))) +#define bM4_SDIOC2_CMD_DAT (*((volatile unsigned int*)(0x42E001D4UL))) +#define bM4_SDIOC2_CMD_TYP0 (*((volatile unsigned int*)(0x42E001D8UL))) +#define bM4_SDIOC2_CMD_TYP1 (*((volatile unsigned int*)(0x42E001DCUL))) +#define bM4_SDIOC2_CMD_IDX0 (*((volatile unsigned int*)(0x42E001E0UL))) +#define bM4_SDIOC2_CMD_IDX1 (*((volatile unsigned int*)(0x42E001E4UL))) +#define bM4_SDIOC2_CMD_IDX2 (*((volatile unsigned int*)(0x42E001E8UL))) +#define bM4_SDIOC2_CMD_IDX3 (*((volatile unsigned int*)(0x42E001ECUL))) +#define bM4_SDIOC2_CMD_IDX4 (*((volatile unsigned int*)(0x42E001F0UL))) +#define bM4_SDIOC2_CMD_IDX5 (*((volatile unsigned int*)(0x42E001F4UL))) +#define bM4_SDIOC2_PSTAT_CIC (*((volatile unsigned int*)(0x42E00480UL))) +#define bM4_SDIOC2_PSTAT_CID (*((volatile unsigned int*)(0x42E00484UL))) +#define bM4_SDIOC2_PSTAT_DA (*((volatile unsigned int*)(0x42E00488UL))) +#define bM4_SDIOC2_PSTAT_WTA (*((volatile unsigned int*)(0x42E004A0UL))) +#define bM4_SDIOC2_PSTAT_RTA (*((volatile unsigned int*)(0x42E004A4UL))) +#define bM4_SDIOC2_PSTAT_BWE (*((volatile unsigned int*)(0x42E004A8UL))) +#define bM4_SDIOC2_PSTAT_BRE (*((volatile unsigned int*)(0x42E004ACUL))) +#define bM4_SDIOC2_PSTAT_CIN (*((volatile unsigned int*)(0x42E004C0UL))) +#define bM4_SDIOC2_PSTAT_CSS (*((volatile unsigned int*)(0x42E004C4UL))) +#define bM4_SDIOC2_PSTAT_CDL (*((volatile unsigned int*)(0x42E004C8UL))) +#define bM4_SDIOC2_PSTAT_WPL (*((volatile unsigned int*)(0x42E004CCUL))) +#define bM4_SDIOC2_PSTAT_DATL0 (*((volatile unsigned int*)(0x42E004D0UL))) +#define bM4_SDIOC2_PSTAT_DATL1 (*((volatile unsigned int*)(0x42E004D4UL))) +#define bM4_SDIOC2_PSTAT_DATL2 (*((volatile unsigned int*)(0x42E004D8UL))) +#define bM4_SDIOC2_PSTAT_DATL3 (*((volatile unsigned int*)(0x42E004DCUL))) +#define bM4_SDIOC2_PSTAT_CMDL (*((volatile unsigned int*)(0x42E004E0UL))) +#define bM4_SDIOC2_HOSTCON_DW (*((volatile unsigned int*)(0x42E00504UL))) +#define bM4_SDIOC2_HOSTCON_HSEN (*((volatile unsigned int*)(0x42E00508UL))) +#define bM4_SDIOC2_HOSTCON_EXDW (*((volatile unsigned int*)(0x42E00514UL))) +#define bM4_SDIOC2_HOSTCON_CDTL (*((volatile unsigned int*)(0x42E00518UL))) +#define bM4_SDIOC2_HOSTCON_CDSS (*((volatile unsigned int*)(0x42E0051CUL))) +#define bM4_SDIOC2_PWRCON_PWON (*((volatile unsigned int*)(0x42E00520UL))) +#define bM4_SDIOC2_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42E00540UL))) +#define bM4_SDIOC2_BLKGPCON_CR (*((volatile unsigned int*)(0x42E00544UL))) +#define bM4_SDIOC2_BLKGPCON_RWC (*((volatile unsigned int*)(0x42E00548UL))) +#define bM4_SDIOC2_BLKGPCON_IABG (*((volatile unsigned int*)(0x42E0054CUL))) +#define bM4_SDIOC2_CLKCON_ICE (*((volatile unsigned int*)(0x42E00580UL))) +#define bM4_SDIOC2_CLKCON_CE (*((volatile unsigned int*)(0x42E00588UL))) +#define bM4_SDIOC2_CLKCON_FS0 (*((volatile unsigned int*)(0x42E005A0UL))) +#define bM4_SDIOC2_CLKCON_FS1 (*((volatile unsigned int*)(0x42E005A4UL))) +#define bM4_SDIOC2_CLKCON_FS2 (*((volatile unsigned int*)(0x42E005A8UL))) +#define bM4_SDIOC2_CLKCON_FS3 (*((volatile unsigned int*)(0x42E005ACUL))) +#define bM4_SDIOC2_CLKCON_FS4 (*((volatile unsigned int*)(0x42E005B0UL))) +#define bM4_SDIOC2_CLKCON_FS5 (*((volatile unsigned int*)(0x42E005B4UL))) +#define bM4_SDIOC2_CLKCON_FS6 (*((volatile unsigned int*)(0x42E005B8UL))) +#define bM4_SDIOC2_CLKCON_FS7 (*((volatile unsigned int*)(0x42E005BCUL))) +#define bM4_SDIOC2_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42E005C0UL))) +#define bM4_SDIOC2_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42E005C4UL))) +#define bM4_SDIOC2_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42E005C8UL))) +#define bM4_SDIOC2_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42E005CCUL))) +#define bM4_SDIOC2_SFTRST_RSTA (*((volatile unsigned int*)(0x42E005E0UL))) +#define bM4_SDIOC2_SFTRST_RSTC (*((volatile unsigned int*)(0x42E005E4UL))) +#define bM4_SDIOC2_SFTRST_RSTD (*((volatile unsigned int*)(0x42E005E8UL))) +#define bM4_SDIOC2_NORINTST_CC (*((volatile unsigned int*)(0x42E00600UL))) +#define bM4_SDIOC2_NORINTST_TC (*((volatile unsigned int*)(0x42E00604UL))) +#define bM4_SDIOC2_NORINTST_BGE (*((volatile unsigned int*)(0x42E00608UL))) +#define bM4_SDIOC2_NORINTST_BWR (*((volatile unsigned int*)(0x42E00610UL))) +#define bM4_SDIOC2_NORINTST_BRR (*((volatile unsigned int*)(0x42E00614UL))) +#define bM4_SDIOC2_NORINTST_CIST (*((volatile unsigned int*)(0x42E00618UL))) +#define bM4_SDIOC2_NORINTST_CRM (*((volatile unsigned int*)(0x42E0061CUL))) +#define bM4_SDIOC2_NORINTST_CINT (*((volatile unsigned int*)(0x42E00620UL))) +#define bM4_SDIOC2_NORINTST_EI (*((volatile unsigned int*)(0x42E0063CUL))) +#define bM4_SDIOC2_ERRINTST_CTOE (*((volatile unsigned int*)(0x42E00640UL))) +#define bM4_SDIOC2_ERRINTST_CCE (*((volatile unsigned int*)(0x42E00644UL))) +#define bM4_SDIOC2_ERRINTST_CEBE (*((volatile unsigned int*)(0x42E00648UL))) +#define bM4_SDIOC2_ERRINTST_CIE (*((volatile unsigned int*)(0x42E0064CUL))) +#define bM4_SDIOC2_ERRINTST_DTOE (*((volatile unsigned int*)(0x42E00650UL))) +#define bM4_SDIOC2_ERRINTST_DCE (*((volatile unsigned int*)(0x42E00654UL))) +#define bM4_SDIOC2_ERRINTST_DEBE (*((volatile unsigned int*)(0x42E00658UL))) +#define bM4_SDIOC2_ERRINTST_ACE (*((volatile unsigned int*)(0x42E00660UL))) +#define bM4_SDIOC2_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42E00680UL))) +#define bM4_SDIOC2_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42E00684UL))) +#define bM4_SDIOC2_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42E00688UL))) +#define bM4_SDIOC2_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42E00690UL))) +#define bM4_SDIOC2_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42E00694UL))) +#define bM4_SDIOC2_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42E00698UL))) +#define bM4_SDIOC2_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42E0069CUL))) +#define bM4_SDIOC2_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42E006A0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42E006C0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42E006C4UL))) +#define bM4_SDIOC2_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42E006C8UL))) +#define bM4_SDIOC2_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42E006CCUL))) +#define bM4_SDIOC2_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42E006D0UL))) +#define bM4_SDIOC2_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42E006D4UL))) +#define bM4_SDIOC2_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42E006D8UL))) +#define bM4_SDIOC2_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42E006E0UL))) +#define bM4_SDIOC2_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42E00700UL))) +#define bM4_SDIOC2_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42E00704UL))) +#define bM4_SDIOC2_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42E00708UL))) +#define bM4_SDIOC2_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42E00710UL))) +#define bM4_SDIOC2_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42E00714UL))) +#define bM4_SDIOC2_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42E00718UL))) +#define bM4_SDIOC2_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42E0071CUL))) +#define bM4_SDIOC2_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42E00720UL))) +#define bM4_SDIOC2_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42E00740UL))) +#define bM4_SDIOC2_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42E00744UL))) +#define bM4_SDIOC2_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42E00748UL))) +#define bM4_SDIOC2_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42E0074CUL))) +#define bM4_SDIOC2_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42E00750UL))) +#define bM4_SDIOC2_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42E00754UL))) +#define bM4_SDIOC2_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42E00758UL))) +#define bM4_SDIOC2_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42E00760UL))) +#define bM4_SDIOC2_ATCERRST_NE (*((volatile unsigned int*)(0x42E00780UL))) +#define bM4_SDIOC2_ATCERRST_TOE (*((volatile unsigned int*)(0x42E00784UL))) +#define bM4_SDIOC2_ATCERRST_CE (*((volatile unsigned int*)(0x42E00788UL))) +#define bM4_SDIOC2_ATCERRST_EBE (*((volatile unsigned int*)(0x42E0078CUL))) +#define bM4_SDIOC2_ATCERRST_IE (*((volatile unsigned int*)(0x42E00790UL))) +#define bM4_SDIOC2_ATCERRST_CMDE (*((volatile unsigned int*)(0x42E0079CUL))) +#define bM4_SDIOC2_FEA_FNE (*((volatile unsigned int*)(0x42E00A00UL))) +#define bM4_SDIOC2_FEA_FTOE (*((volatile unsigned int*)(0x42E00A04UL))) +#define bM4_SDIOC2_FEA_FCE (*((volatile unsigned int*)(0x42E00A08UL))) +#define bM4_SDIOC2_FEA_FEBE (*((volatile unsigned int*)(0x42E00A0CUL))) +#define bM4_SDIOC2_FEA_FIE (*((volatile unsigned int*)(0x42E00A10UL))) +#define bM4_SDIOC2_FEA_FCMDE (*((volatile unsigned int*)(0x42E00A1CUL))) +#define bM4_SDIOC2_FEE_FCTOE (*((volatile unsigned int*)(0x42E00A40UL))) +#define bM4_SDIOC2_FEE_FCCE (*((volatile unsigned int*)(0x42E00A44UL))) +#define bM4_SDIOC2_FEE_FCEBE (*((volatile unsigned int*)(0x42E00A48UL))) +#define bM4_SDIOC2_FEE_FCIE (*((volatile unsigned int*)(0x42E00A4CUL))) +#define bM4_SDIOC2_FEE_FDTOE (*((volatile unsigned int*)(0x42E00A50UL))) +#define bM4_SDIOC2_FEE_FDCE (*((volatile unsigned int*)(0x42E00A54UL))) +#define bM4_SDIOC2_FEE_FDEBE (*((volatile unsigned int*)(0x42E00A58UL))) +#define bM4_SDIOC2_FEE_FACE (*((volatile unsigned int*)(0x42E00A60UL))) +#define bM4_SPI1_CR1_SPIMDS (*((volatile unsigned int*)(0x42380080UL))) +#define bM4_SPI1_CR1_TXMDS (*((volatile unsigned int*)(0x42380084UL))) +#define bM4_SPI1_CR1_MSTR (*((volatile unsigned int*)(0x4238008CUL))) +#define bM4_SPI1_CR1_SPLPBK (*((volatile unsigned int*)(0x42380090UL))) +#define bM4_SPI1_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42380094UL))) +#define bM4_SPI1_CR1_SPE (*((volatile unsigned int*)(0x42380098UL))) +#define bM4_SPI1_CR1_CSUSPE (*((volatile unsigned int*)(0x4238009CUL))) +#define bM4_SPI1_CR1_EIE (*((volatile unsigned int*)(0x423800A0UL))) +#define bM4_SPI1_CR1_TXIE (*((volatile unsigned int*)(0x423800A4UL))) +#define bM4_SPI1_CR1_RXIE (*((volatile unsigned int*)(0x423800A8UL))) +#define bM4_SPI1_CR1_IDIE (*((volatile unsigned int*)(0x423800ACUL))) +#define bM4_SPI1_CR1_MODFE (*((volatile unsigned int*)(0x423800B0UL))) +#define bM4_SPI1_CR1_PATE (*((volatile unsigned int*)(0x423800B4UL))) +#define bM4_SPI1_CR1_PAOE (*((volatile unsigned int*)(0x423800B8UL))) +#define bM4_SPI1_CR1_PAE (*((volatile unsigned int*)(0x423800BCUL))) +#define bM4_SPI1_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42380180UL))) +#define bM4_SPI1_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42380184UL))) +#define bM4_SPI1_CFG1_SPRDTD (*((volatile unsigned int*)(0x42380198UL))) +#define bM4_SPI1_CFG1_SS0PV (*((volatile unsigned int*)(0x423801A0UL))) +#define bM4_SPI1_CFG1_SS1PV (*((volatile unsigned int*)(0x423801A4UL))) +#define bM4_SPI1_CFG1_SS2PV (*((volatile unsigned int*)(0x423801A8UL))) +#define bM4_SPI1_CFG1_SS3PV (*((volatile unsigned int*)(0x423801ACUL))) +#define bM4_SPI1_CFG1_MSSI0 (*((volatile unsigned int*)(0x423801D0UL))) +#define bM4_SPI1_CFG1_MSSI1 (*((volatile unsigned int*)(0x423801D4UL))) +#define bM4_SPI1_CFG1_MSSI2 (*((volatile unsigned int*)(0x423801D8UL))) +#define bM4_SPI1_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423801E0UL))) +#define bM4_SPI1_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423801E4UL))) +#define bM4_SPI1_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423801E8UL))) +#define bM4_SPI1_CFG1_MIDI0 (*((volatile unsigned int*)(0x423801F0UL))) +#define bM4_SPI1_CFG1_MIDI1 (*((volatile unsigned int*)(0x423801F4UL))) +#define bM4_SPI1_CFG1_MIDI2 (*((volatile unsigned int*)(0x423801F8UL))) +#define bM4_SPI1_SR_OVRERF (*((volatile unsigned int*)(0x42380280UL))) +#define bM4_SPI1_SR_IDLNF (*((volatile unsigned int*)(0x42380284UL))) +#define bM4_SPI1_SR_MODFERF (*((volatile unsigned int*)(0x42380288UL))) +#define bM4_SPI1_SR_PERF (*((volatile unsigned int*)(0x4238028CUL))) +#define bM4_SPI1_SR_UDRERF (*((volatile unsigned int*)(0x42380290UL))) +#define bM4_SPI1_SR_TDEF (*((volatile unsigned int*)(0x42380294UL))) +#define bM4_SPI1_SR_RDFF (*((volatile unsigned int*)(0x4238029CUL))) +#define bM4_SPI1_CFG2_CPHA (*((volatile unsigned int*)(0x42380300UL))) +#define bM4_SPI1_CFG2_CPOL (*((volatile unsigned int*)(0x42380304UL))) +#define bM4_SPI1_CFG2_MBR0 (*((volatile unsigned int*)(0x42380308UL))) +#define bM4_SPI1_CFG2_MBR1 (*((volatile unsigned int*)(0x4238030CUL))) +#define bM4_SPI1_CFG2_MBR2 (*((volatile unsigned int*)(0x42380310UL))) +#define bM4_SPI1_CFG2_SSA0 (*((volatile unsigned int*)(0x42380314UL))) +#define bM4_SPI1_CFG2_SSA1 (*((volatile unsigned int*)(0x42380318UL))) +#define bM4_SPI1_CFG2_SSA2 (*((volatile unsigned int*)(0x4238031CUL))) +#define bM4_SPI1_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42380320UL))) +#define bM4_SPI1_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42380324UL))) +#define bM4_SPI1_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42380328UL))) +#define bM4_SPI1_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238032CUL))) +#define bM4_SPI1_CFG2_LSBF (*((volatile unsigned int*)(0x42380330UL))) +#define bM4_SPI1_CFG2_MIDIE (*((volatile unsigned int*)(0x42380334UL))) +#define bM4_SPI1_CFG2_MSSDLE (*((volatile unsigned int*)(0x42380338UL))) +#define bM4_SPI1_CFG2_MSSIE (*((volatile unsigned int*)(0x4238033CUL))) +#define bM4_SPI2_CR1_SPIMDS (*((volatile unsigned int*)(0x42388080UL))) +#define bM4_SPI2_CR1_TXMDS (*((volatile unsigned int*)(0x42388084UL))) +#define bM4_SPI2_CR1_MSTR (*((volatile unsigned int*)(0x4238808CUL))) +#define bM4_SPI2_CR1_SPLPBK (*((volatile unsigned int*)(0x42388090UL))) +#define bM4_SPI2_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42388094UL))) +#define bM4_SPI2_CR1_SPE (*((volatile unsigned int*)(0x42388098UL))) +#define bM4_SPI2_CR1_CSUSPE (*((volatile unsigned int*)(0x4238809CUL))) +#define bM4_SPI2_CR1_EIE (*((volatile unsigned int*)(0x423880A0UL))) +#define bM4_SPI2_CR1_TXIE (*((volatile unsigned int*)(0x423880A4UL))) +#define bM4_SPI2_CR1_RXIE (*((volatile unsigned int*)(0x423880A8UL))) +#define bM4_SPI2_CR1_IDIE (*((volatile unsigned int*)(0x423880ACUL))) +#define bM4_SPI2_CR1_MODFE (*((volatile unsigned int*)(0x423880B0UL))) +#define bM4_SPI2_CR1_PATE (*((volatile unsigned int*)(0x423880B4UL))) +#define bM4_SPI2_CR1_PAOE (*((volatile unsigned int*)(0x423880B8UL))) +#define bM4_SPI2_CR1_PAE (*((volatile unsigned int*)(0x423880BCUL))) +#define bM4_SPI2_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42388180UL))) +#define bM4_SPI2_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42388184UL))) +#define bM4_SPI2_CFG1_SPRDTD (*((volatile unsigned int*)(0x42388198UL))) +#define bM4_SPI2_CFG1_SS0PV (*((volatile unsigned int*)(0x423881A0UL))) +#define bM4_SPI2_CFG1_SS1PV (*((volatile unsigned int*)(0x423881A4UL))) +#define bM4_SPI2_CFG1_SS2PV (*((volatile unsigned int*)(0x423881A8UL))) +#define bM4_SPI2_CFG1_SS3PV (*((volatile unsigned int*)(0x423881ACUL))) +#define bM4_SPI2_CFG1_MSSI0 (*((volatile unsigned int*)(0x423881D0UL))) +#define bM4_SPI2_CFG1_MSSI1 (*((volatile unsigned int*)(0x423881D4UL))) +#define bM4_SPI2_CFG1_MSSI2 (*((volatile unsigned int*)(0x423881D8UL))) +#define bM4_SPI2_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423881E0UL))) +#define bM4_SPI2_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423881E4UL))) +#define bM4_SPI2_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423881E8UL))) +#define bM4_SPI2_CFG1_MIDI0 (*((volatile unsigned int*)(0x423881F0UL))) +#define bM4_SPI2_CFG1_MIDI1 (*((volatile unsigned int*)(0x423881F4UL))) +#define bM4_SPI2_CFG1_MIDI2 (*((volatile unsigned int*)(0x423881F8UL))) +#define bM4_SPI2_SR_OVRERF (*((volatile unsigned int*)(0x42388280UL))) +#define bM4_SPI2_SR_IDLNF (*((volatile unsigned int*)(0x42388284UL))) +#define bM4_SPI2_SR_MODFERF (*((volatile unsigned int*)(0x42388288UL))) +#define bM4_SPI2_SR_PERF (*((volatile unsigned int*)(0x4238828CUL))) +#define bM4_SPI2_SR_UDRERF (*((volatile unsigned int*)(0x42388290UL))) +#define bM4_SPI2_SR_TDEF (*((volatile unsigned int*)(0x42388294UL))) +#define bM4_SPI2_SR_RDFF (*((volatile unsigned int*)(0x4238829CUL))) +#define bM4_SPI2_CFG2_CPHA (*((volatile unsigned int*)(0x42388300UL))) +#define bM4_SPI2_CFG2_CPOL (*((volatile unsigned int*)(0x42388304UL))) +#define bM4_SPI2_CFG2_MBR0 (*((volatile unsigned int*)(0x42388308UL))) +#define bM4_SPI2_CFG2_MBR1 (*((volatile unsigned int*)(0x4238830CUL))) +#define bM4_SPI2_CFG2_MBR2 (*((volatile unsigned int*)(0x42388310UL))) +#define bM4_SPI2_CFG2_SSA0 (*((volatile unsigned int*)(0x42388314UL))) +#define bM4_SPI2_CFG2_SSA1 (*((volatile unsigned int*)(0x42388318UL))) +#define bM4_SPI2_CFG2_SSA2 (*((volatile unsigned int*)(0x4238831CUL))) +#define bM4_SPI2_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42388320UL))) +#define bM4_SPI2_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42388324UL))) +#define bM4_SPI2_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42388328UL))) +#define bM4_SPI2_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238832CUL))) +#define bM4_SPI2_CFG2_LSBF (*((volatile unsigned int*)(0x42388330UL))) +#define bM4_SPI2_CFG2_MIDIE (*((volatile unsigned int*)(0x42388334UL))) +#define bM4_SPI2_CFG2_MSSDLE (*((volatile unsigned int*)(0x42388338UL))) +#define bM4_SPI2_CFG2_MSSIE (*((volatile unsigned int*)(0x4238833CUL))) +#define bM4_SPI3_CR1_SPIMDS (*((volatile unsigned int*)(0x42400080UL))) +#define bM4_SPI3_CR1_TXMDS (*((volatile unsigned int*)(0x42400084UL))) +#define bM4_SPI3_CR1_MSTR (*((volatile unsigned int*)(0x4240008CUL))) +#define bM4_SPI3_CR1_SPLPBK (*((volatile unsigned int*)(0x42400090UL))) +#define bM4_SPI3_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42400094UL))) +#define bM4_SPI3_CR1_SPE (*((volatile unsigned int*)(0x42400098UL))) +#define bM4_SPI3_CR1_CSUSPE (*((volatile unsigned int*)(0x4240009CUL))) +#define bM4_SPI3_CR1_EIE (*((volatile unsigned int*)(0x424000A0UL))) +#define bM4_SPI3_CR1_TXIE (*((volatile unsigned int*)(0x424000A4UL))) +#define bM4_SPI3_CR1_RXIE (*((volatile unsigned int*)(0x424000A8UL))) +#define bM4_SPI3_CR1_IDIE (*((volatile unsigned int*)(0x424000ACUL))) +#define bM4_SPI3_CR1_MODFE (*((volatile unsigned int*)(0x424000B0UL))) +#define bM4_SPI3_CR1_PATE (*((volatile unsigned int*)(0x424000B4UL))) +#define bM4_SPI3_CR1_PAOE (*((volatile unsigned int*)(0x424000B8UL))) +#define bM4_SPI3_CR1_PAE (*((volatile unsigned int*)(0x424000BCUL))) +#define bM4_SPI3_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42400180UL))) +#define bM4_SPI3_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42400184UL))) +#define bM4_SPI3_CFG1_SPRDTD (*((volatile unsigned int*)(0x42400198UL))) +#define bM4_SPI3_CFG1_SS0PV (*((volatile unsigned int*)(0x424001A0UL))) +#define bM4_SPI3_CFG1_SS1PV (*((volatile unsigned int*)(0x424001A4UL))) +#define bM4_SPI3_CFG1_SS2PV (*((volatile unsigned int*)(0x424001A8UL))) +#define bM4_SPI3_CFG1_SS3PV (*((volatile unsigned int*)(0x424001ACUL))) +#define bM4_SPI3_CFG1_MSSI0 (*((volatile unsigned int*)(0x424001D0UL))) +#define bM4_SPI3_CFG1_MSSI1 (*((volatile unsigned int*)(0x424001D4UL))) +#define bM4_SPI3_CFG1_MSSI2 (*((volatile unsigned int*)(0x424001D8UL))) +#define bM4_SPI3_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424001E0UL))) +#define bM4_SPI3_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424001E4UL))) +#define bM4_SPI3_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424001E8UL))) +#define bM4_SPI3_CFG1_MIDI0 (*((volatile unsigned int*)(0x424001F0UL))) +#define bM4_SPI3_CFG1_MIDI1 (*((volatile unsigned int*)(0x424001F4UL))) +#define bM4_SPI3_CFG1_MIDI2 (*((volatile unsigned int*)(0x424001F8UL))) +#define bM4_SPI3_SR_OVRERF (*((volatile unsigned int*)(0x42400280UL))) +#define bM4_SPI3_SR_IDLNF (*((volatile unsigned int*)(0x42400284UL))) +#define bM4_SPI3_SR_MODFERF (*((volatile unsigned int*)(0x42400288UL))) +#define bM4_SPI3_SR_PERF (*((volatile unsigned int*)(0x4240028CUL))) +#define bM4_SPI3_SR_UDRERF (*((volatile unsigned int*)(0x42400290UL))) +#define bM4_SPI3_SR_TDEF (*((volatile unsigned int*)(0x42400294UL))) +#define bM4_SPI3_SR_RDFF (*((volatile unsigned int*)(0x4240029CUL))) +#define bM4_SPI3_CFG2_CPHA (*((volatile unsigned int*)(0x42400300UL))) +#define bM4_SPI3_CFG2_CPOL (*((volatile unsigned int*)(0x42400304UL))) +#define bM4_SPI3_CFG2_MBR0 (*((volatile unsigned int*)(0x42400308UL))) +#define bM4_SPI3_CFG2_MBR1 (*((volatile unsigned int*)(0x4240030CUL))) +#define bM4_SPI3_CFG2_MBR2 (*((volatile unsigned int*)(0x42400310UL))) +#define bM4_SPI3_CFG2_SSA0 (*((volatile unsigned int*)(0x42400314UL))) +#define bM4_SPI3_CFG2_SSA1 (*((volatile unsigned int*)(0x42400318UL))) +#define bM4_SPI3_CFG2_SSA2 (*((volatile unsigned int*)(0x4240031CUL))) +#define bM4_SPI3_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42400320UL))) +#define bM4_SPI3_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42400324UL))) +#define bM4_SPI3_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42400328UL))) +#define bM4_SPI3_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240032CUL))) +#define bM4_SPI3_CFG2_LSBF (*((volatile unsigned int*)(0x42400330UL))) +#define bM4_SPI3_CFG2_MIDIE (*((volatile unsigned int*)(0x42400334UL))) +#define bM4_SPI3_CFG2_MSSDLE (*((volatile unsigned int*)(0x42400338UL))) +#define bM4_SPI3_CFG2_MSSIE (*((volatile unsigned int*)(0x4240033CUL))) +#define bM4_SPI4_CR1_SPIMDS (*((volatile unsigned int*)(0x42408080UL))) +#define bM4_SPI4_CR1_TXMDS (*((volatile unsigned int*)(0x42408084UL))) +#define bM4_SPI4_CR1_MSTR (*((volatile unsigned int*)(0x4240808CUL))) +#define bM4_SPI4_CR1_SPLPBK (*((volatile unsigned int*)(0x42408090UL))) +#define bM4_SPI4_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42408094UL))) +#define bM4_SPI4_CR1_SPE (*((volatile unsigned int*)(0x42408098UL))) +#define bM4_SPI4_CR1_CSUSPE (*((volatile unsigned int*)(0x4240809CUL))) +#define bM4_SPI4_CR1_EIE (*((volatile unsigned int*)(0x424080A0UL))) +#define bM4_SPI4_CR1_TXIE (*((volatile unsigned int*)(0x424080A4UL))) +#define bM4_SPI4_CR1_RXIE (*((volatile unsigned int*)(0x424080A8UL))) +#define bM4_SPI4_CR1_IDIE (*((volatile unsigned int*)(0x424080ACUL))) +#define bM4_SPI4_CR1_MODFE (*((volatile unsigned int*)(0x424080B0UL))) +#define bM4_SPI4_CR1_PATE (*((volatile unsigned int*)(0x424080B4UL))) +#define bM4_SPI4_CR1_PAOE (*((volatile unsigned int*)(0x424080B8UL))) +#define bM4_SPI4_CR1_PAE (*((volatile unsigned int*)(0x424080BCUL))) +#define bM4_SPI4_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42408180UL))) +#define bM4_SPI4_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42408184UL))) +#define bM4_SPI4_CFG1_SPRDTD (*((volatile unsigned int*)(0x42408198UL))) +#define bM4_SPI4_CFG1_SS0PV (*((volatile unsigned int*)(0x424081A0UL))) +#define bM4_SPI4_CFG1_SS1PV (*((volatile unsigned int*)(0x424081A4UL))) +#define bM4_SPI4_CFG1_SS2PV (*((volatile unsigned int*)(0x424081A8UL))) +#define bM4_SPI4_CFG1_SS3PV (*((volatile unsigned int*)(0x424081ACUL))) +#define bM4_SPI4_CFG1_MSSI0 (*((volatile unsigned int*)(0x424081D0UL))) +#define bM4_SPI4_CFG1_MSSI1 (*((volatile unsigned int*)(0x424081D4UL))) +#define bM4_SPI4_CFG1_MSSI2 (*((volatile unsigned int*)(0x424081D8UL))) +#define bM4_SPI4_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424081E0UL))) +#define bM4_SPI4_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424081E4UL))) +#define bM4_SPI4_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424081E8UL))) +#define bM4_SPI4_CFG1_MIDI0 (*((volatile unsigned int*)(0x424081F0UL))) +#define bM4_SPI4_CFG1_MIDI1 (*((volatile unsigned int*)(0x424081F4UL))) +#define bM4_SPI4_CFG1_MIDI2 (*((volatile unsigned int*)(0x424081F8UL))) +#define bM4_SPI4_SR_OVRERF (*((volatile unsigned int*)(0x42408280UL))) +#define bM4_SPI4_SR_IDLNF (*((volatile unsigned int*)(0x42408284UL))) +#define bM4_SPI4_SR_MODFERF (*((volatile unsigned int*)(0x42408288UL))) +#define bM4_SPI4_SR_PERF (*((volatile unsigned int*)(0x4240828CUL))) +#define bM4_SPI4_SR_UDRERF (*((volatile unsigned int*)(0x42408290UL))) +#define bM4_SPI4_SR_TDEF (*((volatile unsigned int*)(0x42408294UL))) +#define bM4_SPI4_SR_RDFF (*((volatile unsigned int*)(0x4240829CUL))) +#define bM4_SPI4_CFG2_CPHA (*((volatile unsigned int*)(0x42408300UL))) +#define bM4_SPI4_CFG2_CPOL (*((volatile unsigned int*)(0x42408304UL))) +#define bM4_SPI4_CFG2_MBR0 (*((volatile unsigned int*)(0x42408308UL))) +#define bM4_SPI4_CFG2_MBR1 (*((volatile unsigned int*)(0x4240830CUL))) +#define bM4_SPI4_CFG2_MBR2 (*((volatile unsigned int*)(0x42408310UL))) +#define bM4_SPI4_CFG2_SSA0 (*((volatile unsigned int*)(0x42408314UL))) +#define bM4_SPI4_CFG2_SSA1 (*((volatile unsigned int*)(0x42408318UL))) +#define bM4_SPI4_CFG2_SSA2 (*((volatile unsigned int*)(0x4240831CUL))) +#define bM4_SPI4_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42408320UL))) +#define bM4_SPI4_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42408324UL))) +#define bM4_SPI4_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42408328UL))) +#define bM4_SPI4_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240832CUL))) +#define bM4_SPI4_CFG2_LSBF (*((volatile unsigned int*)(0x42408330UL))) +#define bM4_SPI4_CFG2_MIDIE (*((volatile unsigned int*)(0x42408334UL))) +#define bM4_SPI4_CFG2_MSSDLE (*((volatile unsigned int*)(0x42408338UL))) +#define bM4_SPI4_CFG2_MSSIE (*((volatile unsigned int*)(0x4240833CUL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT0 (*((volatile unsigned int*)(0x42A10000UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT1 (*((volatile unsigned int*)(0x42A10004UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT2 (*((volatile unsigned int*)(0x42A10008UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT0 (*((volatile unsigned int*)(0x42A10010UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT1 (*((volatile unsigned int*)(0x42A10014UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT2 (*((volatile unsigned int*)(0x42A10018UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT0 (*((volatile unsigned int*)(0x42A10020UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT1 (*((volatile unsigned int*)(0x42A10024UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT2 (*((volatile unsigned int*)(0x42A10028UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT0 (*((volatile unsigned int*)(0x42A10030UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT1 (*((volatile unsigned int*)(0x42A10034UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT2 (*((volatile unsigned int*)(0x42A10038UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT0 (*((volatile unsigned int*)(0x42A10040UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT1 (*((volatile unsigned int*)(0x42A10044UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT2 (*((volatile unsigned int*)(0x42A10048UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT0 (*((volatile unsigned int*)(0x42A10050UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT1 (*((volatile unsigned int*)(0x42A10054UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT2 (*((volatile unsigned int*)(0x42A10058UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT0 (*((volatile unsigned int*)(0x42A10060UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT1 (*((volatile unsigned int*)(0x42A10064UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT2 (*((volatile unsigned int*)(0x42A10068UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT0 (*((volatile unsigned int*)(0x42A10070UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT1 (*((volatile unsigned int*)(0x42A10074UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT2 (*((volatile unsigned int*)(0x42A10078UL))) +#define bM4_SRAMC_WTPR_WTPRC (*((volatile unsigned int*)(0x42A10080UL))) +#define bM4_SRAMC_WTPR_WTPRKW0 (*((volatile unsigned int*)(0x42A10084UL))) +#define bM4_SRAMC_WTPR_WTPRKW1 (*((volatile unsigned int*)(0x42A10088UL))) +#define bM4_SRAMC_WTPR_WTPRKW2 (*((volatile unsigned int*)(0x42A1008CUL))) +#define bM4_SRAMC_WTPR_WTPRKW3 (*((volatile unsigned int*)(0x42A10090UL))) +#define bM4_SRAMC_WTPR_WTPRKW4 (*((volatile unsigned int*)(0x42A10094UL))) +#define bM4_SRAMC_WTPR_WTPRKW5 (*((volatile unsigned int*)(0x42A10098UL))) +#define bM4_SRAMC_WTPR_WTPRKW6 (*((volatile unsigned int*)(0x42A1009CUL))) +#define bM4_SRAMC_CKCR_PYOAD (*((volatile unsigned int*)(0x42A10100UL))) +#define bM4_SRAMC_CKCR_ECCOAD (*((volatile unsigned int*)(0x42A10140UL))) +#define bM4_SRAMC_CKCR_ECCMOD0 (*((volatile unsigned int*)(0x42A10160UL))) +#define bM4_SRAMC_CKCR_ECCMOD1 (*((volatile unsigned int*)(0x42A10164UL))) +#define bM4_SRAMC_CKPR_CKPRC (*((volatile unsigned int*)(0x42A10180UL))) +#define bM4_SRAMC_CKPR_CKPRKW0 (*((volatile unsigned int*)(0x42A10184UL))) +#define bM4_SRAMC_CKPR_CKPRKW1 (*((volatile unsigned int*)(0x42A10188UL))) +#define bM4_SRAMC_CKPR_CKPRKW2 (*((volatile unsigned int*)(0x42A1018CUL))) +#define bM4_SRAMC_CKPR_CKPRKW3 (*((volatile unsigned int*)(0x42A10190UL))) +#define bM4_SRAMC_CKPR_CKPRKW4 (*((volatile unsigned int*)(0x42A10194UL))) +#define bM4_SRAMC_CKPR_CKPRKW5 (*((volatile unsigned int*)(0x42A10198UL))) +#define bM4_SRAMC_CKPR_CKPRKW6 (*((volatile unsigned int*)(0x42A1019CUL))) +#define bM4_SRAMC_CKSR_SRAM3_1ERR (*((volatile unsigned int*)(0x42A10200UL))) +#define bM4_SRAMC_CKSR_SRAM3_2ERR (*((volatile unsigned int*)(0x42A10204UL))) +#define bM4_SRAMC_CKSR_SRAM12_PYERR (*((volatile unsigned int*)(0x42A10208UL))) +#define bM4_SRAMC_CKSR_SRAMH_PYERR (*((volatile unsigned int*)(0x42A1020CUL))) +#define bM4_SRAMC_CKSR_SRAMR_PYERR (*((volatile unsigned int*)(0x42A10210UL))) +#define bM4_SWDT_SR_CNT0 (*((volatile unsigned int*)(0x42928080UL))) +#define bM4_SWDT_SR_CNT1 (*((volatile unsigned int*)(0x42928084UL))) +#define bM4_SWDT_SR_CNT2 (*((volatile unsigned int*)(0x42928088UL))) +#define bM4_SWDT_SR_CNT3 (*((volatile unsigned int*)(0x4292808CUL))) +#define bM4_SWDT_SR_CNT4 (*((volatile unsigned int*)(0x42928090UL))) +#define bM4_SWDT_SR_CNT5 (*((volatile unsigned int*)(0x42928094UL))) +#define bM4_SWDT_SR_CNT6 (*((volatile unsigned int*)(0x42928098UL))) +#define bM4_SWDT_SR_CNT7 (*((volatile unsigned int*)(0x4292809CUL))) +#define bM4_SWDT_SR_CNT8 (*((volatile unsigned int*)(0x429280A0UL))) +#define bM4_SWDT_SR_CNT9 (*((volatile unsigned int*)(0x429280A4UL))) +#define bM4_SWDT_SR_CNT10 (*((volatile unsigned int*)(0x429280A8UL))) +#define bM4_SWDT_SR_CNT11 (*((volatile unsigned int*)(0x429280ACUL))) +#define bM4_SWDT_SR_CNT12 (*((volatile unsigned int*)(0x429280B0UL))) +#define bM4_SWDT_SR_CNT13 (*((volatile unsigned int*)(0x429280B4UL))) +#define bM4_SWDT_SR_CNT14 (*((volatile unsigned int*)(0x429280B8UL))) +#define bM4_SWDT_SR_CNT15 (*((volatile unsigned int*)(0x429280BCUL))) +#define bM4_SWDT_SR_UDF (*((volatile unsigned int*)(0x429280C0UL))) +#define bM4_SWDT_SR_REF (*((volatile unsigned int*)(0x429280C4UL))) +#define bM4_SWDT_RR_RF0 (*((volatile unsigned int*)(0x42928100UL))) +#define bM4_SWDT_RR_RF1 (*((volatile unsigned int*)(0x42928104UL))) +#define bM4_SWDT_RR_RF2 (*((volatile unsigned int*)(0x42928108UL))) +#define bM4_SWDT_RR_RF3 (*((volatile unsigned int*)(0x4292810CUL))) +#define bM4_SWDT_RR_RF4 (*((volatile unsigned int*)(0x42928110UL))) +#define bM4_SWDT_RR_RF5 (*((volatile unsigned int*)(0x42928114UL))) +#define bM4_SWDT_RR_RF6 (*((volatile unsigned int*)(0x42928118UL))) +#define bM4_SWDT_RR_RF7 (*((volatile unsigned int*)(0x4292811CUL))) +#define bM4_SWDT_RR_RF8 (*((volatile unsigned int*)(0x42928120UL))) +#define bM4_SWDT_RR_RF9 (*((volatile unsigned int*)(0x42928124UL))) +#define bM4_SWDT_RR_RF10 (*((volatile unsigned int*)(0x42928128UL))) +#define bM4_SWDT_RR_RF11 (*((volatile unsigned int*)(0x4292812CUL))) +#define bM4_SWDT_RR_RF12 (*((volatile unsigned int*)(0x42928130UL))) +#define bM4_SWDT_RR_RF13 (*((volatile unsigned int*)(0x42928134UL))) +#define bM4_SWDT_RR_RF14 (*((volatile unsigned int*)(0x42928138UL))) +#define bM4_SWDT_RR_RF15 (*((volatile unsigned int*)(0x4292813CUL))) +#define bM4_SYSREG_PWR_STPMCR_FLNWT (*((volatile unsigned int*)(0x42A80180UL))) +#define bM4_SYSREG_PWR_STPMCR_CKSMRC (*((volatile unsigned int*)(0x42A80184UL))) +#define bM4_SYSREG_PWR_STPMCR_STOP (*((volatile unsigned int*)(0x42A801BCUL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL0 (*((volatile unsigned int*)(0x42A80200UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL1 (*((volatile unsigned int*)(0x42A80204UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL2 (*((volatile unsigned int*)(0x42A80208UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL3 (*((volatile unsigned int*)(0x42A8020CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL0 (*((volatile unsigned int*)(0x42A80240UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL1 (*((volatile unsigned int*)(0x42A80244UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL2 (*((volatile unsigned int*)(0x42A80248UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL3 (*((volatile unsigned int*)(0x42A8024CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL0 (*((volatile unsigned int*)(0x42A80250UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL1 (*((volatile unsigned int*)(0x42A80254UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL2 (*((volatile unsigned int*)(0x42A80258UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL3 (*((volatile unsigned int*)(0x42A8025CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL0 (*((volatile unsigned int*)(0x42A80260UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL1 (*((volatile unsigned int*)(0x42A80264UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL2 (*((volatile unsigned int*)(0x42A80268UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL3 (*((volatile unsigned int*)(0x42A8026CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL0 (*((volatile unsigned int*)(0x42A80270UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL1 (*((volatile unsigned int*)(0x42A80274UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL2 (*((volatile unsigned int*)(0x42A80278UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL3 (*((volatile unsigned int*)(0x42A8027CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC0 (*((volatile unsigned int*)(0x42A80280UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC1 (*((volatile unsigned int*)(0x42A80284UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC2 (*((volatile unsigned int*)(0x42A80288UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC3 (*((volatile unsigned int*)(0x42A8028CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC4 (*((volatile unsigned int*)(0x42A80290UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC5 (*((volatile unsigned int*)(0x42A80294UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC6 (*((volatile unsigned int*)(0x42A80298UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC7 (*((volatile unsigned int*)(0x42A8029CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC8 (*((volatile unsigned int*)(0x42A802A0UL))) +#define bM4_SYSREG_MPU_IPPR_AESRDP (*((volatile unsigned int*)(0x42A80380UL))) +#define bM4_SYSREG_MPU_IPPR_AESWRP (*((volatile unsigned int*)(0x42A80384UL))) +#define bM4_SYSREG_MPU_IPPR_HASHRDP (*((volatile unsigned int*)(0x42A80388UL))) +#define bM4_SYSREG_MPU_IPPR_HASHWRP (*((volatile unsigned int*)(0x42A8038CUL))) +#define bM4_SYSREG_MPU_IPPR_TRNGRDP (*((volatile unsigned int*)(0x42A80390UL))) +#define bM4_SYSREG_MPU_IPPR_TRNGWRP (*((volatile unsigned int*)(0x42A80394UL))) +#define bM4_SYSREG_MPU_IPPR_CRCRDP (*((volatile unsigned int*)(0x42A80398UL))) +#define bM4_SYSREG_MPU_IPPR_CRCWRP (*((volatile unsigned int*)(0x42A8039CUL))) +#define bM4_SYSREG_MPU_IPPR_FMCRDP (*((volatile unsigned int*)(0x42A803A0UL))) +#define bM4_SYSREG_MPU_IPPR_FMCWRP (*((volatile unsigned int*)(0x42A803A4UL))) +#define bM4_SYSREG_MPU_IPPR_WDTRDP (*((volatile unsigned int*)(0x42A803B0UL))) +#define bM4_SYSREG_MPU_IPPR_WDTWRP (*((volatile unsigned int*)(0x42A803B4UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTRDP (*((volatile unsigned int*)(0x42A803B8UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTWRP (*((volatile unsigned int*)(0x42A803BCUL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMRDP (*((volatile unsigned int*)(0x42A803C0UL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMWRP (*((volatile unsigned int*)(0x42A803C4UL))) +#define bM4_SYSREG_MPU_IPPR_RTCRDP (*((volatile unsigned int*)(0x42A803C8UL))) +#define bM4_SYSREG_MPU_IPPR_RTCWRP (*((volatile unsigned int*)(0x42A803CCUL))) +#define bM4_SYSREG_MPU_IPPR_DMPURDP (*((volatile unsigned int*)(0x42A803D0UL))) +#define bM4_SYSREG_MPU_IPPR_DMPUWRP (*((volatile unsigned int*)(0x42A803D4UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCRDP (*((volatile unsigned int*)(0x42A803D8UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCWRP (*((volatile unsigned int*)(0x42A803DCUL))) +#define bM4_SYSREG_MPU_IPPR_INTCRDP (*((volatile unsigned int*)(0x42A803E0UL))) +#define bM4_SYSREG_MPU_IPPR_INTCWRP (*((volatile unsigned int*)(0x42A803E4UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCRDP (*((volatile unsigned int*)(0x42A803E8UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCWRP (*((volatile unsigned int*)(0x42A803ECUL))) +#define bM4_SYSREG_MPU_IPPR_MSTPRDP (*((volatile unsigned int*)(0x42A803F0UL))) +#define bM4_SYSREG_MPU_IPPR_MSTPWRP (*((volatile unsigned int*)(0x42A803F4UL))) +#define bM4_SYSREG_MPU_IPPR_BUSERRE (*((volatile unsigned int*)(0x42A803FCUL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S0 (*((volatile unsigned int*)(0x42A80400UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S1 (*((volatile unsigned int*)(0x42A80404UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S2 (*((volatile unsigned int*)(0x42A80408UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S0 (*((volatile unsigned int*)(0x42A80410UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S1 (*((volatile unsigned int*)(0x42A80414UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S2 (*((volatile unsigned int*)(0x42A80418UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S0 (*((volatile unsigned int*)(0x42A80420UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S1 (*((volatile unsigned int*)(0x42A80424UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S2 (*((volatile unsigned int*)(0x42A80428UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S0 (*((volatile unsigned int*)(0x42A80430UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S1 (*((volatile unsigned int*)(0x42A80434UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S2 (*((volatile unsigned int*)(0x42A80438UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S0 (*((volatile unsigned int*)(0x42A80440UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S1 (*((volatile unsigned int*)(0x42A80444UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S2 (*((volatile unsigned int*)(0x42A80448UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS0 (*((volatile unsigned int*)(0x42A80450UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS1 (*((volatile unsigned int*)(0x42A80454UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS2 (*((volatile unsigned int*)(0x42A80458UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS0 (*((volatile unsigned int*)(0x42A80460UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS1 (*((volatile unsigned int*)(0x42A80464UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS2 (*((volatile unsigned int*)(0x42A80468UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS0 (*((volatile unsigned int*)(0x42A80490UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS1 (*((volatile unsigned int*)(0x42A80494UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS2 (*((volatile unsigned int*)(0x42A80498UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS3 (*((volatile unsigned int*)(0x42A8049CUL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW0 (*((volatile unsigned int*)(0x42A804C0UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW1 (*((volatile unsigned int*)(0x42A804C4UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW2 (*((volatile unsigned int*)(0x42A804C8UL))) +#define bM4_SYSREG_CMU_PLLCR_MPLLOFF (*((volatile unsigned int*)(0x42A80540UL))) +#define bM4_SYSREG_CMU_UPLLCR_UPLLOFF (*((volatile unsigned int*)(0x42A805C0UL))) +#define bM4_SYSREG_CMU_XTALCR_XTALSTP (*((volatile unsigned int*)(0x42A80640UL))) +#define bM4_SYSREG_CMU_HRCCR_HRCSTP (*((volatile unsigned int*)(0x42A806C0UL))) +#define bM4_SYSREG_CMU_MRCCR_MRCSTP (*((volatile unsigned int*)(0x42A80700UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_HRCSTBF (*((volatile unsigned int*)(0x42A80780UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_XTALSTBF (*((volatile unsigned int*)(0x42A8078CUL))) +#define bM4_SYSREG_CMU_OSCSTBSR_MPLLSTBF (*((volatile unsigned int*)(0x42A80794UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_UPLLSTBF (*((volatile unsigned int*)(0x42A80798UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL0 (*((volatile unsigned int*)(0x42A807A0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL1 (*((volatile unsigned int*)(0x42A807A4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL2 (*((volatile unsigned int*)(0x42A807A8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL3 (*((volatile unsigned int*)(0x42A807ACUL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV0 (*((volatile unsigned int*)(0x42A807B0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV1 (*((volatile unsigned int*)(0x42A807B4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV2 (*((volatile unsigned int*)(0x42A807B8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1EN (*((volatile unsigned int*)(0x42A807BCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL0 (*((volatile unsigned int*)(0x42A807C0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL1 (*((volatile unsigned int*)(0x42A807C4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL2 (*((volatile unsigned int*)(0x42A807C8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL3 (*((volatile unsigned int*)(0x42A807CCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV0 (*((volatile unsigned int*)(0x42A807D0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV1 (*((volatile unsigned int*)(0x42A807D4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV2 (*((volatile unsigned int*)(0x42A807D8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2EN (*((volatile unsigned int*)(0x42A807DCUL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS0 (*((volatile unsigned int*)(0x42A807E0UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS1 (*((volatile unsigned int*)(0x42A807E4UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKOE (*((volatile unsigned int*)(0x42A807FCUL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE (*((volatile unsigned int*)(0x42A80800UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRE (*((volatile unsigned int*)(0x42A80804UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRIS (*((volatile unsigned int*)(0x42A80808UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDE (*((volatile unsigned int*)(0x42A8081CUL))) +#define bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF (*((volatile unsigned int*)(0x42A80820UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB0 (*((volatile unsigned int*)(0x42A81440UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB1 (*((volatile unsigned int*)(0x42A81444UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB2 (*((volatile unsigned int*)(0x42A81448UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB3 (*((volatile unsigned int*)(0x42A8144CUL))) +#define bM4_SYSREG_RMU_RSTF0_PORF (*((volatile unsigned int*)(0x42A81800UL))) +#define bM4_SYSREG_RMU_RSTF0_PINRF (*((volatile unsigned int*)(0x42A81804UL))) +#define bM4_SYSREG_RMU_RSTF0_BORF (*((volatile unsigned int*)(0x42A81808UL))) +#define bM4_SYSREG_RMU_RSTF0_PVD1RF (*((volatile unsigned int*)(0x42A8180CUL))) +#define bM4_SYSREG_RMU_RSTF0_PVD2RF (*((volatile unsigned int*)(0x42A81810UL))) +#define bM4_SYSREG_RMU_RSTF0_WDRF (*((volatile unsigned int*)(0x42A81814UL))) +#define bM4_SYSREG_RMU_RSTF0_SWDRF (*((volatile unsigned int*)(0x42A81818UL))) +#define bM4_SYSREG_RMU_RSTF0_PDRF (*((volatile unsigned int*)(0x42A8181CUL))) +#define bM4_SYSREG_RMU_RSTF0_SWRF (*((volatile unsigned int*)(0x42A81820UL))) +#define bM4_SYSREG_RMU_RSTF0_MPUERF (*((volatile unsigned int*)(0x42A81824UL))) +#define bM4_SYSREG_RMU_RSTF0_RAPERF (*((volatile unsigned int*)(0x42A81828UL))) +#define bM4_SYSREG_RMU_RSTF0_RAECRF (*((volatile unsigned int*)(0x42A8182CUL))) +#define bM4_SYSREG_RMU_RSTF0_CKFERF (*((volatile unsigned int*)(0x42A81830UL))) +#define bM4_SYSREG_RMU_RSTF0_XTALERF (*((volatile unsigned int*)(0x42A81834UL))) +#define bM4_SYSREG_RMU_RSTF0_MULTIRF (*((volatile unsigned int*)(0x42A81838UL))) +#define bM4_SYSREG_RMU_RSTF0_CLRF (*((volatile unsigned int*)(0x42A8183CUL))) +#define bM4_SYSREG_PWR_PVDICR_PVD1NMIS (*((volatile unsigned int*)(0x42A81C00UL))) +#define bM4_SYSREG_PWR_PVDICR_PVD2NMIS (*((volatile unsigned int*)(0x42A81C10UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1MON (*((volatile unsigned int*)(0x42A81C20UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG (*((volatile unsigned int*)(0x42A81C24UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2MON (*((volatile unsigned int*)(0x42A81C30UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG (*((volatile unsigned int*)(0x42A81C34UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM0 (*((volatile unsigned int*)(0x42A82000UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM1 (*((volatile unsigned int*)(0x42A82004UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM2 (*((volatile unsigned int*)(0x42A82008UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM3 (*((volatile unsigned int*)(0x42A8200CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM4 (*((volatile unsigned int*)(0x42A82010UL))) +#define bM4_SYSREG_CMU_PLLCFGR_PLLSRC (*((volatile unsigned int*)(0x42A8201CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN0 (*((volatile unsigned int*)(0x42A82020UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN1 (*((volatile unsigned int*)(0x42A82024UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN2 (*((volatile unsigned int*)(0x42A82028UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN3 (*((volatile unsigned int*)(0x42A8202CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN4 (*((volatile unsigned int*)(0x42A82030UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN5 (*((volatile unsigned int*)(0x42A82034UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN6 (*((volatile unsigned int*)(0x42A82038UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN7 (*((volatile unsigned int*)(0x42A8203CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN8 (*((volatile unsigned int*)(0x42A82040UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR0 (*((volatile unsigned int*)(0x42A82050UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR1 (*((volatile unsigned int*)(0x42A82054UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR2 (*((volatile unsigned int*)(0x42A82058UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR3 (*((volatile unsigned int*)(0x42A8205CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ0 (*((volatile unsigned int*)(0x42A82060UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ1 (*((volatile unsigned int*)(0x42A82064UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ2 (*((volatile unsigned int*)(0x42A82068UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ3 (*((volatile unsigned int*)(0x42A8206CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP0 (*((volatile unsigned int*)(0x42A82070UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP1 (*((volatile unsigned int*)(0x42A82074UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP2 (*((volatile unsigned int*)(0x42A82078UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP3 (*((volatile unsigned int*)(0x42A8207CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM0 (*((volatile unsigned int*)(0x42A82080UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM1 (*((volatile unsigned int*)(0x42A82084UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM2 (*((volatile unsigned int*)(0x42A82088UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM3 (*((volatile unsigned int*)(0x42A8208CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM4 (*((volatile unsigned int*)(0x42A82090UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN0 (*((volatile unsigned int*)(0x42A820A0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN1 (*((volatile unsigned int*)(0x42A820A4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN2 (*((volatile unsigned int*)(0x42A820A8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN3 (*((volatile unsigned int*)(0x42A820ACUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN4 (*((volatile unsigned int*)(0x42A820B0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN5 (*((volatile unsigned int*)(0x42A820B4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN6 (*((volatile unsigned int*)(0x42A820B8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN7 (*((volatile unsigned int*)(0x42A820BCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN8 (*((volatile unsigned int*)(0x42A820C0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR0 (*((volatile unsigned int*)(0x42A820D0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR1 (*((volatile unsigned int*)(0x42A820D4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR2 (*((volatile unsigned int*)(0x42A820D8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR3 (*((volatile unsigned int*)(0x42A820DCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ0 (*((volatile unsigned int*)(0x42A820E0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ1 (*((volatile unsigned int*)(0x42A820E4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ2 (*((volatile unsigned int*)(0x42A820E8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ3 (*((volatile unsigned int*)(0x42A820ECUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP0 (*((volatile unsigned int*)(0x42A820F0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP1 (*((volatile unsigned int*)(0x42A820F4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP2 (*((volatile unsigned int*)(0x42A820F8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP3 (*((volatile unsigned int*)(0x42A820FCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB0 (*((volatile unsigned int*)(0x42A87FC0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB1 (*((volatile unsigned int*)(0x42A87FC4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB2 (*((volatile unsigned int*)(0x42A87FC8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB3 (*((volatile unsigned int*)(0x42A87FCCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE0 (*((volatile unsigned int*)(0x42A87FE0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE1 (*((volatile unsigned int*)(0x42A87FE4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE2 (*((volatile unsigned int*)(0x42A87FE8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE3 (*((volatile unsigned int*)(0x42A87FECUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE4 (*((volatile unsigned int*)(0x42A87FF0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE5 (*((volatile unsigned int*)(0x42A87FF4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE6 (*((volatile unsigned int*)(0x42A87FF8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE7 (*((volatile unsigned int*)(0x42A87FFCUL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS0 (*((volatile unsigned int*)(0x42A88000UL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS1 (*((volatile unsigned int*)(0x42A88004UL))) +#define bM4_SYSREG_PWR_PWRC0_VVDRSD (*((volatile unsigned int*)(0x42A88008UL))) +#define bM4_SYSREG_PWR_PWRC0_RETRAMSD (*((volatile unsigned int*)(0x42A8800CUL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN0 (*((volatile unsigned int*)(0x42A88010UL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN1 (*((volatile unsigned int*)(0x42A88014UL))) +#define bM4_SYSREG_PWR_PWRC0_PWDN (*((volatile unsigned int*)(0x42A8801CUL))) +#define bM4_SYSREG_PWR_PWRC1_VPLLSD (*((volatile unsigned int*)(0x42A88020UL))) +#define bM4_SYSREG_PWR_PWRC1_VHRCSD (*((volatile unsigned int*)(0x42A88024UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS0 (*((volatile unsigned int*)(0x42A88038UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS1 (*((volatile unsigned int*)(0x42A8803CUL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS0 (*((volatile unsigned int*)(0x42A88040UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS1 (*((volatile unsigned int*)(0x42A88044UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS2 (*((volatile unsigned int*)(0x42A88048UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS3 (*((volatile unsigned int*)(0x42A8804CUL))) +#define bM4_SYSREG_PWR_PWRC2_DVS0 (*((volatile unsigned int*)(0x42A88050UL))) +#define bM4_SYSREG_PWR_PWRC2_DVS1 (*((volatile unsigned int*)(0x42A88054UL))) +#define bM4_SYSREG_PWR_PWRC3_PDTS (*((volatile unsigned int*)(0x42A88068UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE00 (*((volatile unsigned int*)(0x42A88080UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE01 (*((volatile unsigned int*)(0x42A88084UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE02 (*((volatile unsigned int*)(0x42A88088UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE03 (*((volatile unsigned int*)(0x42A8808CUL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE10 (*((volatile unsigned int*)(0x42A88090UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE11 (*((volatile unsigned int*)(0x42A88094UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE12 (*((volatile unsigned int*)(0x42A88098UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE13 (*((volatile unsigned int*)(0x42A8809CUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE20 (*((volatile unsigned int*)(0x42A880A0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE21 (*((volatile unsigned int*)(0x42A880A4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE22 (*((volatile unsigned int*)(0x42A880A8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE23 (*((volatile unsigned int*)(0x42A880ACUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE30 (*((volatile unsigned int*)(0x42A880B0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE31 (*((volatile unsigned int*)(0x42A880B4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE32 (*((volatile unsigned int*)(0x42A880B8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE33 (*((volatile unsigned int*)(0x42A880BCUL))) +#define bM4_SYSREG_PWR_PDWKE2_VD1WKE (*((volatile unsigned int*)(0x42A880C0UL))) +#define bM4_SYSREG_PWR_PDWKE2_VD2WKE (*((volatile unsigned int*)(0x42A880C4UL))) +#define bM4_SYSREG_PWR_PDWKE2_NMIWKE (*((volatile unsigned int*)(0x42A880C8UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCPRDWKE (*((volatile unsigned int*)(0x42A880D0UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCALMWKE (*((volatile unsigned int*)(0x42A880D4UL))) +#define bM4_SYSREG_PWR_PDWKE2_WKTMWKE (*((volatile unsigned int*)(0x42A880DCUL))) +#define bM4_SYSREG_PWR_PDWKES_WK0EGS (*((volatile unsigned int*)(0x42A880E0UL))) +#define bM4_SYSREG_PWR_PDWKES_WK1EGS (*((volatile unsigned int*)(0x42A880E4UL))) +#define bM4_SYSREG_PWR_PDWKES_WK2EGS (*((volatile unsigned int*)(0x42A880E8UL))) +#define bM4_SYSREG_PWR_PDWKES_WK3EGS (*((volatile unsigned int*)(0x42A880ECUL))) +#define bM4_SYSREG_PWR_PDWKES_VD1EGS (*((volatile unsigned int*)(0x42A880F0UL))) +#define bM4_SYSREG_PWR_PDWKES_VD2EGS (*((volatile unsigned int*)(0x42A880F4UL))) +#define bM4_SYSREG_PWR_PDWKES_NMIEGS (*((volatile unsigned int*)(0x42A880F8UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK0F (*((volatile unsigned int*)(0x42A88100UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK1F (*((volatile unsigned int*)(0x42A88104UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK2F (*((volatile unsigned int*)(0x42A88108UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK3F (*((volatile unsigned int*)(0x42A8810CUL))) +#define bM4_SYSREG_PWR_PDWKF0_VD1WKF (*((volatile unsigned int*)(0x42A88110UL))) +#define bM4_SYSREG_PWR_PDWKF0_VD2WKF (*((volatile unsigned int*)(0x42A88114UL))) +#define bM4_SYSREG_PWR_PDWKF0_NMIWKF (*((volatile unsigned int*)(0x42A88118UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCPRDWKF (*((volatile unsigned int*)(0x42A88130UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCALMWKF (*((volatile unsigned int*)(0x42A88134UL))) +#define bM4_SYSREG_PWR_PDWKF1_WKTMWKF (*((volatile unsigned int*)(0x42A8813CUL))) +#define bM4_SYSREG_PWR_PWCMR_ADBUFE (*((volatile unsigned int*)(0x42A8815CUL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV0 (*((volatile unsigned int*)(0x42A88210UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV1 (*((volatile unsigned int*)(0x42A88214UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALMS (*((volatile unsigned int*)(0x42A88218UL))) +#define bM4_SYSREG_CMU_XTALCFGR_SUPDRV (*((volatile unsigned int*)(0x42A8821CUL))) +#define bM4_SYSREG_PWR_PVDCR0_EXVCCINEN (*((volatile unsigned int*)(0x42A88240UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD1EN (*((volatile unsigned int*)(0x42A88254UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD2EN (*((volatile unsigned int*)(0x42A88258UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRE (*((volatile unsigned int*)(0x42A88260UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRS (*((volatile unsigned int*)(0x42A88264UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1CMPOE (*((volatile unsigned int*)(0x42A88268UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRE (*((volatile unsigned int*)(0x42A88270UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRS (*((volatile unsigned int*)(0x42A88274UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2CMPOE (*((volatile unsigned int*)(0x42A88278UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFDIS (*((volatile unsigned int*)(0x42A88280UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS0 (*((volatile unsigned int*)(0x42A88284UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS1 (*((volatile unsigned int*)(0x42A88288UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFDIS (*((volatile unsigned int*)(0x42A88290UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS0 (*((volatile unsigned int*)(0x42A88294UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS1 (*((volatile unsigned int*)(0x42A88298UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL0 (*((volatile unsigned int*)(0x42A882A0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL1 (*((volatile unsigned int*)(0x42A882A4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL2 (*((volatile unsigned int*)(0x42A882A8UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL0 (*((volatile unsigned int*)(0x42A882B0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL1 (*((volatile unsigned int*)(0x42A882B4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL2 (*((volatile unsigned int*)(0x42A882B8UL))) +#define bM4_SYSREG_CMU_XTAL32CR_XTAL32STP (*((volatile unsigned int*)(0x42A88400UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV0 (*((volatile unsigned int*)(0x42A88420UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV1 (*((volatile unsigned int*)(0x42A88424UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV2 (*((volatile unsigned int*)(0x42A88428UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF0 (*((volatile unsigned int*)(0x42A884A0UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF1 (*((volatile unsigned int*)(0x42A884A4UL))) +#define bM4_SYSREG_CMU_LRCCR_LRCSTP (*((volatile unsigned int*)(0x42A884E0UL))) +#define bM4_SYSREG_PWR_XTAL32CS_CSDIS (*((volatile unsigned int*)(0x42A8857CUL))) +#define bM4_TMR01_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42480000UL))) +#define bM4_TMR01_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42480004UL))) +#define bM4_TMR01_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42480008UL))) +#define bM4_TMR01_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248000CUL))) +#define bM4_TMR01_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42480010UL))) +#define bM4_TMR01_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42480014UL))) +#define bM4_TMR01_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42480018UL))) +#define bM4_TMR01_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248001CUL))) +#define bM4_TMR01_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42480020UL))) +#define bM4_TMR01_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42480024UL))) +#define bM4_TMR01_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42480028UL))) +#define bM4_TMR01_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248002CUL))) +#define bM4_TMR01_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42480030UL))) +#define bM4_TMR01_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42480034UL))) +#define bM4_TMR01_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42480038UL))) +#define bM4_TMR01_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248003CUL))) +#define bM4_TMR01_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42480080UL))) +#define bM4_TMR01_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42480084UL))) +#define bM4_TMR01_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42480088UL))) +#define bM4_TMR01_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248008CUL))) +#define bM4_TMR01_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42480090UL))) +#define bM4_TMR01_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42480094UL))) +#define bM4_TMR01_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42480098UL))) +#define bM4_TMR01_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248009CUL))) +#define bM4_TMR01_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424800A0UL))) +#define bM4_TMR01_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424800A4UL))) +#define bM4_TMR01_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424800A8UL))) +#define bM4_TMR01_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424800ACUL))) +#define bM4_TMR01_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424800B0UL))) +#define bM4_TMR01_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424800B4UL))) +#define bM4_TMR01_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424800B8UL))) +#define bM4_TMR01_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424800BCUL))) +#define bM4_TMR01_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42480100UL))) +#define bM4_TMR01_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42480104UL))) +#define bM4_TMR01_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42480108UL))) +#define bM4_TMR01_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248010CUL))) +#define bM4_TMR01_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42480110UL))) +#define bM4_TMR01_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42480114UL))) +#define bM4_TMR01_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42480118UL))) +#define bM4_TMR01_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248011CUL))) +#define bM4_TMR01_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42480120UL))) +#define bM4_TMR01_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42480124UL))) +#define bM4_TMR01_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42480128UL))) +#define bM4_TMR01_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248012CUL))) +#define bM4_TMR01_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42480130UL))) +#define bM4_TMR01_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42480134UL))) +#define bM4_TMR01_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42480138UL))) +#define bM4_TMR01_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248013CUL))) +#define bM4_TMR01_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42480180UL))) +#define bM4_TMR01_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42480184UL))) +#define bM4_TMR01_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42480188UL))) +#define bM4_TMR01_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248018CUL))) +#define bM4_TMR01_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42480190UL))) +#define bM4_TMR01_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42480194UL))) +#define bM4_TMR01_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42480198UL))) +#define bM4_TMR01_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248019CUL))) +#define bM4_TMR01_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424801A0UL))) +#define bM4_TMR01_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424801A4UL))) +#define bM4_TMR01_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424801A8UL))) +#define bM4_TMR01_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424801ACUL))) +#define bM4_TMR01_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424801B0UL))) +#define bM4_TMR01_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424801B4UL))) +#define bM4_TMR01_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424801B8UL))) +#define bM4_TMR01_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424801BCUL))) +#define bM4_TMR01_BCONR_CSTA (*((volatile unsigned int*)(0x42480200UL))) +#define bM4_TMR01_BCONR_CAPMDA (*((volatile unsigned int*)(0x42480204UL))) +#define bM4_TMR01_BCONR_INTENA (*((volatile unsigned int*)(0x42480208UL))) +#define bM4_TMR01_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42480210UL))) +#define bM4_TMR01_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42480214UL))) +#define bM4_TMR01_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42480218UL))) +#define bM4_TMR01_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248021CUL))) +#define bM4_TMR01_BCONR_SYNSA (*((volatile unsigned int*)(0x42480220UL))) +#define bM4_TMR01_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42480224UL))) +#define bM4_TMR01_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42480228UL))) +#define bM4_TMR01_BCONR_HSTAA (*((volatile unsigned int*)(0x42480230UL))) +#define bM4_TMR01_BCONR_HSTPA (*((volatile unsigned int*)(0x42480234UL))) +#define bM4_TMR01_BCONR_HCLEA (*((volatile unsigned int*)(0x42480238UL))) +#define bM4_TMR01_BCONR_HICPA (*((volatile unsigned int*)(0x4248023CUL))) +#define bM4_TMR01_BCONR_CSTB (*((volatile unsigned int*)(0x42480240UL))) +#define bM4_TMR01_BCONR_CAPMDB (*((volatile unsigned int*)(0x42480244UL))) +#define bM4_TMR01_BCONR_INTENB (*((volatile unsigned int*)(0x42480248UL))) +#define bM4_TMR01_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42480250UL))) +#define bM4_TMR01_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42480254UL))) +#define bM4_TMR01_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42480258UL))) +#define bM4_TMR01_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248025CUL))) +#define bM4_TMR01_BCONR_SYNSB (*((volatile unsigned int*)(0x42480260UL))) +#define bM4_TMR01_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42480264UL))) +#define bM4_TMR01_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42480268UL))) +#define bM4_TMR01_BCONR_HSTAB (*((volatile unsigned int*)(0x42480270UL))) +#define bM4_TMR01_BCONR_HSTPB (*((volatile unsigned int*)(0x42480274UL))) +#define bM4_TMR01_BCONR_HCLEB (*((volatile unsigned int*)(0x42480278UL))) +#define bM4_TMR01_BCONR_HICPB (*((volatile unsigned int*)(0x4248027CUL))) +#define bM4_TMR01_STFLR_CMAF (*((volatile unsigned int*)(0x42480280UL))) +#define bM4_TMR01_STFLR_CMBF (*((volatile unsigned int*)(0x424802C0UL))) +#define bM4_TMR02_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42488000UL))) +#define bM4_TMR02_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42488004UL))) +#define bM4_TMR02_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42488008UL))) +#define bM4_TMR02_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248800CUL))) +#define bM4_TMR02_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42488010UL))) +#define bM4_TMR02_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42488014UL))) +#define bM4_TMR02_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42488018UL))) +#define bM4_TMR02_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248801CUL))) +#define bM4_TMR02_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42488020UL))) +#define bM4_TMR02_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42488024UL))) +#define bM4_TMR02_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42488028UL))) +#define bM4_TMR02_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248802CUL))) +#define bM4_TMR02_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42488030UL))) +#define bM4_TMR02_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42488034UL))) +#define bM4_TMR02_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42488038UL))) +#define bM4_TMR02_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248803CUL))) +#define bM4_TMR02_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42488080UL))) +#define bM4_TMR02_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42488084UL))) +#define bM4_TMR02_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42488088UL))) +#define bM4_TMR02_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248808CUL))) +#define bM4_TMR02_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42488090UL))) +#define bM4_TMR02_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42488094UL))) +#define bM4_TMR02_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42488098UL))) +#define bM4_TMR02_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248809CUL))) +#define bM4_TMR02_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424880A0UL))) +#define bM4_TMR02_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424880A4UL))) +#define bM4_TMR02_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424880A8UL))) +#define bM4_TMR02_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424880ACUL))) +#define bM4_TMR02_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424880B0UL))) +#define bM4_TMR02_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424880B4UL))) +#define bM4_TMR02_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424880B8UL))) +#define bM4_TMR02_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424880BCUL))) +#define bM4_TMR02_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42488100UL))) +#define bM4_TMR02_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42488104UL))) +#define bM4_TMR02_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42488108UL))) +#define bM4_TMR02_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248810CUL))) +#define bM4_TMR02_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42488110UL))) +#define bM4_TMR02_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42488114UL))) +#define bM4_TMR02_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42488118UL))) +#define bM4_TMR02_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248811CUL))) +#define bM4_TMR02_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42488120UL))) +#define bM4_TMR02_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42488124UL))) +#define bM4_TMR02_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42488128UL))) +#define bM4_TMR02_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248812CUL))) +#define bM4_TMR02_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42488130UL))) +#define bM4_TMR02_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42488134UL))) +#define bM4_TMR02_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42488138UL))) +#define bM4_TMR02_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248813CUL))) +#define bM4_TMR02_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42488180UL))) +#define bM4_TMR02_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42488184UL))) +#define bM4_TMR02_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42488188UL))) +#define bM4_TMR02_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248818CUL))) +#define bM4_TMR02_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42488190UL))) +#define bM4_TMR02_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42488194UL))) +#define bM4_TMR02_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42488198UL))) +#define bM4_TMR02_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248819CUL))) +#define bM4_TMR02_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424881A0UL))) +#define bM4_TMR02_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424881A4UL))) +#define bM4_TMR02_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424881A8UL))) +#define bM4_TMR02_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424881ACUL))) +#define bM4_TMR02_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424881B0UL))) +#define bM4_TMR02_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424881B4UL))) +#define bM4_TMR02_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424881B8UL))) +#define bM4_TMR02_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424881BCUL))) +#define bM4_TMR02_BCONR_CSTA (*((volatile unsigned int*)(0x42488200UL))) +#define bM4_TMR02_BCONR_CAPMDA (*((volatile unsigned int*)(0x42488204UL))) +#define bM4_TMR02_BCONR_INTENA (*((volatile unsigned int*)(0x42488208UL))) +#define bM4_TMR02_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42488210UL))) +#define bM4_TMR02_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42488214UL))) +#define bM4_TMR02_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42488218UL))) +#define bM4_TMR02_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248821CUL))) +#define bM4_TMR02_BCONR_SYNSA (*((volatile unsigned int*)(0x42488220UL))) +#define bM4_TMR02_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42488224UL))) +#define bM4_TMR02_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42488228UL))) +#define bM4_TMR02_BCONR_HSTAA (*((volatile unsigned int*)(0x42488230UL))) +#define bM4_TMR02_BCONR_HSTPA (*((volatile unsigned int*)(0x42488234UL))) +#define bM4_TMR02_BCONR_HCLEA (*((volatile unsigned int*)(0x42488238UL))) +#define bM4_TMR02_BCONR_HICPA (*((volatile unsigned int*)(0x4248823CUL))) +#define bM4_TMR02_BCONR_CSTB (*((volatile unsigned int*)(0x42488240UL))) +#define bM4_TMR02_BCONR_CAPMDB (*((volatile unsigned int*)(0x42488244UL))) +#define bM4_TMR02_BCONR_INTENB (*((volatile unsigned int*)(0x42488248UL))) +#define bM4_TMR02_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42488250UL))) +#define bM4_TMR02_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42488254UL))) +#define bM4_TMR02_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42488258UL))) +#define bM4_TMR02_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248825CUL))) +#define bM4_TMR02_BCONR_SYNSB (*((volatile unsigned int*)(0x42488260UL))) +#define bM4_TMR02_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42488264UL))) +#define bM4_TMR02_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42488268UL))) +#define bM4_TMR02_BCONR_HSTAB (*((volatile unsigned int*)(0x42488270UL))) +#define bM4_TMR02_BCONR_HSTPB (*((volatile unsigned int*)(0x42488274UL))) +#define bM4_TMR02_BCONR_HCLEB (*((volatile unsigned int*)(0x42488278UL))) +#define bM4_TMR02_BCONR_HICPB (*((volatile unsigned int*)(0x4248827CUL))) +#define bM4_TMR02_STFLR_CMAF (*((volatile unsigned int*)(0x42488280UL))) +#define bM4_TMR02_STFLR_CMBF (*((volatile unsigned int*)(0x424882C0UL))) +#define bM4_TMR41_OCSRU_OCEH (*((volatile unsigned int*)(0x422E0300UL))) +#define bM4_TMR41_OCSRU_OCEL (*((volatile unsigned int*)(0x422E0304UL))) +#define bM4_TMR41_OCSRU_OCPH (*((volatile unsigned int*)(0x422E0308UL))) +#define bM4_TMR41_OCSRU_OCPL (*((volatile unsigned int*)(0x422E030CUL))) +#define bM4_TMR41_OCSRU_OCIEH (*((volatile unsigned int*)(0x422E0310UL))) +#define bM4_TMR41_OCSRU_OCIEL (*((volatile unsigned int*)(0x422E0314UL))) +#define bM4_TMR41_OCSRU_OCFH (*((volatile unsigned int*)(0x422E0318UL))) +#define bM4_TMR41_OCSRU_OCFL (*((volatile unsigned int*)(0x422E031CUL))) +#define bM4_TMR41_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x422E0340UL))) +#define bM4_TMR41_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x422E0344UL))) +#define bM4_TMR41_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x422E0348UL))) +#define bM4_TMR41_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x422E034CUL))) +#define bM4_TMR41_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x422E0350UL))) +#define bM4_TMR41_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x422E0354UL))) +#define bM4_TMR41_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x422E0358UL))) +#define bM4_TMR41_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x422E035CUL))) +#define bM4_TMR41_OCERU_LMCH (*((volatile unsigned int*)(0x422E0360UL))) +#define bM4_TMR41_OCERU_LMCL (*((volatile unsigned int*)(0x422E0364UL))) +#define bM4_TMR41_OCERU_LMMH (*((volatile unsigned int*)(0x422E0368UL))) +#define bM4_TMR41_OCERU_LMML (*((volatile unsigned int*)(0x422E036CUL))) +#define bM4_TMR41_OCERU_MCECH (*((volatile unsigned int*)(0x422E0370UL))) +#define bM4_TMR41_OCERU_MCECL (*((volatile unsigned int*)(0x422E0374UL))) +#define bM4_TMR41_OCSRV_OCEH (*((volatile unsigned int*)(0x422E0380UL))) +#define bM4_TMR41_OCSRV_OCEL (*((volatile unsigned int*)(0x422E0384UL))) +#define bM4_TMR41_OCSRV_OCPH (*((volatile unsigned int*)(0x422E0388UL))) +#define bM4_TMR41_OCSRV_OCPL (*((volatile unsigned int*)(0x422E038CUL))) +#define bM4_TMR41_OCSRV_OCIEH (*((volatile unsigned int*)(0x422E0390UL))) +#define bM4_TMR41_OCSRV_OCIEL (*((volatile unsigned int*)(0x422E0394UL))) +#define bM4_TMR41_OCSRV_OCFH (*((volatile unsigned int*)(0x422E0398UL))) +#define bM4_TMR41_OCSRV_OCFL (*((volatile unsigned int*)(0x422E039CUL))) +#define bM4_TMR41_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x422E03C0UL))) +#define bM4_TMR41_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x422E03C4UL))) +#define bM4_TMR41_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x422E03C8UL))) +#define bM4_TMR41_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x422E03CCUL))) +#define bM4_TMR41_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x422E03D0UL))) +#define bM4_TMR41_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x422E03D4UL))) +#define bM4_TMR41_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x422E03D8UL))) +#define bM4_TMR41_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x422E03DCUL))) +#define bM4_TMR41_OCERV_LMCH (*((volatile unsigned int*)(0x422E03E0UL))) +#define bM4_TMR41_OCERV_LMCL (*((volatile unsigned int*)(0x422E03E4UL))) +#define bM4_TMR41_OCERV_LMMH (*((volatile unsigned int*)(0x422E03E8UL))) +#define bM4_TMR41_OCERV_LMML (*((volatile unsigned int*)(0x422E03ECUL))) +#define bM4_TMR41_OCERV_MCECH (*((volatile unsigned int*)(0x422E03F0UL))) +#define bM4_TMR41_OCERV_MCECL (*((volatile unsigned int*)(0x422E03F4UL))) +#define bM4_TMR41_OCSRW_OCEH (*((volatile unsigned int*)(0x422E0400UL))) +#define bM4_TMR41_OCSRW_OCEL (*((volatile unsigned int*)(0x422E0404UL))) +#define bM4_TMR41_OCSRW_OCPH (*((volatile unsigned int*)(0x422E0408UL))) +#define bM4_TMR41_OCSRW_OCPL (*((volatile unsigned int*)(0x422E040CUL))) +#define bM4_TMR41_OCSRW_OCIEH (*((volatile unsigned int*)(0x422E0410UL))) +#define bM4_TMR41_OCSRW_OCIEL (*((volatile unsigned int*)(0x422E0414UL))) +#define bM4_TMR41_OCSRW_OCFH (*((volatile unsigned int*)(0x422E0418UL))) +#define bM4_TMR41_OCSRW_OCFL (*((volatile unsigned int*)(0x422E041CUL))) +#define bM4_TMR41_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x422E0440UL))) +#define bM4_TMR41_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x422E0444UL))) +#define bM4_TMR41_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x422E0448UL))) +#define bM4_TMR41_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x422E044CUL))) +#define bM4_TMR41_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x422E0450UL))) +#define bM4_TMR41_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x422E0454UL))) +#define bM4_TMR41_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x422E0458UL))) +#define bM4_TMR41_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x422E045CUL))) +#define bM4_TMR41_OCERW_LMCH (*((volatile unsigned int*)(0x422E0460UL))) +#define bM4_TMR41_OCERW_LMCL (*((volatile unsigned int*)(0x422E0464UL))) +#define bM4_TMR41_OCERW_LMMH (*((volatile unsigned int*)(0x422E0468UL))) +#define bM4_TMR41_OCERW_LMML (*((volatile unsigned int*)(0x422E046CUL))) +#define bM4_TMR41_OCERW_MCECH (*((volatile unsigned int*)(0x422E0470UL))) +#define bM4_TMR41_OCERW_MCECL (*((volatile unsigned int*)(0x422E0474UL))) +#define bM4_TMR41_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x422E0480UL))) +#define bM4_TMR41_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x422E0484UL))) +#define bM4_TMR41_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x422E0488UL))) +#define bM4_TMR41_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x422E048CUL))) +#define bM4_TMR41_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x422E0490UL))) +#define bM4_TMR41_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x422E0494UL))) +#define bM4_TMR41_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x422E0498UL))) +#define bM4_TMR41_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x422E049CUL))) +#define bM4_TMR41_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x422E04A0UL))) +#define bM4_TMR41_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x422E04A4UL))) +#define bM4_TMR41_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x422E04A8UL))) +#define bM4_TMR41_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x422E04ACUL))) +#define bM4_TMR41_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x422E04B0UL))) +#define bM4_TMR41_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x422E04B4UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x422E04B8UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x422E04BCUL))) +#define bM4_TMR41_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x422E0500UL))) +#define bM4_TMR41_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x422E0504UL))) +#define bM4_TMR41_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x422E0508UL))) +#define bM4_TMR41_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x422E050CUL))) +#define bM4_TMR41_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x422E0510UL))) +#define bM4_TMR41_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x422E0514UL))) +#define bM4_TMR41_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x422E0518UL))) +#define bM4_TMR41_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x422E051CUL))) +#define bM4_TMR41_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x422E0520UL))) +#define bM4_TMR41_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x422E0524UL))) +#define bM4_TMR41_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x422E0528UL))) +#define bM4_TMR41_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x422E052CUL))) +#define bM4_TMR41_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x422E0530UL))) +#define bM4_TMR41_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x422E0534UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x422E0538UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x422E053CUL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0540UL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0544UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0548UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x422E054CUL))) +#define bM4_TMR41_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x422E0550UL))) +#define bM4_TMR41_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x422E0554UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x422E0558UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x422E055CUL))) +#define bM4_TMR41_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x422E0560UL))) +#define bM4_TMR41_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x422E0564UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x422E0568UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x422E056CUL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0570UL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0574UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0578UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x422E057CUL))) +#define bM4_TMR41_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x422E0580UL))) +#define bM4_TMR41_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x422E0584UL))) +#define bM4_TMR41_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x422E0588UL))) +#define bM4_TMR41_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x422E058CUL))) +#define bM4_TMR41_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x422E0590UL))) +#define bM4_TMR41_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x422E0594UL))) +#define bM4_TMR41_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x422E0598UL))) +#define bM4_TMR41_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x422E059CUL))) +#define bM4_TMR41_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x422E05A0UL))) +#define bM4_TMR41_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x422E05A4UL))) +#define bM4_TMR41_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x422E05A8UL))) +#define bM4_TMR41_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x422E05ACUL))) +#define bM4_TMR41_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x422E05B0UL))) +#define bM4_TMR41_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x422E05B4UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x422E05B8UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x422E05BCUL))) +#define bM4_TMR41_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x422E0600UL))) +#define bM4_TMR41_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x422E0604UL))) +#define bM4_TMR41_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x422E0608UL))) +#define bM4_TMR41_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x422E060CUL))) +#define bM4_TMR41_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x422E0610UL))) +#define bM4_TMR41_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x422E0614UL))) +#define bM4_TMR41_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x422E0618UL))) +#define bM4_TMR41_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x422E061CUL))) +#define bM4_TMR41_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x422E0620UL))) +#define bM4_TMR41_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x422E0624UL))) +#define bM4_TMR41_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x422E0628UL))) +#define bM4_TMR41_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x422E062CUL))) +#define bM4_TMR41_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x422E0630UL))) +#define bM4_TMR41_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x422E0634UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x422E0638UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x422E063CUL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0640UL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0644UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0648UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x422E064CUL))) +#define bM4_TMR41_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x422E0650UL))) +#define bM4_TMR41_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x422E0654UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x422E0658UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x422E065CUL))) +#define bM4_TMR41_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x422E0660UL))) +#define bM4_TMR41_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x422E0664UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x422E0668UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x422E066CUL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0670UL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0674UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0678UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x422E067CUL))) +#define bM4_TMR41_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x422E0680UL))) +#define bM4_TMR41_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x422E0684UL))) +#define bM4_TMR41_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x422E0688UL))) +#define bM4_TMR41_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x422E068CUL))) +#define bM4_TMR41_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x422E0690UL))) +#define bM4_TMR41_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x422E0694UL))) +#define bM4_TMR41_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x422E0698UL))) +#define bM4_TMR41_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x422E069CUL))) +#define bM4_TMR41_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x422E06A0UL))) +#define bM4_TMR41_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x422E06A4UL))) +#define bM4_TMR41_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x422E06A8UL))) +#define bM4_TMR41_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x422E06ACUL))) +#define bM4_TMR41_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x422E06B0UL))) +#define bM4_TMR41_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x422E06B4UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x422E06B8UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x422E06BCUL))) +#define bM4_TMR41_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x422E0700UL))) +#define bM4_TMR41_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x422E0704UL))) +#define bM4_TMR41_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x422E0708UL))) +#define bM4_TMR41_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x422E070CUL))) +#define bM4_TMR41_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x422E0710UL))) +#define bM4_TMR41_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x422E0714UL))) +#define bM4_TMR41_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x422E0718UL))) +#define bM4_TMR41_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x422E071CUL))) +#define bM4_TMR41_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x422E0720UL))) +#define bM4_TMR41_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x422E0724UL))) +#define bM4_TMR41_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x422E0728UL))) +#define bM4_TMR41_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x422E072CUL))) +#define bM4_TMR41_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x422E0730UL))) +#define bM4_TMR41_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x422E0734UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x422E0738UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x422E073CUL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0740UL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0744UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0748UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x422E074CUL))) +#define bM4_TMR41_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x422E0750UL))) +#define bM4_TMR41_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x422E0754UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x422E0758UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x422E075CUL))) +#define bM4_TMR41_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x422E0760UL))) +#define bM4_TMR41_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x422E0764UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x422E0768UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x422E076CUL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0770UL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0774UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0778UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x422E077CUL))) +#define bM4_TMR41_CCSR_CKDIV0 (*((volatile unsigned int*)(0x422E0900UL))) +#define bM4_TMR41_CCSR_CKDIV1 (*((volatile unsigned int*)(0x422E0904UL))) +#define bM4_TMR41_CCSR_CKDIV2 (*((volatile unsigned int*)(0x422E0908UL))) +#define bM4_TMR41_CCSR_CKDIV3 (*((volatile unsigned int*)(0x422E090CUL))) +#define bM4_TMR41_CCSR_CLEAR (*((volatile unsigned int*)(0x422E0910UL))) +#define bM4_TMR41_CCSR_MODE (*((volatile unsigned int*)(0x422E0914UL))) +#define bM4_TMR41_CCSR_STOP (*((volatile unsigned int*)(0x422E0918UL))) +#define bM4_TMR41_CCSR_BUFEN (*((volatile unsigned int*)(0x422E091CUL))) +#define bM4_TMR41_CCSR_IRQPEN (*((volatile unsigned int*)(0x422E0920UL))) +#define bM4_TMR41_CCSR_IRQPF (*((volatile unsigned int*)(0x422E0924UL))) +#define bM4_TMR41_CCSR_IRQZEN (*((volatile unsigned int*)(0x422E0934UL))) +#define bM4_TMR41_CCSR_IRQZF (*((volatile unsigned int*)(0x422E0938UL))) +#define bM4_TMR41_CCSR_ECKEN (*((volatile unsigned int*)(0x422E093CUL))) +#define bM4_TMR41_CVPR_ZIM0 (*((volatile unsigned int*)(0x422E0940UL))) +#define bM4_TMR41_CVPR_ZIM1 (*((volatile unsigned int*)(0x422E0944UL))) +#define bM4_TMR41_CVPR_ZIM2 (*((volatile unsigned int*)(0x422E0948UL))) +#define bM4_TMR41_CVPR_ZIM3 (*((volatile unsigned int*)(0x422E094CUL))) +#define bM4_TMR41_CVPR_PIM0 (*((volatile unsigned int*)(0x422E0950UL))) +#define bM4_TMR41_CVPR_PIM1 (*((volatile unsigned int*)(0x422E0954UL))) +#define bM4_TMR41_CVPR_PIM2 (*((volatile unsigned int*)(0x422E0958UL))) +#define bM4_TMR41_CVPR_PIM3 (*((volatile unsigned int*)(0x422E095CUL))) +#define bM4_TMR41_CVPR_ZIC0 (*((volatile unsigned int*)(0x422E0960UL))) +#define bM4_TMR41_CVPR_ZIC1 (*((volatile unsigned int*)(0x422E0964UL))) +#define bM4_TMR41_CVPR_ZIC2 (*((volatile unsigned int*)(0x422E0968UL))) +#define bM4_TMR41_CVPR_ZIC3 (*((volatile unsigned int*)(0x422E096CUL))) +#define bM4_TMR41_CVPR_PIC0 (*((volatile unsigned int*)(0x422E0970UL))) +#define bM4_TMR41_CVPR_PIC1 (*((volatile unsigned int*)(0x422E0974UL))) +#define bM4_TMR41_CVPR_PIC2 (*((volatile unsigned int*)(0x422E0978UL))) +#define bM4_TMR41_CVPR_PIC3 (*((volatile unsigned int*)(0x422E097CUL))) +#define bM4_TMR41_POCRU_DIVCK0 (*((volatile unsigned int*)(0x422E1300UL))) +#define bM4_TMR41_POCRU_DIVCK1 (*((volatile unsigned int*)(0x422E1304UL))) +#define bM4_TMR41_POCRU_DIVCK2 (*((volatile unsigned int*)(0x422E1308UL))) +#define bM4_TMR41_POCRU_DIVCK3 (*((volatile unsigned int*)(0x422E130CUL))) +#define bM4_TMR41_POCRU_PWMMD0 (*((volatile unsigned int*)(0x422E1310UL))) +#define bM4_TMR41_POCRU_PWMMD1 (*((volatile unsigned int*)(0x422E1314UL))) +#define bM4_TMR41_POCRU_LVLS0 (*((volatile unsigned int*)(0x422E1318UL))) +#define bM4_TMR41_POCRU_LVLS1 (*((volatile unsigned int*)(0x422E131CUL))) +#define bM4_TMR41_POCRV_DIVCK0 (*((volatile unsigned int*)(0x422E1380UL))) +#define bM4_TMR41_POCRV_DIVCK1 (*((volatile unsigned int*)(0x422E1384UL))) +#define bM4_TMR41_POCRV_DIVCK2 (*((volatile unsigned int*)(0x422E1388UL))) +#define bM4_TMR41_POCRV_DIVCK3 (*((volatile unsigned int*)(0x422E138CUL))) +#define bM4_TMR41_POCRV_PWMMD0 (*((volatile unsigned int*)(0x422E1390UL))) +#define bM4_TMR41_POCRV_PWMMD1 (*((volatile unsigned int*)(0x422E1394UL))) +#define bM4_TMR41_POCRV_LVLS0 (*((volatile unsigned int*)(0x422E1398UL))) +#define bM4_TMR41_POCRV_LVLS1 (*((volatile unsigned int*)(0x422E139CUL))) +#define bM4_TMR41_POCRW_DIVCK0 (*((volatile unsigned int*)(0x422E1400UL))) +#define bM4_TMR41_POCRW_DIVCK1 (*((volatile unsigned int*)(0x422E1404UL))) +#define bM4_TMR41_POCRW_DIVCK2 (*((volatile unsigned int*)(0x422E1408UL))) +#define bM4_TMR41_POCRW_DIVCK3 (*((volatile unsigned int*)(0x422E140CUL))) +#define bM4_TMR41_POCRW_PWMMD0 (*((volatile unsigned int*)(0x422E1410UL))) +#define bM4_TMR41_POCRW_PWMMD1 (*((volatile unsigned int*)(0x422E1414UL))) +#define bM4_TMR41_POCRW_LVLS0 (*((volatile unsigned int*)(0x422E1418UL))) +#define bM4_TMR41_POCRW_LVLS1 (*((volatile unsigned int*)(0x422E141CUL))) +#define bM4_TMR41_RCSR_RTIDU (*((volatile unsigned int*)(0x422E1480UL))) +#define bM4_TMR41_RCSR_RTIDV (*((volatile unsigned int*)(0x422E1484UL))) +#define bM4_TMR41_RCSR_RTIDW (*((volatile unsigned int*)(0x422E1488UL))) +#define bM4_TMR41_RCSR_RTIFU (*((volatile unsigned int*)(0x422E1490UL))) +#define bM4_TMR41_RCSR_RTICU (*((volatile unsigned int*)(0x422E1494UL))) +#define bM4_TMR41_RCSR_RTEU (*((volatile unsigned int*)(0x422E1498UL))) +#define bM4_TMR41_RCSR_RTSU (*((volatile unsigned int*)(0x422E149CUL))) +#define bM4_TMR41_RCSR_RTIFV (*((volatile unsigned int*)(0x422E14A0UL))) +#define bM4_TMR41_RCSR_RTICV (*((volatile unsigned int*)(0x422E14A4UL))) +#define bM4_TMR41_RCSR_RTEV (*((volatile unsigned int*)(0x422E14A8UL))) +#define bM4_TMR41_RCSR_RTSV (*((volatile unsigned int*)(0x422E14ACUL))) +#define bM4_TMR41_RCSR_RTIFW (*((volatile unsigned int*)(0x422E14B0UL))) +#define bM4_TMR41_RCSR_RTICW (*((volatile unsigned int*)(0x422E14B4UL))) +#define bM4_TMR41_RCSR_RTEW (*((volatile unsigned int*)(0x422E14B8UL))) +#define bM4_TMR41_RCSR_RTSW (*((volatile unsigned int*)(0x422E14BCUL))) +#define bM4_TMR41_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x422E1900UL))) +#define bM4_TMR41_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x422E1904UL))) +#define bM4_TMR41_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x422E1908UL))) +#define bM4_TMR41_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x422E190CUL))) +#define bM4_TMR41_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x422E1910UL))) +#define bM4_TMR41_SCSRUH_LMC (*((volatile unsigned int*)(0x422E1914UL))) +#define bM4_TMR41_SCSRUH_EVTMS (*((volatile unsigned int*)(0x422E1920UL))) +#define bM4_TMR41_SCSRUH_EVTDS (*((volatile unsigned int*)(0x422E1924UL))) +#define bM4_TMR41_SCSRUH_DEN (*((volatile unsigned int*)(0x422E1930UL))) +#define bM4_TMR41_SCSRUH_PEN (*((volatile unsigned int*)(0x422E1934UL))) +#define bM4_TMR41_SCSRUH_UEN (*((volatile unsigned int*)(0x422E1938UL))) +#define bM4_TMR41_SCSRUH_ZEN (*((volatile unsigned int*)(0x422E193CUL))) +#define bM4_TMR41_SCMRUH_AMC0 (*((volatile unsigned int*)(0x422E1940UL))) +#define bM4_TMR41_SCMRUH_AMC1 (*((volatile unsigned int*)(0x422E1944UL))) +#define bM4_TMR41_SCMRUH_AMC2 (*((volatile unsigned int*)(0x422E1948UL))) +#define bM4_TMR41_SCMRUH_AMC3 (*((volatile unsigned int*)(0x422E194CUL))) +#define bM4_TMR41_SCMRUH_MZCE (*((volatile unsigned int*)(0x422E1958UL))) +#define bM4_TMR41_SCMRUH_MPCE (*((volatile unsigned int*)(0x422E195CUL))) +#define bM4_TMR41_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x422E1980UL))) +#define bM4_TMR41_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x422E1984UL))) +#define bM4_TMR41_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x422E1988UL))) +#define bM4_TMR41_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x422E198CUL))) +#define bM4_TMR41_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x422E1990UL))) +#define bM4_TMR41_SCSRUL_LMC (*((volatile unsigned int*)(0x422E1994UL))) +#define bM4_TMR41_SCSRUL_EVTMS (*((volatile unsigned int*)(0x422E19A0UL))) +#define bM4_TMR41_SCSRUL_EVTDS (*((volatile unsigned int*)(0x422E19A4UL))) +#define bM4_TMR41_SCSRUL_DEN (*((volatile unsigned int*)(0x422E19B0UL))) +#define bM4_TMR41_SCSRUL_PEN (*((volatile unsigned int*)(0x422E19B4UL))) +#define bM4_TMR41_SCSRUL_UEN (*((volatile unsigned int*)(0x422E19B8UL))) +#define bM4_TMR41_SCSRUL_ZEN (*((volatile unsigned int*)(0x422E19BCUL))) +#define bM4_TMR41_SCMRUL_AMC0 (*((volatile unsigned int*)(0x422E19C0UL))) +#define bM4_TMR41_SCMRUL_AMC1 (*((volatile unsigned int*)(0x422E19C4UL))) +#define bM4_TMR41_SCMRUL_AMC2 (*((volatile unsigned int*)(0x422E19C8UL))) +#define bM4_TMR41_SCMRUL_AMC3 (*((volatile unsigned int*)(0x422E19CCUL))) +#define bM4_TMR41_SCMRUL_MZCE (*((volatile unsigned int*)(0x422E19D8UL))) +#define bM4_TMR41_SCMRUL_MPCE (*((volatile unsigned int*)(0x422E19DCUL))) +#define bM4_TMR41_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x422E1A00UL))) +#define bM4_TMR41_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x422E1A04UL))) +#define bM4_TMR41_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x422E1A08UL))) +#define bM4_TMR41_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x422E1A0CUL))) +#define bM4_TMR41_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x422E1A10UL))) +#define bM4_TMR41_SCSRVH_LMC (*((volatile unsigned int*)(0x422E1A14UL))) +#define bM4_TMR41_SCSRVH_EVTMS (*((volatile unsigned int*)(0x422E1A20UL))) +#define bM4_TMR41_SCSRVH_EVTDS (*((volatile unsigned int*)(0x422E1A24UL))) +#define bM4_TMR41_SCSRVH_DEN (*((volatile unsigned int*)(0x422E1A30UL))) +#define bM4_TMR41_SCSRVH_PEN (*((volatile unsigned int*)(0x422E1A34UL))) +#define bM4_TMR41_SCSRVH_UEN (*((volatile unsigned int*)(0x422E1A38UL))) +#define bM4_TMR41_SCSRVH_ZEN (*((volatile unsigned int*)(0x422E1A3CUL))) +#define bM4_TMR41_SCMRVH_AMC0 (*((volatile unsigned int*)(0x422E1A40UL))) +#define bM4_TMR41_SCMRVH_AMC1 (*((volatile unsigned int*)(0x422E1A44UL))) +#define bM4_TMR41_SCMRVH_AMC2 (*((volatile unsigned int*)(0x422E1A48UL))) +#define bM4_TMR41_SCMRVH_AMC3 (*((volatile unsigned int*)(0x422E1A4CUL))) +#define bM4_TMR41_SCMRVH_MZCE (*((volatile unsigned int*)(0x422E1A58UL))) +#define bM4_TMR41_SCMRVH_MPCE (*((volatile unsigned int*)(0x422E1A5CUL))) +#define bM4_TMR41_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x422E1A80UL))) +#define bM4_TMR41_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x422E1A84UL))) +#define bM4_TMR41_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x422E1A88UL))) +#define bM4_TMR41_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x422E1A8CUL))) +#define bM4_TMR41_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x422E1A90UL))) +#define bM4_TMR41_SCSRVL_LMC (*((volatile unsigned int*)(0x422E1A94UL))) +#define bM4_TMR41_SCSRVL_EVTMS (*((volatile unsigned int*)(0x422E1AA0UL))) +#define bM4_TMR41_SCSRVL_EVTDS (*((volatile unsigned int*)(0x422E1AA4UL))) +#define bM4_TMR41_SCSRVL_DEN (*((volatile unsigned int*)(0x422E1AB0UL))) +#define bM4_TMR41_SCSRVL_PEN (*((volatile unsigned int*)(0x422E1AB4UL))) +#define bM4_TMR41_SCSRVL_UEN (*((volatile unsigned int*)(0x422E1AB8UL))) +#define bM4_TMR41_SCSRVL_ZEN (*((volatile unsigned int*)(0x422E1ABCUL))) +#define bM4_TMR41_SCMRVL_AMC0 (*((volatile unsigned int*)(0x422E1AC0UL))) +#define bM4_TMR41_SCMRVL_AMC1 (*((volatile unsigned int*)(0x422E1AC4UL))) +#define bM4_TMR41_SCMRVL_AMC2 (*((volatile unsigned int*)(0x422E1AC8UL))) +#define bM4_TMR41_SCMRVL_AMC3 (*((volatile unsigned int*)(0x422E1ACCUL))) +#define bM4_TMR41_SCMRVL_MZCE (*((volatile unsigned int*)(0x422E1AD8UL))) +#define bM4_TMR41_SCMRVL_MPCE (*((volatile unsigned int*)(0x422E1ADCUL))) +#define bM4_TMR41_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x422E1B00UL))) +#define bM4_TMR41_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x422E1B04UL))) +#define bM4_TMR41_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x422E1B08UL))) +#define bM4_TMR41_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x422E1B0CUL))) +#define bM4_TMR41_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x422E1B10UL))) +#define bM4_TMR41_SCSRWH_LMC (*((volatile unsigned int*)(0x422E1B14UL))) +#define bM4_TMR41_SCSRWH_EVTMS (*((volatile unsigned int*)(0x422E1B20UL))) +#define bM4_TMR41_SCSRWH_EVTDS (*((volatile unsigned int*)(0x422E1B24UL))) +#define bM4_TMR41_SCSRWH_DEN (*((volatile unsigned int*)(0x422E1B30UL))) +#define bM4_TMR41_SCSRWH_PEN (*((volatile unsigned int*)(0x422E1B34UL))) +#define bM4_TMR41_SCSRWH_UEN (*((volatile unsigned int*)(0x422E1B38UL))) +#define bM4_TMR41_SCSRWH_ZEN (*((volatile unsigned int*)(0x422E1B3CUL))) +#define bM4_TMR41_SCMRWH_AMC0 (*((volatile unsigned int*)(0x422E1B40UL))) +#define bM4_TMR41_SCMRWH_AMC1 (*((volatile unsigned int*)(0x422E1B44UL))) +#define bM4_TMR41_SCMRWH_AMC2 (*((volatile unsigned int*)(0x422E1B48UL))) +#define bM4_TMR41_SCMRWH_AMC3 (*((volatile unsigned int*)(0x422E1B4CUL))) +#define bM4_TMR41_SCMRWH_MZCE (*((volatile unsigned int*)(0x422E1B58UL))) +#define bM4_TMR41_SCMRWH_MPCE (*((volatile unsigned int*)(0x422E1B5CUL))) +#define bM4_TMR41_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x422E1B80UL))) +#define bM4_TMR41_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x422E1B84UL))) +#define bM4_TMR41_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x422E1B88UL))) +#define bM4_TMR41_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x422E1B8CUL))) +#define bM4_TMR41_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x422E1B90UL))) +#define bM4_TMR41_SCSRWL_LMC (*((volatile unsigned int*)(0x422E1B94UL))) +#define bM4_TMR41_SCSRWL_EVTMS (*((volatile unsigned int*)(0x422E1BA0UL))) +#define bM4_TMR41_SCSRWL_EVTDS (*((volatile unsigned int*)(0x422E1BA4UL))) +#define bM4_TMR41_SCSRWL_DEN (*((volatile unsigned int*)(0x422E1BB0UL))) +#define bM4_TMR41_SCSRWL_PEN (*((volatile unsigned int*)(0x422E1BB4UL))) +#define bM4_TMR41_SCSRWL_UEN (*((volatile unsigned int*)(0x422E1BB8UL))) +#define bM4_TMR41_SCSRWL_ZEN (*((volatile unsigned int*)(0x422E1BBCUL))) +#define bM4_TMR41_SCMRWL_AMC0 (*((volatile unsigned int*)(0x422E1BC0UL))) +#define bM4_TMR41_SCMRWL_AMC1 (*((volatile unsigned int*)(0x422E1BC4UL))) +#define bM4_TMR41_SCMRWL_AMC2 (*((volatile unsigned int*)(0x422E1BC8UL))) +#define bM4_TMR41_SCMRWL_AMC3 (*((volatile unsigned int*)(0x422E1BCCUL))) +#define bM4_TMR41_SCMRWL_MZCE (*((volatile unsigned int*)(0x422E1BD8UL))) +#define bM4_TMR41_SCMRWL_MPCE (*((volatile unsigned int*)(0x422E1BDCUL))) +#define bM4_TMR41_ECSR_HOLD (*((volatile unsigned int*)(0x422E1E1CUL))) +#define bM4_TMR42_OCSRU_OCEH (*((volatile unsigned int*)(0x42490300UL))) +#define bM4_TMR42_OCSRU_OCEL (*((volatile unsigned int*)(0x42490304UL))) +#define bM4_TMR42_OCSRU_OCPH (*((volatile unsigned int*)(0x42490308UL))) +#define bM4_TMR42_OCSRU_OCPL (*((volatile unsigned int*)(0x4249030CUL))) +#define bM4_TMR42_OCSRU_OCIEH (*((volatile unsigned int*)(0x42490310UL))) +#define bM4_TMR42_OCSRU_OCIEL (*((volatile unsigned int*)(0x42490314UL))) +#define bM4_TMR42_OCSRU_OCFH (*((volatile unsigned int*)(0x42490318UL))) +#define bM4_TMR42_OCSRU_OCFL (*((volatile unsigned int*)(0x4249031CUL))) +#define bM4_TMR42_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42490340UL))) +#define bM4_TMR42_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42490344UL))) +#define bM4_TMR42_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42490348UL))) +#define bM4_TMR42_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249034CUL))) +#define bM4_TMR42_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42490350UL))) +#define bM4_TMR42_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42490354UL))) +#define bM4_TMR42_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42490358UL))) +#define bM4_TMR42_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249035CUL))) +#define bM4_TMR42_OCERU_LMCH (*((volatile unsigned int*)(0x42490360UL))) +#define bM4_TMR42_OCERU_LMCL (*((volatile unsigned int*)(0x42490364UL))) +#define bM4_TMR42_OCERU_LMMH (*((volatile unsigned int*)(0x42490368UL))) +#define bM4_TMR42_OCERU_LMML (*((volatile unsigned int*)(0x4249036CUL))) +#define bM4_TMR42_OCERU_MCECH (*((volatile unsigned int*)(0x42490370UL))) +#define bM4_TMR42_OCERU_MCECL (*((volatile unsigned int*)(0x42490374UL))) +#define bM4_TMR42_OCSRV_OCEH (*((volatile unsigned int*)(0x42490380UL))) +#define bM4_TMR42_OCSRV_OCEL (*((volatile unsigned int*)(0x42490384UL))) +#define bM4_TMR42_OCSRV_OCPH (*((volatile unsigned int*)(0x42490388UL))) +#define bM4_TMR42_OCSRV_OCPL (*((volatile unsigned int*)(0x4249038CUL))) +#define bM4_TMR42_OCSRV_OCIEH (*((volatile unsigned int*)(0x42490390UL))) +#define bM4_TMR42_OCSRV_OCIEL (*((volatile unsigned int*)(0x42490394UL))) +#define bM4_TMR42_OCSRV_OCFH (*((volatile unsigned int*)(0x42490398UL))) +#define bM4_TMR42_OCSRV_OCFL (*((volatile unsigned int*)(0x4249039CUL))) +#define bM4_TMR42_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424903C0UL))) +#define bM4_TMR42_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424903C4UL))) +#define bM4_TMR42_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424903C8UL))) +#define bM4_TMR42_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424903CCUL))) +#define bM4_TMR42_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424903D0UL))) +#define bM4_TMR42_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424903D4UL))) +#define bM4_TMR42_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424903D8UL))) +#define bM4_TMR42_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424903DCUL))) +#define bM4_TMR42_OCERV_LMCH (*((volatile unsigned int*)(0x424903E0UL))) +#define bM4_TMR42_OCERV_LMCL (*((volatile unsigned int*)(0x424903E4UL))) +#define bM4_TMR42_OCERV_LMMH (*((volatile unsigned int*)(0x424903E8UL))) +#define bM4_TMR42_OCERV_LMML (*((volatile unsigned int*)(0x424903ECUL))) +#define bM4_TMR42_OCERV_MCECH (*((volatile unsigned int*)(0x424903F0UL))) +#define bM4_TMR42_OCERV_MCECL (*((volatile unsigned int*)(0x424903F4UL))) +#define bM4_TMR42_OCSRW_OCEH (*((volatile unsigned int*)(0x42490400UL))) +#define bM4_TMR42_OCSRW_OCEL (*((volatile unsigned int*)(0x42490404UL))) +#define bM4_TMR42_OCSRW_OCPH (*((volatile unsigned int*)(0x42490408UL))) +#define bM4_TMR42_OCSRW_OCPL (*((volatile unsigned int*)(0x4249040CUL))) +#define bM4_TMR42_OCSRW_OCIEH (*((volatile unsigned int*)(0x42490410UL))) +#define bM4_TMR42_OCSRW_OCIEL (*((volatile unsigned int*)(0x42490414UL))) +#define bM4_TMR42_OCSRW_OCFH (*((volatile unsigned int*)(0x42490418UL))) +#define bM4_TMR42_OCSRW_OCFL (*((volatile unsigned int*)(0x4249041CUL))) +#define bM4_TMR42_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42490440UL))) +#define bM4_TMR42_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42490444UL))) +#define bM4_TMR42_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42490448UL))) +#define bM4_TMR42_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249044CUL))) +#define bM4_TMR42_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42490450UL))) +#define bM4_TMR42_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42490454UL))) +#define bM4_TMR42_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42490458UL))) +#define bM4_TMR42_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249045CUL))) +#define bM4_TMR42_OCERW_LMCH (*((volatile unsigned int*)(0x42490460UL))) +#define bM4_TMR42_OCERW_LMCL (*((volatile unsigned int*)(0x42490464UL))) +#define bM4_TMR42_OCERW_LMMH (*((volatile unsigned int*)(0x42490468UL))) +#define bM4_TMR42_OCERW_LMML (*((volatile unsigned int*)(0x4249046CUL))) +#define bM4_TMR42_OCERW_MCECH (*((volatile unsigned int*)(0x42490470UL))) +#define bM4_TMR42_OCERW_MCECL (*((volatile unsigned int*)(0x42490474UL))) +#define bM4_TMR42_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42490480UL))) +#define bM4_TMR42_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42490484UL))) +#define bM4_TMR42_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42490488UL))) +#define bM4_TMR42_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249048CUL))) +#define bM4_TMR42_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42490490UL))) +#define bM4_TMR42_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42490494UL))) +#define bM4_TMR42_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42490498UL))) +#define bM4_TMR42_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249049CUL))) +#define bM4_TMR42_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424904A0UL))) +#define bM4_TMR42_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424904A4UL))) +#define bM4_TMR42_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424904A8UL))) +#define bM4_TMR42_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424904ACUL))) +#define bM4_TMR42_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424904B0UL))) +#define bM4_TMR42_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424904B4UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424904B8UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424904BCUL))) +#define bM4_TMR42_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42490500UL))) +#define bM4_TMR42_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42490504UL))) +#define bM4_TMR42_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42490508UL))) +#define bM4_TMR42_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249050CUL))) +#define bM4_TMR42_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42490510UL))) +#define bM4_TMR42_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42490514UL))) +#define bM4_TMR42_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42490518UL))) +#define bM4_TMR42_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249051CUL))) +#define bM4_TMR42_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42490520UL))) +#define bM4_TMR42_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42490524UL))) +#define bM4_TMR42_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42490528UL))) +#define bM4_TMR42_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249052CUL))) +#define bM4_TMR42_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42490530UL))) +#define bM4_TMR42_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42490534UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42490538UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249053CUL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42490540UL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42490544UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42490548UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249054CUL))) +#define bM4_TMR42_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42490550UL))) +#define bM4_TMR42_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42490554UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42490558UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249055CUL))) +#define bM4_TMR42_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42490560UL))) +#define bM4_TMR42_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42490564UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42490568UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249056CUL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42490570UL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42490574UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42490578UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249057CUL))) +#define bM4_TMR42_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42490580UL))) +#define bM4_TMR42_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42490584UL))) +#define bM4_TMR42_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42490588UL))) +#define bM4_TMR42_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249058CUL))) +#define bM4_TMR42_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42490590UL))) +#define bM4_TMR42_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42490594UL))) +#define bM4_TMR42_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42490598UL))) +#define bM4_TMR42_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249059CUL))) +#define bM4_TMR42_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424905A0UL))) +#define bM4_TMR42_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424905A4UL))) +#define bM4_TMR42_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424905A8UL))) +#define bM4_TMR42_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424905ACUL))) +#define bM4_TMR42_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424905B0UL))) +#define bM4_TMR42_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424905B4UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424905B8UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424905BCUL))) +#define bM4_TMR42_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42490600UL))) +#define bM4_TMR42_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42490604UL))) +#define bM4_TMR42_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42490608UL))) +#define bM4_TMR42_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249060CUL))) +#define bM4_TMR42_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42490610UL))) +#define bM4_TMR42_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42490614UL))) +#define bM4_TMR42_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42490618UL))) +#define bM4_TMR42_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249061CUL))) +#define bM4_TMR42_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42490620UL))) +#define bM4_TMR42_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42490624UL))) +#define bM4_TMR42_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42490628UL))) +#define bM4_TMR42_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249062CUL))) +#define bM4_TMR42_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42490630UL))) +#define bM4_TMR42_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42490634UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42490638UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249063CUL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42490640UL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42490644UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42490648UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249064CUL))) +#define bM4_TMR42_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42490650UL))) +#define bM4_TMR42_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42490654UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42490658UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249065CUL))) +#define bM4_TMR42_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42490660UL))) +#define bM4_TMR42_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42490664UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42490668UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249066CUL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42490670UL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42490674UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42490678UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249067CUL))) +#define bM4_TMR42_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42490680UL))) +#define bM4_TMR42_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42490684UL))) +#define bM4_TMR42_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42490688UL))) +#define bM4_TMR42_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249068CUL))) +#define bM4_TMR42_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42490690UL))) +#define bM4_TMR42_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42490694UL))) +#define bM4_TMR42_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42490698UL))) +#define bM4_TMR42_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249069CUL))) +#define bM4_TMR42_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424906A0UL))) +#define bM4_TMR42_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424906A4UL))) +#define bM4_TMR42_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424906A8UL))) +#define bM4_TMR42_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424906ACUL))) +#define bM4_TMR42_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424906B0UL))) +#define bM4_TMR42_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424906B4UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424906B8UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424906BCUL))) +#define bM4_TMR42_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42490700UL))) +#define bM4_TMR42_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42490704UL))) +#define bM4_TMR42_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42490708UL))) +#define bM4_TMR42_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249070CUL))) +#define bM4_TMR42_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42490710UL))) +#define bM4_TMR42_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42490714UL))) +#define bM4_TMR42_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42490718UL))) +#define bM4_TMR42_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249071CUL))) +#define bM4_TMR42_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42490720UL))) +#define bM4_TMR42_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42490724UL))) +#define bM4_TMR42_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42490728UL))) +#define bM4_TMR42_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249072CUL))) +#define bM4_TMR42_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42490730UL))) +#define bM4_TMR42_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42490734UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42490738UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249073CUL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42490740UL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42490744UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42490748UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249074CUL))) +#define bM4_TMR42_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42490750UL))) +#define bM4_TMR42_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42490754UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42490758UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249075CUL))) +#define bM4_TMR42_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42490760UL))) +#define bM4_TMR42_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42490764UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42490768UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249076CUL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42490770UL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42490774UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42490778UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249077CUL))) +#define bM4_TMR42_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42490900UL))) +#define bM4_TMR42_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42490904UL))) +#define bM4_TMR42_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42490908UL))) +#define bM4_TMR42_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249090CUL))) +#define bM4_TMR42_CCSR_CLEAR (*((volatile unsigned int*)(0x42490910UL))) +#define bM4_TMR42_CCSR_MODE (*((volatile unsigned int*)(0x42490914UL))) +#define bM4_TMR42_CCSR_STOP (*((volatile unsigned int*)(0x42490918UL))) +#define bM4_TMR42_CCSR_BUFEN (*((volatile unsigned int*)(0x4249091CUL))) +#define bM4_TMR42_CCSR_IRQPEN (*((volatile unsigned int*)(0x42490920UL))) +#define bM4_TMR42_CCSR_IRQPF (*((volatile unsigned int*)(0x42490924UL))) +#define bM4_TMR42_CCSR_IRQZEN (*((volatile unsigned int*)(0x42490934UL))) +#define bM4_TMR42_CCSR_IRQZF (*((volatile unsigned int*)(0x42490938UL))) +#define bM4_TMR42_CCSR_ECKEN (*((volatile unsigned int*)(0x4249093CUL))) +#define bM4_TMR42_CVPR_ZIM0 (*((volatile unsigned int*)(0x42490940UL))) +#define bM4_TMR42_CVPR_ZIM1 (*((volatile unsigned int*)(0x42490944UL))) +#define bM4_TMR42_CVPR_ZIM2 (*((volatile unsigned int*)(0x42490948UL))) +#define bM4_TMR42_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249094CUL))) +#define bM4_TMR42_CVPR_PIM0 (*((volatile unsigned int*)(0x42490950UL))) +#define bM4_TMR42_CVPR_PIM1 (*((volatile unsigned int*)(0x42490954UL))) +#define bM4_TMR42_CVPR_PIM2 (*((volatile unsigned int*)(0x42490958UL))) +#define bM4_TMR42_CVPR_PIM3 (*((volatile unsigned int*)(0x4249095CUL))) +#define bM4_TMR42_CVPR_ZIC0 (*((volatile unsigned int*)(0x42490960UL))) +#define bM4_TMR42_CVPR_ZIC1 (*((volatile unsigned int*)(0x42490964UL))) +#define bM4_TMR42_CVPR_ZIC2 (*((volatile unsigned int*)(0x42490968UL))) +#define bM4_TMR42_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249096CUL))) +#define bM4_TMR42_CVPR_PIC0 (*((volatile unsigned int*)(0x42490970UL))) +#define bM4_TMR42_CVPR_PIC1 (*((volatile unsigned int*)(0x42490974UL))) +#define bM4_TMR42_CVPR_PIC2 (*((volatile unsigned int*)(0x42490978UL))) +#define bM4_TMR42_CVPR_PIC3 (*((volatile unsigned int*)(0x4249097CUL))) +#define bM4_TMR42_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42491300UL))) +#define bM4_TMR42_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42491304UL))) +#define bM4_TMR42_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42491308UL))) +#define bM4_TMR42_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249130CUL))) +#define bM4_TMR42_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42491310UL))) +#define bM4_TMR42_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42491314UL))) +#define bM4_TMR42_POCRU_LVLS0 (*((volatile unsigned int*)(0x42491318UL))) +#define bM4_TMR42_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249131CUL))) +#define bM4_TMR42_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42491380UL))) +#define bM4_TMR42_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42491384UL))) +#define bM4_TMR42_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42491388UL))) +#define bM4_TMR42_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249138CUL))) +#define bM4_TMR42_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42491390UL))) +#define bM4_TMR42_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42491394UL))) +#define bM4_TMR42_POCRV_LVLS0 (*((volatile unsigned int*)(0x42491398UL))) +#define bM4_TMR42_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249139CUL))) +#define bM4_TMR42_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42491400UL))) +#define bM4_TMR42_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42491404UL))) +#define bM4_TMR42_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42491408UL))) +#define bM4_TMR42_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249140CUL))) +#define bM4_TMR42_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42491410UL))) +#define bM4_TMR42_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42491414UL))) +#define bM4_TMR42_POCRW_LVLS0 (*((volatile unsigned int*)(0x42491418UL))) +#define bM4_TMR42_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249141CUL))) +#define bM4_TMR42_RCSR_RTIDU (*((volatile unsigned int*)(0x42491480UL))) +#define bM4_TMR42_RCSR_RTIDV (*((volatile unsigned int*)(0x42491484UL))) +#define bM4_TMR42_RCSR_RTIDW (*((volatile unsigned int*)(0x42491488UL))) +#define bM4_TMR42_RCSR_RTIFU (*((volatile unsigned int*)(0x42491490UL))) +#define bM4_TMR42_RCSR_RTICU (*((volatile unsigned int*)(0x42491494UL))) +#define bM4_TMR42_RCSR_RTEU (*((volatile unsigned int*)(0x42491498UL))) +#define bM4_TMR42_RCSR_RTSU (*((volatile unsigned int*)(0x4249149CUL))) +#define bM4_TMR42_RCSR_RTIFV (*((volatile unsigned int*)(0x424914A0UL))) +#define bM4_TMR42_RCSR_RTICV (*((volatile unsigned int*)(0x424914A4UL))) +#define bM4_TMR42_RCSR_RTEV (*((volatile unsigned int*)(0x424914A8UL))) +#define bM4_TMR42_RCSR_RTSV (*((volatile unsigned int*)(0x424914ACUL))) +#define bM4_TMR42_RCSR_RTIFW (*((volatile unsigned int*)(0x424914B0UL))) +#define bM4_TMR42_RCSR_RTICW (*((volatile unsigned int*)(0x424914B4UL))) +#define bM4_TMR42_RCSR_RTEW (*((volatile unsigned int*)(0x424914B8UL))) +#define bM4_TMR42_RCSR_RTSW (*((volatile unsigned int*)(0x424914BCUL))) +#define bM4_TMR42_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42491900UL))) +#define bM4_TMR42_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42491904UL))) +#define bM4_TMR42_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42491908UL))) +#define bM4_TMR42_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249190CUL))) +#define bM4_TMR42_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42491910UL))) +#define bM4_TMR42_SCSRUH_LMC (*((volatile unsigned int*)(0x42491914UL))) +#define bM4_TMR42_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42491920UL))) +#define bM4_TMR42_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42491924UL))) +#define bM4_TMR42_SCSRUH_DEN (*((volatile unsigned int*)(0x42491930UL))) +#define bM4_TMR42_SCSRUH_PEN (*((volatile unsigned int*)(0x42491934UL))) +#define bM4_TMR42_SCSRUH_UEN (*((volatile unsigned int*)(0x42491938UL))) +#define bM4_TMR42_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249193CUL))) +#define bM4_TMR42_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42491940UL))) +#define bM4_TMR42_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42491944UL))) +#define bM4_TMR42_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42491948UL))) +#define bM4_TMR42_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249194CUL))) +#define bM4_TMR42_SCMRUH_MZCE (*((volatile unsigned int*)(0x42491958UL))) +#define bM4_TMR42_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249195CUL))) +#define bM4_TMR42_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42491980UL))) +#define bM4_TMR42_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42491984UL))) +#define bM4_TMR42_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42491988UL))) +#define bM4_TMR42_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249198CUL))) +#define bM4_TMR42_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42491990UL))) +#define bM4_TMR42_SCSRUL_LMC (*((volatile unsigned int*)(0x42491994UL))) +#define bM4_TMR42_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424919A0UL))) +#define bM4_TMR42_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424919A4UL))) +#define bM4_TMR42_SCSRUL_DEN (*((volatile unsigned int*)(0x424919B0UL))) +#define bM4_TMR42_SCSRUL_PEN (*((volatile unsigned int*)(0x424919B4UL))) +#define bM4_TMR42_SCSRUL_UEN (*((volatile unsigned int*)(0x424919B8UL))) +#define bM4_TMR42_SCSRUL_ZEN (*((volatile unsigned int*)(0x424919BCUL))) +#define bM4_TMR42_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424919C0UL))) +#define bM4_TMR42_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424919C4UL))) +#define bM4_TMR42_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424919C8UL))) +#define bM4_TMR42_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424919CCUL))) +#define bM4_TMR42_SCMRUL_MZCE (*((volatile unsigned int*)(0x424919D8UL))) +#define bM4_TMR42_SCMRUL_MPCE (*((volatile unsigned int*)(0x424919DCUL))) +#define bM4_TMR42_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42491A00UL))) +#define bM4_TMR42_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42491A04UL))) +#define bM4_TMR42_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42491A08UL))) +#define bM4_TMR42_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42491A0CUL))) +#define bM4_TMR42_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42491A10UL))) +#define bM4_TMR42_SCSRVH_LMC (*((volatile unsigned int*)(0x42491A14UL))) +#define bM4_TMR42_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42491A20UL))) +#define bM4_TMR42_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42491A24UL))) +#define bM4_TMR42_SCSRVH_DEN (*((volatile unsigned int*)(0x42491A30UL))) +#define bM4_TMR42_SCSRVH_PEN (*((volatile unsigned int*)(0x42491A34UL))) +#define bM4_TMR42_SCSRVH_UEN (*((volatile unsigned int*)(0x42491A38UL))) +#define bM4_TMR42_SCSRVH_ZEN (*((volatile unsigned int*)(0x42491A3CUL))) +#define bM4_TMR42_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42491A40UL))) +#define bM4_TMR42_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42491A44UL))) +#define bM4_TMR42_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42491A48UL))) +#define bM4_TMR42_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42491A4CUL))) +#define bM4_TMR42_SCMRVH_MZCE (*((volatile unsigned int*)(0x42491A58UL))) +#define bM4_TMR42_SCMRVH_MPCE (*((volatile unsigned int*)(0x42491A5CUL))) +#define bM4_TMR42_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42491A80UL))) +#define bM4_TMR42_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42491A84UL))) +#define bM4_TMR42_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42491A88UL))) +#define bM4_TMR42_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42491A8CUL))) +#define bM4_TMR42_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42491A90UL))) +#define bM4_TMR42_SCSRVL_LMC (*((volatile unsigned int*)(0x42491A94UL))) +#define bM4_TMR42_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42491AA0UL))) +#define bM4_TMR42_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42491AA4UL))) +#define bM4_TMR42_SCSRVL_DEN (*((volatile unsigned int*)(0x42491AB0UL))) +#define bM4_TMR42_SCSRVL_PEN (*((volatile unsigned int*)(0x42491AB4UL))) +#define bM4_TMR42_SCSRVL_UEN (*((volatile unsigned int*)(0x42491AB8UL))) +#define bM4_TMR42_SCSRVL_ZEN (*((volatile unsigned int*)(0x42491ABCUL))) +#define bM4_TMR42_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42491AC0UL))) +#define bM4_TMR42_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42491AC4UL))) +#define bM4_TMR42_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42491AC8UL))) +#define bM4_TMR42_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42491ACCUL))) +#define bM4_TMR42_SCMRVL_MZCE (*((volatile unsigned int*)(0x42491AD8UL))) +#define bM4_TMR42_SCMRVL_MPCE (*((volatile unsigned int*)(0x42491ADCUL))) +#define bM4_TMR42_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42491B00UL))) +#define bM4_TMR42_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42491B04UL))) +#define bM4_TMR42_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42491B08UL))) +#define bM4_TMR42_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42491B0CUL))) +#define bM4_TMR42_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42491B10UL))) +#define bM4_TMR42_SCSRWH_LMC (*((volatile unsigned int*)(0x42491B14UL))) +#define bM4_TMR42_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42491B20UL))) +#define bM4_TMR42_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42491B24UL))) +#define bM4_TMR42_SCSRWH_DEN (*((volatile unsigned int*)(0x42491B30UL))) +#define bM4_TMR42_SCSRWH_PEN (*((volatile unsigned int*)(0x42491B34UL))) +#define bM4_TMR42_SCSRWH_UEN (*((volatile unsigned int*)(0x42491B38UL))) +#define bM4_TMR42_SCSRWH_ZEN (*((volatile unsigned int*)(0x42491B3CUL))) +#define bM4_TMR42_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42491B40UL))) +#define bM4_TMR42_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42491B44UL))) +#define bM4_TMR42_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42491B48UL))) +#define bM4_TMR42_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42491B4CUL))) +#define bM4_TMR42_SCMRWH_MZCE (*((volatile unsigned int*)(0x42491B58UL))) +#define bM4_TMR42_SCMRWH_MPCE (*((volatile unsigned int*)(0x42491B5CUL))) +#define bM4_TMR42_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42491B80UL))) +#define bM4_TMR42_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42491B84UL))) +#define bM4_TMR42_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42491B88UL))) +#define bM4_TMR42_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42491B8CUL))) +#define bM4_TMR42_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42491B90UL))) +#define bM4_TMR42_SCSRWL_LMC (*((volatile unsigned int*)(0x42491B94UL))) +#define bM4_TMR42_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42491BA0UL))) +#define bM4_TMR42_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42491BA4UL))) +#define bM4_TMR42_SCSRWL_DEN (*((volatile unsigned int*)(0x42491BB0UL))) +#define bM4_TMR42_SCSRWL_PEN (*((volatile unsigned int*)(0x42491BB4UL))) +#define bM4_TMR42_SCSRWL_UEN (*((volatile unsigned int*)(0x42491BB8UL))) +#define bM4_TMR42_SCSRWL_ZEN (*((volatile unsigned int*)(0x42491BBCUL))) +#define bM4_TMR42_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42491BC0UL))) +#define bM4_TMR42_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42491BC4UL))) +#define bM4_TMR42_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42491BC8UL))) +#define bM4_TMR42_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42491BCCUL))) +#define bM4_TMR42_SCMRWL_MZCE (*((volatile unsigned int*)(0x42491BD8UL))) +#define bM4_TMR42_SCMRWL_MPCE (*((volatile unsigned int*)(0x42491BDCUL))) +#define bM4_TMR42_ECSR_HOLD (*((volatile unsigned int*)(0x42491E1CUL))) +#define bM4_TMR43_OCSRU_OCEH (*((volatile unsigned int*)(0x42498300UL))) +#define bM4_TMR43_OCSRU_OCEL (*((volatile unsigned int*)(0x42498304UL))) +#define bM4_TMR43_OCSRU_OCPH (*((volatile unsigned int*)(0x42498308UL))) +#define bM4_TMR43_OCSRU_OCPL (*((volatile unsigned int*)(0x4249830CUL))) +#define bM4_TMR43_OCSRU_OCIEH (*((volatile unsigned int*)(0x42498310UL))) +#define bM4_TMR43_OCSRU_OCIEL (*((volatile unsigned int*)(0x42498314UL))) +#define bM4_TMR43_OCSRU_OCFH (*((volatile unsigned int*)(0x42498318UL))) +#define bM4_TMR43_OCSRU_OCFL (*((volatile unsigned int*)(0x4249831CUL))) +#define bM4_TMR43_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42498340UL))) +#define bM4_TMR43_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42498344UL))) +#define bM4_TMR43_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42498348UL))) +#define bM4_TMR43_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249834CUL))) +#define bM4_TMR43_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42498350UL))) +#define bM4_TMR43_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42498354UL))) +#define bM4_TMR43_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42498358UL))) +#define bM4_TMR43_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249835CUL))) +#define bM4_TMR43_OCERU_LMCH (*((volatile unsigned int*)(0x42498360UL))) +#define bM4_TMR43_OCERU_LMCL (*((volatile unsigned int*)(0x42498364UL))) +#define bM4_TMR43_OCERU_LMMH (*((volatile unsigned int*)(0x42498368UL))) +#define bM4_TMR43_OCERU_LMML (*((volatile unsigned int*)(0x4249836CUL))) +#define bM4_TMR43_OCERU_MCECH (*((volatile unsigned int*)(0x42498370UL))) +#define bM4_TMR43_OCERU_MCECL (*((volatile unsigned int*)(0x42498374UL))) +#define bM4_TMR43_OCSRV_OCEH (*((volatile unsigned int*)(0x42498380UL))) +#define bM4_TMR43_OCSRV_OCEL (*((volatile unsigned int*)(0x42498384UL))) +#define bM4_TMR43_OCSRV_OCPH (*((volatile unsigned int*)(0x42498388UL))) +#define bM4_TMR43_OCSRV_OCPL (*((volatile unsigned int*)(0x4249838CUL))) +#define bM4_TMR43_OCSRV_OCIEH (*((volatile unsigned int*)(0x42498390UL))) +#define bM4_TMR43_OCSRV_OCIEL (*((volatile unsigned int*)(0x42498394UL))) +#define bM4_TMR43_OCSRV_OCFH (*((volatile unsigned int*)(0x42498398UL))) +#define bM4_TMR43_OCSRV_OCFL (*((volatile unsigned int*)(0x4249839CUL))) +#define bM4_TMR43_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424983C0UL))) +#define bM4_TMR43_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424983C4UL))) +#define bM4_TMR43_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424983C8UL))) +#define bM4_TMR43_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424983CCUL))) +#define bM4_TMR43_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424983D0UL))) +#define bM4_TMR43_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424983D4UL))) +#define bM4_TMR43_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424983D8UL))) +#define bM4_TMR43_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424983DCUL))) +#define bM4_TMR43_OCERV_LMCH (*((volatile unsigned int*)(0x424983E0UL))) +#define bM4_TMR43_OCERV_LMCL (*((volatile unsigned int*)(0x424983E4UL))) +#define bM4_TMR43_OCERV_LMMH (*((volatile unsigned int*)(0x424983E8UL))) +#define bM4_TMR43_OCERV_LMML (*((volatile unsigned int*)(0x424983ECUL))) +#define bM4_TMR43_OCERV_MCECH (*((volatile unsigned int*)(0x424983F0UL))) +#define bM4_TMR43_OCERV_MCECL (*((volatile unsigned int*)(0x424983F4UL))) +#define bM4_TMR43_OCSRW_OCEH (*((volatile unsigned int*)(0x42498400UL))) +#define bM4_TMR43_OCSRW_OCEL (*((volatile unsigned int*)(0x42498404UL))) +#define bM4_TMR43_OCSRW_OCPH (*((volatile unsigned int*)(0x42498408UL))) +#define bM4_TMR43_OCSRW_OCPL (*((volatile unsigned int*)(0x4249840CUL))) +#define bM4_TMR43_OCSRW_OCIEH (*((volatile unsigned int*)(0x42498410UL))) +#define bM4_TMR43_OCSRW_OCIEL (*((volatile unsigned int*)(0x42498414UL))) +#define bM4_TMR43_OCSRW_OCFH (*((volatile unsigned int*)(0x42498418UL))) +#define bM4_TMR43_OCSRW_OCFL (*((volatile unsigned int*)(0x4249841CUL))) +#define bM4_TMR43_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42498440UL))) +#define bM4_TMR43_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42498444UL))) +#define bM4_TMR43_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42498448UL))) +#define bM4_TMR43_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249844CUL))) +#define bM4_TMR43_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42498450UL))) +#define bM4_TMR43_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42498454UL))) +#define bM4_TMR43_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42498458UL))) +#define bM4_TMR43_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249845CUL))) +#define bM4_TMR43_OCERW_LMCH (*((volatile unsigned int*)(0x42498460UL))) +#define bM4_TMR43_OCERW_LMCL (*((volatile unsigned int*)(0x42498464UL))) +#define bM4_TMR43_OCERW_LMMH (*((volatile unsigned int*)(0x42498468UL))) +#define bM4_TMR43_OCERW_LMML (*((volatile unsigned int*)(0x4249846CUL))) +#define bM4_TMR43_OCERW_MCECH (*((volatile unsigned int*)(0x42498470UL))) +#define bM4_TMR43_OCERW_MCECL (*((volatile unsigned int*)(0x42498474UL))) +#define bM4_TMR43_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42498480UL))) +#define bM4_TMR43_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42498484UL))) +#define bM4_TMR43_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42498488UL))) +#define bM4_TMR43_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249848CUL))) +#define bM4_TMR43_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42498490UL))) +#define bM4_TMR43_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42498494UL))) +#define bM4_TMR43_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42498498UL))) +#define bM4_TMR43_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249849CUL))) +#define bM4_TMR43_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424984A0UL))) +#define bM4_TMR43_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424984A4UL))) +#define bM4_TMR43_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424984A8UL))) +#define bM4_TMR43_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424984ACUL))) +#define bM4_TMR43_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424984B0UL))) +#define bM4_TMR43_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424984B4UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424984B8UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424984BCUL))) +#define bM4_TMR43_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42498500UL))) +#define bM4_TMR43_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42498504UL))) +#define bM4_TMR43_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42498508UL))) +#define bM4_TMR43_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249850CUL))) +#define bM4_TMR43_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42498510UL))) +#define bM4_TMR43_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42498514UL))) +#define bM4_TMR43_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42498518UL))) +#define bM4_TMR43_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249851CUL))) +#define bM4_TMR43_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42498520UL))) +#define bM4_TMR43_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42498524UL))) +#define bM4_TMR43_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42498528UL))) +#define bM4_TMR43_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249852CUL))) +#define bM4_TMR43_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42498530UL))) +#define bM4_TMR43_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42498534UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42498538UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249853CUL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42498540UL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42498544UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42498548UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249854CUL))) +#define bM4_TMR43_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42498550UL))) +#define bM4_TMR43_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42498554UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42498558UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249855CUL))) +#define bM4_TMR43_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42498560UL))) +#define bM4_TMR43_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42498564UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42498568UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249856CUL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42498570UL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42498574UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42498578UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249857CUL))) +#define bM4_TMR43_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42498580UL))) +#define bM4_TMR43_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42498584UL))) +#define bM4_TMR43_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42498588UL))) +#define bM4_TMR43_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249858CUL))) +#define bM4_TMR43_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42498590UL))) +#define bM4_TMR43_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42498594UL))) +#define bM4_TMR43_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42498598UL))) +#define bM4_TMR43_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249859CUL))) +#define bM4_TMR43_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424985A0UL))) +#define bM4_TMR43_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424985A4UL))) +#define bM4_TMR43_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424985A8UL))) +#define bM4_TMR43_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424985ACUL))) +#define bM4_TMR43_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424985B0UL))) +#define bM4_TMR43_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424985B4UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424985B8UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424985BCUL))) +#define bM4_TMR43_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42498600UL))) +#define bM4_TMR43_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42498604UL))) +#define bM4_TMR43_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42498608UL))) +#define bM4_TMR43_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249860CUL))) +#define bM4_TMR43_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42498610UL))) +#define bM4_TMR43_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42498614UL))) +#define bM4_TMR43_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42498618UL))) +#define bM4_TMR43_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249861CUL))) +#define bM4_TMR43_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42498620UL))) +#define bM4_TMR43_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42498624UL))) +#define bM4_TMR43_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42498628UL))) +#define bM4_TMR43_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249862CUL))) +#define bM4_TMR43_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42498630UL))) +#define bM4_TMR43_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42498634UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42498638UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249863CUL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42498640UL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42498644UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42498648UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249864CUL))) +#define bM4_TMR43_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42498650UL))) +#define bM4_TMR43_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42498654UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42498658UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249865CUL))) +#define bM4_TMR43_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42498660UL))) +#define bM4_TMR43_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42498664UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42498668UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249866CUL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42498670UL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42498674UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42498678UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249867CUL))) +#define bM4_TMR43_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42498680UL))) +#define bM4_TMR43_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42498684UL))) +#define bM4_TMR43_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42498688UL))) +#define bM4_TMR43_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249868CUL))) +#define bM4_TMR43_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42498690UL))) +#define bM4_TMR43_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42498694UL))) +#define bM4_TMR43_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42498698UL))) +#define bM4_TMR43_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249869CUL))) +#define bM4_TMR43_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424986A0UL))) +#define bM4_TMR43_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424986A4UL))) +#define bM4_TMR43_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424986A8UL))) +#define bM4_TMR43_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424986ACUL))) +#define bM4_TMR43_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424986B0UL))) +#define bM4_TMR43_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424986B4UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424986B8UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424986BCUL))) +#define bM4_TMR43_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42498700UL))) +#define bM4_TMR43_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42498704UL))) +#define bM4_TMR43_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42498708UL))) +#define bM4_TMR43_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249870CUL))) +#define bM4_TMR43_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42498710UL))) +#define bM4_TMR43_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42498714UL))) +#define bM4_TMR43_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42498718UL))) +#define bM4_TMR43_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249871CUL))) +#define bM4_TMR43_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42498720UL))) +#define bM4_TMR43_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42498724UL))) +#define bM4_TMR43_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42498728UL))) +#define bM4_TMR43_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249872CUL))) +#define bM4_TMR43_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42498730UL))) +#define bM4_TMR43_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42498734UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42498738UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249873CUL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42498740UL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42498744UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42498748UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249874CUL))) +#define bM4_TMR43_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42498750UL))) +#define bM4_TMR43_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42498754UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42498758UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249875CUL))) +#define bM4_TMR43_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42498760UL))) +#define bM4_TMR43_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42498764UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42498768UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249876CUL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42498770UL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42498774UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42498778UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249877CUL))) +#define bM4_TMR43_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42498900UL))) +#define bM4_TMR43_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42498904UL))) +#define bM4_TMR43_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42498908UL))) +#define bM4_TMR43_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249890CUL))) +#define bM4_TMR43_CCSR_CLEAR (*((volatile unsigned int*)(0x42498910UL))) +#define bM4_TMR43_CCSR_MODE (*((volatile unsigned int*)(0x42498914UL))) +#define bM4_TMR43_CCSR_STOP (*((volatile unsigned int*)(0x42498918UL))) +#define bM4_TMR43_CCSR_BUFEN (*((volatile unsigned int*)(0x4249891CUL))) +#define bM4_TMR43_CCSR_IRQPEN (*((volatile unsigned int*)(0x42498920UL))) +#define bM4_TMR43_CCSR_IRQPF (*((volatile unsigned int*)(0x42498924UL))) +#define bM4_TMR43_CCSR_IRQZEN (*((volatile unsigned int*)(0x42498934UL))) +#define bM4_TMR43_CCSR_IRQZF (*((volatile unsigned int*)(0x42498938UL))) +#define bM4_TMR43_CCSR_ECKEN (*((volatile unsigned int*)(0x4249893CUL))) +#define bM4_TMR43_CVPR_ZIM0 (*((volatile unsigned int*)(0x42498940UL))) +#define bM4_TMR43_CVPR_ZIM1 (*((volatile unsigned int*)(0x42498944UL))) +#define bM4_TMR43_CVPR_ZIM2 (*((volatile unsigned int*)(0x42498948UL))) +#define bM4_TMR43_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249894CUL))) +#define bM4_TMR43_CVPR_PIM0 (*((volatile unsigned int*)(0x42498950UL))) +#define bM4_TMR43_CVPR_PIM1 (*((volatile unsigned int*)(0x42498954UL))) +#define bM4_TMR43_CVPR_PIM2 (*((volatile unsigned int*)(0x42498958UL))) +#define bM4_TMR43_CVPR_PIM3 (*((volatile unsigned int*)(0x4249895CUL))) +#define bM4_TMR43_CVPR_ZIC0 (*((volatile unsigned int*)(0x42498960UL))) +#define bM4_TMR43_CVPR_ZIC1 (*((volatile unsigned int*)(0x42498964UL))) +#define bM4_TMR43_CVPR_ZIC2 (*((volatile unsigned int*)(0x42498968UL))) +#define bM4_TMR43_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249896CUL))) +#define bM4_TMR43_CVPR_PIC0 (*((volatile unsigned int*)(0x42498970UL))) +#define bM4_TMR43_CVPR_PIC1 (*((volatile unsigned int*)(0x42498974UL))) +#define bM4_TMR43_CVPR_PIC2 (*((volatile unsigned int*)(0x42498978UL))) +#define bM4_TMR43_CVPR_PIC3 (*((volatile unsigned int*)(0x4249897CUL))) +#define bM4_TMR43_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42499300UL))) +#define bM4_TMR43_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42499304UL))) +#define bM4_TMR43_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42499308UL))) +#define bM4_TMR43_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249930CUL))) +#define bM4_TMR43_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42499310UL))) +#define bM4_TMR43_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42499314UL))) +#define bM4_TMR43_POCRU_LVLS0 (*((volatile unsigned int*)(0x42499318UL))) +#define bM4_TMR43_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249931CUL))) +#define bM4_TMR43_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42499380UL))) +#define bM4_TMR43_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42499384UL))) +#define bM4_TMR43_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42499388UL))) +#define bM4_TMR43_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249938CUL))) +#define bM4_TMR43_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42499390UL))) +#define bM4_TMR43_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42499394UL))) +#define bM4_TMR43_POCRV_LVLS0 (*((volatile unsigned int*)(0x42499398UL))) +#define bM4_TMR43_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249939CUL))) +#define bM4_TMR43_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42499400UL))) +#define bM4_TMR43_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42499404UL))) +#define bM4_TMR43_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42499408UL))) +#define bM4_TMR43_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249940CUL))) +#define bM4_TMR43_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42499410UL))) +#define bM4_TMR43_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42499414UL))) +#define bM4_TMR43_POCRW_LVLS0 (*((volatile unsigned int*)(0x42499418UL))) +#define bM4_TMR43_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249941CUL))) +#define bM4_TMR43_RCSR_RTIDU (*((volatile unsigned int*)(0x42499480UL))) +#define bM4_TMR43_RCSR_RTIDV (*((volatile unsigned int*)(0x42499484UL))) +#define bM4_TMR43_RCSR_RTIDW (*((volatile unsigned int*)(0x42499488UL))) +#define bM4_TMR43_RCSR_RTIFU (*((volatile unsigned int*)(0x42499490UL))) +#define bM4_TMR43_RCSR_RTICU (*((volatile unsigned int*)(0x42499494UL))) +#define bM4_TMR43_RCSR_RTEU (*((volatile unsigned int*)(0x42499498UL))) +#define bM4_TMR43_RCSR_RTSU (*((volatile unsigned int*)(0x4249949CUL))) +#define bM4_TMR43_RCSR_RTIFV (*((volatile unsigned int*)(0x424994A0UL))) +#define bM4_TMR43_RCSR_RTICV (*((volatile unsigned int*)(0x424994A4UL))) +#define bM4_TMR43_RCSR_RTEV (*((volatile unsigned int*)(0x424994A8UL))) +#define bM4_TMR43_RCSR_RTSV (*((volatile unsigned int*)(0x424994ACUL))) +#define bM4_TMR43_RCSR_RTIFW (*((volatile unsigned int*)(0x424994B0UL))) +#define bM4_TMR43_RCSR_RTICW (*((volatile unsigned int*)(0x424994B4UL))) +#define bM4_TMR43_RCSR_RTEW (*((volatile unsigned int*)(0x424994B8UL))) +#define bM4_TMR43_RCSR_RTSW (*((volatile unsigned int*)(0x424994BCUL))) +#define bM4_TMR43_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42499900UL))) +#define bM4_TMR43_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42499904UL))) +#define bM4_TMR43_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42499908UL))) +#define bM4_TMR43_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249990CUL))) +#define bM4_TMR43_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42499910UL))) +#define bM4_TMR43_SCSRUH_LMC (*((volatile unsigned int*)(0x42499914UL))) +#define bM4_TMR43_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42499920UL))) +#define bM4_TMR43_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42499924UL))) +#define bM4_TMR43_SCSRUH_DEN (*((volatile unsigned int*)(0x42499930UL))) +#define bM4_TMR43_SCSRUH_PEN (*((volatile unsigned int*)(0x42499934UL))) +#define bM4_TMR43_SCSRUH_UEN (*((volatile unsigned int*)(0x42499938UL))) +#define bM4_TMR43_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249993CUL))) +#define bM4_TMR43_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42499940UL))) +#define bM4_TMR43_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42499944UL))) +#define bM4_TMR43_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42499948UL))) +#define bM4_TMR43_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249994CUL))) +#define bM4_TMR43_SCMRUH_MZCE (*((volatile unsigned int*)(0x42499958UL))) +#define bM4_TMR43_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249995CUL))) +#define bM4_TMR43_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42499980UL))) +#define bM4_TMR43_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42499984UL))) +#define bM4_TMR43_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42499988UL))) +#define bM4_TMR43_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249998CUL))) +#define bM4_TMR43_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42499990UL))) +#define bM4_TMR43_SCSRUL_LMC (*((volatile unsigned int*)(0x42499994UL))) +#define bM4_TMR43_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424999A0UL))) +#define bM4_TMR43_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424999A4UL))) +#define bM4_TMR43_SCSRUL_DEN (*((volatile unsigned int*)(0x424999B0UL))) +#define bM4_TMR43_SCSRUL_PEN (*((volatile unsigned int*)(0x424999B4UL))) +#define bM4_TMR43_SCSRUL_UEN (*((volatile unsigned int*)(0x424999B8UL))) +#define bM4_TMR43_SCSRUL_ZEN (*((volatile unsigned int*)(0x424999BCUL))) +#define bM4_TMR43_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424999C0UL))) +#define bM4_TMR43_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424999C4UL))) +#define bM4_TMR43_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424999C8UL))) +#define bM4_TMR43_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424999CCUL))) +#define bM4_TMR43_SCMRUL_MZCE (*((volatile unsigned int*)(0x424999D8UL))) +#define bM4_TMR43_SCMRUL_MPCE (*((volatile unsigned int*)(0x424999DCUL))) +#define bM4_TMR43_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42499A00UL))) +#define bM4_TMR43_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42499A04UL))) +#define bM4_TMR43_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42499A08UL))) +#define bM4_TMR43_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42499A0CUL))) +#define bM4_TMR43_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42499A10UL))) +#define bM4_TMR43_SCSRVH_LMC (*((volatile unsigned int*)(0x42499A14UL))) +#define bM4_TMR43_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42499A20UL))) +#define bM4_TMR43_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42499A24UL))) +#define bM4_TMR43_SCSRVH_DEN (*((volatile unsigned int*)(0x42499A30UL))) +#define bM4_TMR43_SCSRVH_PEN (*((volatile unsigned int*)(0x42499A34UL))) +#define bM4_TMR43_SCSRVH_UEN (*((volatile unsigned int*)(0x42499A38UL))) +#define bM4_TMR43_SCSRVH_ZEN (*((volatile unsigned int*)(0x42499A3CUL))) +#define bM4_TMR43_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42499A40UL))) +#define bM4_TMR43_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42499A44UL))) +#define bM4_TMR43_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42499A48UL))) +#define bM4_TMR43_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42499A4CUL))) +#define bM4_TMR43_SCMRVH_MZCE (*((volatile unsigned int*)(0x42499A58UL))) +#define bM4_TMR43_SCMRVH_MPCE (*((volatile unsigned int*)(0x42499A5CUL))) +#define bM4_TMR43_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42499A80UL))) +#define bM4_TMR43_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42499A84UL))) +#define bM4_TMR43_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42499A88UL))) +#define bM4_TMR43_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42499A8CUL))) +#define bM4_TMR43_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42499A90UL))) +#define bM4_TMR43_SCSRVL_LMC (*((volatile unsigned int*)(0x42499A94UL))) +#define bM4_TMR43_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42499AA0UL))) +#define bM4_TMR43_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42499AA4UL))) +#define bM4_TMR43_SCSRVL_DEN (*((volatile unsigned int*)(0x42499AB0UL))) +#define bM4_TMR43_SCSRVL_PEN (*((volatile unsigned int*)(0x42499AB4UL))) +#define bM4_TMR43_SCSRVL_UEN (*((volatile unsigned int*)(0x42499AB8UL))) +#define bM4_TMR43_SCSRVL_ZEN (*((volatile unsigned int*)(0x42499ABCUL))) +#define bM4_TMR43_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42499AC0UL))) +#define bM4_TMR43_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42499AC4UL))) +#define bM4_TMR43_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42499AC8UL))) +#define bM4_TMR43_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42499ACCUL))) +#define bM4_TMR43_SCMRVL_MZCE (*((volatile unsigned int*)(0x42499AD8UL))) +#define bM4_TMR43_SCMRVL_MPCE (*((volatile unsigned int*)(0x42499ADCUL))) +#define bM4_TMR43_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42499B00UL))) +#define bM4_TMR43_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42499B04UL))) +#define bM4_TMR43_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42499B08UL))) +#define bM4_TMR43_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42499B0CUL))) +#define bM4_TMR43_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42499B10UL))) +#define bM4_TMR43_SCSRWH_LMC (*((volatile unsigned int*)(0x42499B14UL))) +#define bM4_TMR43_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42499B20UL))) +#define bM4_TMR43_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42499B24UL))) +#define bM4_TMR43_SCSRWH_DEN (*((volatile unsigned int*)(0x42499B30UL))) +#define bM4_TMR43_SCSRWH_PEN (*((volatile unsigned int*)(0x42499B34UL))) +#define bM4_TMR43_SCSRWH_UEN (*((volatile unsigned int*)(0x42499B38UL))) +#define bM4_TMR43_SCSRWH_ZEN (*((volatile unsigned int*)(0x42499B3CUL))) +#define bM4_TMR43_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42499B40UL))) +#define bM4_TMR43_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42499B44UL))) +#define bM4_TMR43_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42499B48UL))) +#define bM4_TMR43_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42499B4CUL))) +#define bM4_TMR43_SCMRWH_MZCE (*((volatile unsigned int*)(0x42499B58UL))) +#define bM4_TMR43_SCMRWH_MPCE (*((volatile unsigned int*)(0x42499B5CUL))) +#define bM4_TMR43_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42499B80UL))) +#define bM4_TMR43_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42499B84UL))) +#define bM4_TMR43_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42499B88UL))) +#define bM4_TMR43_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42499B8CUL))) +#define bM4_TMR43_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42499B90UL))) +#define bM4_TMR43_SCSRWL_LMC (*((volatile unsigned int*)(0x42499B94UL))) +#define bM4_TMR43_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42499BA0UL))) +#define bM4_TMR43_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42499BA4UL))) +#define bM4_TMR43_SCSRWL_DEN (*((volatile unsigned int*)(0x42499BB0UL))) +#define bM4_TMR43_SCSRWL_PEN (*((volatile unsigned int*)(0x42499BB4UL))) +#define bM4_TMR43_SCSRWL_UEN (*((volatile unsigned int*)(0x42499BB8UL))) +#define bM4_TMR43_SCSRWL_ZEN (*((volatile unsigned int*)(0x42499BBCUL))) +#define bM4_TMR43_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42499BC0UL))) +#define bM4_TMR43_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42499BC4UL))) +#define bM4_TMR43_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42499BC8UL))) +#define bM4_TMR43_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42499BCCUL))) +#define bM4_TMR43_SCMRWL_MZCE (*((volatile unsigned int*)(0x42499BD8UL))) +#define bM4_TMR43_SCMRWL_MPCE (*((volatile unsigned int*)(0x42499BDCUL))) +#define bM4_TMR43_ECSR_HOLD (*((volatile unsigned int*)(0x42499E1CUL))) +#define bM4_TMR4_CR_ECER1_EMBVAL0 (*((volatile unsigned int*)(0x42AA8100UL))) +#define bM4_TMR4_CR_ECER1_EMBVAL1 (*((volatile unsigned int*)(0x42AA8104UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL0 (*((volatile unsigned int*)(0x42AA8180UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL1 (*((volatile unsigned int*)(0x42AA8184UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL0 (*((volatile unsigned int*)(0x42AA8200UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL1 (*((volatile unsigned int*)(0x42AA8204UL))) +#define bM4_TMR61_CNTER_CNT0 (*((volatile unsigned int*)(0x42300000UL))) +#define bM4_TMR61_CNTER_CNT1 (*((volatile unsigned int*)(0x42300004UL))) +#define bM4_TMR61_CNTER_CNT2 (*((volatile unsigned int*)(0x42300008UL))) +#define bM4_TMR61_CNTER_CNT3 (*((volatile unsigned int*)(0x4230000CUL))) +#define bM4_TMR61_CNTER_CNT4 (*((volatile unsigned int*)(0x42300010UL))) +#define bM4_TMR61_CNTER_CNT5 (*((volatile unsigned int*)(0x42300014UL))) +#define bM4_TMR61_CNTER_CNT6 (*((volatile unsigned int*)(0x42300018UL))) +#define bM4_TMR61_CNTER_CNT7 (*((volatile unsigned int*)(0x4230001CUL))) +#define bM4_TMR61_CNTER_CNT8 (*((volatile unsigned int*)(0x42300020UL))) +#define bM4_TMR61_CNTER_CNT9 (*((volatile unsigned int*)(0x42300024UL))) +#define bM4_TMR61_CNTER_CNT10 (*((volatile unsigned int*)(0x42300028UL))) +#define bM4_TMR61_CNTER_CNT11 (*((volatile unsigned int*)(0x4230002CUL))) +#define bM4_TMR61_CNTER_CNT12 (*((volatile unsigned int*)(0x42300030UL))) +#define bM4_TMR61_CNTER_CNT13 (*((volatile unsigned int*)(0x42300034UL))) +#define bM4_TMR61_CNTER_CNT14 (*((volatile unsigned int*)(0x42300038UL))) +#define bM4_TMR61_CNTER_CNT15 (*((volatile unsigned int*)(0x4230003CUL))) +#define bM4_TMR61_PERAR_PERA0 (*((volatile unsigned int*)(0x42300080UL))) +#define bM4_TMR61_PERAR_PERA1 (*((volatile unsigned int*)(0x42300084UL))) +#define bM4_TMR61_PERAR_PERA2 (*((volatile unsigned int*)(0x42300088UL))) +#define bM4_TMR61_PERAR_PERA3 (*((volatile unsigned int*)(0x4230008CUL))) +#define bM4_TMR61_PERAR_PERA4 (*((volatile unsigned int*)(0x42300090UL))) +#define bM4_TMR61_PERAR_PERA5 (*((volatile unsigned int*)(0x42300094UL))) +#define bM4_TMR61_PERAR_PERA6 (*((volatile unsigned int*)(0x42300098UL))) +#define bM4_TMR61_PERAR_PERA7 (*((volatile unsigned int*)(0x4230009CUL))) +#define bM4_TMR61_PERAR_PERA8 (*((volatile unsigned int*)(0x423000A0UL))) +#define bM4_TMR61_PERAR_PERA9 (*((volatile unsigned int*)(0x423000A4UL))) +#define bM4_TMR61_PERAR_PERA10 (*((volatile unsigned int*)(0x423000A8UL))) +#define bM4_TMR61_PERAR_PERA11 (*((volatile unsigned int*)(0x423000ACUL))) +#define bM4_TMR61_PERAR_PERA12 (*((volatile unsigned int*)(0x423000B0UL))) +#define bM4_TMR61_PERAR_PERA13 (*((volatile unsigned int*)(0x423000B4UL))) +#define bM4_TMR61_PERAR_PERA14 (*((volatile unsigned int*)(0x423000B8UL))) +#define bM4_TMR61_PERAR_PERA15 (*((volatile unsigned int*)(0x423000BCUL))) +#define bM4_TMR61_PERBR_PERB0 (*((volatile unsigned int*)(0x42300100UL))) +#define bM4_TMR61_PERBR_PERB1 (*((volatile unsigned int*)(0x42300104UL))) +#define bM4_TMR61_PERBR_PERB2 (*((volatile unsigned int*)(0x42300108UL))) +#define bM4_TMR61_PERBR_PERB3 (*((volatile unsigned int*)(0x4230010CUL))) +#define bM4_TMR61_PERBR_PERB4 (*((volatile unsigned int*)(0x42300110UL))) +#define bM4_TMR61_PERBR_PERB5 (*((volatile unsigned int*)(0x42300114UL))) +#define bM4_TMR61_PERBR_PERB6 (*((volatile unsigned int*)(0x42300118UL))) +#define bM4_TMR61_PERBR_PERB7 (*((volatile unsigned int*)(0x4230011CUL))) +#define bM4_TMR61_PERBR_PERB8 (*((volatile unsigned int*)(0x42300120UL))) +#define bM4_TMR61_PERBR_PERB9 (*((volatile unsigned int*)(0x42300124UL))) +#define bM4_TMR61_PERBR_PERB10 (*((volatile unsigned int*)(0x42300128UL))) +#define bM4_TMR61_PERBR_PERB11 (*((volatile unsigned int*)(0x4230012CUL))) +#define bM4_TMR61_PERBR_PERB12 (*((volatile unsigned int*)(0x42300130UL))) +#define bM4_TMR61_PERBR_PERB13 (*((volatile unsigned int*)(0x42300134UL))) +#define bM4_TMR61_PERBR_PERB14 (*((volatile unsigned int*)(0x42300138UL))) +#define bM4_TMR61_PERBR_PERB15 (*((volatile unsigned int*)(0x4230013CUL))) +#define bM4_TMR61_PERCR_PERC0 (*((volatile unsigned int*)(0x42300180UL))) +#define bM4_TMR61_PERCR_PERC1 (*((volatile unsigned int*)(0x42300184UL))) +#define bM4_TMR61_PERCR_PERC2 (*((volatile unsigned int*)(0x42300188UL))) +#define bM4_TMR61_PERCR_PERC3 (*((volatile unsigned int*)(0x4230018CUL))) +#define bM4_TMR61_PERCR_PERC4 (*((volatile unsigned int*)(0x42300190UL))) +#define bM4_TMR61_PERCR_PERC5 (*((volatile unsigned int*)(0x42300194UL))) +#define bM4_TMR61_PERCR_PERC6 (*((volatile unsigned int*)(0x42300198UL))) +#define bM4_TMR61_PERCR_PERC7 (*((volatile unsigned int*)(0x4230019CUL))) +#define bM4_TMR61_PERCR_PERC8 (*((volatile unsigned int*)(0x423001A0UL))) +#define bM4_TMR61_PERCR_PERC9 (*((volatile unsigned int*)(0x423001A4UL))) +#define bM4_TMR61_PERCR_PERC10 (*((volatile unsigned int*)(0x423001A8UL))) +#define bM4_TMR61_PERCR_PERC11 (*((volatile unsigned int*)(0x423001ACUL))) +#define bM4_TMR61_PERCR_PERC12 (*((volatile unsigned int*)(0x423001B0UL))) +#define bM4_TMR61_PERCR_PERC13 (*((volatile unsigned int*)(0x423001B4UL))) +#define bM4_TMR61_PERCR_PERC14 (*((volatile unsigned int*)(0x423001B8UL))) +#define bM4_TMR61_PERCR_PERC15 (*((volatile unsigned int*)(0x423001BCUL))) +#define bM4_TMR61_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42300200UL))) +#define bM4_TMR61_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42300204UL))) +#define bM4_TMR61_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42300208UL))) +#define bM4_TMR61_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230020CUL))) +#define bM4_TMR61_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42300210UL))) +#define bM4_TMR61_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42300214UL))) +#define bM4_TMR61_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42300218UL))) +#define bM4_TMR61_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230021CUL))) +#define bM4_TMR61_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42300220UL))) +#define bM4_TMR61_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42300224UL))) +#define bM4_TMR61_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42300228UL))) +#define bM4_TMR61_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230022CUL))) +#define bM4_TMR61_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42300230UL))) +#define bM4_TMR61_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42300234UL))) +#define bM4_TMR61_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42300238UL))) +#define bM4_TMR61_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230023CUL))) +#define bM4_TMR61_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42300280UL))) +#define bM4_TMR61_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42300284UL))) +#define bM4_TMR61_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42300288UL))) +#define bM4_TMR61_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230028CUL))) +#define bM4_TMR61_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42300290UL))) +#define bM4_TMR61_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42300294UL))) +#define bM4_TMR61_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42300298UL))) +#define bM4_TMR61_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230029CUL))) +#define bM4_TMR61_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423002A0UL))) +#define bM4_TMR61_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423002A4UL))) +#define bM4_TMR61_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423002A8UL))) +#define bM4_TMR61_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423002ACUL))) +#define bM4_TMR61_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423002B0UL))) +#define bM4_TMR61_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423002B4UL))) +#define bM4_TMR61_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423002B8UL))) +#define bM4_TMR61_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423002BCUL))) +#define bM4_TMR61_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42300300UL))) +#define bM4_TMR61_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42300304UL))) +#define bM4_TMR61_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42300308UL))) +#define bM4_TMR61_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230030CUL))) +#define bM4_TMR61_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42300310UL))) +#define bM4_TMR61_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42300314UL))) +#define bM4_TMR61_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42300318UL))) +#define bM4_TMR61_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230031CUL))) +#define bM4_TMR61_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42300320UL))) +#define bM4_TMR61_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42300324UL))) +#define bM4_TMR61_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42300328UL))) +#define bM4_TMR61_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230032CUL))) +#define bM4_TMR61_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42300330UL))) +#define bM4_TMR61_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42300334UL))) +#define bM4_TMR61_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42300338UL))) +#define bM4_TMR61_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230033CUL))) +#define bM4_TMR61_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42300380UL))) +#define bM4_TMR61_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42300384UL))) +#define bM4_TMR61_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42300388UL))) +#define bM4_TMR61_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230038CUL))) +#define bM4_TMR61_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42300390UL))) +#define bM4_TMR61_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42300394UL))) +#define bM4_TMR61_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42300398UL))) +#define bM4_TMR61_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230039CUL))) +#define bM4_TMR61_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423003A0UL))) +#define bM4_TMR61_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423003A4UL))) +#define bM4_TMR61_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423003A8UL))) +#define bM4_TMR61_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423003ACUL))) +#define bM4_TMR61_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423003B0UL))) +#define bM4_TMR61_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423003B4UL))) +#define bM4_TMR61_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423003B8UL))) +#define bM4_TMR61_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423003BCUL))) +#define bM4_TMR61_GCMER_GCME0 (*((volatile unsigned int*)(0x42300400UL))) +#define bM4_TMR61_GCMER_GCME1 (*((volatile unsigned int*)(0x42300404UL))) +#define bM4_TMR61_GCMER_GCME2 (*((volatile unsigned int*)(0x42300408UL))) +#define bM4_TMR61_GCMER_GCME3 (*((volatile unsigned int*)(0x4230040CUL))) +#define bM4_TMR61_GCMER_GCME4 (*((volatile unsigned int*)(0x42300410UL))) +#define bM4_TMR61_GCMER_GCME5 (*((volatile unsigned int*)(0x42300414UL))) +#define bM4_TMR61_GCMER_GCME6 (*((volatile unsigned int*)(0x42300418UL))) +#define bM4_TMR61_GCMER_GCME7 (*((volatile unsigned int*)(0x4230041CUL))) +#define bM4_TMR61_GCMER_GCME8 (*((volatile unsigned int*)(0x42300420UL))) +#define bM4_TMR61_GCMER_GCME9 (*((volatile unsigned int*)(0x42300424UL))) +#define bM4_TMR61_GCMER_GCME10 (*((volatile unsigned int*)(0x42300428UL))) +#define bM4_TMR61_GCMER_GCME11 (*((volatile unsigned int*)(0x4230042CUL))) +#define bM4_TMR61_GCMER_GCME12 (*((volatile unsigned int*)(0x42300430UL))) +#define bM4_TMR61_GCMER_GCME13 (*((volatile unsigned int*)(0x42300434UL))) +#define bM4_TMR61_GCMER_GCME14 (*((volatile unsigned int*)(0x42300438UL))) +#define bM4_TMR61_GCMER_GCME15 (*((volatile unsigned int*)(0x4230043CUL))) +#define bM4_TMR61_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42300480UL))) +#define bM4_TMR61_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42300484UL))) +#define bM4_TMR61_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42300488UL))) +#define bM4_TMR61_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230048CUL))) +#define bM4_TMR61_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42300490UL))) +#define bM4_TMR61_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42300494UL))) +#define bM4_TMR61_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42300498UL))) +#define bM4_TMR61_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230049CUL))) +#define bM4_TMR61_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423004A0UL))) +#define bM4_TMR61_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423004A4UL))) +#define bM4_TMR61_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423004A8UL))) +#define bM4_TMR61_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423004ACUL))) +#define bM4_TMR61_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423004B0UL))) +#define bM4_TMR61_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423004B4UL))) +#define bM4_TMR61_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423004B8UL))) +#define bM4_TMR61_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423004BCUL))) +#define bM4_TMR61_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42300500UL))) +#define bM4_TMR61_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42300504UL))) +#define bM4_TMR61_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42300508UL))) +#define bM4_TMR61_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230050CUL))) +#define bM4_TMR61_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42300510UL))) +#define bM4_TMR61_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42300514UL))) +#define bM4_TMR61_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42300518UL))) +#define bM4_TMR61_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230051CUL))) +#define bM4_TMR61_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42300520UL))) +#define bM4_TMR61_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42300524UL))) +#define bM4_TMR61_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42300528UL))) +#define bM4_TMR61_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230052CUL))) +#define bM4_TMR61_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42300530UL))) +#define bM4_TMR61_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42300534UL))) +#define bM4_TMR61_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42300538UL))) +#define bM4_TMR61_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230053CUL))) +#define bM4_TMR61_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42300580UL))) +#define bM4_TMR61_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42300584UL))) +#define bM4_TMR61_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42300588UL))) +#define bM4_TMR61_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230058CUL))) +#define bM4_TMR61_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42300590UL))) +#define bM4_TMR61_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42300594UL))) +#define bM4_TMR61_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42300598UL))) +#define bM4_TMR61_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230059CUL))) +#define bM4_TMR61_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423005A0UL))) +#define bM4_TMR61_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423005A4UL))) +#define bM4_TMR61_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423005A8UL))) +#define bM4_TMR61_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423005ACUL))) +#define bM4_TMR61_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423005B0UL))) +#define bM4_TMR61_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423005B4UL))) +#define bM4_TMR61_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423005B8UL))) +#define bM4_TMR61_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423005BCUL))) +#define bM4_TMR61_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42300600UL))) +#define bM4_TMR61_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42300604UL))) +#define bM4_TMR61_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42300608UL))) +#define bM4_TMR61_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230060CUL))) +#define bM4_TMR61_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42300610UL))) +#define bM4_TMR61_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42300614UL))) +#define bM4_TMR61_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42300618UL))) +#define bM4_TMR61_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230061CUL))) +#define bM4_TMR61_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42300620UL))) +#define bM4_TMR61_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42300624UL))) +#define bM4_TMR61_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42300628UL))) +#define bM4_TMR61_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230062CUL))) +#define bM4_TMR61_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42300630UL))) +#define bM4_TMR61_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42300634UL))) +#define bM4_TMR61_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42300638UL))) +#define bM4_TMR61_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230063CUL))) +#define bM4_TMR61_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42300680UL))) +#define bM4_TMR61_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42300684UL))) +#define bM4_TMR61_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42300688UL))) +#define bM4_TMR61_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230068CUL))) +#define bM4_TMR61_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42300690UL))) +#define bM4_TMR61_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42300694UL))) +#define bM4_TMR61_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42300698UL))) +#define bM4_TMR61_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230069CUL))) +#define bM4_TMR61_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423006A0UL))) +#define bM4_TMR61_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423006A4UL))) +#define bM4_TMR61_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423006A8UL))) +#define bM4_TMR61_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423006ACUL))) +#define bM4_TMR61_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423006B0UL))) +#define bM4_TMR61_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423006B4UL))) +#define bM4_TMR61_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423006B8UL))) +#define bM4_TMR61_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423006BCUL))) +#define bM4_TMR61_SCMER_SCME0 (*((volatile unsigned int*)(0x42300700UL))) +#define bM4_TMR61_SCMER_SCME1 (*((volatile unsigned int*)(0x42300704UL))) +#define bM4_TMR61_SCMER_SCME2 (*((volatile unsigned int*)(0x42300708UL))) +#define bM4_TMR61_SCMER_SCME3 (*((volatile unsigned int*)(0x4230070CUL))) +#define bM4_TMR61_SCMER_SCME4 (*((volatile unsigned int*)(0x42300710UL))) +#define bM4_TMR61_SCMER_SCME5 (*((volatile unsigned int*)(0x42300714UL))) +#define bM4_TMR61_SCMER_SCME6 (*((volatile unsigned int*)(0x42300718UL))) +#define bM4_TMR61_SCMER_SCME7 (*((volatile unsigned int*)(0x4230071CUL))) +#define bM4_TMR61_SCMER_SCME8 (*((volatile unsigned int*)(0x42300720UL))) +#define bM4_TMR61_SCMER_SCME9 (*((volatile unsigned int*)(0x42300724UL))) +#define bM4_TMR61_SCMER_SCME10 (*((volatile unsigned int*)(0x42300728UL))) +#define bM4_TMR61_SCMER_SCME11 (*((volatile unsigned int*)(0x4230072CUL))) +#define bM4_TMR61_SCMER_SCME12 (*((volatile unsigned int*)(0x42300730UL))) +#define bM4_TMR61_SCMER_SCME13 (*((volatile unsigned int*)(0x42300734UL))) +#define bM4_TMR61_SCMER_SCME14 (*((volatile unsigned int*)(0x42300738UL))) +#define bM4_TMR61_SCMER_SCME15 (*((volatile unsigned int*)(0x4230073CUL))) +#define bM4_TMR61_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42300780UL))) +#define bM4_TMR61_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42300784UL))) +#define bM4_TMR61_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42300788UL))) +#define bM4_TMR61_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230078CUL))) +#define bM4_TMR61_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42300790UL))) +#define bM4_TMR61_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42300794UL))) +#define bM4_TMR61_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42300798UL))) +#define bM4_TMR61_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230079CUL))) +#define bM4_TMR61_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423007A0UL))) +#define bM4_TMR61_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423007A4UL))) +#define bM4_TMR61_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423007A8UL))) +#define bM4_TMR61_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423007ACUL))) +#define bM4_TMR61_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423007B0UL))) +#define bM4_TMR61_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423007B4UL))) +#define bM4_TMR61_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423007B8UL))) +#define bM4_TMR61_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423007BCUL))) +#define bM4_TMR61_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42300800UL))) +#define bM4_TMR61_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42300804UL))) +#define bM4_TMR61_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42300808UL))) +#define bM4_TMR61_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230080CUL))) +#define bM4_TMR61_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42300810UL))) +#define bM4_TMR61_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42300814UL))) +#define bM4_TMR61_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42300818UL))) +#define bM4_TMR61_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230081CUL))) +#define bM4_TMR61_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42300820UL))) +#define bM4_TMR61_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42300824UL))) +#define bM4_TMR61_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42300828UL))) +#define bM4_TMR61_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230082CUL))) +#define bM4_TMR61_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42300830UL))) +#define bM4_TMR61_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42300834UL))) +#define bM4_TMR61_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42300838UL))) +#define bM4_TMR61_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230083CUL))) +#define bM4_TMR61_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42300880UL))) +#define bM4_TMR61_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42300884UL))) +#define bM4_TMR61_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42300888UL))) +#define bM4_TMR61_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230088CUL))) +#define bM4_TMR61_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42300890UL))) +#define bM4_TMR61_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42300894UL))) +#define bM4_TMR61_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42300898UL))) +#define bM4_TMR61_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230089CUL))) +#define bM4_TMR61_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423008A0UL))) +#define bM4_TMR61_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423008A4UL))) +#define bM4_TMR61_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423008A8UL))) +#define bM4_TMR61_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423008ACUL))) +#define bM4_TMR61_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423008B0UL))) +#define bM4_TMR61_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423008B4UL))) +#define bM4_TMR61_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423008B8UL))) +#define bM4_TMR61_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423008BCUL))) +#define bM4_TMR61_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42300900UL))) +#define bM4_TMR61_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42300904UL))) +#define bM4_TMR61_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42300908UL))) +#define bM4_TMR61_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230090CUL))) +#define bM4_TMR61_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42300910UL))) +#define bM4_TMR61_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42300914UL))) +#define bM4_TMR61_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42300918UL))) +#define bM4_TMR61_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230091CUL))) +#define bM4_TMR61_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42300920UL))) +#define bM4_TMR61_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42300924UL))) +#define bM4_TMR61_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42300928UL))) +#define bM4_TMR61_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230092CUL))) +#define bM4_TMR61_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42300930UL))) +#define bM4_TMR61_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42300934UL))) +#define bM4_TMR61_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42300938UL))) +#define bM4_TMR61_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230093CUL))) +#define bM4_TMR61_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42300980UL))) +#define bM4_TMR61_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42300984UL))) +#define bM4_TMR61_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42300988UL))) +#define bM4_TMR61_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230098CUL))) +#define bM4_TMR61_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42300990UL))) +#define bM4_TMR61_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42300994UL))) +#define bM4_TMR61_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42300998UL))) +#define bM4_TMR61_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230099CUL))) +#define bM4_TMR61_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423009A0UL))) +#define bM4_TMR61_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423009A4UL))) +#define bM4_TMR61_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423009A8UL))) +#define bM4_TMR61_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423009ACUL))) +#define bM4_TMR61_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423009B0UL))) +#define bM4_TMR61_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423009B4UL))) +#define bM4_TMR61_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423009B8UL))) +#define bM4_TMR61_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423009BCUL))) +#define bM4_TMR61_GCONR_START (*((volatile unsigned int*)(0x42300A00UL))) +#define bM4_TMR61_GCONR_MODE0 (*((volatile unsigned int*)(0x42300A04UL))) +#define bM4_TMR61_GCONR_MODE1 (*((volatile unsigned int*)(0x42300A08UL))) +#define bM4_TMR61_GCONR_MODE2 (*((volatile unsigned int*)(0x42300A0CUL))) +#define bM4_TMR61_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42300A10UL))) +#define bM4_TMR61_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42300A14UL))) +#define bM4_TMR61_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42300A18UL))) +#define bM4_TMR61_GCONR_DIR (*((volatile unsigned int*)(0x42300A20UL))) +#define bM4_TMR61_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42300A40UL))) +#define bM4_TMR61_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42300A44UL))) +#define bM4_TMR61_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42300A48UL))) +#define bM4_TMR61_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42300A4CUL))) +#define bM4_TMR61_ICONR_INTENA (*((volatile unsigned int*)(0x42300A80UL))) +#define bM4_TMR61_ICONR_INTENB (*((volatile unsigned int*)(0x42300A84UL))) +#define bM4_TMR61_ICONR_INTENC (*((volatile unsigned int*)(0x42300A88UL))) +#define bM4_TMR61_ICONR_INTEND (*((volatile unsigned int*)(0x42300A8CUL))) +#define bM4_TMR61_ICONR_INTENE (*((volatile unsigned int*)(0x42300A90UL))) +#define bM4_TMR61_ICONR_INTENF (*((volatile unsigned int*)(0x42300A94UL))) +#define bM4_TMR61_ICONR_INTENOVF (*((volatile unsigned int*)(0x42300A98UL))) +#define bM4_TMR61_ICONR_INTENUDF (*((volatile unsigned int*)(0x42300A9CUL))) +#define bM4_TMR61_ICONR_INTENDTE (*((volatile unsigned int*)(0x42300AA0UL))) +#define bM4_TMR61_ICONR_INTENSAU (*((volatile unsigned int*)(0x42300AC0UL))) +#define bM4_TMR61_ICONR_INTENSAD (*((volatile unsigned int*)(0x42300AC4UL))) +#define bM4_TMR61_ICONR_INTENSBU (*((volatile unsigned int*)(0x42300AC8UL))) +#define bM4_TMR61_ICONR_INTENSBD (*((volatile unsigned int*)(0x42300ACCUL))) +#define bM4_TMR61_PCONR_CAPMDA (*((volatile unsigned int*)(0x42300B00UL))) +#define bM4_TMR61_PCONR_STACA (*((volatile unsigned int*)(0x42300B04UL))) +#define bM4_TMR61_PCONR_STPCA (*((volatile unsigned int*)(0x42300B08UL))) +#define bM4_TMR61_PCONR_STASTPSA (*((volatile unsigned int*)(0x42300B0CUL))) +#define bM4_TMR61_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42300B10UL))) +#define bM4_TMR61_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42300B14UL))) +#define bM4_TMR61_PCONR_PERCA0 (*((volatile unsigned int*)(0x42300B18UL))) +#define bM4_TMR61_PCONR_PERCA1 (*((volatile unsigned int*)(0x42300B1CUL))) +#define bM4_TMR61_PCONR_OUTENA (*((volatile unsigned int*)(0x42300B20UL))) +#define bM4_TMR61_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42300B2CUL))) +#define bM4_TMR61_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42300B30UL))) +#define bM4_TMR61_PCONR_CAPMDB (*((volatile unsigned int*)(0x42300B40UL))) +#define bM4_TMR61_PCONR_STACB (*((volatile unsigned int*)(0x42300B44UL))) +#define bM4_TMR61_PCONR_STPCB (*((volatile unsigned int*)(0x42300B48UL))) +#define bM4_TMR61_PCONR_STASTPSB (*((volatile unsigned int*)(0x42300B4CUL))) +#define bM4_TMR61_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42300B50UL))) +#define bM4_TMR61_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42300B54UL))) +#define bM4_TMR61_PCONR_PERCB0 (*((volatile unsigned int*)(0x42300B58UL))) +#define bM4_TMR61_PCONR_PERCB1 (*((volatile unsigned int*)(0x42300B5CUL))) +#define bM4_TMR61_PCONR_OUTENB (*((volatile unsigned int*)(0x42300B60UL))) +#define bM4_TMR61_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42300B6CUL))) +#define bM4_TMR61_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42300B70UL))) +#define bM4_TMR61_BCONR_BENA (*((volatile unsigned int*)(0x42300B80UL))) +#define bM4_TMR61_BCONR_BSEA (*((volatile unsigned int*)(0x42300B84UL))) +#define bM4_TMR61_BCONR_BENB (*((volatile unsigned int*)(0x42300B88UL))) +#define bM4_TMR61_BCONR_BSEB (*((volatile unsigned int*)(0x42300B8CUL))) +#define bM4_TMR61_BCONR_BENP (*((volatile unsigned int*)(0x42300BA0UL))) +#define bM4_TMR61_BCONR_BSEP (*((volatile unsigned int*)(0x42300BA4UL))) +#define bM4_TMR61_BCONR_BENSPA (*((volatile unsigned int*)(0x42300BC0UL))) +#define bM4_TMR61_BCONR_BSESPA (*((volatile unsigned int*)(0x42300BC4UL))) +#define bM4_TMR61_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42300BD0UL))) +#define bM4_TMR61_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42300BD4UL))) +#define bM4_TMR61_BCONR_BENSPB (*((volatile unsigned int*)(0x42300BE0UL))) +#define bM4_TMR61_BCONR_BSESPB (*((volatile unsigned int*)(0x42300BE4UL))) +#define bM4_TMR61_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42300BF0UL))) +#define bM4_TMR61_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42300BF4UL))) +#define bM4_TMR61_DCONR_DTCEN (*((volatile unsigned int*)(0x42300C00UL))) +#define bM4_TMR61_DCONR_DTBENU (*((volatile unsigned int*)(0x42300C10UL))) +#define bM4_TMR61_DCONR_DTBEND (*((volatile unsigned int*)(0x42300C14UL))) +#define bM4_TMR61_DCONR_SEPA (*((volatile unsigned int*)(0x42300C20UL))) +#define bM4_TMR61_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42300D00UL))) +#define bM4_TMR61_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42300D04UL))) +#define bM4_TMR61_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42300D08UL))) +#define bM4_TMR61_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42300D10UL))) +#define bM4_TMR61_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42300D14UL))) +#define bM4_TMR61_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42300D18UL))) +#define bM4_TMR61_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42300D40UL))) +#define bM4_TMR61_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42300D44UL))) +#define bM4_TMR61_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42300D48UL))) +#define bM4_TMR61_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42300D50UL))) +#define bM4_TMR61_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42300D54UL))) +#define bM4_TMR61_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42300D58UL))) +#define bM4_TMR61_VPERR_SPPERIA (*((volatile unsigned int*)(0x42300DA0UL))) +#define bM4_TMR61_VPERR_SPPERIB (*((volatile unsigned int*)(0x42300DA4UL))) +#define bM4_TMR61_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42300DC0UL))) +#define bM4_TMR61_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42300DC4UL))) +#define bM4_TMR61_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42300DC8UL))) +#define bM4_TMR61_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42300DCCUL))) +#define bM4_TMR61_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42300DD0UL))) +#define bM4_TMR61_STFLR_CMAF (*((volatile unsigned int*)(0x42300E00UL))) +#define bM4_TMR61_STFLR_CMBF (*((volatile unsigned int*)(0x42300E04UL))) +#define bM4_TMR61_STFLR_CMCF (*((volatile unsigned int*)(0x42300E08UL))) +#define bM4_TMR61_STFLR_CMDF (*((volatile unsigned int*)(0x42300E0CUL))) +#define bM4_TMR61_STFLR_CMEF (*((volatile unsigned int*)(0x42300E10UL))) +#define bM4_TMR61_STFLR_CMFF (*((volatile unsigned int*)(0x42300E14UL))) +#define bM4_TMR61_STFLR_OVFF (*((volatile unsigned int*)(0x42300E18UL))) +#define bM4_TMR61_STFLR_UDFF (*((volatile unsigned int*)(0x42300E1CUL))) +#define bM4_TMR61_STFLR_DTEF (*((volatile unsigned int*)(0x42300E20UL))) +#define bM4_TMR61_STFLR_CMSAUF (*((volatile unsigned int*)(0x42300E24UL))) +#define bM4_TMR61_STFLR_CMSADF (*((volatile unsigned int*)(0x42300E28UL))) +#define bM4_TMR61_STFLR_CMSBUF (*((volatile unsigned int*)(0x42300E2CUL))) +#define bM4_TMR61_STFLR_CMSBDF (*((volatile unsigned int*)(0x42300E30UL))) +#define bM4_TMR61_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42300E54UL))) +#define bM4_TMR61_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42300E58UL))) +#define bM4_TMR61_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42300E5CUL))) +#define bM4_TMR61_STFLR_DIRF (*((volatile unsigned int*)(0x42300E7CUL))) +#define bM4_TMR61_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42300E80UL))) +#define bM4_TMR61_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42300E84UL))) +#define bM4_TMR61_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42300E90UL))) +#define bM4_TMR61_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42300E94UL))) +#define bM4_TMR61_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42300E98UL))) +#define bM4_TMR61_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42300E9CUL))) +#define bM4_TMR61_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42300EA0UL))) +#define bM4_TMR61_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42300EA4UL))) +#define bM4_TMR61_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42300EA8UL))) +#define bM4_TMR61_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42300EACUL))) +#define bM4_TMR61_HSTAR_STARTS (*((volatile unsigned int*)(0x42300EFCUL))) +#define bM4_TMR61_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42300F00UL))) +#define bM4_TMR61_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42300F04UL))) +#define bM4_TMR61_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42300F10UL))) +#define bM4_TMR61_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42300F14UL))) +#define bM4_TMR61_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42300F18UL))) +#define bM4_TMR61_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42300F1CUL))) +#define bM4_TMR61_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42300F20UL))) +#define bM4_TMR61_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42300F24UL))) +#define bM4_TMR61_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42300F28UL))) +#define bM4_TMR61_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42300F2CUL))) +#define bM4_TMR61_HSTPR_STOPS (*((volatile unsigned int*)(0x42300F7CUL))) +#define bM4_TMR61_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42300F80UL))) +#define bM4_TMR61_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42300F84UL))) +#define bM4_TMR61_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42300F90UL))) +#define bM4_TMR61_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42300F94UL))) +#define bM4_TMR61_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42300F98UL))) +#define bM4_TMR61_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42300F9CUL))) +#define bM4_TMR61_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42300FA0UL))) +#define bM4_TMR61_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42300FA4UL))) +#define bM4_TMR61_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42300FA8UL))) +#define bM4_TMR61_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42300FACUL))) +#define bM4_TMR61_HCLRR_CLEARS (*((volatile unsigned int*)(0x42300FFCUL))) +#define bM4_TMR61_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42301000UL))) +#define bM4_TMR61_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42301004UL))) +#define bM4_TMR61_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42301010UL))) +#define bM4_TMR61_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42301014UL))) +#define bM4_TMR61_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42301018UL))) +#define bM4_TMR61_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230101CUL))) +#define bM4_TMR61_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42301020UL))) +#define bM4_TMR61_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42301024UL))) +#define bM4_TMR61_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42301028UL))) +#define bM4_TMR61_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230102CUL))) +#define bM4_TMR61_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42301080UL))) +#define bM4_TMR61_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42301084UL))) +#define bM4_TMR61_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42301090UL))) +#define bM4_TMR61_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42301094UL))) +#define bM4_TMR61_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42301098UL))) +#define bM4_TMR61_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230109CUL))) +#define bM4_TMR61_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423010A0UL))) +#define bM4_TMR61_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423010A4UL))) +#define bM4_TMR61_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423010A8UL))) +#define bM4_TMR61_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423010ACUL))) +#define bM4_TMR61_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42301100UL))) +#define bM4_TMR61_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42301104UL))) +#define bM4_TMR61_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42301108UL))) +#define bM4_TMR61_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230110CUL))) +#define bM4_TMR61_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42301110UL))) +#define bM4_TMR61_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42301114UL))) +#define bM4_TMR61_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42301118UL))) +#define bM4_TMR61_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230111CUL))) +#define bM4_TMR61_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42301120UL))) +#define bM4_TMR61_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42301124UL))) +#define bM4_TMR61_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42301128UL))) +#define bM4_TMR61_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230112CUL))) +#define bM4_TMR61_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42301140UL))) +#define bM4_TMR61_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42301144UL))) +#define bM4_TMR61_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42301180UL))) +#define bM4_TMR61_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42301184UL))) +#define bM4_TMR61_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42301188UL))) +#define bM4_TMR61_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230118CUL))) +#define bM4_TMR61_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42301190UL))) +#define bM4_TMR61_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42301194UL))) +#define bM4_TMR61_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42301198UL))) +#define bM4_TMR61_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230119CUL))) +#define bM4_TMR61_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423011A0UL))) +#define bM4_TMR61_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423011A4UL))) +#define bM4_TMR61_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423011A8UL))) +#define bM4_TMR61_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423011ACUL))) +#define bM4_TMR61_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423011C0UL))) +#define bM4_TMR61_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423011C4UL))) +#define bM4_TMR62_CNTER_CNT0 (*((volatile unsigned int*)(0x42308000UL))) +#define bM4_TMR62_CNTER_CNT1 (*((volatile unsigned int*)(0x42308004UL))) +#define bM4_TMR62_CNTER_CNT2 (*((volatile unsigned int*)(0x42308008UL))) +#define bM4_TMR62_CNTER_CNT3 (*((volatile unsigned int*)(0x4230800CUL))) +#define bM4_TMR62_CNTER_CNT4 (*((volatile unsigned int*)(0x42308010UL))) +#define bM4_TMR62_CNTER_CNT5 (*((volatile unsigned int*)(0x42308014UL))) +#define bM4_TMR62_CNTER_CNT6 (*((volatile unsigned int*)(0x42308018UL))) +#define bM4_TMR62_CNTER_CNT7 (*((volatile unsigned int*)(0x4230801CUL))) +#define bM4_TMR62_CNTER_CNT8 (*((volatile unsigned int*)(0x42308020UL))) +#define bM4_TMR62_CNTER_CNT9 (*((volatile unsigned int*)(0x42308024UL))) +#define bM4_TMR62_CNTER_CNT10 (*((volatile unsigned int*)(0x42308028UL))) +#define bM4_TMR62_CNTER_CNT11 (*((volatile unsigned int*)(0x4230802CUL))) +#define bM4_TMR62_CNTER_CNT12 (*((volatile unsigned int*)(0x42308030UL))) +#define bM4_TMR62_CNTER_CNT13 (*((volatile unsigned int*)(0x42308034UL))) +#define bM4_TMR62_CNTER_CNT14 (*((volatile unsigned int*)(0x42308038UL))) +#define bM4_TMR62_CNTER_CNT15 (*((volatile unsigned int*)(0x4230803CUL))) +#define bM4_TMR62_PERAR_PERA0 (*((volatile unsigned int*)(0x42308080UL))) +#define bM4_TMR62_PERAR_PERA1 (*((volatile unsigned int*)(0x42308084UL))) +#define bM4_TMR62_PERAR_PERA2 (*((volatile unsigned int*)(0x42308088UL))) +#define bM4_TMR62_PERAR_PERA3 (*((volatile unsigned int*)(0x4230808CUL))) +#define bM4_TMR62_PERAR_PERA4 (*((volatile unsigned int*)(0x42308090UL))) +#define bM4_TMR62_PERAR_PERA5 (*((volatile unsigned int*)(0x42308094UL))) +#define bM4_TMR62_PERAR_PERA6 (*((volatile unsigned int*)(0x42308098UL))) +#define bM4_TMR62_PERAR_PERA7 (*((volatile unsigned int*)(0x4230809CUL))) +#define bM4_TMR62_PERAR_PERA8 (*((volatile unsigned int*)(0x423080A0UL))) +#define bM4_TMR62_PERAR_PERA9 (*((volatile unsigned int*)(0x423080A4UL))) +#define bM4_TMR62_PERAR_PERA10 (*((volatile unsigned int*)(0x423080A8UL))) +#define bM4_TMR62_PERAR_PERA11 (*((volatile unsigned int*)(0x423080ACUL))) +#define bM4_TMR62_PERAR_PERA12 (*((volatile unsigned int*)(0x423080B0UL))) +#define bM4_TMR62_PERAR_PERA13 (*((volatile unsigned int*)(0x423080B4UL))) +#define bM4_TMR62_PERAR_PERA14 (*((volatile unsigned int*)(0x423080B8UL))) +#define bM4_TMR62_PERAR_PERA15 (*((volatile unsigned int*)(0x423080BCUL))) +#define bM4_TMR62_PERBR_PERB0 (*((volatile unsigned int*)(0x42308100UL))) +#define bM4_TMR62_PERBR_PERB1 (*((volatile unsigned int*)(0x42308104UL))) +#define bM4_TMR62_PERBR_PERB2 (*((volatile unsigned int*)(0x42308108UL))) +#define bM4_TMR62_PERBR_PERB3 (*((volatile unsigned int*)(0x4230810CUL))) +#define bM4_TMR62_PERBR_PERB4 (*((volatile unsigned int*)(0x42308110UL))) +#define bM4_TMR62_PERBR_PERB5 (*((volatile unsigned int*)(0x42308114UL))) +#define bM4_TMR62_PERBR_PERB6 (*((volatile unsigned int*)(0x42308118UL))) +#define bM4_TMR62_PERBR_PERB7 (*((volatile unsigned int*)(0x4230811CUL))) +#define bM4_TMR62_PERBR_PERB8 (*((volatile unsigned int*)(0x42308120UL))) +#define bM4_TMR62_PERBR_PERB9 (*((volatile unsigned int*)(0x42308124UL))) +#define bM4_TMR62_PERBR_PERB10 (*((volatile unsigned int*)(0x42308128UL))) +#define bM4_TMR62_PERBR_PERB11 (*((volatile unsigned int*)(0x4230812CUL))) +#define bM4_TMR62_PERBR_PERB12 (*((volatile unsigned int*)(0x42308130UL))) +#define bM4_TMR62_PERBR_PERB13 (*((volatile unsigned int*)(0x42308134UL))) +#define bM4_TMR62_PERBR_PERB14 (*((volatile unsigned int*)(0x42308138UL))) +#define bM4_TMR62_PERBR_PERB15 (*((volatile unsigned int*)(0x4230813CUL))) +#define bM4_TMR62_PERCR_PERC0 (*((volatile unsigned int*)(0x42308180UL))) +#define bM4_TMR62_PERCR_PERC1 (*((volatile unsigned int*)(0x42308184UL))) +#define bM4_TMR62_PERCR_PERC2 (*((volatile unsigned int*)(0x42308188UL))) +#define bM4_TMR62_PERCR_PERC3 (*((volatile unsigned int*)(0x4230818CUL))) +#define bM4_TMR62_PERCR_PERC4 (*((volatile unsigned int*)(0x42308190UL))) +#define bM4_TMR62_PERCR_PERC5 (*((volatile unsigned int*)(0x42308194UL))) +#define bM4_TMR62_PERCR_PERC6 (*((volatile unsigned int*)(0x42308198UL))) +#define bM4_TMR62_PERCR_PERC7 (*((volatile unsigned int*)(0x4230819CUL))) +#define bM4_TMR62_PERCR_PERC8 (*((volatile unsigned int*)(0x423081A0UL))) +#define bM4_TMR62_PERCR_PERC9 (*((volatile unsigned int*)(0x423081A4UL))) +#define bM4_TMR62_PERCR_PERC10 (*((volatile unsigned int*)(0x423081A8UL))) +#define bM4_TMR62_PERCR_PERC11 (*((volatile unsigned int*)(0x423081ACUL))) +#define bM4_TMR62_PERCR_PERC12 (*((volatile unsigned int*)(0x423081B0UL))) +#define bM4_TMR62_PERCR_PERC13 (*((volatile unsigned int*)(0x423081B4UL))) +#define bM4_TMR62_PERCR_PERC14 (*((volatile unsigned int*)(0x423081B8UL))) +#define bM4_TMR62_PERCR_PERC15 (*((volatile unsigned int*)(0x423081BCUL))) +#define bM4_TMR62_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42308200UL))) +#define bM4_TMR62_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42308204UL))) +#define bM4_TMR62_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42308208UL))) +#define bM4_TMR62_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230820CUL))) +#define bM4_TMR62_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42308210UL))) +#define bM4_TMR62_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42308214UL))) +#define bM4_TMR62_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42308218UL))) +#define bM4_TMR62_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230821CUL))) +#define bM4_TMR62_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42308220UL))) +#define bM4_TMR62_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42308224UL))) +#define bM4_TMR62_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42308228UL))) +#define bM4_TMR62_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230822CUL))) +#define bM4_TMR62_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42308230UL))) +#define bM4_TMR62_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42308234UL))) +#define bM4_TMR62_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42308238UL))) +#define bM4_TMR62_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230823CUL))) +#define bM4_TMR62_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42308280UL))) +#define bM4_TMR62_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42308284UL))) +#define bM4_TMR62_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42308288UL))) +#define bM4_TMR62_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230828CUL))) +#define bM4_TMR62_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42308290UL))) +#define bM4_TMR62_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42308294UL))) +#define bM4_TMR62_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42308298UL))) +#define bM4_TMR62_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230829CUL))) +#define bM4_TMR62_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423082A0UL))) +#define bM4_TMR62_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423082A4UL))) +#define bM4_TMR62_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423082A8UL))) +#define bM4_TMR62_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423082ACUL))) +#define bM4_TMR62_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423082B0UL))) +#define bM4_TMR62_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423082B4UL))) +#define bM4_TMR62_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423082B8UL))) +#define bM4_TMR62_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423082BCUL))) +#define bM4_TMR62_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42308300UL))) +#define bM4_TMR62_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42308304UL))) +#define bM4_TMR62_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42308308UL))) +#define bM4_TMR62_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230830CUL))) +#define bM4_TMR62_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42308310UL))) +#define bM4_TMR62_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42308314UL))) +#define bM4_TMR62_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42308318UL))) +#define bM4_TMR62_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230831CUL))) +#define bM4_TMR62_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42308320UL))) +#define bM4_TMR62_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42308324UL))) +#define bM4_TMR62_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42308328UL))) +#define bM4_TMR62_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230832CUL))) +#define bM4_TMR62_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42308330UL))) +#define bM4_TMR62_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42308334UL))) +#define bM4_TMR62_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42308338UL))) +#define bM4_TMR62_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230833CUL))) +#define bM4_TMR62_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42308380UL))) +#define bM4_TMR62_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42308384UL))) +#define bM4_TMR62_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42308388UL))) +#define bM4_TMR62_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230838CUL))) +#define bM4_TMR62_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42308390UL))) +#define bM4_TMR62_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42308394UL))) +#define bM4_TMR62_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42308398UL))) +#define bM4_TMR62_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230839CUL))) +#define bM4_TMR62_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423083A0UL))) +#define bM4_TMR62_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423083A4UL))) +#define bM4_TMR62_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423083A8UL))) +#define bM4_TMR62_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423083ACUL))) +#define bM4_TMR62_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423083B0UL))) +#define bM4_TMR62_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423083B4UL))) +#define bM4_TMR62_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423083B8UL))) +#define bM4_TMR62_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423083BCUL))) +#define bM4_TMR62_GCMER_GCME0 (*((volatile unsigned int*)(0x42308400UL))) +#define bM4_TMR62_GCMER_GCME1 (*((volatile unsigned int*)(0x42308404UL))) +#define bM4_TMR62_GCMER_GCME2 (*((volatile unsigned int*)(0x42308408UL))) +#define bM4_TMR62_GCMER_GCME3 (*((volatile unsigned int*)(0x4230840CUL))) +#define bM4_TMR62_GCMER_GCME4 (*((volatile unsigned int*)(0x42308410UL))) +#define bM4_TMR62_GCMER_GCME5 (*((volatile unsigned int*)(0x42308414UL))) +#define bM4_TMR62_GCMER_GCME6 (*((volatile unsigned int*)(0x42308418UL))) +#define bM4_TMR62_GCMER_GCME7 (*((volatile unsigned int*)(0x4230841CUL))) +#define bM4_TMR62_GCMER_GCME8 (*((volatile unsigned int*)(0x42308420UL))) +#define bM4_TMR62_GCMER_GCME9 (*((volatile unsigned int*)(0x42308424UL))) +#define bM4_TMR62_GCMER_GCME10 (*((volatile unsigned int*)(0x42308428UL))) +#define bM4_TMR62_GCMER_GCME11 (*((volatile unsigned int*)(0x4230842CUL))) +#define bM4_TMR62_GCMER_GCME12 (*((volatile unsigned int*)(0x42308430UL))) +#define bM4_TMR62_GCMER_GCME13 (*((volatile unsigned int*)(0x42308434UL))) +#define bM4_TMR62_GCMER_GCME14 (*((volatile unsigned int*)(0x42308438UL))) +#define bM4_TMR62_GCMER_GCME15 (*((volatile unsigned int*)(0x4230843CUL))) +#define bM4_TMR62_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42308480UL))) +#define bM4_TMR62_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42308484UL))) +#define bM4_TMR62_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42308488UL))) +#define bM4_TMR62_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230848CUL))) +#define bM4_TMR62_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42308490UL))) +#define bM4_TMR62_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42308494UL))) +#define bM4_TMR62_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42308498UL))) +#define bM4_TMR62_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230849CUL))) +#define bM4_TMR62_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423084A0UL))) +#define bM4_TMR62_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423084A4UL))) +#define bM4_TMR62_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423084A8UL))) +#define bM4_TMR62_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423084ACUL))) +#define bM4_TMR62_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423084B0UL))) +#define bM4_TMR62_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423084B4UL))) +#define bM4_TMR62_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423084B8UL))) +#define bM4_TMR62_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423084BCUL))) +#define bM4_TMR62_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42308500UL))) +#define bM4_TMR62_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42308504UL))) +#define bM4_TMR62_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42308508UL))) +#define bM4_TMR62_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230850CUL))) +#define bM4_TMR62_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42308510UL))) +#define bM4_TMR62_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42308514UL))) +#define bM4_TMR62_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42308518UL))) +#define bM4_TMR62_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230851CUL))) +#define bM4_TMR62_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42308520UL))) +#define bM4_TMR62_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42308524UL))) +#define bM4_TMR62_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42308528UL))) +#define bM4_TMR62_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230852CUL))) +#define bM4_TMR62_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42308530UL))) +#define bM4_TMR62_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42308534UL))) +#define bM4_TMR62_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42308538UL))) +#define bM4_TMR62_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230853CUL))) +#define bM4_TMR62_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42308580UL))) +#define bM4_TMR62_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42308584UL))) +#define bM4_TMR62_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42308588UL))) +#define bM4_TMR62_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230858CUL))) +#define bM4_TMR62_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42308590UL))) +#define bM4_TMR62_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42308594UL))) +#define bM4_TMR62_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42308598UL))) +#define bM4_TMR62_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230859CUL))) +#define bM4_TMR62_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423085A0UL))) +#define bM4_TMR62_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423085A4UL))) +#define bM4_TMR62_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423085A8UL))) +#define bM4_TMR62_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423085ACUL))) +#define bM4_TMR62_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423085B0UL))) +#define bM4_TMR62_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423085B4UL))) +#define bM4_TMR62_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423085B8UL))) +#define bM4_TMR62_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423085BCUL))) +#define bM4_TMR62_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42308600UL))) +#define bM4_TMR62_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42308604UL))) +#define bM4_TMR62_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42308608UL))) +#define bM4_TMR62_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230860CUL))) +#define bM4_TMR62_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42308610UL))) +#define bM4_TMR62_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42308614UL))) +#define bM4_TMR62_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42308618UL))) +#define bM4_TMR62_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230861CUL))) +#define bM4_TMR62_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42308620UL))) +#define bM4_TMR62_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42308624UL))) +#define bM4_TMR62_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42308628UL))) +#define bM4_TMR62_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230862CUL))) +#define bM4_TMR62_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42308630UL))) +#define bM4_TMR62_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42308634UL))) +#define bM4_TMR62_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42308638UL))) +#define bM4_TMR62_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230863CUL))) +#define bM4_TMR62_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42308680UL))) +#define bM4_TMR62_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42308684UL))) +#define bM4_TMR62_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42308688UL))) +#define bM4_TMR62_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230868CUL))) +#define bM4_TMR62_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42308690UL))) +#define bM4_TMR62_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42308694UL))) +#define bM4_TMR62_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42308698UL))) +#define bM4_TMR62_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230869CUL))) +#define bM4_TMR62_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423086A0UL))) +#define bM4_TMR62_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423086A4UL))) +#define bM4_TMR62_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423086A8UL))) +#define bM4_TMR62_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423086ACUL))) +#define bM4_TMR62_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423086B0UL))) +#define bM4_TMR62_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423086B4UL))) +#define bM4_TMR62_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423086B8UL))) +#define bM4_TMR62_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423086BCUL))) +#define bM4_TMR62_SCMER_SCME0 (*((volatile unsigned int*)(0x42308700UL))) +#define bM4_TMR62_SCMER_SCME1 (*((volatile unsigned int*)(0x42308704UL))) +#define bM4_TMR62_SCMER_SCME2 (*((volatile unsigned int*)(0x42308708UL))) +#define bM4_TMR62_SCMER_SCME3 (*((volatile unsigned int*)(0x4230870CUL))) +#define bM4_TMR62_SCMER_SCME4 (*((volatile unsigned int*)(0x42308710UL))) +#define bM4_TMR62_SCMER_SCME5 (*((volatile unsigned int*)(0x42308714UL))) +#define bM4_TMR62_SCMER_SCME6 (*((volatile unsigned int*)(0x42308718UL))) +#define bM4_TMR62_SCMER_SCME7 (*((volatile unsigned int*)(0x4230871CUL))) +#define bM4_TMR62_SCMER_SCME8 (*((volatile unsigned int*)(0x42308720UL))) +#define bM4_TMR62_SCMER_SCME9 (*((volatile unsigned int*)(0x42308724UL))) +#define bM4_TMR62_SCMER_SCME10 (*((volatile unsigned int*)(0x42308728UL))) +#define bM4_TMR62_SCMER_SCME11 (*((volatile unsigned int*)(0x4230872CUL))) +#define bM4_TMR62_SCMER_SCME12 (*((volatile unsigned int*)(0x42308730UL))) +#define bM4_TMR62_SCMER_SCME13 (*((volatile unsigned int*)(0x42308734UL))) +#define bM4_TMR62_SCMER_SCME14 (*((volatile unsigned int*)(0x42308738UL))) +#define bM4_TMR62_SCMER_SCME15 (*((volatile unsigned int*)(0x4230873CUL))) +#define bM4_TMR62_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42308780UL))) +#define bM4_TMR62_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42308784UL))) +#define bM4_TMR62_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42308788UL))) +#define bM4_TMR62_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230878CUL))) +#define bM4_TMR62_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42308790UL))) +#define bM4_TMR62_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42308794UL))) +#define bM4_TMR62_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42308798UL))) +#define bM4_TMR62_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230879CUL))) +#define bM4_TMR62_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423087A0UL))) +#define bM4_TMR62_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423087A4UL))) +#define bM4_TMR62_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423087A8UL))) +#define bM4_TMR62_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423087ACUL))) +#define bM4_TMR62_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423087B0UL))) +#define bM4_TMR62_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423087B4UL))) +#define bM4_TMR62_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423087B8UL))) +#define bM4_TMR62_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423087BCUL))) +#define bM4_TMR62_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42308800UL))) +#define bM4_TMR62_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42308804UL))) +#define bM4_TMR62_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42308808UL))) +#define bM4_TMR62_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230880CUL))) +#define bM4_TMR62_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42308810UL))) +#define bM4_TMR62_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42308814UL))) +#define bM4_TMR62_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42308818UL))) +#define bM4_TMR62_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230881CUL))) +#define bM4_TMR62_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42308820UL))) +#define bM4_TMR62_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42308824UL))) +#define bM4_TMR62_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42308828UL))) +#define bM4_TMR62_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230882CUL))) +#define bM4_TMR62_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42308830UL))) +#define bM4_TMR62_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42308834UL))) +#define bM4_TMR62_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42308838UL))) +#define bM4_TMR62_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230883CUL))) +#define bM4_TMR62_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42308880UL))) +#define bM4_TMR62_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42308884UL))) +#define bM4_TMR62_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42308888UL))) +#define bM4_TMR62_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230888CUL))) +#define bM4_TMR62_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42308890UL))) +#define bM4_TMR62_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42308894UL))) +#define bM4_TMR62_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42308898UL))) +#define bM4_TMR62_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230889CUL))) +#define bM4_TMR62_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423088A0UL))) +#define bM4_TMR62_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423088A4UL))) +#define bM4_TMR62_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423088A8UL))) +#define bM4_TMR62_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423088ACUL))) +#define bM4_TMR62_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423088B0UL))) +#define bM4_TMR62_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423088B4UL))) +#define bM4_TMR62_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423088B8UL))) +#define bM4_TMR62_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423088BCUL))) +#define bM4_TMR62_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42308900UL))) +#define bM4_TMR62_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42308904UL))) +#define bM4_TMR62_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42308908UL))) +#define bM4_TMR62_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230890CUL))) +#define bM4_TMR62_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42308910UL))) +#define bM4_TMR62_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42308914UL))) +#define bM4_TMR62_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42308918UL))) +#define bM4_TMR62_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230891CUL))) +#define bM4_TMR62_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42308920UL))) +#define bM4_TMR62_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42308924UL))) +#define bM4_TMR62_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42308928UL))) +#define bM4_TMR62_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230892CUL))) +#define bM4_TMR62_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42308930UL))) +#define bM4_TMR62_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42308934UL))) +#define bM4_TMR62_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42308938UL))) +#define bM4_TMR62_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230893CUL))) +#define bM4_TMR62_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42308980UL))) +#define bM4_TMR62_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42308984UL))) +#define bM4_TMR62_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42308988UL))) +#define bM4_TMR62_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230898CUL))) +#define bM4_TMR62_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42308990UL))) +#define bM4_TMR62_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42308994UL))) +#define bM4_TMR62_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42308998UL))) +#define bM4_TMR62_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230899CUL))) +#define bM4_TMR62_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423089A0UL))) +#define bM4_TMR62_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423089A4UL))) +#define bM4_TMR62_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423089A8UL))) +#define bM4_TMR62_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423089ACUL))) +#define bM4_TMR62_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423089B0UL))) +#define bM4_TMR62_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423089B4UL))) +#define bM4_TMR62_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423089B8UL))) +#define bM4_TMR62_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423089BCUL))) +#define bM4_TMR62_GCONR_START (*((volatile unsigned int*)(0x42308A00UL))) +#define bM4_TMR62_GCONR_MODE0 (*((volatile unsigned int*)(0x42308A04UL))) +#define bM4_TMR62_GCONR_MODE1 (*((volatile unsigned int*)(0x42308A08UL))) +#define bM4_TMR62_GCONR_MODE2 (*((volatile unsigned int*)(0x42308A0CUL))) +#define bM4_TMR62_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42308A10UL))) +#define bM4_TMR62_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42308A14UL))) +#define bM4_TMR62_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42308A18UL))) +#define bM4_TMR62_GCONR_DIR (*((volatile unsigned int*)(0x42308A20UL))) +#define bM4_TMR62_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42308A40UL))) +#define bM4_TMR62_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42308A44UL))) +#define bM4_TMR62_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42308A48UL))) +#define bM4_TMR62_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42308A4CUL))) +#define bM4_TMR62_ICONR_INTENA (*((volatile unsigned int*)(0x42308A80UL))) +#define bM4_TMR62_ICONR_INTENB (*((volatile unsigned int*)(0x42308A84UL))) +#define bM4_TMR62_ICONR_INTENC (*((volatile unsigned int*)(0x42308A88UL))) +#define bM4_TMR62_ICONR_INTEND (*((volatile unsigned int*)(0x42308A8CUL))) +#define bM4_TMR62_ICONR_INTENE (*((volatile unsigned int*)(0x42308A90UL))) +#define bM4_TMR62_ICONR_INTENF (*((volatile unsigned int*)(0x42308A94UL))) +#define bM4_TMR62_ICONR_INTENOVF (*((volatile unsigned int*)(0x42308A98UL))) +#define bM4_TMR62_ICONR_INTENUDF (*((volatile unsigned int*)(0x42308A9CUL))) +#define bM4_TMR62_ICONR_INTENDTE (*((volatile unsigned int*)(0x42308AA0UL))) +#define bM4_TMR62_ICONR_INTENSAU (*((volatile unsigned int*)(0x42308AC0UL))) +#define bM4_TMR62_ICONR_INTENSAD (*((volatile unsigned int*)(0x42308AC4UL))) +#define bM4_TMR62_ICONR_INTENSBU (*((volatile unsigned int*)(0x42308AC8UL))) +#define bM4_TMR62_ICONR_INTENSBD (*((volatile unsigned int*)(0x42308ACCUL))) +#define bM4_TMR62_PCONR_CAPMDA (*((volatile unsigned int*)(0x42308B00UL))) +#define bM4_TMR62_PCONR_STACA (*((volatile unsigned int*)(0x42308B04UL))) +#define bM4_TMR62_PCONR_STPCA (*((volatile unsigned int*)(0x42308B08UL))) +#define bM4_TMR62_PCONR_STASTPSA (*((volatile unsigned int*)(0x42308B0CUL))) +#define bM4_TMR62_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42308B10UL))) +#define bM4_TMR62_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42308B14UL))) +#define bM4_TMR62_PCONR_PERCA0 (*((volatile unsigned int*)(0x42308B18UL))) +#define bM4_TMR62_PCONR_PERCA1 (*((volatile unsigned int*)(0x42308B1CUL))) +#define bM4_TMR62_PCONR_OUTENA (*((volatile unsigned int*)(0x42308B20UL))) +#define bM4_TMR62_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42308B2CUL))) +#define bM4_TMR62_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42308B30UL))) +#define bM4_TMR62_PCONR_CAPMDB (*((volatile unsigned int*)(0x42308B40UL))) +#define bM4_TMR62_PCONR_STACB (*((volatile unsigned int*)(0x42308B44UL))) +#define bM4_TMR62_PCONR_STPCB (*((volatile unsigned int*)(0x42308B48UL))) +#define bM4_TMR62_PCONR_STASTPSB (*((volatile unsigned int*)(0x42308B4CUL))) +#define bM4_TMR62_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42308B50UL))) +#define bM4_TMR62_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42308B54UL))) +#define bM4_TMR62_PCONR_PERCB0 (*((volatile unsigned int*)(0x42308B58UL))) +#define bM4_TMR62_PCONR_PERCB1 (*((volatile unsigned int*)(0x42308B5CUL))) +#define bM4_TMR62_PCONR_OUTENB (*((volatile unsigned int*)(0x42308B60UL))) +#define bM4_TMR62_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42308B6CUL))) +#define bM4_TMR62_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42308B70UL))) +#define bM4_TMR62_BCONR_BENA (*((volatile unsigned int*)(0x42308B80UL))) +#define bM4_TMR62_BCONR_BSEA (*((volatile unsigned int*)(0x42308B84UL))) +#define bM4_TMR62_BCONR_BENB (*((volatile unsigned int*)(0x42308B88UL))) +#define bM4_TMR62_BCONR_BSEB (*((volatile unsigned int*)(0x42308B8CUL))) +#define bM4_TMR62_BCONR_BENP (*((volatile unsigned int*)(0x42308BA0UL))) +#define bM4_TMR62_BCONR_BSEP (*((volatile unsigned int*)(0x42308BA4UL))) +#define bM4_TMR62_BCONR_BENSPA (*((volatile unsigned int*)(0x42308BC0UL))) +#define bM4_TMR62_BCONR_BSESPA (*((volatile unsigned int*)(0x42308BC4UL))) +#define bM4_TMR62_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42308BD0UL))) +#define bM4_TMR62_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42308BD4UL))) +#define bM4_TMR62_BCONR_BENSPB (*((volatile unsigned int*)(0x42308BE0UL))) +#define bM4_TMR62_BCONR_BSESPB (*((volatile unsigned int*)(0x42308BE4UL))) +#define bM4_TMR62_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42308BF0UL))) +#define bM4_TMR62_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42308BF4UL))) +#define bM4_TMR62_DCONR_DTCEN (*((volatile unsigned int*)(0x42308C00UL))) +#define bM4_TMR62_DCONR_DTBENU (*((volatile unsigned int*)(0x42308C10UL))) +#define bM4_TMR62_DCONR_DTBEND (*((volatile unsigned int*)(0x42308C14UL))) +#define bM4_TMR62_DCONR_SEPA (*((volatile unsigned int*)(0x42308C20UL))) +#define bM4_TMR62_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42308D00UL))) +#define bM4_TMR62_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42308D04UL))) +#define bM4_TMR62_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42308D08UL))) +#define bM4_TMR62_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42308D10UL))) +#define bM4_TMR62_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42308D14UL))) +#define bM4_TMR62_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42308D18UL))) +#define bM4_TMR62_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42308D40UL))) +#define bM4_TMR62_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42308D44UL))) +#define bM4_TMR62_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42308D48UL))) +#define bM4_TMR62_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42308D50UL))) +#define bM4_TMR62_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42308D54UL))) +#define bM4_TMR62_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42308D58UL))) +#define bM4_TMR62_VPERR_SPPERIA (*((volatile unsigned int*)(0x42308DA0UL))) +#define bM4_TMR62_VPERR_SPPERIB (*((volatile unsigned int*)(0x42308DA4UL))) +#define bM4_TMR62_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42308DC0UL))) +#define bM4_TMR62_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42308DC4UL))) +#define bM4_TMR62_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42308DC8UL))) +#define bM4_TMR62_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42308DCCUL))) +#define bM4_TMR62_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42308DD0UL))) +#define bM4_TMR62_STFLR_CMAF (*((volatile unsigned int*)(0x42308E00UL))) +#define bM4_TMR62_STFLR_CMBF (*((volatile unsigned int*)(0x42308E04UL))) +#define bM4_TMR62_STFLR_CMCF (*((volatile unsigned int*)(0x42308E08UL))) +#define bM4_TMR62_STFLR_CMDF (*((volatile unsigned int*)(0x42308E0CUL))) +#define bM4_TMR62_STFLR_CMEF (*((volatile unsigned int*)(0x42308E10UL))) +#define bM4_TMR62_STFLR_CMFF (*((volatile unsigned int*)(0x42308E14UL))) +#define bM4_TMR62_STFLR_OVFF (*((volatile unsigned int*)(0x42308E18UL))) +#define bM4_TMR62_STFLR_UDFF (*((volatile unsigned int*)(0x42308E1CUL))) +#define bM4_TMR62_STFLR_DTEF (*((volatile unsigned int*)(0x42308E20UL))) +#define bM4_TMR62_STFLR_CMSAUF (*((volatile unsigned int*)(0x42308E24UL))) +#define bM4_TMR62_STFLR_CMSADF (*((volatile unsigned int*)(0x42308E28UL))) +#define bM4_TMR62_STFLR_CMSBUF (*((volatile unsigned int*)(0x42308E2CUL))) +#define bM4_TMR62_STFLR_CMSBDF (*((volatile unsigned int*)(0x42308E30UL))) +#define bM4_TMR62_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42308E54UL))) +#define bM4_TMR62_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42308E58UL))) +#define bM4_TMR62_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42308E5CUL))) +#define bM4_TMR62_STFLR_DIRF (*((volatile unsigned int*)(0x42308E7CUL))) +#define bM4_TMR62_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42308E80UL))) +#define bM4_TMR62_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42308E84UL))) +#define bM4_TMR62_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42308E90UL))) +#define bM4_TMR62_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42308E94UL))) +#define bM4_TMR62_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42308E98UL))) +#define bM4_TMR62_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42308E9CUL))) +#define bM4_TMR62_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42308EA0UL))) +#define bM4_TMR62_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42308EA4UL))) +#define bM4_TMR62_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42308EA8UL))) +#define bM4_TMR62_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42308EACUL))) +#define bM4_TMR62_HSTAR_STARTS (*((volatile unsigned int*)(0x42308EFCUL))) +#define bM4_TMR62_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42308F00UL))) +#define bM4_TMR62_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42308F04UL))) +#define bM4_TMR62_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42308F10UL))) +#define bM4_TMR62_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42308F14UL))) +#define bM4_TMR62_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42308F18UL))) +#define bM4_TMR62_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42308F1CUL))) +#define bM4_TMR62_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42308F20UL))) +#define bM4_TMR62_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42308F24UL))) +#define bM4_TMR62_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42308F28UL))) +#define bM4_TMR62_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42308F2CUL))) +#define bM4_TMR62_HSTPR_STOPS (*((volatile unsigned int*)(0x42308F7CUL))) +#define bM4_TMR62_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42308F80UL))) +#define bM4_TMR62_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42308F84UL))) +#define bM4_TMR62_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42308F90UL))) +#define bM4_TMR62_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42308F94UL))) +#define bM4_TMR62_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42308F98UL))) +#define bM4_TMR62_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42308F9CUL))) +#define bM4_TMR62_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42308FA0UL))) +#define bM4_TMR62_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42308FA4UL))) +#define bM4_TMR62_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42308FA8UL))) +#define bM4_TMR62_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42308FACUL))) +#define bM4_TMR62_HCLRR_CLEARS (*((volatile unsigned int*)(0x42308FFCUL))) +#define bM4_TMR62_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42309000UL))) +#define bM4_TMR62_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42309004UL))) +#define bM4_TMR62_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42309010UL))) +#define bM4_TMR62_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42309014UL))) +#define bM4_TMR62_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42309018UL))) +#define bM4_TMR62_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230901CUL))) +#define bM4_TMR62_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42309020UL))) +#define bM4_TMR62_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42309024UL))) +#define bM4_TMR62_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42309028UL))) +#define bM4_TMR62_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230902CUL))) +#define bM4_TMR62_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42309080UL))) +#define bM4_TMR62_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42309084UL))) +#define bM4_TMR62_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42309090UL))) +#define bM4_TMR62_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42309094UL))) +#define bM4_TMR62_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42309098UL))) +#define bM4_TMR62_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230909CUL))) +#define bM4_TMR62_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423090A0UL))) +#define bM4_TMR62_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423090A4UL))) +#define bM4_TMR62_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423090A8UL))) +#define bM4_TMR62_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423090ACUL))) +#define bM4_TMR62_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42309100UL))) +#define bM4_TMR62_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42309104UL))) +#define bM4_TMR62_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42309108UL))) +#define bM4_TMR62_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230910CUL))) +#define bM4_TMR62_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42309110UL))) +#define bM4_TMR62_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42309114UL))) +#define bM4_TMR62_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42309118UL))) +#define bM4_TMR62_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230911CUL))) +#define bM4_TMR62_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42309120UL))) +#define bM4_TMR62_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42309124UL))) +#define bM4_TMR62_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42309128UL))) +#define bM4_TMR62_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230912CUL))) +#define bM4_TMR62_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42309140UL))) +#define bM4_TMR62_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42309144UL))) +#define bM4_TMR62_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42309180UL))) +#define bM4_TMR62_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42309184UL))) +#define bM4_TMR62_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42309188UL))) +#define bM4_TMR62_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230918CUL))) +#define bM4_TMR62_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42309190UL))) +#define bM4_TMR62_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42309194UL))) +#define bM4_TMR62_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42309198UL))) +#define bM4_TMR62_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230919CUL))) +#define bM4_TMR62_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423091A0UL))) +#define bM4_TMR62_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423091A4UL))) +#define bM4_TMR62_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423091A8UL))) +#define bM4_TMR62_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423091ACUL))) +#define bM4_TMR62_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423091C0UL))) +#define bM4_TMR62_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423091C4UL))) +#define bM4_TMR63_CNTER_CNT0 (*((volatile unsigned int*)(0x42310000UL))) +#define bM4_TMR63_CNTER_CNT1 (*((volatile unsigned int*)(0x42310004UL))) +#define bM4_TMR63_CNTER_CNT2 (*((volatile unsigned int*)(0x42310008UL))) +#define bM4_TMR63_CNTER_CNT3 (*((volatile unsigned int*)(0x4231000CUL))) +#define bM4_TMR63_CNTER_CNT4 (*((volatile unsigned int*)(0x42310010UL))) +#define bM4_TMR63_CNTER_CNT5 (*((volatile unsigned int*)(0x42310014UL))) +#define bM4_TMR63_CNTER_CNT6 (*((volatile unsigned int*)(0x42310018UL))) +#define bM4_TMR63_CNTER_CNT7 (*((volatile unsigned int*)(0x4231001CUL))) +#define bM4_TMR63_CNTER_CNT8 (*((volatile unsigned int*)(0x42310020UL))) +#define bM4_TMR63_CNTER_CNT9 (*((volatile unsigned int*)(0x42310024UL))) +#define bM4_TMR63_CNTER_CNT10 (*((volatile unsigned int*)(0x42310028UL))) +#define bM4_TMR63_CNTER_CNT11 (*((volatile unsigned int*)(0x4231002CUL))) +#define bM4_TMR63_CNTER_CNT12 (*((volatile unsigned int*)(0x42310030UL))) +#define bM4_TMR63_CNTER_CNT13 (*((volatile unsigned int*)(0x42310034UL))) +#define bM4_TMR63_CNTER_CNT14 (*((volatile unsigned int*)(0x42310038UL))) +#define bM4_TMR63_CNTER_CNT15 (*((volatile unsigned int*)(0x4231003CUL))) +#define bM4_TMR63_PERAR_PERA0 (*((volatile unsigned int*)(0x42310080UL))) +#define bM4_TMR63_PERAR_PERA1 (*((volatile unsigned int*)(0x42310084UL))) +#define bM4_TMR63_PERAR_PERA2 (*((volatile unsigned int*)(0x42310088UL))) +#define bM4_TMR63_PERAR_PERA3 (*((volatile unsigned int*)(0x4231008CUL))) +#define bM4_TMR63_PERAR_PERA4 (*((volatile unsigned int*)(0x42310090UL))) +#define bM4_TMR63_PERAR_PERA5 (*((volatile unsigned int*)(0x42310094UL))) +#define bM4_TMR63_PERAR_PERA6 (*((volatile unsigned int*)(0x42310098UL))) +#define bM4_TMR63_PERAR_PERA7 (*((volatile unsigned int*)(0x4231009CUL))) +#define bM4_TMR63_PERAR_PERA8 (*((volatile unsigned int*)(0x423100A0UL))) +#define bM4_TMR63_PERAR_PERA9 (*((volatile unsigned int*)(0x423100A4UL))) +#define bM4_TMR63_PERAR_PERA10 (*((volatile unsigned int*)(0x423100A8UL))) +#define bM4_TMR63_PERAR_PERA11 (*((volatile unsigned int*)(0x423100ACUL))) +#define bM4_TMR63_PERAR_PERA12 (*((volatile unsigned int*)(0x423100B0UL))) +#define bM4_TMR63_PERAR_PERA13 (*((volatile unsigned int*)(0x423100B4UL))) +#define bM4_TMR63_PERAR_PERA14 (*((volatile unsigned int*)(0x423100B8UL))) +#define bM4_TMR63_PERAR_PERA15 (*((volatile unsigned int*)(0x423100BCUL))) +#define bM4_TMR63_PERBR_PERB0 (*((volatile unsigned int*)(0x42310100UL))) +#define bM4_TMR63_PERBR_PERB1 (*((volatile unsigned int*)(0x42310104UL))) +#define bM4_TMR63_PERBR_PERB2 (*((volatile unsigned int*)(0x42310108UL))) +#define bM4_TMR63_PERBR_PERB3 (*((volatile unsigned int*)(0x4231010CUL))) +#define bM4_TMR63_PERBR_PERB4 (*((volatile unsigned int*)(0x42310110UL))) +#define bM4_TMR63_PERBR_PERB5 (*((volatile unsigned int*)(0x42310114UL))) +#define bM4_TMR63_PERBR_PERB6 (*((volatile unsigned int*)(0x42310118UL))) +#define bM4_TMR63_PERBR_PERB7 (*((volatile unsigned int*)(0x4231011CUL))) +#define bM4_TMR63_PERBR_PERB8 (*((volatile unsigned int*)(0x42310120UL))) +#define bM4_TMR63_PERBR_PERB9 (*((volatile unsigned int*)(0x42310124UL))) +#define bM4_TMR63_PERBR_PERB10 (*((volatile unsigned int*)(0x42310128UL))) +#define bM4_TMR63_PERBR_PERB11 (*((volatile unsigned int*)(0x4231012CUL))) +#define bM4_TMR63_PERBR_PERB12 (*((volatile unsigned int*)(0x42310130UL))) +#define bM4_TMR63_PERBR_PERB13 (*((volatile unsigned int*)(0x42310134UL))) +#define bM4_TMR63_PERBR_PERB14 (*((volatile unsigned int*)(0x42310138UL))) +#define bM4_TMR63_PERBR_PERB15 (*((volatile unsigned int*)(0x4231013CUL))) +#define bM4_TMR63_PERCR_PERC0 (*((volatile unsigned int*)(0x42310180UL))) +#define bM4_TMR63_PERCR_PERC1 (*((volatile unsigned int*)(0x42310184UL))) +#define bM4_TMR63_PERCR_PERC2 (*((volatile unsigned int*)(0x42310188UL))) +#define bM4_TMR63_PERCR_PERC3 (*((volatile unsigned int*)(0x4231018CUL))) +#define bM4_TMR63_PERCR_PERC4 (*((volatile unsigned int*)(0x42310190UL))) +#define bM4_TMR63_PERCR_PERC5 (*((volatile unsigned int*)(0x42310194UL))) +#define bM4_TMR63_PERCR_PERC6 (*((volatile unsigned int*)(0x42310198UL))) +#define bM4_TMR63_PERCR_PERC7 (*((volatile unsigned int*)(0x4231019CUL))) +#define bM4_TMR63_PERCR_PERC8 (*((volatile unsigned int*)(0x423101A0UL))) +#define bM4_TMR63_PERCR_PERC9 (*((volatile unsigned int*)(0x423101A4UL))) +#define bM4_TMR63_PERCR_PERC10 (*((volatile unsigned int*)(0x423101A8UL))) +#define bM4_TMR63_PERCR_PERC11 (*((volatile unsigned int*)(0x423101ACUL))) +#define bM4_TMR63_PERCR_PERC12 (*((volatile unsigned int*)(0x423101B0UL))) +#define bM4_TMR63_PERCR_PERC13 (*((volatile unsigned int*)(0x423101B4UL))) +#define bM4_TMR63_PERCR_PERC14 (*((volatile unsigned int*)(0x423101B8UL))) +#define bM4_TMR63_PERCR_PERC15 (*((volatile unsigned int*)(0x423101BCUL))) +#define bM4_TMR63_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42310200UL))) +#define bM4_TMR63_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42310204UL))) +#define bM4_TMR63_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42310208UL))) +#define bM4_TMR63_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4231020CUL))) +#define bM4_TMR63_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42310210UL))) +#define bM4_TMR63_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42310214UL))) +#define bM4_TMR63_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42310218UL))) +#define bM4_TMR63_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4231021CUL))) +#define bM4_TMR63_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42310220UL))) +#define bM4_TMR63_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42310224UL))) +#define bM4_TMR63_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42310228UL))) +#define bM4_TMR63_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4231022CUL))) +#define bM4_TMR63_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42310230UL))) +#define bM4_TMR63_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42310234UL))) +#define bM4_TMR63_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42310238UL))) +#define bM4_TMR63_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4231023CUL))) +#define bM4_TMR63_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42310280UL))) +#define bM4_TMR63_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42310284UL))) +#define bM4_TMR63_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42310288UL))) +#define bM4_TMR63_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4231028CUL))) +#define bM4_TMR63_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42310290UL))) +#define bM4_TMR63_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42310294UL))) +#define bM4_TMR63_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42310298UL))) +#define bM4_TMR63_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4231029CUL))) +#define bM4_TMR63_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423102A0UL))) +#define bM4_TMR63_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423102A4UL))) +#define bM4_TMR63_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423102A8UL))) +#define bM4_TMR63_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423102ACUL))) +#define bM4_TMR63_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423102B0UL))) +#define bM4_TMR63_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423102B4UL))) +#define bM4_TMR63_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423102B8UL))) +#define bM4_TMR63_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423102BCUL))) +#define bM4_TMR63_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42310300UL))) +#define bM4_TMR63_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42310304UL))) +#define bM4_TMR63_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42310308UL))) +#define bM4_TMR63_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4231030CUL))) +#define bM4_TMR63_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42310310UL))) +#define bM4_TMR63_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42310314UL))) +#define bM4_TMR63_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42310318UL))) +#define bM4_TMR63_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4231031CUL))) +#define bM4_TMR63_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42310320UL))) +#define bM4_TMR63_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42310324UL))) +#define bM4_TMR63_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42310328UL))) +#define bM4_TMR63_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4231032CUL))) +#define bM4_TMR63_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42310330UL))) +#define bM4_TMR63_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42310334UL))) +#define bM4_TMR63_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42310338UL))) +#define bM4_TMR63_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4231033CUL))) +#define bM4_TMR63_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42310380UL))) +#define bM4_TMR63_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42310384UL))) +#define bM4_TMR63_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42310388UL))) +#define bM4_TMR63_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4231038CUL))) +#define bM4_TMR63_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42310390UL))) +#define bM4_TMR63_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42310394UL))) +#define bM4_TMR63_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42310398UL))) +#define bM4_TMR63_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4231039CUL))) +#define bM4_TMR63_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423103A0UL))) +#define bM4_TMR63_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423103A4UL))) +#define bM4_TMR63_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423103A8UL))) +#define bM4_TMR63_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423103ACUL))) +#define bM4_TMR63_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423103B0UL))) +#define bM4_TMR63_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423103B4UL))) +#define bM4_TMR63_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423103B8UL))) +#define bM4_TMR63_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423103BCUL))) +#define bM4_TMR63_GCMER_GCME0 (*((volatile unsigned int*)(0x42310400UL))) +#define bM4_TMR63_GCMER_GCME1 (*((volatile unsigned int*)(0x42310404UL))) +#define bM4_TMR63_GCMER_GCME2 (*((volatile unsigned int*)(0x42310408UL))) +#define bM4_TMR63_GCMER_GCME3 (*((volatile unsigned int*)(0x4231040CUL))) +#define bM4_TMR63_GCMER_GCME4 (*((volatile unsigned int*)(0x42310410UL))) +#define bM4_TMR63_GCMER_GCME5 (*((volatile unsigned int*)(0x42310414UL))) +#define bM4_TMR63_GCMER_GCME6 (*((volatile unsigned int*)(0x42310418UL))) +#define bM4_TMR63_GCMER_GCME7 (*((volatile unsigned int*)(0x4231041CUL))) +#define bM4_TMR63_GCMER_GCME8 (*((volatile unsigned int*)(0x42310420UL))) +#define bM4_TMR63_GCMER_GCME9 (*((volatile unsigned int*)(0x42310424UL))) +#define bM4_TMR63_GCMER_GCME10 (*((volatile unsigned int*)(0x42310428UL))) +#define bM4_TMR63_GCMER_GCME11 (*((volatile unsigned int*)(0x4231042CUL))) +#define bM4_TMR63_GCMER_GCME12 (*((volatile unsigned int*)(0x42310430UL))) +#define bM4_TMR63_GCMER_GCME13 (*((volatile unsigned int*)(0x42310434UL))) +#define bM4_TMR63_GCMER_GCME14 (*((volatile unsigned int*)(0x42310438UL))) +#define bM4_TMR63_GCMER_GCME15 (*((volatile unsigned int*)(0x4231043CUL))) +#define bM4_TMR63_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42310480UL))) +#define bM4_TMR63_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42310484UL))) +#define bM4_TMR63_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42310488UL))) +#define bM4_TMR63_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4231048CUL))) +#define bM4_TMR63_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42310490UL))) +#define bM4_TMR63_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42310494UL))) +#define bM4_TMR63_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42310498UL))) +#define bM4_TMR63_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4231049CUL))) +#define bM4_TMR63_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423104A0UL))) +#define bM4_TMR63_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423104A4UL))) +#define bM4_TMR63_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423104A8UL))) +#define bM4_TMR63_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423104ACUL))) +#define bM4_TMR63_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423104B0UL))) +#define bM4_TMR63_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423104B4UL))) +#define bM4_TMR63_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423104B8UL))) +#define bM4_TMR63_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423104BCUL))) +#define bM4_TMR63_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42310500UL))) +#define bM4_TMR63_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42310504UL))) +#define bM4_TMR63_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42310508UL))) +#define bM4_TMR63_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4231050CUL))) +#define bM4_TMR63_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42310510UL))) +#define bM4_TMR63_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42310514UL))) +#define bM4_TMR63_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42310518UL))) +#define bM4_TMR63_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4231051CUL))) +#define bM4_TMR63_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42310520UL))) +#define bM4_TMR63_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42310524UL))) +#define bM4_TMR63_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42310528UL))) +#define bM4_TMR63_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4231052CUL))) +#define bM4_TMR63_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42310530UL))) +#define bM4_TMR63_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42310534UL))) +#define bM4_TMR63_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42310538UL))) +#define bM4_TMR63_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4231053CUL))) +#define bM4_TMR63_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42310580UL))) +#define bM4_TMR63_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42310584UL))) +#define bM4_TMR63_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42310588UL))) +#define bM4_TMR63_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4231058CUL))) +#define bM4_TMR63_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42310590UL))) +#define bM4_TMR63_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42310594UL))) +#define bM4_TMR63_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42310598UL))) +#define bM4_TMR63_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4231059CUL))) +#define bM4_TMR63_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423105A0UL))) +#define bM4_TMR63_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423105A4UL))) +#define bM4_TMR63_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423105A8UL))) +#define bM4_TMR63_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423105ACUL))) +#define bM4_TMR63_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423105B0UL))) +#define bM4_TMR63_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423105B4UL))) +#define bM4_TMR63_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423105B8UL))) +#define bM4_TMR63_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423105BCUL))) +#define bM4_TMR63_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42310600UL))) +#define bM4_TMR63_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42310604UL))) +#define bM4_TMR63_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42310608UL))) +#define bM4_TMR63_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4231060CUL))) +#define bM4_TMR63_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42310610UL))) +#define bM4_TMR63_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42310614UL))) +#define bM4_TMR63_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42310618UL))) +#define bM4_TMR63_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4231061CUL))) +#define bM4_TMR63_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42310620UL))) +#define bM4_TMR63_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42310624UL))) +#define bM4_TMR63_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42310628UL))) +#define bM4_TMR63_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4231062CUL))) +#define bM4_TMR63_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42310630UL))) +#define bM4_TMR63_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42310634UL))) +#define bM4_TMR63_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42310638UL))) +#define bM4_TMR63_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4231063CUL))) +#define bM4_TMR63_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42310680UL))) +#define bM4_TMR63_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42310684UL))) +#define bM4_TMR63_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42310688UL))) +#define bM4_TMR63_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4231068CUL))) +#define bM4_TMR63_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42310690UL))) +#define bM4_TMR63_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42310694UL))) +#define bM4_TMR63_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42310698UL))) +#define bM4_TMR63_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4231069CUL))) +#define bM4_TMR63_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423106A0UL))) +#define bM4_TMR63_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423106A4UL))) +#define bM4_TMR63_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423106A8UL))) +#define bM4_TMR63_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423106ACUL))) +#define bM4_TMR63_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423106B0UL))) +#define bM4_TMR63_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423106B4UL))) +#define bM4_TMR63_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423106B8UL))) +#define bM4_TMR63_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423106BCUL))) +#define bM4_TMR63_SCMER_SCME0 (*((volatile unsigned int*)(0x42310700UL))) +#define bM4_TMR63_SCMER_SCME1 (*((volatile unsigned int*)(0x42310704UL))) +#define bM4_TMR63_SCMER_SCME2 (*((volatile unsigned int*)(0x42310708UL))) +#define bM4_TMR63_SCMER_SCME3 (*((volatile unsigned int*)(0x4231070CUL))) +#define bM4_TMR63_SCMER_SCME4 (*((volatile unsigned int*)(0x42310710UL))) +#define bM4_TMR63_SCMER_SCME5 (*((volatile unsigned int*)(0x42310714UL))) +#define bM4_TMR63_SCMER_SCME6 (*((volatile unsigned int*)(0x42310718UL))) +#define bM4_TMR63_SCMER_SCME7 (*((volatile unsigned int*)(0x4231071CUL))) +#define bM4_TMR63_SCMER_SCME8 (*((volatile unsigned int*)(0x42310720UL))) +#define bM4_TMR63_SCMER_SCME9 (*((volatile unsigned int*)(0x42310724UL))) +#define bM4_TMR63_SCMER_SCME10 (*((volatile unsigned int*)(0x42310728UL))) +#define bM4_TMR63_SCMER_SCME11 (*((volatile unsigned int*)(0x4231072CUL))) +#define bM4_TMR63_SCMER_SCME12 (*((volatile unsigned int*)(0x42310730UL))) +#define bM4_TMR63_SCMER_SCME13 (*((volatile unsigned int*)(0x42310734UL))) +#define bM4_TMR63_SCMER_SCME14 (*((volatile unsigned int*)(0x42310738UL))) +#define bM4_TMR63_SCMER_SCME15 (*((volatile unsigned int*)(0x4231073CUL))) +#define bM4_TMR63_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42310780UL))) +#define bM4_TMR63_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42310784UL))) +#define bM4_TMR63_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42310788UL))) +#define bM4_TMR63_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4231078CUL))) +#define bM4_TMR63_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42310790UL))) +#define bM4_TMR63_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42310794UL))) +#define bM4_TMR63_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42310798UL))) +#define bM4_TMR63_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4231079CUL))) +#define bM4_TMR63_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423107A0UL))) +#define bM4_TMR63_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423107A4UL))) +#define bM4_TMR63_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423107A8UL))) +#define bM4_TMR63_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423107ACUL))) +#define bM4_TMR63_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423107B0UL))) +#define bM4_TMR63_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423107B4UL))) +#define bM4_TMR63_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423107B8UL))) +#define bM4_TMR63_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423107BCUL))) +#define bM4_TMR63_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42310800UL))) +#define bM4_TMR63_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42310804UL))) +#define bM4_TMR63_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42310808UL))) +#define bM4_TMR63_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4231080CUL))) +#define bM4_TMR63_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42310810UL))) +#define bM4_TMR63_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42310814UL))) +#define bM4_TMR63_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42310818UL))) +#define bM4_TMR63_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4231081CUL))) +#define bM4_TMR63_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42310820UL))) +#define bM4_TMR63_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42310824UL))) +#define bM4_TMR63_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42310828UL))) +#define bM4_TMR63_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4231082CUL))) +#define bM4_TMR63_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42310830UL))) +#define bM4_TMR63_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42310834UL))) +#define bM4_TMR63_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42310838UL))) +#define bM4_TMR63_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4231083CUL))) +#define bM4_TMR63_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42310880UL))) +#define bM4_TMR63_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42310884UL))) +#define bM4_TMR63_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42310888UL))) +#define bM4_TMR63_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4231088CUL))) +#define bM4_TMR63_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42310890UL))) +#define bM4_TMR63_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42310894UL))) +#define bM4_TMR63_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42310898UL))) +#define bM4_TMR63_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4231089CUL))) +#define bM4_TMR63_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423108A0UL))) +#define bM4_TMR63_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423108A4UL))) +#define bM4_TMR63_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423108A8UL))) +#define bM4_TMR63_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423108ACUL))) +#define bM4_TMR63_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423108B0UL))) +#define bM4_TMR63_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423108B4UL))) +#define bM4_TMR63_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423108B8UL))) +#define bM4_TMR63_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423108BCUL))) +#define bM4_TMR63_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42310900UL))) +#define bM4_TMR63_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42310904UL))) +#define bM4_TMR63_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42310908UL))) +#define bM4_TMR63_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4231090CUL))) +#define bM4_TMR63_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42310910UL))) +#define bM4_TMR63_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42310914UL))) +#define bM4_TMR63_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42310918UL))) +#define bM4_TMR63_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4231091CUL))) +#define bM4_TMR63_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42310920UL))) +#define bM4_TMR63_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42310924UL))) +#define bM4_TMR63_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42310928UL))) +#define bM4_TMR63_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4231092CUL))) +#define bM4_TMR63_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42310930UL))) +#define bM4_TMR63_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42310934UL))) +#define bM4_TMR63_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42310938UL))) +#define bM4_TMR63_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4231093CUL))) +#define bM4_TMR63_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42310980UL))) +#define bM4_TMR63_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42310984UL))) +#define bM4_TMR63_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42310988UL))) +#define bM4_TMR63_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4231098CUL))) +#define bM4_TMR63_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42310990UL))) +#define bM4_TMR63_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42310994UL))) +#define bM4_TMR63_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42310998UL))) +#define bM4_TMR63_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4231099CUL))) +#define bM4_TMR63_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423109A0UL))) +#define bM4_TMR63_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423109A4UL))) +#define bM4_TMR63_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423109A8UL))) +#define bM4_TMR63_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423109ACUL))) +#define bM4_TMR63_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423109B0UL))) +#define bM4_TMR63_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423109B4UL))) +#define bM4_TMR63_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423109B8UL))) +#define bM4_TMR63_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423109BCUL))) +#define bM4_TMR63_GCONR_START (*((volatile unsigned int*)(0x42310A00UL))) +#define bM4_TMR63_GCONR_MODE0 (*((volatile unsigned int*)(0x42310A04UL))) +#define bM4_TMR63_GCONR_MODE1 (*((volatile unsigned int*)(0x42310A08UL))) +#define bM4_TMR63_GCONR_MODE2 (*((volatile unsigned int*)(0x42310A0CUL))) +#define bM4_TMR63_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42310A10UL))) +#define bM4_TMR63_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42310A14UL))) +#define bM4_TMR63_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42310A18UL))) +#define bM4_TMR63_GCONR_DIR (*((volatile unsigned int*)(0x42310A20UL))) +#define bM4_TMR63_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42310A40UL))) +#define bM4_TMR63_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42310A44UL))) +#define bM4_TMR63_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42310A48UL))) +#define bM4_TMR63_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42310A4CUL))) +#define bM4_TMR63_ICONR_INTENA (*((volatile unsigned int*)(0x42310A80UL))) +#define bM4_TMR63_ICONR_INTENB (*((volatile unsigned int*)(0x42310A84UL))) +#define bM4_TMR63_ICONR_INTENC (*((volatile unsigned int*)(0x42310A88UL))) +#define bM4_TMR63_ICONR_INTEND (*((volatile unsigned int*)(0x42310A8CUL))) +#define bM4_TMR63_ICONR_INTENE (*((volatile unsigned int*)(0x42310A90UL))) +#define bM4_TMR63_ICONR_INTENF (*((volatile unsigned int*)(0x42310A94UL))) +#define bM4_TMR63_ICONR_INTENOVF (*((volatile unsigned int*)(0x42310A98UL))) +#define bM4_TMR63_ICONR_INTENUDF (*((volatile unsigned int*)(0x42310A9CUL))) +#define bM4_TMR63_ICONR_INTENDTE (*((volatile unsigned int*)(0x42310AA0UL))) +#define bM4_TMR63_ICONR_INTENSAU (*((volatile unsigned int*)(0x42310AC0UL))) +#define bM4_TMR63_ICONR_INTENSAD (*((volatile unsigned int*)(0x42310AC4UL))) +#define bM4_TMR63_ICONR_INTENSBU (*((volatile unsigned int*)(0x42310AC8UL))) +#define bM4_TMR63_ICONR_INTENSBD (*((volatile unsigned int*)(0x42310ACCUL))) +#define bM4_TMR63_PCONR_CAPMDA (*((volatile unsigned int*)(0x42310B00UL))) +#define bM4_TMR63_PCONR_STACA (*((volatile unsigned int*)(0x42310B04UL))) +#define bM4_TMR63_PCONR_STPCA (*((volatile unsigned int*)(0x42310B08UL))) +#define bM4_TMR63_PCONR_STASTPSA (*((volatile unsigned int*)(0x42310B0CUL))) +#define bM4_TMR63_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42310B10UL))) +#define bM4_TMR63_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42310B14UL))) +#define bM4_TMR63_PCONR_PERCA0 (*((volatile unsigned int*)(0x42310B18UL))) +#define bM4_TMR63_PCONR_PERCA1 (*((volatile unsigned int*)(0x42310B1CUL))) +#define bM4_TMR63_PCONR_OUTENA (*((volatile unsigned int*)(0x42310B20UL))) +#define bM4_TMR63_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42310B2CUL))) +#define bM4_TMR63_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42310B30UL))) +#define bM4_TMR63_PCONR_CAPMDB (*((volatile unsigned int*)(0x42310B40UL))) +#define bM4_TMR63_PCONR_STACB (*((volatile unsigned int*)(0x42310B44UL))) +#define bM4_TMR63_PCONR_STPCB (*((volatile unsigned int*)(0x42310B48UL))) +#define bM4_TMR63_PCONR_STASTPSB (*((volatile unsigned int*)(0x42310B4CUL))) +#define bM4_TMR63_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42310B50UL))) +#define bM4_TMR63_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42310B54UL))) +#define bM4_TMR63_PCONR_PERCB0 (*((volatile unsigned int*)(0x42310B58UL))) +#define bM4_TMR63_PCONR_PERCB1 (*((volatile unsigned int*)(0x42310B5CUL))) +#define bM4_TMR63_PCONR_OUTENB (*((volatile unsigned int*)(0x42310B60UL))) +#define bM4_TMR63_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42310B6CUL))) +#define bM4_TMR63_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42310B70UL))) +#define bM4_TMR63_BCONR_BENA (*((volatile unsigned int*)(0x42310B80UL))) +#define bM4_TMR63_BCONR_BSEA (*((volatile unsigned int*)(0x42310B84UL))) +#define bM4_TMR63_BCONR_BENB (*((volatile unsigned int*)(0x42310B88UL))) +#define bM4_TMR63_BCONR_BSEB (*((volatile unsigned int*)(0x42310B8CUL))) +#define bM4_TMR63_BCONR_BENP (*((volatile unsigned int*)(0x42310BA0UL))) +#define bM4_TMR63_BCONR_BSEP (*((volatile unsigned int*)(0x42310BA4UL))) +#define bM4_TMR63_BCONR_BENSPA (*((volatile unsigned int*)(0x42310BC0UL))) +#define bM4_TMR63_BCONR_BSESPA (*((volatile unsigned int*)(0x42310BC4UL))) +#define bM4_TMR63_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42310BD0UL))) +#define bM4_TMR63_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42310BD4UL))) +#define bM4_TMR63_BCONR_BENSPB (*((volatile unsigned int*)(0x42310BE0UL))) +#define bM4_TMR63_BCONR_BSESPB (*((volatile unsigned int*)(0x42310BE4UL))) +#define bM4_TMR63_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42310BF0UL))) +#define bM4_TMR63_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42310BF4UL))) +#define bM4_TMR63_DCONR_DTCEN (*((volatile unsigned int*)(0x42310C00UL))) +#define bM4_TMR63_DCONR_DTBENU (*((volatile unsigned int*)(0x42310C10UL))) +#define bM4_TMR63_DCONR_DTBEND (*((volatile unsigned int*)(0x42310C14UL))) +#define bM4_TMR63_DCONR_SEPA (*((volatile unsigned int*)(0x42310C20UL))) +#define bM4_TMR63_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42310D00UL))) +#define bM4_TMR63_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42310D04UL))) +#define bM4_TMR63_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42310D08UL))) +#define bM4_TMR63_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42310D10UL))) +#define bM4_TMR63_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42310D14UL))) +#define bM4_TMR63_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42310D18UL))) +#define bM4_TMR63_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42310D40UL))) +#define bM4_TMR63_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42310D44UL))) +#define bM4_TMR63_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42310D48UL))) +#define bM4_TMR63_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42310D50UL))) +#define bM4_TMR63_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42310D54UL))) +#define bM4_TMR63_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42310D58UL))) +#define bM4_TMR63_VPERR_SPPERIA (*((volatile unsigned int*)(0x42310DA0UL))) +#define bM4_TMR63_VPERR_SPPERIB (*((volatile unsigned int*)(0x42310DA4UL))) +#define bM4_TMR63_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42310DC0UL))) +#define bM4_TMR63_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42310DC4UL))) +#define bM4_TMR63_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42310DC8UL))) +#define bM4_TMR63_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42310DCCUL))) +#define bM4_TMR63_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42310DD0UL))) +#define bM4_TMR63_STFLR_CMAF (*((volatile unsigned int*)(0x42310E00UL))) +#define bM4_TMR63_STFLR_CMBF (*((volatile unsigned int*)(0x42310E04UL))) +#define bM4_TMR63_STFLR_CMCF (*((volatile unsigned int*)(0x42310E08UL))) +#define bM4_TMR63_STFLR_CMDF (*((volatile unsigned int*)(0x42310E0CUL))) +#define bM4_TMR63_STFLR_CMEF (*((volatile unsigned int*)(0x42310E10UL))) +#define bM4_TMR63_STFLR_CMFF (*((volatile unsigned int*)(0x42310E14UL))) +#define bM4_TMR63_STFLR_OVFF (*((volatile unsigned int*)(0x42310E18UL))) +#define bM4_TMR63_STFLR_UDFF (*((volatile unsigned int*)(0x42310E1CUL))) +#define bM4_TMR63_STFLR_DTEF (*((volatile unsigned int*)(0x42310E20UL))) +#define bM4_TMR63_STFLR_CMSAUF (*((volatile unsigned int*)(0x42310E24UL))) +#define bM4_TMR63_STFLR_CMSADF (*((volatile unsigned int*)(0x42310E28UL))) +#define bM4_TMR63_STFLR_CMSBUF (*((volatile unsigned int*)(0x42310E2CUL))) +#define bM4_TMR63_STFLR_CMSBDF (*((volatile unsigned int*)(0x42310E30UL))) +#define bM4_TMR63_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42310E54UL))) +#define bM4_TMR63_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42310E58UL))) +#define bM4_TMR63_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42310E5CUL))) +#define bM4_TMR63_STFLR_DIRF (*((volatile unsigned int*)(0x42310E7CUL))) +#define bM4_TMR63_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42310E80UL))) +#define bM4_TMR63_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42310E84UL))) +#define bM4_TMR63_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42310E90UL))) +#define bM4_TMR63_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42310E94UL))) +#define bM4_TMR63_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42310E98UL))) +#define bM4_TMR63_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42310E9CUL))) +#define bM4_TMR63_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42310EA0UL))) +#define bM4_TMR63_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42310EA4UL))) +#define bM4_TMR63_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42310EA8UL))) +#define bM4_TMR63_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42310EACUL))) +#define bM4_TMR63_HSTAR_STARTS (*((volatile unsigned int*)(0x42310EFCUL))) +#define bM4_TMR63_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42310F00UL))) +#define bM4_TMR63_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42310F04UL))) +#define bM4_TMR63_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42310F10UL))) +#define bM4_TMR63_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42310F14UL))) +#define bM4_TMR63_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42310F18UL))) +#define bM4_TMR63_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42310F1CUL))) +#define bM4_TMR63_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42310F20UL))) +#define bM4_TMR63_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42310F24UL))) +#define bM4_TMR63_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42310F28UL))) +#define bM4_TMR63_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42310F2CUL))) +#define bM4_TMR63_HSTPR_STOPS (*((volatile unsigned int*)(0x42310F7CUL))) +#define bM4_TMR63_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42310F80UL))) +#define bM4_TMR63_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42310F84UL))) +#define bM4_TMR63_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42310F90UL))) +#define bM4_TMR63_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42310F94UL))) +#define bM4_TMR63_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42310F98UL))) +#define bM4_TMR63_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42310F9CUL))) +#define bM4_TMR63_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42310FA0UL))) +#define bM4_TMR63_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42310FA4UL))) +#define bM4_TMR63_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42310FA8UL))) +#define bM4_TMR63_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42310FACUL))) +#define bM4_TMR63_HCLRR_CLEARS (*((volatile unsigned int*)(0x42310FFCUL))) +#define bM4_TMR63_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42311000UL))) +#define bM4_TMR63_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42311004UL))) +#define bM4_TMR63_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42311010UL))) +#define bM4_TMR63_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42311014UL))) +#define bM4_TMR63_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42311018UL))) +#define bM4_TMR63_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4231101CUL))) +#define bM4_TMR63_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42311020UL))) +#define bM4_TMR63_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42311024UL))) +#define bM4_TMR63_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42311028UL))) +#define bM4_TMR63_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4231102CUL))) +#define bM4_TMR63_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42311080UL))) +#define bM4_TMR63_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42311084UL))) +#define bM4_TMR63_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42311090UL))) +#define bM4_TMR63_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42311094UL))) +#define bM4_TMR63_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42311098UL))) +#define bM4_TMR63_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4231109CUL))) +#define bM4_TMR63_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423110A0UL))) +#define bM4_TMR63_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423110A4UL))) +#define bM4_TMR63_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423110A8UL))) +#define bM4_TMR63_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423110ACUL))) +#define bM4_TMR63_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42311100UL))) +#define bM4_TMR63_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42311104UL))) +#define bM4_TMR63_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42311108UL))) +#define bM4_TMR63_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4231110CUL))) +#define bM4_TMR63_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42311110UL))) +#define bM4_TMR63_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42311114UL))) +#define bM4_TMR63_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42311118UL))) +#define bM4_TMR63_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4231111CUL))) +#define bM4_TMR63_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42311120UL))) +#define bM4_TMR63_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42311124UL))) +#define bM4_TMR63_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42311128UL))) +#define bM4_TMR63_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4231112CUL))) +#define bM4_TMR63_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42311140UL))) +#define bM4_TMR63_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42311144UL))) +#define bM4_TMR63_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42311180UL))) +#define bM4_TMR63_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42311184UL))) +#define bM4_TMR63_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42311188UL))) +#define bM4_TMR63_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4231118CUL))) +#define bM4_TMR63_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42311190UL))) +#define bM4_TMR63_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42311194UL))) +#define bM4_TMR63_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42311198UL))) +#define bM4_TMR63_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4231119CUL))) +#define bM4_TMR63_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423111A0UL))) +#define bM4_TMR63_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423111A4UL))) +#define bM4_TMR63_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423111A8UL))) +#define bM4_TMR63_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423111ACUL))) +#define bM4_TMR63_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423111C0UL))) +#define bM4_TMR63_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423111C4UL))) +#define bM4_TMR6_CR_SSTAR_SSTA1 (*((volatile unsigned int*)(0x42307E80UL))) +#define bM4_TMR6_CR_SSTAR_SSTA2 (*((volatile unsigned int*)(0x42307E84UL))) +#define bM4_TMR6_CR_SSTAR_SSTA3 (*((volatile unsigned int*)(0x42307E88UL))) +#define bM4_TMR6_CR_SSTAR_RESV0 (*((volatile unsigned int*)(0x42307EC0UL))) +#define bM4_TMR6_CR_SSTAR_RESV (*((volatile unsigned int*)(0x42307EE0UL))) +#define bM4_TMR6_CR_SSTPR_SSTP1 (*((volatile unsigned int*)(0x42307F00UL))) +#define bM4_TMR6_CR_SSTPR_SSTP2 (*((volatile unsigned int*)(0x42307F04UL))) +#define bM4_TMR6_CR_SSTPR_SSTP3 (*((volatile unsigned int*)(0x42307F08UL))) +#define bM4_TMR6_CR_SCLRR_SCLE1 (*((volatile unsigned int*)(0x42307F80UL))) +#define bM4_TMR6_CR_SCLRR_SCLE2 (*((volatile unsigned int*)(0x42307F84UL))) +#define bM4_TMR6_CR_SCLRR_SCLE3 (*((volatile unsigned int*)(0x42307F88UL))) +#define bM4_TMRA1_CNTER_CNT0 (*((volatile unsigned int*)(0x422A0000UL))) +#define bM4_TMRA1_CNTER_CNT1 (*((volatile unsigned int*)(0x422A0004UL))) +#define bM4_TMRA1_CNTER_CNT2 (*((volatile unsigned int*)(0x422A0008UL))) +#define bM4_TMRA1_CNTER_CNT3 (*((volatile unsigned int*)(0x422A000CUL))) +#define bM4_TMRA1_CNTER_CNT4 (*((volatile unsigned int*)(0x422A0010UL))) +#define bM4_TMRA1_CNTER_CNT5 (*((volatile unsigned int*)(0x422A0014UL))) +#define bM4_TMRA1_CNTER_CNT6 (*((volatile unsigned int*)(0x422A0018UL))) +#define bM4_TMRA1_CNTER_CNT7 (*((volatile unsigned int*)(0x422A001CUL))) +#define bM4_TMRA1_CNTER_CNT8 (*((volatile unsigned int*)(0x422A0020UL))) +#define bM4_TMRA1_CNTER_CNT9 (*((volatile unsigned int*)(0x422A0024UL))) +#define bM4_TMRA1_CNTER_CNT10 (*((volatile unsigned int*)(0x422A0028UL))) +#define bM4_TMRA1_CNTER_CNT11 (*((volatile unsigned int*)(0x422A002CUL))) +#define bM4_TMRA1_CNTER_CNT12 (*((volatile unsigned int*)(0x422A0030UL))) +#define bM4_TMRA1_CNTER_CNT13 (*((volatile unsigned int*)(0x422A0034UL))) +#define bM4_TMRA1_CNTER_CNT14 (*((volatile unsigned int*)(0x422A0038UL))) +#define bM4_TMRA1_CNTER_CNT15 (*((volatile unsigned int*)(0x422A003CUL))) +#define bM4_TMRA1_PERAR_PER0 (*((volatile unsigned int*)(0x422A0080UL))) +#define bM4_TMRA1_PERAR_PER1 (*((volatile unsigned int*)(0x422A0084UL))) +#define bM4_TMRA1_PERAR_PER2 (*((volatile unsigned int*)(0x422A0088UL))) +#define bM4_TMRA1_PERAR_PER3 (*((volatile unsigned int*)(0x422A008CUL))) +#define bM4_TMRA1_PERAR_PER4 (*((volatile unsigned int*)(0x422A0090UL))) +#define bM4_TMRA1_PERAR_PER5 (*((volatile unsigned int*)(0x422A0094UL))) +#define bM4_TMRA1_PERAR_PER6 (*((volatile unsigned int*)(0x422A0098UL))) +#define bM4_TMRA1_PERAR_PER7 (*((volatile unsigned int*)(0x422A009CUL))) +#define bM4_TMRA1_PERAR_PER8 (*((volatile unsigned int*)(0x422A00A0UL))) +#define bM4_TMRA1_PERAR_PER9 (*((volatile unsigned int*)(0x422A00A4UL))) +#define bM4_TMRA1_PERAR_PER10 (*((volatile unsigned int*)(0x422A00A8UL))) +#define bM4_TMRA1_PERAR_PER11 (*((volatile unsigned int*)(0x422A00ACUL))) +#define bM4_TMRA1_PERAR_PER12 (*((volatile unsigned int*)(0x422A00B0UL))) +#define bM4_TMRA1_PERAR_PER13 (*((volatile unsigned int*)(0x422A00B4UL))) +#define bM4_TMRA1_PERAR_PER14 (*((volatile unsigned int*)(0x422A00B8UL))) +#define bM4_TMRA1_PERAR_PER15 (*((volatile unsigned int*)(0x422A00BCUL))) +#define bM4_TMRA1_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A0800UL))) +#define bM4_TMRA1_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A0804UL))) +#define bM4_TMRA1_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A0808UL))) +#define bM4_TMRA1_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A080CUL))) +#define bM4_TMRA1_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A0810UL))) +#define bM4_TMRA1_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A0814UL))) +#define bM4_TMRA1_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A0818UL))) +#define bM4_TMRA1_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A081CUL))) +#define bM4_TMRA1_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A0820UL))) +#define bM4_TMRA1_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A0824UL))) +#define bM4_TMRA1_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A0828UL))) +#define bM4_TMRA1_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A082CUL))) +#define bM4_TMRA1_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A0830UL))) +#define bM4_TMRA1_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A0834UL))) +#define bM4_TMRA1_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A0838UL))) +#define bM4_TMRA1_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A083CUL))) +#define bM4_TMRA1_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A0880UL))) +#define bM4_TMRA1_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A0884UL))) +#define bM4_TMRA1_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A0888UL))) +#define bM4_TMRA1_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A088CUL))) +#define bM4_TMRA1_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A0890UL))) +#define bM4_TMRA1_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A0894UL))) +#define bM4_TMRA1_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A0898UL))) +#define bM4_TMRA1_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A089CUL))) +#define bM4_TMRA1_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A08A0UL))) +#define bM4_TMRA1_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A08A4UL))) +#define bM4_TMRA1_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A08A8UL))) +#define bM4_TMRA1_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A08ACUL))) +#define bM4_TMRA1_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A08B0UL))) +#define bM4_TMRA1_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A08B4UL))) +#define bM4_TMRA1_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A08B8UL))) +#define bM4_TMRA1_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A08BCUL))) +#define bM4_TMRA1_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A0900UL))) +#define bM4_TMRA1_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A0904UL))) +#define bM4_TMRA1_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A0908UL))) +#define bM4_TMRA1_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A090CUL))) +#define bM4_TMRA1_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A0910UL))) +#define bM4_TMRA1_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A0914UL))) +#define bM4_TMRA1_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A0918UL))) +#define bM4_TMRA1_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A091CUL))) +#define bM4_TMRA1_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A0920UL))) +#define bM4_TMRA1_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A0924UL))) +#define bM4_TMRA1_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A0928UL))) +#define bM4_TMRA1_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A092CUL))) +#define bM4_TMRA1_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A0930UL))) +#define bM4_TMRA1_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A0934UL))) +#define bM4_TMRA1_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A0938UL))) +#define bM4_TMRA1_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A093CUL))) +#define bM4_TMRA1_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A0980UL))) +#define bM4_TMRA1_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A0984UL))) +#define bM4_TMRA1_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A0988UL))) +#define bM4_TMRA1_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A098CUL))) +#define bM4_TMRA1_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A0990UL))) +#define bM4_TMRA1_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A0994UL))) +#define bM4_TMRA1_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A0998UL))) +#define bM4_TMRA1_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A099CUL))) +#define bM4_TMRA1_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A09A0UL))) +#define bM4_TMRA1_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A09A4UL))) +#define bM4_TMRA1_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A09A8UL))) +#define bM4_TMRA1_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A09ACUL))) +#define bM4_TMRA1_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A09B0UL))) +#define bM4_TMRA1_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A09B4UL))) +#define bM4_TMRA1_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A09B8UL))) +#define bM4_TMRA1_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A09BCUL))) +#define bM4_TMRA1_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A0A00UL))) +#define bM4_TMRA1_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A0A04UL))) +#define bM4_TMRA1_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A0A08UL))) +#define bM4_TMRA1_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A0A0CUL))) +#define bM4_TMRA1_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A0A10UL))) +#define bM4_TMRA1_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A0A14UL))) +#define bM4_TMRA1_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A0A18UL))) +#define bM4_TMRA1_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A0A1CUL))) +#define bM4_TMRA1_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A0A20UL))) +#define bM4_TMRA1_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A0A24UL))) +#define bM4_TMRA1_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A0A28UL))) +#define bM4_TMRA1_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A0A2CUL))) +#define bM4_TMRA1_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A0A30UL))) +#define bM4_TMRA1_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A0A34UL))) +#define bM4_TMRA1_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A0A38UL))) +#define bM4_TMRA1_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A0A3CUL))) +#define bM4_TMRA1_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A0A80UL))) +#define bM4_TMRA1_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A0A84UL))) +#define bM4_TMRA1_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A0A88UL))) +#define bM4_TMRA1_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A0A8CUL))) +#define bM4_TMRA1_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A0A90UL))) +#define bM4_TMRA1_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A0A94UL))) +#define bM4_TMRA1_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A0A98UL))) +#define bM4_TMRA1_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A0A9CUL))) +#define bM4_TMRA1_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A0AA0UL))) +#define bM4_TMRA1_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A0AA4UL))) +#define bM4_TMRA1_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A0AA8UL))) +#define bM4_TMRA1_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A0AACUL))) +#define bM4_TMRA1_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A0AB0UL))) +#define bM4_TMRA1_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A0AB4UL))) +#define bM4_TMRA1_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A0AB8UL))) +#define bM4_TMRA1_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A0ABCUL))) +#define bM4_TMRA1_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A0B00UL))) +#define bM4_TMRA1_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A0B04UL))) +#define bM4_TMRA1_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A0B08UL))) +#define bM4_TMRA1_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A0B0CUL))) +#define bM4_TMRA1_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A0B10UL))) +#define bM4_TMRA1_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A0B14UL))) +#define bM4_TMRA1_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A0B18UL))) +#define bM4_TMRA1_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A0B1CUL))) +#define bM4_TMRA1_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A0B20UL))) +#define bM4_TMRA1_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A0B24UL))) +#define bM4_TMRA1_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A0B28UL))) +#define bM4_TMRA1_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A0B2CUL))) +#define bM4_TMRA1_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A0B30UL))) +#define bM4_TMRA1_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A0B34UL))) +#define bM4_TMRA1_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A0B38UL))) +#define bM4_TMRA1_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A0B3CUL))) +#define bM4_TMRA1_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A0B80UL))) +#define bM4_TMRA1_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A0B84UL))) +#define bM4_TMRA1_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A0B88UL))) +#define bM4_TMRA1_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A0B8CUL))) +#define bM4_TMRA1_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A0B90UL))) +#define bM4_TMRA1_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A0B94UL))) +#define bM4_TMRA1_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A0B98UL))) +#define bM4_TMRA1_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A0B9CUL))) +#define bM4_TMRA1_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A0BA0UL))) +#define bM4_TMRA1_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A0BA4UL))) +#define bM4_TMRA1_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A0BA8UL))) +#define bM4_TMRA1_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A0BACUL))) +#define bM4_TMRA1_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A0BB0UL))) +#define bM4_TMRA1_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A0BB4UL))) +#define bM4_TMRA1_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A0BB8UL))) +#define bM4_TMRA1_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A0BBCUL))) +#define bM4_TMRA1_BCSTR_START (*((volatile unsigned int*)(0x422A1000UL))) +#define bM4_TMRA1_BCSTR_DIR (*((volatile unsigned int*)(0x422A1004UL))) +#define bM4_TMRA1_BCSTR_MODE (*((volatile unsigned int*)(0x422A1008UL))) +#define bM4_TMRA1_BCSTR_SYNST (*((volatile unsigned int*)(0x422A100CUL))) +#define bM4_TMRA1_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A1010UL))) +#define bM4_TMRA1_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A1014UL))) +#define bM4_TMRA1_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A1018UL))) +#define bM4_TMRA1_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A101CUL))) +#define bM4_TMRA1_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A1030UL))) +#define bM4_TMRA1_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A1034UL))) +#define bM4_TMRA1_BCSTR_OVFF (*((volatile unsigned int*)(0x422A1038UL))) +#define bM4_TMRA1_BCSTR_UDFF (*((volatile unsigned int*)(0x422A103CUL))) +#define bM4_TMRA1_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A1080UL))) +#define bM4_TMRA1_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A1084UL))) +#define bM4_TMRA1_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A1088UL))) +#define bM4_TMRA1_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A1090UL))) +#define bM4_TMRA1_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A1094UL))) +#define bM4_TMRA1_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A1098UL))) +#define bM4_TMRA1_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A10A0UL))) +#define bM4_TMRA1_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A10A4UL))) +#define bM4_TMRA1_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A10A8UL))) +#define bM4_TMRA1_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A10B0UL))) +#define bM4_TMRA1_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A10B4UL))) +#define bM4_TMRA1_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A10B8UL))) +#define bM4_TMRA1_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A10BCUL))) +#define bM4_TMRA1_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A1100UL))) +#define bM4_TMRA1_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A1104UL))) +#define bM4_TMRA1_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A1108UL))) +#define bM4_TMRA1_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A110CUL))) +#define bM4_TMRA1_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A1110UL))) +#define bM4_TMRA1_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A1114UL))) +#define bM4_TMRA1_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A1118UL))) +#define bM4_TMRA1_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A111CUL))) +#define bM4_TMRA1_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A1120UL))) +#define bM4_TMRA1_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A1124UL))) +#define bM4_TMRA1_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A1128UL))) +#define bM4_TMRA1_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A112CUL))) +#define bM4_TMRA1_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A1130UL))) +#define bM4_TMRA1_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A1180UL))) +#define bM4_TMRA1_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A1184UL))) +#define bM4_TMRA1_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A1188UL))) +#define bM4_TMRA1_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A118CUL))) +#define bM4_TMRA1_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A1190UL))) +#define bM4_TMRA1_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A1194UL))) +#define bM4_TMRA1_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A1198UL))) +#define bM4_TMRA1_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A119CUL))) +#define bM4_TMRA1_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A11A0UL))) +#define bM4_TMRA1_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A11A4UL))) +#define bM4_TMRA1_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A11A8UL))) +#define bM4_TMRA1_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A11ACUL))) +#define bM4_TMRA1_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A11B0UL))) +#define bM4_TMRA1_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A1200UL))) +#define bM4_TMRA1_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A1204UL))) +#define bM4_TMRA1_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A1208UL))) +#define bM4_TMRA1_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A120CUL))) +#define bM4_TMRA1_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A1210UL))) +#define bM4_TMRA1_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A1214UL))) +#define bM4_TMRA1_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A1218UL))) +#define bM4_TMRA1_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A121CUL))) +#define bM4_TMRA1_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A1280UL))) +#define bM4_TMRA1_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A1284UL))) +#define bM4_TMRA1_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A1288UL))) +#define bM4_TMRA1_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A128CUL))) +#define bM4_TMRA1_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A1290UL))) +#define bM4_TMRA1_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A1294UL))) +#define bM4_TMRA1_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A1298UL))) +#define bM4_TMRA1_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A129CUL))) +#define bM4_TMRA1_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A1300UL))) +#define bM4_TMRA1_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A1304UL))) +#define bM4_TMRA1_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A1308UL))) +#define bM4_TMRA1_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A1320UL))) +#define bM4_TMRA1_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A1324UL))) +#define bM4_TMRA1_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A1328UL))) +#define bM4_TMRA1_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A1330UL))) +#define bM4_TMRA1_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A1334UL))) +#define bM4_TMRA1_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A1338UL))) +#define bM4_TMRA1_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A1380UL))) +#define bM4_TMRA1_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A1384UL))) +#define bM4_TMRA1_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A1388UL))) +#define bM4_TMRA1_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A138CUL))) +#define bM4_TMRA1_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A1390UL))) +#define bM4_TMRA1_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A1394UL))) +#define bM4_TMRA1_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A1398UL))) +#define bM4_TMRA1_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A139CUL))) +#define bM4_TMRA1_BCONR1_BEN (*((volatile unsigned int*)(0x422A1800UL))) +#define bM4_TMRA1_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A1804UL))) +#define bM4_TMRA1_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A1808UL))) +#define bM4_TMRA1_BCONR2_BEN (*((volatile unsigned int*)(0x422A1900UL))) +#define bM4_TMRA1_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A1904UL))) +#define bM4_TMRA1_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A1908UL))) +#define bM4_TMRA1_BCONR3_BEN (*((volatile unsigned int*)(0x422A1A00UL))) +#define bM4_TMRA1_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A1A04UL))) +#define bM4_TMRA1_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A1A08UL))) +#define bM4_TMRA1_BCONR4_BEN (*((volatile unsigned int*)(0x422A1B00UL))) +#define bM4_TMRA1_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A1B04UL))) +#define bM4_TMRA1_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A1B08UL))) +#define bM4_TMRA1_CCONR1_CAPMD (*((volatile unsigned int*)(0x422A2000UL))) +#define bM4_TMRA1_CCONR1_HICP0 (*((volatile unsigned int*)(0x422A2010UL))) +#define bM4_TMRA1_CCONR1_HICP1 (*((volatile unsigned int*)(0x422A2014UL))) +#define bM4_TMRA1_CCONR1_HICP2 (*((volatile unsigned int*)(0x422A2018UL))) +#define bM4_TMRA1_CCONR1_HICP3 (*((volatile unsigned int*)(0x422A2020UL))) +#define bM4_TMRA1_CCONR1_HICP4 (*((volatile unsigned int*)(0x422A2024UL))) +#define bM4_TMRA1_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422A2030UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422A2034UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422A2038UL))) +#define bM4_TMRA1_CCONR2_CAPMD (*((volatile unsigned int*)(0x422A2080UL))) +#define bM4_TMRA1_CCONR2_HICP0 (*((volatile unsigned int*)(0x422A2090UL))) +#define bM4_TMRA1_CCONR2_HICP1 (*((volatile unsigned int*)(0x422A2094UL))) +#define bM4_TMRA1_CCONR2_HICP2 (*((volatile unsigned int*)(0x422A2098UL))) +#define bM4_TMRA1_CCONR2_HICP3 (*((volatile unsigned int*)(0x422A20A0UL))) +#define bM4_TMRA1_CCONR2_HICP4 (*((volatile unsigned int*)(0x422A20A4UL))) +#define bM4_TMRA1_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422A20B0UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422A20B4UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422A20B8UL))) +#define bM4_TMRA1_CCONR3_CAPMD (*((volatile unsigned int*)(0x422A2100UL))) +#define bM4_TMRA1_CCONR3_HICP0 (*((volatile unsigned int*)(0x422A2110UL))) +#define bM4_TMRA1_CCONR3_HICP1 (*((volatile unsigned int*)(0x422A2114UL))) +#define bM4_TMRA1_CCONR3_HICP2 (*((volatile unsigned int*)(0x422A2118UL))) +#define bM4_TMRA1_CCONR3_HICP3 (*((volatile unsigned int*)(0x422A2120UL))) +#define bM4_TMRA1_CCONR3_HICP4 (*((volatile unsigned int*)(0x422A2124UL))) +#define bM4_TMRA1_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422A2130UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422A2134UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422A2138UL))) +#define bM4_TMRA1_CCONR4_CAPMD (*((volatile unsigned int*)(0x422A2180UL))) +#define bM4_TMRA1_CCONR4_HICP0 (*((volatile unsigned int*)(0x422A2190UL))) +#define bM4_TMRA1_CCONR4_HICP1 (*((volatile unsigned int*)(0x422A2194UL))) +#define bM4_TMRA1_CCONR4_HICP2 (*((volatile unsigned int*)(0x422A2198UL))) +#define bM4_TMRA1_CCONR4_HICP3 (*((volatile unsigned int*)(0x422A21A0UL))) +#define bM4_TMRA1_CCONR4_HICP4 (*((volatile unsigned int*)(0x422A21A4UL))) +#define bM4_TMRA1_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422A21B0UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422A21B4UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422A21B8UL))) +#define bM4_TMRA1_CCONR5_CAPMD (*((volatile unsigned int*)(0x422A2200UL))) +#define bM4_TMRA1_CCONR5_HICP0 (*((volatile unsigned int*)(0x422A2210UL))) +#define bM4_TMRA1_CCONR5_HICP1 (*((volatile unsigned int*)(0x422A2214UL))) +#define bM4_TMRA1_CCONR5_HICP2 (*((volatile unsigned int*)(0x422A2218UL))) +#define bM4_TMRA1_CCONR5_HICP3 (*((volatile unsigned int*)(0x422A2220UL))) +#define bM4_TMRA1_CCONR5_HICP4 (*((volatile unsigned int*)(0x422A2224UL))) +#define bM4_TMRA1_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422A2230UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422A2234UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422A2238UL))) +#define bM4_TMRA1_CCONR6_CAPMD (*((volatile unsigned int*)(0x422A2280UL))) +#define bM4_TMRA1_CCONR6_HICP0 (*((volatile unsigned int*)(0x422A2290UL))) +#define bM4_TMRA1_CCONR6_HICP1 (*((volatile unsigned int*)(0x422A2294UL))) +#define bM4_TMRA1_CCONR6_HICP2 (*((volatile unsigned int*)(0x422A2298UL))) +#define bM4_TMRA1_CCONR6_HICP3 (*((volatile unsigned int*)(0x422A22A0UL))) +#define bM4_TMRA1_CCONR6_HICP4 (*((volatile unsigned int*)(0x422A22A4UL))) +#define bM4_TMRA1_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422A22B0UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422A22B4UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422A22B8UL))) +#define bM4_TMRA1_CCONR7_CAPMD (*((volatile unsigned int*)(0x422A2300UL))) +#define bM4_TMRA1_CCONR7_HICP0 (*((volatile unsigned int*)(0x422A2310UL))) +#define bM4_TMRA1_CCONR7_HICP1 (*((volatile unsigned int*)(0x422A2314UL))) +#define bM4_TMRA1_CCONR7_HICP2 (*((volatile unsigned int*)(0x422A2318UL))) +#define bM4_TMRA1_CCONR7_HICP3 (*((volatile unsigned int*)(0x422A2320UL))) +#define bM4_TMRA1_CCONR7_HICP4 (*((volatile unsigned int*)(0x422A2324UL))) +#define bM4_TMRA1_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422A2330UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422A2334UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422A2338UL))) +#define bM4_TMRA1_CCONR8_CAPMD (*((volatile unsigned int*)(0x422A2380UL))) +#define bM4_TMRA1_CCONR8_HICP0 (*((volatile unsigned int*)(0x422A2390UL))) +#define bM4_TMRA1_CCONR8_HICP1 (*((volatile unsigned int*)(0x422A2394UL))) +#define bM4_TMRA1_CCONR8_HICP2 (*((volatile unsigned int*)(0x422A2398UL))) +#define bM4_TMRA1_CCONR8_HICP3 (*((volatile unsigned int*)(0x422A23A0UL))) +#define bM4_TMRA1_CCONR8_HICP4 (*((volatile unsigned int*)(0x422A23A4UL))) +#define bM4_TMRA1_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422A23B0UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422A23B4UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422A23B8UL))) +#define bM4_TMRA1_PCONR1_STAC0 (*((volatile unsigned int*)(0x422A2800UL))) +#define bM4_TMRA1_PCONR1_STAC1 (*((volatile unsigned int*)(0x422A2804UL))) +#define bM4_TMRA1_PCONR1_STPC0 (*((volatile unsigned int*)(0x422A2808UL))) +#define bM4_TMRA1_PCONR1_STPC1 (*((volatile unsigned int*)(0x422A280CUL))) +#define bM4_TMRA1_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422A2810UL))) +#define bM4_TMRA1_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422A2814UL))) +#define bM4_TMRA1_PCONR1_PERC0 (*((volatile unsigned int*)(0x422A2818UL))) +#define bM4_TMRA1_PCONR1_PERC1 (*((volatile unsigned int*)(0x422A281CUL))) +#define bM4_TMRA1_PCONR1_FORC0 (*((volatile unsigned int*)(0x422A2820UL))) +#define bM4_TMRA1_PCONR1_FORC1 (*((volatile unsigned int*)(0x422A2824UL))) +#define bM4_TMRA1_PCONR1_OUTEN (*((volatile unsigned int*)(0x422A2830UL))) +#define bM4_TMRA1_PCONR2_STAC0 (*((volatile unsigned int*)(0x422A2880UL))) +#define bM4_TMRA1_PCONR2_STAC1 (*((volatile unsigned int*)(0x422A2884UL))) +#define bM4_TMRA1_PCONR2_STPC0 (*((volatile unsigned int*)(0x422A2888UL))) +#define bM4_TMRA1_PCONR2_STPC1 (*((volatile unsigned int*)(0x422A288CUL))) +#define bM4_TMRA1_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422A2890UL))) +#define bM4_TMRA1_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422A2894UL))) +#define bM4_TMRA1_PCONR2_PERC0 (*((volatile unsigned int*)(0x422A2898UL))) +#define bM4_TMRA1_PCONR2_PERC1 (*((volatile unsigned int*)(0x422A289CUL))) +#define bM4_TMRA1_PCONR2_FORC0 (*((volatile unsigned int*)(0x422A28A0UL))) +#define bM4_TMRA1_PCONR2_FORC1 (*((volatile unsigned int*)(0x422A28A4UL))) +#define bM4_TMRA1_PCONR2_OUTEN (*((volatile unsigned int*)(0x422A28B0UL))) +#define bM4_TMRA1_PCONR3_STAC0 (*((volatile unsigned int*)(0x422A2900UL))) +#define bM4_TMRA1_PCONR3_STAC1 (*((volatile unsigned int*)(0x422A2904UL))) +#define bM4_TMRA1_PCONR3_STPC0 (*((volatile unsigned int*)(0x422A2908UL))) +#define bM4_TMRA1_PCONR3_STPC1 (*((volatile unsigned int*)(0x422A290CUL))) +#define bM4_TMRA1_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422A2910UL))) +#define bM4_TMRA1_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422A2914UL))) +#define bM4_TMRA1_PCONR3_PERC0 (*((volatile unsigned int*)(0x422A2918UL))) +#define bM4_TMRA1_PCONR3_PERC1 (*((volatile unsigned int*)(0x422A291CUL))) +#define bM4_TMRA1_PCONR3_FORC0 (*((volatile unsigned int*)(0x422A2920UL))) +#define bM4_TMRA1_PCONR3_FORC1 (*((volatile unsigned int*)(0x422A2924UL))) +#define bM4_TMRA1_PCONR3_OUTEN (*((volatile unsigned int*)(0x422A2930UL))) +#define bM4_TMRA1_PCONR4_STAC0 (*((volatile unsigned int*)(0x422A2980UL))) +#define bM4_TMRA1_PCONR4_STAC1 (*((volatile unsigned int*)(0x422A2984UL))) +#define bM4_TMRA1_PCONR4_STPC0 (*((volatile unsigned int*)(0x422A2988UL))) +#define bM4_TMRA1_PCONR4_STPC1 (*((volatile unsigned int*)(0x422A298CUL))) +#define bM4_TMRA1_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422A2990UL))) +#define bM4_TMRA1_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422A2994UL))) +#define bM4_TMRA1_PCONR4_PERC0 (*((volatile unsigned int*)(0x422A2998UL))) +#define bM4_TMRA1_PCONR4_PERC1 (*((volatile unsigned int*)(0x422A299CUL))) +#define bM4_TMRA1_PCONR4_FORC0 (*((volatile unsigned int*)(0x422A29A0UL))) +#define bM4_TMRA1_PCONR4_FORC1 (*((volatile unsigned int*)(0x422A29A4UL))) +#define bM4_TMRA1_PCONR4_OUTEN (*((volatile unsigned int*)(0x422A29B0UL))) +#define bM4_TMRA1_PCONR5_STAC0 (*((volatile unsigned int*)(0x422A2A00UL))) +#define bM4_TMRA1_PCONR5_STAC1 (*((volatile unsigned int*)(0x422A2A04UL))) +#define bM4_TMRA1_PCONR5_STPC0 (*((volatile unsigned int*)(0x422A2A08UL))) +#define bM4_TMRA1_PCONR5_STPC1 (*((volatile unsigned int*)(0x422A2A0CUL))) +#define bM4_TMRA1_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422A2A10UL))) +#define bM4_TMRA1_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422A2A14UL))) +#define bM4_TMRA1_PCONR5_PERC0 (*((volatile unsigned int*)(0x422A2A18UL))) +#define bM4_TMRA1_PCONR5_PERC1 (*((volatile unsigned int*)(0x422A2A1CUL))) +#define bM4_TMRA1_PCONR5_FORC0 (*((volatile unsigned int*)(0x422A2A20UL))) +#define bM4_TMRA1_PCONR5_FORC1 (*((volatile unsigned int*)(0x422A2A24UL))) +#define bM4_TMRA1_PCONR5_OUTEN (*((volatile unsigned int*)(0x422A2A30UL))) +#define bM4_TMRA1_PCONR6_STAC0 (*((volatile unsigned int*)(0x422A2A80UL))) +#define bM4_TMRA1_PCONR6_STAC1 (*((volatile unsigned int*)(0x422A2A84UL))) +#define bM4_TMRA1_PCONR6_STPC0 (*((volatile unsigned int*)(0x422A2A88UL))) +#define bM4_TMRA1_PCONR6_STPC1 (*((volatile unsigned int*)(0x422A2A8CUL))) +#define bM4_TMRA1_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422A2A90UL))) +#define bM4_TMRA1_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422A2A94UL))) +#define bM4_TMRA1_PCONR6_PERC0 (*((volatile unsigned int*)(0x422A2A98UL))) +#define bM4_TMRA1_PCONR6_PERC1 (*((volatile unsigned int*)(0x422A2A9CUL))) +#define bM4_TMRA1_PCONR6_FORC0 (*((volatile unsigned int*)(0x422A2AA0UL))) +#define bM4_TMRA1_PCONR6_FORC1 (*((volatile unsigned int*)(0x422A2AA4UL))) +#define bM4_TMRA1_PCONR6_OUTEN (*((volatile unsigned int*)(0x422A2AB0UL))) +#define bM4_TMRA1_PCONR7_STAC0 (*((volatile unsigned int*)(0x422A2B00UL))) +#define bM4_TMRA1_PCONR7_STAC1 (*((volatile unsigned int*)(0x422A2B04UL))) +#define bM4_TMRA1_PCONR7_STPC0 (*((volatile unsigned int*)(0x422A2B08UL))) +#define bM4_TMRA1_PCONR7_STPC1 (*((volatile unsigned int*)(0x422A2B0CUL))) +#define bM4_TMRA1_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422A2B10UL))) +#define bM4_TMRA1_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422A2B14UL))) +#define bM4_TMRA1_PCONR7_PERC0 (*((volatile unsigned int*)(0x422A2B18UL))) +#define bM4_TMRA1_PCONR7_PERC1 (*((volatile unsigned int*)(0x422A2B1CUL))) +#define bM4_TMRA1_PCONR7_FORC0 (*((volatile unsigned int*)(0x422A2B20UL))) +#define bM4_TMRA1_PCONR7_FORC1 (*((volatile unsigned int*)(0x422A2B24UL))) +#define bM4_TMRA1_PCONR7_OUTEN (*((volatile unsigned int*)(0x422A2B30UL))) +#define bM4_TMRA1_PCONR8_STAC0 (*((volatile unsigned int*)(0x422A2B80UL))) +#define bM4_TMRA1_PCONR8_STAC1 (*((volatile unsigned int*)(0x422A2B84UL))) +#define bM4_TMRA1_PCONR8_STPC0 (*((volatile unsigned int*)(0x422A2B88UL))) +#define bM4_TMRA1_PCONR8_STPC1 (*((volatile unsigned int*)(0x422A2B8CUL))) +#define bM4_TMRA1_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422A2B90UL))) +#define bM4_TMRA1_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422A2B94UL))) +#define bM4_TMRA1_PCONR8_PERC0 (*((volatile unsigned int*)(0x422A2B98UL))) +#define bM4_TMRA1_PCONR8_PERC1 (*((volatile unsigned int*)(0x422A2B9CUL))) +#define bM4_TMRA1_PCONR8_FORC0 (*((volatile unsigned int*)(0x422A2BA0UL))) +#define bM4_TMRA1_PCONR8_FORC1 (*((volatile unsigned int*)(0x422A2BA4UL))) +#define bM4_TMRA1_PCONR8_OUTEN (*((volatile unsigned int*)(0x422A2BB0UL))) +#define bM4_TMRA2_CNTER_CNT0 (*((volatile unsigned int*)(0x422A8000UL))) +#define bM4_TMRA2_CNTER_CNT1 (*((volatile unsigned int*)(0x422A8004UL))) +#define bM4_TMRA2_CNTER_CNT2 (*((volatile unsigned int*)(0x422A8008UL))) +#define bM4_TMRA2_CNTER_CNT3 (*((volatile unsigned int*)(0x422A800CUL))) +#define bM4_TMRA2_CNTER_CNT4 (*((volatile unsigned int*)(0x422A8010UL))) +#define bM4_TMRA2_CNTER_CNT5 (*((volatile unsigned int*)(0x422A8014UL))) +#define bM4_TMRA2_CNTER_CNT6 (*((volatile unsigned int*)(0x422A8018UL))) +#define bM4_TMRA2_CNTER_CNT7 (*((volatile unsigned int*)(0x422A801CUL))) +#define bM4_TMRA2_CNTER_CNT8 (*((volatile unsigned int*)(0x422A8020UL))) +#define bM4_TMRA2_CNTER_CNT9 (*((volatile unsigned int*)(0x422A8024UL))) +#define bM4_TMRA2_CNTER_CNT10 (*((volatile unsigned int*)(0x422A8028UL))) +#define bM4_TMRA2_CNTER_CNT11 (*((volatile unsigned int*)(0x422A802CUL))) +#define bM4_TMRA2_CNTER_CNT12 (*((volatile unsigned int*)(0x422A8030UL))) +#define bM4_TMRA2_CNTER_CNT13 (*((volatile unsigned int*)(0x422A8034UL))) +#define bM4_TMRA2_CNTER_CNT14 (*((volatile unsigned int*)(0x422A8038UL))) +#define bM4_TMRA2_CNTER_CNT15 (*((volatile unsigned int*)(0x422A803CUL))) +#define bM4_TMRA2_PERAR_PER0 (*((volatile unsigned int*)(0x422A8080UL))) +#define bM4_TMRA2_PERAR_PER1 (*((volatile unsigned int*)(0x422A8084UL))) +#define bM4_TMRA2_PERAR_PER2 (*((volatile unsigned int*)(0x422A8088UL))) +#define bM4_TMRA2_PERAR_PER3 (*((volatile unsigned int*)(0x422A808CUL))) +#define bM4_TMRA2_PERAR_PER4 (*((volatile unsigned int*)(0x422A8090UL))) +#define bM4_TMRA2_PERAR_PER5 (*((volatile unsigned int*)(0x422A8094UL))) +#define bM4_TMRA2_PERAR_PER6 (*((volatile unsigned int*)(0x422A8098UL))) +#define bM4_TMRA2_PERAR_PER7 (*((volatile unsigned int*)(0x422A809CUL))) +#define bM4_TMRA2_PERAR_PER8 (*((volatile unsigned int*)(0x422A80A0UL))) +#define bM4_TMRA2_PERAR_PER9 (*((volatile unsigned int*)(0x422A80A4UL))) +#define bM4_TMRA2_PERAR_PER10 (*((volatile unsigned int*)(0x422A80A8UL))) +#define bM4_TMRA2_PERAR_PER11 (*((volatile unsigned int*)(0x422A80ACUL))) +#define bM4_TMRA2_PERAR_PER12 (*((volatile unsigned int*)(0x422A80B0UL))) +#define bM4_TMRA2_PERAR_PER13 (*((volatile unsigned int*)(0x422A80B4UL))) +#define bM4_TMRA2_PERAR_PER14 (*((volatile unsigned int*)(0x422A80B8UL))) +#define bM4_TMRA2_PERAR_PER15 (*((volatile unsigned int*)(0x422A80BCUL))) +#define bM4_TMRA2_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A8800UL))) +#define bM4_TMRA2_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A8804UL))) +#define bM4_TMRA2_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A8808UL))) +#define bM4_TMRA2_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A880CUL))) +#define bM4_TMRA2_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A8810UL))) +#define bM4_TMRA2_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A8814UL))) +#define bM4_TMRA2_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A8818UL))) +#define bM4_TMRA2_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A881CUL))) +#define bM4_TMRA2_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A8820UL))) +#define bM4_TMRA2_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A8824UL))) +#define bM4_TMRA2_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A8828UL))) +#define bM4_TMRA2_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A882CUL))) +#define bM4_TMRA2_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A8830UL))) +#define bM4_TMRA2_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A8834UL))) +#define bM4_TMRA2_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A8838UL))) +#define bM4_TMRA2_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A883CUL))) +#define bM4_TMRA2_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A8880UL))) +#define bM4_TMRA2_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A8884UL))) +#define bM4_TMRA2_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A8888UL))) +#define bM4_TMRA2_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A888CUL))) +#define bM4_TMRA2_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A8890UL))) +#define bM4_TMRA2_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A8894UL))) +#define bM4_TMRA2_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A8898UL))) +#define bM4_TMRA2_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A889CUL))) +#define bM4_TMRA2_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A88A0UL))) +#define bM4_TMRA2_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A88A4UL))) +#define bM4_TMRA2_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A88A8UL))) +#define bM4_TMRA2_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A88ACUL))) +#define bM4_TMRA2_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A88B0UL))) +#define bM4_TMRA2_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A88B4UL))) +#define bM4_TMRA2_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A88B8UL))) +#define bM4_TMRA2_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A88BCUL))) +#define bM4_TMRA2_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A8900UL))) +#define bM4_TMRA2_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A8904UL))) +#define bM4_TMRA2_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A8908UL))) +#define bM4_TMRA2_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A890CUL))) +#define bM4_TMRA2_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A8910UL))) +#define bM4_TMRA2_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A8914UL))) +#define bM4_TMRA2_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A8918UL))) +#define bM4_TMRA2_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A891CUL))) +#define bM4_TMRA2_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A8920UL))) +#define bM4_TMRA2_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A8924UL))) +#define bM4_TMRA2_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A8928UL))) +#define bM4_TMRA2_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A892CUL))) +#define bM4_TMRA2_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A8930UL))) +#define bM4_TMRA2_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A8934UL))) +#define bM4_TMRA2_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A8938UL))) +#define bM4_TMRA2_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A893CUL))) +#define bM4_TMRA2_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A8980UL))) +#define bM4_TMRA2_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A8984UL))) +#define bM4_TMRA2_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A8988UL))) +#define bM4_TMRA2_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A898CUL))) +#define bM4_TMRA2_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A8990UL))) +#define bM4_TMRA2_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A8994UL))) +#define bM4_TMRA2_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A8998UL))) +#define bM4_TMRA2_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A899CUL))) +#define bM4_TMRA2_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A89A0UL))) +#define bM4_TMRA2_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A89A4UL))) +#define bM4_TMRA2_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A89A8UL))) +#define bM4_TMRA2_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A89ACUL))) +#define bM4_TMRA2_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A89B0UL))) +#define bM4_TMRA2_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A89B4UL))) +#define bM4_TMRA2_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A89B8UL))) +#define bM4_TMRA2_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A89BCUL))) +#define bM4_TMRA2_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A8A00UL))) +#define bM4_TMRA2_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A8A04UL))) +#define bM4_TMRA2_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A8A08UL))) +#define bM4_TMRA2_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A8A0CUL))) +#define bM4_TMRA2_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A8A10UL))) +#define bM4_TMRA2_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A8A14UL))) +#define bM4_TMRA2_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A8A18UL))) +#define bM4_TMRA2_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A8A1CUL))) +#define bM4_TMRA2_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A8A20UL))) +#define bM4_TMRA2_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A8A24UL))) +#define bM4_TMRA2_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A8A28UL))) +#define bM4_TMRA2_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A8A2CUL))) +#define bM4_TMRA2_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A8A30UL))) +#define bM4_TMRA2_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A8A34UL))) +#define bM4_TMRA2_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A8A38UL))) +#define bM4_TMRA2_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A8A3CUL))) +#define bM4_TMRA2_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A8A80UL))) +#define bM4_TMRA2_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A8A84UL))) +#define bM4_TMRA2_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A8A88UL))) +#define bM4_TMRA2_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A8A8CUL))) +#define bM4_TMRA2_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A8A90UL))) +#define bM4_TMRA2_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A8A94UL))) +#define bM4_TMRA2_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A8A98UL))) +#define bM4_TMRA2_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A8A9CUL))) +#define bM4_TMRA2_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A8AA0UL))) +#define bM4_TMRA2_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A8AA4UL))) +#define bM4_TMRA2_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A8AA8UL))) +#define bM4_TMRA2_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A8AACUL))) +#define bM4_TMRA2_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A8AB0UL))) +#define bM4_TMRA2_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A8AB4UL))) +#define bM4_TMRA2_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A8AB8UL))) +#define bM4_TMRA2_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A8ABCUL))) +#define bM4_TMRA2_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A8B00UL))) +#define bM4_TMRA2_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A8B04UL))) +#define bM4_TMRA2_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A8B08UL))) +#define bM4_TMRA2_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A8B0CUL))) +#define bM4_TMRA2_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A8B10UL))) +#define bM4_TMRA2_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A8B14UL))) +#define bM4_TMRA2_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A8B18UL))) +#define bM4_TMRA2_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A8B1CUL))) +#define bM4_TMRA2_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A8B20UL))) +#define bM4_TMRA2_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A8B24UL))) +#define bM4_TMRA2_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A8B28UL))) +#define bM4_TMRA2_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A8B2CUL))) +#define bM4_TMRA2_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A8B30UL))) +#define bM4_TMRA2_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A8B34UL))) +#define bM4_TMRA2_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A8B38UL))) +#define bM4_TMRA2_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A8B3CUL))) +#define bM4_TMRA2_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A8B80UL))) +#define bM4_TMRA2_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A8B84UL))) +#define bM4_TMRA2_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A8B88UL))) +#define bM4_TMRA2_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A8B8CUL))) +#define bM4_TMRA2_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A8B90UL))) +#define bM4_TMRA2_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A8B94UL))) +#define bM4_TMRA2_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A8B98UL))) +#define bM4_TMRA2_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A8B9CUL))) +#define bM4_TMRA2_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A8BA0UL))) +#define bM4_TMRA2_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A8BA4UL))) +#define bM4_TMRA2_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A8BA8UL))) +#define bM4_TMRA2_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A8BACUL))) +#define bM4_TMRA2_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A8BB0UL))) +#define bM4_TMRA2_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A8BB4UL))) +#define bM4_TMRA2_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A8BB8UL))) +#define bM4_TMRA2_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A8BBCUL))) +#define bM4_TMRA2_BCSTR_START (*((volatile unsigned int*)(0x422A9000UL))) +#define bM4_TMRA2_BCSTR_DIR (*((volatile unsigned int*)(0x422A9004UL))) +#define bM4_TMRA2_BCSTR_MODE (*((volatile unsigned int*)(0x422A9008UL))) +#define bM4_TMRA2_BCSTR_SYNST (*((volatile unsigned int*)(0x422A900CUL))) +#define bM4_TMRA2_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A9010UL))) +#define bM4_TMRA2_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A9014UL))) +#define bM4_TMRA2_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A9018UL))) +#define bM4_TMRA2_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A901CUL))) +#define bM4_TMRA2_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A9030UL))) +#define bM4_TMRA2_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A9034UL))) +#define bM4_TMRA2_BCSTR_OVFF (*((volatile unsigned int*)(0x422A9038UL))) +#define bM4_TMRA2_BCSTR_UDFF (*((volatile unsigned int*)(0x422A903CUL))) +#define bM4_TMRA2_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A9080UL))) +#define bM4_TMRA2_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A9084UL))) +#define bM4_TMRA2_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A9088UL))) +#define bM4_TMRA2_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A9090UL))) +#define bM4_TMRA2_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A9094UL))) +#define bM4_TMRA2_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A9098UL))) +#define bM4_TMRA2_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A90A0UL))) +#define bM4_TMRA2_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A90A4UL))) +#define bM4_TMRA2_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A90A8UL))) +#define bM4_TMRA2_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A90B0UL))) +#define bM4_TMRA2_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A90B4UL))) +#define bM4_TMRA2_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A90B8UL))) +#define bM4_TMRA2_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A90BCUL))) +#define bM4_TMRA2_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A9100UL))) +#define bM4_TMRA2_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A9104UL))) +#define bM4_TMRA2_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A9108UL))) +#define bM4_TMRA2_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A910CUL))) +#define bM4_TMRA2_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A9110UL))) +#define bM4_TMRA2_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A9114UL))) +#define bM4_TMRA2_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A9118UL))) +#define bM4_TMRA2_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A911CUL))) +#define bM4_TMRA2_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A9120UL))) +#define bM4_TMRA2_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A9124UL))) +#define bM4_TMRA2_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A9128UL))) +#define bM4_TMRA2_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A912CUL))) +#define bM4_TMRA2_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A9130UL))) +#define bM4_TMRA2_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A9180UL))) +#define bM4_TMRA2_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A9184UL))) +#define bM4_TMRA2_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A9188UL))) +#define bM4_TMRA2_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A918CUL))) +#define bM4_TMRA2_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A9190UL))) +#define bM4_TMRA2_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A9194UL))) +#define bM4_TMRA2_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A9198UL))) +#define bM4_TMRA2_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A919CUL))) +#define bM4_TMRA2_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A91A0UL))) +#define bM4_TMRA2_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A91A4UL))) +#define bM4_TMRA2_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A91A8UL))) +#define bM4_TMRA2_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A91ACUL))) +#define bM4_TMRA2_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A91B0UL))) +#define bM4_TMRA2_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A9200UL))) +#define bM4_TMRA2_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A9204UL))) +#define bM4_TMRA2_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A9208UL))) +#define bM4_TMRA2_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A920CUL))) +#define bM4_TMRA2_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A9210UL))) +#define bM4_TMRA2_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A9214UL))) +#define bM4_TMRA2_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A9218UL))) +#define bM4_TMRA2_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A921CUL))) +#define bM4_TMRA2_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A9280UL))) +#define bM4_TMRA2_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A9284UL))) +#define bM4_TMRA2_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A9288UL))) +#define bM4_TMRA2_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A928CUL))) +#define bM4_TMRA2_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A9290UL))) +#define bM4_TMRA2_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A9294UL))) +#define bM4_TMRA2_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A9298UL))) +#define bM4_TMRA2_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A929CUL))) +#define bM4_TMRA2_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A9300UL))) +#define bM4_TMRA2_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A9304UL))) +#define bM4_TMRA2_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A9308UL))) +#define bM4_TMRA2_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A9320UL))) +#define bM4_TMRA2_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A9324UL))) +#define bM4_TMRA2_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A9328UL))) +#define bM4_TMRA2_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A9330UL))) +#define bM4_TMRA2_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A9334UL))) +#define bM4_TMRA2_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A9338UL))) +#define bM4_TMRA2_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A9380UL))) +#define bM4_TMRA2_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A9384UL))) +#define bM4_TMRA2_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A9388UL))) +#define bM4_TMRA2_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A938CUL))) +#define bM4_TMRA2_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A9390UL))) +#define bM4_TMRA2_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A9394UL))) +#define bM4_TMRA2_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A9398UL))) +#define bM4_TMRA2_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A939CUL))) +#define bM4_TMRA2_BCONR1_BEN (*((volatile unsigned int*)(0x422A9800UL))) +#define bM4_TMRA2_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A9804UL))) +#define bM4_TMRA2_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A9808UL))) +#define bM4_TMRA2_BCONR2_BEN (*((volatile unsigned int*)(0x422A9900UL))) +#define bM4_TMRA2_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A9904UL))) +#define bM4_TMRA2_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A9908UL))) +#define bM4_TMRA2_BCONR3_BEN (*((volatile unsigned int*)(0x422A9A00UL))) +#define bM4_TMRA2_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A9A04UL))) +#define bM4_TMRA2_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A9A08UL))) +#define bM4_TMRA2_BCONR4_BEN (*((volatile unsigned int*)(0x422A9B00UL))) +#define bM4_TMRA2_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A9B04UL))) +#define bM4_TMRA2_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A9B08UL))) +#define bM4_TMRA2_CCONR1_CAPMD (*((volatile unsigned int*)(0x422AA000UL))) +#define bM4_TMRA2_CCONR1_HICP0 (*((volatile unsigned int*)(0x422AA010UL))) +#define bM4_TMRA2_CCONR1_HICP1 (*((volatile unsigned int*)(0x422AA014UL))) +#define bM4_TMRA2_CCONR1_HICP2 (*((volatile unsigned int*)(0x422AA018UL))) +#define bM4_TMRA2_CCONR1_HICP3 (*((volatile unsigned int*)(0x422AA020UL))) +#define bM4_TMRA2_CCONR1_HICP4 (*((volatile unsigned int*)(0x422AA024UL))) +#define bM4_TMRA2_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422AA030UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422AA034UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422AA038UL))) +#define bM4_TMRA2_CCONR2_CAPMD (*((volatile unsigned int*)(0x422AA080UL))) +#define bM4_TMRA2_CCONR2_HICP0 (*((volatile unsigned int*)(0x422AA090UL))) +#define bM4_TMRA2_CCONR2_HICP1 (*((volatile unsigned int*)(0x422AA094UL))) +#define bM4_TMRA2_CCONR2_HICP2 (*((volatile unsigned int*)(0x422AA098UL))) +#define bM4_TMRA2_CCONR2_HICP3 (*((volatile unsigned int*)(0x422AA0A0UL))) +#define bM4_TMRA2_CCONR2_HICP4 (*((volatile unsigned int*)(0x422AA0A4UL))) +#define bM4_TMRA2_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422AA0B0UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422AA0B4UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422AA0B8UL))) +#define bM4_TMRA2_CCONR3_CAPMD (*((volatile unsigned int*)(0x422AA100UL))) +#define bM4_TMRA2_CCONR3_HICP0 (*((volatile unsigned int*)(0x422AA110UL))) +#define bM4_TMRA2_CCONR3_HICP1 (*((volatile unsigned int*)(0x422AA114UL))) +#define bM4_TMRA2_CCONR3_HICP2 (*((volatile unsigned int*)(0x422AA118UL))) +#define bM4_TMRA2_CCONR3_HICP3 (*((volatile unsigned int*)(0x422AA120UL))) +#define bM4_TMRA2_CCONR3_HICP4 (*((volatile unsigned int*)(0x422AA124UL))) +#define bM4_TMRA2_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422AA130UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422AA134UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422AA138UL))) +#define bM4_TMRA2_CCONR4_CAPMD (*((volatile unsigned int*)(0x422AA180UL))) +#define bM4_TMRA2_CCONR4_HICP0 (*((volatile unsigned int*)(0x422AA190UL))) +#define bM4_TMRA2_CCONR4_HICP1 (*((volatile unsigned int*)(0x422AA194UL))) +#define bM4_TMRA2_CCONR4_HICP2 (*((volatile unsigned int*)(0x422AA198UL))) +#define bM4_TMRA2_CCONR4_HICP3 (*((volatile unsigned int*)(0x422AA1A0UL))) +#define bM4_TMRA2_CCONR4_HICP4 (*((volatile unsigned int*)(0x422AA1A4UL))) +#define bM4_TMRA2_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422AA1B0UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422AA1B4UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422AA1B8UL))) +#define bM4_TMRA2_CCONR5_CAPMD (*((volatile unsigned int*)(0x422AA200UL))) +#define bM4_TMRA2_CCONR5_HICP0 (*((volatile unsigned int*)(0x422AA210UL))) +#define bM4_TMRA2_CCONR5_HICP1 (*((volatile unsigned int*)(0x422AA214UL))) +#define bM4_TMRA2_CCONR5_HICP2 (*((volatile unsigned int*)(0x422AA218UL))) +#define bM4_TMRA2_CCONR5_HICP3 (*((volatile unsigned int*)(0x422AA220UL))) +#define bM4_TMRA2_CCONR5_HICP4 (*((volatile unsigned int*)(0x422AA224UL))) +#define bM4_TMRA2_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422AA230UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422AA234UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422AA238UL))) +#define bM4_TMRA2_CCONR6_CAPMD (*((volatile unsigned int*)(0x422AA280UL))) +#define bM4_TMRA2_CCONR6_HICP0 (*((volatile unsigned int*)(0x422AA290UL))) +#define bM4_TMRA2_CCONR6_HICP1 (*((volatile unsigned int*)(0x422AA294UL))) +#define bM4_TMRA2_CCONR6_HICP2 (*((volatile unsigned int*)(0x422AA298UL))) +#define bM4_TMRA2_CCONR6_HICP3 (*((volatile unsigned int*)(0x422AA2A0UL))) +#define bM4_TMRA2_CCONR6_HICP4 (*((volatile unsigned int*)(0x422AA2A4UL))) +#define bM4_TMRA2_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422AA2B0UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422AA2B4UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422AA2B8UL))) +#define bM4_TMRA2_CCONR7_CAPMD (*((volatile unsigned int*)(0x422AA300UL))) +#define bM4_TMRA2_CCONR7_HICP0 (*((volatile unsigned int*)(0x422AA310UL))) +#define bM4_TMRA2_CCONR7_HICP1 (*((volatile unsigned int*)(0x422AA314UL))) +#define bM4_TMRA2_CCONR7_HICP2 (*((volatile unsigned int*)(0x422AA318UL))) +#define bM4_TMRA2_CCONR7_HICP3 (*((volatile unsigned int*)(0x422AA320UL))) +#define bM4_TMRA2_CCONR7_HICP4 (*((volatile unsigned int*)(0x422AA324UL))) +#define bM4_TMRA2_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422AA330UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422AA334UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422AA338UL))) +#define bM4_TMRA2_CCONR8_CAPMD (*((volatile unsigned int*)(0x422AA380UL))) +#define bM4_TMRA2_CCONR8_HICP0 (*((volatile unsigned int*)(0x422AA390UL))) +#define bM4_TMRA2_CCONR8_HICP1 (*((volatile unsigned int*)(0x422AA394UL))) +#define bM4_TMRA2_CCONR8_HICP2 (*((volatile unsigned int*)(0x422AA398UL))) +#define bM4_TMRA2_CCONR8_HICP3 (*((volatile unsigned int*)(0x422AA3A0UL))) +#define bM4_TMRA2_CCONR8_HICP4 (*((volatile unsigned int*)(0x422AA3A4UL))) +#define bM4_TMRA2_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422AA3B0UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422AA3B4UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422AA3B8UL))) +#define bM4_TMRA2_PCONR1_STAC0 (*((volatile unsigned int*)(0x422AA800UL))) +#define bM4_TMRA2_PCONR1_STAC1 (*((volatile unsigned int*)(0x422AA804UL))) +#define bM4_TMRA2_PCONR1_STPC0 (*((volatile unsigned int*)(0x422AA808UL))) +#define bM4_TMRA2_PCONR1_STPC1 (*((volatile unsigned int*)(0x422AA80CUL))) +#define bM4_TMRA2_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422AA810UL))) +#define bM4_TMRA2_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422AA814UL))) +#define bM4_TMRA2_PCONR1_PERC0 (*((volatile unsigned int*)(0x422AA818UL))) +#define bM4_TMRA2_PCONR1_PERC1 (*((volatile unsigned int*)(0x422AA81CUL))) +#define bM4_TMRA2_PCONR1_FORC0 (*((volatile unsigned int*)(0x422AA820UL))) +#define bM4_TMRA2_PCONR1_FORC1 (*((volatile unsigned int*)(0x422AA824UL))) +#define bM4_TMRA2_PCONR1_OUTEN (*((volatile unsigned int*)(0x422AA830UL))) +#define bM4_TMRA2_PCONR2_STAC0 (*((volatile unsigned int*)(0x422AA880UL))) +#define bM4_TMRA2_PCONR2_STAC1 (*((volatile unsigned int*)(0x422AA884UL))) +#define bM4_TMRA2_PCONR2_STPC0 (*((volatile unsigned int*)(0x422AA888UL))) +#define bM4_TMRA2_PCONR2_STPC1 (*((volatile unsigned int*)(0x422AA88CUL))) +#define bM4_TMRA2_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422AA890UL))) +#define bM4_TMRA2_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422AA894UL))) +#define bM4_TMRA2_PCONR2_PERC0 (*((volatile unsigned int*)(0x422AA898UL))) +#define bM4_TMRA2_PCONR2_PERC1 (*((volatile unsigned int*)(0x422AA89CUL))) +#define bM4_TMRA2_PCONR2_FORC0 (*((volatile unsigned int*)(0x422AA8A0UL))) +#define bM4_TMRA2_PCONR2_FORC1 (*((volatile unsigned int*)(0x422AA8A4UL))) +#define bM4_TMRA2_PCONR2_OUTEN (*((volatile unsigned int*)(0x422AA8B0UL))) +#define bM4_TMRA2_PCONR3_STAC0 (*((volatile unsigned int*)(0x422AA900UL))) +#define bM4_TMRA2_PCONR3_STAC1 (*((volatile unsigned int*)(0x422AA904UL))) +#define bM4_TMRA2_PCONR3_STPC0 (*((volatile unsigned int*)(0x422AA908UL))) +#define bM4_TMRA2_PCONR3_STPC1 (*((volatile unsigned int*)(0x422AA90CUL))) +#define bM4_TMRA2_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422AA910UL))) +#define bM4_TMRA2_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422AA914UL))) +#define bM4_TMRA2_PCONR3_PERC0 (*((volatile unsigned int*)(0x422AA918UL))) +#define bM4_TMRA2_PCONR3_PERC1 (*((volatile unsigned int*)(0x422AA91CUL))) +#define bM4_TMRA2_PCONR3_FORC0 (*((volatile unsigned int*)(0x422AA920UL))) +#define bM4_TMRA2_PCONR3_FORC1 (*((volatile unsigned int*)(0x422AA924UL))) +#define bM4_TMRA2_PCONR3_OUTEN (*((volatile unsigned int*)(0x422AA930UL))) +#define bM4_TMRA2_PCONR4_STAC0 (*((volatile unsigned int*)(0x422AA980UL))) +#define bM4_TMRA2_PCONR4_STAC1 (*((volatile unsigned int*)(0x422AA984UL))) +#define bM4_TMRA2_PCONR4_STPC0 (*((volatile unsigned int*)(0x422AA988UL))) +#define bM4_TMRA2_PCONR4_STPC1 (*((volatile unsigned int*)(0x422AA98CUL))) +#define bM4_TMRA2_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422AA990UL))) +#define bM4_TMRA2_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422AA994UL))) +#define bM4_TMRA2_PCONR4_PERC0 (*((volatile unsigned int*)(0x422AA998UL))) +#define bM4_TMRA2_PCONR4_PERC1 (*((volatile unsigned int*)(0x422AA99CUL))) +#define bM4_TMRA2_PCONR4_FORC0 (*((volatile unsigned int*)(0x422AA9A0UL))) +#define bM4_TMRA2_PCONR4_FORC1 (*((volatile unsigned int*)(0x422AA9A4UL))) +#define bM4_TMRA2_PCONR4_OUTEN (*((volatile unsigned int*)(0x422AA9B0UL))) +#define bM4_TMRA2_PCONR5_STAC0 (*((volatile unsigned int*)(0x422AAA00UL))) +#define bM4_TMRA2_PCONR5_STAC1 (*((volatile unsigned int*)(0x422AAA04UL))) +#define bM4_TMRA2_PCONR5_STPC0 (*((volatile unsigned int*)(0x422AAA08UL))) +#define bM4_TMRA2_PCONR5_STPC1 (*((volatile unsigned int*)(0x422AAA0CUL))) +#define bM4_TMRA2_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422AAA10UL))) +#define bM4_TMRA2_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422AAA14UL))) +#define bM4_TMRA2_PCONR5_PERC0 (*((volatile unsigned int*)(0x422AAA18UL))) +#define bM4_TMRA2_PCONR5_PERC1 (*((volatile unsigned int*)(0x422AAA1CUL))) +#define bM4_TMRA2_PCONR5_FORC0 (*((volatile unsigned int*)(0x422AAA20UL))) +#define bM4_TMRA2_PCONR5_FORC1 (*((volatile unsigned int*)(0x422AAA24UL))) +#define bM4_TMRA2_PCONR5_OUTEN (*((volatile unsigned int*)(0x422AAA30UL))) +#define bM4_TMRA2_PCONR6_STAC0 (*((volatile unsigned int*)(0x422AAA80UL))) +#define bM4_TMRA2_PCONR6_STAC1 (*((volatile unsigned int*)(0x422AAA84UL))) +#define bM4_TMRA2_PCONR6_STPC0 (*((volatile unsigned int*)(0x422AAA88UL))) +#define bM4_TMRA2_PCONR6_STPC1 (*((volatile unsigned int*)(0x422AAA8CUL))) +#define bM4_TMRA2_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422AAA90UL))) +#define bM4_TMRA2_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422AAA94UL))) +#define bM4_TMRA2_PCONR6_PERC0 (*((volatile unsigned int*)(0x422AAA98UL))) +#define bM4_TMRA2_PCONR6_PERC1 (*((volatile unsigned int*)(0x422AAA9CUL))) +#define bM4_TMRA2_PCONR6_FORC0 (*((volatile unsigned int*)(0x422AAAA0UL))) +#define bM4_TMRA2_PCONR6_FORC1 (*((volatile unsigned int*)(0x422AAAA4UL))) +#define bM4_TMRA2_PCONR6_OUTEN (*((volatile unsigned int*)(0x422AAAB0UL))) +#define bM4_TMRA2_PCONR7_STAC0 (*((volatile unsigned int*)(0x422AAB00UL))) +#define bM4_TMRA2_PCONR7_STAC1 (*((volatile unsigned int*)(0x422AAB04UL))) +#define bM4_TMRA2_PCONR7_STPC0 (*((volatile unsigned int*)(0x422AAB08UL))) +#define bM4_TMRA2_PCONR7_STPC1 (*((volatile unsigned int*)(0x422AAB0CUL))) +#define bM4_TMRA2_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422AAB10UL))) +#define bM4_TMRA2_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422AAB14UL))) +#define bM4_TMRA2_PCONR7_PERC0 (*((volatile unsigned int*)(0x422AAB18UL))) +#define bM4_TMRA2_PCONR7_PERC1 (*((volatile unsigned int*)(0x422AAB1CUL))) +#define bM4_TMRA2_PCONR7_FORC0 (*((volatile unsigned int*)(0x422AAB20UL))) +#define bM4_TMRA2_PCONR7_FORC1 (*((volatile unsigned int*)(0x422AAB24UL))) +#define bM4_TMRA2_PCONR7_OUTEN (*((volatile unsigned int*)(0x422AAB30UL))) +#define bM4_TMRA2_PCONR8_STAC0 (*((volatile unsigned int*)(0x422AAB80UL))) +#define bM4_TMRA2_PCONR8_STAC1 (*((volatile unsigned int*)(0x422AAB84UL))) +#define bM4_TMRA2_PCONR8_STPC0 (*((volatile unsigned int*)(0x422AAB88UL))) +#define bM4_TMRA2_PCONR8_STPC1 (*((volatile unsigned int*)(0x422AAB8CUL))) +#define bM4_TMRA2_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422AAB90UL))) +#define bM4_TMRA2_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422AAB94UL))) +#define bM4_TMRA2_PCONR8_PERC0 (*((volatile unsigned int*)(0x422AAB98UL))) +#define bM4_TMRA2_PCONR8_PERC1 (*((volatile unsigned int*)(0x422AAB9CUL))) +#define bM4_TMRA2_PCONR8_FORC0 (*((volatile unsigned int*)(0x422AABA0UL))) +#define bM4_TMRA2_PCONR8_FORC1 (*((volatile unsigned int*)(0x422AABA4UL))) +#define bM4_TMRA2_PCONR8_OUTEN (*((volatile unsigned int*)(0x422AABB0UL))) +#define bM4_TMRA3_CNTER_CNT0 (*((volatile unsigned int*)(0x422B0000UL))) +#define bM4_TMRA3_CNTER_CNT1 (*((volatile unsigned int*)(0x422B0004UL))) +#define bM4_TMRA3_CNTER_CNT2 (*((volatile unsigned int*)(0x422B0008UL))) +#define bM4_TMRA3_CNTER_CNT3 (*((volatile unsigned int*)(0x422B000CUL))) +#define bM4_TMRA3_CNTER_CNT4 (*((volatile unsigned int*)(0x422B0010UL))) +#define bM4_TMRA3_CNTER_CNT5 (*((volatile unsigned int*)(0x422B0014UL))) +#define bM4_TMRA3_CNTER_CNT6 (*((volatile unsigned int*)(0x422B0018UL))) +#define bM4_TMRA3_CNTER_CNT7 (*((volatile unsigned int*)(0x422B001CUL))) +#define bM4_TMRA3_CNTER_CNT8 (*((volatile unsigned int*)(0x422B0020UL))) +#define bM4_TMRA3_CNTER_CNT9 (*((volatile unsigned int*)(0x422B0024UL))) +#define bM4_TMRA3_CNTER_CNT10 (*((volatile unsigned int*)(0x422B0028UL))) +#define bM4_TMRA3_CNTER_CNT11 (*((volatile unsigned int*)(0x422B002CUL))) +#define bM4_TMRA3_CNTER_CNT12 (*((volatile unsigned int*)(0x422B0030UL))) +#define bM4_TMRA3_CNTER_CNT13 (*((volatile unsigned int*)(0x422B0034UL))) +#define bM4_TMRA3_CNTER_CNT14 (*((volatile unsigned int*)(0x422B0038UL))) +#define bM4_TMRA3_CNTER_CNT15 (*((volatile unsigned int*)(0x422B003CUL))) +#define bM4_TMRA3_PERAR_PER0 (*((volatile unsigned int*)(0x422B0080UL))) +#define bM4_TMRA3_PERAR_PER1 (*((volatile unsigned int*)(0x422B0084UL))) +#define bM4_TMRA3_PERAR_PER2 (*((volatile unsigned int*)(0x422B0088UL))) +#define bM4_TMRA3_PERAR_PER3 (*((volatile unsigned int*)(0x422B008CUL))) +#define bM4_TMRA3_PERAR_PER4 (*((volatile unsigned int*)(0x422B0090UL))) +#define bM4_TMRA3_PERAR_PER5 (*((volatile unsigned int*)(0x422B0094UL))) +#define bM4_TMRA3_PERAR_PER6 (*((volatile unsigned int*)(0x422B0098UL))) +#define bM4_TMRA3_PERAR_PER7 (*((volatile unsigned int*)(0x422B009CUL))) +#define bM4_TMRA3_PERAR_PER8 (*((volatile unsigned int*)(0x422B00A0UL))) +#define bM4_TMRA3_PERAR_PER9 (*((volatile unsigned int*)(0x422B00A4UL))) +#define bM4_TMRA3_PERAR_PER10 (*((volatile unsigned int*)(0x422B00A8UL))) +#define bM4_TMRA3_PERAR_PER11 (*((volatile unsigned int*)(0x422B00ACUL))) +#define bM4_TMRA3_PERAR_PER12 (*((volatile unsigned int*)(0x422B00B0UL))) +#define bM4_TMRA3_PERAR_PER13 (*((volatile unsigned int*)(0x422B00B4UL))) +#define bM4_TMRA3_PERAR_PER14 (*((volatile unsigned int*)(0x422B00B8UL))) +#define bM4_TMRA3_PERAR_PER15 (*((volatile unsigned int*)(0x422B00BCUL))) +#define bM4_TMRA3_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B0800UL))) +#define bM4_TMRA3_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B0804UL))) +#define bM4_TMRA3_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B0808UL))) +#define bM4_TMRA3_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B080CUL))) +#define bM4_TMRA3_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B0810UL))) +#define bM4_TMRA3_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B0814UL))) +#define bM4_TMRA3_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B0818UL))) +#define bM4_TMRA3_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B081CUL))) +#define bM4_TMRA3_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B0820UL))) +#define bM4_TMRA3_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B0824UL))) +#define bM4_TMRA3_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B0828UL))) +#define bM4_TMRA3_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B082CUL))) +#define bM4_TMRA3_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B0830UL))) +#define bM4_TMRA3_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B0834UL))) +#define bM4_TMRA3_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B0838UL))) +#define bM4_TMRA3_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B083CUL))) +#define bM4_TMRA3_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B0880UL))) +#define bM4_TMRA3_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B0884UL))) +#define bM4_TMRA3_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B0888UL))) +#define bM4_TMRA3_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B088CUL))) +#define bM4_TMRA3_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B0890UL))) +#define bM4_TMRA3_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B0894UL))) +#define bM4_TMRA3_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B0898UL))) +#define bM4_TMRA3_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B089CUL))) +#define bM4_TMRA3_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B08A0UL))) +#define bM4_TMRA3_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B08A4UL))) +#define bM4_TMRA3_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B08A8UL))) +#define bM4_TMRA3_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B08ACUL))) +#define bM4_TMRA3_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B08B0UL))) +#define bM4_TMRA3_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B08B4UL))) +#define bM4_TMRA3_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B08B8UL))) +#define bM4_TMRA3_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B08BCUL))) +#define bM4_TMRA3_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B0900UL))) +#define bM4_TMRA3_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B0904UL))) +#define bM4_TMRA3_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B0908UL))) +#define bM4_TMRA3_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B090CUL))) +#define bM4_TMRA3_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B0910UL))) +#define bM4_TMRA3_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B0914UL))) +#define bM4_TMRA3_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B0918UL))) +#define bM4_TMRA3_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B091CUL))) +#define bM4_TMRA3_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B0920UL))) +#define bM4_TMRA3_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B0924UL))) +#define bM4_TMRA3_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B0928UL))) +#define bM4_TMRA3_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B092CUL))) +#define bM4_TMRA3_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B0930UL))) +#define bM4_TMRA3_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B0934UL))) +#define bM4_TMRA3_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B0938UL))) +#define bM4_TMRA3_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B093CUL))) +#define bM4_TMRA3_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B0980UL))) +#define bM4_TMRA3_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B0984UL))) +#define bM4_TMRA3_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B0988UL))) +#define bM4_TMRA3_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B098CUL))) +#define bM4_TMRA3_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B0990UL))) +#define bM4_TMRA3_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B0994UL))) +#define bM4_TMRA3_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B0998UL))) +#define bM4_TMRA3_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B099CUL))) +#define bM4_TMRA3_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B09A0UL))) +#define bM4_TMRA3_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B09A4UL))) +#define bM4_TMRA3_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B09A8UL))) +#define bM4_TMRA3_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B09ACUL))) +#define bM4_TMRA3_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B09B0UL))) +#define bM4_TMRA3_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B09B4UL))) +#define bM4_TMRA3_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B09B8UL))) +#define bM4_TMRA3_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B09BCUL))) +#define bM4_TMRA3_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B0A00UL))) +#define bM4_TMRA3_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B0A04UL))) +#define bM4_TMRA3_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B0A08UL))) +#define bM4_TMRA3_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B0A0CUL))) +#define bM4_TMRA3_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B0A10UL))) +#define bM4_TMRA3_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B0A14UL))) +#define bM4_TMRA3_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B0A18UL))) +#define bM4_TMRA3_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B0A1CUL))) +#define bM4_TMRA3_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B0A20UL))) +#define bM4_TMRA3_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B0A24UL))) +#define bM4_TMRA3_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B0A28UL))) +#define bM4_TMRA3_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B0A2CUL))) +#define bM4_TMRA3_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B0A30UL))) +#define bM4_TMRA3_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B0A34UL))) +#define bM4_TMRA3_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B0A38UL))) +#define bM4_TMRA3_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B0A3CUL))) +#define bM4_TMRA3_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B0A80UL))) +#define bM4_TMRA3_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B0A84UL))) +#define bM4_TMRA3_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B0A88UL))) +#define bM4_TMRA3_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B0A8CUL))) +#define bM4_TMRA3_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B0A90UL))) +#define bM4_TMRA3_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B0A94UL))) +#define bM4_TMRA3_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B0A98UL))) +#define bM4_TMRA3_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B0A9CUL))) +#define bM4_TMRA3_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B0AA0UL))) +#define bM4_TMRA3_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B0AA4UL))) +#define bM4_TMRA3_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B0AA8UL))) +#define bM4_TMRA3_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B0AACUL))) +#define bM4_TMRA3_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B0AB0UL))) +#define bM4_TMRA3_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B0AB4UL))) +#define bM4_TMRA3_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B0AB8UL))) +#define bM4_TMRA3_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B0ABCUL))) +#define bM4_TMRA3_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B0B00UL))) +#define bM4_TMRA3_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B0B04UL))) +#define bM4_TMRA3_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B0B08UL))) +#define bM4_TMRA3_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B0B0CUL))) +#define bM4_TMRA3_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B0B10UL))) +#define bM4_TMRA3_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B0B14UL))) +#define bM4_TMRA3_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B0B18UL))) +#define bM4_TMRA3_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B0B1CUL))) +#define bM4_TMRA3_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B0B20UL))) +#define bM4_TMRA3_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B0B24UL))) +#define bM4_TMRA3_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B0B28UL))) +#define bM4_TMRA3_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B0B2CUL))) +#define bM4_TMRA3_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B0B30UL))) +#define bM4_TMRA3_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B0B34UL))) +#define bM4_TMRA3_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B0B38UL))) +#define bM4_TMRA3_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B0B3CUL))) +#define bM4_TMRA3_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B0B80UL))) +#define bM4_TMRA3_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B0B84UL))) +#define bM4_TMRA3_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B0B88UL))) +#define bM4_TMRA3_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B0B8CUL))) +#define bM4_TMRA3_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B0B90UL))) +#define bM4_TMRA3_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B0B94UL))) +#define bM4_TMRA3_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B0B98UL))) +#define bM4_TMRA3_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B0B9CUL))) +#define bM4_TMRA3_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B0BA0UL))) +#define bM4_TMRA3_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B0BA4UL))) +#define bM4_TMRA3_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B0BA8UL))) +#define bM4_TMRA3_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B0BACUL))) +#define bM4_TMRA3_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B0BB0UL))) +#define bM4_TMRA3_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B0BB4UL))) +#define bM4_TMRA3_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B0BB8UL))) +#define bM4_TMRA3_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B0BBCUL))) +#define bM4_TMRA3_BCSTR_START (*((volatile unsigned int*)(0x422B1000UL))) +#define bM4_TMRA3_BCSTR_DIR (*((volatile unsigned int*)(0x422B1004UL))) +#define bM4_TMRA3_BCSTR_MODE (*((volatile unsigned int*)(0x422B1008UL))) +#define bM4_TMRA3_BCSTR_SYNST (*((volatile unsigned int*)(0x422B100CUL))) +#define bM4_TMRA3_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B1010UL))) +#define bM4_TMRA3_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B1014UL))) +#define bM4_TMRA3_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B1018UL))) +#define bM4_TMRA3_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B101CUL))) +#define bM4_TMRA3_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B1030UL))) +#define bM4_TMRA3_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B1034UL))) +#define bM4_TMRA3_BCSTR_OVFF (*((volatile unsigned int*)(0x422B1038UL))) +#define bM4_TMRA3_BCSTR_UDFF (*((volatile unsigned int*)(0x422B103CUL))) +#define bM4_TMRA3_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B1080UL))) +#define bM4_TMRA3_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B1084UL))) +#define bM4_TMRA3_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B1088UL))) +#define bM4_TMRA3_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B1090UL))) +#define bM4_TMRA3_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B1094UL))) +#define bM4_TMRA3_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B1098UL))) +#define bM4_TMRA3_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B10A0UL))) +#define bM4_TMRA3_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B10A4UL))) +#define bM4_TMRA3_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B10A8UL))) +#define bM4_TMRA3_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B10B0UL))) +#define bM4_TMRA3_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B10B4UL))) +#define bM4_TMRA3_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B10B8UL))) +#define bM4_TMRA3_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B10BCUL))) +#define bM4_TMRA3_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B1100UL))) +#define bM4_TMRA3_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B1104UL))) +#define bM4_TMRA3_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B1108UL))) +#define bM4_TMRA3_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B110CUL))) +#define bM4_TMRA3_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B1110UL))) +#define bM4_TMRA3_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B1114UL))) +#define bM4_TMRA3_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B1118UL))) +#define bM4_TMRA3_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B111CUL))) +#define bM4_TMRA3_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B1120UL))) +#define bM4_TMRA3_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B1124UL))) +#define bM4_TMRA3_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B1128UL))) +#define bM4_TMRA3_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B112CUL))) +#define bM4_TMRA3_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B1130UL))) +#define bM4_TMRA3_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B1180UL))) +#define bM4_TMRA3_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B1184UL))) +#define bM4_TMRA3_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B1188UL))) +#define bM4_TMRA3_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B118CUL))) +#define bM4_TMRA3_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B1190UL))) +#define bM4_TMRA3_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B1194UL))) +#define bM4_TMRA3_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B1198UL))) +#define bM4_TMRA3_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B119CUL))) +#define bM4_TMRA3_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B11A0UL))) +#define bM4_TMRA3_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B11A4UL))) +#define bM4_TMRA3_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B11A8UL))) +#define bM4_TMRA3_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B11ACUL))) +#define bM4_TMRA3_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B11B0UL))) +#define bM4_TMRA3_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B1200UL))) +#define bM4_TMRA3_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B1204UL))) +#define bM4_TMRA3_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B1208UL))) +#define bM4_TMRA3_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B120CUL))) +#define bM4_TMRA3_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B1210UL))) +#define bM4_TMRA3_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B1214UL))) +#define bM4_TMRA3_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B1218UL))) +#define bM4_TMRA3_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B121CUL))) +#define bM4_TMRA3_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B1280UL))) +#define bM4_TMRA3_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B1284UL))) +#define bM4_TMRA3_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B1288UL))) +#define bM4_TMRA3_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B128CUL))) +#define bM4_TMRA3_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B1290UL))) +#define bM4_TMRA3_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B1294UL))) +#define bM4_TMRA3_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B1298UL))) +#define bM4_TMRA3_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B129CUL))) +#define bM4_TMRA3_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B1300UL))) +#define bM4_TMRA3_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B1304UL))) +#define bM4_TMRA3_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B1308UL))) +#define bM4_TMRA3_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B1320UL))) +#define bM4_TMRA3_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B1324UL))) +#define bM4_TMRA3_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B1328UL))) +#define bM4_TMRA3_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B1330UL))) +#define bM4_TMRA3_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B1334UL))) +#define bM4_TMRA3_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B1338UL))) +#define bM4_TMRA3_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B1380UL))) +#define bM4_TMRA3_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B1384UL))) +#define bM4_TMRA3_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B1388UL))) +#define bM4_TMRA3_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B138CUL))) +#define bM4_TMRA3_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B1390UL))) +#define bM4_TMRA3_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B1394UL))) +#define bM4_TMRA3_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B1398UL))) +#define bM4_TMRA3_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B139CUL))) +#define bM4_TMRA3_BCONR1_BEN (*((volatile unsigned int*)(0x422B1800UL))) +#define bM4_TMRA3_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B1804UL))) +#define bM4_TMRA3_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B1808UL))) +#define bM4_TMRA3_BCONR2_BEN (*((volatile unsigned int*)(0x422B1900UL))) +#define bM4_TMRA3_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B1904UL))) +#define bM4_TMRA3_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B1908UL))) +#define bM4_TMRA3_BCONR3_BEN (*((volatile unsigned int*)(0x422B1A00UL))) +#define bM4_TMRA3_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B1A04UL))) +#define bM4_TMRA3_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B1A08UL))) +#define bM4_TMRA3_BCONR4_BEN (*((volatile unsigned int*)(0x422B1B00UL))) +#define bM4_TMRA3_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B1B04UL))) +#define bM4_TMRA3_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B1B08UL))) +#define bM4_TMRA3_CCONR1_CAPMD (*((volatile unsigned int*)(0x422B2000UL))) +#define bM4_TMRA3_CCONR1_HICP0 (*((volatile unsigned int*)(0x422B2010UL))) +#define bM4_TMRA3_CCONR1_HICP1 (*((volatile unsigned int*)(0x422B2014UL))) +#define bM4_TMRA3_CCONR1_HICP2 (*((volatile unsigned int*)(0x422B2018UL))) +#define bM4_TMRA3_CCONR1_HICP3 (*((volatile unsigned int*)(0x422B2020UL))) +#define bM4_TMRA3_CCONR1_HICP4 (*((volatile unsigned int*)(0x422B2024UL))) +#define bM4_TMRA3_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422B2030UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422B2034UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422B2038UL))) +#define bM4_TMRA3_CCONR2_CAPMD (*((volatile unsigned int*)(0x422B2080UL))) +#define bM4_TMRA3_CCONR2_HICP0 (*((volatile unsigned int*)(0x422B2090UL))) +#define bM4_TMRA3_CCONR2_HICP1 (*((volatile unsigned int*)(0x422B2094UL))) +#define bM4_TMRA3_CCONR2_HICP2 (*((volatile unsigned int*)(0x422B2098UL))) +#define bM4_TMRA3_CCONR2_HICP3 (*((volatile unsigned int*)(0x422B20A0UL))) +#define bM4_TMRA3_CCONR2_HICP4 (*((volatile unsigned int*)(0x422B20A4UL))) +#define bM4_TMRA3_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422B20B0UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422B20B4UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422B20B8UL))) +#define bM4_TMRA3_CCONR3_CAPMD (*((volatile unsigned int*)(0x422B2100UL))) +#define bM4_TMRA3_CCONR3_HICP0 (*((volatile unsigned int*)(0x422B2110UL))) +#define bM4_TMRA3_CCONR3_HICP1 (*((volatile unsigned int*)(0x422B2114UL))) +#define bM4_TMRA3_CCONR3_HICP2 (*((volatile unsigned int*)(0x422B2118UL))) +#define bM4_TMRA3_CCONR3_HICP3 (*((volatile unsigned int*)(0x422B2120UL))) +#define bM4_TMRA3_CCONR3_HICP4 (*((volatile unsigned int*)(0x422B2124UL))) +#define bM4_TMRA3_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422B2130UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422B2134UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422B2138UL))) +#define bM4_TMRA3_CCONR4_CAPMD (*((volatile unsigned int*)(0x422B2180UL))) +#define bM4_TMRA3_CCONR4_HICP0 (*((volatile unsigned int*)(0x422B2190UL))) +#define bM4_TMRA3_CCONR4_HICP1 (*((volatile unsigned int*)(0x422B2194UL))) +#define bM4_TMRA3_CCONR4_HICP2 (*((volatile unsigned int*)(0x422B2198UL))) +#define bM4_TMRA3_CCONR4_HICP3 (*((volatile unsigned int*)(0x422B21A0UL))) +#define bM4_TMRA3_CCONR4_HICP4 (*((volatile unsigned int*)(0x422B21A4UL))) +#define bM4_TMRA3_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422B21B0UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422B21B4UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422B21B8UL))) +#define bM4_TMRA3_CCONR5_CAPMD (*((volatile unsigned int*)(0x422B2200UL))) +#define bM4_TMRA3_CCONR5_HICP0 (*((volatile unsigned int*)(0x422B2210UL))) +#define bM4_TMRA3_CCONR5_HICP1 (*((volatile unsigned int*)(0x422B2214UL))) +#define bM4_TMRA3_CCONR5_HICP2 (*((volatile unsigned int*)(0x422B2218UL))) +#define bM4_TMRA3_CCONR5_HICP3 (*((volatile unsigned int*)(0x422B2220UL))) +#define bM4_TMRA3_CCONR5_HICP4 (*((volatile unsigned int*)(0x422B2224UL))) +#define bM4_TMRA3_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422B2230UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422B2234UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422B2238UL))) +#define bM4_TMRA3_CCONR6_CAPMD (*((volatile unsigned int*)(0x422B2280UL))) +#define bM4_TMRA3_CCONR6_HICP0 (*((volatile unsigned int*)(0x422B2290UL))) +#define bM4_TMRA3_CCONR6_HICP1 (*((volatile unsigned int*)(0x422B2294UL))) +#define bM4_TMRA3_CCONR6_HICP2 (*((volatile unsigned int*)(0x422B2298UL))) +#define bM4_TMRA3_CCONR6_HICP3 (*((volatile unsigned int*)(0x422B22A0UL))) +#define bM4_TMRA3_CCONR6_HICP4 (*((volatile unsigned int*)(0x422B22A4UL))) +#define bM4_TMRA3_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422B22B0UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422B22B4UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422B22B8UL))) +#define bM4_TMRA3_CCONR7_CAPMD (*((volatile unsigned int*)(0x422B2300UL))) +#define bM4_TMRA3_CCONR7_HICP0 (*((volatile unsigned int*)(0x422B2310UL))) +#define bM4_TMRA3_CCONR7_HICP1 (*((volatile unsigned int*)(0x422B2314UL))) +#define bM4_TMRA3_CCONR7_HICP2 (*((volatile unsigned int*)(0x422B2318UL))) +#define bM4_TMRA3_CCONR7_HICP3 (*((volatile unsigned int*)(0x422B2320UL))) +#define bM4_TMRA3_CCONR7_HICP4 (*((volatile unsigned int*)(0x422B2324UL))) +#define bM4_TMRA3_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422B2330UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422B2334UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422B2338UL))) +#define bM4_TMRA3_CCONR8_CAPMD (*((volatile unsigned int*)(0x422B2380UL))) +#define bM4_TMRA3_CCONR8_HICP0 (*((volatile unsigned int*)(0x422B2390UL))) +#define bM4_TMRA3_CCONR8_HICP1 (*((volatile unsigned int*)(0x422B2394UL))) +#define bM4_TMRA3_CCONR8_HICP2 (*((volatile unsigned int*)(0x422B2398UL))) +#define bM4_TMRA3_CCONR8_HICP3 (*((volatile unsigned int*)(0x422B23A0UL))) +#define bM4_TMRA3_CCONR8_HICP4 (*((volatile unsigned int*)(0x422B23A4UL))) +#define bM4_TMRA3_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422B23B0UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422B23B4UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422B23B8UL))) +#define bM4_TMRA3_PCONR1_STAC0 (*((volatile unsigned int*)(0x422B2800UL))) +#define bM4_TMRA3_PCONR1_STAC1 (*((volatile unsigned int*)(0x422B2804UL))) +#define bM4_TMRA3_PCONR1_STPC0 (*((volatile unsigned int*)(0x422B2808UL))) +#define bM4_TMRA3_PCONR1_STPC1 (*((volatile unsigned int*)(0x422B280CUL))) +#define bM4_TMRA3_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422B2810UL))) +#define bM4_TMRA3_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422B2814UL))) +#define bM4_TMRA3_PCONR1_PERC0 (*((volatile unsigned int*)(0x422B2818UL))) +#define bM4_TMRA3_PCONR1_PERC1 (*((volatile unsigned int*)(0x422B281CUL))) +#define bM4_TMRA3_PCONR1_FORC0 (*((volatile unsigned int*)(0x422B2820UL))) +#define bM4_TMRA3_PCONR1_FORC1 (*((volatile unsigned int*)(0x422B2824UL))) +#define bM4_TMRA3_PCONR1_OUTEN (*((volatile unsigned int*)(0x422B2830UL))) +#define bM4_TMRA3_PCONR2_STAC0 (*((volatile unsigned int*)(0x422B2880UL))) +#define bM4_TMRA3_PCONR2_STAC1 (*((volatile unsigned int*)(0x422B2884UL))) +#define bM4_TMRA3_PCONR2_STPC0 (*((volatile unsigned int*)(0x422B2888UL))) +#define bM4_TMRA3_PCONR2_STPC1 (*((volatile unsigned int*)(0x422B288CUL))) +#define bM4_TMRA3_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422B2890UL))) +#define bM4_TMRA3_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422B2894UL))) +#define bM4_TMRA3_PCONR2_PERC0 (*((volatile unsigned int*)(0x422B2898UL))) +#define bM4_TMRA3_PCONR2_PERC1 (*((volatile unsigned int*)(0x422B289CUL))) +#define bM4_TMRA3_PCONR2_FORC0 (*((volatile unsigned int*)(0x422B28A0UL))) +#define bM4_TMRA3_PCONR2_FORC1 (*((volatile unsigned int*)(0x422B28A4UL))) +#define bM4_TMRA3_PCONR2_OUTEN (*((volatile unsigned int*)(0x422B28B0UL))) +#define bM4_TMRA3_PCONR3_STAC0 (*((volatile unsigned int*)(0x422B2900UL))) +#define bM4_TMRA3_PCONR3_STAC1 (*((volatile unsigned int*)(0x422B2904UL))) +#define bM4_TMRA3_PCONR3_STPC0 (*((volatile unsigned int*)(0x422B2908UL))) +#define bM4_TMRA3_PCONR3_STPC1 (*((volatile unsigned int*)(0x422B290CUL))) +#define bM4_TMRA3_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422B2910UL))) +#define bM4_TMRA3_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422B2914UL))) +#define bM4_TMRA3_PCONR3_PERC0 (*((volatile unsigned int*)(0x422B2918UL))) +#define bM4_TMRA3_PCONR3_PERC1 (*((volatile unsigned int*)(0x422B291CUL))) +#define bM4_TMRA3_PCONR3_FORC0 (*((volatile unsigned int*)(0x422B2920UL))) +#define bM4_TMRA3_PCONR3_FORC1 (*((volatile unsigned int*)(0x422B2924UL))) +#define bM4_TMRA3_PCONR3_OUTEN (*((volatile unsigned int*)(0x422B2930UL))) +#define bM4_TMRA3_PCONR4_STAC0 (*((volatile unsigned int*)(0x422B2980UL))) +#define bM4_TMRA3_PCONR4_STAC1 (*((volatile unsigned int*)(0x422B2984UL))) +#define bM4_TMRA3_PCONR4_STPC0 (*((volatile unsigned int*)(0x422B2988UL))) +#define bM4_TMRA3_PCONR4_STPC1 (*((volatile unsigned int*)(0x422B298CUL))) +#define bM4_TMRA3_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422B2990UL))) +#define bM4_TMRA3_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422B2994UL))) +#define bM4_TMRA3_PCONR4_PERC0 (*((volatile unsigned int*)(0x422B2998UL))) +#define bM4_TMRA3_PCONR4_PERC1 (*((volatile unsigned int*)(0x422B299CUL))) +#define bM4_TMRA3_PCONR4_FORC0 (*((volatile unsigned int*)(0x422B29A0UL))) +#define bM4_TMRA3_PCONR4_FORC1 (*((volatile unsigned int*)(0x422B29A4UL))) +#define bM4_TMRA3_PCONR4_OUTEN (*((volatile unsigned int*)(0x422B29B0UL))) +#define bM4_TMRA3_PCONR5_STAC0 (*((volatile unsigned int*)(0x422B2A00UL))) +#define bM4_TMRA3_PCONR5_STAC1 (*((volatile unsigned int*)(0x422B2A04UL))) +#define bM4_TMRA3_PCONR5_STPC0 (*((volatile unsigned int*)(0x422B2A08UL))) +#define bM4_TMRA3_PCONR5_STPC1 (*((volatile unsigned int*)(0x422B2A0CUL))) +#define bM4_TMRA3_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422B2A10UL))) +#define bM4_TMRA3_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422B2A14UL))) +#define bM4_TMRA3_PCONR5_PERC0 (*((volatile unsigned int*)(0x422B2A18UL))) +#define bM4_TMRA3_PCONR5_PERC1 (*((volatile unsigned int*)(0x422B2A1CUL))) +#define bM4_TMRA3_PCONR5_FORC0 (*((volatile unsigned int*)(0x422B2A20UL))) +#define bM4_TMRA3_PCONR5_FORC1 (*((volatile unsigned int*)(0x422B2A24UL))) +#define bM4_TMRA3_PCONR5_OUTEN (*((volatile unsigned int*)(0x422B2A30UL))) +#define bM4_TMRA3_PCONR6_STAC0 (*((volatile unsigned int*)(0x422B2A80UL))) +#define bM4_TMRA3_PCONR6_STAC1 (*((volatile unsigned int*)(0x422B2A84UL))) +#define bM4_TMRA3_PCONR6_STPC0 (*((volatile unsigned int*)(0x422B2A88UL))) +#define bM4_TMRA3_PCONR6_STPC1 (*((volatile unsigned int*)(0x422B2A8CUL))) +#define bM4_TMRA3_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422B2A90UL))) +#define bM4_TMRA3_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422B2A94UL))) +#define bM4_TMRA3_PCONR6_PERC0 (*((volatile unsigned int*)(0x422B2A98UL))) +#define bM4_TMRA3_PCONR6_PERC1 (*((volatile unsigned int*)(0x422B2A9CUL))) +#define bM4_TMRA3_PCONR6_FORC0 (*((volatile unsigned int*)(0x422B2AA0UL))) +#define bM4_TMRA3_PCONR6_FORC1 (*((volatile unsigned int*)(0x422B2AA4UL))) +#define bM4_TMRA3_PCONR6_OUTEN (*((volatile unsigned int*)(0x422B2AB0UL))) +#define bM4_TMRA3_PCONR7_STAC0 (*((volatile unsigned int*)(0x422B2B00UL))) +#define bM4_TMRA3_PCONR7_STAC1 (*((volatile unsigned int*)(0x422B2B04UL))) +#define bM4_TMRA3_PCONR7_STPC0 (*((volatile unsigned int*)(0x422B2B08UL))) +#define bM4_TMRA3_PCONR7_STPC1 (*((volatile unsigned int*)(0x422B2B0CUL))) +#define bM4_TMRA3_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422B2B10UL))) +#define bM4_TMRA3_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422B2B14UL))) +#define bM4_TMRA3_PCONR7_PERC0 (*((volatile unsigned int*)(0x422B2B18UL))) +#define bM4_TMRA3_PCONR7_PERC1 (*((volatile unsigned int*)(0x422B2B1CUL))) +#define bM4_TMRA3_PCONR7_FORC0 (*((volatile unsigned int*)(0x422B2B20UL))) +#define bM4_TMRA3_PCONR7_FORC1 (*((volatile unsigned int*)(0x422B2B24UL))) +#define bM4_TMRA3_PCONR7_OUTEN (*((volatile unsigned int*)(0x422B2B30UL))) +#define bM4_TMRA3_PCONR8_STAC0 (*((volatile unsigned int*)(0x422B2B80UL))) +#define bM4_TMRA3_PCONR8_STAC1 (*((volatile unsigned int*)(0x422B2B84UL))) +#define bM4_TMRA3_PCONR8_STPC0 (*((volatile unsigned int*)(0x422B2B88UL))) +#define bM4_TMRA3_PCONR8_STPC1 (*((volatile unsigned int*)(0x422B2B8CUL))) +#define bM4_TMRA3_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422B2B90UL))) +#define bM4_TMRA3_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422B2B94UL))) +#define bM4_TMRA3_PCONR8_PERC0 (*((volatile unsigned int*)(0x422B2B98UL))) +#define bM4_TMRA3_PCONR8_PERC1 (*((volatile unsigned int*)(0x422B2B9CUL))) +#define bM4_TMRA3_PCONR8_FORC0 (*((volatile unsigned int*)(0x422B2BA0UL))) +#define bM4_TMRA3_PCONR8_FORC1 (*((volatile unsigned int*)(0x422B2BA4UL))) +#define bM4_TMRA3_PCONR8_OUTEN (*((volatile unsigned int*)(0x422B2BB0UL))) +#define bM4_TMRA4_CNTER_CNT0 (*((volatile unsigned int*)(0x422B8000UL))) +#define bM4_TMRA4_CNTER_CNT1 (*((volatile unsigned int*)(0x422B8004UL))) +#define bM4_TMRA4_CNTER_CNT2 (*((volatile unsigned int*)(0x422B8008UL))) +#define bM4_TMRA4_CNTER_CNT3 (*((volatile unsigned int*)(0x422B800CUL))) +#define bM4_TMRA4_CNTER_CNT4 (*((volatile unsigned int*)(0x422B8010UL))) +#define bM4_TMRA4_CNTER_CNT5 (*((volatile unsigned int*)(0x422B8014UL))) +#define bM4_TMRA4_CNTER_CNT6 (*((volatile unsigned int*)(0x422B8018UL))) +#define bM4_TMRA4_CNTER_CNT7 (*((volatile unsigned int*)(0x422B801CUL))) +#define bM4_TMRA4_CNTER_CNT8 (*((volatile unsigned int*)(0x422B8020UL))) +#define bM4_TMRA4_CNTER_CNT9 (*((volatile unsigned int*)(0x422B8024UL))) +#define bM4_TMRA4_CNTER_CNT10 (*((volatile unsigned int*)(0x422B8028UL))) +#define bM4_TMRA4_CNTER_CNT11 (*((volatile unsigned int*)(0x422B802CUL))) +#define bM4_TMRA4_CNTER_CNT12 (*((volatile unsigned int*)(0x422B8030UL))) +#define bM4_TMRA4_CNTER_CNT13 (*((volatile unsigned int*)(0x422B8034UL))) +#define bM4_TMRA4_CNTER_CNT14 (*((volatile unsigned int*)(0x422B8038UL))) +#define bM4_TMRA4_CNTER_CNT15 (*((volatile unsigned int*)(0x422B803CUL))) +#define bM4_TMRA4_PERAR_PER0 (*((volatile unsigned int*)(0x422B8080UL))) +#define bM4_TMRA4_PERAR_PER1 (*((volatile unsigned int*)(0x422B8084UL))) +#define bM4_TMRA4_PERAR_PER2 (*((volatile unsigned int*)(0x422B8088UL))) +#define bM4_TMRA4_PERAR_PER3 (*((volatile unsigned int*)(0x422B808CUL))) +#define bM4_TMRA4_PERAR_PER4 (*((volatile unsigned int*)(0x422B8090UL))) +#define bM4_TMRA4_PERAR_PER5 (*((volatile unsigned int*)(0x422B8094UL))) +#define bM4_TMRA4_PERAR_PER6 (*((volatile unsigned int*)(0x422B8098UL))) +#define bM4_TMRA4_PERAR_PER7 (*((volatile unsigned int*)(0x422B809CUL))) +#define bM4_TMRA4_PERAR_PER8 (*((volatile unsigned int*)(0x422B80A0UL))) +#define bM4_TMRA4_PERAR_PER9 (*((volatile unsigned int*)(0x422B80A4UL))) +#define bM4_TMRA4_PERAR_PER10 (*((volatile unsigned int*)(0x422B80A8UL))) +#define bM4_TMRA4_PERAR_PER11 (*((volatile unsigned int*)(0x422B80ACUL))) +#define bM4_TMRA4_PERAR_PER12 (*((volatile unsigned int*)(0x422B80B0UL))) +#define bM4_TMRA4_PERAR_PER13 (*((volatile unsigned int*)(0x422B80B4UL))) +#define bM4_TMRA4_PERAR_PER14 (*((volatile unsigned int*)(0x422B80B8UL))) +#define bM4_TMRA4_PERAR_PER15 (*((volatile unsigned int*)(0x422B80BCUL))) +#define bM4_TMRA4_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B8800UL))) +#define bM4_TMRA4_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B8804UL))) +#define bM4_TMRA4_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B8808UL))) +#define bM4_TMRA4_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B880CUL))) +#define bM4_TMRA4_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B8810UL))) +#define bM4_TMRA4_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B8814UL))) +#define bM4_TMRA4_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B8818UL))) +#define bM4_TMRA4_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B881CUL))) +#define bM4_TMRA4_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B8820UL))) +#define bM4_TMRA4_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B8824UL))) +#define bM4_TMRA4_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B8828UL))) +#define bM4_TMRA4_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B882CUL))) +#define bM4_TMRA4_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B8830UL))) +#define bM4_TMRA4_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B8834UL))) +#define bM4_TMRA4_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B8838UL))) +#define bM4_TMRA4_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B883CUL))) +#define bM4_TMRA4_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B8880UL))) +#define bM4_TMRA4_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B8884UL))) +#define bM4_TMRA4_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B8888UL))) +#define bM4_TMRA4_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B888CUL))) +#define bM4_TMRA4_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B8890UL))) +#define bM4_TMRA4_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B8894UL))) +#define bM4_TMRA4_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B8898UL))) +#define bM4_TMRA4_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B889CUL))) +#define bM4_TMRA4_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B88A0UL))) +#define bM4_TMRA4_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B88A4UL))) +#define bM4_TMRA4_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B88A8UL))) +#define bM4_TMRA4_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B88ACUL))) +#define bM4_TMRA4_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B88B0UL))) +#define bM4_TMRA4_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B88B4UL))) +#define bM4_TMRA4_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B88B8UL))) +#define bM4_TMRA4_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B88BCUL))) +#define bM4_TMRA4_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B8900UL))) +#define bM4_TMRA4_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B8904UL))) +#define bM4_TMRA4_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B8908UL))) +#define bM4_TMRA4_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B890CUL))) +#define bM4_TMRA4_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B8910UL))) +#define bM4_TMRA4_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B8914UL))) +#define bM4_TMRA4_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B8918UL))) +#define bM4_TMRA4_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B891CUL))) +#define bM4_TMRA4_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B8920UL))) +#define bM4_TMRA4_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B8924UL))) +#define bM4_TMRA4_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B8928UL))) +#define bM4_TMRA4_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B892CUL))) +#define bM4_TMRA4_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B8930UL))) +#define bM4_TMRA4_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B8934UL))) +#define bM4_TMRA4_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B8938UL))) +#define bM4_TMRA4_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B893CUL))) +#define bM4_TMRA4_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B8980UL))) +#define bM4_TMRA4_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B8984UL))) +#define bM4_TMRA4_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B8988UL))) +#define bM4_TMRA4_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B898CUL))) +#define bM4_TMRA4_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B8990UL))) +#define bM4_TMRA4_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B8994UL))) +#define bM4_TMRA4_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B8998UL))) +#define bM4_TMRA4_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B899CUL))) +#define bM4_TMRA4_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B89A0UL))) +#define bM4_TMRA4_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B89A4UL))) +#define bM4_TMRA4_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B89A8UL))) +#define bM4_TMRA4_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B89ACUL))) +#define bM4_TMRA4_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B89B0UL))) +#define bM4_TMRA4_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B89B4UL))) +#define bM4_TMRA4_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B89B8UL))) +#define bM4_TMRA4_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B89BCUL))) +#define bM4_TMRA4_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B8A00UL))) +#define bM4_TMRA4_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B8A04UL))) +#define bM4_TMRA4_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B8A08UL))) +#define bM4_TMRA4_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B8A0CUL))) +#define bM4_TMRA4_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B8A10UL))) +#define bM4_TMRA4_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B8A14UL))) +#define bM4_TMRA4_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B8A18UL))) +#define bM4_TMRA4_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B8A1CUL))) +#define bM4_TMRA4_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B8A20UL))) +#define bM4_TMRA4_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B8A24UL))) +#define bM4_TMRA4_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B8A28UL))) +#define bM4_TMRA4_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B8A2CUL))) +#define bM4_TMRA4_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B8A30UL))) +#define bM4_TMRA4_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B8A34UL))) +#define bM4_TMRA4_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B8A38UL))) +#define bM4_TMRA4_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B8A3CUL))) +#define bM4_TMRA4_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B8A80UL))) +#define bM4_TMRA4_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B8A84UL))) +#define bM4_TMRA4_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B8A88UL))) +#define bM4_TMRA4_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B8A8CUL))) +#define bM4_TMRA4_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B8A90UL))) +#define bM4_TMRA4_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B8A94UL))) +#define bM4_TMRA4_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B8A98UL))) +#define bM4_TMRA4_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B8A9CUL))) +#define bM4_TMRA4_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B8AA0UL))) +#define bM4_TMRA4_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B8AA4UL))) +#define bM4_TMRA4_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B8AA8UL))) +#define bM4_TMRA4_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B8AACUL))) +#define bM4_TMRA4_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B8AB0UL))) +#define bM4_TMRA4_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B8AB4UL))) +#define bM4_TMRA4_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B8AB8UL))) +#define bM4_TMRA4_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B8ABCUL))) +#define bM4_TMRA4_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B8B00UL))) +#define bM4_TMRA4_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B8B04UL))) +#define bM4_TMRA4_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B8B08UL))) +#define bM4_TMRA4_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B8B0CUL))) +#define bM4_TMRA4_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B8B10UL))) +#define bM4_TMRA4_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B8B14UL))) +#define bM4_TMRA4_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B8B18UL))) +#define bM4_TMRA4_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B8B1CUL))) +#define bM4_TMRA4_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B8B20UL))) +#define bM4_TMRA4_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B8B24UL))) +#define bM4_TMRA4_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B8B28UL))) +#define bM4_TMRA4_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B8B2CUL))) +#define bM4_TMRA4_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B8B30UL))) +#define bM4_TMRA4_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B8B34UL))) +#define bM4_TMRA4_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B8B38UL))) +#define bM4_TMRA4_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B8B3CUL))) +#define bM4_TMRA4_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B8B80UL))) +#define bM4_TMRA4_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B8B84UL))) +#define bM4_TMRA4_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B8B88UL))) +#define bM4_TMRA4_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B8B8CUL))) +#define bM4_TMRA4_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B8B90UL))) +#define bM4_TMRA4_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B8B94UL))) +#define bM4_TMRA4_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B8B98UL))) +#define bM4_TMRA4_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B8B9CUL))) +#define bM4_TMRA4_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B8BA0UL))) +#define bM4_TMRA4_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B8BA4UL))) +#define bM4_TMRA4_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B8BA8UL))) +#define bM4_TMRA4_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B8BACUL))) +#define bM4_TMRA4_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B8BB0UL))) +#define bM4_TMRA4_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B8BB4UL))) +#define bM4_TMRA4_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B8BB8UL))) +#define bM4_TMRA4_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B8BBCUL))) +#define bM4_TMRA4_BCSTR_START (*((volatile unsigned int*)(0x422B9000UL))) +#define bM4_TMRA4_BCSTR_DIR (*((volatile unsigned int*)(0x422B9004UL))) +#define bM4_TMRA4_BCSTR_MODE (*((volatile unsigned int*)(0x422B9008UL))) +#define bM4_TMRA4_BCSTR_SYNST (*((volatile unsigned int*)(0x422B900CUL))) +#define bM4_TMRA4_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B9010UL))) +#define bM4_TMRA4_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B9014UL))) +#define bM4_TMRA4_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B9018UL))) +#define bM4_TMRA4_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B901CUL))) +#define bM4_TMRA4_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B9030UL))) +#define bM4_TMRA4_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B9034UL))) +#define bM4_TMRA4_BCSTR_OVFF (*((volatile unsigned int*)(0x422B9038UL))) +#define bM4_TMRA4_BCSTR_UDFF (*((volatile unsigned int*)(0x422B903CUL))) +#define bM4_TMRA4_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B9080UL))) +#define bM4_TMRA4_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B9084UL))) +#define bM4_TMRA4_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B9088UL))) +#define bM4_TMRA4_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B9090UL))) +#define bM4_TMRA4_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B9094UL))) +#define bM4_TMRA4_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B9098UL))) +#define bM4_TMRA4_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B90A0UL))) +#define bM4_TMRA4_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B90A4UL))) +#define bM4_TMRA4_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B90A8UL))) +#define bM4_TMRA4_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B90B0UL))) +#define bM4_TMRA4_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B90B4UL))) +#define bM4_TMRA4_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B90B8UL))) +#define bM4_TMRA4_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B90BCUL))) +#define bM4_TMRA4_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B9100UL))) +#define bM4_TMRA4_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B9104UL))) +#define bM4_TMRA4_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B9108UL))) +#define bM4_TMRA4_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B910CUL))) +#define bM4_TMRA4_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B9110UL))) +#define bM4_TMRA4_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B9114UL))) +#define bM4_TMRA4_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B9118UL))) +#define bM4_TMRA4_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B911CUL))) +#define bM4_TMRA4_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B9120UL))) +#define bM4_TMRA4_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B9124UL))) +#define bM4_TMRA4_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B9128UL))) +#define bM4_TMRA4_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B912CUL))) +#define bM4_TMRA4_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B9130UL))) +#define bM4_TMRA4_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B9180UL))) +#define bM4_TMRA4_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B9184UL))) +#define bM4_TMRA4_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B9188UL))) +#define bM4_TMRA4_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B918CUL))) +#define bM4_TMRA4_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B9190UL))) +#define bM4_TMRA4_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B9194UL))) +#define bM4_TMRA4_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B9198UL))) +#define bM4_TMRA4_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B919CUL))) +#define bM4_TMRA4_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B91A0UL))) +#define bM4_TMRA4_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B91A4UL))) +#define bM4_TMRA4_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B91A8UL))) +#define bM4_TMRA4_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B91ACUL))) +#define bM4_TMRA4_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B91B0UL))) +#define bM4_TMRA4_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B9200UL))) +#define bM4_TMRA4_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B9204UL))) +#define bM4_TMRA4_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B9208UL))) +#define bM4_TMRA4_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B920CUL))) +#define bM4_TMRA4_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B9210UL))) +#define bM4_TMRA4_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B9214UL))) +#define bM4_TMRA4_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B9218UL))) +#define bM4_TMRA4_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B921CUL))) +#define bM4_TMRA4_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B9280UL))) +#define bM4_TMRA4_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B9284UL))) +#define bM4_TMRA4_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B9288UL))) +#define bM4_TMRA4_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B928CUL))) +#define bM4_TMRA4_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B9290UL))) +#define bM4_TMRA4_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B9294UL))) +#define bM4_TMRA4_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B9298UL))) +#define bM4_TMRA4_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B929CUL))) +#define bM4_TMRA4_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B9300UL))) +#define bM4_TMRA4_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B9304UL))) +#define bM4_TMRA4_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B9308UL))) +#define bM4_TMRA4_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B9320UL))) +#define bM4_TMRA4_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B9324UL))) +#define bM4_TMRA4_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B9328UL))) +#define bM4_TMRA4_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B9330UL))) +#define bM4_TMRA4_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B9334UL))) +#define bM4_TMRA4_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B9338UL))) +#define bM4_TMRA4_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B9380UL))) +#define bM4_TMRA4_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B9384UL))) +#define bM4_TMRA4_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B9388UL))) +#define bM4_TMRA4_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B938CUL))) +#define bM4_TMRA4_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B9390UL))) +#define bM4_TMRA4_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B9394UL))) +#define bM4_TMRA4_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B9398UL))) +#define bM4_TMRA4_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B939CUL))) +#define bM4_TMRA4_BCONR1_BEN (*((volatile unsigned int*)(0x422B9800UL))) +#define bM4_TMRA4_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B9804UL))) +#define bM4_TMRA4_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B9808UL))) +#define bM4_TMRA4_BCONR2_BEN (*((volatile unsigned int*)(0x422B9900UL))) +#define bM4_TMRA4_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B9904UL))) +#define bM4_TMRA4_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B9908UL))) +#define bM4_TMRA4_BCONR3_BEN (*((volatile unsigned int*)(0x422B9A00UL))) +#define bM4_TMRA4_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B9A04UL))) +#define bM4_TMRA4_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B9A08UL))) +#define bM4_TMRA4_BCONR4_BEN (*((volatile unsigned int*)(0x422B9B00UL))) +#define bM4_TMRA4_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B9B04UL))) +#define bM4_TMRA4_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B9B08UL))) +#define bM4_TMRA4_CCONR1_CAPMD (*((volatile unsigned int*)(0x422BA000UL))) +#define bM4_TMRA4_CCONR1_HICP0 (*((volatile unsigned int*)(0x422BA010UL))) +#define bM4_TMRA4_CCONR1_HICP1 (*((volatile unsigned int*)(0x422BA014UL))) +#define bM4_TMRA4_CCONR1_HICP2 (*((volatile unsigned int*)(0x422BA018UL))) +#define bM4_TMRA4_CCONR1_HICP3 (*((volatile unsigned int*)(0x422BA020UL))) +#define bM4_TMRA4_CCONR1_HICP4 (*((volatile unsigned int*)(0x422BA024UL))) +#define bM4_TMRA4_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422BA030UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422BA034UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422BA038UL))) +#define bM4_TMRA4_CCONR2_CAPMD (*((volatile unsigned int*)(0x422BA080UL))) +#define bM4_TMRA4_CCONR2_HICP0 (*((volatile unsigned int*)(0x422BA090UL))) +#define bM4_TMRA4_CCONR2_HICP1 (*((volatile unsigned int*)(0x422BA094UL))) +#define bM4_TMRA4_CCONR2_HICP2 (*((volatile unsigned int*)(0x422BA098UL))) +#define bM4_TMRA4_CCONR2_HICP3 (*((volatile unsigned int*)(0x422BA0A0UL))) +#define bM4_TMRA4_CCONR2_HICP4 (*((volatile unsigned int*)(0x422BA0A4UL))) +#define bM4_TMRA4_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422BA0B0UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422BA0B4UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422BA0B8UL))) +#define bM4_TMRA4_CCONR3_CAPMD (*((volatile unsigned int*)(0x422BA100UL))) +#define bM4_TMRA4_CCONR3_HICP0 (*((volatile unsigned int*)(0x422BA110UL))) +#define bM4_TMRA4_CCONR3_HICP1 (*((volatile unsigned int*)(0x422BA114UL))) +#define bM4_TMRA4_CCONR3_HICP2 (*((volatile unsigned int*)(0x422BA118UL))) +#define bM4_TMRA4_CCONR3_HICP3 (*((volatile unsigned int*)(0x422BA120UL))) +#define bM4_TMRA4_CCONR3_HICP4 (*((volatile unsigned int*)(0x422BA124UL))) +#define bM4_TMRA4_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422BA130UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422BA134UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422BA138UL))) +#define bM4_TMRA4_CCONR4_CAPMD (*((volatile unsigned int*)(0x422BA180UL))) +#define bM4_TMRA4_CCONR4_HICP0 (*((volatile unsigned int*)(0x422BA190UL))) +#define bM4_TMRA4_CCONR4_HICP1 (*((volatile unsigned int*)(0x422BA194UL))) +#define bM4_TMRA4_CCONR4_HICP2 (*((volatile unsigned int*)(0x422BA198UL))) +#define bM4_TMRA4_CCONR4_HICP3 (*((volatile unsigned int*)(0x422BA1A0UL))) +#define bM4_TMRA4_CCONR4_HICP4 (*((volatile unsigned int*)(0x422BA1A4UL))) +#define bM4_TMRA4_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422BA1B0UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422BA1B4UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422BA1B8UL))) +#define bM4_TMRA4_CCONR5_CAPMD (*((volatile unsigned int*)(0x422BA200UL))) +#define bM4_TMRA4_CCONR5_HICP0 (*((volatile unsigned int*)(0x422BA210UL))) +#define bM4_TMRA4_CCONR5_HICP1 (*((volatile unsigned int*)(0x422BA214UL))) +#define bM4_TMRA4_CCONR5_HICP2 (*((volatile unsigned int*)(0x422BA218UL))) +#define bM4_TMRA4_CCONR5_HICP3 (*((volatile unsigned int*)(0x422BA220UL))) +#define bM4_TMRA4_CCONR5_HICP4 (*((volatile unsigned int*)(0x422BA224UL))) +#define bM4_TMRA4_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422BA230UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422BA234UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422BA238UL))) +#define bM4_TMRA4_CCONR6_CAPMD (*((volatile unsigned int*)(0x422BA280UL))) +#define bM4_TMRA4_CCONR6_HICP0 (*((volatile unsigned int*)(0x422BA290UL))) +#define bM4_TMRA4_CCONR6_HICP1 (*((volatile unsigned int*)(0x422BA294UL))) +#define bM4_TMRA4_CCONR6_HICP2 (*((volatile unsigned int*)(0x422BA298UL))) +#define bM4_TMRA4_CCONR6_HICP3 (*((volatile unsigned int*)(0x422BA2A0UL))) +#define bM4_TMRA4_CCONR6_HICP4 (*((volatile unsigned int*)(0x422BA2A4UL))) +#define bM4_TMRA4_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422BA2B0UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422BA2B4UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422BA2B8UL))) +#define bM4_TMRA4_CCONR7_CAPMD (*((volatile unsigned int*)(0x422BA300UL))) +#define bM4_TMRA4_CCONR7_HICP0 (*((volatile unsigned int*)(0x422BA310UL))) +#define bM4_TMRA4_CCONR7_HICP1 (*((volatile unsigned int*)(0x422BA314UL))) +#define bM4_TMRA4_CCONR7_HICP2 (*((volatile unsigned int*)(0x422BA318UL))) +#define bM4_TMRA4_CCONR7_HICP3 (*((volatile unsigned int*)(0x422BA320UL))) +#define bM4_TMRA4_CCONR7_HICP4 (*((volatile unsigned int*)(0x422BA324UL))) +#define bM4_TMRA4_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422BA330UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422BA334UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422BA338UL))) +#define bM4_TMRA4_CCONR8_CAPMD (*((volatile unsigned int*)(0x422BA380UL))) +#define bM4_TMRA4_CCONR8_HICP0 (*((volatile unsigned int*)(0x422BA390UL))) +#define bM4_TMRA4_CCONR8_HICP1 (*((volatile unsigned int*)(0x422BA394UL))) +#define bM4_TMRA4_CCONR8_HICP2 (*((volatile unsigned int*)(0x422BA398UL))) +#define bM4_TMRA4_CCONR8_HICP3 (*((volatile unsigned int*)(0x422BA3A0UL))) +#define bM4_TMRA4_CCONR8_HICP4 (*((volatile unsigned int*)(0x422BA3A4UL))) +#define bM4_TMRA4_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422BA3B0UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422BA3B4UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422BA3B8UL))) +#define bM4_TMRA4_PCONR1_STAC0 (*((volatile unsigned int*)(0x422BA800UL))) +#define bM4_TMRA4_PCONR1_STAC1 (*((volatile unsigned int*)(0x422BA804UL))) +#define bM4_TMRA4_PCONR1_STPC0 (*((volatile unsigned int*)(0x422BA808UL))) +#define bM4_TMRA4_PCONR1_STPC1 (*((volatile unsigned int*)(0x422BA80CUL))) +#define bM4_TMRA4_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422BA810UL))) +#define bM4_TMRA4_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422BA814UL))) +#define bM4_TMRA4_PCONR1_PERC0 (*((volatile unsigned int*)(0x422BA818UL))) +#define bM4_TMRA4_PCONR1_PERC1 (*((volatile unsigned int*)(0x422BA81CUL))) +#define bM4_TMRA4_PCONR1_FORC0 (*((volatile unsigned int*)(0x422BA820UL))) +#define bM4_TMRA4_PCONR1_FORC1 (*((volatile unsigned int*)(0x422BA824UL))) +#define bM4_TMRA4_PCONR1_OUTEN (*((volatile unsigned int*)(0x422BA830UL))) +#define bM4_TMRA4_PCONR2_STAC0 (*((volatile unsigned int*)(0x422BA880UL))) +#define bM4_TMRA4_PCONR2_STAC1 (*((volatile unsigned int*)(0x422BA884UL))) +#define bM4_TMRA4_PCONR2_STPC0 (*((volatile unsigned int*)(0x422BA888UL))) +#define bM4_TMRA4_PCONR2_STPC1 (*((volatile unsigned int*)(0x422BA88CUL))) +#define bM4_TMRA4_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422BA890UL))) +#define bM4_TMRA4_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422BA894UL))) +#define bM4_TMRA4_PCONR2_PERC0 (*((volatile unsigned int*)(0x422BA898UL))) +#define bM4_TMRA4_PCONR2_PERC1 (*((volatile unsigned int*)(0x422BA89CUL))) +#define bM4_TMRA4_PCONR2_FORC0 (*((volatile unsigned int*)(0x422BA8A0UL))) +#define bM4_TMRA4_PCONR2_FORC1 (*((volatile unsigned int*)(0x422BA8A4UL))) +#define bM4_TMRA4_PCONR2_OUTEN (*((volatile unsigned int*)(0x422BA8B0UL))) +#define bM4_TMRA4_PCONR3_STAC0 (*((volatile unsigned int*)(0x422BA900UL))) +#define bM4_TMRA4_PCONR3_STAC1 (*((volatile unsigned int*)(0x422BA904UL))) +#define bM4_TMRA4_PCONR3_STPC0 (*((volatile unsigned int*)(0x422BA908UL))) +#define bM4_TMRA4_PCONR3_STPC1 (*((volatile unsigned int*)(0x422BA90CUL))) +#define bM4_TMRA4_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422BA910UL))) +#define bM4_TMRA4_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422BA914UL))) +#define bM4_TMRA4_PCONR3_PERC0 (*((volatile unsigned int*)(0x422BA918UL))) +#define bM4_TMRA4_PCONR3_PERC1 (*((volatile unsigned int*)(0x422BA91CUL))) +#define bM4_TMRA4_PCONR3_FORC0 (*((volatile unsigned int*)(0x422BA920UL))) +#define bM4_TMRA4_PCONR3_FORC1 (*((volatile unsigned int*)(0x422BA924UL))) +#define bM4_TMRA4_PCONR3_OUTEN (*((volatile unsigned int*)(0x422BA930UL))) +#define bM4_TMRA4_PCONR4_STAC0 (*((volatile unsigned int*)(0x422BA980UL))) +#define bM4_TMRA4_PCONR4_STAC1 (*((volatile unsigned int*)(0x422BA984UL))) +#define bM4_TMRA4_PCONR4_STPC0 (*((volatile unsigned int*)(0x422BA988UL))) +#define bM4_TMRA4_PCONR4_STPC1 (*((volatile unsigned int*)(0x422BA98CUL))) +#define bM4_TMRA4_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422BA990UL))) +#define bM4_TMRA4_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422BA994UL))) +#define bM4_TMRA4_PCONR4_PERC0 (*((volatile unsigned int*)(0x422BA998UL))) +#define bM4_TMRA4_PCONR4_PERC1 (*((volatile unsigned int*)(0x422BA99CUL))) +#define bM4_TMRA4_PCONR4_FORC0 (*((volatile unsigned int*)(0x422BA9A0UL))) +#define bM4_TMRA4_PCONR4_FORC1 (*((volatile unsigned int*)(0x422BA9A4UL))) +#define bM4_TMRA4_PCONR4_OUTEN (*((volatile unsigned int*)(0x422BA9B0UL))) +#define bM4_TMRA4_PCONR5_STAC0 (*((volatile unsigned int*)(0x422BAA00UL))) +#define bM4_TMRA4_PCONR5_STAC1 (*((volatile unsigned int*)(0x422BAA04UL))) +#define bM4_TMRA4_PCONR5_STPC0 (*((volatile unsigned int*)(0x422BAA08UL))) +#define bM4_TMRA4_PCONR5_STPC1 (*((volatile unsigned int*)(0x422BAA0CUL))) +#define bM4_TMRA4_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422BAA10UL))) +#define bM4_TMRA4_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422BAA14UL))) +#define bM4_TMRA4_PCONR5_PERC0 (*((volatile unsigned int*)(0x422BAA18UL))) +#define bM4_TMRA4_PCONR5_PERC1 (*((volatile unsigned int*)(0x422BAA1CUL))) +#define bM4_TMRA4_PCONR5_FORC0 (*((volatile unsigned int*)(0x422BAA20UL))) +#define bM4_TMRA4_PCONR5_FORC1 (*((volatile unsigned int*)(0x422BAA24UL))) +#define bM4_TMRA4_PCONR5_OUTEN (*((volatile unsigned int*)(0x422BAA30UL))) +#define bM4_TMRA4_PCONR6_STAC0 (*((volatile unsigned int*)(0x422BAA80UL))) +#define bM4_TMRA4_PCONR6_STAC1 (*((volatile unsigned int*)(0x422BAA84UL))) +#define bM4_TMRA4_PCONR6_STPC0 (*((volatile unsigned int*)(0x422BAA88UL))) +#define bM4_TMRA4_PCONR6_STPC1 (*((volatile unsigned int*)(0x422BAA8CUL))) +#define bM4_TMRA4_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422BAA90UL))) +#define bM4_TMRA4_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422BAA94UL))) +#define bM4_TMRA4_PCONR6_PERC0 (*((volatile unsigned int*)(0x422BAA98UL))) +#define bM4_TMRA4_PCONR6_PERC1 (*((volatile unsigned int*)(0x422BAA9CUL))) +#define bM4_TMRA4_PCONR6_FORC0 (*((volatile unsigned int*)(0x422BAAA0UL))) +#define bM4_TMRA4_PCONR6_FORC1 (*((volatile unsigned int*)(0x422BAAA4UL))) +#define bM4_TMRA4_PCONR6_OUTEN (*((volatile unsigned int*)(0x422BAAB0UL))) +#define bM4_TMRA4_PCONR7_STAC0 (*((volatile unsigned int*)(0x422BAB00UL))) +#define bM4_TMRA4_PCONR7_STAC1 (*((volatile unsigned int*)(0x422BAB04UL))) +#define bM4_TMRA4_PCONR7_STPC0 (*((volatile unsigned int*)(0x422BAB08UL))) +#define bM4_TMRA4_PCONR7_STPC1 (*((volatile unsigned int*)(0x422BAB0CUL))) +#define bM4_TMRA4_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422BAB10UL))) +#define bM4_TMRA4_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422BAB14UL))) +#define bM4_TMRA4_PCONR7_PERC0 (*((volatile unsigned int*)(0x422BAB18UL))) +#define bM4_TMRA4_PCONR7_PERC1 (*((volatile unsigned int*)(0x422BAB1CUL))) +#define bM4_TMRA4_PCONR7_FORC0 (*((volatile unsigned int*)(0x422BAB20UL))) +#define bM4_TMRA4_PCONR7_FORC1 (*((volatile unsigned int*)(0x422BAB24UL))) +#define bM4_TMRA4_PCONR7_OUTEN (*((volatile unsigned int*)(0x422BAB30UL))) +#define bM4_TMRA4_PCONR8_STAC0 (*((volatile unsigned int*)(0x422BAB80UL))) +#define bM4_TMRA4_PCONR8_STAC1 (*((volatile unsigned int*)(0x422BAB84UL))) +#define bM4_TMRA4_PCONR8_STPC0 (*((volatile unsigned int*)(0x422BAB88UL))) +#define bM4_TMRA4_PCONR8_STPC1 (*((volatile unsigned int*)(0x422BAB8CUL))) +#define bM4_TMRA4_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422BAB90UL))) +#define bM4_TMRA4_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422BAB94UL))) +#define bM4_TMRA4_PCONR8_PERC0 (*((volatile unsigned int*)(0x422BAB98UL))) +#define bM4_TMRA4_PCONR8_PERC1 (*((volatile unsigned int*)(0x422BAB9CUL))) +#define bM4_TMRA4_PCONR8_FORC0 (*((volatile unsigned int*)(0x422BABA0UL))) +#define bM4_TMRA4_PCONR8_FORC1 (*((volatile unsigned int*)(0x422BABA4UL))) +#define bM4_TMRA4_PCONR8_OUTEN (*((volatile unsigned int*)(0x422BABB0UL))) +#define bM4_TMRA5_CNTER_CNT0 (*((volatile unsigned int*)(0x422C0000UL))) +#define bM4_TMRA5_CNTER_CNT1 (*((volatile unsigned int*)(0x422C0004UL))) +#define bM4_TMRA5_CNTER_CNT2 (*((volatile unsigned int*)(0x422C0008UL))) +#define bM4_TMRA5_CNTER_CNT3 (*((volatile unsigned int*)(0x422C000CUL))) +#define bM4_TMRA5_CNTER_CNT4 (*((volatile unsigned int*)(0x422C0010UL))) +#define bM4_TMRA5_CNTER_CNT5 (*((volatile unsigned int*)(0x422C0014UL))) +#define bM4_TMRA5_CNTER_CNT6 (*((volatile unsigned int*)(0x422C0018UL))) +#define bM4_TMRA5_CNTER_CNT7 (*((volatile unsigned int*)(0x422C001CUL))) +#define bM4_TMRA5_CNTER_CNT8 (*((volatile unsigned int*)(0x422C0020UL))) +#define bM4_TMRA5_CNTER_CNT9 (*((volatile unsigned int*)(0x422C0024UL))) +#define bM4_TMRA5_CNTER_CNT10 (*((volatile unsigned int*)(0x422C0028UL))) +#define bM4_TMRA5_CNTER_CNT11 (*((volatile unsigned int*)(0x422C002CUL))) +#define bM4_TMRA5_CNTER_CNT12 (*((volatile unsigned int*)(0x422C0030UL))) +#define bM4_TMRA5_CNTER_CNT13 (*((volatile unsigned int*)(0x422C0034UL))) +#define bM4_TMRA5_CNTER_CNT14 (*((volatile unsigned int*)(0x422C0038UL))) +#define bM4_TMRA5_CNTER_CNT15 (*((volatile unsigned int*)(0x422C003CUL))) +#define bM4_TMRA5_PERAR_PER0 (*((volatile unsigned int*)(0x422C0080UL))) +#define bM4_TMRA5_PERAR_PER1 (*((volatile unsigned int*)(0x422C0084UL))) +#define bM4_TMRA5_PERAR_PER2 (*((volatile unsigned int*)(0x422C0088UL))) +#define bM4_TMRA5_PERAR_PER3 (*((volatile unsigned int*)(0x422C008CUL))) +#define bM4_TMRA5_PERAR_PER4 (*((volatile unsigned int*)(0x422C0090UL))) +#define bM4_TMRA5_PERAR_PER5 (*((volatile unsigned int*)(0x422C0094UL))) +#define bM4_TMRA5_PERAR_PER6 (*((volatile unsigned int*)(0x422C0098UL))) +#define bM4_TMRA5_PERAR_PER7 (*((volatile unsigned int*)(0x422C009CUL))) +#define bM4_TMRA5_PERAR_PER8 (*((volatile unsigned int*)(0x422C00A0UL))) +#define bM4_TMRA5_PERAR_PER9 (*((volatile unsigned int*)(0x422C00A4UL))) +#define bM4_TMRA5_PERAR_PER10 (*((volatile unsigned int*)(0x422C00A8UL))) +#define bM4_TMRA5_PERAR_PER11 (*((volatile unsigned int*)(0x422C00ACUL))) +#define bM4_TMRA5_PERAR_PER12 (*((volatile unsigned int*)(0x422C00B0UL))) +#define bM4_TMRA5_PERAR_PER13 (*((volatile unsigned int*)(0x422C00B4UL))) +#define bM4_TMRA5_PERAR_PER14 (*((volatile unsigned int*)(0x422C00B8UL))) +#define bM4_TMRA5_PERAR_PER15 (*((volatile unsigned int*)(0x422C00BCUL))) +#define bM4_TMRA5_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C0800UL))) +#define bM4_TMRA5_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C0804UL))) +#define bM4_TMRA5_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C0808UL))) +#define bM4_TMRA5_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C080CUL))) +#define bM4_TMRA5_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C0810UL))) +#define bM4_TMRA5_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C0814UL))) +#define bM4_TMRA5_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C0818UL))) +#define bM4_TMRA5_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C081CUL))) +#define bM4_TMRA5_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C0820UL))) +#define bM4_TMRA5_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C0824UL))) +#define bM4_TMRA5_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C0828UL))) +#define bM4_TMRA5_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C082CUL))) +#define bM4_TMRA5_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C0830UL))) +#define bM4_TMRA5_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C0834UL))) +#define bM4_TMRA5_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C0838UL))) +#define bM4_TMRA5_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C083CUL))) +#define bM4_TMRA5_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C0880UL))) +#define bM4_TMRA5_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C0884UL))) +#define bM4_TMRA5_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C0888UL))) +#define bM4_TMRA5_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C088CUL))) +#define bM4_TMRA5_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C0890UL))) +#define bM4_TMRA5_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C0894UL))) +#define bM4_TMRA5_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C0898UL))) +#define bM4_TMRA5_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C089CUL))) +#define bM4_TMRA5_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C08A0UL))) +#define bM4_TMRA5_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C08A4UL))) +#define bM4_TMRA5_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C08A8UL))) +#define bM4_TMRA5_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C08ACUL))) +#define bM4_TMRA5_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C08B0UL))) +#define bM4_TMRA5_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C08B4UL))) +#define bM4_TMRA5_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C08B8UL))) +#define bM4_TMRA5_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C08BCUL))) +#define bM4_TMRA5_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C0900UL))) +#define bM4_TMRA5_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C0904UL))) +#define bM4_TMRA5_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C0908UL))) +#define bM4_TMRA5_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C090CUL))) +#define bM4_TMRA5_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C0910UL))) +#define bM4_TMRA5_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C0914UL))) +#define bM4_TMRA5_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C0918UL))) +#define bM4_TMRA5_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C091CUL))) +#define bM4_TMRA5_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C0920UL))) +#define bM4_TMRA5_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C0924UL))) +#define bM4_TMRA5_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C0928UL))) +#define bM4_TMRA5_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C092CUL))) +#define bM4_TMRA5_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C0930UL))) +#define bM4_TMRA5_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C0934UL))) +#define bM4_TMRA5_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C0938UL))) +#define bM4_TMRA5_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C093CUL))) +#define bM4_TMRA5_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C0980UL))) +#define bM4_TMRA5_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C0984UL))) +#define bM4_TMRA5_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C0988UL))) +#define bM4_TMRA5_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C098CUL))) +#define bM4_TMRA5_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C0990UL))) +#define bM4_TMRA5_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C0994UL))) +#define bM4_TMRA5_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C0998UL))) +#define bM4_TMRA5_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C099CUL))) +#define bM4_TMRA5_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C09A0UL))) +#define bM4_TMRA5_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C09A4UL))) +#define bM4_TMRA5_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C09A8UL))) +#define bM4_TMRA5_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C09ACUL))) +#define bM4_TMRA5_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C09B0UL))) +#define bM4_TMRA5_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C09B4UL))) +#define bM4_TMRA5_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C09B8UL))) +#define bM4_TMRA5_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C09BCUL))) +#define bM4_TMRA5_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C0A00UL))) +#define bM4_TMRA5_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C0A04UL))) +#define bM4_TMRA5_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C0A08UL))) +#define bM4_TMRA5_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C0A0CUL))) +#define bM4_TMRA5_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C0A10UL))) +#define bM4_TMRA5_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C0A14UL))) +#define bM4_TMRA5_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C0A18UL))) +#define bM4_TMRA5_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C0A1CUL))) +#define bM4_TMRA5_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C0A20UL))) +#define bM4_TMRA5_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C0A24UL))) +#define bM4_TMRA5_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C0A28UL))) +#define bM4_TMRA5_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C0A2CUL))) +#define bM4_TMRA5_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C0A30UL))) +#define bM4_TMRA5_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C0A34UL))) +#define bM4_TMRA5_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C0A38UL))) +#define bM4_TMRA5_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C0A3CUL))) +#define bM4_TMRA5_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C0A80UL))) +#define bM4_TMRA5_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C0A84UL))) +#define bM4_TMRA5_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C0A88UL))) +#define bM4_TMRA5_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C0A8CUL))) +#define bM4_TMRA5_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C0A90UL))) +#define bM4_TMRA5_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C0A94UL))) +#define bM4_TMRA5_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C0A98UL))) +#define bM4_TMRA5_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C0A9CUL))) +#define bM4_TMRA5_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C0AA0UL))) +#define bM4_TMRA5_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C0AA4UL))) +#define bM4_TMRA5_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C0AA8UL))) +#define bM4_TMRA5_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C0AACUL))) +#define bM4_TMRA5_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C0AB0UL))) +#define bM4_TMRA5_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C0AB4UL))) +#define bM4_TMRA5_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C0AB8UL))) +#define bM4_TMRA5_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C0ABCUL))) +#define bM4_TMRA5_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C0B00UL))) +#define bM4_TMRA5_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C0B04UL))) +#define bM4_TMRA5_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C0B08UL))) +#define bM4_TMRA5_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C0B0CUL))) +#define bM4_TMRA5_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C0B10UL))) +#define bM4_TMRA5_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C0B14UL))) +#define bM4_TMRA5_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C0B18UL))) +#define bM4_TMRA5_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C0B1CUL))) +#define bM4_TMRA5_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C0B20UL))) +#define bM4_TMRA5_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C0B24UL))) +#define bM4_TMRA5_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C0B28UL))) +#define bM4_TMRA5_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C0B2CUL))) +#define bM4_TMRA5_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C0B30UL))) +#define bM4_TMRA5_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C0B34UL))) +#define bM4_TMRA5_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C0B38UL))) +#define bM4_TMRA5_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C0B3CUL))) +#define bM4_TMRA5_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C0B80UL))) +#define bM4_TMRA5_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C0B84UL))) +#define bM4_TMRA5_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C0B88UL))) +#define bM4_TMRA5_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C0B8CUL))) +#define bM4_TMRA5_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C0B90UL))) +#define bM4_TMRA5_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C0B94UL))) +#define bM4_TMRA5_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C0B98UL))) +#define bM4_TMRA5_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C0B9CUL))) +#define bM4_TMRA5_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C0BA0UL))) +#define bM4_TMRA5_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C0BA4UL))) +#define bM4_TMRA5_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C0BA8UL))) +#define bM4_TMRA5_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C0BACUL))) +#define bM4_TMRA5_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C0BB0UL))) +#define bM4_TMRA5_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C0BB4UL))) +#define bM4_TMRA5_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C0BB8UL))) +#define bM4_TMRA5_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C0BBCUL))) +#define bM4_TMRA5_BCSTR_START (*((volatile unsigned int*)(0x422C1000UL))) +#define bM4_TMRA5_BCSTR_DIR (*((volatile unsigned int*)(0x422C1004UL))) +#define bM4_TMRA5_BCSTR_MODE (*((volatile unsigned int*)(0x422C1008UL))) +#define bM4_TMRA5_BCSTR_SYNST (*((volatile unsigned int*)(0x422C100CUL))) +#define bM4_TMRA5_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C1010UL))) +#define bM4_TMRA5_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C1014UL))) +#define bM4_TMRA5_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C1018UL))) +#define bM4_TMRA5_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C101CUL))) +#define bM4_TMRA5_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C1030UL))) +#define bM4_TMRA5_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C1034UL))) +#define bM4_TMRA5_BCSTR_OVFF (*((volatile unsigned int*)(0x422C1038UL))) +#define bM4_TMRA5_BCSTR_UDFF (*((volatile unsigned int*)(0x422C103CUL))) +#define bM4_TMRA5_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C1080UL))) +#define bM4_TMRA5_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C1084UL))) +#define bM4_TMRA5_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C1088UL))) +#define bM4_TMRA5_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C1090UL))) +#define bM4_TMRA5_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C1094UL))) +#define bM4_TMRA5_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C1098UL))) +#define bM4_TMRA5_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C10A0UL))) +#define bM4_TMRA5_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C10A4UL))) +#define bM4_TMRA5_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C10A8UL))) +#define bM4_TMRA5_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C10B0UL))) +#define bM4_TMRA5_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C10B4UL))) +#define bM4_TMRA5_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C10B8UL))) +#define bM4_TMRA5_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C10BCUL))) +#define bM4_TMRA5_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C1100UL))) +#define bM4_TMRA5_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C1104UL))) +#define bM4_TMRA5_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C1108UL))) +#define bM4_TMRA5_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C110CUL))) +#define bM4_TMRA5_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C1110UL))) +#define bM4_TMRA5_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C1114UL))) +#define bM4_TMRA5_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C1118UL))) +#define bM4_TMRA5_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C111CUL))) +#define bM4_TMRA5_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C1120UL))) +#define bM4_TMRA5_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C1124UL))) +#define bM4_TMRA5_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C1128UL))) +#define bM4_TMRA5_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C112CUL))) +#define bM4_TMRA5_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C1130UL))) +#define bM4_TMRA5_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C1180UL))) +#define bM4_TMRA5_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C1184UL))) +#define bM4_TMRA5_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C1188UL))) +#define bM4_TMRA5_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C118CUL))) +#define bM4_TMRA5_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C1190UL))) +#define bM4_TMRA5_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C1194UL))) +#define bM4_TMRA5_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C1198UL))) +#define bM4_TMRA5_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C119CUL))) +#define bM4_TMRA5_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C11A0UL))) +#define bM4_TMRA5_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C11A4UL))) +#define bM4_TMRA5_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C11A8UL))) +#define bM4_TMRA5_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C11ACUL))) +#define bM4_TMRA5_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C11B0UL))) +#define bM4_TMRA5_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C1200UL))) +#define bM4_TMRA5_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C1204UL))) +#define bM4_TMRA5_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C1208UL))) +#define bM4_TMRA5_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C120CUL))) +#define bM4_TMRA5_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C1210UL))) +#define bM4_TMRA5_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C1214UL))) +#define bM4_TMRA5_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C1218UL))) +#define bM4_TMRA5_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C121CUL))) +#define bM4_TMRA5_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C1280UL))) +#define bM4_TMRA5_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C1284UL))) +#define bM4_TMRA5_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C1288UL))) +#define bM4_TMRA5_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C128CUL))) +#define bM4_TMRA5_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C1290UL))) +#define bM4_TMRA5_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C1294UL))) +#define bM4_TMRA5_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C1298UL))) +#define bM4_TMRA5_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C129CUL))) +#define bM4_TMRA5_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C1300UL))) +#define bM4_TMRA5_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C1304UL))) +#define bM4_TMRA5_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C1308UL))) +#define bM4_TMRA5_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C1320UL))) +#define bM4_TMRA5_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C1324UL))) +#define bM4_TMRA5_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C1328UL))) +#define bM4_TMRA5_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C1330UL))) +#define bM4_TMRA5_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C1334UL))) +#define bM4_TMRA5_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C1338UL))) +#define bM4_TMRA5_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C1380UL))) +#define bM4_TMRA5_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C1384UL))) +#define bM4_TMRA5_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C1388UL))) +#define bM4_TMRA5_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C138CUL))) +#define bM4_TMRA5_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C1390UL))) +#define bM4_TMRA5_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C1394UL))) +#define bM4_TMRA5_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C1398UL))) +#define bM4_TMRA5_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C139CUL))) +#define bM4_TMRA5_BCONR1_BEN (*((volatile unsigned int*)(0x422C1800UL))) +#define bM4_TMRA5_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C1804UL))) +#define bM4_TMRA5_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C1808UL))) +#define bM4_TMRA5_BCONR2_BEN (*((volatile unsigned int*)(0x422C1900UL))) +#define bM4_TMRA5_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C1904UL))) +#define bM4_TMRA5_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C1908UL))) +#define bM4_TMRA5_BCONR3_BEN (*((volatile unsigned int*)(0x422C1A00UL))) +#define bM4_TMRA5_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C1A04UL))) +#define bM4_TMRA5_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C1A08UL))) +#define bM4_TMRA5_BCONR4_BEN (*((volatile unsigned int*)(0x422C1B00UL))) +#define bM4_TMRA5_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C1B04UL))) +#define bM4_TMRA5_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C1B08UL))) +#define bM4_TMRA5_CCONR1_CAPMD (*((volatile unsigned int*)(0x422C2000UL))) +#define bM4_TMRA5_CCONR1_HICP0 (*((volatile unsigned int*)(0x422C2010UL))) +#define bM4_TMRA5_CCONR1_HICP1 (*((volatile unsigned int*)(0x422C2014UL))) +#define bM4_TMRA5_CCONR1_HICP2 (*((volatile unsigned int*)(0x422C2018UL))) +#define bM4_TMRA5_CCONR1_HICP3 (*((volatile unsigned int*)(0x422C2020UL))) +#define bM4_TMRA5_CCONR1_HICP4 (*((volatile unsigned int*)(0x422C2024UL))) +#define bM4_TMRA5_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422C2030UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422C2034UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422C2038UL))) +#define bM4_TMRA5_CCONR2_CAPMD (*((volatile unsigned int*)(0x422C2080UL))) +#define bM4_TMRA5_CCONR2_HICP0 (*((volatile unsigned int*)(0x422C2090UL))) +#define bM4_TMRA5_CCONR2_HICP1 (*((volatile unsigned int*)(0x422C2094UL))) +#define bM4_TMRA5_CCONR2_HICP2 (*((volatile unsigned int*)(0x422C2098UL))) +#define bM4_TMRA5_CCONR2_HICP3 (*((volatile unsigned int*)(0x422C20A0UL))) +#define bM4_TMRA5_CCONR2_HICP4 (*((volatile unsigned int*)(0x422C20A4UL))) +#define bM4_TMRA5_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422C20B0UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422C20B4UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422C20B8UL))) +#define bM4_TMRA5_CCONR3_CAPMD (*((volatile unsigned int*)(0x422C2100UL))) +#define bM4_TMRA5_CCONR3_HICP0 (*((volatile unsigned int*)(0x422C2110UL))) +#define bM4_TMRA5_CCONR3_HICP1 (*((volatile unsigned int*)(0x422C2114UL))) +#define bM4_TMRA5_CCONR3_HICP2 (*((volatile unsigned int*)(0x422C2118UL))) +#define bM4_TMRA5_CCONR3_HICP3 (*((volatile unsigned int*)(0x422C2120UL))) +#define bM4_TMRA5_CCONR3_HICP4 (*((volatile unsigned int*)(0x422C2124UL))) +#define bM4_TMRA5_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422C2130UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422C2134UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422C2138UL))) +#define bM4_TMRA5_CCONR4_CAPMD (*((volatile unsigned int*)(0x422C2180UL))) +#define bM4_TMRA5_CCONR4_HICP0 (*((volatile unsigned int*)(0x422C2190UL))) +#define bM4_TMRA5_CCONR4_HICP1 (*((volatile unsigned int*)(0x422C2194UL))) +#define bM4_TMRA5_CCONR4_HICP2 (*((volatile unsigned int*)(0x422C2198UL))) +#define bM4_TMRA5_CCONR4_HICP3 (*((volatile unsigned int*)(0x422C21A0UL))) +#define bM4_TMRA5_CCONR4_HICP4 (*((volatile unsigned int*)(0x422C21A4UL))) +#define bM4_TMRA5_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422C21B0UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422C21B4UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422C21B8UL))) +#define bM4_TMRA5_CCONR5_CAPMD (*((volatile unsigned int*)(0x422C2200UL))) +#define bM4_TMRA5_CCONR5_HICP0 (*((volatile unsigned int*)(0x422C2210UL))) +#define bM4_TMRA5_CCONR5_HICP1 (*((volatile unsigned int*)(0x422C2214UL))) +#define bM4_TMRA5_CCONR5_HICP2 (*((volatile unsigned int*)(0x422C2218UL))) +#define bM4_TMRA5_CCONR5_HICP3 (*((volatile unsigned int*)(0x422C2220UL))) +#define bM4_TMRA5_CCONR5_HICP4 (*((volatile unsigned int*)(0x422C2224UL))) +#define bM4_TMRA5_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422C2230UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422C2234UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422C2238UL))) +#define bM4_TMRA5_CCONR6_CAPMD (*((volatile unsigned int*)(0x422C2280UL))) +#define bM4_TMRA5_CCONR6_HICP0 (*((volatile unsigned int*)(0x422C2290UL))) +#define bM4_TMRA5_CCONR6_HICP1 (*((volatile unsigned int*)(0x422C2294UL))) +#define bM4_TMRA5_CCONR6_HICP2 (*((volatile unsigned int*)(0x422C2298UL))) +#define bM4_TMRA5_CCONR6_HICP3 (*((volatile unsigned int*)(0x422C22A0UL))) +#define bM4_TMRA5_CCONR6_HICP4 (*((volatile unsigned int*)(0x422C22A4UL))) +#define bM4_TMRA5_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422C22B0UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422C22B4UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422C22B8UL))) +#define bM4_TMRA5_CCONR7_CAPMD (*((volatile unsigned int*)(0x422C2300UL))) +#define bM4_TMRA5_CCONR7_HICP0 (*((volatile unsigned int*)(0x422C2310UL))) +#define bM4_TMRA5_CCONR7_HICP1 (*((volatile unsigned int*)(0x422C2314UL))) +#define bM4_TMRA5_CCONR7_HICP2 (*((volatile unsigned int*)(0x422C2318UL))) +#define bM4_TMRA5_CCONR7_HICP3 (*((volatile unsigned int*)(0x422C2320UL))) +#define bM4_TMRA5_CCONR7_HICP4 (*((volatile unsigned int*)(0x422C2324UL))) +#define bM4_TMRA5_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422C2330UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422C2334UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422C2338UL))) +#define bM4_TMRA5_CCONR8_CAPMD (*((volatile unsigned int*)(0x422C2380UL))) +#define bM4_TMRA5_CCONR8_HICP0 (*((volatile unsigned int*)(0x422C2390UL))) +#define bM4_TMRA5_CCONR8_HICP1 (*((volatile unsigned int*)(0x422C2394UL))) +#define bM4_TMRA5_CCONR8_HICP2 (*((volatile unsigned int*)(0x422C2398UL))) +#define bM4_TMRA5_CCONR8_HICP3 (*((volatile unsigned int*)(0x422C23A0UL))) +#define bM4_TMRA5_CCONR8_HICP4 (*((volatile unsigned int*)(0x422C23A4UL))) +#define bM4_TMRA5_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422C23B0UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422C23B4UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422C23B8UL))) +#define bM4_TMRA5_PCONR1_STAC0 (*((volatile unsigned int*)(0x422C2800UL))) +#define bM4_TMRA5_PCONR1_STAC1 (*((volatile unsigned int*)(0x422C2804UL))) +#define bM4_TMRA5_PCONR1_STPC0 (*((volatile unsigned int*)(0x422C2808UL))) +#define bM4_TMRA5_PCONR1_STPC1 (*((volatile unsigned int*)(0x422C280CUL))) +#define bM4_TMRA5_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422C2810UL))) +#define bM4_TMRA5_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422C2814UL))) +#define bM4_TMRA5_PCONR1_PERC0 (*((volatile unsigned int*)(0x422C2818UL))) +#define bM4_TMRA5_PCONR1_PERC1 (*((volatile unsigned int*)(0x422C281CUL))) +#define bM4_TMRA5_PCONR1_FORC0 (*((volatile unsigned int*)(0x422C2820UL))) +#define bM4_TMRA5_PCONR1_FORC1 (*((volatile unsigned int*)(0x422C2824UL))) +#define bM4_TMRA5_PCONR1_OUTEN (*((volatile unsigned int*)(0x422C2830UL))) +#define bM4_TMRA5_PCONR2_STAC0 (*((volatile unsigned int*)(0x422C2880UL))) +#define bM4_TMRA5_PCONR2_STAC1 (*((volatile unsigned int*)(0x422C2884UL))) +#define bM4_TMRA5_PCONR2_STPC0 (*((volatile unsigned int*)(0x422C2888UL))) +#define bM4_TMRA5_PCONR2_STPC1 (*((volatile unsigned int*)(0x422C288CUL))) +#define bM4_TMRA5_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422C2890UL))) +#define bM4_TMRA5_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422C2894UL))) +#define bM4_TMRA5_PCONR2_PERC0 (*((volatile unsigned int*)(0x422C2898UL))) +#define bM4_TMRA5_PCONR2_PERC1 (*((volatile unsigned int*)(0x422C289CUL))) +#define bM4_TMRA5_PCONR2_FORC0 (*((volatile unsigned int*)(0x422C28A0UL))) +#define bM4_TMRA5_PCONR2_FORC1 (*((volatile unsigned int*)(0x422C28A4UL))) +#define bM4_TMRA5_PCONR2_OUTEN (*((volatile unsigned int*)(0x422C28B0UL))) +#define bM4_TMRA5_PCONR3_STAC0 (*((volatile unsigned int*)(0x422C2900UL))) +#define bM4_TMRA5_PCONR3_STAC1 (*((volatile unsigned int*)(0x422C2904UL))) +#define bM4_TMRA5_PCONR3_STPC0 (*((volatile unsigned int*)(0x422C2908UL))) +#define bM4_TMRA5_PCONR3_STPC1 (*((volatile unsigned int*)(0x422C290CUL))) +#define bM4_TMRA5_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422C2910UL))) +#define bM4_TMRA5_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422C2914UL))) +#define bM4_TMRA5_PCONR3_PERC0 (*((volatile unsigned int*)(0x422C2918UL))) +#define bM4_TMRA5_PCONR3_PERC1 (*((volatile unsigned int*)(0x422C291CUL))) +#define bM4_TMRA5_PCONR3_FORC0 (*((volatile unsigned int*)(0x422C2920UL))) +#define bM4_TMRA5_PCONR3_FORC1 (*((volatile unsigned int*)(0x422C2924UL))) +#define bM4_TMRA5_PCONR3_OUTEN (*((volatile unsigned int*)(0x422C2930UL))) +#define bM4_TMRA5_PCONR4_STAC0 (*((volatile unsigned int*)(0x422C2980UL))) +#define bM4_TMRA5_PCONR4_STAC1 (*((volatile unsigned int*)(0x422C2984UL))) +#define bM4_TMRA5_PCONR4_STPC0 (*((volatile unsigned int*)(0x422C2988UL))) +#define bM4_TMRA5_PCONR4_STPC1 (*((volatile unsigned int*)(0x422C298CUL))) +#define bM4_TMRA5_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422C2990UL))) +#define bM4_TMRA5_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422C2994UL))) +#define bM4_TMRA5_PCONR4_PERC0 (*((volatile unsigned int*)(0x422C2998UL))) +#define bM4_TMRA5_PCONR4_PERC1 (*((volatile unsigned int*)(0x422C299CUL))) +#define bM4_TMRA5_PCONR4_FORC0 (*((volatile unsigned int*)(0x422C29A0UL))) +#define bM4_TMRA5_PCONR4_FORC1 (*((volatile unsigned int*)(0x422C29A4UL))) +#define bM4_TMRA5_PCONR4_OUTEN (*((volatile unsigned int*)(0x422C29B0UL))) +#define bM4_TMRA5_PCONR5_STAC0 (*((volatile unsigned int*)(0x422C2A00UL))) +#define bM4_TMRA5_PCONR5_STAC1 (*((volatile unsigned int*)(0x422C2A04UL))) +#define bM4_TMRA5_PCONR5_STPC0 (*((volatile unsigned int*)(0x422C2A08UL))) +#define bM4_TMRA5_PCONR5_STPC1 (*((volatile unsigned int*)(0x422C2A0CUL))) +#define bM4_TMRA5_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422C2A10UL))) +#define bM4_TMRA5_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422C2A14UL))) +#define bM4_TMRA5_PCONR5_PERC0 (*((volatile unsigned int*)(0x422C2A18UL))) +#define bM4_TMRA5_PCONR5_PERC1 (*((volatile unsigned int*)(0x422C2A1CUL))) +#define bM4_TMRA5_PCONR5_FORC0 (*((volatile unsigned int*)(0x422C2A20UL))) +#define bM4_TMRA5_PCONR5_FORC1 (*((volatile unsigned int*)(0x422C2A24UL))) +#define bM4_TMRA5_PCONR5_OUTEN (*((volatile unsigned int*)(0x422C2A30UL))) +#define bM4_TMRA5_PCONR6_STAC0 (*((volatile unsigned int*)(0x422C2A80UL))) +#define bM4_TMRA5_PCONR6_STAC1 (*((volatile unsigned int*)(0x422C2A84UL))) +#define bM4_TMRA5_PCONR6_STPC0 (*((volatile unsigned int*)(0x422C2A88UL))) +#define bM4_TMRA5_PCONR6_STPC1 (*((volatile unsigned int*)(0x422C2A8CUL))) +#define bM4_TMRA5_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422C2A90UL))) +#define bM4_TMRA5_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422C2A94UL))) +#define bM4_TMRA5_PCONR6_PERC0 (*((volatile unsigned int*)(0x422C2A98UL))) +#define bM4_TMRA5_PCONR6_PERC1 (*((volatile unsigned int*)(0x422C2A9CUL))) +#define bM4_TMRA5_PCONR6_FORC0 (*((volatile unsigned int*)(0x422C2AA0UL))) +#define bM4_TMRA5_PCONR6_FORC1 (*((volatile unsigned int*)(0x422C2AA4UL))) +#define bM4_TMRA5_PCONR6_OUTEN (*((volatile unsigned int*)(0x422C2AB0UL))) +#define bM4_TMRA5_PCONR7_STAC0 (*((volatile unsigned int*)(0x422C2B00UL))) +#define bM4_TMRA5_PCONR7_STAC1 (*((volatile unsigned int*)(0x422C2B04UL))) +#define bM4_TMRA5_PCONR7_STPC0 (*((volatile unsigned int*)(0x422C2B08UL))) +#define bM4_TMRA5_PCONR7_STPC1 (*((volatile unsigned int*)(0x422C2B0CUL))) +#define bM4_TMRA5_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422C2B10UL))) +#define bM4_TMRA5_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422C2B14UL))) +#define bM4_TMRA5_PCONR7_PERC0 (*((volatile unsigned int*)(0x422C2B18UL))) +#define bM4_TMRA5_PCONR7_PERC1 (*((volatile unsigned int*)(0x422C2B1CUL))) +#define bM4_TMRA5_PCONR7_FORC0 (*((volatile unsigned int*)(0x422C2B20UL))) +#define bM4_TMRA5_PCONR7_FORC1 (*((volatile unsigned int*)(0x422C2B24UL))) +#define bM4_TMRA5_PCONR7_OUTEN (*((volatile unsigned int*)(0x422C2B30UL))) +#define bM4_TMRA5_PCONR8_STAC0 (*((volatile unsigned int*)(0x422C2B80UL))) +#define bM4_TMRA5_PCONR8_STAC1 (*((volatile unsigned int*)(0x422C2B84UL))) +#define bM4_TMRA5_PCONR8_STPC0 (*((volatile unsigned int*)(0x422C2B88UL))) +#define bM4_TMRA5_PCONR8_STPC1 (*((volatile unsigned int*)(0x422C2B8CUL))) +#define bM4_TMRA5_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422C2B90UL))) +#define bM4_TMRA5_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422C2B94UL))) +#define bM4_TMRA5_PCONR8_PERC0 (*((volatile unsigned int*)(0x422C2B98UL))) +#define bM4_TMRA5_PCONR8_PERC1 (*((volatile unsigned int*)(0x422C2B9CUL))) +#define bM4_TMRA5_PCONR8_FORC0 (*((volatile unsigned int*)(0x422C2BA0UL))) +#define bM4_TMRA5_PCONR8_FORC1 (*((volatile unsigned int*)(0x422C2BA4UL))) +#define bM4_TMRA5_PCONR8_OUTEN (*((volatile unsigned int*)(0x422C2BB0UL))) +#define bM4_TMRA6_CNTER_CNT0 (*((volatile unsigned int*)(0x422C8000UL))) +#define bM4_TMRA6_CNTER_CNT1 (*((volatile unsigned int*)(0x422C8004UL))) +#define bM4_TMRA6_CNTER_CNT2 (*((volatile unsigned int*)(0x422C8008UL))) +#define bM4_TMRA6_CNTER_CNT3 (*((volatile unsigned int*)(0x422C800CUL))) +#define bM4_TMRA6_CNTER_CNT4 (*((volatile unsigned int*)(0x422C8010UL))) +#define bM4_TMRA6_CNTER_CNT5 (*((volatile unsigned int*)(0x422C8014UL))) +#define bM4_TMRA6_CNTER_CNT6 (*((volatile unsigned int*)(0x422C8018UL))) +#define bM4_TMRA6_CNTER_CNT7 (*((volatile unsigned int*)(0x422C801CUL))) +#define bM4_TMRA6_CNTER_CNT8 (*((volatile unsigned int*)(0x422C8020UL))) +#define bM4_TMRA6_CNTER_CNT9 (*((volatile unsigned int*)(0x422C8024UL))) +#define bM4_TMRA6_CNTER_CNT10 (*((volatile unsigned int*)(0x422C8028UL))) +#define bM4_TMRA6_CNTER_CNT11 (*((volatile unsigned int*)(0x422C802CUL))) +#define bM4_TMRA6_CNTER_CNT12 (*((volatile unsigned int*)(0x422C8030UL))) +#define bM4_TMRA6_CNTER_CNT13 (*((volatile unsigned int*)(0x422C8034UL))) +#define bM4_TMRA6_CNTER_CNT14 (*((volatile unsigned int*)(0x422C8038UL))) +#define bM4_TMRA6_CNTER_CNT15 (*((volatile unsigned int*)(0x422C803CUL))) +#define bM4_TMRA6_PERAR_PER0 (*((volatile unsigned int*)(0x422C8080UL))) +#define bM4_TMRA6_PERAR_PER1 (*((volatile unsigned int*)(0x422C8084UL))) +#define bM4_TMRA6_PERAR_PER2 (*((volatile unsigned int*)(0x422C8088UL))) +#define bM4_TMRA6_PERAR_PER3 (*((volatile unsigned int*)(0x422C808CUL))) +#define bM4_TMRA6_PERAR_PER4 (*((volatile unsigned int*)(0x422C8090UL))) +#define bM4_TMRA6_PERAR_PER5 (*((volatile unsigned int*)(0x422C8094UL))) +#define bM4_TMRA6_PERAR_PER6 (*((volatile unsigned int*)(0x422C8098UL))) +#define bM4_TMRA6_PERAR_PER7 (*((volatile unsigned int*)(0x422C809CUL))) +#define bM4_TMRA6_PERAR_PER8 (*((volatile unsigned int*)(0x422C80A0UL))) +#define bM4_TMRA6_PERAR_PER9 (*((volatile unsigned int*)(0x422C80A4UL))) +#define bM4_TMRA6_PERAR_PER10 (*((volatile unsigned int*)(0x422C80A8UL))) +#define bM4_TMRA6_PERAR_PER11 (*((volatile unsigned int*)(0x422C80ACUL))) +#define bM4_TMRA6_PERAR_PER12 (*((volatile unsigned int*)(0x422C80B0UL))) +#define bM4_TMRA6_PERAR_PER13 (*((volatile unsigned int*)(0x422C80B4UL))) +#define bM4_TMRA6_PERAR_PER14 (*((volatile unsigned int*)(0x422C80B8UL))) +#define bM4_TMRA6_PERAR_PER15 (*((volatile unsigned int*)(0x422C80BCUL))) +#define bM4_TMRA6_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C8800UL))) +#define bM4_TMRA6_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C8804UL))) +#define bM4_TMRA6_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C8808UL))) +#define bM4_TMRA6_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C880CUL))) +#define bM4_TMRA6_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C8810UL))) +#define bM4_TMRA6_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C8814UL))) +#define bM4_TMRA6_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C8818UL))) +#define bM4_TMRA6_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C881CUL))) +#define bM4_TMRA6_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C8820UL))) +#define bM4_TMRA6_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C8824UL))) +#define bM4_TMRA6_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C8828UL))) +#define bM4_TMRA6_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C882CUL))) +#define bM4_TMRA6_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C8830UL))) +#define bM4_TMRA6_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C8834UL))) +#define bM4_TMRA6_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C8838UL))) +#define bM4_TMRA6_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C883CUL))) +#define bM4_TMRA6_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C8880UL))) +#define bM4_TMRA6_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C8884UL))) +#define bM4_TMRA6_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C8888UL))) +#define bM4_TMRA6_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C888CUL))) +#define bM4_TMRA6_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C8890UL))) +#define bM4_TMRA6_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C8894UL))) +#define bM4_TMRA6_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C8898UL))) +#define bM4_TMRA6_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C889CUL))) +#define bM4_TMRA6_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C88A0UL))) +#define bM4_TMRA6_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C88A4UL))) +#define bM4_TMRA6_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C88A8UL))) +#define bM4_TMRA6_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C88ACUL))) +#define bM4_TMRA6_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C88B0UL))) +#define bM4_TMRA6_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C88B4UL))) +#define bM4_TMRA6_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C88B8UL))) +#define bM4_TMRA6_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C88BCUL))) +#define bM4_TMRA6_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C8900UL))) +#define bM4_TMRA6_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C8904UL))) +#define bM4_TMRA6_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C8908UL))) +#define bM4_TMRA6_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C890CUL))) +#define bM4_TMRA6_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C8910UL))) +#define bM4_TMRA6_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C8914UL))) +#define bM4_TMRA6_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C8918UL))) +#define bM4_TMRA6_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C891CUL))) +#define bM4_TMRA6_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C8920UL))) +#define bM4_TMRA6_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C8924UL))) +#define bM4_TMRA6_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C8928UL))) +#define bM4_TMRA6_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C892CUL))) +#define bM4_TMRA6_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C8930UL))) +#define bM4_TMRA6_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C8934UL))) +#define bM4_TMRA6_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C8938UL))) +#define bM4_TMRA6_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C893CUL))) +#define bM4_TMRA6_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C8980UL))) +#define bM4_TMRA6_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C8984UL))) +#define bM4_TMRA6_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C8988UL))) +#define bM4_TMRA6_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C898CUL))) +#define bM4_TMRA6_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C8990UL))) +#define bM4_TMRA6_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C8994UL))) +#define bM4_TMRA6_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C8998UL))) +#define bM4_TMRA6_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C899CUL))) +#define bM4_TMRA6_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C89A0UL))) +#define bM4_TMRA6_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C89A4UL))) +#define bM4_TMRA6_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C89A8UL))) +#define bM4_TMRA6_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C89ACUL))) +#define bM4_TMRA6_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C89B0UL))) +#define bM4_TMRA6_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C89B4UL))) +#define bM4_TMRA6_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C89B8UL))) +#define bM4_TMRA6_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C89BCUL))) +#define bM4_TMRA6_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C8A00UL))) +#define bM4_TMRA6_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C8A04UL))) +#define bM4_TMRA6_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C8A08UL))) +#define bM4_TMRA6_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C8A0CUL))) +#define bM4_TMRA6_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C8A10UL))) +#define bM4_TMRA6_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C8A14UL))) +#define bM4_TMRA6_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C8A18UL))) +#define bM4_TMRA6_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C8A1CUL))) +#define bM4_TMRA6_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C8A20UL))) +#define bM4_TMRA6_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C8A24UL))) +#define bM4_TMRA6_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C8A28UL))) +#define bM4_TMRA6_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C8A2CUL))) +#define bM4_TMRA6_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C8A30UL))) +#define bM4_TMRA6_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C8A34UL))) +#define bM4_TMRA6_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C8A38UL))) +#define bM4_TMRA6_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C8A3CUL))) +#define bM4_TMRA6_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C8A80UL))) +#define bM4_TMRA6_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C8A84UL))) +#define bM4_TMRA6_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C8A88UL))) +#define bM4_TMRA6_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C8A8CUL))) +#define bM4_TMRA6_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C8A90UL))) +#define bM4_TMRA6_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C8A94UL))) +#define bM4_TMRA6_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C8A98UL))) +#define bM4_TMRA6_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C8A9CUL))) +#define bM4_TMRA6_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C8AA0UL))) +#define bM4_TMRA6_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C8AA4UL))) +#define bM4_TMRA6_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C8AA8UL))) +#define bM4_TMRA6_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C8AACUL))) +#define bM4_TMRA6_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C8AB0UL))) +#define bM4_TMRA6_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C8AB4UL))) +#define bM4_TMRA6_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C8AB8UL))) +#define bM4_TMRA6_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C8ABCUL))) +#define bM4_TMRA6_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C8B00UL))) +#define bM4_TMRA6_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C8B04UL))) +#define bM4_TMRA6_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C8B08UL))) +#define bM4_TMRA6_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C8B0CUL))) +#define bM4_TMRA6_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C8B10UL))) +#define bM4_TMRA6_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C8B14UL))) +#define bM4_TMRA6_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C8B18UL))) +#define bM4_TMRA6_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C8B1CUL))) +#define bM4_TMRA6_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C8B20UL))) +#define bM4_TMRA6_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C8B24UL))) +#define bM4_TMRA6_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C8B28UL))) +#define bM4_TMRA6_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C8B2CUL))) +#define bM4_TMRA6_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C8B30UL))) +#define bM4_TMRA6_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C8B34UL))) +#define bM4_TMRA6_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C8B38UL))) +#define bM4_TMRA6_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C8B3CUL))) +#define bM4_TMRA6_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C8B80UL))) +#define bM4_TMRA6_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C8B84UL))) +#define bM4_TMRA6_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C8B88UL))) +#define bM4_TMRA6_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C8B8CUL))) +#define bM4_TMRA6_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C8B90UL))) +#define bM4_TMRA6_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C8B94UL))) +#define bM4_TMRA6_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C8B98UL))) +#define bM4_TMRA6_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C8B9CUL))) +#define bM4_TMRA6_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C8BA0UL))) +#define bM4_TMRA6_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C8BA4UL))) +#define bM4_TMRA6_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C8BA8UL))) +#define bM4_TMRA6_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C8BACUL))) +#define bM4_TMRA6_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C8BB0UL))) +#define bM4_TMRA6_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C8BB4UL))) +#define bM4_TMRA6_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C8BB8UL))) +#define bM4_TMRA6_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C8BBCUL))) +#define bM4_TMRA6_BCSTR_START (*((volatile unsigned int*)(0x422C9000UL))) +#define bM4_TMRA6_BCSTR_DIR (*((volatile unsigned int*)(0x422C9004UL))) +#define bM4_TMRA6_BCSTR_MODE (*((volatile unsigned int*)(0x422C9008UL))) +#define bM4_TMRA6_BCSTR_SYNST (*((volatile unsigned int*)(0x422C900CUL))) +#define bM4_TMRA6_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C9010UL))) +#define bM4_TMRA6_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C9014UL))) +#define bM4_TMRA6_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C9018UL))) +#define bM4_TMRA6_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C901CUL))) +#define bM4_TMRA6_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C9030UL))) +#define bM4_TMRA6_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C9034UL))) +#define bM4_TMRA6_BCSTR_OVFF (*((volatile unsigned int*)(0x422C9038UL))) +#define bM4_TMRA6_BCSTR_UDFF (*((volatile unsigned int*)(0x422C903CUL))) +#define bM4_TMRA6_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C9080UL))) +#define bM4_TMRA6_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C9084UL))) +#define bM4_TMRA6_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C9088UL))) +#define bM4_TMRA6_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C9090UL))) +#define bM4_TMRA6_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C9094UL))) +#define bM4_TMRA6_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C9098UL))) +#define bM4_TMRA6_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C90A0UL))) +#define bM4_TMRA6_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C90A4UL))) +#define bM4_TMRA6_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C90A8UL))) +#define bM4_TMRA6_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C90B0UL))) +#define bM4_TMRA6_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C90B4UL))) +#define bM4_TMRA6_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C90B8UL))) +#define bM4_TMRA6_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C90BCUL))) +#define bM4_TMRA6_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C9100UL))) +#define bM4_TMRA6_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C9104UL))) +#define bM4_TMRA6_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C9108UL))) +#define bM4_TMRA6_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C910CUL))) +#define bM4_TMRA6_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C9110UL))) +#define bM4_TMRA6_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C9114UL))) +#define bM4_TMRA6_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C9118UL))) +#define bM4_TMRA6_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C911CUL))) +#define bM4_TMRA6_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C9120UL))) +#define bM4_TMRA6_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C9124UL))) +#define bM4_TMRA6_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C9128UL))) +#define bM4_TMRA6_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C912CUL))) +#define bM4_TMRA6_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C9130UL))) +#define bM4_TMRA6_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C9180UL))) +#define bM4_TMRA6_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C9184UL))) +#define bM4_TMRA6_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C9188UL))) +#define bM4_TMRA6_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C918CUL))) +#define bM4_TMRA6_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C9190UL))) +#define bM4_TMRA6_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C9194UL))) +#define bM4_TMRA6_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C9198UL))) +#define bM4_TMRA6_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C919CUL))) +#define bM4_TMRA6_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C91A0UL))) +#define bM4_TMRA6_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C91A4UL))) +#define bM4_TMRA6_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C91A8UL))) +#define bM4_TMRA6_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C91ACUL))) +#define bM4_TMRA6_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C91B0UL))) +#define bM4_TMRA6_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C9200UL))) +#define bM4_TMRA6_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C9204UL))) +#define bM4_TMRA6_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C9208UL))) +#define bM4_TMRA6_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C920CUL))) +#define bM4_TMRA6_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C9210UL))) +#define bM4_TMRA6_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C9214UL))) +#define bM4_TMRA6_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C9218UL))) +#define bM4_TMRA6_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C921CUL))) +#define bM4_TMRA6_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C9280UL))) +#define bM4_TMRA6_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C9284UL))) +#define bM4_TMRA6_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C9288UL))) +#define bM4_TMRA6_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C928CUL))) +#define bM4_TMRA6_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C9290UL))) +#define bM4_TMRA6_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C9294UL))) +#define bM4_TMRA6_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C9298UL))) +#define bM4_TMRA6_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C929CUL))) +#define bM4_TMRA6_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C9300UL))) +#define bM4_TMRA6_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C9304UL))) +#define bM4_TMRA6_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C9308UL))) +#define bM4_TMRA6_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C9320UL))) +#define bM4_TMRA6_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C9324UL))) +#define bM4_TMRA6_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C9328UL))) +#define bM4_TMRA6_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C9330UL))) +#define bM4_TMRA6_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C9334UL))) +#define bM4_TMRA6_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C9338UL))) +#define bM4_TMRA6_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C9380UL))) +#define bM4_TMRA6_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C9384UL))) +#define bM4_TMRA6_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C9388UL))) +#define bM4_TMRA6_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C938CUL))) +#define bM4_TMRA6_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C9390UL))) +#define bM4_TMRA6_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C9394UL))) +#define bM4_TMRA6_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C9398UL))) +#define bM4_TMRA6_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C939CUL))) +#define bM4_TMRA6_BCONR1_BEN (*((volatile unsigned int*)(0x422C9800UL))) +#define bM4_TMRA6_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C9804UL))) +#define bM4_TMRA6_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C9808UL))) +#define bM4_TMRA6_BCONR2_BEN (*((volatile unsigned int*)(0x422C9900UL))) +#define bM4_TMRA6_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C9904UL))) +#define bM4_TMRA6_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C9908UL))) +#define bM4_TMRA6_BCONR3_BEN (*((volatile unsigned int*)(0x422C9A00UL))) +#define bM4_TMRA6_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C9A04UL))) +#define bM4_TMRA6_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C9A08UL))) +#define bM4_TMRA6_BCONR4_BEN (*((volatile unsigned int*)(0x422C9B00UL))) +#define bM4_TMRA6_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C9B04UL))) +#define bM4_TMRA6_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C9B08UL))) +#define bM4_TMRA6_CCONR1_CAPMD (*((volatile unsigned int*)(0x422CA000UL))) +#define bM4_TMRA6_CCONR1_HICP0 (*((volatile unsigned int*)(0x422CA010UL))) +#define bM4_TMRA6_CCONR1_HICP1 (*((volatile unsigned int*)(0x422CA014UL))) +#define bM4_TMRA6_CCONR1_HICP2 (*((volatile unsigned int*)(0x422CA018UL))) +#define bM4_TMRA6_CCONR1_HICP3 (*((volatile unsigned int*)(0x422CA020UL))) +#define bM4_TMRA6_CCONR1_HICP4 (*((volatile unsigned int*)(0x422CA024UL))) +#define bM4_TMRA6_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422CA030UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422CA034UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422CA038UL))) +#define bM4_TMRA6_CCONR2_CAPMD (*((volatile unsigned int*)(0x422CA080UL))) +#define bM4_TMRA6_CCONR2_HICP0 (*((volatile unsigned int*)(0x422CA090UL))) +#define bM4_TMRA6_CCONR2_HICP1 (*((volatile unsigned int*)(0x422CA094UL))) +#define bM4_TMRA6_CCONR2_HICP2 (*((volatile unsigned int*)(0x422CA098UL))) +#define bM4_TMRA6_CCONR2_HICP3 (*((volatile unsigned int*)(0x422CA0A0UL))) +#define bM4_TMRA6_CCONR2_HICP4 (*((volatile unsigned int*)(0x422CA0A4UL))) +#define bM4_TMRA6_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422CA0B0UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422CA0B4UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422CA0B8UL))) +#define bM4_TMRA6_CCONR3_CAPMD (*((volatile unsigned int*)(0x422CA100UL))) +#define bM4_TMRA6_CCONR3_HICP0 (*((volatile unsigned int*)(0x422CA110UL))) +#define bM4_TMRA6_CCONR3_HICP1 (*((volatile unsigned int*)(0x422CA114UL))) +#define bM4_TMRA6_CCONR3_HICP2 (*((volatile unsigned int*)(0x422CA118UL))) +#define bM4_TMRA6_CCONR3_HICP3 (*((volatile unsigned int*)(0x422CA120UL))) +#define bM4_TMRA6_CCONR3_HICP4 (*((volatile unsigned int*)(0x422CA124UL))) +#define bM4_TMRA6_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422CA130UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422CA134UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422CA138UL))) +#define bM4_TMRA6_CCONR4_CAPMD (*((volatile unsigned int*)(0x422CA180UL))) +#define bM4_TMRA6_CCONR4_HICP0 (*((volatile unsigned int*)(0x422CA190UL))) +#define bM4_TMRA6_CCONR4_HICP1 (*((volatile unsigned int*)(0x422CA194UL))) +#define bM4_TMRA6_CCONR4_HICP2 (*((volatile unsigned int*)(0x422CA198UL))) +#define bM4_TMRA6_CCONR4_HICP3 (*((volatile unsigned int*)(0x422CA1A0UL))) +#define bM4_TMRA6_CCONR4_HICP4 (*((volatile unsigned int*)(0x422CA1A4UL))) +#define bM4_TMRA6_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422CA1B0UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422CA1B4UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422CA1B8UL))) +#define bM4_TMRA6_CCONR5_CAPMD (*((volatile unsigned int*)(0x422CA200UL))) +#define bM4_TMRA6_CCONR5_HICP0 (*((volatile unsigned int*)(0x422CA210UL))) +#define bM4_TMRA6_CCONR5_HICP1 (*((volatile unsigned int*)(0x422CA214UL))) +#define bM4_TMRA6_CCONR5_HICP2 (*((volatile unsigned int*)(0x422CA218UL))) +#define bM4_TMRA6_CCONR5_HICP3 (*((volatile unsigned int*)(0x422CA220UL))) +#define bM4_TMRA6_CCONR5_HICP4 (*((volatile unsigned int*)(0x422CA224UL))) +#define bM4_TMRA6_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422CA230UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422CA234UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422CA238UL))) +#define bM4_TMRA6_CCONR6_CAPMD (*((volatile unsigned int*)(0x422CA280UL))) +#define bM4_TMRA6_CCONR6_HICP0 (*((volatile unsigned int*)(0x422CA290UL))) +#define bM4_TMRA6_CCONR6_HICP1 (*((volatile unsigned int*)(0x422CA294UL))) +#define bM4_TMRA6_CCONR6_HICP2 (*((volatile unsigned int*)(0x422CA298UL))) +#define bM4_TMRA6_CCONR6_HICP3 (*((volatile unsigned int*)(0x422CA2A0UL))) +#define bM4_TMRA6_CCONR6_HICP4 (*((volatile unsigned int*)(0x422CA2A4UL))) +#define bM4_TMRA6_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422CA2B0UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422CA2B4UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422CA2B8UL))) +#define bM4_TMRA6_CCONR7_CAPMD (*((volatile unsigned int*)(0x422CA300UL))) +#define bM4_TMRA6_CCONR7_HICP0 (*((volatile unsigned int*)(0x422CA310UL))) +#define bM4_TMRA6_CCONR7_HICP1 (*((volatile unsigned int*)(0x422CA314UL))) +#define bM4_TMRA6_CCONR7_HICP2 (*((volatile unsigned int*)(0x422CA318UL))) +#define bM4_TMRA6_CCONR7_HICP3 (*((volatile unsigned int*)(0x422CA320UL))) +#define bM4_TMRA6_CCONR7_HICP4 (*((volatile unsigned int*)(0x422CA324UL))) +#define bM4_TMRA6_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422CA330UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422CA334UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422CA338UL))) +#define bM4_TMRA6_CCONR8_CAPMD (*((volatile unsigned int*)(0x422CA380UL))) +#define bM4_TMRA6_CCONR8_HICP0 (*((volatile unsigned int*)(0x422CA390UL))) +#define bM4_TMRA6_CCONR8_HICP1 (*((volatile unsigned int*)(0x422CA394UL))) +#define bM4_TMRA6_CCONR8_HICP2 (*((volatile unsigned int*)(0x422CA398UL))) +#define bM4_TMRA6_CCONR8_HICP3 (*((volatile unsigned int*)(0x422CA3A0UL))) +#define bM4_TMRA6_CCONR8_HICP4 (*((volatile unsigned int*)(0x422CA3A4UL))) +#define bM4_TMRA6_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422CA3B0UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422CA3B4UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422CA3B8UL))) +#define bM4_TMRA6_PCONR1_STAC0 (*((volatile unsigned int*)(0x422CA800UL))) +#define bM4_TMRA6_PCONR1_STAC1 (*((volatile unsigned int*)(0x422CA804UL))) +#define bM4_TMRA6_PCONR1_STPC0 (*((volatile unsigned int*)(0x422CA808UL))) +#define bM4_TMRA6_PCONR1_STPC1 (*((volatile unsigned int*)(0x422CA80CUL))) +#define bM4_TMRA6_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422CA810UL))) +#define bM4_TMRA6_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422CA814UL))) +#define bM4_TMRA6_PCONR1_PERC0 (*((volatile unsigned int*)(0x422CA818UL))) +#define bM4_TMRA6_PCONR1_PERC1 (*((volatile unsigned int*)(0x422CA81CUL))) +#define bM4_TMRA6_PCONR1_FORC0 (*((volatile unsigned int*)(0x422CA820UL))) +#define bM4_TMRA6_PCONR1_FORC1 (*((volatile unsigned int*)(0x422CA824UL))) +#define bM4_TMRA6_PCONR1_OUTEN (*((volatile unsigned int*)(0x422CA830UL))) +#define bM4_TMRA6_PCONR2_STAC0 (*((volatile unsigned int*)(0x422CA880UL))) +#define bM4_TMRA6_PCONR2_STAC1 (*((volatile unsigned int*)(0x422CA884UL))) +#define bM4_TMRA6_PCONR2_STPC0 (*((volatile unsigned int*)(0x422CA888UL))) +#define bM4_TMRA6_PCONR2_STPC1 (*((volatile unsigned int*)(0x422CA88CUL))) +#define bM4_TMRA6_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422CA890UL))) +#define bM4_TMRA6_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422CA894UL))) +#define bM4_TMRA6_PCONR2_PERC0 (*((volatile unsigned int*)(0x422CA898UL))) +#define bM4_TMRA6_PCONR2_PERC1 (*((volatile unsigned int*)(0x422CA89CUL))) +#define bM4_TMRA6_PCONR2_FORC0 (*((volatile unsigned int*)(0x422CA8A0UL))) +#define bM4_TMRA6_PCONR2_FORC1 (*((volatile unsigned int*)(0x422CA8A4UL))) +#define bM4_TMRA6_PCONR2_OUTEN (*((volatile unsigned int*)(0x422CA8B0UL))) +#define bM4_TMRA6_PCONR3_STAC0 (*((volatile unsigned int*)(0x422CA900UL))) +#define bM4_TMRA6_PCONR3_STAC1 (*((volatile unsigned int*)(0x422CA904UL))) +#define bM4_TMRA6_PCONR3_STPC0 (*((volatile unsigned int*)(0x422CA908UL))) +#define bM4_TMRA6_PCONR3_STPC1 (*((volatile unsigned int*)(0x422CA90CUL))) +#define bM4_TMRA6_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422CA910UL))) +#define bM4_TMRA6_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422CA914UL))) +#define bM4_TMRA6_PCONR3_PERC0 (*((volatile unsigned int*)(0x422CA918UL))) +#define bM4_TMRA6_PCONR3_PERC1 (*((volatile unsigned int*)(0x422CA91CUL))) +#define bM4_TMRA6_PCONR3_FORC0 (*((volatile unsigned int*)(0x422CA920UL))) +#define bM4_TMRA6_PCONR3_FORC1 (*((volatile unsigned int*)(0x422CA924UL))) +#define bM4_TMRA6_PCONR3_OUTEN (*((volatile unsigned int*)(0x422CA930UL))) +#define bM4_TMRA6_PCONR4_STAC0 (*((volatile unsigned int*)(0x422CA980UL))) +#define bM4_TMRA6_PCONR4_STAC1 (*((volatile unsigned int*)(0x422CA984UL))) +#define bM4_TMRA6_PCONR4_STPC0 (*((volatile unsigned int*)(0x422CA988UL))) +#define bM4_TMRA6_PCONR4_STPC1 (*((volatile unsigned int*)(0x422CA98CUL))) +#define bM4_TMRA6_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422CA990UL))) +#define bM4_TMRA6_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422CA994UL))) +#define bM4_TMRA6_PCONR4_PERC0 (*((volatile unsigned int*)(0x422CA998UL))) +#define bM4_TMRA6_PCONR4_PERC1 (*((volatile unsigned int*)(0x422CA99CUL))) +#define bM4_TMRA6_PCONR4_FORC0 (*((volatile unsigned int*)(0x422CA9A0UL))) +#define bM4_TMRA6_PCONR4_FORC1 (*((volatile unsigned int*)(0x422CA9A4UL))) +#define bM4_TMRA6_PCONR4_OUTEN (*((volatile unsigned int*)(0x422CA9B0UL))) +#define bM4_TMRA6_PCONR5_STAC0 (*((volatile unsigned int*)(0x422CAA00UL))) +#define bM4_TMRA6_PCONR5_STAC1 (*((volatile unsigned int*)(0x422CAA04UL))) +#define bM4_TMRA6_PCONR5_STPC0 (*((volatile unsigned int*)(0x422CAA08UL))) +#define bM4_TMRA6_PCONR5_STPC1 (*((volatile unsigned int*)(0x422CAA0CUL))) +#define bM4_TMRA6_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422CAA10UL))) +#define bM4_TMRA6_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422CAA14UL))) +#define bM4_TMRA6_PCONR5_PERC0 (*((volatile unsigned int*)(0x422CAA18UL))) +#define bM4_TMRA6_PCONR5_PERC1 (*((volatile unsigned int*)(0x422CAA1CUL))) +#define bM4_TMRA6_PCONR5_FORC0 (*((volatile unsigned int*)(0x422CAA20UL))) +#define bM4_TMRA6_PCONR5_FORC1 (*((volatile unsigned int*)(0x422CAA24UL))) +#define bM4_TMRA6_PCONR5_OUTEN (*((volatile unsigned int*)(0x422CAA30UL))) +#define bM4_TMRA6_PCONR6_STAC0 (*((volatile unsigned int*)(0x422CAA80UL))) +#define bM4_TMRA6_PCONR6_STAC1 (*((volatile unsigned int*)(0x422CAA84UL))) +#define bM4_TMRA6_PCONR6_STPC0 (*((volatile unsigned int*)(0x422CAA88UL))) +#define bM4_TMRA6_PCONR6_STPC1 (*((volatile unsigned int*)(0x422CAA8CUL))) +#define bM4_TMRA6_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422CAA90UL))) +#define bM4_TMRA6_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422CAA94UL))) +#define bM4_TMRA6_PCONR6_PERC0 (*((volatile unsigned int*)(0x422CAA98UL))) +#define bM4_TMRA6_PCONR6_PERC1 (*((volatile unsigned int*)(0x422CAA9CUL))) +#define bM4_TMRA6_PCONR6_FORC0 (*((volatile unsigned int*)(0x422CAAA0UL))) +#define bM4_TMRA6_PCONR6_FORC1 (*((volatile unsigned int*)(0x422CAAA4UL))) +#define bM4_TMRA6_PCONR6_OUTEN (*((volatile unsigned int*)(0x422CAAB0UL))) +#define bM4_TMRA6_PCONR7_STAC0 (*((volatile unsigned int*)(0x422CAB00UL))) +#define bM4_TMRA6_PCONR7_STAC1 (*((volatile unsigned int*)(0x422CAB04UL))) +#define bM4_TMRA6_PCONR7_STPC0 (*((volatile unsigned int*)(0x422CAB08UL))) +#define bM4_TMRA6_PCONR7_STPC1 (*((volatile unsigned int*)(0x422CAB0CUL))) +#define bM4_TMRA6_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422CAB10UL))) +#define bM4_TMRA6_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422CAB14UL))) +#define bM4_TMRA6_PCONR7_PERC0 (*((volatile unsigned int*)(0x422CAB18UL))) +#define bM4_TMRA6_PCONR7_PERC1 (*((volatile unsigned int*)(0x422CAB1CUL))) +#define bM4_TMRA6_PCONR7_FORC0 (*((volatile unsigned int*)(0x422CAB20UL))) +#define bM4_TMRA6_PCONR7_FORC1 (*((volatile unsigned int*)(0x422CAB24UL))) +#define bM4_TMRA6_PCONR7_OUTEN (*((volatile unsigned int*)(0x422CAB30UL))) +#define bM4_TMRA6_PCONR8_STAC0 (*((volatile unsigned int*)(0x422CAB80UL))) +#define bM4_TMRA6_PCONR8_STAC1 (*((volatile unsigned int*)(0x422CAB84UL))) +#define bM4_TMRA6_PCONR8_STPC0 (*((volatile unsigned int*)(0x422CAB88UL))) +#define bM4_TMRA6_PCONR8_STPC1 (*((volatile unsigned int*)(0x422CAB8CUL))) +#define bM4_TMRA6_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422CAB90UL))) +#define bM4_TMRA6_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422CAB94UL))) +#define bM4_TMRA6_PCONR8_PERC0 (*((volatile unsigned int*)(0x422CAB98UL))) +#define bM4_TMRA6_PCONR8_PERC1 (*((volatile unsigned int*)(0x422CAB9CUL))) +#define bM4_TMRA6_PCONR8_FORC0 (*((volatile unsigned int*)(0x422CABA0UL))) +#define bM4_TMRA6_PCONR8_FORC1 (*((volatile unsigned int*)(0x422CABA4UL))) +#define bM4_TMRA6_PCONR8_OUTEN (*((volatile unsigned int*)(0x422CABB0UL))) +#define bM4_TRNG_CR_EN (*((volatile unsigned int*)(0x42820000UL))) +#define bM4_TRNG_CR_RUN (*((volatile unsigned int*)(0x42820004UL))) +#define bM4_TRNG_MR_LOAD (*((volatile unsigned int*)(0x42820080UL))) +#define bM4_TRNG_MR_CNT0 (*((volatile unsigned int*)(0x42820088UL))) +#define bM4_TRNG_MR_CNT1 (*((volatile unsigned int*)(0x4282008CUL))) +#define bM4_TRNG_MR_CNT2 (*((volatile unsigned int*)(0x42820090UL))) +#define bM4_USART1_SR_PE (*((volatile unsigned int*)(0x423A0000UL))) +#define bM4_USART1_SR_FE (*((volatile unsigned int*)(0x423A0004UL))) +#define bM4_USART1_SR_ORE (*((volatile unsigned int*)(0x423A000CUL))) +#define bM4_USART1_SR_RXNE (*((volatile unsigned int*)(0x423A0014UL))) +#define bM4_USART1_SR_TC (*((volatile unsigned int*)(0x423A0018UL))) +#define bM4_USART1_SR_TXE (*((volatile unsigned int*)(0x423A001CUL))) +#define bM4_USART1_SR_RTOF (*((volatile unsigned int*)(0x423A0020UL))) +#define bM4_USART1_SR_MPB (*((volatile unsigned int*)(0x423A0040UL))) +#define bM4_USART1_DR_TDR0 (*((volatile unsigned int*)(0x423A0080UL))) +#define bM4_USART1_DR_TDR1 (*((volatile unsigned int*)(0x423A0084UL))) +#define bM4_USART1_DR_TDR2 (*((volatile unsigned int*)(0x423A0088UL))) +#define bM4_USART1_DR_TDR3 (*((volatile unsigned int*)(0x423A008CUL))) +#define bM4_USART1_DR_TDR4 (*((volatile unsigned int*)(0x423A0090UL))) +#define bM4_USART1_DR_TDR5 (*((volatile unsigned int*)(0x423A0094UL))) +#define bM4_USART1_DR_TDR6 (*((volatile unsigned int*)(0x423A0098UL))) +#define bM4_USART1_DR_TDR7 (*((volatile unsigned int*)(0x423A009CUL))) +#define bM4_USART1_DR_TDR8 (*((volatile unsigned int*)(0x423A00A0UL))) +#define bM4_USART1_DR_MPID (*((volatile unsigned int*)(0x423A00A4UL))) +#define bM4_USART1_DR_RDR0 (*((volatile unsigned int*)(0x423A00C0UL))) +#define bM4_USART1_DR_RDR1 (*((volatile unsigned int*)(0x423A00C4UL))) +#define bM4_USART1_DR_RDR2 (*((volatile unsigned int*)(0x423A00C8UL))) +#define bM4_USART1_DR_RDR3 (*((volatile unsigned int*)(0x423A00CCUL))) +#define bM4_USART1_DR_RDR4 (*((volatile unsigned int*)(0x423A00D0UL))) +#define bM4_USART1_DR_RDR5 (*((volatile unsigned int*)(0x423A00D4UL))) +#define bM4_USART1_DR_RDR6 (*((volatile unsigned int*)(0x423A00D8UL))) +#define bM4_USART1_DR_RDR7 (*((volatile unsigned int*)(0x423A00DCUL))) +#define bM4_USART1_DR_RDR8 (*((volatile unsigned int*)(0x423A00E0UL))) +#define bM4_USART1_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A0100UL))) +#define bM4_USART1_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A0104UL))) +#define bM4_USART1_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A0108UL))) +#define bM4_USART1_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A010CUL))) +#define bM4_USART1_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A0110UL))) +#define bM4_USART1_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A0114UL))) +#define bM4_USART1_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A0118UL))) +#define bM4_USART1_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A0120UL))) +#define bM4_USART1_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A0124UL))) +#define bM4_USART1_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A0128UL))) +#define bM4_USART1_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A012CUL))) +#define bM4_USART1_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A0130UL))) +#define bM4_USART1_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A0134UL))) +#define bM4_USART1_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A0138UL))) +#define bM4_USART1_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A013CUL))) +#define bM4_USART1_CR1_RTOE (*((volatile unsigned int*)(0x423A0180UL))) +#define bM4_USART1_CR1_RTOIE (*((volatile unsigned int*)(0x423A0184UL))) +#define bM4_USART1_CR1_RE (*((volatile unsigned int*)(0x423A0188UL))) +#define bM4_USART1_CR1_TE (*((volatile unsigned int*)(0x423A018CUL))) +#define bM4_USART1_CR1_SLME (*((volatile unsigned int*)(0x423A0190UL))) +#define bM4_USART1_CR1_RIE (*((volatile unsigned int*)(0x423A0194UL))) +#define bM4_USART1_CR1_TCIE (*((volatile unsigned int*)(0x423A0198UL))) +#define bM4_USART1_CR1_TXEIE (*((volatile unsigned int*)(0x423A019CUL))) +#define bM4_USART1_CR1_PS (*((volatile unsigned int*)(0x423A01A4UL))) +#define bM4_USART1_CR1_PCE (*((volatile unsigned int*)(0x423A01A8UL))) +#define bM4_USART1_CR1_M (*((volatile unsigned int*)(0x423A01B0UL))) +#define bM4_USART1_CR1_OVER8 (*((volatile unsigned int*)(0x423A01BCUL))) +#define bM4_USART1_CR1_CPE (*((volatile unsigned int*)(0x423A01C0UL))) +#define bM4_USART1_CR1_CFE (*((volatile unsigned int*)(0x423A01C4UL))) +#define bM4_USART1_CR1_CORE (*((volatile unsigned int*)(0x423A01CCUL))) +#define bM4_USART1_CR1_CRTOF (*((volatile unsigned int*)(0x423A01D0UL))) +#define bM4_USART1_CR1_MS (*((volatile unsigned int*)(0x423A01E0UL))) +#define bM4_USART1_CR1_ML (*((volatile unsigned int*)(0x423A01F0UL))) +#define bM4_USART1_CR1_FBME (*((volatile unsigned int*)(0x423A01F4UL))) +#define bM4_USART1_CR1_NFE (*((volatile unsigned int*)(0x423A01F8UL))) +#define bM4_USART1_CR1_SBS (*((volatile unsigned int*)(0x423A01FCUL))) +#define bM4_USART1_CR2_MPE (*((volatile unsigned int*)(0x423A0200UL))) +#define bM4_USART1_CR2_CLKC0 (*((volatile unsigned int*)(0x423A022CUL))) +#define bM4_USART1_CR2_CLKC1 (*((volatile unsigned int*)(0x423A0230UL))) +#define bM4_USART1_CR2_STOP (*((volatile unsigned int*)(0x423A0234UL))) +#define bM4_USART1_CR3_SCEN (*((volatile unsigned int*)(0x423A0294UL))) +#define bM4_USART1_CR3_CTSE (*((volatile unsigned int*)(0x423A02A4UL))) +#define bM4_USART1_CR3_BCN0 (*((volatile unsigned int*)(0x423A02D4UL))) +#define bM4_USART1_CR3_BCN1 (*((volatile unsigned int*)(0x423A02D8UL))) +#define bM4_USART1_CR3_BCN2 (*((volatile unsigned int*)(0x423A02DCUL))) +#define bM4_USART1_PR_PSC0 (*((volatile unsigned int*)(0x423A0300UL))) +#define bM4_USART1_PR_PSC1 (*((volatile unsigned int*)(0x423A0304UL))) +#define bM4_USART2_SR_PE (*((volatile unsigned int*)(0x423A8000UL))) +#define bM4_USART2_SR_FE (*((volatile unsigned int*)(0x423A8004UL))) +#define bM4_USART2_SR_ORE (*((volatile unsigned int*)(0x423A800CUL))) +#define bM4_USART2_SR_RXNE (*((volatile unsigned int*)(0x423A8014UL))) +#define bM4_USART2_SR_TC (*((volatile unsigned int*)(0x423A8018UL))) +#define bM4_USART2_SR_TXE (*((volatile unsigned int*)(0x423A801CUL))) +#define bM4_USART2_SR_RTOF (*((volatile unsigned int*)(0x423A8020UL))) +#define bM4_USART2_SR_MPB (*((volatile unsigned int*)(0x423A8040UL))) +#define bM4_USART2_DR_TDR0 (*((volatile unsigned int*)(0x423A8080UL))) +#define bM4_USART2_DR_TDR1 (*((volatile unsigned int*)(0x423A8084UL))) +#define bM4_USART2_DR_TDR2 (*((volatile unsigned int*)(0x423A8088UL))) +#define bM4_USART2_DR_TDR3 (*((volatile unsigned int*)(0x423A808CUL))) +#define bM4_USART2_DR_TDR4 (*((volatile unsigned int*)(0x423A8090UL))) +#define bM4_USART2_DR_TDR5 (*((volatile unsigned int*)(0x423A8094UL))) +#define bM4_USART2_DR_TDR6 (*((volatile unsigned int*)(0x423A8098UL))) +#define bM4_USART2_DR_TDR7 (*((volatile unsigned int*)(0x423A809CUL))) +#define bM4_USART2_DR_TDR8 (*((volatile unsigned int*)(0x423A80A0UL))) +#define bM4_USART2_DR_MPID (*((volatile unsigned int*)(0x423A80A4UL))) +#define bM4_USART2_DR_RDR0 (*((volatile unsigned int*)(0x423A80C0UL))) +#define bM4_USART2_DR_RDR1 (*((volatile unsigned int*)(0x423A80C4UL))) +#define bM4_USART2_DR_RDR2 (*((volatile unsigned int*)(0x423A80C8UL))) +#define bM4_USART2_DR_RDR3 (*((volatile unsigned int*)(0x423A80CCUL))) +#define bM4_USART2_DR_RDR4 (*((volatile unsigned int*)(0x423A80D0UL))) +#define bM4_USART2_DR_RDR5 (*((volatile unsigned int*)(0x423A80D4UL))) +#define bM4_USART2_DR_RDR6 (*((volatile unsigned int*)(0x423A80D8UL))) +#define bM4_USART2_DR_RDR7 (*((volatile unsigned int*)(0x423A80DCUL))) +#define bM4_USART2_DR_RDR8 (*((volatile unsigned int*)(0x423A80E0UL))) +#define bM4_USART2_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A8100UL))) +#define bM4_USART2_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A8104UL))) +#define bM4_USART2_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A8108UL))) +#define bM4_USART2_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A810CUL))) +#define bM4_USART2_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A8110UL))) +#define bM4_USART2_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A8114UL))) +#define bM4_USART2_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A8118UL))) +#define bM4_USART2_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A8120UL))) +#define bM4_USART2_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A8124UL))) +#define bM4_USART2_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A8128UL))) +#define bM4_USART2_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A812CUL))) +#define bM4_USART2_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A8130UL))) +#define bM4_USART2_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A8134UL))) +#define bM4_USART2_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A8138UL))) +#define bM4_USART2_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A813CUL))) +#define bM4_USART2_CR1_RTOE (*((volatile unsigned int*)(0x423A8180UL))) +#define bM4_USART2_CR1_RTOIE (*((volatile unsigned int*)(0x423A8184UL))) +#define bM4_USART2_CR1_RE (*((volatile unsigned int*)(0x423A8188UL))) +#define bM4_USART2_CR1_TE (*((volatile unsigned int*)(0x423A818CUL))) +#define bM4_USART2_CR1_SLME (*((volatile unsigned int*)(0x423A8190UL))) +#define bM4_USART2_CR1_RIE (*((volatile unsigned int*)(0x423A8194UL))) +#define bM4_USART2_CR1_TCIE (*((volatile unsigned int*)(0x423A8198UL))) +#define bM4_USART2_CR1_TXEIE (*((volatile unsigned int*)(0x423A819CUL))) +#define bM4_USART2_CR1_PS (*((volatile unsigned int*)(0x423A81A4UL))) +#define bM4_USART2_CR1_PCE (*((volatile unsigned int*)(0x423A81A8UL))) +#define bM4_USART2_CR1_M (*((volatile unsigned int*)(0x423A81B0UL))) +#define bM4_USART2_CR1_OVER8 (*((volatile unsigned int*)(0x423A81BCUL))) +#define bM4_USART2_CR1_CPE (*((volatile unsigned int*)(0x423A81C0UL))) +#define bM4_USART2_CR1_CFE (*((volatile unsigned int*)(0x423A81C4UL))) +#define bM4_USART2_CR1_CORE (*((volatile unsigned int*)(0x423A81CCUL))) +#define bM4_USART2_CR1_CRTOF (*((volatile unsigned int*)(0x423A81D0UL))) +#define bM4_USART2_CR1_MS (*((volatile unsigned int*)(0x423A81E0UL))) +#define bM4_USART2_CR1_ML (*((volatile unsigned int*)(0x423A81F0UL))) +#define bM4_USART2_CR1_FBME (*((volatile unsigned int*)(0x423A81F4UL))) +#define bM4_USART2_CR1_NFE (*((volatile unsigned int*)(0x423A81F8UL))) +#define bM4_USART2_CR1_SBS (*((volatile unsigned int*)(0x423A81FCUL))) +#define bM4_USART2_CR2_MPE (*((volatile unsigned int*)(0x423A8200UL))) +#define bM4_USART2_CR2_CLKC0 (*((volatile unsigned int*)(0x423A822CUL))) +#define bM4_USART2_CR2_CLKC1 (*((volatile unsigned int*)(0x423A8230UL))) +#define bM4_USART2_CR2_STOP (*((volatile unsigned int*)(0x423A8234UL))) +#define bM4_USART2_CR3_SCEN (*((volatile unsigned int*)(0x423A8294UL))) +#define bM4_USART2_CR3_CTSE (*((volatile unsigned int*)(0x423A82A4UL))) +#define bM4_USART2_CR3_BCN0 (*((volatile unsigned int*)(0x423A82D4UL))) +#define bM4_USART2_CR3_BCN1 (*((volatile unsigned int*)(0x423A82D8UL))) +#define bM4_USART2_CR3_BCN2 (*((volatile unsigned int*)(0x423A82DCUL))) +#define bM4_USART2_PR_PSC0 (*((volatile unsigned int*)(0x423A8300UL))) +#define bM4_USART2_PR_PSC1 (*((volatile unsigned int*)(0x423A8304UL))) +#define bM4_USART3_SR_PE (*((volatile unsigned int*)(0x42420000UL))) +#define bM4_USART3_SR_FE (*((volatile unsigned int*)(0x42420004UL))) +#define bM4_USART3_SR_ORE (*((volatile unsigned int*)(0x4242000CUL))) +#define bM4_USART3_SR_RXNE (*((volatile unsigned int*)(0x42420014UL))) +#define bM4_USART3_SR_TC (*((volatile unsigned int*)(0x42420018UL))) +#define bM4_USART3_SR_TXE (*((volatile unsigned int*)(0x4242001CUL))) +#define bM4_USART3_SR_RTOF (*((volatile unsigned int*)(0x42420020UL))) +#define bM4_USART3_SR_MPB (*((volatile unsigned int*)(0x42420040UL))) +#define bM4_USART3_DR_TDR0 (*((volatile unsigned int*)(0x42420080UL))) +#define bM4_USART3_DR_TDR1 (*((volatile unsigned int*)(0x42420084UL))) +#define bM4_USART3_DR_TDR2 (*((volatile unsigned int*)(0x42420088UL))) +#define bM4_USART3_DR_TDR3 (*((volatile unsigned int*)(0x4242008CUL))) +#define bM4_USART3_DR_TDR4 (*((volatile unsigned int*)(0x42420090UL))) +#define bM4_USART3_DR_TDR5 (*((volatile unsigned int*)(0x42420094UL))) +#define bM4_USART3_DR_TDR6 (*((volatile unsigned int*)(0x42420098UL))) +#define bM4_USART3_DR_TDR7 (*((volatile unsigned int*)(0x4242009CUL))) +#define bM4_USART3_DR_TDR8 (*((volatile unsigned int*)(0x424200A0UL))) +#define bM4_USART3_DR_MPID (*((volatile unsigned int*)(0x424200A4UL))) +#define bM4_USART3_DR_RDR0 (*((volatile unsigned int*)(0x424200C0UL))) +#define bM4_USART3_DR_RDR1 (*((volatile unsigned int*)(0x424200C4UL))) +#define bM4_USART3_DR_RDR2 (*((volatile unsigned int*)(0x424200C8UL))) +#define bM4_USART3_DR_RDR3 (*((volatile unsigned int*)(0x424200CCUL))) +#define bM4_USART3_DR_RDR4 (*((volatile unsigned int*)(0x424200D0UL))) +#define bM4_USART3_DR_RDR5 (*((volatile unsigned int*)(0x424200D4UL))) +#define bM4_USART3_DR_RDR6 (*((volatile unsigned int*)(0x424200D8UL))) +#define bM4_USART3_DR_RDR7 (*((volatile unsigned int*)(0x424200DCUL))) +#define bM4_USART3_DR_RDR8 (*((volatile unsigned int*)(0x424200E0UL))) +#define bM4_USART3_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42420100UL))) +#define bM4_USART3_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42420104UL))) +#define bM4_USART3_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42420108UL))) +#define bM4_USART3_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242010CUL))) +#define bM4_USART3_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42420110UL))) +#define bM4_USART3_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42420114UL))) +#define bM4_USART3_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42420118UL))) +#define bM4_USART3_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42420120UL))) +#define bM4_USART3_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42420124UL))) +#define bM4_USART3_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42420128UL))) +#define bM4_USART3_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242012CUL))) +#define bM4_USART3_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42420130UL))) +#define bM4_USART3_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42420134UL))) +#define bM4_USART3_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42420138UL))) +#define bM4_USART3_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242013CUL))) +#define bM4_USART3_CR1_RTOE (*((volatile unsigned int*)(0x42420180UL))) +#define bM4_USART3_CR1_RTOIE (*((volatile unsigned int*)(0x42420184UL))) +#define bM4_USART3_CR1_RE (*((volatile unsigned int*)(0x42420188UL))) +#define bM4_USART3_CR1_TE (*((volatile unsigned int*)(0x4242018CUL))) +#define bM4_USART3_CR1_SLME (*((volatile unsigned int*)(0x42420190UL))) +#define bM4_USART3_CR1_RIE (*((volatile unsigned int*)(0x42420194UL))) +#define bM4_USART3_CR1_TCIE (*((volatile unsigned int*)(0x42420198UL))) +#define bM4_USART3_CR1_TXEIE (*((volatile unsigned int*)(0x4242019CUL))) +#define bM4_USART3_CR1_PS (*((volatile unsigned int*)(0x424201A4UL))) +#define bM4_USART3_CR1_PCE (*((volatile unsigned int*)(0x424201A8UL))) +#define bM4_USART3_CR1_M (*((volatile unsigned int*)(0x424201B0UL))) +#define bM4_USART3_CR1_OVER8 (*((volatile unsigned int*)(0x424201BCUL))) +#define bM4_USART3_CR1_CPE (*((volatile unsigned int*)(0x424201C0UL))) +#define bM4_USART3_CR1_CFE (*((volatile unsigned int*)(0x424201C4UL))) +#define bM4_USART3_CR1_CORE (*((volatile unsigned int*)(0x424201CCUL))) +#define bM4_USART3_CR1_CRTOF (*((volatile unsigned int*)(0x424201D0UL))) +#define bM4_USART3_CR1_MS (*((volatile unsigned int*)(0x424201E0UL))) +#define bM4_USART3_CR1_ML (*((volatile unsigned int*)(0x424201F0UL))) +#define bM4_USART3_CR1_FBME (*((volatile unsigned int*)(0x424201F4UL))) +#define bM4_USART3_CR1_NFE (*((volatile unsigned int*)(0x424201F8UL))) +#define bM4_USART3_CR1_SBS (*((volatile unsigned int*)(0x424201FCUL))) +#define bM4_USART3_CR2_MPE (*((volatile unsigned int*)(0x42420200UL))) +#define bM4_USART3_CR2_CLKC0 (*((volatile unsigned int*)(0x4242022CUL))) +#define bM4_USART3_CR2_CLKC1 (*((volatile unsigned int*)(0x42420230UL))) +#define bM4_USART3_CR2_STOP (*((volatile unsigned int*)(0x42420234UL))) +#define bM4_USART3_CR3_SCEN (*((volatile unsigned int*)(0x42420294UL))) +#define bM4_USART3_CR3_CTSE (*((volatile unsigned int*)(0x424202A4UL))) +#define bM4_USART3_CR3_BCN0 (*((volatile unsigned int*)(0x424202D4UL))) +#define bM4_USART3_CR3_BCN1 (*((volatile unsigned int*)(0x424202D8UL))) +#define bM4_USART3_CR3_BCN2 (*((volatile unsigned int*)(0x424202DCUL))) +#define bM4_USART3_PR_PSC0 (*((volatile unsigned int*)(0x42420300UL))) +#define bM4_USART3_PR_PSC1 (*((volatile unsigned int*)(0x42420304UL))) +#define bM4_USART4_SR_PE (*((volatile unsigned int*)(0x42428000UL))) +#define bM4_USART4_SR_FE (*((volatile unsigned int*)(0x42428004UL))) +#define bM4_USART4_SR_ORE (*((volatile unsigned int*)(0x4242800CUL))) +#define bM4_USART4_SR_RXNE (*((volatile unsigned int*)(0x42428014UL))) +#define bM4_USART4_SR_TC (*((volatile unsigned int*)(0x42428018UL))) +#define bM4_USART4_SR_TXE (*((volatile unsigned int*)(0x4242801CUL))) +#define bM4_USART4_SR_RTOF (*((volatile unsigned int*)(0x42428020UL))) +#define bM4_USART4_SR_MPB (*((volatile unsigned int*)(0x42428040UL))) +#define bM4_USART4_DR_TDR0 (*((volatile unsigned int*)(0x42428080UL))) +#define bM4_USART4_DR_TDR1 (*((volatile unsigned int*)(0x42428084UL))) +#define bM4_USART4_DR_TDR2 (*((volatile unsigned int*)(0x42428088UL))) +#define bM4_USART4_DR_TDR3 (*((volatile unsigned int*)(0x4242808CUL))) +#define bM4_USART4_DR_TDR4 (*((volatile unsigned int*)(0x42428090UL))) +#define bM4_USART4_DR_TDR5 (*((volatile unsigned int*)(0x42428094UL))) +#define bM4_USART4_DR_TDR6 (*((volatile unsigned int*)(0x42428098UL))) +#define bM4_USART4_DR_TDR7 (*((volatile unsigned int*)(0x4242809CUL))) +#define bM4_USART4_DR_TDR8 (*((volatile unsigned int*)(0x424280A0UL))) +#define bM4_USART4_DR_MPID (*((volatile unsigned int*)(0x424280A4UL))) +#define bM4_USART4_DR_RDR0 (*((volatile unsigned int*)(0x424280C0UL))) +#define bM4_USART4_DR_RDR1 (*((volatile unsigned int*)(0x424280C4UL))) +#define bM4_USART4_DR_RDR2 (*((volatile unsigned int*)(0x424280C8UL))) +#define bM4_USART4_DR_RDR3 (*((volatile unsigned int*)(0x424280CCUL))) +#define bM4_USART4_DR_RDR4 (*((volatile unsigned int*)(0x424280D0UL))) +#define bM4_USART4_DR_RDR5 (*((volatile unsigned int*)(0x424280D4UL))) +#define bM4_USART4_DR_RDR6 (*((volatile unsigned int*)(0x424280D8UL))) +#define bM4_USART4_DR_RDR7 (*((volatile unsigned int*)(0x424280DCUL))) +#define bM4_USART4_DR_RDR8 (*((volatile unsigned int*)(0x424280E0UL))) +#define bM4_USART4_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42428100UL))) +#define bM4_USART4_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42428104UL))) +#define bM4_USART4_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42428108UL))) +#define bM4_USART4_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242810CUL))) +#define bM4_USART4_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42428110UL))) +#define bM4_USART4_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42428114UL))) +#define bM4_USART4_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42428118UL))) +#define bM4_USART4_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42428120UL))) +#define bM4_USART4_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42428124UL))) +#define bM4_USART4_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42428128UL))) +#define bM4_USART4_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242812CUL))) +#define bM4_USART4_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42428130UL))) +#define bM4_USART4_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42428134UL))) +#define bM4_USART4_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42428138UL))) +#define bM4_USART4_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242813CUL))) +#define bM4_USART4_CR1_RTOE (*((volatile unsigned int*)(0x42428180UL))) +#define bM4_USART4_CR1_RTOIE (*((volatile unsigned int*)(0x42428184UL))) +#define bM4_USART4_CR1_RE (*((volatile unsigned int*)(0x42428188UL))) +#define bM4_USART4_CR1_TE (*((volatile unsigned int*)(0x4242818CUL))) +#define bM4_USART4_CR1_SLME (*((volatile unsigned int*)(0x42428190UL))) +#define bM4_USART4_CR1_RIE (*((volatile unsigned int*)(0x42428194UL))) +#define bM4_USART4_CR1_TCIE (*((volatile unsigned int*)(0x42428198UL))) +#define bM4_USART4_CR1_TXEIE (*((volatile unsigned int*)(0x4242819CUL))) +#define bM4_USART4_CR1_PS (*((volatile unsigned int*)(0x424281A4UL))) +#define bM4_USART4_CR1_PCE (*((volatile unsigned int*)(0x424281A8UL))) +#define bM4_USART4_CR1_M (*((volatile unsigned int*)(0x424281B0UL))) +#define bM4_USART4_CR1_OVER8 (*((volatile unsigned int*)(0x424281BCUL))) +#define bM4_USART4_CR1_CPE (*((volatile unsigned int*)(0x424281C0UL))) +#define bM4_USART4_CR1_CFE (*((volatile unsigned int*)(0x424281C4UL))) +#define bM4_USART4_CR1_CORE (*((volatile unsigned int*)(0x424281CCUL))) +#define bM4_USART4_CR1_CRTOF (*((volatile unsigned int*)(0x424281D0UL))) +#define bM4_USART4_CR1_MS (*((volatile unsigned int*)(0x424281E0UL))) +#define bM4_USART4_CR1_ML (*((volatile unsigned int*)(0x424281F0UL))) +#define bM4_USART4_CR1_FBME (*((volatile unsigned int*)(0x424281F4UL))) +#define bM4_USART4_CR1_NFE (*((volatile unsigned int*)(0x424281F8UL))) +#define bM4_USART4_CR1_SBS (*((volatile unsigned int*)(0x424281FCUL))) +#define bM4_USART4_CR2_MPE (*((volatile unsigned int*)(0x42428200UL))) +#define bM4_USART4_CR2_CLKC0 (*((volatile unsigned int*)(0x4242822CUL))) +#define bM4_USART4_CR2_CLKC1 (*((volatile unsigned int*)(0x42428230UL))) +#define bM4_USART4_CR2_STOP (*((volatile unsigned int*)(0x42428234UL))) +#define bM4_USART4_CR3_SCEN (*((volatile unsigned int*)(0x42428294UL))) +#define bM4_USART4_CR3_CTSE (*((volatile unsigned int*)(0x424282A4UL))) +#define bM4_USART4_CR3_BCN0 (*((volatile unsigned int*)(0x424282D4UL))) +#define bM4_USART4_CR3_BCN1 (*((volatile unsigned int*)(0x424282D8UL))) +#define bM4_USART4_CR3_BCN2 (*((volatile unsigned int*)(0x424282DCUL))) +#define bM4_USART4_PR_PSC0 (*((volatile unsigned int*)(0x42428300UL))) +#define bM4_USART4_PR_PSC1 (*((volatile unsigned int*)(0x42428304UL))) +#define bM4_USBFS_GVBUSCFG_VBUSOVEN (*((volatile unsigned int*)(0x43800018UL))) +#define bM4_USBFS_GVBUSCFG_VBUSVAL (*((volatile unsigned int*)(0x4380001CUL))) +#define bM4_USBFS_GAHBCFG_GINTMSK (*((volatile unsigned int*)(0x43800100UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN0 (*((volatile unsigned int*)(0x43800104UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN1 (*((volatile unsigned int*)(0x43800108UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN2 (*((volatile unsigned int*)(0x4380010CUL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN3 (*((volatile unsigned int*)(0x43800110UL))) +#define bM4_USBFS_GAHBCFG_DMAEN (*((volatile unsigned int*)(0x43800114UL))) +#define bM4_USBFS_GAHBCFG_TXFELVL (*((volatile unsigned int*)(0x4380011CUL))) +#define bM4_USBFS_GAHBCFG_PTXFELVL (*((volatile unsigned int*)(0x43800120UL))) +#define bM4_USBFS_GUSBCFG_TOCAL0 (*((volatile unsigned int*)(0x43800180UL))) +#define bM4_USBFS_GUSBCFG_TOCAL1 (*((volatile unsigned int*)(0x43800184UL))) +#define bM4_USBFS_GUSBCFG_TOCAL2 (*((volatile unsigned int*)(0x43800188UL))) +#define bM4_USBFS_GUSBCFG_PHYSEL (*((volatile unsigned int*)(0x43800198UL))) +#define bM4_USBFS_GUSBCFG_TRDT0 (*((volatile unsigned int*)(0x438001A8UL))) +#define bM4_USBFS_GUSBCFG_TRDT1 (*((volatile unsigned int*)(0x438001ACUL))) +#define bM4_USBFS_GUSBCFG_TRDT2 (*((volatile unsigned int*)(0x438001B0UL))) +#define bM4_USBFS_GUSBCFG_TRDT3 (*((volatile unsigned int*)(0x438001B4UL))) +#define bM4_USBFS_GUSBCFG_FHMOD (*((volatile unsigned int*)(0x438001F4UL))) +#define bM4_USBFS_GUSBCFG_FDMOD (*((volatile unsigned int*)(0x438001F8UL))) +#define bM4_USBFS_GRSTCTL_CSRST (*((volatile unsigned int*)(0x43800200UL))) +#define bM4_USBFS_GRSTCTL_HSRST (*((volatile unsigned int*)(0x43800204UL))) +#define bM4_USBFS_GRSTCTL_FCRST (*((volatile unsigned int*)(0x43800208UL))) +#define bM4_USBFS_GRSTCTL_RXFFLSH (*((volatile unsigned int*)(0x43800210UL))) +#define bM4_USBFS_GRSTCTL_TXFFLSH (*((volatile unsigned int*)(0x43800214UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM0 (*((volatile unsigned int*)(0x43800218UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM1 (*((volatile unsigned int*)(0x4380021CUL))) +#define bM4_USBFS_GRSTCTL_TXFNUM2 (*((volatile unsigned int*)(0x43800220UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM3 (*((volatile unsigned int*)(0x43800224UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM4 (*((volatile unsigned int*)(0x43800228UL))) +#define bM4_USBFS_GRSTCTL_DMAREQ (*((volatile unsigned int*)(0x43800278UL))) +#define bM4_USBFS_GRSTCTL_AHBIDL (*((volatile unsigned int*)(0x4380027CUL))) +#define bM4_USBFS_GINTSTS_CMOD (*((volatile unsigned int*)(0x43800280UL))) +#define bM4_USBFS_GINTSTS_MMIS (*((volatile unsigned int*)(0x43800284UL))) +#define bM4_USBFS_GINTSTS_SOF (*((volatile unsigned int*)(0x4380028CUL))) +#define bM4_USBFS_GINTSTS_RXFNE (*((volatile unsigned int*)(0x43800290UL))) +#define bM4_USBFS_GINTSTS_NPTXFE (*((volatile unsigned int*)(0x43800294UL))) +#define bM4_USBFS_GINTSTS_GINAKEFF (*((volatile unsigned int*)(0x43800298UL))) +#define bM4_USBFS_GINTSTS_GONAKEFF (*((volatile unsigned int*)(0x4380029CUL))) +#define bM4_USBFS_GINTSTS_ESUSP (*((volatile unsigned int*)(0x438002A8UL))) +#define bM4_USBFS_GINTSTS_USBSUSP (*((volatile unsigned int*)(0x438002ACUL))) +#define bM4_USBFS_GINTSTS_USBRST (*((volatile unsigned int*)(0x438002B0UL))) +#define bM4_USBFS_GINTSTS_ENUMDNE (*((volatile unsigned int*)(0x438002B4UL))) +#define bM4_USBFS_GINTSTS_ISOODRP (*((volatile unsigned int*)(0x438002B8UL))) +#define bM4_USBFS_GINTSTS_EOPF (*((volatile unsigned int*)(0x438002BCUL))) +#define bM4_USBFS_GINTSTS_IEPINT (*((volatile unsigned int*)(0x438002C8UL))) +#define bM4_USBFS_GINTSTS_OEPINT (*((volatile unsigned int*)(0x438002CCUL))) +#define bM4_USBFS_GINTSTS_IISOIXFR (*((volatile unsigned int*)(0x438002D0UL))) +#define bM4_USBFS_GINTSTS_IPXFR_INCOMPISOOUT (*((volatile unsigned int*)(0x438002D4UL))) +#define bM4_USBFS_GINTSTS_DATAFSUSP (*((volatile unsigned int*)(0x438002D8UL))) +#define bM4_USBFS_GINTSTS_HPRTINT (*((volatile unsigned int*)(0x438002E0UL))) +#define bM4_USBFS_GINTSTS_HCINT (*((volatile unsigned int*)(0x438002E4UL))) +#define bM4_USBFS_GINTSTS_PTXFE (*((volatile unsigned int*)(0x438002E8UL))) +#define bM4_USBFS_GINTSTS_CIDSCHG (*((volatile unsigned int*)(0x438002F0UL))) +#define bM4_USBFS_GINTSTS_DISCINT (*((volatile unsigned int*)(0x438002F4UL))) +#define bM4_USBFS_GINTSTS_VBUSVINT (*((volatile unsigned int*)(0x438002F8UL))) +#define bM4_USBFS_GINTSTS_WKUINT (*((volatile unsigned int*)(0x438002FCUL))) +#define bM4_USBFS_GINTMSK_MMISM (*((volatile unsigned int*)(0x43800304UL))) +#define bM4_USBFS_GINTMSK_SOFM (*((volatile unsigned int*)(0x4380030CUL))) +#define bM4_USBFS_GINTMSK_RXFNEM (*((volatile unsigned int*)(0x43800310UL))) +#define bM4_USBFS_GINTMSK_NPTXFEM (*((volatile unsigned int*)(0x43800314UL))) +#define bM4_USBFS_GINTMSK_GINAKEFFM (*((volatile unsigned int*)(0x43800318UL))) +#define bM4_USBFS_GINTMSK_GONAKEFFM (*((volatile unsigned int*)(0x4380031CUL))) +#define bM4_USBFS_GINTMSK_ESUSPM (*((volatile unsigned int*)(0x43800328UL))) +#define bM4_USBFS_GINTMSK_USBSUSPM (*((volatile unsigned int*)(0x4380032CUL))) +#define bM4_USBFS_GINTMSK_USBRSTM (*((volatile unsigned int*)(0x43800330UL))) +#define bM4_USBFS_GINTMSK_ENUMDNEM (*((volatile unsigned int*)(0x43800334UL))) +#define bM4_USBFS_GINTMSK_ISOODRPM (*((volatile unsigned int*)(0x43800338UL))) +#define bM4_USBFS_GINTMSK_EOPFM (*((volatile unsigned int*)(0x4380033CUL))) +#define bM4_USBFS_GINTMSK_IEPIM (*((volatile unsigned int*)(0x43800348UL))) +#define bM4_USBFS_GINTMSK_OEPIM (*((volatile unsigned int*)(0x4380034CUL))) +#define bM4_USBFS_GINTMSK_IISOIXFRM (*((volatile unsigned int*)(0x43800350UL))) +#define bM4_USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (*((volatile unsigned int*)(0x43800354UL))) +#define bM4_USBFS_GINTMSK_DATAFSUSPM (*((volatile unsigned int*)(0x43800358UL))) +#define bM4_USBFS_GINTMSK_HPRTIM (*((volatile unsigned int*)(0x43800360UL))) +#define bM4_USBFS_GINTMSK_HCIM (*((volatile unsigned int*)(0x43800364UL))) +#define bM4_USBFS_GINTMSK_PTXFEM (*((volatile unsigned int*)(0x43800368UL))) +#define bM4_USBFS_GINTMSK_CIDSCHGM (*((volatile unsigned int*)(0x43800370UL))) +#define bM4_USBFS_GINTMSK_DISCIM (*((volatile unsigned int*)(0x43800374UL))) +#define bM4_USBFS_GINTMSK_VBUSVIM (*((volatile unsigned int*)(0x43800378UL))) +#define bM4_USBFS_GINTMSK_WKUIM (*((volatile unsigned int*)(0x4380037CUL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800380UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800384UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800388UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380038CUL))) +#define bM4_USBFS_GRXSTSR_BCNT0 (*((volatile unsigned int*)(0x43800390UL))) +#define bM4_USBFS_GRXSTSR_BCNT1 (*((volatile unsigned int*)(0x43800394UL))) +#define bM4_USBFS_GRXSTSR_BCNT2 (*((volatile unsigned int*)(0x43800398UL))) +#define bM4_USBFS_GRXSTSR_BCNT3 (*((volatile unsigned int*)(0x4380039CUL))) +#define bM4_USBFS_GRXSTSR_BCNT4 (*((volatile unsigned int*)(0x438003A0UL))) +#define bM4_USBFS_GRXSTSR_BCNT5 (*((volatile unsigned int*)(0x438003A4UL))) +#define bM4_USBFS_GRXSTSR_BCNT6 (*((volatile unsigned int*)(0x438003A8UL))) +#define bM4_USBFS_GRXSTSR_BCNT7 (*((volatile unsigned int*)(0x438003ACUL))) +#define bM4_USBFS_GRXSTSR_BCNT8 (*((volatile unsigned int*)(0x438003B0UL))) +#define bM4_USBFS_GRXSTSR_BCNT9 (*((volatile unsigned int*)(0x438003B4UL))) +#define bM4_USBFS_GRXSTSR_BCNT10 (*((volatile unsigned int*)(0x438003B8UL))) +#define bM4_USBFS_GRXSTSR_DPID0 (*((volatile unsigned int*)(0x438003BCUL))) +#define bM4_USBFS_GRXSTSR_DPID1 (*((volatile unsigned int*)(0x438003C0UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS0 (*((volatile unsigned int*)(0x438003C4UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS1 (*((volatile unsigned int*)(0x438003C8UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS2 (*((volatile unsigned int*)(0x438003CCUL))) +#define bM4_USBFS_GRXSTSR_PKTSTS3 (*((volatile unsigned int*)(0x438003D0UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800400UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800404UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800408UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380040CUL))) +#define bM4_USBFS_GRXSTSP_BCNT0 (*((volatile unsigned int*)(0x43800410UL))) +#define bM4_USBFS_GRXSTSP_BCNT1 (*((volatile unsigned int*)(0x43800414UL))) +#define bM4_USBFS_GRXSTSP_BCNT2 (*((volatile unsigned int*)(0x43800418UL))) +#define bM4_USBFS_GRXSTSP_BCNT3 (*((volatile unsigned int*)(0x4380041CUL))) +#define bM4_USBFS_GRXSTSP_BCNT4 (*((volatile unsigned int*)(0x43800420UL))) +#define bM4_USBFS_GRXSTSP_BCNT5 (*((volatile unsigned int*)(0x43800424UL))) +#define bM4_USBFS_GRXSTSP_BCNT6 (*((volatile unsigned int*)(0x43800428UL))) +#define bM4_USBFS_GRXSTSP_BCNT7 (*((volatile unsigned int*)(0x4380042CUL))) +#define bM4_USBFS_GRXSTSP_BCNT8 (*((volatile unsigned int*)(0x43800430UL))) +#define bM4_USBFS_GRXSTSP_BCNT9 (*((volatile unsigned int*)(0x43800434UL))) +#define bM4_USBFS_GRXSTSP_BCNT10 (*((volatile unsigned int*)(0x43800438UL))) +#define bM4_USBFS_GRXSTSP_DPID0 (*((volatile unsigned int*)(0x4380043CUL))) +#define bM4_USBFS_GRXSTSP_DPID1 (*((volatile unsigned int*)(0x43800440UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS0 (*((volatile unsigned int*)(0x43800444UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS1 (*((volatile unsigned int*)(0x43800448UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS2 (*((volatile unsigned int*)(0x4380044CUL))) +#define bM4_USBFS_GRXSTSP_PKTSTS3 (*((volatile unsigned int*)(0x43800450UL))) +#define bM4_USBFS_GRXFSIZ_RXFD0 (*((volatile unsigned int*)(0x43800480UL))) +#define bM4_USBFS_GRXFSIZ_RXFD1 (*((volatile unsigned int*)(0x43800484UL))) +#define bM4_USBFS_GRXFSIZ_RXFD2 (*((volatile unsigned int*)(0x43800488UL))) +#define bM4_USBFS_GRXFSIZ_RXFD3 (*((volatile unsigned int*)(0x4380048CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD4 (*((volatile unsigned int*)(0x43800490UL))) +#define bM4_USBFS_GRXFSIZ_RXFD5 (*((volatile unsigned int*)(0x43800494UL))) +#define bM4_USBFS_GRXFSIZ_RXFD6 (*((volatile unsigned int*)(0x43800498UL))) +#define bM4_USBFS_GRXFSIZ_RXFD7 (*((volatile unsigned int*)(0x4380049CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD8 (*((volatile unsigned int*)(0x438004A0UL))) +#define bM4_USBFS_GRXFSIZ_RXFD9 (*((volatile unsigned int*)(0x438004A4UL))) +#define bM4_USBFS_GRXFSIZ_RXFD10 (*((volatile unsigned int*)(0x438004A8UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA0 (*((volatile unsigned int*)(0x43800500UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA1 (*((volatile unsigned int*)(0x43800504UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA2 (*((volatile unsigned int*)(0x43800508UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA3 (*((volatile unsigned int*)(0x4380050CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA4 (*((volatile unsigned int*)(0x43800510UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA5 (*((volatile unsigned int*)(0x43800514UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA6 (*((volatile unsigned int*)(0x43800518UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA7 (*((volatile unsigned int*)(0x4380051CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA8 (*((volatile unsigned int*)(0x43800520UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA9 (*((volatile unsigned int*)(0x43800524UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA10 (*((volatile unsigned int*)(0x43800528UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA11 (*((volatile unsigned int*)(0x4380052CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA12 (*((volatile unsigned int*)(0x43800530UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA13 (*((volatile unsigned int*)(0x43800534UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA14 (*((volatile unsigned int*)(0x43800538UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA15 (*((volatile unsigned int*)(0x4380053CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD0 (*((volatile unsigned int*)(0x43800540UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD1 (*((volatile unsigned int*)(0x43800544UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD2 (*((volatile unsigned int*)(0x43800548UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD3 (*((volatile unsigned int*)(0x4380054CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD4 (*((volatile unsigned int*)(0x43800550UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD5 (*((volatile unsigned int*)(0x43800554UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD6 (*((volatile unsigned int*)(0x43800558UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD7 (*((volatile unsigned int*)(0x4380055CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD8 (*((volatile unsigned int*)(0x43800560UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD9 (*((volatile unsigned int*)(0x43800564UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD10 (*((volatile unsigned int*)(0x43800568UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD11 (*((volatile unsigned int*)(0x4380056CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD12 (*((volatile unsigned int*)(0x43800570UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD13 (*((volatile unsigned int*)(0x43800574UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD14 (*((volatile unsigned int*)(0x43800578UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD15 (*((volatile unsigned int*)(0x4380057CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV0 (*((volatile unsigned int*)(0x43800580UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV1 (*((volatile unsigned int*)(0x43800584UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV2 (*((volatile unsigned int*)(0x43800588UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV3 (*((volatile unsigned int*)(0x4380058CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV4 (*((volatile unsigned int*)(0x43800590UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV5 (*((volatile unsigned int*)(0x43800594UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV6 (*((volatile unsigned int*)(0x43800598UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV7 (*((volatile unsigned int*)(0x4380059CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV8 (*((volatile unsigned int*)(0x438005A0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV9 (*((volatile unsigned int*)(0x438005A4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV10 (*((volatile unsigned int*)(0x438005A8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV11 (*((volatile unsigned int*)(0x438005ACUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV12 (*((volatile unsigned int*)(0x438005B0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV13 (*((volatile unsigned int*)(0x438005B4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV14 (*((volatile unsigned int*)(0x438005B8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV15 (*((volatile unsigned int*)(0x438005BCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV0 (*((volatile unsigned int*)(0x438005C0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV1 (*((volatile unsigned int*)(0x438005C4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV2 (*((volatile unsigned int*)(0x438005C8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV3 (*((volatile unsigned int*)(0x438005CCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV4 (*((volatile unsigned int*)(0x438005D0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV5 (*((volatile unsigned int*)(0x438005D4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV6 (*((volatile unsigned int*)(0x438005D8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV7 (*((volatile unsigned int*)(0x438005DCUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP0 (*((volatile unsigned int*)(0x438005E0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP1 (*((volatile unsigned int*)(0x438005E4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP2 (*((volatile unsigned int*)(0x438005E8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP3 (*((volatile unsigned int*)(0x438005ECUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP4 (*((volatile unsigned int*)(0x438005F0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP5 (*((volatile unsigned int*)(0x438005F4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP6 (*((volatile unsigned int*)(0x438005F8UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA0 (*((volatile unsigned int*)(0x43802000UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA1 (*((volatile unsigned int*)(0x43802004UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA2 (*((volatile unsigned int*)(0x43802008UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA3 (*((volatile unsigned int*)(0x4380200CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA4 (*((volatile unsigned int*)(0x43802010UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA5 (*((volatile unsigned int*)(0x43802014UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA6 (*((volatile unsigned int*)(0x43802018UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA7 (*((volatile unsigned int*)(0x4380201CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA8 (*((volatile unsigned int*)(0x43802020UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA9 (*((volatile unsigned int*)(0x43802024UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA10 (*((volatile unsigned int*)(0x43802028UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA11 (*((volatile unsigned int*)(0x4380202CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD0 (*((volatile unsigned int*)(0x43802040UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD1 (*((volatile unsigned int*)(0x43802044UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD2 (*((volatile unsigned int*)(0x43802048UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD3 (*((volatile unsigned int*)(0x4380204CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD4 (*((volatile unsigned int*)(0x43802050UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD5 (*((volatile unsigned int*)(0x43802054UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD6 (*((volatile unsigned int*)(0x43802058UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD7 (*((volatile unsigned int*)(0x4380205CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD8 (*((volatile unsigned int*)(0x43802060UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD9 (*((volatile unsigned int*)(0x43802064UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD10 (*((volatile unsigned int*)(0x43802068UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA0 (*((volatile unsigned int*)(0x43802080UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA1 (*((volatile unsigned int*)(0x43802084UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA2 (*((volatile unsigned int*)(0x43802088UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA3 (*((volatile unsigned int*)(0x4380208CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA4 (*((volatile unsigned int*)(0x43802090UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA5 (*((volatile unsigned int*)(0x43802094UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA6 (*((volatile unsigned int*)(0x43802098UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA7 (*((volatile unsigned int*)(0x4380209CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA8 (*((volatile unsigned int*)(0x438020A0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA9 (*((volatile unsigned int*)(0x438020A4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA10 (*((volatile unsigned int*)(0x438020A8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA11 (*((volatile unsigned int*)(0x438020ACUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD0 (*((volatile unsigned int*)(0x438020C0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD1 (*((volatile unsigned int*)(0x438020C4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD2 (*((volatile unsigned int*)(0x438020C8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD3 (*((volatile unsigned int*)(0x438020CCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD4 (*((volatile unsigned int*)(0x438020D0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD5 (*((volatile unsigned int*)(0x438020D4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD6 (*((volatile unsigned int*)(0x438020D8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD7 (*((volatile unsigned int*)(0x438020DCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD8 (*((volatile unsigned int*)(0x438020E0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD9 (*((volatile unsigned int*)(0x438020E4UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA0 (*((volatile unsigned int*)(0x43802100UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA1 (*((volatile unsigned int*)(0x43802104UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA2 (*((volatile unsigned int*)(0x43802108UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA3 (*((volatile unsigned int*)(0x4380210CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA4 (*((volatile unsigned int*)(0x43802110UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA5 (*((volatile unsigned int*)(0x43802114UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA6 (*((volatile unsigned int*)(0x43802118UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA7 (*((volatile unsigned int*)(0x4380211CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA8 (*((volatile unsigned int*)(0x43802120UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA9 (*((volatile unsigned int*)(0x43802124UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA10 (*((volatile unsigned int*)(0x43802128UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA11 (*((volatile unsigned int*)(0x4380212CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD0 (*((volatile unsigned int*)(0x43802140UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD1 (*((volatile unsigned int*)(0x43802144UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD2 (*((volatile unsigned int*)(0x43802148UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD3 (*((volatile unsigned int*)(0x4380214CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD4 (*((volatile unsigned int*)(0x43802150UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD5 (*((volatile unsigned int*)(0x43802154UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD6 (*((volatile unsigned int*)(0x43802158UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD7 (*((volatile unsigned int*)(0x4380215CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD8 (*((volatile unsigned int*)(0x43802160UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD9 (*((volatile unsigned int*)(0x43802164UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA0 (*((volatile unsigned int*)(0x43802180UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA1 (*((volatile unsigned int*)(0x43802184UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA2 (*((volatile unsigned int*)(0x43802188UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA3 (*((volatile unsigned int*)(0x4380218CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA4 (*((volatile unsigned int*)(0x43802190UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA5 (*((volatile unsigned int*)(0x43802194UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA6 (*((volatile unsigned int*)(0x43802198UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA7 (*((volatile unsigned int*)(0x4380219CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA8 (*((volatile unsigned int*)(0x438021A0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA9 (*((volatile unsigned int*)(0x438021A4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA10 (*((volatile unsigned int*)(0x438021A8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA11 (*((volatile unsigned int*)(0x438021ACUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD0 (*((volatile unsigned int*)(0x438021C0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD1 (*((volatile unsigned int*)(0x438021C4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD2 (*((volatile unsigned int*)(0x438021C8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD3 (*((volatile unsigned int*)(0x438021CCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD4 (*((volatile unsigned int*)(0x438021D0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD5 (*((volatile unsigned int*)(0x438021D4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD6 (*((volatile unsigned int*)(0x438021D8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD7 (*((volatile unsigned int*)(0x438021DCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD8 (*((volatile unsigned int*)(0x438021E0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD9 (*((volatile unsigned int*)(0x438021E4UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA0 (*((volatile unsigned int*)(0x43802200UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA1 (*((volatile unsigned int*)(0x43802204UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA2 (*((volatile unsigned int*)(0x43802208UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA3 (*((volatile unsigned int*)(0x4380220CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA4 (*((volatile unsigned int*)(0x43802210UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA5 (*((volatile unsigned int*)(0x43802214UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA6 (*((volatile unsigned int*)(0x43802218UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA7 (*((volatile unsigned int*)(0x4380221CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA8 (*((volatile unsigned int*)(0x43802220UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA9 (*((volatile unsigned int*)(0x43802224UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA10 (*((volatile unsigned int*)(0x43802228UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA11 (*((volatile unsigned int*)(0x4380222CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD0 (*((volatile unsigned int*)(0x43802240UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD1 (*((volatile unsigned int*)(0x43802244UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD2 (*((volatile unsigned int*)(0x43802248UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD3 (*((volatile unsigned int*)(0x4380224CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD4 (*((volatile unsigned int*)(0x43802250UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD5 (*((volatile unsigned int*)(0x43802254UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD6 (*((volatile unsigned int*)(0x43802258UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD7 (*((volatile unsigned int*)(0x4380225CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD8 (*((volatile unsigned int*)(0x43802260UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD9 (*((volatile unsigned int*)(0x43802264UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA0 (*((volatile unsigned int*)(0x43802280UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA1 (*((volatile unsigned int*)(0x43802284UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA2 (*((volatile unsigned int*)(0x43802288UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA3 (*((volatile unsigned int*)(0x4380228CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA4 (*((volatile unsigned int*)(0x43802290UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA5 (*((volatile unsigned int*)(0x43802294UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA6 (*((volatile unsigned int*)(0x43802298UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA7 (*((volatile unsigned int*)(0x4380229CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA8 (*((volatile unsigned int*)(0x438022A0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA9 (*((volatile unsigned int*)(0x438022A4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA10 (*((volatile unsigned int*)(0x438022A8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA11 (*((volatile unsigned int*)(0x438022ACUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD0 (*((volatile unsigned int*)(0x438022C0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD1 (*((volatile unsigned int*)(0x438022C4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD2 (*((volatile unsigned int*)(0x438022C8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD3 (*((volatile unsigned int*)(0x438022CCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD4 (*((volatile unsigned int*)(0x438022D0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD5 (*((volatile unsigned int*)(0x438022D4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD6 (*((volatile unsigned int*)(0x438022D8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD7 (*((volatile unsigned int*)(0x438022DCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD8 (*((volatile unsigned int*)(0x438022E0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD9 (*((volatile unsigned int*)(0x438022E4UL))) +#define bM4_USBFS_HCFG_FSLSPCS0 (*((volatile unsigned int*)(0x43808000UL))) +#define bM4_USBFS_HCFG_FSLSPCS1 (*((volatile unsigned int*)(0x43808004UL))) +#define bM4_USBFS_HCFG_FSLSS (*((volatile unsigned int*)(0x43808008UL))) +#define bM4_USBFS_HFIR_FRIVL0 (*((volatile unsigned int*)(0x43808080UL))) +#define bM4_USBFS_HFIR_FRIVL1 (*((volatile unsigned int*)(0x43808084UL))) +#define bM4_USBFS_HFIR_FRIVL2 (*((volatile unsigned int*)(0x43808088UL))) +#define bM4_USBFS_HFIR_FRIVL3 (*((volatile unsigned int*)(0x4380808CUL))) +#define bM4_USBFS_HFIR_FRIVL4 (*((volatile unsigned int*)(0x43808090UL))) +#define bM4_USBFS_HFIR_FRIVL5 (*((volatile unsigned int*)(0x43808094UL))) +#define bM4_USBFS_HFIR_FRIVL6 (*((volatile unsigned int*)(0x43808098UL))) +#define bM4_USBFS_HFIR_FRIVL7 (*((volatile unsigned int*)(0x4380809CUL))) +#define bM4_USBFS_HFIR_FRIVL8 (*((volatile unsigned int*)(0x438080A0UL))) +#define bM4_USBFS_HFIR_FRIVL9 (*((volatile unsigned int*)(0x438080A4UL))) +#define bM4_USBFS_HFIR_FRIVL10 (*((volatile unsigned int*)(0x438080A8UL))) +#define bM4_USBFS_HFIR_FRIVL11 (*((volatile unsigned int*)(0x438080ACUL))) +#define bM4_USBFS_HFIR_FRIVL12 (*((volatile unsigned int*)(0x438080B0UL))) +#define bM4_USBFS_HFIR_FRIVL13 (*((volatile unsigned int*)(0x438080B4UL))) +#define bM4_USBFS_HFIR_FRIVL14 (*((volatile unsigned int*)(0x438080B8UL))) +#define bM4_USBFS_HFIR_FRIVL15 (*((volatile unsigned int*)(0x438080BCUL))) +#define bM4_USBFS_HFNUM_FRNUM0 (*((volatile unsigned int*)(0x43808100UL))) +#define bM4_USBFS_HFNUM_FRNUM1 (*((volatile unsigned int*)(0x43808104UL))) +#define bM4_USBFS_HFNUM_FRNUM2 (*((volatile unsigned int*)(0x43808108UL))) +#define bM4_USBFS_HFNUM_FRNUM3 (*((volatile unsigned int*)(0x4380810CUL))) +#define bM4_USBFS_HFNUM_FRNUM4 (*((volatile unsigned int*)(0x43808110UL))) +#define bM4_USBFS_HFNUM_FRNUM5 (*((volatile unsigned int*)(0x43808114UL))) +#define bM4_USBFS_HFNUM_FRNUM6 (*((volatile unsigned int*)(0x43808118UL))) +#define bM4_USBFS_HFNUM_FRNUM7 (*((volatile unsigned int*)(0x4380811CUL))) +#define bM4_USBFS_HFNUM_FRNUM8 (*((volatile unsigned int*)(0x43808120UL))) +#define bM4_USBFS_HFNUM_FRNUM9 (*((volatile unsigned int*)(0x43808124UL))) +#define bM4_USBFS_HFNUM_FRNUM10 (*((volatile unsigned int*)(0x43808128UL))) +#define bM4_USBFS_HFNUM_FRNUM11 (*((volatile unsigned int*)(0x4380812CUL))) +#define bM4_USBFS_HFNUM_FRNUM12 (*((volatile unsigned int*)(0x43808130UL))) +#define bM4_USBFS_HFNUM_FRNUM13 (*((volatile unsigned int*)(0x43808134UL))) +#define bM4_USBFS_HFNUM_FRNUM14 (*((volatile unsigned int*)(0x43808138UL))) +#define bM4_USBFS_HFNUM_FRNUM15 (*((volatile unsigned int*)(0x4380813CUL))) +#define bM4_USBFS_HFNUM_FTREM0 (*((volatile unsigned int*)(0x43808140UL))) +#define bM4_USBFS_HFNUM_FTREM1 (*((volatile unsigned int*)(0x43808144UL))) +#define bM4_USBFS_HFNUM_FTREM2 (*((volatile unsigned int*)(0x43808148UL))) +#define bM4_USBFS_HFNUM_FTREM3 (*((volatile unsigned int*)(0x4380814CUL))) +#define bM4_USBFS_HFNUM_FTREM4 (*((volatile unsigned int*)(0x43808150UL))) +#define bM4_USBFS_HFNUM_FTREM5 (*((volatile unsigned int*)(0x43808154UL))) +#define bM4_USBFS_HFNUM_FTREM6 (*((volatile unsigned int*)(0x43808158UL))) +#define bM4_USBFS_HFNUM_FTREM7 (*((volatile unsigned int*)(0x4380815CUL))) +#define bM4_USBFS_HFNUM_FTREM8 (*((volatile unsigned int*)(0x43808160UL))) +#define bM4_USBFS_HFNUM_FTREM9 (*((volatile unsigned int*)(0x43808164UL))) +#define bM4_USBFS_HFNUM_FTREM10 (*((volatile unsigned int*)(0x43808168UL))) +#define bM4_USBFS_HFNUM_FTREM11 (*((volatile unsigned int*)(0x4380816CUL))) +#define bM4_USBFS_HFNUM_FTREM12 (*((volatile unsigned int*)(0x43808170UL))) +#define bM4_USBFS_HFNUM_FTREM13 (*((volatile unsigned int*)(0x43808174UL))) +#define bM4_USBFS_HFNUM_FTREM14 (*((volatile unsigned int*)(0x43808178UL))) +#define bM4_USBFS_HFNUM_FTREM15 (*((volatile unsigned int*)(0x4380817CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL0 (*((volatile unsigned int*)(0x43808200UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL1 (*((volatile unsigned int*)(0x43808204UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL2 (*((volatile unsigned int*)(0x43808208UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL3 (*((volatile unsigned int*)(0x4380820CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL4 (*((volatile unsigned int*)(0x43808210UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL5 (*((volatile unsigned int*)(0x43808214UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL6 (*((volatile unsigned int*)(0x43808218UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL7 (*((volatile unsigned int*)(0x4380821CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL8 (*((volatile unsigned int*)(0x43808220UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL9 (*((volatile unsigned int*)(0x43808224UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL10 (*((volatile unsigned int*)(0x43808228UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL11 (*((volatile unsigned int*)(0x4380822CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL12 (*((volatile unsigned int*)(0x43808230UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL13 (*((volatile unsigned int*)(0x43808234UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL14 (*((volatile unsigned int*)(0x43808238UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL15 (*((volatile unsigned int*)(0x4380823CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV0 (*((volatile unsigned int*)(0x43808240UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV1 (*((volatile unsigned int*)(0x43808244UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV2 (*((volatile unsigned int*)(0x43808248UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV3 (*((volatile unsigned int*)(0x4380824CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV4 (*((volatile unsigned int*)(0x43808250UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV5 (*((volatile unsigned int*)(0x43808254UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV6 (*((volatile unsigned int*)(0x43808258UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV7 (*((volatile unsigned int*)(0x4380825CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP0 (*((volatile unsigned int*)(0x43808260UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP1 (*((volatile unsigned int*)(0x43808264UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP2 (*((volatile unsigned int*)(0x43808268UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP3 (*((volatile unsigned int*)(0x4380826CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP4 (*((volatile unsigned int*)(0x43808270UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP5 (*((volatile unsigned int*)(0x43808274UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP6 (*((volatile unsigned int*)(0x43808278UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP7 (*((volatile unsigned int*)(0x4380827CUL))) +#define bM4_USBFS_HAINT_HAINT0 (*((volatile unsigned int*)(0x43808280UL))) +#define bM4_USBFS_HAINT_HAINT1 (*((volatile unsigned int*)(0x43808284UL))) +#define bM4_USBFS_HAINT_HAINT2 (*((volatile unsigned int*)(0x43808288UL))) +#define bM4_USBFS_HAINT_HAINT3 (*((volatile unsigned int*)(0x4380828CUL))) +#define bM4_USBFS_HAINT_HAINT4 (*((volatile unsigned int*)(0x43808290UL))) +#define bM4_USBFS_HAINT_HAINT5 (*((volatile unsigned int*)(0x43808294UL))) +#define bM4_USBFS_HAINT_HAINT6 (*((volatile unsigned int*)(0x43808298UL))) +#define bM4_USBFS_HAINT_HAINT7 (*((volatile unsigned int*)(0x4380829CUL))) +#define bM4_USBFS_HAINT_HAINT8 (*((volatile unsigned int*)(0x438082A0UL))) +#define bM4_USBFS_HAINT_HAINT9 (*((volatile unsigned int*)(0x438082A4UL))) +#define bM4_USBFS_HAINT_HAINT10 (*((volatile unsigned int*)(0x438082A8UL))) +#define bM4_USBFS_HAINT_HAINT11 (*((volatile unsigned int*)(0x438082ACUL))) +#define bM4_USBFS_HAINTMSK_HAINTM0 (*((volatile unsigned int*)(0x43808300UL))) +#define bM4_USBFS_HAINTMSK_HAINTM1 (*((volatile unsigned int*)(0x43808304UL))) +#define bM4_USBFS_HAINTMSK_HAINTM2 (*((volatile unsigned int*)(0x43808308UL))) +#define bM4_USBFS_HAINTMSK_HAINTM3 (*((volatile unsigned int*)(0x4380830CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM4 (*((volatile unsigned int*)(0x43808310UL))) +#define bM4_USBFS_HAINTMSK_HAINTM5 (*((volatile unsigned int*)(0x43808314UL))) +#define bM4_USBFS_HAINTMSK_HAINTM6 (*((volatile unsigned int*)(0x43808318UL))) +#define bM4_USBFS_HAINTMSK_HAINTM7 (*((volatile unsigned int*)(0x4380831CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM8 (*((volatile unsigned int*)(0x43808320UL))) +#define bM4_USBFS_HAINTMSK_HAINTM9 (*((volatile unsigned int*)(0x43808324UL))) +#define bM4_USBFS_HAINTMSK_HAINTM10 (*((volatile unsigned int*)(0x43808328UL))) +#define bM4_USBFS_HAINTMSK_HAINTM11 (*((volatile unsigned int*)(0x4380832CUL))) +#define bM4_USBFS_HPRT_PCSTS (*((volatile unsigned int*)(0x43808800UL))) +#define bM4_USBFS_HPRT_PCDET (*((volatile unsigned int*)(0x43808804UL))) +#define bM4_USBFS_HPRT_PENA (*((volatile unsigned int*)(0x43808808UL))) +#define bM4_USBFS_HPRT_PENCHNG (*((volatile unsigned int*)(0x4380880CUL))) +#define bM4_USBFS_HPRT_PRES (*((volatile unsigned int*)(0x43808818UL))) +#define bM4_USBFS_HPRT_PSUSP (*((volatile unsigned int*)(0x4380881CUL))) +#define bM4_USBFS_HPRT_PRST (*((volatile unsigned int*)(0x43808820UL))) +#define bM4_USBFS_HPRT_PLSTS0 (*((volatile unsigned int*)(0x43808828UL))) +#define bM4_USBFS_HPRT_PLSTS1 (*((volatile unsigned int*)(0x4380882CUL))) +#define bM4_USBFS_HPRT_PWPR (*((volatile unsigned int*)(0x43808830UL))) +#define bM4_USBFS_HPRT_PSPD0 (*((volatile unsigned int*)(0x43808844UL))) +#define bM4_USBFS_HPRT_PSPD1 (*((volatile unsigned int*)(0x43808848UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ0 (*((volatile unsigned int*)(0x4380A000UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ1 (*((volatile unsigned int*)(0x4380A004UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ2 (*((volatile unsigned int*)(0x4380A008UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ3 (*((volatile unsigned int*)(0x4380A00CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ4 (*((volatile unsigned int*)(0x4380A010UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ5 (*((volatile unsigned int*)(0x4380A014UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ6 (*((volatile unsigned int*)(0x4380A018UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ7 (*((volatile unsigned int*)(0x4380A01CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ8 (*((volatile unsigned int*)(0x4380A020UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ9 (*((volatile unsigned int*)(0x4380A024UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ10 (*((volatile unsigned int*)(0x4380A028UL))) +#define bM4_USBFS_HCCHAR0_EPNUM0 (*((volatile unsigned int*)(0x4380A02CUL))) +#define bM4_USBFS_HCCHAR0_EPNUM1 (*((volatile unsigned int*)(0x4380A030UL))) +#define bM4_USBFS_HCCHAR0_EPNUM2 (*((volatile unsigned int*)(0x4380A034UL))) +#define bM4_USBFS_HCCHAR0_EPNUM3 (*((volatile unsigned int*)(0x4380A038UL))) +#define bM4_USBFS_HCCHAR0_EPDIR (*((volatile unsigned int*)(0x4380A03CUL))) +#define bM4_USBFS_HCCHAR0_LSDEV (*((volatile unsigned int*)(0x4380A044UL))) +#define bM4_USBFS_HCCHAR0_EPTYP0 (*((volatile unsigned int*)(0x4380A048UL))) +#define bM4_USBFS_HCCHAR0_EPTYP1 (*((volatile unsigned int*)(0x4380A04CUL))) +#define bM4_USBFS_HCCHAR0_DAD0 (*((volatile unsigned int*)(0x4380A058UL))) +#define bM4_USBFS_HCCHAR0_DAD1 (*((volatile unsigned int*)(0x4380A05CUL))) +#define bM4_USBFS_HCCHAR0_DAD2 (*((volatile unsigned int*)(0x4380A060UL))) +#define bM4_USBFS_HCCHAR0_DAD3 (*((volatile unsigned int*)(0x4380A064UL))) +#define bM4_USBFS_HCCHAR0_DAD4 (*((volatile unsigned int*)(0x4380A068UL))) +#define bM4_USBFS_HCCHAR0_DAD5 (*((volatile unsigned int*)(0x4380A06CUL))) +#define bM4_USBFS_HCCHAR0_DAD6 (*((volatile unsigned int*)(0x4380A070UL))) +#define bM4_USBFS_HCCHAR0_ODDFRM (*((volatile unsigned int*)(0x4380A074UL))) +#define bM4_USBFS_HCCHAR0_CHDIS (*((volatile unsigned int*)(0x4380A078UL))) +#define bM4_USBFS_HCCHAR0_CHENA (*((volatile unsigned int*)(0x4380A07CUL))) +#define bM4_USBFS_HCINT0_XFRC (*((volatile unsigned int*)(0x4380A100UL))) +#define bM4_USBFS_HCINT0_CHH (*((volatile unsigned int*)(0x4380A104UL))) +#define bM4_USBFS_HCINT0_STALL (*((volatile unsigned int*)(0x4380A10CUL))) +#define bM4_USBFS_HCINT0_NAK (*((volatile unsigned int*)(0x4380A110UL))) +#define bM4_USBFS_HCINT0_ACK (*((volatile unsigned int*)(0x4380A114UL))) +#define bM4_USBFS_HCINT0_TXERR (*((volatile unsigned int*)(0x4380A11CUL))) +#define bM4_USBFS_HCINT0_BBERR (*((volatile unsigned int*)(0x4380A120UL))) +#define bM4_USBFS_HCINT0_FRMOR (*((volatile unsigned int*)(0x4380A124UL))) +#define bM4_USBFS_HCINT0_DTERR (*((volatile unsigned int*)(0x4380A128UL))) +#define bM4_USBFS_HCINTMSK0_XFRCM (*((volatile unsigned int*)(0x4380A180UL))) +#define bM4_USBFS_HCINTMSK0_CHHM (*((volatile unsigned int*)(0x4380A184UL))) +#define bM4_USBFS_HCINTMSK0_STALLM (*((volatile unsigned int*)(0x4380A18CUL))) +#define bM4_USBFS_HCINTMSK0_NAKM (*((volatile unsigned int*)(0x4380A190UL))) +#define bM4_USBFS_HCINTMSK0_ACKM (*((volatile unsigned int*)(0x4380A194UL))) +#define bM4_USBFS_HCINTMSK0_TXERRM (*((volatile unsigned int*)(0x4380A19CUL))) +#define bM4_USBFS_HCINTMSK0_BBERRM (*((volatile unsigned int*)(0x4380A1A0UL))) +#define bM4_USBFS_HCINTMSK0_FRMORM (*((volatile unsigned int*)(0x4380A1A4UL))) +#define bM4_USBFS_HCINTMSK0_DTERRM (*((volatile unsigned int*)(0x4380A1A8UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x4380A200UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x4380A204UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x4380A208UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4380A20CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x4380A210UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x4380A214UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x4380A218UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ7 (*((volatile unsigned int*)(0x4380A21CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ8 (*((volatile unsigned int*)(0x4380A220UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ9 (*((volatile unsigned int*)(0x4380A224UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ10 (*((volatile unsigned int*)(0x4380A228UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ11 (*((volatile unsigned int*)(0x4380A22CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ12 (*((volatile unsigned int*)(0x4380A230UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ13 (*((volatile unsigned int*)(0x4380A234UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ14 (*((volatile unsigned int*)(0x4380A238UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ15 (*((volatile unsigned int*)(0x4380A23CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ16 (*((volatile unsigned int*)(0x4380A240UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ17 (*((volatile unsigned int*)(0x4380A244UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ18 (*((volatile unsigned int*)(0x4380A248UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4380A24CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x4380A250UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT2 (*((volatile unsigned int*)(0x4380A254UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT3 (*((volatile unsigned int*)(0x4380A258UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT4 (*((volatile unsigned int*)(0x4380A25CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT5 (*((volatile unsigned int*)(0x4380A260UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT6 (*((volatile unsigned int*)(0x4380A264UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT7 (*((volatile unsigned int*)(0x4380A268UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT8 (*((volatile unsigned int*)(0x4380A26CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT9 (*((volatile unsigned int*)(0x4380A270UL))) +#define bM4_USBFS_HCTSIZ0_DPID0 (*((volatile unsigned int*)(0x4380A274UL))) +#define bM4_USBFS_HCTSIZ0_DPID1 (*((volatile unsigned int*)(0x4380A278UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ0 (*((volatile unsigned int*)(0x4380A400UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ1 (*((volatile unsigned int*)(0x4380A404UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ2 (*((volatile unsigned int*)(0x4380A408UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ3 (*((volatile unsigned int*)(0x4380A40CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ4 (*((volatile unsigned int*)(0x4380A410UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ5 (*((volatile unsigned int*)(0x4380A414UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ6 (*((volatile unsigned int*)(0x4380A418UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ7 (*((volatile unsigned int*)(0x4380A41CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ8 (*((volatile unsigned int*)(0x4380A420UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ9 (*((volatile unsigned int*)(0x4380A424UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ10 (*((volatile unsigned int*)(0x4380A428UL))) +#define bM4_USBFS_HCCHAR1_EPNUM0 (*((volatile unsigned int*)(0x4380A42CUL))) +#define bM4_USBFS_HCCHAR1_EPNUM1 (*((volatile unsigned int*)(0x4380A430UL))) +#define bM4_USBFS_HCCHAR1_EPNUM2 (*((volatile unsigned int*)(0x4380A434UL))) +#define bM4_USBFS_HCCHAR1_EPNUM3 (*((volatile unsigned int*)(0x4380A438UL))) +#define bM4_USBFS_HCCHAR1_EPDIR (*((volatile unsigned int*)(0x4380A43CUL))) +#define bM4_USBFS_HCCHAR1_LSDEV (*((volatile unsigned int*)(0x4380A444UL))) +#define bM4_USBFS_HCCHAR1_EPTYP0 (*((volatile unsigned int*)(0x4380A448UL))) +#define bM4_USBFS_HCCHAR1_EPTYP1 (*((volatile unsigned int*)(0x4380A44CUL))) +#define bM4_USBFS_HCCHAR1_DAD0 (*((volatile unsigned int*)(0x4380A458UL))) +#define bM4_USBFS_HCCHAR1_DAD1 (*((volatile unsigned int*)(0x4380A45CUL))) +#define bM4_USBFS_HCCHAR1_DAD2 (*((volatile unsigned int*)(0x4380A460UL))) +#define bM4_USBFS_HCCHAR1_DAD3 (*((volatile unsigned int*)(0x4380A464UL))) +#define bM4_USBFS_HCCHAR1_DAD4 (*((volatile unsigned int*)(0x4380A468UL))) +#define bM4_USBFS_HCCHAR1_DAD5 (*((volatile unsigned int*)(0x4380A46CUL))) +#define bM4_USBFS_HCCHAR1_DAD6 (*((volatile unsigned int*)(0x4380A470UL))) +#define bM4_USBFS_HCCHAR1_ODDFRM (*((volatile unsigned int*)(0x4380A474UL))) +#define bM4_USBFS_HCCHAR1_CHDIS (*((volatile unsigned int*)(0x4380A478UL))) +#define bM4_USBFS_HCCHAR1_CHENA (*((volatile unsigned int*)(0x4380A47CUL))) +#define bM4_USBFS_HCINT1_XFRC (*((volatile unsigned int*)(0x4380A500UL))) +#define bM4_USBFS_HCINT1_CHH (*((volatile unsigned int*)(0x4380A504UL))) +#define bM4_USBFS_HCINT1_STALL (*((volatile unsigned int*)(0x4380A50CUL))) +#define bM4_USBFS_HCINT1_NAK (*((volatile unsigned int*)(0x4380A510UL))) +#define bM4_USBFS_HCINT1_ACK (*((volatile unsigned int*)(0x4380A514UL))) +#define bM4_USBFS_HCINT1_TXERR (*((volatile unsigned int*)(0x4380A51CUL))) +#define bM4_USBFS_HCINT1_BBERR (*((volatile unsigned int*)(0x4380A520UL))) +#define bM4_USBFS_HCINT1_FRMOR (*((volatile unsigned int*)(0x4380A524UL))) +#define bM4_USBFS_HCINT1_DTERR (*((volatile unsigned int*)(0x4380A528UL))) +#define bM4_USBFS_HCINTMSK1_XFRCM (*((volatile unsigned int*)(0x4380A580UL))) +#define bM4_USBFS_HCINTMSK1_CHHM (*((volatile unsigned int*)(0x4380A584UL))) +#define bM4_USBFS_HCINTMSK1_STALLM (*((volatile unsigned int*)(0x4380A58CUL))) +#define bM4_USBFS_HCINTMSK1_NAKM (*((volatile unsigned int*)(0x4380A590UL))) +#define bM4_USBFS_HCINTMSK1_ACKM (*((volatile unsigned int*)(0x4380A594UL))) +#define bM4_USBFS_HCINTMSK1_TXERRM (*((volatile unsigned int*)(0x4380A59CUL))) +#define bM4_USBFS_HCINTMSK1_BBERRM (*((volatile unsigned int*)(0x4380A5A0UL))) +#define bM4_USBFS_HCINTMSK1_FRMORM (*((volatile unsigned int*)(0x4380A5A4UL))) +#define bM4_USBFS_HCINTMSK1_DTERRM (*((volatile unsigned int*)(0x4380A5A8UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x4380A600UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x4380A604UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x4380A608UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4380A60CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x4380A610UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x4380A614UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x4380A618UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4380A61CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x4380A620UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x4380A624UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x4380A628UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4380A62CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x4380A630UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x4380A634UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x4380A638UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4380A63CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x4380A640UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x4380A644UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x4380A648UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4380A64CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x4380A650UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x4380A654UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x4380A658UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4380A65CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x4380A660UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x4380A664UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x4380A668UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4380A66CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x4380A670UL))) +#define bM4_USBFS_HCTSIZ1_DPID0 (*((volatile unsigned int*)(0x4380A674UL))) +#define bM4_USBFS_HCTSIZ1_DPID1 (*((volatile unsigned int*)(0x4380A678UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ0 (*((volatile unsigned int*)(0x4380A800UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ1 (*((volatile unsigned int*)(0x4380A804UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ2 (*((volatile unsigned int*)(0x4380A808UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ3 (*((volatile unsigned int*)(0x4380A80CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ4 (*((volatile unsigned int*)(0x4380A810UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ5 (*((volatile unsigned int*)(0x4380A814UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ6 (*((volatile unsigned int*)(0x4380A818UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ7 (*((volatile unsigned int*)(0x4380A81CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ8 (*((volatile unsigned int*)(0x4380A820UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ9 (*((volatile unsigned int*)(0x4380A824UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ10 (*((volatile unsigned int*)(0x4380A828UL))) +#define bM4_USBFS_HCCHAR2_EPNUM0 (*((volatile unsigned int*)(0x4380A82CUL))) +#define bM4_USBFS_HCCHAR2_EPNUM1 (*((volatile unsigned int*)(0x4380A830UL))) +#define bM4_USBFS_HCCHAR2_EPNUM2 (*((volatile unsigned int*)(0x4380A834UL))) +#define bM4_USBFS_HCCHAR2_EPNUM3 (*((volatile unsigned int*)(0x4380A838UL))) +#define bM4_USBFS_HCCHAR2_EPDIR (*((volatile unsigned int*)(0x4380A83CUL))) +#define bM4_USBFS_HCCHAR2_LSDEV (*((volatile unsigned int*)(0x4380A844UL))) +#define bM4_USBFS_HCCHAR2_EPTYP0 (*((volatile unsigned int*)(0x4380A848UL))) +#define bM4_USBFS_HCCHAR2_EPTYP1 (*((volatile unsigned int*)(0x4380A84CUL))) +#define bM4_USBFS_HCCHAR2_DAD0 (*((volatile unsigned int*)(0x4380A858UL))) +#define bM4_USBFS_HCCHAR2_DAD1 (*((volatile unsigned int*)(0x4380A85CUL))) +#define bM4_USBFS_HCCHAR2_DAD2 (*((volatile unsigned int*)(0x4380A860UL))) +#define bM4_USBFS_HCCHAR2_DAD3 (*((volatile unsigned int*)(0x4380A864UL))) +#define bM4_USBFS_HCCHAR2_DAD4 (*((volatile unsigned int*)(0x4380A868UL))) +#define bM4_USBFS_HCCHAR2_DAD5 (*((volatile unsigned int*)(0x4380A86CUL))) +#define bM4_USBFS_HCCHAR2_DAD6 (*((volatile unsigned int*)(0x4380A870UL))) +#define bM4_USBFS_HCCHAR2_ODDFRM (*((volatile unsigned int*)(0x4380A874UL))) +#define bM4_USBFS_HCCHAR2_CHDIS (*((volatile unsigned int*)(0x4380A878UL))) +#define bM4_USBFS_HCCHAR2_CHENA (*((volatile unsigned int*)(0x4380A87CUL))) +#define bM4_USBFS_HCINT2_XFRC (*((volatile unsigned int*)(0x4380A900UL))) +#define bM4_USBFS_HCINT2_CHH (*((volatile unsigned int*)(0x4380A904UL))) +#define bM4_USBFS_HCINT2_STALL (*((volatile unsigned int*)(0x4380A90CUL))) +#define bM4_USBFS_HCINT2_NAK (*((volatile unsigned int*)(0x4380A910UL))) +#define bM4_USBFS_HCINT2_ACK (*((volatile unsigned int*)(0x4380A914UL))) +#define bM4_USBFS_HCINT2_TXERR (*((volatile unsigned int*)(0x4380A91CUL))) +#define bM4_USBFS_HCINT2_BBERR (*((volatile unsigned int*)(0x4380A920UL))) +#define bM4_USBFS_HCINT2_FRMOR (*((volatile unsigned int*)(0x4380A924UL))) +#define bM4_USBFS_HCINT2_DTERR (*((volatile unsigned int*)(0x4380A928UL))) +#define bM4_USBFS_HCINTMSK2_XFRCM (*((volatile unsigned int*)(0x4380A980UL))) +#define bM4_USBFS_HCINTMSK2_CHHM (*((volatile unsigned int*)(0x4380A984UL))) +#define bM4_USBFS_HCINTMSK2_STALLM (*((volatile unsigned int*)(0x4380A98CUL))) +#define bM4_USBFS_HCINTMSK2_NAKM (*((volatile unsigned int*)(0x4380A990UL))) +#define bM4_USBFS_HCINTMSK2_ACKM (*((volatile unsigned int*)(0x4380A994UL))) +#define bM4_USBFS_HCINTMSK2_TXERRM (*((volatile unsigned int*)(0x4380A99CUL))) +#define bM4_USBFS_HCINTMSK2_BBERRM (*((volatile unsigned int*)(0x4380A9A0UL))) +#define bM4_USBFS_HCINTMSK2_FRMORM (*((volatile unsigned int*)(0x4380A9A4UL))) +#define bM4_USBFS_HCINTMSK2_DTERRM (*((volatile unsigned int*)(0x4380A9A8UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x4380AA00UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x4380AA04UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x4380AA08UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x4380AA0CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x4380AA10UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x4380AA14UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x4380AA18UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x4380AA1CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x4380AA20UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x4380AA24UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x4380AA28UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x4380AA2CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x4380AA30UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x4380AA34UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x4380AA38UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x4380AA3CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x4380AA40UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x4380AA44UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x4380AA48UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x4380AA4CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x4380AA50UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x4380AA54UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x4380AA58UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x4380AA5CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x4380AA60UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x4380AA64UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x4380AA68UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x4380AA6CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x4380AA70UL))) +#define bM4_USBFS_HCTSIZ2_DPID0 (*((volatile unsigned int*)(0x4380AA74UL))) +#define bM4_USBFS_HCTSIZ2_DPID1 (*((volatile unsigned int*)(0x4380AA78UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ0 (*((volatile unsigned int*)(0x4380AC00UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ1 (*((volatile unsigned int*)(0x4380AC04UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ2 (*((volatile unsigned int*)(0x4380AC08UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ3 (*((volatile unsigned int*)(0x4380AC0CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ4 (*((volatile unsigned int*)(0x4380AC10UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ5 (*((volatile unsigned int*)(0x4380AC14UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ6 (*((volatile unsigned int*)(0x4380AC18UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ7 (*((volatile unsigned int*)(0x4380AC1CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ8 (*((volatile unsigned int*)(0x4380AC20UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ9 (*((volatile unsigned int*)(0x4380AC24UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ10 (*((volatile unsigned int*)(0x4380AC28UL))) +#define bM4_USBFS_HCCHAR3_EPNUM0 (*((volatile unsigned int*)(0x4380AC2CUL))) +#define bM4_USBFS_HCCHAR3_EPNUM1 (*((volatile unsigned int*)(0x4380AC30UL))) +#define bM4_USBFS_HCCHAR3_EPNUM2 (*((volatile unsigned int*)(0x4380AC34UL))) +#define bM4_USBFS_HCCHAR3_EPNUM3 (*((volatile unsigned int*)(0x4380AC38UL))) +#define bM4_USBFS_HCCHAR3_EPDIR (*((volatile unsigned int*)(0x4380AC3CUL))) +#define bM4_USBFS_HCCHAR3_LSDEV (*((volatile unsigned int*)(0x4380AC44UL))) +#define bM4_USBFS_HCCHAR3_EPTYP0 (*((volatile unsigned int*)(0x4380AC48UL))) +#define bM4_USBFS_HCCHAR3_EPTYP1 (*((volatile unsigned int*)(0x4380AC4CUL))) +#define bM4_USBFS_HCCHAR3_DAD0 (*((volatile unsigned int*)(0x4380AC58UL))) +#define bM4_USBFS_HCCHAR3_DAD1 (*((volatile unsigned int*)(0x4380AC5CUL))) +#define bM4_USBFS_HCCHAR3_DAD2 (*((volatile unsigned int*)(0x4380AC60UL))) +#define bM4_USBFS_HCCHAR3_DAD3 (*((volatile unsigned int*)(0x4380AC64UL))) +#define bM4_USBFS_HCCHAR3_DAD4 (*((volatile unsigned int*)(0x4380AC68UL))) +#define bM4_USBFS_HCCHAR3_DAD5 (*((volatile unsigned int*)(0x4380AC6CUL))) +#define bM4_USBFS_HCCHAR3_DAD6 (*((volatile unsigned int*)(0x4380AC70UL))) +#define bM4_USBFS_HCCHAR3_ODDFRM (*((volatile unsigned int*)(0x4380AC74UL))) +#define bM4_USBFS_HCCHAR3_CHDIS (*((volatile unsigned int*)(0x4380AC78UL))) +#define bM4_USBFS_HCCHAR3_CHENA (*((volatile unsigned int*)(0x4380AC7CUL))) +#define bM4_USBFS_HCINT3_XFRC (*((volatile unsigned int*)(0x4380AD00UL))) +#define bM4_USBFS_HCINT3_CHH (*((volatile unsigned int*)(0x4380AD04UL))) +#define bM4_USBFS_HCINT3_STALL (*((volatile unsigned int*)(0x4380AD0CUL))) +#define bM4_USBFS_HCINT3_NAK (*((volatile unsigned int*)(0x4380AD10UL))) +#define bM4_USBFS_HCINT3_ACK (*((volatile unsigned int*)(0x4380AD14UL))) +#define bM4_USBFS_HCINT3_TXERR (*((volatile unsigned int*)(0x4380AD1CUL))) +#define bM4_USBFS_HCINT3_BBERR (*((volatile unsigned int*)(0x4380AD20UL))) +#define bM4_USBFS_HCINT3_FRMOR (*((volatile unsigned int*)(0x4380AD24UL))) +#define bM4_USBFS_HCINT3_DTERR (*((volatile unsigned int*)(0x4380AD28UL))) +#define bM4_USBFS_HCINTMSK3_XFRCM (*((volatile unsigned int*)(0x4380AD80UL))) +#define bM4_USBFS_HCINTMSK3_CHHM (*((volatile unsigned int*)(0x4380AD84UL))) +#define bM4_USBFS_HCINTMSK3_STALLM (*((volatile unsigned int*)(0x4380AD8CUL))) +#define bM4_USBFS_HCINTMSK3_NAKM (*((volatile unsigned int*)(0x4380AD90UL))) +#define bM4_USBFS_HCINTMSK3_ACKM (*((volatile unsigned int*)(0x4380AD94UL))) +#define bM4_USBFS_HCINTMSK3_TXERRM (*((volatile unsigned int*)(0x4380AD9CUL))) +#define bM4_USBFS_HCINTMSK3_BBERRM (*((volatile unsigned int*)(0x4380ADA0UL))) +#define bM4_USBFS_HCINTMSK3_FRMORM (*((volatile unsigned int*)(0x4380ADA4UL))) +#define bM4_USBFS_HCINTMSK3_DTERRM (*((volatile unsigned int*)(0x4380ADA8UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x4380AE00UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x4380AE04UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x4380AE08UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x4380AE0CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x4380AE10UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x4380AE14UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x4380AE18UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x4380AE1CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x4380AE20UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x4380AE24UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x4380AE28UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x4380AE2CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x4380AE30UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x4380AE34UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x4380AE38UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x4380AE3CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x4380AE40UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x4380AE44UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x4380AE48UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x4380AE4CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x4380AE50UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x4380AE54UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x4380AE58UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x4380AE5CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x4380AE60UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x4380AE64UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x4380AE68UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x4380AE6CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x4380AE70UL))) +#define bM4_USBFS_HCTSIZ3_DPID0 (*((volatile unsigned int*)(0x4380AE74UL))) +#define bM4_USBFS_HCTSIZ3_DPID1 (*((volatile unsigned int*)(0x4380AE78UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ0 (*((volatile unsigned int*)(0x4380B000UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ1 (*((volatile unsigned int*)(0x4380B004UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ2 (*((volatile unsigned int*)(0x4380B008UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ3 (*((volatile unsigned int*)(0x4380B00CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ4 (*((volatile unsigned int*)(0x4380B010UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ5 (*((volatile unsigned int*)(0x4380B014UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ6 (*((volatile unsigned int*)(0x4380B018UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ7 (*((volatile unsigned int*)(0x4380B01CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ8 (*((volatile unsigned int*)(0x4380B020UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ9 (*((volatile unsigned int*)(0x4380B024UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ10 (*((volatile unsigned int*)(0x4380B028UL))) +#define bM4_USBFS_HCCHAR4_EPNUM0 (*((volatile unsigned int*)(0x4380B02CUL))) +#define bM4_USBFS_HCCHAR4_EPNUM1 (*((volatile unsigned int*)(0x4380B030UL))) +#define bM4_USBFS_HCCHAR4_EPNUM2 (*((volatile unsigned int*)(0x4380B034UL))) +#define bM4_USBFS_HCCHAR4_EPNUM3 (*((volatile unsigned int*)(0x4380B038UL))) +#define bM4_USBFS_HCCHAR4_EPDIR (*((volatile unsigned int*)(0x4380B03CUL))) +#define bM4_USBFS_HCCHAR4_LSDEV (*((volatile unsigned int*)(0x4380B044UL))) +#define bM4_USBFS_HCCHAR4_EPTYP0 (*((volatile unsigned int*)(0x4380B048UL))) +#define bM4_USBFS_HCCHAR4_EPTYP1 (*((volatile unsigned int*)(0x4380B04CUL))) +#define bM4_USBFS_HCCHAR4_DAD0 (*((volatile unsigned int*)(0x4380B058UL))) +#define bM4_USBFS_HCCHAR4_DAD1 (*((volatile unsigned int*)(0x4380B05CUL))) +#define bM4_USBFS_HCCHAR4_DAD2 (*((volatile unsigned int*)(0x4380B060UL))) +#define bM4_USBFS_HCCHAR4_DAD3 (*((volatile unsigned int*)(0x4380B064UL))) +#define bM4_USBFS_HCCHAR4_DAD4 (*((volatile unsigned int*)(0x4380B068UL))) +#define bM4_USBFS_HCCHAR4_DAD5 (*((volatile unsigned int*)(0x4380B06CUL))) +#define bM4_USBFS_HCCHAR4_DAD6 (*((volatile unsigned int*)(0x4380B070UL))) +#define bM4_USBFS_HCCHAR4_ODDFRM (*((volatile unsigned int*)(0x4380B074UL))) +#define bM4_USBFS_HCCHAR4_CHDIS (*((volatile unsigned int*)(0x4380B078UL))) +#define bM4_USBFS_HCCHAR4_CHENA (*((volatile unsigned int*)(0x4380B07CUL))) +#define bM4_USBFS_HCINT4_XFRC (*((volatile unsigned int*)(0x4380B100UL))) +#define bM4_USBFS_HCINT4_CHH (*((volatile unsigned int*)(0x4380B104UL))) +#define bM4_USBFS_HCINT4_STALL (*((volatile unsigned int*)(0x4380B10CUL))) +#define bM4_USBFS_HCINT4_NAK (*((volatile unsigned int*)(0x4380B110UL))) +#define bM4_USBFS_HCINT4_ACK (*((volatile unsigned int*)(0x4380B114UL))) +#define bM4_USBFS_HCINT4_TXERR (*((volatile unsigned int*)(0x4380B11CUL))) +#define bM4_USBFS_HCINT4_BBERR (*((volatile unsigned int*)(0x4380B120UL))) +#define bM4_USBFS_HCINT4_FRMOR (*((volatile unsigned int*)(0x4380B124UL))) +#define bM4_USBFS_HCINT4_DTERR (*((volatile unsigned int*)(0x4380B128UL))) +#define bM4_USBFS_HCINTMSK4_XFRCM (*((volatile unsigned int*)(0x4380B180UL))) +#define bM4_USBFS_HCINTMSK4_CHHM (*((volatile unsigned int*)(0x4380B184UL))) +#define bM4_USBFS_HCINTMSK4_STALLM (*((volatile unsigned int*)(0x4380B18CUL))) +#define bM4_USBFS_HCINTMSK4_NAKM (*((volatile unsigned int*)(0x4380B190UL))) +#define bM4_USBFS_HCINTMSK4_ACKM (*((volatile unsigned int*)(0x4380B194UL))) +#define bM4_USBFS_HCINTMSK4_TXERRM (*((volatile unsigned int*)(0x4380B19CUL))) +#define bM4_USBFS_HCINTMSK4_BBERRM (*((volatile unsigned int*)(0x4380B1A0UL))) +#define bM4_USBFS_HCINTMSK4_FRMORM (*((volatile unsigned int*)(0x4380B1A4UL))) +#define bM4_USBFS_HCINTMSK4_DTERRM (*((volatile unsigned int*)(0x4380B1A8UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x4380B200UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x4380B204UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x4380B208UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4380B20CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x4380B210UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x4380B214UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x4380B218UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4380B21CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x4380B220UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x4380B224UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x4380B228UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4380B22CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x4380B230UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x4380B234UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x4380B238UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4380B23CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x4380B240UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x4380B244UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x4380B248UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4380B24CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x4380B250UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x4380B254UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x4380B258UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4380B25CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x4380B260UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x4380B264UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x4380B268UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4380B26CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x4380B270UL))) +#define bM4_USBFS_HCTSIZ4_DPID0 (*((volatile unsigned int*)(0x4380B274UL))) +#define bM4_USBFS_HCTSIZ4_DPID1 (*((volatile unsigned int*)(0x4380B278UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ0 (*((volatile unsigned int*)(0x4380B400UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ1 (*((volatile unsigned int*)(0x4380B404UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ2 (*((volatile unsigned int*)(0x4380B408UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ3 (*((volatile unsigned int*)(0x4380B40CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ4 (*((volatile unsigned int*)(0x4380B410UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ5 (*((volatile unsigned int*)(0x4380B414UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ6 (*((volatile unsigned int*)(0x4380B418UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ7 (*((volatile unsigned int*)(0x4380B41CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ8 (*((volatile unsigned int*)(0x4380B420UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ9 (*((volatile unsigned int*)(0x4380B424UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ10 (*((volatile unsigned int*)(0x4380B428UL))) +#define bM4_USBFS_HCCHAR5_EPNUM0 (*((volatile unsigned int*)(0x4380B42CUL))) +#define bM4_USBFS_HCCHAR5_EPNUM1 (*((volatile unsigned int*)(0x4380B430UL))) +#define bM4_USBFS_HCCHAR5_EPNUM2 (*((volatile unsigned int*)(0x4380B434UL))) +#define bM4_USBFS_HCCHAR5_EPNUM3 (*((volatile unsigned int*)(0x4380B438UL))) +#define bM4_USBFS_HCCHAR5_EPDIR (*((volatile unsigned int*)(0x4380B43CUL))) +#define bM4_USBFS_HCCHAR5_LSDEV (*((volatile unsigned int*)(0x4380B444UL))) +#define bM4_USBFS_HCCHAR5_EPTYP0 (*((volatile unsigned int*)(0x4380B448UL))) +#define bM4_USBFS_HCCHAR5_EPTYP1 (*((volatile unsigned int*)(0x4380B44CUL))) +#define bM4_USBFS_HCCHAR5_DAD0 (*((volatile unsigned int*)(0x4380B458UL))) +#define bM4_USBFS_HCCHAR5_DAD1 (*((volatile unsigned int*)(0x4380B45CUL))) +#define bM4_USBFS_HCCHAR5_DAD2 (*((volatile unsigned int*)(0x4380B460UL))) +#define bM4_USBFS_HCCHAR5_DAD3 (*((volatile unsigned int*)(0x4380B464UL))) +#define bM4_USBFS_HCCHAR5_DAD4 (*((volatile unsigned int*)(0x4380B468UL))) +#define bM4_USBFS_HCCHAR5_DAD5 (*((volatile unsigned int*)(0x4380B46CUL))) +#define bM4_USBFS_HCCHAR5_DAD6 (*((volatile unsigned int*)(0x4380B470UL))) +#define bM4_USBFS_HCCHAR5_ODDFRM (*((volatile unsigned int*)(0x4380B474UL))) +#define bM4_USBFS_HCCHAR5_CHDIS (*((volatile unsigned int*)(0x4380B478UL))) +#define bM4_USBFS_HCCHAR5_CHENA (*((volatile unsigned int*)(0x4380B47CUL))) +#define bM4_USBFS_HCINT5_XFRC (*((volatile unsigned int*)(0x4380B500UL))) +#define bM4_USBFS_HCINT5_CHH (*((volatile unsigned int*)(0x4380B504UL))) +#define bM4_USBFS_HCINT5_STALL (*((volatile unsigned int*)(0x4380B50CUL))) +#define bM4_USBFS_HCINT5_NAK (*((volatile unsigned int*)(0x4380B510UL))) +#define bM4_USBFS_HCINT5_ACK (*((volatile unsigned int*)(0x4380B514UL))) +#define bM4_USBFS_HCINT5_TXERR (*((volatile unsigned int*)(0x4380B51CUL))) +#define bM4_USBFS_HCINT5_BBERR (*((volatile unsigned int*)(0x4380B520UL))) +#define bM4_USBFS_HCINT5_FRMOR (*((volatile unsigned int*)(0x4380B524UL))) +#define bM4_USBFS_HCINT5_DTERR (*((volatile unsigned int*)(0x4380B528UL))) +#define bM4_USBFS_HCINTMSK5_XFRCM (*((volatile unsigned int*)(0x4380B580UL))) +#define bM4_USBFS_HCINTMSK5_CHHM (*((volatile unsigned int*)(0x4380B584UL))) +#define bM4_USBFS_HCINTMSK5_STALLM (*((volatile unsigned int*)(0x4380B58CUL))) +#define bM4_USBFS_HCINTMSK5_NAKM (*((volatile unsigned int*)(0x4380B590UL))) +#define bM4_USBFS_HCINTMSK5_ACKM (*((volatile unsigned int*)(0x4380B594UL))) +#define bM4_USBFS_HCINTMSK5_TXERRM (*((volatile unsigned int*)(0x4380B59CUL))) +#define bM4_USBFS_HCINTMSK5_BBERRM (*((volatile unsigned int*)(0x4380B5A0UL))) +#define bM4_USBFS_HCINTMSK5_FRMORM (*((volatile unsigned int*)(0x4380B5A4UL))) +#define bM4_USBFS_HCINTMSK5_DTERRM (*((volatile unsigned int*)(0x4380B5A8UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x4380B600UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x4380B604UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x4380B608UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4380B60CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x4380B610UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x4380B614UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x4380B618UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4380B61CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x4380B620UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x4380B624UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x4380B628UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4380B62CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x4380B630UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x4380B634UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x4380B638UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4380B63CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x4380B640UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x4380B644UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x4380B648UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4380B64CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x4380B650UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x4380B654UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x4380B658UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4380B65CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x4380B660UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x4380B664UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x4380B668UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4380B66CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x4380B670UL))) +#define bM4_USBFS_HCTSIZ5_DPID0 (*((volatile unsigned int*)(0x4380B674UL))) +#define bM4_USBFS_HCTSIZ5_DPID1 (*((volatile unsigned int*)(0x4380B678UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ0 (*((volatile unsigned int*)(0x4380B800UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ1 (*((volatile unsigned int*)(0x4380B804UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ2 (*((volatile unsigned int*)(0x4380B808UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ3 (*((volatile unsigned int*)(0x4380B80CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ4 (*((volatile unsigned int*)(0x4380B810UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ5 (*((volatile unsigned int*)(0x4380B814UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ6 (*((volatile unsigned int*)(0x4380B818UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ7 (*((volatile unsigned int*)(0x4380B81CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ8 (*((volatile unsigned int*)(0x4380B820UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ9 (*((volatile unsigned int*)(0x4380B824UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ10 (*((volatile unsigned int*)(0x4380B828UL))) +#define bM4_USBFS_HCCHAR6_EPNUM0 (*((volatile unsigned int*)(0x4380B82CUL))) +#define bM4_USBFS_HCCHAR6_EPNUM1 (*((volatile unsigned int*)(0x4380B830UL))) +#define bM4_USBFS_HCCHAR6_EPNUM2 (*((volatile unsigned int*)(0x4380B834UL))) +#define bM4_USBFS_HCCHAR6_EPNUM3 (*((volatile unsigned int*)(0x4380B838UL))) +#define bM4_USBFS_HCCHAR6_EPDIR (*((volatile unsigned int*)(0x4380B83CUL))) +#define bM4_USBFS_HCCHAR6_LSDEV (*((volatile unsigned int*)(0x4380B844UL))) +#define bM4_USBFS_HCCHAR6_EPTYP0 (*((volatile unsigned int*)(0x4380B848UL))) +#define bM4_USBFS_HCCHAR6_EPTYP1 (*((volatile unsigned int*)(0x4380B84CUL))) +#define bM4_USBFS_HCCHAR6_DAD0 (*((volatile unsigned int*)(0x4380B858UL))) +#define bM4_USBFS_HCCHAR6_DAD1 (*((volatile unsigned int*)(0x4380B85CUL))) +#define bM4_USBFS_HCCHAR6_DAD2 (*((volatile unsigned int*)(0x4380B860UL))) +#define bM4_USBFS_HCCHAR6_DAD3 (*((volatile unsigned int*)(0x4380B864UL))) +#define bM4_USBFS_HCCHAR6_DAD4 (*((volatile unsigned int*)(0x4380B868UL))) +#define bM4_USBFS_HCCHAR6_DAD5 (*((volatile unsigned int*)(0x4380B86CUL))) +#define bM4_USBFS_HCCHAR6_DAD6 (*((volatile unsigned int*)(0x4380B870UL))) +#define bM4_USBFS_HCCHAR6_ODDFRM (*((volatile unsigned int*)(0x4380B874UL))) +#define bM4_USBFS_HCCHAR6_CHDIS (*((volatile unsigned int*)(0x4380B878UL))) +#define bM4_USBFS_HCCHAR6_CHENA (*((volatile unsigned int*)(0x4380B87CUL))) +#define bM4_USBFS_HCINT6_XFRC (*((volatile unsigned int*)(0x4380B900UL))) +#define bM4_USBFS_HCINT6_CHH (*((volatile unsigned int*)(0x4380B904UL))) +#define bM4_USBFS_HCINT6_STALL (*((volatile unsigned int*)(0x4380B90CUL))) +#define bM4_USBFS_HCINT6_NAK (*((volatile unsigned int*)(0x4380B910UL))) +#define bM4_USBFS_HCINT6_ACK (*((volatile unsigned int*)(0x4380B914UL))) +#define bM4_USBFS_HCINT6_TXERR (*((volatile unsigned int*)(0x4380B91CUL))) +#define bM4_USBFS_HCINT6_BBERR (*((volatile unsigned int*)(0x4380B920UL))) +#define bM4_USBFS_HCINT6_FRMOR (*((volatile unsigned int*)(0x4380B924UL))) +#define bM4_USBFS_HCINT6_DTERR (*((volatile unsigned int*)(0x4380B928UL))) +#define bM4_USBFS_HCINTMSK6_XFRCM (*((volatile unsigned int*)(0x4380B980UL))) +#define bM4_USBFS_HCINTMSK6_CHHM (*((volatile unsigned int*)(0x4380B984UL))) +#define bM4_USBFS_HCINTMSK6_STALLM (*((volatile unsigned int*)(0x4380B98CUL))) +#define bM4_USBFS_HCINTMSK6_NAKM (*((volatile unsigned int*)(0x4380B990UL))) +#define bM4_USBFS_HCINTMSK6_ACKM (*((volatile unsigned int*)(0x4380B994UL))) +#define bM4_USBFS_HCINTMSK6_TXERRM (*((volatile unsigned int*)(0x4380B99CUL))) +#define bM4_USBFS_HCINTMSK6_BBERRM (*((volatile unsigned int*)(0x4380B9A0UL))) +#define bM4_USBFS_HCINTMSK6_FRMORM (*((volatile unsigned int*)(0x4380B9A4UL))) +#define bM4_USBFS_HCINTMSK6_DTERRM (*((volatile unsigned int*)(0x4380B9A8UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ0 (*((volatile unsigned int*)(0x4380BA00UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ1 (*((volatile unsigned int*)(0x4380BA04UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ2 (*((volatile unsigned int*)(0x4380BA08UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ3 (*((volatile unsigned int*)(0x4380BA0CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ4 (*((volatile unsigned int*)(0x4380BA10UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ5 (*((volatile unsigned int*)(0x4380BA14UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ6 (*((volatile unsigned int*)(0x4380BA18UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ7 (*((volatile unsigned int*)(0x4380BA1CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ8 (*((volatile unsigned int*)(0x4380BA20UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ9 (*((volatile unsigned int*)(0x4380BA24UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ10 (*((volatile unsigned int*)(0x4380BA28UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ11 (*((volatile unsigned int*)(0x4380BA2CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ12 (*((volatile unsigned int*)(0x4380BA30UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ13 (*((volatile unsigned int*)(0x4380BA34UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ14 (*((volatile unsigned int*)(0x4380BA38UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ15 (*((volatile unsigned int*)(0x4380BA3CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ16 (*((volatile unsigned int*)(0x4380BA40UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ17 (*((volatile unsigned int*)(0x4380BA44UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ18 (*((volatile unsigned int*)(0x4380BA48UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT0 (*((volatile unsigned int*)(0x4380BA4CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT1 (*((volatile unsigned int*)(0x4380BA50UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT2 (*((volatile unsigned int*)(0x4380BA54UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT3 (*((volatile unsigned int*)(0x4380BA58UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT4 (*((volatile unsigned int*)(0x4380BA5CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT5 (*((volatile unsigned int*)(0x4380BA60UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT6 (*((volatile unsigned int*)(0x4380BA64UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT7 (*((volatile unsigned int*)(0x4380BA68UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT8 (*((volatile unsigned int*)(0x4380BA6CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT9 (*((volatile unsigned int*)(0x4380BA70UL))) +#define bM4_USBFS_HCTSIZ6_DPID0 (*((volatile unsigned int*)(0x4380BA74UL))) +#define bM4_USBFS_HCTSIZ6_DPID1 (*((volatile unsigned int*)(0x4380BA78UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ0 (*((volatile unsigned int*)(0x4380BC00UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ1 (*((volatile unsigned int*)(0x4380BC04UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ2 (*((volatile unsigned int*)(0x4380BC08UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ3 (*((volatile unsigned int*)(0x4380BC0CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ4 (*((volatile unsigned int*)(0x4380BC10UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ5 (*((volatile unsigned int*)(0x4380BC14UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ6 (*((volatile unsigned int*)(0x4380BC18UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ7 (*((volatile unsigned int*)(0x4380BC1CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ8 (*((volatile unsigned int*)(0x4380BC20UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ9 (*((volatile unsigned int*)(0x4380BC24UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ10 (*((volatile unsigned int*)(0x4380BC28UL))) +#define bM4_USBFS_HCCHAR7_EPNUM0 (*((volatile unsigned int*)(0x4380BC2CUL))) +#define bM4_USBFS_HCCHAR7_EPNUM1 (*((volatile unsigned int*)(0x4380BC30UL))) +#define bM4_USBFS_HCCHAR7_EPNUM2 (*((volatile unsigned int*)(0x4380BC34UL))) +#define bM4_USBFS_HCCHAR7_EPNUM3 (*((volatile unsigned int*)(0x4380BC38UL))) +#define bM4_USBFS_HCCHAR7_EPDIR (*((volatile unsigned int*)(0x4380BC3CUL))) +#define bM4_USBFS_HCCHAR7_LSDEV (*((volatile unsigned int*)(0x4380BC44UL))) +#define bM4_USBFS_HCCHAR7_EPTYP0 (*((volatile unsigned int*)(0x4380BC48UL))) +#define bM4_USBFS_HCCHAR7_EPTYP1 (*((volatile unsigned int*)(0x4380BC4CUL))) +#define bM4_USBFS_HCCHAR7_DAD0 (*((volatile unsigned int*)(0x4380BC58UL))) +#define bM4_USBFS_HCCHAR7_DAD1 (*((volatile unsigned int*)(0x4380BC5CUL))) +#define bM4_USBFS_HCCHAR7_DAD2 (*((volatile unsigned int*)(0x4380BC60UL))) +#define bM4_USBFS_HCCHAR7_DAD3 (*((volatile unsigned int*)(0x4380BC64UL))) +#define bM4_USBFS_HCCHAR7_DAD4 (*((volatile unsigned int*)(0x4380BC68UL))) +#define bM4_USBFS_HCCHAR7_DAD5 (*((volatile unsigned int*)(0x4380BC6CUL))) +#define bM4_USBFS_HCCHAR7_DAD6 (*((volatile unsigned int*)(0x4380BC70UL))) +#define bM4_USBFS_HCCHAR7_ODDFRM (*((volatile unsigned int*)(0x4380BC74UL))) +#define bM4_USBFS_HCCHAR7_CHDIS (*((volatile unsigned int*)(0x4380BC78UL))) +#define bM4_USBFS_HCCHAR7_CHENA (*((volatile unsigned int*)(0x4380BC7CUL))) +#define bM4_USBFS_HCINT7_XFRC (*((volatile unsigned int*)(0x4380BD00UL))) +#define bM4_USBFS_HCINT7_CHH (*((volatile unsigned int*)(0x4380BD04UL))) +#define bM4_USBFS_HCINT7_STALL (*((volatile unsigned int*)(0x4380BD0CUL))) +#define bM4_USBFS_HCINT7_NAK (*((volatile unsigned int*)(0x4380BD10UL))) +#define bM4_USBFS_HCINT7_ACK (*((volatile unsigned int*)(0x4380BD14UL))) +#define bM4_USBFS_HCINT7_TXERR (*((volatile unsigned int*)(0x4380BD1CUL))) +#define bM4_USBFS_HCINT7_BBERR (*((volatile unsigned int*)(0x4380BD20UL))) +#define bM4_USBFS_HCINT7_FRMOR (*((volatile unsigned int*)(0x4380BD24UL))) +#define bM4_USBFS_HCINT7_DTERR (*((volatile unsigned int*)(0x4380BD28UL))) +#define bM4_USBFS_HCINTMSK7_XFRCM (*((volatile unsigned int*)(0x4380BD80UL))) +#define bM4_USBFS_HCINTMSK7_CHHM (*((volatile unsigned int*)(0x4380BD84UL))) +#define bM4_USBFS_HCINTMSK7_STALLM (*((volatile unsigned int*)(0x4380BD8CUL))) +#define bM4_USBFS_HCINTMSK7_NAKM (*((volatile unsigned int*)(0x4380BD90UL))) +#define bM4_USBFS_HCINTMSK7_ACKM (*((volatile unsigned int*)(0x4380BD94UL))) +#define bM4_USBFS_HCINTMSK7_TXERRM (*((volatile unsigned int*)(0x4380BD9CUL))) +#define bM4_USBFS_HCINTMSK7_BBERRM (*((volatile unsigned int*)(0x4380BDA0UL))) +#define bM4_USBFS_HCINTMSK7_FRMORM (*((volatile unsigned int*)(0x4380BDA4UL))) +#define bM4_USBFS_HCINTMSK7_DTERRM (*((volatile unsigned int*)(0x4380BDA8UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ0 (*((volatile unsigned int*)(0x4380BE00UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ1 (*((volatile unsigned int*)(0x4380BE04UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ2 (*((volatile unsigned int*)(0x4380BE08UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ3 (*((volatile unsigned int*)(0x4380BE0CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ4 (*((volatile unsigned int*)(0x4380BE10UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ5 (*((volatile unsigned int*)(0x4380BE14UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ6 (*((volatile unsigned int*)(0x4380BE18UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ7 (*((volatile unsigned int*)(0x4380BE1CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ8 (*((volatile unsigned int*)(0x4380BE20UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ9 (*((volatile unsigned int*)(0x4380BE24UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ10 (*((volatile unsigned int*)(0x4380BE28UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ11 (*((volatile unsigned int*)(0x4380BE2CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ12 (*((volatile unsigned int*)(0x4380BE30UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ13 (*((volatile unsigned int*)(0x4380BE34UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ14 (*((volatile unsigned int*)(0x4380BE38UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ15 (*((volatile unsigned int*)(0x4380BE3CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ16 (*((volatile unsigned int*)(0x4380BE40UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ17 (*((volatile unsigned int*)(0x4380BE44UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ18 (*((volatile unsigned int*)(0x4380BE48UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT0 (*((volatile unsigned int*)(0x4380BE4CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT1 (*((volatile unsigned int*)(0x4380BE50UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT2 (*((volatile unsigned int*)(0x4380BE54UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT3 (*((volatile unsigned int*)(0x4380BE58UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT4 (*((volatile unsigned int*)(0x4380BE5CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT5 (*((volatile unsigned int*)(0x4380BE60UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT6 (*((volatile unsigned int*)(0x4380BE64UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT7 (*((volatile unsigned int*)(0x4380BE68UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT8 (*((volatile unsigned int*)(0x4380BE6CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT9 (*((volatile unsigned int*)(0x4380BE70UL))) +#define bM4_USBFS_HCTSIZ7_DPID0 (*((volatile unsigned int*)(0x4380BE74UL))) +#define bM4_USBFS_HCTSIZ7_DPID1 (*((volatile unsigned int*)(0x4380BE78UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ0 (*((volatile unsigned int*)(0x4380C000UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ1 (*((volatile unsigned int*)(0x4380C004UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ2 (*((volatile unsigned int*)(0x4380C008UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ3 (*((volatile unsigned int*)(0x4380C00CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ4 (*((volatile unsigned int*)(0x4380C010UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ5 (*((volatile unsigned int*)(0x4380C014UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ6 (*((volatile unsigned int*)(0x4380C018UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ7 (*((volatile unsigned int*)(0x4380C01CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ8 (*((volatile unsigned int*)(0x4380C020UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ9 (*((volatile unsigned int*)(0x4380C024UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ10 (*((volatile unsigned int*)(0x4380C028UL))) +#define bM4_USBFS_HCCHAR8_EPNUM0 (*((volatile unsigned int*)(0x4380C02CUL))) +#define bM4_USBFS_HCCHAR8_EPNUM1 (*((volatile unsigned int*)(0x4380C030UL))) +#define bM4_USBFS_HCCHAR8_EPNUM2 (*((volatile unsigned int*)(0x4380C034UL))) +#define bM4_USBFS_HCCHAR8_EPNUM3 (*((volatile unsigned int*)(0x4380C038UL))) +#define bM4_USBFS_HCCHAR8_EPDIR (*((volatile unsigned int*)(0x4380C03CUL))) +#define bM4_USBFS_HCCHAR8_LSDEV (*((volatile unsigned int*)(0x4380C044UL))) +#define bM4_USBFS_HCCHAR8_EPTYP0 (*((volatile unsigned int*)(0x4380C048UL))) +#define bM4_USBFS_HCCHAR8_EPTYP1 (*((volatile unsigned int*)(0x4380C04CUL))) +#define bM4_USBFS_HCCHAR8_DAD0 (*((volatile unsigned int*)(0x4380C058UL))) +#define bM4_USBFS_HCCHAR8_DAD1 (*((volatile unsigned int*)(0x4380C05CUL))) +#define bM4_USBFS_HCCHAR8_DAD2 (*((volatile unsigned int*)(0x4380C060UL))) +#define bM4_USBFS_HCCHAR8_DAD3 (*((volatile unsigned int*)(0x4380C064UL))) +#define bM4_USBFS_HCCHAR8_DAD4 (*((volatile unsigned int*)(0x4380C068UL))) +#define bM4_USBFS_HCCHAR8_DAD5 (*((volatile unsigned int*)(0x4380C06CUL))) +#define bM4_USBFS_HCCHAR8_DAD6 (*((volatile unsigned int*)(0x4380C070UL))) +#define bM4_USBFS_HCCHAR8_ODDFRM (*((volatile unsigned int*)(0x4380C074UL))) +#define bM4_USBFS_HCCHAR8_CHDIS (*((volatile unsigned int*)(0x4380C078UL))) +#define bM4_USBFS_HCCHAR8_CHENA (*((volatile unsigned int*)(0x4380C07CUL))) +#define bM4_USBFS_HCINT8_XFRC (*((volatile unsigned int*)(0x4380C100UL))) +#define bM4_USBFS_HCINT8_CHH (*((volatile unsigned int*)(0x4380C104UL))) +#define bM4_USBFS_HCINT8_STALL (*((volatile unsigned int*)(0x4380C10CUL))) +#define bM4_USBFS_HCINT8_NAK (*((volatile unsigned int*)(0x4380C110UL))) +#define bM4_USBFS_HCINT8_ACK (*((volatile unsigned int*)(0x4380C114UL))) +#define bM4_USBFS_HCINT8_TXERR (*((volatile unsigned int*)(0x4380C11CUL))) +#define bM4_USBFS_HCINT8_BBERR (*((volatile unsigned int*)(0x4380C120UL))) +#define bM4_USBFS_HCINT8_FRMOR (*((volatile unsigned int*)(0x4380C124UL))) +#define bM4_USBFS_HCINT8_DTERR (*((volatile unsigned int*)(0x4380C128UL))) +#define bM4_USBFS_HCINTMSK8_XFRCM (*((volatile unsigned int*)(0x4380C180UL))) +#define bM4_USBFS_HCINTMSK8_CHHM (*((volatile unsigned int*)(0x4380C184UL))) +#define bM4_USBFS_HCINTMSK8_STALLM (*((volatile unsigned int*)(0x4380C18CUL))) +#define bM4_USBFS_HCINTMSK8_NAKM (*((volatile unsigned int*)(0x4380C190UL))) +#define bM4_USBFS_HCINTMSK8_ACKM (*((volatile unsigned int*)(0x4380C194UL))) +#define bM4_USBFS_HCINTMSK8_TXERRM (*((volatile unsigned int*)(0x4380C19CUL))) +#define bM4_USBFS_HCINTMSK8_BBERRM (*((volatile unsigned int*)(0x4380C1A0UL))) +#define bM4_USBFS_HCINTMSK8_FRMORM (*((volatile unsigned int*)(0x4380C1A4UL))) +#define bM4_USBFS_HCINTMSK8_DTERRM (*((volatile unsigned int*)(0x4380C1A8UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ0 (*((volatile unsigned int*)(0x4380C200UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ1 (*((volatile unsigned int*)(0x4380C204UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ2 (*((volatile unsigned int*)(0x4380C208UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ3 (*((volatile unsigned int*)(0x4380C20CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ4 (*((volatile unsigned int*)(0x4380C210UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ5 (*((volatile unsigned int*)(0x4380C214UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ6 (*((volatile unsigned int*)(0x4380C218UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ7 (*((volatile unsigned int*)(0x4380C21CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ8 (*((volatile unsigned int*)(0x4380C220UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ9 (*((volatile unsigned int*)(0x4380C224UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ10 (*((volatile unsigned int*)(0x4380C228UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ11 (*((volatile unsigned int*)(0x4380C22CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ12 (*((volatile unsigned int*)(0x4380C230UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ13 (*((volatile unsigned int*)(0x4380C234UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ14 (*((volatile unsigned int*)(0x4380C238UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ15 (*((volatile unsigned int*)(0x4380C23CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ16 (*((volatile unsigned int*)(0x4380C240UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ17 (*((volatile unsigned int*)(0x4380C244UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ18 (*((volatile unsigned int*)(0x4380C248UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT0 (*((volatile unsigned int*)(0x4380C24CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT1 (*((volatile unsigned int*)(0x4380C250UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT2 (*((volatile unsigned int*)(0x4380C254UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT3 (*((volatile unsigned int*)(0x4380C258UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT4 (*((volatile unsigned int*)(0x4380C25CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT5 (*((volatile unsigned int*)(0x4380C260UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT6 (*((volatile unsigned int*)(0x4380C264UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT7 (*((volatile unsigned int*)(0x4380C268UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT8 (*((volatile unsigned int*)(0x4380C26CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT9 (*((volatile unsigned int*)(0x4380C270UL))) +#define bM4_USBFS_HCTSIZ8_DPID0 (*((volatile unsigned int*)(0x4380C274UL))) +#define bM4_USBFS_HCTSIZ8_DPID1 (*((volatile unsigned int*)(0x4380C278UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ0 (*((volatile unsigned int*)(0x4380C400UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ1 (*((volatile unsigned int*)(0x4380C404UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ2 (*((volatile unsigned int*)(0x4380C408UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ3 (*((volatile unsigned int*)(0x4380C40CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ4 (*((volatile unsigned int*)(0x4380C410UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ5 (*((volatile unsigned int*)(0x4380C414UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ6 (*((volatile unsigned int*)(0x4380C418UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ7 (*((volatile unsigned int*)(0x4380C41CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ8 (*((volatile unsigned int*)(0x4380C420UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ9 (*((volatile unsigned int*)(0x4380C424UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ10 (*((volatile unsigned int*)(0x4380C428UL))) +#define bM4_USBFS_HCCHAR9_EPNUM0 (*((volatile unsigned int*)(0x4380C42CUL))) +#define bM4_USBFS_HCCHAR9_EPNUM1 (*((volatile unsigned int*)(0x4380C430UL))) +#define bM4_USBFS_HCCHAR9_EPNUM2 (*((volatile unsigned int*)(0x4380C434UL))) +#define bM4_USBFS_HCCHAR9_EPNUM3 (*((volatile unsigned int*)(0x4380C438UL))) +#define bM4_USBFS_HCCHAR9_EPDIR (*((volatile unsigned int*)(0x4380C43CUL))) +#define bM4_USBFS_HCCHAR9_LSDEV (*((volatile unsigned int*)(0x4380C444UL))) +#define bM4_USBFS_HCCHAR9_EPTYP0 (*((volatile unsigned int*)(0x4380C448UL))) +#define bM4_USBFS_HCCHAR9_EPTYP1 (*((volatile unsigned int*)(0x4380C44CUL))) +#define bM4_USBFS_HCCHAR9_DAD0 (*((volatile unsigned int*)(0x4380C458UL))) +#define bM4_USBFS_HCCHAR9_DAD1 (*((volatile unsigned int*)(0x4380C45CUL))) +#define bM4_USBFS_HCCHAR9_DAD2 (*((volatile unsigned int*)(0x4380C460UL))) +#define bM4_USBFS_HCCHAR9_DAD3 (*((volatile unsigned int*)(0x4380C464UL))) +#define bM4_USBFS_HCCHAR9_DAD4 (*((volatile unsigned int*)(0x4380C468UL))) +#define bM4_USBFS_HCCHAR9_DAD5 (*((volatile unsigned int*)(0x4380C46CUL))) +#define bM4_USBFS_HCCHAR9_DAD6 (*((volatile unsigned int*)(0x4380C470UL))) +#define bM4_USBFS_HCCHAR9_ODDFRM (*((volatile unsigned int*)(0x4380C474UL))) +#define bM4_USBFS_HCCHAR9_CHDIS (*((volatile unsigned int*)(0x4380C478UL))) +#define bM4_USBFS_HCCHAR9_CHENA (*((volatile unsigned int*)(0x4380C47CUL))) +#define bM4_USBFS_HCINT9_XFRC (*((volatile unsigned int*)(0x4380C500UL))) +#define bM4_USBFS_HCINT9_CHH (*((volatile unsigned int*)(0x4380C504UL))) +#define bM4_USBFS_HCINT9_STALL (*((volatile unsigned int*)(0x4380C50CUL))) +#define bM4_USBFS_HCINT9_NAK (*((volatile unsigned int*)(0x4380C510UL))) +#define bM4_USBFS_HCINT9_ACK (*((volatile unsigned int*)(0x4380C514UL))) +#define bM4_USBFS_HCINT9_TXERR (*((volatile unsigned int*)(0x4380C51CUL))) +#define bM4_USBFS_HCINT9_BBERR (*((volatile unsigned int*)(0x4380C520UL))) +#define bM4_USBFS_HCINT9_FRMOR (*((volatile unsigned int*)(0x4380C524UL))) +#define bM4_USBFS_HCINT9_DTERR (*((volatile unsigned int*)(0x4380C528UL))) +#define bM4_USBFS_HCINTMSK9_XFRCM (*((volatile unsigned int*)(0x4380C580UL))) +#define bM4_USBFS_HCINTMSK9_CHHM (*((volatile unsigned int*)(0x4380C584UL))) +#define bM4_USBFS_HCINTMSK9_STALLM (*((volatile unsigned int*)(0x4380C58CUL))) +#define bM4_USBFS_HCINTMSK9_NAKM (*((volatile unsigned int*)(0x4380C590UL))) +#define bM4_USBFS_HCINTMSK9_ACKM (*((volatile unsigned int*)(0x4380C594UL))) +#define bM4_USBFS_HCINTMSK9_TXERRM (*((volatile unsigned int*)(0x4380C59CUL))) +#define bM4_USBFS_HCINTMSK9_BBERRM (*((volatile unsigned int*)(0x4380C5A0UL))) +#define bM4_USBFS_HCINTMSK9_FRMORM (*((volatile unsigned int*)(0x4380C5A4UL))) +#define bM4_USBFS_HCINTMSK9_DTERRM (*((volatile unsigned int*)(0x4380C5A8UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ0 (*((volatile unsigned int*)(0x4380C600UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ1 (*((volatile unsigned int*)(0x4380C604UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ2 (*((volatile unsigned int*)(0x4380C608UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ3 (*((volatile unsigned int*)(0x4380C60CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ4 (*((volatile unsigned int*)(0x4380C610UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ5 (*((volatile unsigned int*)(0x4380C614UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ6 (*((volatile unsigned int*)(0x4380C618UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ7 (*((volatile unsigned int*)(0x4380C61CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ8 (*((volatile unsigned int*)(0x4380C620UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ9 (*((volatile unsigned int*)(0x4380C624UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ10 (*((volatile unsigned int*)(0x4380C628UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ11 (*((volatile unsigned int*)(0x4380C62CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ12 (*((volatile unsigned int*)(0x4380C630UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ13 (*((volatile unsigned int*)(0x4380C634UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ14 (*((volatile unsigned int*)(0x4380C638UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ15 (*((volatile unsigned int*)(0x4380C63CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ16 (*((volatile unsigned int*)(0x4380C640UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ17 (*((volatile unsigned int*)(0x4380C644UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ18 (*((volatile unsigned int*)(0x4380C648UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT0 (*((volatile unsigned int*)(0x4380C64CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT1 (*((volatile unsigned int*)(0x4380C650UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT2 (*((volatile unsigned int*)(0x4380C654UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT3 (*((volatile unsigned int*)(0x4380C658UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT4 (*((volatile unsigned int*)(0x4380C65CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT5 (*((volatile unsigned int*)(0x4380C660UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT6 (*((volatile unsigned int*)(0x4380C664UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT7 (*((volatile unsigned int*)(0x4380C668UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT8 (*((volatile unsigned int*)(0x4380C66CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT9 (*((volatile unsigned int*)(0x4380C670UL))) +#define bM4_USBFS_HCTSIZ9_DPID0 (*((volatile unsigned int*)(0x4380C674UL))) +#define bM4_USBFS_HCTSIZ9_DPID1 (*((volatile unsigned int*)(0x4380C678UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ0 (*((volatile unsigned int*)(0x4380C800UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ1 (*((volatile unsigned int*)(0x4380C804UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ2 (*((volatile unsigned int*)(0x4380C808UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ3 (*((volatile unsigned int*)(0x4380C80CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ4 (*((volatile unsigned int*)(0x4380C810UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ5 (*((volatile unsigned int*)(0x4380C814UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ6 (*((volatile unsigned int*)(0x4380C818UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ7 (*((volatile unsigned int*)(0x4380C81CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ8 (*((volatile unsigned int*)(0x4380C820UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ9 (*((volatile unsigned int*)(0x4380C824UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ10 (*((volatile unsigned int*)(0x4380C828UL))) +#define bM4_USBFS_HCCHAR10_EPNUM0 (*((volatile unsigned int*)(0x4380C82CUL))) +#define bM4_USBFS_HCCHAR10_EPNUM1 (*((volatile unsigned int*)(0x4380C830UL))) +#define bM4_USBFS_HCCHAR10_EPNUM2 (*((volatile unsigned int*)(0x4380C834UL))) +#define bM4_USBFS_HCCHAR10_EPNUM3 (*((volatile unsigned int*)(0x4380C838UL))) +#define bM4_USBFS_HCCHAR10_EPDIR (*((volatile unsigned int*)(0x4380C83CUL))) +#define bM4_USBFS_HCCHAR10_LSDEV (*((volatile unsigned int*)(0x4380C844UL))) +#define bM4_USBFS_HCCHAR10_EPTYP0 (*((volatile unsigned int*)(0x4380C848UL))) +#define bM4_USBFS_HCCHAR10_EPTYP1 (*((volatile unsigned int*)(0x4380C84CUL))) +#define bM4_USBFS_HCCHAR10_DAD0 (*((volatile unsigned int*)(0x4380C858UL))) +#define bM4_USBFS_HCCHAR10_DAD1 (*((volatile unsigned int*)(0x4380C85CUL))) +#define bM4_USBFS_HCCHAR10_DAD2 (*((volatile unsigned int*)(0x4380C860UL))) +#define bM4_USBFS_HCCHAR10_DAD3 (*((volatile unsigned int*)(0x4380C864UL))) +#define bM4_USBFS_HCCHAR10_DAD4 (*((volatile unsigned int*)(0x4380C868UL))) +#define bM4_USBFS_HCCHAR10_DAD5 (*((volatile unsigned int*)(0x4380C86CUL))) +#define bM4_USBFS_HCCHAR10_DAD6 (*((volatile unsigned int*)(0x4380C870UL))) +#define bM4_USBFS_HCCHAR10_ODDFRM (*((volatile unsigned int*)(0x4380C874UL))) +#define bM4_USBFS_HCCHAR10_CHDIS (*((volatile unsigned int*)(0x4380C878UL))) +#define bM4_USBFS_HCCHAR10_CHENA (*((volatile unsigned int*)(0x4380C87CUL))) +#define bM4_USBFS_HCINT10_XFRC (*((volatile unsigned int*)(0x4380C900UL))) +#define bM4_USBFS_HCINT10_CHH (*((volatile unsigned int*)(0x4380C904UL))) +#define bM4_USBFS_HCINT10_STALL (*((volatile unsigned int*)(0x4380C90CUL))) +#define bM4_USBFS_HCINT10_NAK (*((volatile unsigned int*)(0x4380C910UL))) +#define bM4_USBFS_HCINT10_ACK (*((volatile unsigned int*)(0x4380C914UL))) +#define bM4_USBFS_HCINT10_TXERR (*((volatile unsigned int*)(0x4380C91CUL))) +#define bM4_USBFS_HCINT10_BBERR (*((volatile unsigned int*)(0x4380C920UL))) +#define bM4_USBFS_HCINT10_FRMOR (*((volatile unsigned int*)(0x4380C924UL))) +#define bM4_USBFS_HCINT10_DTERR (*((volatile unsigned int*)(0x4380C928UL))) +#define bM4_USBFS_HCINTMSK10_XFRCM (*((volatile unsigned int*)(0x4380C980UL))) +#define bM4_USBFS_HCINTMSK10_CHHM (*((volatile unsigned int*)(0x4380C984UL))) +#define bM4_USBFS_HCINTMSK10_STALLM (*((volatile unsigned int*)(0x4380C98CUL))) +#define bM4_USBFS_HCINTMSK10_NAKM (*((volatile unsigned int*)(0x4380C990UL))) +#define bM4_USBFS_HCINTMSK10_ACKM (*((volatile unsigned int*)(0x4380C994UL))) +#define bM4_USBFS_HCINTMSK10_TXERRM (*((volatile unsigned int*)(0x4380C99CUL))) +#define bM4_USBFS_HCINTMSK10_BBERRM (*((volatile unsigned int*)(0x4380C9A0UL))) +#define bM4_USBFS_HCINTMSK10_FRMORM (*((volatile unsigned int*)(0x4380C9A4UL))) +#define bM4_USBFS_HCINTMSK10_DTERRM (*((volatile unsigned int*)(0x4380C9A8UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ0 (*((volatile unsigned int*)(0x4380CA00UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ1 (*((volatile unsigned int*)(0x4380CA04UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ2 (*((volatile unsigned int*)(0x4380CA08UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ3 (*((volatile unsigned int*)(0x4380CA0CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ4 (*((volatile unsigned int*)(0x4380CA10UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ5 (*((volatile unsigned int*)(0x4380CA14UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ6 (*((volatile unsigned int*)(0x4380CA18UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ7 (*((volatile unsigned int*)(0x4380CA1CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ8 (*((volatile unsigned int*)(0x4380CA20UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ9 (*((volatile unsigned int*)(0x4380CA24UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ10 (*((volatile unsigned int*)(0x4380CA28UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ11 (*((volatile unsigned int*)(0x4380CA2CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ12 (*((volatile unsigned int*)(0x4380CA30UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ13 (*((volatile unsigned int*)(0x4380CA34UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ14 (*((volatile unsigned int*)(0x4380CA38UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ15 (*((volatile unsigned int*)(0x4380CA3CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ16 (*((volatile unsigned int*)(0x4380CA40UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ17 (*((volatile unsigned int*)(0x4380CA44UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ18 (*((volatile unsigned int*)(0x4380CA48UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT0 (*((volatile unsigned int*)(0x4380CA4CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT1 (*((volatile unsigned int*)(0x4380CA50UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT2 (*((volatile unsigned int*)(0x4380CA54UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT3 (*((volatile unsigned int*)(0x4380CA58UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT4 (*((volatile unsigned int*)(0x4380CA5CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT5 (*((volatile unsigned int*)(0x4380CA60UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT6 (*((volatile unsigned int*)(0x4380CA64UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT7 (*((volatile unsigned int*)(0x4380CA68UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT8 (*((volatile unsigned int*)(0x4380CA6CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT9 (*((volatile unsigned int*)(0x4380CA70UL))) +#define bM4_USBFS_HCTSIZ10_DPID0 (*((volatile unsigned int*)(0x4380CA74UL))) +#define bM4_USBFS_HCTSIZ10_DPID1 (*((volatile unsigned int*)(0x4380CA78UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ0 (*((volatile unsigned int*)(0x4380CC00UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ1 (*((volatile unsigned int*)(0x4380CC04UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ2 (*((volatile unsigned int*)(0x4380CC08UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ3 (*((volatile unsigned int*)(0x4380CC0CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ4 (*((volatile unsigned int*)(0x4380CC10UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ5 (*((volatile unsigned int*)(0x4380CC14UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ6 (*((volatile unsigned int*)(0x4380CC18UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ7 (*((volatile unsigned int*)(0x4380CC1CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ8 (*((volatile unsigned int*)(0x4380CC20UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ9 (*((volatile unsigned int*)(0x4380CC24UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ10 (*((volatile unsigned int*)(0x4380CC28UL))) +#define bM4_USBFS_HCCHAR11_EPNUM0 (*((volatile unsigned int*)(0x4380CC2CUL))) +#define bM4_USBFS_HCCHAR11_EPNUM1 (*((volatile unsigned int*)(0x4380CC30UL))) +#define bM4_USBFS_HCCHAR11_EPNUM2 (*((volatile unsigned int*)(0x4380CC34UL))) +#define bM4_USBFS_HCCHAR11_EPNUM3 (*((volatile unsigned int*)(0x4380CC38UL))) +#define bM4_USBFS_HCCHAR11_EPDIR (*((volatile unsigned int*)(0x4380CC3CUL))) +#define bM4_USBFS_HCCHAR11_LSDEV (*((volatile unsigned int*)(0x4380CC44UL))) +#define bM4_USBFS_HCCHAR11_EPTYP0 (*((volatile unsigned int*)(0x4380CC48UL))) +#define bM4_USBFS_HCCHAR11_EPTYP1 (*((volatile unsigned int*)(0x4380CC4CUL))) +#define bM4_USBFS_HCCHAR11_DAD0 (*((volatile unsigned int*)(0x4380CC58UL))) +#define bM4_USBFS_HCCHAR11_DAD1 (*((volatile unsigned int*)(0x4380CC5CUL))) +#define bM4_USBFS_HCCHAR11_DAD2 (*((volatile unsigned int*)(0x4380CC60UL))) +#define bM4_USBFS_HCCHAR11_DAD3 (*((volatile unsigned int*)(0x4380CC64UL))) +#define bM4_USBFS_HCCHAR11_DAD4 (*((volatile unsigned int*)(0x4380CC68UL))) +#define bM4_USBFS_HCCHAR11_DAD5 (*((volatile unsigned int*)(0x4380CC6CUL))) +#define bM4_USBFS_HCCHAR11_DAD6 (*((volatile unsigned int*)(0x4380CC70UL))) +#define bM4_USBFS_HCCHAR11_ODDFRM (*((volatile unsigned int*)(0x4380CC74UL))) +#define bM4_USBFS_HCCHAR11_CHDIS (*((volatile unsigned int*)(0x4380CC78UL))) +#define bM4_USBFS_HCCHAR11_CHENA (*((volatile unsigned int*)(0x4380CC7CUL))) +#define bM4_USBFS_HCINT11_XFRC (*((volatile unsigned int*)(0x4380CD00UL))) +#define bM4_USBFS_HCINT11_CHH (*((volatile unsigned int*)(0x4380CD04UL))) +#define bM4_USBFS_HCINT11_STALL (*((volatile unsigned int*)(0x4380CD0CUL))) +#define bM4_USBFS_HCINT11_NAK (*((volatile unsigned int*)(0x4380CD10UL))) +#define bM4_USBFS_HCINT11_ACK (*((volatile unsigned int*)(0x4380CD14UL))) +#define bM4_USBFS_HCINT11_TXERR (*((volatile unsigned int*)(0x4380CD1CUL))) +#define bM4_USBFS_HCINT11_BBERR (*((volatile unsigned int*)(0x4380CD20UL))) +#define bM4_USBFS_HCINT11_FRMOR (*((volatile unsigned int*)(0x4380CD24UL))) +#define bM4_USBFS_HCINT11_DTERR (*((volatile unsigned int*)(0x4380CD28UL))) +#define bM4_USBFS_HCINTMSK11_XFRCM (*((volatile unsigned int*)(0x4380CD80UL))) +#define bM4_USBFS_HCINTMSK11_CHHM (*((volatile unsigned int*)(0x4380CD84UL))) +#define bM4_USBFS_HCINTMSK11_STALLM (*((volatile unsigned int*)(0x4380CD8CUL))) +#define bM4_USBFS_HCINTMSK11_NAKM (*((volatile unsigned int*)(0x4380CD90UL))) +#define bM4_USBFS_HCINTMSK11_ACKM (*((volatile unsigned int*)(0x4380CD94UL))) +#define bM4_USBFS_HCINTMSK11_TXERRM (*((volatile unsigned int*)(0x4380CD9CUL))) +#define bM4_USBFS_HCINTMSK11_BBERRM (*((volatile unsigned int*)(0x4380CDA0UL))) +#define bM4_USBFS_HCINTMSK11_FRMORM (*((volatile unsigned int*)(0x4380CDA4UL))) +#define bM4_USBFS_HCINTMSK11_DTERRM (*((volatile unsigned int*)(0x4380CDA8UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ0 (*((volatile unsigned int*)(0x4380CE00UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ1 (*((volatile unsigned int*)(0x4380CE04UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ2 (*((volatile unsigned int*)(0x4380CE08UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ3 (*((volatile unsigned int*)(0x4380CE0CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ4 (*((volatile unsigned int*)(0x4380CE10UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ5 (*((volatile unsigned int*)(0x4380CE14UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ6 (*((volatile unsigned int*)(0x4380CE18UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ7 (*((volatile unsigned int*)(0x4380CE1CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ8 (*((volatile unsigned int*)(0x4380CE20UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ9 (*((volatile unsigned int*)(0x4380CE24UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ10 (*((volatile unsigned int*)(0x4380CE28UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ11 (*((volatile unsigned int*)(0x4380CE2CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ12 (*((volatile unsigned int*)(0x4380CE30UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ13 (*((volatile unsigned int*)(0x4380CE34UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ14 (*((volatile unsigned int*)(0x4380CE38UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ15 (*((volatile unsigned int*)(0x4380CE3CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ16 (*((volatile unsigned int*)(0x4380CE40UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ17 (*((volatile unsigned int*)(0x4380CE44UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ18 (*((volatile unsigned int*)(0x4380CE48UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT0 (*((volatile unsigned int*)(0x4380CE4CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT1 (*((volatile unsigned int*)(0x4380CE50UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT2 (*((volatile unsigned int*)(0x4380CE54UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT3 (*((volatile unsigned int*)(0x4380CE58UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT4 (*((volatile unsigned int*)(0x4380CE5CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT5 (*((volatile unsigned int*)(0x4380CE60UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT6 (*((volatile unsigned int*)(0x4380CE64UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT7 (*((volatile unsigned int*)(0x4380CE68UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT8 (*((volatile unsigned int*)(0x4380CE6CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT9 (*((volatile unsigned int*)(0x4380CE70UL))) +#define bM4_USBFS_HCTSIZ11_DPID0 (*((volatile unsigned int*)(0x4380CE74UL))) +#define bM4_USBFS_HCTSIZ11_DPID1 (*((volatile unsigned int*)(0x4380CE78UL))) +#define bM4_USBFS_DCFG_DSPD0 (*((volatile unsigned int*)(0x43810000UL))) +#define bM4_USBFS_DCFG_DSPD1 (*((volatile unsigned int*)(0x43810004UL))) +#define bM4_USBFS_DCFG_NZLSOHSK (*((volatile unsigned int*)(0x43810008UL))) +#define bM4_USBFS_DCFG_DAD0 (*((volatile unsigned int*)(0x43810010UL))) +#define bM4_USBFS_DCFG_DAD1 (*((volatile unsigned int*)(0x43810014UL))) +#define bM4_USBFS_DCFG_DAD2 (*((volatile unsigned int*)(0x43810018UL))) +#define bM4_USBFS_DCFG_DAD3 (*((volatile unsigned int*)(0x4381001CUL))) +#define bM4_USBFS_DCFG_DAD4 (*((volatile unsigned int*)(0x43810020UL))) +#define bM4_USBFS_DCFG_DAD5 (*((volatile unsigned int*)(0x43810024UL))) +#define bM4_USBFS_DCFG_DAD6 (*((volatile unsigned int*)(0x43810028UL))) +#define bM4_USBFS_DCFG_PFIVL0 (*((volatile unsigned int*)(0x4381002CUL))) +#define bM4_USBFS_DCFG_PFIVL1 (*((volatile unsigned int*)(0x43810030UL))) +#define bM4_USBFS_DCTL_RWUSIG (*((volatile unsigned int*)(0x43810080UL))) +#define bM4_USBFS_DCTL_SDIS (*((volatile unsigned int*)(0x43810084UL))) +#define bM4_USBFS_DCTL_GINSTS (*((volatile unsigned int*)(0x43810088UL))) +#define bM4_USBFS_DCTL_GONSTS (*((volatile unsigned int*)(0x4381008CUL))) +#define bM4_USBFS_DCTL_SGINAK (*((volatile unsigned int*)(0x4381009CUL))) +#define bM4_USBFS_DCTL_CGINAK (*((volatile unsigned int*)(0x438100A0UL))) +#define bM4_USBFS_DCTL_SGONAK (*((volatile unsigned int*)(0x438100A4UL))) +#define bM4_USBFS_DCTL_CGONAK (*((volatile unsigned int*)(0x438100A8UL))) +#define bM4_USBFS_DCTL_POPRGDNE (*((volatile unsigned int*)(0x438100ACUL))) +#define bM4_USBFS_DSTS_SUSPSTS (*((volatile unsigned int*)(0x43810100UL))) +#define bM4_USBFS_DSTS_ENUMSPD0 (*((volatile unsigned int*)(0x43810104UL))) +#define bM4_USBFS_DSTS_ENUMSPD1 (*((volatile unsigned int*)(0x43810108UL))) +#define bM4_USBFS_DSTS_EERR (*((volatile unsigned int*)(0x4381010CUL))) +#define bM4_USBFS_DSTS_FNSOF0 (*((volatile unsigned int*)(0x43810120UL))) +#define bM4_USBFS_DSTS_FNSOF1 (*((volatile unsigned int*)(0x43810124UL))) +#define bM4_USBFS_DSTS_FNSOF2 (*((volatile unsigned int*)(0x43810128UL))) +#define bM4_USBFS_DSTS_FNSOF3 (*((volatile unsigned int*)(0x4381012CUL))) +#define bM4_USBFS_DSTS_FNSOF4 (*((volatile unsigned int*)(0x43810130UL))) +#define bM4_USBFS_DSTS_FNSOF5 (*((volatile unsigned int*)(0x43810134UL))) +#define bM4_USBFS_DSTS_FNSOF6 (*((volatile unsigned int*)(0x43810138UL))) +#define bM4_USBFS_DSTS_FNSOF7 (*((volatile unsigned int*)(0x4381013CUL))) +#define bM4_USBFS_DSTS_FNSOF8 (*((volatile unsigned int*)(0x43810140UL))) +#define bM4_USBFS_DSTS_FNSOF9 (*((volatile unsigned int*)(0x43810144UL))) +#define bM4_USBFS_DSTS_FNSOF10 (*((volatile unsigned int*)(0x43810148UL))) +#define bM4_USBFS_DSTS_FNSOF11 (*((volatile unsigned int*)(0x4381014CUL))) +#define bM4_USBFS_DSTS_FNSOF12 (*((volatile unsigned int*)(0x43810150UL))) +#define bM4_USBFS_DSTS_FNSOF13 (*((volatile unsigned int*)(0x43810154UL))) +#define bM4_USBFS_DIEPMSK_XFRCM (*((volatile unsigned int*)(0x43810200UL))) +#define bM4_USBFS_DIEPMSK_EPDM (*((volatile unsigned int*)(0x43810204UL))) +#define bM4_USBFS_DIEPMSK_TOM (*((volatile unsigned int*)(0x4381020CUL))) +#define bM4_USBFS_DIEPMSK_ITTXFEMSK (*((volatile unsigned int*)(0x43810210UL))) +#define bM4_USBFS_DIEPMSK_INEPNMM (*((volatile unsigned int*)(0x43810214UL))) +#define bM4_USBFS_DIEPMSK_INEPNEM (*((volatile unsigned int*)(0x43810218UL))) +#define bM4_USBFS_DOEPMSK_XFRCM (*((volatile unsigned int*)(0x43810280UL))) +#define bM4_USBFS_DOEPMSK_EPDM (*((volatile unsigned int*)(0x43810284UL))) +#define bM4_USBFS_DOEPMSK_STUPM (*((volatile unsigned int*)(0x4381028CUL))) +#define bM4_USBFS_DOEPMSK_OTEPDM (*((volatile unsigned int*)(0x43810290UL))) +#define bM4_USBFS_DAINT_IEPINT0 (*((volatile unsigned int*)(0x43810300UL))) +#define bM4_USBFS_DAINT_IEPINT1 (*((volatile unsigned int*)(0x43810304UL))) +#define bM4_USBFS_DAINT_IEPINT2 (*((volatile unsigned int*)(0x43810308UL))) +#define bM4_USBFS_DAINT_IEPINT3 (*((volatile unsigned int*)(0x4381030CUL))) +#define bM4_USBFS_DAINT_IEPINT4 (*((volatile unsigned int*)(0x43810310UL))) +#define bM4_USBFS_DAINT_IEPINT5 (*((volatile unsigned int*)(0x43810314UL))) +#define bM4_USBFS_DAINT_OEPINT0 (*((volatile unsigned int*)(0x43810340UL))) +#define bM4_USBFS_DAINT_OEPINT1 (*((volatile unsigned int*)(0x43810344UL))) +#define bM4_USBFS_DAINT_OEPINT2 (*((volatile unsigned int*)(0x43810348UL))) +#define bM4_USBFS_DAINT_OEPINT3 (*((volatile unsigned int*)(0x4381034CUL))) +#define bM4_USBFS_DAINT_OEPINT4 (*((volatile unsigned int*)(0x43810350UL))) +#define bM4_USBFS_DAINT_OEPINT5 (*((volatile unsigned int*)(0x43810354UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM0 (*((volatile unsigned int*)(0x43810380UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM1 (*((volatile unsigned int*)(0x43810384UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM2 (*((volatile unsigned int*)(0x43810388UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM3 (*((volatile unsigned int*)(0x4381038CUL))) +#define bM4_USBFS_DAINTMSK_IEPINTM4 (*((volatile unsigned int*)(0x43810390UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM5 (*((volatile unsigned int*)(0x43810394UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM0 (*((volatile unsigned int*)(0x438103C0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM1 (*((volatile unsigned int*)(0x438103C4UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM2 (*((volatile unsigned int*)(0x438103C8UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM3 (*((volatile unsigned int*)(0x438103CCUL))) +#define bM4_USBFS_DAINTMSK_OEPINTM4 (*((volatile unsigned int*)(0x438103D0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM5 (*((volatile unsigned int*)(0x438103D4UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM0 (*((volatile unsigned int*)(0x43810680UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM1 (*((volatile unsigned int*)(0x43810684UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM2 (*((volatile unsigned int*)(0x43810688UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM3 (*((volatile unsigned int*)(0x4381068CUL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM4 (*((volatile unsigned int*)(0x43810690UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM5 (*((volatile unsigned int*)(0x43810694UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43812000UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43812004UL))) +#define bM4_USBFS_DIEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381203CUL))) +#define bM4_USBFS_DIEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43812044UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43812048UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381204CUL))) +#define bM4_USBFS_DIEPCTL0_STALL (*((volatile unsigned int*)(0x43812054UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM0 (*((volatile unsigned int*)(0x43812058UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM1 (*((volatile unsigned int*)(0x4381205CUL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM2 (*((volatile unsigned int*)(0x43812060UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM3 (*((volatile unsigned int*)(0x43812064UL))) +#define bM4_USBFS_DIEPCTL0_CNAK (*((volatile unsigned int*)(0x43812068UL))) +#define bM4_USBFS_DIEPCTL0_SNAK (*((volatile unsigned int*)(0x4381206CUL))) +#define bM4_USBFS_DIEPCTL0_EPDIS (*((volatile unsigned int*)(0x43812078UL))) +#define bM4_USBFS_DIEPCTL0_EPENA (*((volatile unsigned int*)(0x4381207CUL))) +#define bM4_USBFS_DIEPINT0_XFRC (*((volatile unsigned int*)(0x43812100UL))) +#define bM4_USBFS_DIEPINT0_EPDISD (*((volatile unsigned int*)(0x43812104UL))) +#define bM4_USBFS_DIEPINT0_TOC (*((volatile unsigned int*)(0x4381210CUL))) +#define bM4_USBFS_DIEPINT0_TTXFE (*((volatile unsigned int*)(0x43812110UL))) +#define bM4_USBFS_DIEPINT0_INEPNE (*((volatile unsigned int*)(0x43812118UL))) +#define bM4_USBFS_DIEPINT0_TXFE (*((volatile unsigned int*)(0x4381211CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43812200UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43812204UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43812208UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381220CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43812210UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43812214UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43812218UL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4381224CUL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x43812250UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV0 (*((volatile unsigned int*)(0x43812300UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV1 (*((volatile unsigned int*)(0x43812304UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV2 (*((volatile unsigned int*)(0x43812308UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV3 (*((volatile unsigned int*)(0x4381230CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV4 (*((volatile unsigned int*)(0x43812310UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV5 (*((volatile unsigned int*)(0x43812314UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV6 (*((volatile unsigned int*)(0x43812318UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV7 (*((volatile unsigned int*)(0x4381231CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV8 (*((volatile unsigned int*)(0x43812320UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV9 (*((volatile unsigned int*)(0x43812324UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV10 (*((volatile unsigned int*)(0x43812328UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV11 (*((volatile unsigned int*)(0x4381232CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV12 (*((volatile unsigned int*)(0x43812330UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV13 (*((volatile unsigned int*)(0x43812334UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV14 (*((volatile unsigned int*)(0x43812338UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV15 (*((volatile unsigned int*)(0x4381233CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43812400UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43812404UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43812408UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381240CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43812410UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43812414UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43812418UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381241CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43812420UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43812424UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43812428UL))) +#define bM4_USBFS_DIEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381243CUL))) +#define bM4_USBFS_DIEPCTL1_EONUM_DPID (*((volatile unsigned int*)(0x43812440UL))) +#define bM4_USBFS_DIEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43812444UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43812448UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381244CUL))) +#define bM4_USBFS_DIEPCTL1_STALL (*((volatile unsigned int*)(0x43812454UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM0 (*((volatile unsigned int*)(0x43812458UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM1 (*((volatile unsigned int*)(0x4381245CUL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM2 (*((volatile unsigned int*)(0x43812460UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM3 (*((volatile unsigned int*)(0x43812464UL))) +#define bM4_USBFS_DIEPCTL1_CNAK (*((volatile unsigned int*)(0x43812468UL))) +#define bM4_USBFS_DIEPCTL1_SNAK (*((volatile unsigned int*)(0x4381246CUL))) +#define bM4_USBFS_DIEPCTL1_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812470UL))) +#define bM4_USBFS_DIEPCTL1_SODDFRM (*((volatile unsigned int*)(0x43812474UL))) +#define bM4_USBFS_DIEPCTL1_EPDIS (*((volatile unsigned int*)(0x43812478UL))) +#define bM4_USBFS_DIEPCTL1_EPENA (*((volatile unsigned int*)(0x4381247CUL))) +#define bM4_USBFS_DIEPINT1_XFRC (*((volatile unsigned int*)(0x43812500UL))) +#define bM4_USBFS_DIEPINT1_EPDISD (*((volatile unsigned int*)(0x43812504UL))) +#define bM4_USBFS_DIEPINT1_TOC (*((volatile unsigned int*)(0x4381250CUL))) +#define bM4_USBFS_DIEPINT1_TTXFE (*((volatile unsigned int*)(0x43812510UL))) +#define bM4_USBFS_DIEPINT1_INEPNE (*((volatile unsigned int*)(0x43812518UL))) +#define bM4_USBFS_DIEPINT1_TXFE (*((volatile unsigned int*)(0x4381251CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43812600UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43812604UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43812608UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381260CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43812610UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43812614UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43812618UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381261CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43812620UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43812624UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43812628UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381262CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43812630UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43812634UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43812638UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381263CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43812640UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43812644UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43812648UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381264CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43812650UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43812654UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43812658UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381265CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43812660UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43812664UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43812668UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381266CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43812670UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV0 (*((volatile unsigned int*)(0x43812700UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV1 (*((volatile unsigned int*)(0x43812704UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV2 (*((volatile unsigned int*)(0x43812708UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV3 (*((volatile unsigned int*)(0x4381270CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV4 (*((volatile unsigned int*)(0x43812710UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV5 (*((volatile unsigned int*)(0x43812714UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV6 (*((volatile unsigned int*)(0x43812718UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV7 (*((volatile unsigned int*)(0x4381271CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV8 (*((volatile unsigned int*)(0x43812720UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV9 (*((volatile unsigned int*)(0x43812724UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV10 (*((volatile unsigned int*)(0x43812728UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV11 (*((volatile unsigned int*)(0x4381272CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV12 (*((volatile unsigned int*)(0x43812730UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV13 (*((volatile unsigned int*)(0x43812734UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV14 (*((volatile unsigned int*)(0x43812738UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV15 (*((volatile unsigned int*)(0x4381273CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43812800UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43812804UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43812808UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381280CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43812810UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43812814UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43812818UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381281CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43812820UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43812824UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43812828UL))) +#define bM4_USBFS_DIEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381283CUL))) +#define bM4_USBFS_DIEPCTL2_EONUM_DPID (*((volatile unsigned int*)(0x43812840UL))) +#define bM4_USBFS_DIEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43812844UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43812848UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381284CUL))) +#define bM4_USBFS_DIEPCTL2_STALL (*((volatile unsigned int*)(0x43812854UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM0 (*((volatile unsigned int*)(0x43812858UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM1 (*((volatile unsigned int*)(0x4381285CUL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM2 (*((volatile unsigned int*)(0x43812860UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM3 (*((volatile unsigned int*)(0x43812864UL))) +#define bM4_USBFS_DIEPCTL2_CNAK (*((volatile unsigned int*)(0x43812868UL))) +#define bM4_USBFS_DIEPCTL2_SNAK (*((volatile unsigned int*)(0x4381286CUL))) +#define bM4_USBFS_DIEPCTL2_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812870UL))) +#define bM4_USBFS_DIEPCTL2_SODDFRM (*((volatile unsigned int*)(0x43812874UL))) +#define bM4_USBFS_DIEPCTL2_EPDIS (*((volatile unsigned int*)(0x43812878UL))) +#define bM4_USBFS_DIEPCTL2_EPENA (*((volatile unsigned int*)(0x4381287CUL))) +#define bM4_USBFS_DIEPINT2_XFRC (*((volatile unsigned int*)(0x43812900UL))) +#define bM4_USBFS_DIEPINT2_EPDISD (*((volatile unsigned int*)(0x43812904UL))) +#define bM4_USBFS_DIEPINT2_TOC (*((volatile unsigned int*)(0x4381290CUL))) +#define bM4_USBFS_DIEPINT2_TTXFE (*((volatile unsigned int*)(0x43812910UL))) +#define bM4_USBFS_DIEPINT2_INEPNE (*((volatile unsigned int*)(0x43812918UL))) +#define bM4_USBFS_DIEPINT2_TXFE (*((volatile unsigned int*)(0x4381291CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43812A00UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43812A04UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43812A08UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43812A0CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43812A10UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43812A14UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43812A18UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43812A1CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43812A20UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43812A24UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43812A28UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43812A2CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43812A30UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43812A34UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43812A38UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43812A3CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43812A40UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43812A44UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43812A48UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43812A4CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43812A50UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43812A54UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43812A58UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43812A5CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43812A60UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43812A64UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43812A68UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43812A6CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43812A70UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV0 (*((volatile unsigned int*)(0x43812B00UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV1 (*((volatile unsigned int*)(0x43812B04UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV2 (*((volatile unsigned int*)(0x43812B08UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV3 (*((volatile unsigned int*)(0x43812B0CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV4 (*((volatile unsigned int*)(0x43812B10UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV5 (*((volatile unsigned int*)(0x43812B14UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV6 (*((volatile unsigned int*)(0x43812B18UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV7 (*((volatile unsigned int*)(0x43812B1CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV8 (*((volatile unsigned int*)(0x43812B20UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV9 (*((volatile unsigned int*)(0x43812B24UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV10 (*((volatile unsigned int*)(0x43812B28UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV11 (*((volatile unsigned int*)(0x43812B2CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV12 (*((volatile unsigned int*)(0x43812B30UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV13 (*((volatile unsigned int*)(0x43812B34UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV14 (*((volatile unsigned int*)(0x43812B38UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV15 (*((volatile unsigned int*)(0x43812B3CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43812C00UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43812C04UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43812C08UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43812C0CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43812C10UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43812C14UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43812C18UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43812C1CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43812C20UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43812C24UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43812C28UL))) +#define bM4_USBFS_DIEPCTL3_USBAEP (*((volatile unsigned int*)(0x43812C3CUL))) +#define bM4_USBFS_DIEPCTL3_EONUM_DPID (*((volatile unsigned int*)(0x43812C40UL))) +#define bM4_USBFS_DIEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43812C44UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43812C48UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43812C4CUL))) +#define bM4_USBFS_DIEPCTL3_STALL (*((volatile unsigned int*)(0x43812C54UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM0 (*((volatile unsigned int*)(0x43812C58UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM1 (*((volatile unsigned int*)(0x43812C5CUL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM2 (*((volatile unsigned int*)(0x43812C60UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM3 (*((volatile unsigned int*)(0x43812C64UL))) +#define bM4_USBFS_DIEPCTL3_CNAK (*((volatile unsigned int*)(0x43812C68UL))) +#define bM4_USBFS_DIEPCTL3_SNAK (*((volatile unsigned int*)(0x43812C6CUL))) +#define bM4_USBFS_DIEPCTL3_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812C70UL))) +#define bM4_USBFS_DIEPCTL3_SODDFRM (*((volatile unsigned int*)(0x43812C74UL))) +#define bM4_USBFS_DIEPCTL3_EPDIS (*((volatile unsigned int*)(0x43812C78UL))) +#define bM4_USBFS_DIEPCTL3_EPENA (*((volatile unsigned int*)(0x43812C7CUL))) +#define bM4_USBFS_DIEPINT3_XFRC (*((volatile unsigned int*)(0x43812D00UL))) +#define bM4_USBFS_DIEPINT3_EPDISD (*((volatile unsigned int*)(0x43812D04UL))) +#define bM4_USBFS_DIEPINT3_TOC (*((volatile unsigned int*)(0x43812D0CUL))) +#define bM4_USBFS_DIEPINT3_TTXFE (*((volatile unsigned int*)(0x43812D10UL))) +#define bM4_USBFS_DIEPINT3_INEPNE (*((volatile unsigned int*)(0x43812D18UL))) +#define bM4_USBFS_DIEPINT3_TXFE (*((volatile unsigned int*)(0x43812D1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43812E00UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43812E04UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43812E08UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43812E0CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43812E10UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43812E14UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43812E18UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43812E1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43812E20UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43812E24UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43812E28UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43812E2CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43812E30UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43812E34UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43812E38UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43812E3CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43812E40UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43812E44UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43812E48UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43812E4CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43812E50UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43812E54UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43812E58UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43812E5CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43812E60UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43812E64UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43812E68UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43812E6CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43812E70UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV0 (*((volatile unsigned int*)(0x43812F00UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV1 (*((volatile unsigned int*)(0x43812F04UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV2 (*((volatile unsigned int*)(0x43812F08UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV3 (*((volatile unsigned int*)(0x43812F0CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV4 (*((volatile unsigned int*)(0x43812F10UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV5 (*((volatile unsigned int*)(0x43812F14UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV6 (*((volatile unsigned int*)(0x43812F18UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV7 (*((volatile unsigned int*)(0x43812F1CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV8 (*((volatile unsigned int*)(0x43812F20UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV9 (*((volatile unsigned int*)(0x43812F24UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV10 (*((volatile unsigned int*)(0x43812F28UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV11 (*((volatile unsigned int*)(0x43812F2CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV12 (*((volatile unsigned int*)(0x43812F30UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV13 (*((volatile unsigned int*)(0x43812F34UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV14 (*((volatile unsigned int*)(0x43812F38UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV15 (*((volatile unsigned int*)(0x43812F3CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43813000UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43813004UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43813008UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381300CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43813010UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43813014UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43813018UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381301CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43813020UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43813024UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43813028UL))) +#define bM4_USBFS_DIEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381303CUL))) +#define bM4_USBFS_DIEPCTL4_EONUM_DPID (*((volatile unsigned int*)(0x43813040UL))) +#define bM4_USBFS_DIEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43813044UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43813048UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381304CUL))) +#define bM4_USBFS_DIEPCTL4_STALL (*((volatile unsigned int*)(0x43813054UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM0 (*((volatile unsigned int*)(0x43813058UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM1 (*((volatile unsigned int*)(0x4381305CUL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM2 (*((volatile unsigned int*)(0x43813060UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM3 (*((volatile unsigned int*)(0x43813064UL))) +#define bM4_USBFS_DIEPCTL4_CNAK (*((volatile unsigned int*)(0x43813068UL))) +#define bM4_USBFS_DIEPCTL4_SNAK (*((volatile unsigned int*)(0x4381306CUL))) +#define bM4_USBFS_DIEPCTL4_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813070UL))) +#define bM4_USBFS_DIEPCTL4_SODDFRM (*((volatile unsigned int*)(0x43813074UL))) +#define bM4_USBFS_DIEPCTL4_EPDIS (*((volatile unsigned int*)(0x43813078UL))) +#define bM4_USBFS_DIEPCTL4_EPENA (*((volatile unsigned int*)(0x4381307CUL))) +#define bM4_USBFS_DIEPINT4_XFRC (*((volatile unsigned int*)(0x43813100UL))) +#define bM4_USBFS_DIEPINT4_EPDISD (*((volatile unsigned int*)(0x43813104UL))) +#define bM4_USBFS_DIEPINT4_TOC (*((volatile unsigned int*)(0x4381310CUL))) +#define bM4_USBFS_DIEPINT4_TTXFE (*((volatile unsigned int*)(0x43813110UL))) +#define bM4_USBFS_DIEPINT4_INEPNE (*((volatile unsigned int*)(0x43813118UL))) +#define bM4_USBFS_DIEPINT4_TXFE (*((volatile unsigned int*)(0x4381311CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43813200UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43813204UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43813208UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381320CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43813210UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43813214UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43813218UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381321CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43813220UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43813224UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43813228UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381322CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43813230UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43813234UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43813238UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381323CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43813240UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43813244UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43813248UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381324CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43813250UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43813254UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43813258UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381325CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43813260UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43813264UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43813268UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381326CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43813270UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV0 (*((volatile unsigned int*)(0x43813300UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV1 (*((volatile unsigned int*)(0x43813304UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV2 (*((volatile unsigned int*)(0x43813308UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV3 (*((volatile unsigned int*)(0x4381330CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV4 (*((volatile unsigned int*)(0x43813310UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV5 (*((volatile unsigned int*)(0x43813314UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV6 (*((volatile unsigned int*)(0x43813318UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV7 (*((volatile unsigned int*)(0x4381331CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV8 (*((volatile unsigned int*)(0x43813320UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV9 (*((volatile unsigned int*)(0x43813324UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV10 (*((volatile unsigned int*)(0x43813328UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV11 (*((volatile unsigned int*)(0x4381332CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV12 (*((volatile unsigned int*)(0x43813330UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV13 (*((volatile unsigned int*)(0x43813334UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV14 (*((volatile unsigned int*)(0x43813338UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV15 (*((volatile unsigned int*)(0x4381333CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43813400UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43813404UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43813408UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381340CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43813410UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43813414UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43813418UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381341CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43813420UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43813424UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43813428UL))) +#define bM4_USBFS_DIEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381343CUL))) +#define bM4_USBFS_DIEPCTL5_EONUM_DPID (*((volatile unsigned int*)(0x43813440UL))) +#define bM4_USBFS_DIEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43813444UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43813448UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381344CUL))) +#define bM4_USBFS_DIEPCTL5_STALL (*((volatile unsigned int*)(0x43813454UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM0 (*((volatile unsigned int*)(0x43813458UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM1 (*((volatile unsigned int*)(0x4381345CUL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM2 (*((volatile unsigned int*)(0x43813460UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM3 (*((volatile unsigned int*)(0x43813464UL))) +#define bM4_USBFS_DIEPCTL5_CNAK (*((volatile unsigned int*)(0x43813468UL))) +#define bM4_USBFS_DIEPCTL5_SNAK (*((volatile unsigned int*)(0x4381346CUL))) +#define bM4_USBFS_DIEPCTL5_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813470UL))) +#define bM4_USBFS_DIEPCTL5_SODDFRM (*((volatile unsigned int*)(0x43813474UL))) +#define bM4_USBFS_DIEPCTL5_EPDIS (*((volatile unsigned int*)(0x43813478UL))) +#define bM4_USBFS_DIEPCTL5_EPENA (*((volatile unsigned int*)(0x4381347CUL))) +#define bM4_USBFS_DIEPINT5_XFRC (*((volatile unsigned int*)(0x43813500UL))) +#define bM4_USBFS_DIEPINT5_EPDISD (*((volatile unsigned int*)(0x43813504UL))) +#define bM4_USBFS_DIEPINT5_TOC (*((volatile unsigned int*)(0x4381350CUL))) +#define bM4_USBFS_DIEPINT5_TTXFE (*((volatile unsigned int*)(0x43813510UL))) +#define bM4_USBFS_DIEPINT5_INEPNE (*((volatile unsigned int*)(0x43813518UL))) +#define bM4_USBFS_DIEPINT5_TXFE (*((volatile unsigned int*)(0x4381351CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43813600UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43813604UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43813608UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381360CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43813610UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43813614UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43813618UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381361CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43813620UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43813624UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43813628UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381362CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43813630UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43813634UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43813638UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381363CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43813640UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43813644UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43813648UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381364CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43813650UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43813654UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43813658UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381365CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43813660UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43813664UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43813668UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381366CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43813670UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV0 (*((volatile unsigned int*)(0x43813700UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV1 (*((volatile unsigned int*)(0x43813704UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV2 (*((volatile unsigned int*)(0x43813708UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV3 (*((volatile unsigned int*)(0x4381370CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV4 (*((volatile unsigned int*)(0x43813710UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV5 (*((volatile unsigned int*)(0x43813714UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV6 (*((volatile unsigned int*)(0x43813718UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV7 (*((volatile unsigned int*)(0x4381371CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV8 (*((volatile unsigned int*)(0x43813720UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV9 (*((volatile unsigned int*)(0x43813724UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV10 (*((volatile unsigned int*)(0x43813728UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV11 (*((volatile unsigned int*)(0x4381372CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV12 (*((volatile unsigned int*)(0x43813730UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV13 (*((volatile unsigned int*)(0x43813734UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV14 (*((volatile unsigned int*)(0x43813738UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV15 (*((volatile unsigned int*)(0x4381373CUL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43816000UL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43816004UL))) +#define bM4_USBFS_DOEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381603CUL))) +#define bM4_USBFS_DOEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43816044UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43816048UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381604CUL))) +#define bM4_USBFS_DOEPCTL0_SNPM (*((volatile unsigned int*)(0x43816050UL))) +#define bM4_USBFS_DOEPCTL0_STALL (*((volatile unsigned int*)(0x43816054UL))) +#define bM4_USBFS_DOEPCTL0_CNAK (*((volatile unsigned int*)(0x43816068UL))) +#define bM4_USBFS_DOEPCTL0_SNAK (*((volatile unsigned int*)(0x4381606CUL))) +#define bM4_USBFS_DOEPCTL0_EPDIS (*((volatile unsigned int*)(0x43816078UL))) +#define bM4_USBFS_DOEPCTL0_EPENA (*((volatile unsigned int*)(0x4381607CUL))) +#define bM4_USBFS_DOEPINT0_XFRC (*((volatile unsigned int*)(0x43816100UL))) +#define bM4_USBFS_DOEPINT0_EPDISD (*((volatile unsigned int*)(0x43816104UL))) +#define bM4_USBFS_DOEPINT0_STUP (*((volatile unsigned int*)(0x4381610CUL))) +#define bM4_USBFS_DOEPINT0_OTEPDIS (*((volatile unsigned int*)(0x43816110UL))) +#define bM4_USBFS_DOEPINT0_B2BSTUP (*((volatile unsigned int*)(0x43816118UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43816200UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43816204UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43816208UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381620CUL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43816210UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43816214UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43816218UL))) +#define bM4_USBFS_DOEPTSIZ0_PKTCNT (*((volatile unsigned int*)(0x4381624CUL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT0 (*((volatile unsigned int*)(0x43816274UL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT1 (*((volatile unsigned int*)(0x43816278UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43816400UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43816404UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43816408UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381640CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43816410UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43816414UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43816418UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381641CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43816420UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43816424UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43816428UL))) +#define bM4_USBFS_DOEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381643CUL))) +#define bM4_USBFS_DOEPCTL1_DPID (*((volatile unsigned int*)(0x43816440UL))) +#define bM4_USBFS_DOEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43816444UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43816448UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381644CUL))) +#define bM4_USBFS_DOEPCTL1_SNPM (*((volatile unsigned int*)(0x43816450UL))) +#define bM4_USBFS_DOEPCTL1_STALL (*((volatile unsigned int*)(0x43816454UL))) +#define bM4_USBFS_DOEPCTL1_CNAK (*((volatile unsigned int*)(0x43816468UL))) +#define bM4_USBFS_DOEPCTL1_SNAK (*((volatile unsigned int*)(0x4381646CUL))) +#define bM4_USBFS_DOEPCTL1_SD0PID (*((volatile unsigned int*)(0x43816470UL))) +#define bM4_USBFS_DOEPCTL1_SD1PID (*((volatile unsigned int*)(0x43816474UL))) +#define bM4_USBFS_DOEPCTL1_EPDIS (*((volatile unsigned int*)(0x43816478UL))) +#define bM4_USBFS_DOEPCTL1_EPENA (*((volatile unsigned int*)(0x4381647CUL))) +#define bM4_USBFS_DOEPINT1_XFRC (*((volatile unsigned int*)(0x43816500UL))) +#define bM4_USBFS_DOEPINT1_EPDISD (*((volatile unsigned int*)(0x43816504UL))) +#define bM4_USBFS_DOEPINT1_STUP (*((volatile unsigned int*)(0x4381650CUL))) +#define bM4_USBFS_DOEPINT1_OTEPDIS (*((volatile unsigned int*)(0x43816510UL))) +#define bM4_USBFS_DOEPINT1_B2BSTUP (*((volatile unsigned int*)(0x43816518UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43816600UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43816604UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43816608UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381660CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43816610UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43816614UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43816618UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381661CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43816620UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43816624UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43816628UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381662CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43816630UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43816634UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43816638UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381663CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43816640UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43816644UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43816648UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381664CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43816650UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43816654UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43816658UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381665CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43816660UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43816664UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43816668UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381666CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43816670UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43816800UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43816804UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43816808UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381680CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43816810UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43816814UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43816818UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381681CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43816820UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43816824UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43816828UL))) +#define bM4_USBFS_DOEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381683CUL))) +#define bM4_USBFS_DOEPCTL2_DPID (*((volatile unsigned int*)(0x43816840UL))) +#define bM4_USBFS_DOEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43816844UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43816848UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381684CUL))) +#define bM4_USBFS_DOEPCTL2_SNPM (*((volatile unsigned int*)(0x43816850UL))) +#define bM4_USBFS_DOEPCTL2_STALL (*((volatile unsigned int*)(0x43816854UL))) +#define bM4_USBFS_DOEPCTL2_CNAK (*((volatile unsigned int*)(0x43816868UL))) +#define bM4_USBFS_DOEPCTL2_SNAK (*((volatile unsigned int*)(0x4381686CUL))) +#define bM4_USBFS_DOEPCTL2_SD0PID (*((volatile unsigned int*)(0x43816870UL))) +#define bM4_USBFS_DOEPCTL2_SD1PID (*((volatile unsigned int*)(0x43816874UL))) +#define bM4_USBFS_DOEPCTL2_EPDIS (*((volatile unsigned int*)(0x43816878UL))) +#define bM4_USBFS_DOEPCTL2_EPENA (*((volatile unsigned int*)(0x4381687CUL))) +#define bM4_USBFS_DOEPINT2_XFRC (*((volatile unsigned int*)(0x43816900UL))) +#define bM4_USBFS_DOEPINT2_EPDISD (*((volatile unsigned int*)(0x43816904UL))) +#define bM4_USBFS_DOEPINT2_STUP (*((volatile unsigned int*)(0x4381690CUL))) +#define bM4_USBFS_DOEPINT2_OTEPDIS (*((volatile unsigned int*)(0x43816910UL))) +#define bM4_USBFS_DOEPINT2_B2BSTUP (*((volatile unsigned int*)(0x43816918UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43816A00UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43816A04UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43816A08UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43816A0CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43816A10UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43816A14UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43816A18UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43816A1CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43816A20UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43816A24UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43816A28UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43816A2CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43816A30UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43816A34UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43816A38UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43816A3CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43816A40UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43816A44UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43816A48UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43816A4CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43816A50UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43816A54UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43816A58UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43816A5CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43816A60UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43816A64UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43816A68UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43816A6CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43816A70UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43816C00UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43816C04UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43816C08UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43816C0CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43816C10UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43816C14UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43816C18UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43816C1CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43816C20UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43816C24UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43816C28UL))) +#define bM4_USBFS_DOEPCTL3_USBAEP (*((volatile unsigned int*)(0x43816C3CUL))) +#define bM4_USBFS_DOEPCTL3_DPID (*((volatile unsigned int*)(0x43816C40UL))) +#define bM4_USBFS_DOEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43816C44UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43816C48UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43816C4CUL))) +#define bM4_USBFS_DOEPCTL3_SNPM (*((volatile unsigned int*)(0x43816C50UL))) +#define bM4_USBFS_DOEPCTL3_STALL (*((volatile unsigned int*)(0x43816C54UL))) +#define bM4_USBFS_DOEPCTL3_CNAK (*((volatile unsigned int*)(0x43816C68UL))) +#define bM4_USBFS_DOEPCTL3_SNAK (*((volatile unsigned int*)(0x43816C6CUL))) +#define bM4_USBFS_DOEPCTL3_SD0PID (*((volatile unsigned int*)(0x43816C70UL))) +#define bM4_USBFS_DOEPCTL3_SD1PID (*((volatile unsigned int*)(0x43816C74UL))) +#define bM4_USBFS_DOEPCTL3_EPDIS (*((volatile unsigned int*)(0x43816C78UL))) +#define bM4_USBFS_DOEPCTL3_EPENA (*((volatile unsigned int*)(0x43816C7CUL))) +#define bM4_USBFS_DOEPINT3_XFRC (*((volatile unsigned int*)(0x43816D00UL))) +#define bM4_USBFS_DOEPINT3_EPDISD (*((volatile unsigned int*)(0x43816D04UL))) +#define bM4_USBFS_DOEPINT3_STUP (*((volatile unsigned int*)(0x43816D0CUL))) +#define bM4_USBFS_DOEPINT3_OTEPDIS (*((volatile unsigned int*)(0x43816D10UL))) +#define bM4_USBFS_DOEPINT3_B2BSTUP (*((volatile unsigned int*)(0x43816D18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43816E00UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43816E04UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43816E08UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43816E0CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43816E10UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43816E14UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43816E18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43816E1CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43816E20UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43816E24UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43816E28UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43816E2CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43816E30UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43816E34UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43816E38UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43816E3CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43816E40UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43816E44UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43816E48UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43816E4CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43816E50UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43816E54UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43816E58UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43816E5CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43816E60UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43816E64UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43816E68UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43816E6CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43816E70UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43817000UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43817004UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43817008UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381700CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43817010UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43817014UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43817018UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381701CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43817020UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43817024UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43817028UL))) +#define bM4_USBFS_DOEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381703CUL))) +#define bM4_USBFS_DOEPCTL4_DPID (*((volatile unsigned int*)(0x43817040UL))) +#define bM4_USBFS_DOEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43817044UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43817048UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381704CUL))) +#define bM4_USBFS_DOEPCTL4_SNPM (*((volatile unsigned int*)(0x43817050UL))) +#define bM4_USBFS_DOEPCTL4_STALL (*((volatile unsigned int*)(0x43817054UL))) +#define bM4_USBFS_DOEPCTL4_CNAK (*((volatile unsigned int*)(0x43817068UL))) +#define bM4_USBFS_DOEPCTL4_SNAK (*((volatile unsigned int*)(0x4381706CUL))) +#define bM4_USBFS_DOEPCTL4_SD0PID (*((volatile unsigned int*)(0x43817070UL))) +#define bM4_USBFS_DOEPCTL4_SD1PID (*((volatile unsigned int*)(0x43817074UL))) +#define bM4_USBFS_DOEPCTL4_EPDIS (*((volatile unsigned int*)(0x43817078UL))) +#define bM4_USBFS_DOEPCTL4_EPENA (*((volatile unsigned int*)(0x4381707CUL))) +#define bM4_USBFS_DOEPINT4_XFRC (*((volatile unsigned int*)(0x43817100UL))) +#define bM4_USBFS_DOEPINT4_EPDISD (*((volatile unsigned int*)(0x43817104UL))) +#define bM4_USBFS_DOEPINT4_STUP (*((volatile unsigned int*)(0x4381710CUL))) +#define bM4_USBFS_DOEPINT4_OTEPDIS (*((volatile unsigned int*)(0x43817110UL))) +#define bM4_USBFS_DOEPINT4_B2BSTUP (*((volatile unsigned int*)(0x43817118UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43817200UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43817204UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43817208UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381720CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43817210UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43817214UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43817218UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381721CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43817220UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43817224UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43817228UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381722CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43817230UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43817234UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43817238UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381723CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43817240UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43817244UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43817248UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381724CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43817250UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43817254UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43817258UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381725CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43817260UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43817264UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43817268UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381726CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43817270UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43817400UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43817404UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43817408UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381740CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43817410UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43817414UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43817418UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381741CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43817420UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43817424UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43817428UL))) +#define bM4_USBFS_DOEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381743CUL))) +#define bM4_USBFS_DOEPCTL5_DPID (*((volatile unsigned int*)(0x43817440UL))) +#define bM4_USBFS_DOEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43817444UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43817448UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381744CUL))) +#define bM4_USBFS_DOEPCTL5_SNPM (*((volatile unsigned int*)(0x43817450UL))) +#define bM4_USBFS_DOEPCTL5_STALL (*((volatile unsigned int*)(0x43817454UL))) +#define bM4_USBFS_DOEPCTL5_CNAK (*((volatile unsigned int*)(0x43817468UL))) +#define bM4_USBFS_DOEPCTL5_SNAK (*((volatile unsigned int*)(0x4381746CUL))) +#define bM4_USBFS_DOEPCTL5_SD0PID (*((volatile unsigned int*)(0x43817470UL))) +#define bM4_USBFS_DOEPCTL5_SD1PID (*((volatile unsigned int*)(0x43817474UL))) +#define bM4_USBFS_DOEPCTL5_EPDIS (*((volatile unsigned int*)(0x43817478UL))) +#define bM4_USBFS_DOEPCTL5_EPENA (*((volatile unsigned int*)(0x4381747CUL))) +#define bM4_USBFS_DOEPINT5_XFRC (*((volatile unsigned int*)(0x43817500UL))) +#define bM4_USBFS_DOEPINT5_EPDISD (*((volatile unsigned int*)(0x43817504UL))) +#define bM4_USBFS_DOEPINT5_STUP (*((volatile unsigned int*)(0x4381750CUL))) +#define bM4_USBFS_DOEPINT5_OTEPDIS (*((volatile unsigned int*)(0x43817510UL))) +#define bM4_USBFS_DOEPINT5_B2BSTUP (*((volatile unsigned int*)(0x43817518UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43817600UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43817604UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43817608UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381760CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43817610UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43817614UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43817618UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381761CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43817620UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43817624UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43817628UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381762CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43817630UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43817634UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43817638UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381763CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43817640UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43817644UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43817648UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381764CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43817650UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43817654UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43817658UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381765CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43817660UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43817664UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43817668UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381766CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43817670UL))) +#define bM4_USBFS_PCGCCTL_STPPCLK (*((volatile unsigned int*)(0x4381C000UL))) +#define bM4_USBFS_PCGCCTL_GATEHCLK (*((volatile unsigned int*)(0x4381C004UL))) +#define bM4_WDT_CR_PERI0 (*((volatile unsigned int*)(0x42920000UL))) +#define bM4_WDT_CR_PERI1 (*((volatile unsigned int*)(0x42920004UL))) +#define bM4_WDT_CR_CKS0 (*((volatile unsigned int*)(0x42920010UL))) +#define bM4_WDT_CR_CKS1 (*((volatile unsigned int*)(0x42920014UL))) +#define bM4_WDT_CR_CKS2 (*((volatile unsigned int*)(0x42920018UL))) +#define bM4_WDT_CR_CKS3 (*((volatile unsigned int*)(0x4292001CUL))) +#define bM4_WDT_CR_WDPT0 (*((volatile unsigned int*)(0x42920020UL))) +#define bM4_WDT_CR_WDPT1 (*((volatile unsigned int*)(0x42920024UL))) +#define bM4_WDT_CR_WDPT2 (*((volatile unsigned int*)(0x42920028UL))) +#define bM4_WDT_CR_WDPT3 (*((volatile unsigned int*)(0x4292002CUL))) +#define bM4_WDT_CR_SLPOFF (*((volatile unsigned int*)(0x42920040UL))) +#define bM4_WDT_CR_ITS (*((volatile unsigned int*)(0x4292007CUL))) +#define bM4_WDT_SR_CNT0 (*((volatile unsigned int*)(0x42920080UL))) +#define bM4_WDT_SR_CNT1 (*((volatile unsigned int*)(0x42920084UL))) +#define bM4_WDT_SR_CNT2 (*((volatile unsigned int*)(0x42920088UL))) +#define bM4_WDT_SR_CNT3 (*((volatile unsigned int*)(0x4292008CUL))) +#define bM4_WDT_SR_CNT4 (*((volatile unsigned int*)(0x42920090UL))) +#define bM4_WDT_SR_CNT5 (*((volatile unsigned int*)(0x42920094UL))) +#define bM4_WDT_SR_CNT6 (*((volatile unsigned int*)(0x42920098UL))) +#define bM4_WDT_SR_CNT7 (*((volatile unsigned int*)(0x4292009CUL))) +#define bM4_WDT_SR_CNT8 (*((volatile unsigned int*)(0x429200A0UL))) +#define bM4_WDT_SR_CNT9 (*((volatile unsigned int*)(0x429200A4UL))) +#define bM4_WDT_SR_CNT10 (*((volatile unsigned int*)(0x429200A8UL))) +#define bM4_WDT_SR_CNT11 (*((volatile unsigned int*)(0x429200ACUL))) +#define bM4_WDT_SR_CNT12 (*((volatile unsigned int*)(0x429200B0UL))) +#define bM4_WDT_SR_CNT13 (*((volatile unsigned int*)(0x429200B4UL))) +#define bM4_WDT_SR_CNT14 (*((volatile unsigned int*)(0x429200B8UL))) +#define bM4_WDT_SR_CNT15 (*((volatile unsigned int*)(0x429200BCUL))) +#define bM4_WDT_SR_UDF (*((volatile unsigned int*)(0x429200C0UL))) +#define bM4_WDT_SR_REF (*((volatile unsigned int*)(0x429200C4UL))) +#define bM4_WDT_RR_RF0 (*((volatile unsigned int*)(0x42920100UL))) +#define bM4_WDT_RR_RF1 (*((volatile unsigned int*)(0x42920104UL))) +#define bM4_WDT_RR_RF2 (*((volatile unsigned int*)(0x42920108UL))) +#define bM4_WDT_RR_RF3 (*((volatile unsigned int*)(0x4292010CUL))) +#define bM4_WDT_RR_RF4 (*((volatile unsigned int*)(0x42920110UL))) +#define bM4_WDT_RR_RF5 (*((volatile unsigned int*)(0x42920114UL))) +#define bM4_WDT_RR_RF6 (*((volatile unsigned int*)(0x42920118UL))) +#define bM4_WDT_RR_RF7 (*((volatile unsigned int*)(0x4292011CUL))) +#define bM4_WDT_RR_RF8 (*((volatile unsigned int*)(0x42920120UL))) +#define bM4_WDT_RR_RF9 (*((volatile unsigned int*)(0x42920124UL))) +#define bM4_WDT_RR_RF10 (*((volatile unsigned int*)(0x42920128UL))) +#define bM4_WDT_RR_RF11 (*((volatile unsigned int*)(0x4292012CUL))) +#define bM4_WDT_RR_RF12 (*((volatile unsigned int*)(0x42920130UL))) +#define bM4_WDT_RR_RF13 (*((volatile unsigned int*)(0x42920134UL))) +#define bM4_WDT_RR_RF14 (*((volatile unsigned int*)(0x42920138UL))) +#define bM4_WDT_RR_RF15 (*((volatile unsigned int*)(0x4292013CUL))) +#define bM4_WKTM_CR_WKTMCMP0 (*((volatile unsigned int*)(0x42988000UL))) +#define bM4_WKTM_CR_WKTMCMP1 (*((volatile unsigned int*)(0x42988004UL))) +#define bM4_WKTM_CR_WKTMCMP2 (*((volatile unsigned int*)(0x42988008UL))) +#define bM4_WKTM_CR_WKTMCMP3 (*((volatile unsigned int*)(0x4298800CUL))) +#define bM4_WKTM_CR_WKTMCMP4 (*((volatile unsigned int*)(0x42988010UL))) +#define bM4_WKTM_CR_WKTMCMP5 (*((volatile unsigned int*)(0x42988014UL))) +#define bM4_WKTM_CR_WKTMCMP6 (*((volatile unsigned int*)(0x42988018UL))) +#define bM4_WKTM_CR_WKTMCMP7 (*((volatile unsigned int*)(0x4298801CUL))) +#define bM4_WKTM_CR_WKTMCMP8 (*((volatile unsigned int*)(0x42988020UL))) +#define bM4_WKTM_CR_WKTMCMP9 (*((volatile unsigned int*)(0x42988024UL))) +#define bM4_WKTM_CR_WKTMCMP10 (*((volatile unsigned int*)(0x42988028UL))) +#define bM4_WKTM_CR_WKTMCMP11 (*((volatile unsigned int*)(0x4298802CUL))) +#define bM4_WKTM_CR_WKOVF (*((volatile unsigned int*)(0x42988030UL))) +#define bM4_WKTM_CR_WKCKS0 (*((volatile unsigned int*)(0x42988034UL))) +#define bM4_WKTM_CR_WKCKS1 (*((volatile unsigned int*)(0x42988038UL))) +#define bM4_WKTM_CR_WKTCE (*((volatile unsigned int*)(0x4298803CUL))) + + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_H__ */ + diff --git a/lib/hc32f460/mcu/common/system_hc32f460.c b/lib/hc32f460/mcu/common/system_hc32f460.c new file mode 100644 index 000000000000..2c4b90c2a05b --- /dev/null +++ b/lib/hc32f460/mcu/common/system_hc32f460.c @@ -0,0 +1,123 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.c + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/** + ******************************************************************************* + ** \addtogroup Hc32f460SystemGroup + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +//@{ + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t HRC_VALUE = HRC_16MHz_VALUE; +uint32_t SystemCoreClock = MRC_VALUE; + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param None + ** \return None + ******************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + +// SystemCoreClock = 168000000ul; + SystemCoreClockUpdate(); +} + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + uint8_t tmp = 0u; + uint32_t plln = 19u, pllp = 1u, pllm = 0u, pllsource = 0u; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + /* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */ + /* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */ + if (1UL == (HRC_FREQ_MON() & 1UL)) + { + HRC_VALUE = HRC_16MHz_VALUE; + } + else + { + HRC_VALUE = HRC_20MHz_VALUE; + } + + tmp = M4_SYSREG->CMU_CKSWR_f.CKSW; + switch (tmp) + { + case 0x00: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + /* use exteranl high speed OSC as PLL source */ + if (0ul == pllsource) + { + SystemCoreClock = (XTAL_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + /* use interanl high RC as PLL source */ + else if (1ul == pllsource) + { + SystemCoreClock = (HRC_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + else + { + /* Reserved */ + } + break; + } +} + +//@} // UsartGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/hc32f460/mcu/common/system_hc32f460.h b/lib/hc32f460/mcu/common/system_hc32f460.h new file mode 100644 index 000000000000..2fd8334920c8 --- /dev/null +++ b/lib/hc32f460/mcu/common/system_hc32f460.h @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.h + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version. + ** + ******************************************************************************/ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32f460SystemGroup HC32F460 System Configure + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + +#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL))) + +#if !defined (HRC_16MHz_VALUE) + #define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */ +#endif + +#if !defined (HRC_20MHz_VALUE) + #define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */ +#endif + +#if !defined (MRC_VALUE) +#define MRC_VALUE ((uint32_t)8000000) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE ((uint32_t)32768) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE ((uint32_t)8000000) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE ((uint32_t)32768) /*!< External low speed OSC freq. */ +#endif + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern uint32_t HRC_VALUE; // HRC Clock Frequency (Core Clock) +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit(void); // Initialize the system +extern void SystemCoreClockUpdate(void); // Update SystemCoreClock variable + +//@} // Hc32f460SystemGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/lib/n32g45x/include/n32g45x_adc.h b/lib/n32g45x/include/n32g45x_adc.h new file mode 100644 index 000000000000..ab929feb83bb --- /dev/null +++ b/lib/n32g45x/include/n32g45x_adc.h @@ -0,0 +1,331 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +#ifndef ____N32G45x_ADC____ +#define ____N32G45x_ADC____ + +#define __IO volatile + +typedef struct +{ + uint32_t WorkMode; + uint32_t MultiChEn; + uint32_t ContinueConvEn; + uint32_t ExtTrigSelect; + uint32_t DatAlign; + uint8_t ChsNumber; +} ADC_InitType; + +typedef struct +{ + __IO uint32_t STS; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t SAMPT1; + __IO uint32_t SAMPT2; + __IO uint32_t JOFFSET1; + __IO uint32_t JOFFSET2; + __IO uint32_t JOFFSET3; + __IO uint32_t JOFFSET4; + __IO uint32_t WDGHIGH; + __IO uint32_t WDGLOW; + __IO uint32_t RSEQ1; + __IO uint32_t RSEQ2; + __IO uint32_t RSEQ3; + __IO uint32_t JSEQ; + __IO uint32_t JDAT1; + __IO uint32_t JDAT2; + __IO uint32_t JDAT3; + __IO uint32_t JDAT4; + __IO uint32_t DAT; + __IO uint32_t DIFSEL; + __IO uint32_t CALFACT; + __IO uint32_t CTRL3; + __IO uint32_t SAMPT3; +} ADC_Module; + +#define NS_ADC1_BASE ((uint32_t)0x40020800) +#define NS_ADC2_BASE ((uint32_t)0x40020c00) +#define NS_ADC3_BASE ((uint32_t)0x40021800) +#define NS_ADC4_BASE ((uint32_t)0x40021c00) + +#define NS_ADC1 ((ADC_Module *)NS_ADC1_BASE) +#define NS_ADC2 ((ADC_Module *)NS_ADC2_BASE) +#define NS_ADC3 ((ADC_Module *)NS_ADC3_BASE) +#define NS_ADC4 ((ADC_Module *)NS_ADC4_BASE) + +#define ADC_RCC_BASE ((uint32_t)0x40021000) +#define ADC_RCC_CTRL *((uint32_t *)(ADC_RCC_BASE + 0x00)) +#define ADC_RCC_CFG *((uint32_t *)(ADC_RCC_BASE + 0x04)) +#define ADC_RCC_CLKINT *((uint32_t *)(ADC_RCC_BASE + 0x08)) +#define ADC_RCC_APB2PRST *((uint32_t *)(ADC_RCC_BASE + 0x0c)) +#define ADC_RCC_APB1PRST *((uint32_t *)(ADC_RCC_BASE + 0x10)) +#define ADC_RCC_AHBPCLKEN *((uint32_t *)(ADC_RCC_BASE + 0x14)) +#define ADC_RCC_APB2PCLKEN *((uint32_t *)(ADC_RCC_BASE + 0x18)) +#define ADC_RCC_APB1PCLKEN *((uint32_t *)(ADC_RCC_BASE + 0x1c)) +#define ADC_RCC_BDCTRL *((uint32_t *)(ADC_RCC_BASE + 0x20)) +#define ADC_RCC_CTRLSTS *((uint32_t *)(ADC_RCC_BASE + 0x24)) +#define ADC_RCC_AHBPRST *((uint32_t *)(ADC_RCC_BASE + 0x28)) +#define ADC_RCC_CFG2 *((uint32_t *)(ADC_RCC_BASE + 0x2c)) +#define ADC_RCC_CFG3 *((uint32_t *)(ADC_RCC_BASE + 0x30)) + +/* CFG2 register bit mask */ +#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000) +#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF) +#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000) +#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF) +#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00000400) +#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFFFBFF) +#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0000F800) +#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF) +#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0) +#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F) +#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F) +#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0) + +#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) +#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100) +#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110) +#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120) +#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130) +#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140) +#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150) +#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160) +#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170) +#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180) +#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190) +#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0) +#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0) +#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0) + +#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001) +#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002) +#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003) +#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004) +#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005) +#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006) +#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007) +#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008) +#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008) + +#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00000400) + +#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00000800) +#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00001000) +#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00001800) +#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00002000) +#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00002800) +#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00003000) +#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00003800) +#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00004000) +#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00004800) +#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x00005000) +#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x00005800) +#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x00006000) +#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x00006800) +#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x00007000) +#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x00007800) +#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00008000) +#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00008800) +#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00009000) +#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00009800) +#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x0000A000) +#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x0000A800) +#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x0000B000) +#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x0000B800) +#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x0000C000) +#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x0000C800) +#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0000D000) +#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0000D800) +#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0000E000) +#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0000E800) +#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0000F000) +#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0000F800) + +#define RCC_AHB_PERIPH_ADC1 ((uint32_t)0x00001000) +#define RCC_AHB_PERIPH_ADC2 ((uint32_t)0x00002000) +#define RCC_AHB_PERIPH_ADC3 ((uint32_t)0x00004000) +#define RCC_AHB_PERIPH_ADC4 ((uint32_t)0x00008000) + +#define SAMPT1_SMP_SET ((uint32_t)0x00000007) +#define SAMPT2_SMP_SET ((uint32_t)0x00000007) + +#define SQR4_SEQ_SET ((uint32_t)0x0000001F) +#define SQR3_SEQ_SET ((uint32_t)0x0000001F) +#define SQR2_SEQ_SET ((uint32_t)0x0000001F) +#define SQR1_SEQ_SET ((uint32_t)0x0000001F) + +#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) +#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF) +#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD) + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_11 ((uint8_t)0x0B) +#define ADC_CH_12 ((uint8_t)0x0C) +#define ADC_CH_13 ((uint8_t)0x0D) +#define ADC_CH_14 ((uint8_t)0x0E) +#define ADC_CH_15 ((uint8_t)0x0F) +#define ADC_CH_16 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) + +#define ADC_WORKMODE_INDEPENDENT ((uint32_t)0x00000000) +#define ADC_WORKMODE_REG_INJECT_SIMULT ((uint32_t)0x00010000) +#define ADC_WORKMODE_REG_SIMULT_ALTER_TRIG ((uint32_t)0x00020000) +#define ADC_WORKMODE_INJ_SIMULT_FAST_INTERL ((uint32_t)0x00030000) +#define ADC_WORKMODE_INJ_SIMULT_SLOW_INTERL ((uint32_t)0x00040000) +#define ADC_WORKMODE_INJ_SIMULT ((uint32_t)0x00050000) +#define ADC_WORKMODE_REG_SIMULT ((uint32_t)0x00060000) +#define ADC_WORKMODE_FAST_INTERL ((uint32_t)0x00070000) +#define ADC_WORKMODE_SLOW_INTERL ((uint32_t)0x00080000) +#define ADC_WORKMODE_ALTER_TRIG ((uint32_t)0x00090000) + +#define ADC_EXT_TRIGCONV_T1_CC1 \ + ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T1_CC2 \ + ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T2_CC2 \ + ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T1_CC3 \ + ((uint32_t)0x00040000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_NONE \ + ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */ + +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) +#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) + +#define ADC_FLAG_RDY ((uint8_t)0x20) +#define ADC_FLAG_PD_RDY ((uint8_t)0x40) + +#define CTRL2_AD_ON_SET ((uint32_t)0x00000001) +#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE) + +#define CTRL2_CAL_SET ((uint32_t)0x00000004) + +/* ADC Software start mask */ +#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000) +#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF) + +#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) +#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) +#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) +#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) +#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) +#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) +#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) +#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) + +#define ADC_FLAG_AWDG ((uint8_t)0x01) +#define ADC_FLAG_ENDC ((uint8_t)0x02) +#define ADC_FLAG_JENDC ((uint8_t)0x04) +#define ADC_FLAG_JSTR ((uint8_t)0x08) +#define ADC_FLAG_STR ((uint8_t)0x10) +#define ADC_FLAG_EOC_ANY ((uint8_t)0x20) +#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) + +#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_STS_JENDC \ + ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */ +#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Any end of conversion */ +#define ADC_STS_JENDCA \ + ((uint8_t)0x40) /*!< Any injected channel end of conversion */ + +/* ADC DMA mask */ +#define CTRL2_DMA_SET ((uint32_t)0x00000100) +#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF) + +#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000) +#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) +#define VREF1P2_CTRL (*(uint32_t *)(0x40001800 + 0x20)) +/******************* Bit definition for ADC_CTRL2 register + * ********************/ +#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CTRL2_ENDMA \ + ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CTRL2_EXTJSEL \ + ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select \ + for injected group) */ +#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTJTRIG \ + ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected \ + channels */ + +#define ADC_CTRL2_EXTRSEL \ + ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for \ + regular group) */ +#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CTRL2_EXTRTRIG \ + ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular \ + channels */ +#define ADC_CTRL2_SWSTRJCH \ + ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CTRL2_SWSTRRCH \ + ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CTRL2_TEMPEN \ + ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +#define ADC_CTRL3_VABTMEN_MSK ((uint32_t)0x01L << 11) +#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) +#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) +#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) +#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) +#define ADC_CTRL3_PDRDY_MSK ((uint32_t)0x01L << 6) +#define ADC_CTRL3_RDY_MSK ((uint32_t)0x01L << 5) +#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) +#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) +#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) +#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) + +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +#endif \ No newline at end of file diff --git a/lib/n32g45x/n32g45x_adc.c b/lib/n32g45x/n32g45x_adc.c new file mode 100644 index 000000000000..6621bcb21324 --- /dev/null +++ b/lib/n32g45x/n32g45x_adc.c @@ -0,0 +1,211 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +#include "stdint.h" +#include "n32g45x_adc.h" + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + * @param ADC_InitStruct pointer to an ADC_InitType structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + /*---------------------------- ADCx CTRL1 Configuration -----------------*/ + /* Get the ADCx CTRL1 value */ + tmpreg1 = ADCx->CTRL1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CTRL1_CLR_MASK; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to WorkMode value */ + /* Set SCAN bit according to MultiChEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->WorkMode | ((uint32_t)ADC_InitStruct->MultiChEn << 8)); + /* Write to ADCx CTRL1 */ + ADCx->CTRL1 = tmpreg1; + + /*---------------------------- ADCx CTRL2 Configuration -----------------*/ + /* Get the ADCx CTRL2 value */ + tmpreg1 = ADCx->CTRL2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CTRL2_CLR_MASK; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to DatAlign value */ + /* Set EXTSEL bits according to ExtTrigSelect value */ + /* Set CONT bit according to ContinueConvEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect + | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1)); + /* Write to ADCx CTRL2 */ + ADCx->CTRL2 = tmpreg1; + + /*---------------------------- ADCx RSEQ1 Configuration -----------------*/ + /* Get the ADCx RSEQ1 value */ + tmpreg1 = ADCx->RSEQ1; + /* Clear L bits */ + tmpreg1 &= RSEQ1_CLR_MASK; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ChsNumber value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx RSEQ1 */ + ADCx->RSEQ1 = tmpreg1; +} + + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ + +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ1 = tmpreg1; + } +} + diff --git a/lib/stm32g4/include/stm32g431xx.h b/lib/stm32g4/include/stm32g431xx.h new file mode 100644 index 000000000000..100406bf348b --- /dev/null +++ b/lib/stm32g4/include/stm32g431xx.h @@ -0,0 +1,13128 @@ +/** + ****************************************************************************** + * @file stm32g431xx.h + * @author MCD Application Team + * @brief CMSIS STM32G431xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g431xx + * @{ + */ + +#ifndef __STM32G431xx_H +#define __STM32G431xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 16u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ +#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ +#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ +#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g441xx + * @{ + */ + +#ifndef __STM32G441xx_H +#define __STM32G441xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + AES_IRQn = 85, /*!< AES global interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 16u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ +#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ +#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ +#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g471xx + * @{ + */ + +#ifndef __STM32G471xx_H +#define __STM32G471xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ + I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ + SPI4_IRQn = 84, /*!< SPI4 Event interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ + uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ + __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g473xx + * @{ + */ + +#ifndef __STM32G473xx_H +#define __STM32G473xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + ADC5_IRQn = 62, /*!< ADC5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */ + COMP7_IRQn = 66, /*!< COMP7 Interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ + I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ + SPI4_IRQn = 84, /*!< SPI4 Event interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */ + FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ + uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ + __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL) +#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL) +#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL) +#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL) +#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) +#define COMP5 ((COMP_TypeDef *) COMP5_BASE) +#define COMP6 ((COMP_TypeDef *) COMP6_BASE) +#define COMP7 ((COMP_TypeDef *) COMP7_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) +#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC4 ((ADC_TypeDef *) ADC4_BASE) +#define ADC5 ((ADC_TypeDef *) ADC5_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC2 ((DAC_TypeDef *) DAC2_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define DAC4 ((DAC_TypeDef *) DAC4_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g474xx + * @{ + */ + +#ifndef __STM32G474xx_H +#define __STM32G474xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + ADC5_IRQn = 62, /*!< ADC5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */ + COMP7_IRQn = 66, /*!< COMP7 Interrupt */ + HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupt */ + HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ + HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ + HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */ + HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ + HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ + HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ + HRTIM1_TIMF_IRQn = 74, /*!< HRTIM Timer F global Interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ + I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ + SPI4_IRQn = 84, /*!< SPI4 Event interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */ + FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ + uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ + __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief High resolution Timer (HRTIM) + */ + +#define c7amba_hrtim1_v2_0 + +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to F registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + __IO uint32_t TIMxCR2; /*!< HRTIM Timerx Control register 2, Address offset: 0x6C */ + __IO uint32_t EEFxR3; /*!< HRTIM Timerx external event filtering 3 register, Address offset: 0x70 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x74..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ + __IO uint32_t BDTFUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x74 */ + __IO uint32_t ADCER; /*!< HRTIM ADC Extended Trigger register, Address offset: 0x78 */ + __IO uint32_t ADCUR; /*!< HRTIM ADC Trigger Update register, Address offset: 0x7C */ + __IO uint32_t ADCPS1; /*!< HRTIM ADC Post Scaler Register 1, Address offset: 0x80 */ + __IO uint32_t ADCPS2; /*!< HRTIM ADC Post Scaler Register 2, Address offset: 0x84 */ + __IO uint32_t FLTINR3; /*!< HRTIM Fault input register3, Address offset: 0x88 */ + __IO uint32_t FLTINR4; /*!< HRTIM Fault input register4, Address offset: 0x8C */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[6]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL) +#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL) +#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL) +#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define HRTIM1_BASE (APB2PERIPH_BASE + 0x6800UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x0080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x0100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x0180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x0200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x0280UL) +#define HRTIM1_TIMF_BASE (HRTIM1_BASE + 0x0300UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x0380UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL) +#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) +#define COMP5 ((COMP_TypeDef *) COMP5_BASE) +#define COMP6 ((COMP_TypeDef *) COMP6_BASE) +#define COMP7 ((COMP_TypeDef *) COMP7_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) +#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_TIMF ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMF_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC4 ((ADC_TypeDef *) ADC4_BASE) +#define ADC5 ((ADC_TypeDef *) ADC5_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC2 ((DAC_TypeDef *) DAC2_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define DAC4 ((DAC_TypeDef *) DAC4_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ + +/******************* Bit definition for HRTIM_CPT2R register ****************/ +#define HRTIM_CPT2R_CPT2R_Pos (0U) +#define HRTIM_CPT2R_CPT2R_Msk (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */ +#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture 2 Value */ +#define HRTIM_CPT2R_DIR_Pos (16U) +#define HRTIM_CPT2R_DIR_Msk (0x1UL << HRTIM_CPT2R_DIR_Pos) /*!< 0x00010000 */ +#define HRTIM_CPT2R_DIR HRTIM_CPT2R_DIR_Msk /*!< Capture 2 direction */ + +/******************** Bit definition for Slave Deadtime register **************/ +#define HRTIM_DTR_DTR_Pos (0U) +#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */ +#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */ +#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */ +#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */ +#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */ +#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */ +#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */ +#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */ +#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */ +#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */ +#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */ +#define HRTIM_DTR_SDTR_Pos (9U) +#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */ +#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */ +#define HRTIM_DTR_DTPRSC_Pos (10U) +#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */ +#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */ +#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */ +#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */ +#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */ +#define HRTIM_DTR_DTRSLK_Pos (14U) +#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */ +#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */ +#define HRTIM_DTR_DTRLK_Pos (15U) +#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */ +#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */ +#define HRTIM_DTR_DTF_Pos (16U) +#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */ +#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */ +#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */ +#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */ +#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */ +#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */ +#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */ +#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */ +#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */ +#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */ +#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */ +#define HRTIM_DTR_SDTF_Pos (25U) +#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */ +#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */ +#define HRTIM_DTR_DTFSLK_Pos (30U) +#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */ +#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */ +#define HRTIM_DTR_DTFLK_Pos (31U) +#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */ +#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */ + +/**** Bit definition for Slave Output 1 set register **************************/ +#define HRTIM_SET1R_SST_Pos (0U) +#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */ +#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */ +#define HRTIM_SET1R_RESYNC_Pos (1U) +#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_SET1R_PER_Pos (2U) +#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */ +#define HRTIM_SET1R_CMP1_Pos (3U) +#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_SET1R_CMP2_Pos (4U) +#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_SET1R_CMP3_Pos (5U) +#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_SET1R_CMP4_Pos (6U) +#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_SET1R_MSTPER_Pos (7U) +#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */ +#define HRTIM_SET1R_MSTCMP1_Pos (8U) +#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_SET1R_MSTCMP2_Pos (9U) +#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_SET1R_MSTCMP3_Pos (10U) +#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_SET1R_MSTCMP4_Pos (11U) +#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_SET1R_TIMEVNT1_Pos (12U) +#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_SET1R_TIMEVNT2_Pos (13U) +#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_SET1R_TIMEVNT3_Pos (14U) +#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_SET1R_TIMEVNT4_Pos (15U) +#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_SET1R_TIMEVNT5_Pos (16U) +#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_SET1R_TIMEVNT6_Pos (17U) +#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_SET1R_TIMEVNT7_Pos (18U) +#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_SET1R_TIMEVNT8_Pos (19U) +#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_SET1R_TIMEVNT9_Pos (20U) +#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_SET1R_EXTVNT1_Pos (21U) +#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_SET1R_EXTVNT2_Pos (22U) +#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_SET1R_EXTVNT3_Pos (23U) +#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_SET1R_EXTVNT4_Pos (24U) +#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_SET1R_EXTVNT5_Pos (25U) +#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_SET1R_EXTVNT6_Pos (26U) +#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_SET1R_EXTVNT7_Pos (27U) +#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_SET1R_EXTVNT8_Pos (28U) +#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_SET1R_EXTVNT9_Pos (29U) +#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_SET1R_EXTVNT10_Pos (30U) +#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */ + +#define HRTIM_SET1R_UPDATE_Pos (31U) +#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave Output 1 reset register ************************/ +#define HRTIM_RST1R_SRT_Pos (0U) +#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */ +#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */ +#define HRTIM_RST1R_RESYNC_Pos (1U) +#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_RST1R_PER_Pos (2U) +#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */ +#define HRTIM_RST1R_CMP1_Pos (3U) +#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RST1R_CMP2_Pos (4U) +#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RST1R_CMP3_Pos (5U) +#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_RST1R_CMP4_Pos (6U) +#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_RST1R_MSTPER_Pos (7U) +#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */ +#define HRTIM_RST1R_MSTCMP1_Pos (8U) +#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_RST1R_MSTCMP2_Pos (9U) +#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_RST1R_MSTCMP3_Pos (10U) +#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_RST1R_MSTCMP4_Pos (11U) +#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_RST1R_TIMEVNT1_Pos (12U) +#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_RST1R_TIMEVNT2_Pos (13U) +#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_RST1R_TIMEVNT3_Pos (14U) +#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_RST1R_TIMEVNT4_Pos (15U) +#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_RST1R_TIMEVNT5_Pos (16U) +#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_RST1R_TIMEVNT6_Pos (17U) +#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_RST1R_TIMEVNT7_Pos (18U) +#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_RST1R_TIMEVNT8_Pos (19U) +#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_RST1R_TIMEVNT9_Pos (20U) +#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_RST1R_EXTVNT1_Pos (21U) +#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_RST1R_EXTVNT2_Pos (22U) +#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_RST1R_EXTVNT3_Pos (23U) +#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_RST1R_EXTVNT4_Pos (24U) +#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_RST1R_EXTVNT5_Pos (25U) +#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_RST1R_EXTVNT6_Pos (26U) +#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_RST1R_EXTVNT7_Pos (27U) +#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_RST1R_EXTVNT8_Pos (28U) +#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_RST1R_EXTVNT9_Pos (29U) +#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_RST1R_EXTVNT10_Pos (30U) +#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */ +#define HRTIM_RST1R_UPDATE_Pos (31U) +#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave Output 2 set register **************************/ +#define HRTIM_SET2R_SST_Pos (0U) +#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */ +#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */ +#define HRTIM_SET2R_RESYNC_Pos (1U) +#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_SET2R_PER_Pos (2U) +#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */ +#define HRTIM_SET2R_CMP1_Pos (3U) +#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_SET2R_CMP2_Pos (4U) +#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_SET2R_CMP3_Pos (5U) +#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_SET2R_CMP4_Pos (6U) +#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_SET2R_MSTPER_Pos (7U) +#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */ +#define HRTIM_SET2R_MSTCMP1_Pos (8U) +#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_SET2R_MSTCMP2_Pos (9U) +#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_SET2R_MSTCMP3_Pos (10U) +#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_SET2R_MSTCMP4_Pos (11U) +#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_SET2R_TIMEVNT1_Pos (12U) +#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_SET2R_TIMEVNT2_Pos (13U) +#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_SET2R_TIMEVNT3_Pos (14U) +#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_SET2R_TIMEVNT4_Pos (15U) +#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_SET2R_TIMEVNT5_Pos (16U) +#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_SET2R_TIMEVNT6_Pos (17U) +#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_SET2R_TIMEVNT7_Pos (18U) +#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_SET2R_TIMEVNT8_Pos (19U) +#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_SET2R_TIMEVNT9_Pos (20U) +#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_SET2R_EXTVNT1_Pos (21U) +#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_SET2R_EXTVNT2_Pos (22U) +#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_SET2R_EXTVNT3_Pos (23U) +#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_SET2R_EXTVNT4_Pos (24U) +#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_SET2R_EXTVNT5_Pos (25U) +#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_SET2R_EXTVNT6_Pos (26U) +#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_SET2R_EXTVNT7_Pos (27U) +#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_SET2R_EXTVNT8_Pos (28U) +#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_SET2R_EXTVNT9_Pos (29U) +#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_SET2R_EXTVNT10_Pos (30U) +#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */ + +#define HRTIM_SET2R_UPDATE_Pos (31U) +#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave Output 2 reset register ************************/ +#define HRTIM_RST2R_SRT_Pos (0U) +#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */ +#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */ +#define HRTIM_RST2R_RESYNC_Pos (1U) +#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_RST2R_PER_Pos (2U) +#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */ +#define HRTIM_RST2R_CMP1_Pos (3U) +#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RST2R_CMP2_Pos (4U) +#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RST2R_CMP3_Pos (5U) +#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_RST2R_CMP4_Pos (6U) +#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */ +#define HRTIM_RST2R_MSTPER_Pos (7U) +#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */ +#define HRTIM_RST2R_MSTCMP1_Pos (8U) +#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_RST2R_MSTCMP2_Pos (9U) +#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_RST2R_MSTCMP3_Pos (10U) +#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_RST2R_MSTCMP4_Pos (11U) +#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_RST2R_TIMEVNT1_Pos (12U) +#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_RST2R_TIMEVNT2_Pos (13U) +#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_RST2R_TIMEVNT3_Pos (14U) +#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_RST2R_TIMEVNT4_Pos (15U) +#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_RST2R_TIMEVNT5_Pos (16U) +#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_RST2R_TIMEVNT6_Pos (17U) +#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_RST2R_TIMEVNT7_Pos (18U) +#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_RST2R_TIMEVNT8_Pos (19U) +#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_RST2R_TIMEVNT9_Pos (20U) +#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_RST2R_EXTVNT1_Pos (21U) +#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_RST2R_EXTVNT2_Pos (22U) +#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_RST2R_EXTVNT3_Pos (23U) +#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_RST2R_EXTVNT4_Pos (24U) +#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_RST2R_EXTVNT5_Pos (25U) +#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_RST2R_EXTVNT6_Pos (26U) +#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_RST2R_EXTVNT7_Pos (27U) +#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_RST2R_EXTVNT8_Pos (28U) +#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_RST2R_EXTVNT9_Pos (29U) +#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_RST2R_EXTVNT10_Pos (30U) +#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */ +#define HRTIM_RST2R_UPDATE_Pos (31U) +#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave external event filtering register 1 ***********/ +#define HRTIM_EEFR1_EE1LTCH_Pos (0U) +#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */ +#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */ +#define HRTIM_EEFR1_EE1FLTR_Pos (1U) +#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */ +#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */ +#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */ +#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */ +#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */ +#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */ + +#define HRTIM_EEFR1_EE2LTCH_Pos (6U) +#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */ +#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */ +#define HRTIM_EEFR1_EE2FLTR_Pos (7U) +#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */ +#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */ +#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */ +#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */ +#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */ +#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */ + +#define HRTIM_EEFR1_EE3LTCH_Pos (12U) +#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */ +#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */ +#define HRTIM_EEFR1_EE3FLTR_Pos (13U) +#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */ +#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */ +#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */ +#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */ +#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */ +#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */ + +#define HRTIM_EEFR1_EE4LTCH_Pos (18U) +#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */ +#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */ +#define HRTIM_EEFR1_EE4FLTR_Pos (19U) +#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */ +#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */ +#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */ +#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */ +#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */ +#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */ + +#define HRTIM_EEFR1_EE5LTCH_Pos (24U) +#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */ +#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */ +#define HRTIM_EEFR1_EE5FLTR_Pos (25U) +#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */ +#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */ +#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */ +#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */ +#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */ +#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */ + +/**** Bit definition for Slave external event filtering register 2 ***********/ +#define HRTIM_EEFR2_EE6LTCH_Pos (0U) +#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */ +#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */ +#define HRTIM_EEFR2_EE6FLTR_Pos (1U) +#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */ +#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */ +#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */ +#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */ +#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */ +#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */ + +#define HRTIM_EEFR2_EE7LTCH_Pos (6U) +#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */ +#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */ +#define HRTIM_EEFR2_EE7FLTR_Pos (7U) +#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */ +#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */ +#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */ +#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */ +#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */ +#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */ + +#define HRTIM_EEFR2_EE8LTCH_Pos (12U) +#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */ +#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */ +#define HRTIM_EEFR2_EE8FLTR_Pos (13U) +#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */ +#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */ +#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */ +#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */ +#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */ +#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */ + +#define HRTIM_EEFR2_EE9LTCH_Pos (18U) +#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */ +#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */ +#define HRTIM_EEFR2_EE9FLTR_Pos (19U) +#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */ +#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */ +#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */ +#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */ +#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */ +#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */ + +#define HRTIM_EEFR2_EE10LTCH_Pos (24U) +#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */ +#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */ +#define HRTIM_EEFR2_EE10FLTR_Pos (25U) +#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */ +#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */ +#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */ +#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */ +#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */ +#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */ + +/**** Bit definition for Slave Timer reset register ***************************/ + +#define HRTIM_RSTR_TIMFCMP1_Pos (0U) +#define HRTIM_RSTR_TIMFCMP1_Msk (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos) /*!< 0x00000001 */ +#define HRTIM_RSTR_TIMFCMP1 HRTIM_RSTR_TIMFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_RSTR_UPDATE_Pos (1U) +#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */ +#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */ +#define HRTIM_RSTR_CMP2_Pos (2U) +#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */ +#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */ +#define HRTIM_RSTR_CMP4_Pos (3U) +#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */ +#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */ +#define HRTIM_RSTR_MSTPER_Pos (4U) +#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */ +#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */ +#define HRTIM_RSTR_MSTCMP1_Pos (5U) +#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */ +#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */ +#define HRTIM_RSTR_MSTCMP2_Pos (6U) +#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */ +#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */ +#define HRTIM_RSTR_MSTCMP3_Pos (7U) +#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */ +#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */ +#define HRTIM_RSTR_MSTCMP4_Pos (8U) +#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */ +#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */ +#define HRTIM_RSTR_EXTEVNT1_Pos (9U) +#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */ +#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */ +#define HRTIM_RSTR_EXTEVNT2_Pos (10U) +#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */ +#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */ +#define HRTIM_RSTR_EXTEVNT3_Pos (11U) +#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */ +#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */ +#define HRTIM_RSTR_EXTEVNT4_Pos (12U) +#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */ +#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */ +#define HRTIM_RSTR_EXTEVNT5_Pos (13U) +#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */ +#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */ +#define HRTIM_RSTR_EXTEVNT6_Pos (14U) +#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */ +#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */ +#define HRTIM_RSTR_EXTEVNT7_Pos (15U) +#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */ +#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */ +#define HRTIM_RSTR_EXTEVNT8_Pos (16U) +#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */ +#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */ +#define HRTIM_RSTR_EXTEVNT9_Pos (17U) +#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */ +#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */ +#define HRTIM_RSTR_EXTEVNT10_Pos (18U) +#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */ +#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */ +#define HRTIM_RSTR_TIMBCMP1_Pos (19U) +#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */ +#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_RSTR_TIMBCMP2_Pos (20U) +#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */ +#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_RSTR_TIMBCMP4_Pos (21U) +#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */ +#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */ +#define HRTIM_RSTR_TIMCCMP1_Pos (22U) +#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_RSTR_TIMCCMP2_Pos (23U) +#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */ +#define HRTIM_RSTR_TIMCCMP4_Pos (24U) +#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */ +#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */ +#define HRTIM_RSTR_TIMDCMP1_Pos (25U) +#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_RSTR_TIMDCMP2_Pos (26U) +#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_RSTR_TIMDCMP4_Pos (27U) +#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */ +#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */ +#define HRTIM_RSTR_TIMECMP1_Pos (28U) +#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */ +#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_RSTR_TIMECMP2_Pos (29U) +#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */ +#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_RSTR_TIMECMP4_Pos (30U) +#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */ +#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */ +#define HRTIM_RSTR_TIMFCMP2_Pos (31U) +#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */ +#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */ + +/**** Bit definition for Slave Timer Chopper register *************************/ +#define HRTIM_CHPR_CARFRQ_Pos (0U) +#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */ +#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */ +#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */ +#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */ +#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */ +#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */ + +#define HRTIM_CHPR_CARDTY_Pos (4U) +#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */ +#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */ +#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */ +#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */ +#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */ + +#define HRTIM_CHPR_STRPW_Pos (7U) +#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */ +#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */ +#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */ +#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */ +#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */ +#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */ + +/**** Bit definition for Slave Timer Capture 1 control register ***************/ +#define HRTIM_CPT1CR_SWCPT_Pos (0U) +#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */ +#define HRTIM_CPT1CR_UPDCPT_Pos (1U) +#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */ +#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U) +#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */ +#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U) +#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */ +#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U) +#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */ +#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */ +#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U) +#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */ +#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */ +#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U) +#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */ +#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */ +#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U) +#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */ +#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */ +#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U) +#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */ +#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */ +#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U) +#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */ +#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */ +#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U) +#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */ +#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */ +#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U) +#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */ +#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */ + +#define HRTIM_CPT1CR_TF1SET_Pos (0U) +#define HRTIM_CPT1CR_TF1SET_Msk (0x1UL << HRTIM_CPT1CR_TF1SET_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT1CR_TF1SET HRTIM_CPT1CR_TF1SET_Msk /*!< Timer F output 1 set */ +#define HRTIM_CPT1CR_TF1RST_Pos (1U) +#define HRTIM_CPT1CR_TF1RST_Msk (0x1UL << HRTIM_CPT1CR_TF1RST_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT1CR_TF1RST HRTIM_CPT1CR_TF1RST_Msk /*!< Timer F output 1 reset */ +#define HRTIM_CPT1CR_TIMFCMP1_Pos (2U) +#define HRTIM_CPT1CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT1CR_TIMFCMP1 HRTIM_CPT1CR_TIMFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_CPT1CR_TIMFCMP2_Pos (3U) +#define HRTIM_CPT1CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT1CR_TIMFCMP2 HRTIM_CPT1CR_TIMFCMP2_Msk /*!< Timer F compare 2 */ + +#define HRTIM_CPT1CR_TA1SET_Pos (12U) +#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */ +#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */ +#define HRTIM_CPT1CR_TA1RST_Pos (13U) +#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */ +#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */ +#define HRTIM_CPT1CR_TIMACMP1_Pos (14U) +#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */ +#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_CPT1CR_TIMACMP2_Pos (15U) +#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */ +#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */ + +#define HRTIM_CPT1CR_TB1SET_Pos (16U) +#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */ +#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */ +#define HRTIM_CPT1CR_TB1RST_Pos (17U) +#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */ +#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */ +#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U) +#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */ +#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U) +#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */ +#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */ + +#define HRTIM_CPT1CR_TC1SET_Pos (20U) +#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */ +#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */ +#define HRTIM_CPT1CR_TC1RST_Pos (21U) +#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */ +#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */ +#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U) +#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U) +#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */ + +#define HRTIM_CPT1CR_TD1SET_Pos (24U) +#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */ +#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */ +#define HRTIM_CPT1CR_TD1RST_Pos (25U) +#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */ +#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */ +#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U) +#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */ +#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U) +#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */ +#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */ + +#define HRTIM_CPT1CR_TE1SET_Pos (28U) +#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */ +#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */ +#define HRTIM_CPT1CR_TE1RST_Pos (29U) +#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */ +#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */ +#define HRTIM_CPT1CR_TIMECMP1_Pos (30U) +#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */ +#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_CPT1CR_TIMECMP2_Pos (31U) +#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */ +#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */ + +/**** Bit definition for Slave Timer Capture 2 control register ***************/ +#define HRTIM_CPT2CR_SWCPT_Pos (0U) +#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */ +#define HRTIM_CPT2CR_UPDCPT_Pos (1U) +#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */ +#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U) +#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */ +#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U) +#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */ +#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U) +#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */ +#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */ +#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U) +#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */ +#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */ +#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U) +#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */ +#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */ +#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U) +#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */ +#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */ +#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U) +#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */ +#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */ +#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U) +#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */ +#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */ +#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U) +#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */ +#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */ +#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U) +#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */ +#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */ + +#define HRTIM_CPT2CR_TF1SET_Pos (0U) +#define HRTIM_CPT2CR_TF1SET_Msk (0x1UL << HRTIM_CPT2CR_TF1SET_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT2CR_TF1SET HRTIM_CPT2CR_TF1SET_Msk /*!< Timer F output 1 set */ +#define HRTIM_CPT2CR_TF1RST_Pos (1U) +#define HRTIM_CPT2CR_TF1RST_Msk (0x1UL << HRTIM_CPT2CR_TF1RST_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT2CR_TF1RST HRTIM_CPT2CR_TF1RST_Msk /*!< Timer F output 1 reset */ +#define HRTIM_CPT2CR_TIMFCMP1_Pos (2U) +#define HRTIM_CPT2CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT2CR_TIMFCMP1 HRTIM_CPT2CR_TIMFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_CPT2CR_TIMFCMP2_Pos (3U) +#define HRTIM_CPT2CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT2CR_TIMFCMP2 HRTIM_CPT2CR_TIMFCMP2_Msk /*!< Timer F compare 2 */ + +#define HRTIM_CPT2CR_TA1SET_Pos (12U) +#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */ +#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */ +#define HRTIM_CPT2CR_TA1RST_Pos (13U) +#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */ +#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */ +#define HRTIM_CPT2CR_TIMACMP1_Pos (14U) +#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */ +#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_CPT2CR_TIMACMP2_Pos (15U) +#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */ +#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */ + +#define HRTIM_CPT2CR_TB1SET_Pos (16U) +#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */ +#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */ +#define HRTIM_CPT2CR_TB1RST_Pos (17U) +#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */ +#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */ +#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U) +#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */ +#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U) +#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */ +#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */ + +#define HRTIM_CPT2CR_TC1SET_Pos (20U) +#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */ +#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */ +#define HRTIM_CPT2CR_TC1RST_Pos (21U) +#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */ +#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */ +#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U) +#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U) +#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */ + +#define HRTIM_CPT2CR_TD1SET_Pos (24U) +#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */ +#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */ +#define HRTIM_CPT2CR_TD1RST_Pos (25U) +#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */ +#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */ +#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U) +#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */ +#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U) +#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */ +#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */ + +#define HRTIM_CPT2CR_TE1SET_Pos (28U) +#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */ +#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */ +#define HRTIM_CPT2CR_TE1RST_Pos (29U) +#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */ +#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */ +#define HRTIM_CPT2CR_TIMECMP1_Pos (30U) +#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */ +#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_CPT2CR_TIMECMP2_Pos (31U) +#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */ +#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */ + +/**** Bit definition for Slave Timer Output register **************************/ +#define HRTIM_OUTR_POL1_Pos (1U) +#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */ +#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */ +#define HRTIM_OUTR_IDLM1_Pos (2U) +#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */ +#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */ +#define HRTIM_OUTR_IDLES1_Pos (3U) +#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */ +#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */ +#define HRTIM_OUTR_FAULT1_Pos (4U) +#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */ +#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */ +#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */ +#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */ +#define HRTIM_OUTR_CHP1_Pos (6U) +#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */ +#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */ +#define HRTIM_OUTR_DIDL1_Pos (7U) +#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */ +#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */ + +#define HRTIM_OUTR_DTEN_Pos (8U) +#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */ +#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */ +#define HRTIM_OUTR_DLYPRTEN_Pos (9U) +#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */ +#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */ +#define HRTIM_OUTR_DLYPRT_Pos (10U) +#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */ +#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */ +#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */ +#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */ +#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */ +#define HRTIM_OUTR_BIAR_Pos (14U) +#define HRTIM_OUTR_BIAR_Msk (0x1UL << HRTIM_OUTR_BIAR_Pos) /*!< 0x00004000 */ +#define HRTIM_OUTR_BIAR HRTIM_OUTR_BIAR_Msk /*!< Slave output Balanced Idle Automatic resume */ +#define HRTIM_OUTR_POL2_Pos (17U) +#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */ +#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */ +#define HRTIM_OUTR_IDLM2_Pos (18U) +#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */ +#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */ +#define HRTIM_OUTR_IDLES2_Pos (19U) +#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */ +#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */ +#define HRTIM_OUTR_FAULT2_Pos (20U) +#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */ +#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */ +#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */ +#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */ +#define HRTIM_OUTR_CHP2_Pos (22U) +#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */ +#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */ +#define HRTIM_OUTR_DIDL2_Pos (23U) +#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */ +#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */ + +/**** Bit definition for Timerx Fault register ***************************/ +#define HRTIM_FLTR_FLT1EN_Pos (0U) +#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */ +#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */ +#define HRTIM_FLTR_FLT2EN_Pos (1U) +#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */ +#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */ +#define HRTIM_FLTR_FLT3EN_Pos (2U) +#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */ +#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */ +#define HRTIM_FLTR_FLT4EN_Pos (3U) +#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */ +#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */ +#define HRTIM_FLTR_FLT5EN_Pos (4U) +#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */ +#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */ +#define HRTIM_FLTR_FLT6EN_Pos (5U) +#define HRTIM_FLTR_FLT6EN_Msk (0x1UL << HRTIM_FLTR_FLT6EN_Pos) /*!< 0x00000020 */ +#define HRTIM_FLTR_FLT6EN HRTIM_FLTR_FLT6EN_Msk /*!< Fault 6 enable */ +#define HRTIM_FLTR_FLTLCK_Pos (31U) +#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */ +#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */ + +/**** Bit definition for HRTIM Timerx control register 2 ****************/ +#define HRTIM_TIMCR2_DCDE_Pos (0U) +#define HRTIM_TIMCR2_DCDE_Msk (0x1UL << HRTIM_TIMCR2_DCDE_Pos) /*!< 0x00000001 */ +#define HRTIM_TIMCR2_DCDE HRTIM_TIMCR2_DCDE_Msk /*!< Dual Channel DAC trigger enable */ +#define HRTIM_TIMCR2_DCDS_Pos (1U) +#define HRTIM_TIMCR2_DCDS_Msk (0x1UL << HRTIM_TIMCR2_DCDS_Pos) /*!< 0x00000002 */ +#define HRTIM_TIMCR2_DCDS HRTIM_TIMCR2_DCDS_Msk /*!< Dual Channel DAC step trigger */ +#define HRTIM_TIMCR2_DCDR_Pos (2U) +#define HRTIM_TIMCR2_DCDR_Msk (0x1UL << HRTIM_TIMCR2_DCDR_Pos) /*!< 0x00000004 */ +#define HRTIM_TIMCR2_DCDR HRTIM_TIMCR2_DCDR_Msk /*!< Dual Channel DAC reset trigger */ +#define HRTIM_TIMCR2_UDM_Pos (4U) +#define HRTIM_TIMCR2_UDM_Msk (0x1UL << HRTIM_TIMCR2_UDM_Pos) /*!< 0x00000010 */ +#define HRTIM_TIMCR2_UDM HRTIM_TIMCR2_UDM_Msk /*!< Up-Down Mode*/ +#define HRTIM_TIMCR2_ROM_Pos (6U) +#define HRTIM_TIMCR2_ROM_Msk (0x3UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x000000C0 */ +#define HRTIM_TIMCR2_ROM HRTIM_TIMCR2_ROM_Msk /*!< Roll-over Mode */ +#define HRTIM_TIMCR2_ROM_0 (0x1UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000040 */ +#define HRTIM_TIMCR2_ROM_1 (0x2UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000080 */ +#define HRTIM_TIMCR2_OUTROM_Pos (8U) +#define HRTIM_TIMCR2_OUTROM_Msk (0x3UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000300 */ +#define HRTIM_TIMCR2_OUTROM HRTIM_TIMCR2_OUTROM_Msk /*!< Output Roll-Over Mode */ +#define HRTIM_TIMCR2_OUTROM_0 (0x1UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000100 */ +#define HRTIM_TIMCR2_OUTROM_1 (0x2UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000200 */ +#define HRTIM_TIMCR2_ADROM_Pos (10U) +#define HRTIM_TIMCR2_ADROM_Msk (0x3UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000C00 */ +#define HRTIM_TIMCR2_ADROM HRTIM_TIMCR2_ADROM_Msk /*!< ADC Roll-Over Mode */ +#define HRTIM_TIMCR2_ADROM_0 (0x1UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000400 */ +#define HRTIM_TIMCR2_ADROM_1 (0x2UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000800 */ +#define HRTIM_TIMCR2_BMROM_Pos (12U) +#define HRTIM_TIMCR2_BMROM_Msk (0x3UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00003000 */ +#define HRTIM_TIMCR2_BMROM HRTIM_TIMCR2_BMROM_Msk /*!< Burst Mode Rollover Mode */ +#define HRTIM_TIMCR2_BMROM_0 (0x1UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00001000 */ +#define HRTIM_TIMCR2_BMROM_1 (0x2UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00002000 */ +#define HRTIM_TIMCR2_FEROM_Pos (14U) +#define HRTIM_TIMCR2_FEROM_Msk (0x3UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x0000C000 */ +#define HRTIM_TIMCR2_FEROM HRTIM_TIMCR2_FEROM_Msk /*!< Fault and Event Rollover Mode */ +#define HRTIM_TIMCR2_FEROM_0 (0x1UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00004000 */ +#define HRTIM_TIMCR2_FEROM_1 (0x2UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00008000 */ +#define HRTIM_TIMCR2_GTCMP1_Pos (16U) +#define HRTIM_TIMCR2_GTCMP1_Msk (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos) /*!< 0x00010000 */ +#define HRTIM_TIMCR2_GTCMP1 HRTIM_TIMCR2_GTCMP1_Msk /*!< Greater than Compare 1 PWM mode */ +#define HRTIM_TIMCR2_GTCMP3_Pos (17U) +#define HRTIM_TIMCR2_GTCMP3_Msk (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos) /*!< 0x00020000 */ +#define HRTIM_TIMCR2_GTCMP3 HRTIM_TIMCR2_GTCMP3_Msk /*!< Greater than Compare 3 PWM mode */ +#define HRTIM_TIMCR2_TRGHLF_Pos (20U) +#define HRTIM_TIMCR2_TRGHLF_Msk (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos) /*!< 0x00100000 */ +#define HRTIM_TIMCR2_TRGHLF HRTIM_TIMCR2_TRGHLF_Msk /*!< Triggered-Half mode */ + +/**** Bit definition for Slave external event filtering register 3 ***********/ +#define HRTIM_EEFR3_EEVACE_Pos (0U) +#define HRTIM_EEFR3_EEVACE_Msk (0x1UL << HRTIM_EEFR3_EEVACE_Pos) /*!< 0x00000001 */ +#define HRTIM_EEFR3_EEVACE HRTIM_EEFR3_EEVACE_Msk /*!< External Event A Counter Enable */ +#define HRTIM_EEFR3_EEVACRES_Pos (1U) +#define HRTIM_EEFR3_EEVACRES_Msk (0x1UL << HRTIM_EEFR3_EEVACRES_Pos) /*!< 0x00000002 */ +#define HRTIM_EEFR3_EEVACRES HRTIM_EEFR3_EEVACRES_Msk /*!< External Event A Counter Reset */ +#define HRTIM_EEFR3_EEVARSTM_Pos (2U) +#define HRTIM_EEFR3_EEVARSTM_Msk (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos) /*!< 0x00000004 */ +#define HRTIM_EEFR3_EEVARSTM HRTIM_EEFR3_EEVARSTM_Msk /*!< External Event A Counter Reset Mode */ +#define HRTIM_EEFR3_EEVASEL_Pos (4U) +#define HRTIM_EEFR3_EEVASEL_Msk (0xFUL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x000000F0 */ +#define HRTIM_EEFR3_EEVASEL HRTIM_EEFR3_EEVASEL_Msk /*!< External Event A Selection */ +#define HRTIM_EEFR3_EEVASEL_0 (0x1UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000010 */ +#define HRTIM_EEFR3_EEVASEL_1 (0x2UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000020 */ +#define HRTIM_EEFR3_EEVASEL_2 (0x4UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000040 */ +#define HRTIM_EEFR3_EEVASEL_3 (0x8UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000080 */ +#define HRTIM_EEFR3_EEVACNT_Pos (8U) +#define HRTIM_EEFR3_EEVACNT_Msk (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00003F00 */ +#define HRTIM_EEFR3_EEVACNT HRTIM_EEFR3_EEVACNT_Msk /*!< External Event A Selection */ +#define HRTIM_EEFR3_EEVACNT_0 (0x1UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000100 */ +#define HRTIM_EEFR3_EEVACNT_1 (0x2UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000200 */ +#define HRTIM_EEFR3_EEVACNT_2 (0x4UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000400 */ +#define HRTIM_EEFR3_EEVACNT_3 (0x8UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000800 */ +#define HRTIM_EEFR3_EEVACNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00001000 */ +#define HRTIM_EEFR3_EEVACNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00002000 */ +#define HRTIM_EEFR3_EEVBCE_Pos (16U) +#define HRTIM_EEFR3_EEVBCE_Msk (0x1UL << HRTIM_EEFR3_EEVBCE_Pos) /*!< 0x00010000 */ +#define HRTIM_EEFR3_EEVBCE HRTIM_EEFR3_EEVBCE_Msk /*!< External Event B Counter Enable */ +#define HRTIM_EEFR3_EEVBCRES_Pos (17U) +#define HRTIM_EEFR3_EEVBCRES_Msk (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos) /*!< 0x00020000 */ +#define HRTIM_EEFR3_EEVBCRES HRTIM_EEFR3_EEVBCRES_Msk /*!< External Event B Counter Reset */ +#define HRTIM_EEFR3_EEVBRSTM_Pos (18U) +#define HRTIM_EEFR3_EEVBRSTM_Msk (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos) /*!< 0x00040000 */ +#define HRTIM_EEFR3_EEVBRSTM HRTIM_EEFR3_EEVBRSTM_Msk /*!< External Event B Counter Reset Mode */ +#define HRTIM_EEFR3_EEVBSEL_Pos (20U) +#define HRTIM_EEFR3_EEVBSEL_Msk (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00F00000 */ +#define HRTIM_EEFR3_EEVBSEL HRTIM_EEFR3_EEVBSEL_Msk /*!< External Event B Selection */ +#define HRTIM_EEFR3_EEVBSEL_0 (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00100000 */ +#define HRTIM_EEFR3_EEVBSEL_1 (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00200000 */ +#define HRTIM_EEFR3_EEVBSEL_2 (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00400000 */ +#define HRTIM_EEFR3_EEVBSEL_3 (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00800000 */ +#define HRTIM_EEFR3_EEVBCNT_Pos (24U) +#define HRTIM_EEFR3_EEVBCNT_Msk (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x3F000000 */ +#define HRTIM_EEFR3_EEVBCNT HRTIM_EEFR3_EEVBCNT_Msk /*!< External Event B Counter */ +#define HRTIM_EEFR3_EEVBCNT_0 (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x01000000 */ +#define HRTIM_EEFR3_EEVBCNT_1 (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x02000000 */ +#define HRTIM_EEFR3_EEVBCNT_2 (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x04000000 */ +#define HRTIM_EEFR3_EEVBCNT_3 (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x08000000 */ +#define HRTIM_EEFR3_EEVBCNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x10000000 */ +#define HRTIM_EEFR3_EEVBCNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x20000000 */ + +/**** Bit definition for Common HRTIM Timer control register 1 ****************/ +#define HRTIM_CR1_MUDIS_Pos (0U) +#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */ +#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/ +#define HRTIM_CR1_TAUDIS_Pos (1U) +#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */ +#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/ +#define HRTIM_CR1_TBUDIS_Pos (2U) +#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */ +#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/ +#define HRTIM_CR1_TCUDIS_Pos (3U) +#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */ +#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/ +#define HRTIM_CR1_TDUDIS_Pos (4U) +#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */ +#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/ +#define HRTIM_CR1_TEUDIS_Pos (5U) +#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */ +#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/ +#define HRTIM_CR1_TFUDIS_Pos (6U) +#define HRTIM_CR1_TFUDIS_Msk (0x1UL << HRTIM_CR1_TFUDIS_Pos) /*!< 0x00000040 */ +#define HRTIM_CR1_TFUDIS HRTIM_CR1_TFUDIS_Msk /*!< Timer F update disable*/ +#define HRTIM_CR1_ADC1USRC_Pos (16U) +#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */ +#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */ +#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */ +#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */ +#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */ +#define HRTIM_CR1_ADC2USRC_Pos (19U) +#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */ +#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */ +#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */ +#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */ +#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */ +#define HRTIM_CR1_ADC3USRC_Pos (22U) +#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */ +#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */ +#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */ +#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */ +#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */ +#define HRTIM_CR1_ADC4USRC_Pos (25U) +#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */ +#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */ +#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */ +#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */ +#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */ + +/**** Bit definition for Common HRTIM Timer control register 2 ****************/ +#define HRTIM_CR2_MSWU_Pos (0U) +#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */ +#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */ +#define HRTIM_CR2_TASWU_Pos (1U) +#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */ +#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */ +#define HRTIM_CR2_TBSWU_Pos (2U) +#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */ +#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */ +#define HRTIM_CR2_TCSWU_Pos (3U) +#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */ +#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */ +#define HRTIM_CR2_TDSWU_Pos (4U) +#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */ +#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */ +#define HRTIM_CR2_TESWU_Pos (5U) +#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */ +#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */ +#define HRTIM_CR2_TFSWU_Pos (6U) +#define HRTIM_CR2_TFSWU_Msk (0x1UL << HRTIM_CR2_TFSWU_Pos) /*!< 0x00000040 */ +#define HRTIM_CR2_TFSWU HRTIM_CR2_TFSWU_Msk /*!< Timer F software update */ +#define HRTIM_CR2_MRST_Pos (8U) +#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */ +#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */ +#define HRTIM_CR2_TARST_Pos (9U) +#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */ +#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */ +#define HRTIM_CR2_TBRST_Pos (10U) +#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */ +#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */ +#define HRTIM_CR2_TCRST_Pos (11U) +#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */ +#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */ +#define HRTIM_CR2_TDRST_Pos (12U) +#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */ +#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */ +#define HRTIM_CR2_TERST_Pos (13U) +#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */ +#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */ +#define HRTIM_CR2_TFRST_Pos (14U) +#define HRTIM_CR2_TFRST_Msk (0x1UL << HRTIM_CR2_TFRST_Pos) /*!< 0x00004000 */ +#define HRTIM_CR2_TFRST HRTIM_CR2_TFRST_Msk /*!< Timer F count software reset */ +#define HRTIM_CR2_SWPA_Pos (16U) +#define HRTIM_CR2_SWPA_Msk (0x1UL << HRTIM_CR2_SWPA_Pos) /*!< 0x00010000 */ +#define HRTIM_CR2_SWPA HRTIM_CR2_SWPA_Msk /*!< Timer A swap outputs */ +#define HRTIM_CR2_SWPB_Pos (17U) +#define HRTIM_CR2_SWPB_Msk (0x1UL << HRTIM_CR2_SWPB_Pos) /*!< 0x00020000 */ +#define HRTIM_CR2_SWPB HRTIM_CR2_SWPB_Msk /*!< Timer B swap outputs */ +#define HRTIM_CR2_SWPC_Pos (18U) +#define HRTIM_CR2_SWPC_Msk (0x1UL << HRTIM_CR2_SWPC_Pos) /*!< 0x00040000 */ +#define HRTIM_CR2_SWPC HRTIM_CR2_SWPC_Msk /*!< Timer C swap outputs */ +#define HRTIM_CR2_SWPD_Pos (19U) +#define HRTIM_CR2_SWPD_Msk (0x1UL << HRTIM_CR2_SWPD_Pos) /*!< 0x00080000 */ +#define HRTIM_CR2_SWPD HRTIM_CR2_SWPD_Msk /*!< Timer D swap outputs */ +#define HRTIM_CR2_SWPE_Pos (20U) +#define HRTIM_CR2_SWPE_Msk (0x1UL << HRTIM_CR2_SWPE_Pos) /*!< 0x00100000 */ +#define HRTIM_CR2_SWPE HRTIM_CR2_SWPE_Msk /*!< Timer E swap outputs */ +#define HRTIM_CR2_SWPF_Pos (21U) +#define HRTIM_CR2_SWPF_Msk (0x1UL << HRTIM_CR2_SWPF_Pos) /*!< 0x00200000 */ +#define HRTIM_CR2_SWPF HRTIM_CR2_SWPF_Msk /*!< Timer F swap outputs */ + +/**** Bit definition for Common HRTIM Timer interrupt status register *********/ +#define HRTIM_ISR_FLT1_Pos (0U) +#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */ +#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */ +#define HRTIM_ISR_FLT2_Pos (1U) +#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */ +#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */ +#define HRTIM_ISR_FLT3_Pos (2U) +#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */ +#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */ +#define HRTIM_ISR_FLT4_Pos (3U) +#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */ +#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */ +#define HRTIM_ISR_FLT5_Pos (4U) +#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */ +#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */ +#define HRTIM_ISR_SYSFLT_Pos (5U) +#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */ +#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */ +#define HRTIM_ISR_FLT6_Pos (6U) +#define HRTIM_ISR_FLT6_Msk (0x1UL << HRTIM_ISR_FLT6_Pos) /*!< 0x00000040 */ +#define HRTIM_ISR_FLT6 HRTIM_ISR_FLT6_Msk /*!< Fault 6 interrupt flag */ +#define HRTIM_ISR_DLLRDY_Pos (16U) +#define HRTIM_ISR_DLLRDY_Msk (0x1UL << HRTIM_ISR_DLLRDY_Pos) /*!< 0x00010000 */ +#define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk /*!< DLL ready interrupt flag */ +#define HRTIM_ISR_BMPER_Pos (17U) +#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */ +#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */ + +/**** Bit definition for Common HRTIM Timer interrupt clear register **********/ +#define HRTIM_ICR_FLT1C_Pos (0U) +#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */ +#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */ +#define HRTIM_ICR_FLT2C_Pos (1U) +#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */ +#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */ +#define HRTIM_ICR_FLT3C_Pos (2U) +#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */ +#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */ +#define HRTIM_ICR_FLT4C_Pos (3U) +#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */ +#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */ +#define HRTIM_ICR_FLT5C_Pos (4U) +#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */ +#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */ +#define HRTIM_ICR_SYSFLTC_Pos (5U) +#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */ +#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */ + +#define HRTIM_ICR_FLT6C_Pos (6U) +#define HRTIM_ICR_FLT6C_Msk (0x1UL << HRTIM_ICR_FLT6C_Pos) /*!< 0x00000040 */ +#define HRTIM_ICR_FLT6C HRTIM_ICR_FLT6C_Msk /*!< Fault 6 interrupt flag clear */ + +#define HRTIM_ICR_DLLRDYC_Pos (16U) +#define HRTIM_ICR_DLLRDYC_Msk (0x1UL << HRTIM_ICR_DLLRDYC_Pos) /*!< 0x00010000 */ +#define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk /*!< DLL ready interrupt flag clear */ +#define HRTIM_ICR_BMPERC_Pos (17U) +#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */ +#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */ + +/**** Bit definition for Common HRTIM Timer interrupt enable register *********/ +#define HRTIM_IER_FLT1_Pos (0U) +#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */ +#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */ +#define HRTIM_IER_FLT2_Pos (1U) +#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */ +#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */ +#define HRTIM_IER_FLT3_Pos (2U) +#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */ +#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */ +#define HRTIM_IER_FLT4_Pos (3U) +#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */ +#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */ +#define HRTIM_IER_FLT5_Pos (4U) +#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */ +#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */ +#define HRTIM_IER_SYSFLT_Pos (5U) +#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */ +#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */ +#define HRTIM_IER_FLT6_Pos (6U) +#define HRTIM_IER_FLT6_Msk (0x1UL << HRTIM_IER_FLT6_Pos) /*!< 0x00000040 */ +#define HRTIM_IER_FLT6 HRTIM_IER_FLT6_Msk /*!< Fault 6 interrupt enable */ + +#define HRTIM_IER_DLLRDY_Pos (16U) +#define HRTIM_IER_DLLRDY_Msk (0x1UL << HRTIM_IER_DLLRDY_Pos) /*!< 0x00010000 */ +#define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk /*!< DLL ready interrupt enable */ +#define HRTIM_IER_BMPER_Pos (17U) +#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */ +#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */ + +/**** Bit definition for Common HRTIM Timer output enable register ************/ +#define HRTIM_OENR_TA1OEN_Pos (0U) +#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */ +#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */ +#define HRTIM_OENR_TA2OEN_Pos (1U) +#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */ +#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */ +#define HRTIM_OENR_TB1OEN_Pos (2U) +#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */ +#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */ +#define HRTIM_OENR_TB2OEN_Pos (3U) +#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */ +#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */ +#define HRTIM_OENR_TC1OEN_Pos (4U) +#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */ +#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */ +#define HRTIM_OENR_TC2OEN_Pos (5U) +#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */ +#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */ +#define HRTIM_OENR_TD1OEN_Pos (6U) +#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */ +#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */ +#define HRTIM_OENR_TD2OEN_Pos (7U) +#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */ +#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */ +#define HRTIM_OENR_TE1OEN_Pos (8U) +#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */ +#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */ +#define HRTIM_OENR_TE2OEN_Pos (9U) +#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */ +#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */ +#define HRTIM_OENR_TF1OEN_Pos (10U) +#define HRTIM_OENR_TF1OEN_Msk (0x1UL << HRTIM_OENR_TF1OEN_Pos) /*!< 0x00000400 */ +#define HRTIM_OENR_TF1OEN HRTIM_OENR_TF1OEN_Msk /*!< Timer F Output 1 enable */ +#define HRTIM_OENR_TF2OEN_Pos (11U) +#define HRTIM_OENR_TF2OEN_Msk (0x1UL << HRTIM_OENR_TF2OEN_Pos) /*!< 0x00000800 */ +#define HRTIM_OENR_TF2OEN HRTIM_OENR_TF2OEN_Msk /*!< Timer F Output 2 enable */ + +/**** Bit definition for Common HRTIM Timer output disable register ***********/ +#define HRTIM_ODISR_TA1ODIS_Pos (0U) +#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */ +#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */ +#define HRTIM_ODISR_TA2ODIS_Pos (1U) +#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */ +#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */ +#define HRTIM_ODISR_TB1ODIS_Pos (2U) +#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */ +#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */ +#define HRTIM_ODISR_TB2ODIS_Pos (3U) +#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */ +#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */ +#define HRTIM_ODISR_TC1ODIS_Pos (4U) +#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */ +#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */ +#define HRTIM_ODISR_TC2ODIS_Pos (5U) +#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */ +#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */ +#define HRTIM_ODISR_TD1ODIS_Pos (6U) +#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */ +#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */ +#define HRTIM_ODISR_TD2ODIS_Pos (7U) +#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */ +#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */ +#define HRTIM_ODISR_TE1ODIS_Pos (8U) +#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */ +#define HRTIM_ODISR_TE2ODIS_Pos (9U) +#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */ +#define HRTIM_ODISR_TF1ODIS_Pos (10U) +#define HRTIM_ODISR_TF1ODIS_Msk (0x1UL << HRTIM_ODISR_TF1ODIS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODISR_TF1ODIS HRTIM_ODISR_TF1ODIS_Msk /*!< Timer F Output 1 disable */ +#define HRTIM_ODISR_TF2ODIS_Pos (11U) +#define HRTIM_ODISR_TF2ODIS_Msk (0x1UL << HRTIM_ODISR_TF2ODIS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODISR_TF2ODIS HRTIM_ODISR_TF2ODIS_Msk /*!< Timer F Output 2 disable */ + +/**** Bit definition for Common HRTIM Timer output disable status register *****/ +#define HRTIM_ODSR_TA1ODS_Pos (0U) +#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */ +#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */ +#define HRTIM_ODSR_TA2ODS_Pos (1U) +#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */ +#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */ +#define HRTIM_ODSR_TB1ODS_Pos (2U) +#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */ +#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */ +#define HRTIM_ODSR_TB2ODS_Pos (3U) +#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */ +#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */ +#define HRTIM_ODSR_TC1ODS_Pos (4U) +#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */ +#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */ +#define HRTIM_ODSR_TC2ODS_Pos (5U) +#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */ +#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */ +#define HRTIM_ODSR_TD1ODS_Pos (6U) +#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */ +#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */ +#define HRTIM_ODSR_TD2ODS_Pos (7U) +#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */ +#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */ +#define HRTIM_ODSR_TE1ODS_Pos (8U) +#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */ +#define HRTIM_ODSR_TE2ODS_Pos (9U) +#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */ +#define HRTIM_ODSR_TF1ODS_Pos (10U) +#define HRTIM_ODSR_TF1ODS_Msk (0x1UL << HRTIM_ODSR_TF1ODS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODSR_TF1ODS HRTIM_ODSR_TF1ODS_Msk /*!< Timer F Output 1 disable status */ +#define HRTIM_ODSR_TF2ODS_Pos (11U) +#define HRTIM_ODSR_TF2ODS_Msk (0x1UL << HRTIM_ODSR_TF2ODS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODSR_TF2ODS HRTIM_ODSR_TF2ODS_Msk /*!< Timer F Output 2 disable status */ + +/**** Bit definition for Common HRTIM Timer Burst mode control register ********/ +#define HRTIM_BMCR_BME_Pos (0U) +#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */ +#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */ +#define HRTIM_BMCR_BMOM_Pos (1U) +#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */ +#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */ +#define HRTIM_BMCR_BMCLK_Pos (2U) +#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */ +#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */ +#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */ +#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */ +#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */ +#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */ +#define HRTIM_BMCR_BMPRSC_Pos (6U) +#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */ +#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */ +#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */ +#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */ +#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */ +#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */ +#define HRTIM_BMCR_BMPREN_Pos (10U) +#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */ +#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */ +#define HRTIM_BMCR_MTBM_Pos (16U) +#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */ +#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */ +#define HRTIM_BMCR_TABM_Pos (17U) +#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */ +#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */ +#define HRTIM_BMCR_TBBM_Pos (18U) +#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */ +#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */ +#define HRTIM_BMCR_TCBM_Pos (19U) +#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */ +#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */ +#define HRTIM_BMCR_TDBM_Pos (20U) +#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */ +#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */ +#define HRTIM_BMCR_TEBM_Pos (21U) +#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */ +#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */ + +#define HRTIM_BMCR_TFBM_Pos (22U) +#define HRTIM_BMCR_TFBM_Msk (0x1UL << HRTIM_BMCR_TFBM_Pos) /*!< 0x00400000 */ +#define HRTIM_BMCR_TFBM HRTIM_BMCR_TFBM_Msk /*!< Timer F Burst mode */ + +#define HRTIM_BMCR_BMSTAT_Pos (31U) +#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */ +#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */ + +/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/ +#define HRTIM_BMTRGR_SW_Pos (0U) +#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */ +#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */ +#define HRTIM_BMTRGR_MSTRST_Pos (1U) +#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */ +#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */ +#define HRTIM_BMTRGR_MSTREP_Pos (2U) +#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */ +#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */ +#define HRTIM_BMTRGR_MSTCMP1_Pos (3U) +#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_BMTRGR_MSTCMP2_Pos (4U) +#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_BMTRGR_MSTCMP3_Pos (5U) +#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_BMTRGR_MSTCMP4_Pos (6U) +#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */ +#define HRTIM_BMTRGR_TARST_Pos (7U) +#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */ +#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */ +#define HRTIM_BMTRGR_TAREP_Pos (8U) +#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */ +#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */ +#define HRTIM_BMTRGR_TACMP1_Pos (9U) +#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */ +#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_BMTRGR_TACMP2_Pos (10U) +#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */ +#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_BMTRGR_TBRST_Pos (11U) +#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */ +#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */ +#define HRTIM_BMTRGR_TBREP_Pos (12U) +#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */ +#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */ +#define HRTIM_BMTRGR_TBCMP1_Pos (13U) +#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */ +#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_BMTRGR_TBCMP2_Pos (14U) +#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */ +#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_BMTRGR_TCRST_Pos (15U) +#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */ +#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */ +#define HRTIM_BMTRGR_TCREP_Pos (16U) +#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */ +#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */ +#define HRTIM_BMTRGR_TCCMP1_Pos (17U) +#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */ +#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_BMTRGR_TFRST_Pos (18U) +#define HRTIM_BMTRGR_TFRST_Msk (0x1UL << HRTIM_BMTRGR_TFRST_Pos) /*!< 0x00040000 */ +#define HRTIM_BMTRGR_TFRST HRTIM_BMTRGR_TFRST_Msk /*!< Timer F reset */ +#define HRTIM_BMTRGR_TDRST_Pos (19U) +#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */ +#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */ +#define HRTIM_BMTRGR_TDREP_Pos (20U) +#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */ +#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */ +#define HRTIM_BMTRGR_TFREP_Pos (21U) +#define HRTIM_BMTRGR_TFREP_Msk (0x1UL << HRTIM_BMTRGR_TFREP_Pos) /*!< 0x00200000 */ +#define HRTIM_BMTRGR_TFREP HRTIM_BMTRGR_TFREP_Msk /*!< Timer F repetition*/ +#define HRTIM_BMTRGR_TDCMP2_Pos (22U) +#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */ +#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_BMTRGR_TFCMP1_Pos (23U) +#define HRTIM_BMTRGR_TFCMP1_Msk (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos) /*!< 0x00800000 */ +#define HRTIM_BMTRGR_TFCMP1 HRTIM_BMTRGR_TFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_BMTRGR_TEREP_Pos (24U) +#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */ +#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */ +#define HRTIM_BMTRGR_TECMP1_Pos (25U) +#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_BMTRGR_TECMP2_Pos (26U) +#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_BMTRGR_TAEEV7_Pos (27U) +#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */ +#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */ +#define HRTIM_BMTRGR_TDEEV8_Pos (28U) +#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */ +#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */ +#define HRTIM_BMTRGR_EEV7_Pos (29U) +#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */ +#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */ +#define HRTIM_BMTRGR_EEV8_Pos (30U) +#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */ +#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */ +#define HRTIM_BMTRGR_OCHPEV_Pos (31U) +#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */ +#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */ + +/******************* Bit definition for HRTIM_BMCMPR register ***************/ +#define HRTIM_BMCMPR_BMCMPR_Pos (0U) +#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */ +#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g483xx + * @{ + */ + +#ifndef __STM32G483xx_H +#define __STM32G483xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + ADC5_IRQn = 62, /*!< ADC5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */ + COMP7_IRQn = 66, /*!< COMP7 Interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ + I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ + SPI4_IRQn = 84, /*!< SPI4 Event interrupt */ + AES_IRQn = 85, /*!< AES global interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */ + FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ + uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ + __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL) +#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL) +#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL) +#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL) +#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) +#define COMP5 ((COMP_TypeDef *) COMP5_BASE) +#define COMP6 ((COMP_TypeDef *) COMP6_BASE) +#define COMP7 ((COMP_TypeDef *) COMP7_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) +#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC4 ((ADC_TypeDef *) ADC4_BASE) +#define ADC5 ((ADC_TypeDef *) ADC5_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC2 ((DAC_TypeDef *) DAC2_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define DAC4 ((DAC_TypeDef *) DAC4_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g484xx + * @{ + */ + +#ifndef __STM32G484xx_H +#define __STM32G484xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + ADC5_IRQn = 62, /*!< ADC5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */ + COMP7_IRQn = 66, /*!< COMP7 Interrupt */ + HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupt */ + HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ + HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ + HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */ + HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ + HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ + HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ + HRTIM1_TIMF_IRQn = 74, /*!< HRTIM Timer F global Interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ + I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ + SPI4_IRQn = 84, /*!< SPI4 Event interrupt */ + AES_IRQn = 85, /*!< AES global interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */ + FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ + uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ + __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief High resolution Timer (HRTIM) + */ + +#define c7amba_hrtim1_v2_0 + +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to F registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + __IO uint32_t TIMxCR2; /*!< HRTIM Timerx Control register 2, Address offset: 0x6C */ + __IO uint32_t EEFxR3; /*!< HRTIM Timerx external event filtering 3 register, Address offset: 0x70 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x74..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ + __IO uint32_t BDTFUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x74 */ + __IO uint32_t ADCER; /*!< HRTIM ADC Extended Trigger register, Address offset: 0x78 */ + __IO uint32_t ADCUR; /*!< HRTIM ADC Trigger Update register, Address offset: 0x7C */ + __IO uint32_t ADCPS1; /*!< HRTIM ADC Post Scaler Register 1, Address offset: 0x80 */ + __IO uint32_t ADCPS2; /*!< HRTIM ADC Post Scaler Register 2, Address offset: 0x84 */ + __IO uint32_t FLTINR3; /*!< HRTIM Fault input register3, Address offset: 0x88 */ + __IO uint32_t FLTINR4; /*!< HRTIM Fault input register4, Address offset: 0x8C */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[6]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL) +#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL) +#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL) +#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define HRTIM1_BASE (APB2PERIPH_BASE + 0x6800UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x0080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x0100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x0180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x0200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x0280UL) +#define HRTIM1_TIMF_BASE (HRTIM1_BASE + 0x0300UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x0380UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL) +#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) +#define COMP5 ((COMP_TypeDef *) COMP5_BASE) +#define COMP6 ((COMP_TypeDef *) COMP6_BASE) +#define COMP7 ((COMP_TypeDef *) COMP7_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) +#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_TIMF ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMF_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC4 ((ADC_TypeDef *) ADC4_BASE) +#define ADC5 ((ADC_TypeDef *) ADC5_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC2 ((DAC_TypeDef *) DAC2_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define DAC4 ((DAC_TypeDef *) DAC4_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ + +/******************* Bit definition for HRTIM_CPT2R register ****************/ +#define HRTIM_CPT2R_CPT2R_Pos (0U) +#define HRTIM_CPT2R_CPT2R_Msk (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */ +#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture 2 Value */ +#define HRTIM_CPT2R_DIR_Pos (16U) +#define HRTIM_CPT2R_DIR_Msk (0x1UL << HRTIM_CPT2R_DIR_Pos) /*!< 0x00010000 */ +#define HRTIM_CPT2R_DIR HRTIM_CPT2R_DIR_Msk /*!< Capture 2 direction */ + +/******************** Bit definition for Slave Deadtime register **************/ +#define HRTIM_DTR_DTR_Pos (0U) +#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */ +#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */ +#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */ +#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */ +#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */ +#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */ +#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */ +#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */ +#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */ +#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */ +#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */ +#define HRTIM_DTR_SDTR_Pos (9U) +#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */ +#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */ +#define HRTIM_DTR_DTPRSC_Pos (10U) +#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */ +#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */ +#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */ +#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */ +#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */ +#define HRTIM_DTR_DTRSLK_Pos (14U) +#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */ +#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */ +#define HRTIM_DTR_DTRLK_Pos (15U) +#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */ +#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */ +#define HRTIM_DTR_DTF_Pos (16U) +#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */ +#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */ +#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */ +#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */ +#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */ +#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */ +#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */ +#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */ +#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */ +#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */ +#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */ +#define HRTIM_DTR_SDTF_Pos (25U) +#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */ +#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */ +#define HRTIM_DTR_DTFSLK_Pos (30U) +#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */ +#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */ +#define HRTIM_DTR_DTFLK_Pos (31U) +#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */ +#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */ + +/**** Bit definition for Slave Output 1 set register **************************/ +#define HRTIM_SET1R_SST_Pos (0U) +#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */ +#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */ +#define HRTIM_SET1R_RESYNC_Pos (1U) +#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_SET1R_PER_Pos (2U) +#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */ +#define HRTIM_SET1R_CMP1_Pos (3U) +#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_SET1R_CMP2_Pos (4U) +#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_SET1R_CMP3_Pos (5U) +#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_SET1R_CMP4_Pos (6U) +#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_SET1R_MSTPER_Pos (7U) +#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */ +#define HRTIM_SET1R_MSTCMP1_Pos (8U) +#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_SET1R_MSTCMP2_Pos (9U) +#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_SET1R_MSTCMP3_Pos (10U) +#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_SET1R_MSTCMP4_Pos (11U) +#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_SET1R_TIMEVNT1_Pos (12U) +#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_SET1R_TIMEVNT2_Pos (13U) +#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_SET1R_TIMEVNT3_Pos (14U) +#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_SET1R_TIMEVNT4_Pos (15U) +#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_SET1R_TIMEVNT5_Pos (16U) +#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_SET1R_TIMEVNT6_Pos (17U) +#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_SET1R_TIMEVNT7_Pos (18U) +#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_SET1R_TIMEVNT8_Pos (19U) +#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_SET1R_TIMEVNT9_Pos (20U) +#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_SET1R_EXTVNT1_Pos (21U) +#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_SET1R_EXTVNT2_Pos (22U) +#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_SET1R_EXTVNT3_Pos (23U) +#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_SET1R_EXTVNT4_Pos (24U) +#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_SET1R_EXTVNT5_Pos (25U) +#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_SET1R_EXTVNT6_Pos (26U) +#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_SET1R_EXTVNT7_Pos (27U) +#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_SET1R_EXTVNT8_Pos (28U) +#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_SET1R_EXTVNT9_Pos (29U) +#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_SET1R_EXTVNT10_Pos (30U) +#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */ + +#define HRTIM_SET1R_UPDATE_Pos (31U) +#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave Output 1 reset register ************************/ +#define HRTIM_RST1R_SRT_Pos (0U) +#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */ +#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */ +#define HRTIM_RST1R_RESYNC_Pos (1U) +#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_RST1R_PER_Pos (2U) +#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */ +#define HRTIM_RST1R_CMP1_Pos (3U) +#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RST1R_CMP2_Pos (4U) +#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RST1R_CMP3_Pos (5U) +#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_RST1R_CMP4_Pos (6U) +#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_RST1R_MSTPER_Pos (7U) +#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */ +#define HRTIM_RST1R_MSTCMP1_Pos (8U) +#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_RST1R_MSTCMP2_Pos (9U) +#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_RST1R_MSTCMP3_Pos (10U) +#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_RST1R_MSTCMP4_Pos (11U) +#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_RST1R_TIMEVNT1_Pos (12U) +#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_RST1R_TIMEVNT2_Pos (13U) +#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_RST1R_TIMEVNT3_Pos (14U) +#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_RST1R_TIMEVNT4_Pos (15U) +#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_RST1R_TIMEVNT5_Pos (16U) +#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_RST1R_TIMEVNT6_Pos (17U) +#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_RST1R_TIMEVNT7_Pos (18U) +#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_RST1R_TIMEVNT8_Pos (19U) +#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_RST1R_TIMEVNT9_Pos (20U) +#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_RST1R_EXTVNT1_Pos (21U) +#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_RST1R_EXTVNT2_Pos (22U) +#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_RST1R_EXTVNT3_Pos (23U) +#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_RST1R_EXTVNT4_Pos (24U) +#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_RST1R_EXTVNT5_Pos (25U) +#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_RST1R_EXTVNT6_Pos (26U) +#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_RST1R_EXTVNT7_Pos (27U) +#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_RST1R_EXTVNT8_Pos (28U) +#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_RST1R_EXTVNT9_Pos (29U) +#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_RST1R_EXTVNT10_Pos (30U) +#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */ +#define HRTIM_RST1R_UPDATE_Pos (31U) +#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave Output 2 set register **************************/ +#define HRTIM_SET2R_SST_Pos (0U) +#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */ +#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */ +#define HRTIM_SET2R_RESYNC_Pos (1U) +#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_SET2R_PER_Pos (2U) +#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */ +#define HRTIM_SET2R_CMP1_Pos (3U) +#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_SET2R_CMP2_Pos (4U) +#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_SET2R_CMP3_Pos (5U) +#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_SET2R_CMP4_Pos (6U) +#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_SET2R_MSTPER_Pos (7U) +#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */ +#define HRTIM_SET2R_MSTCMP1_Pos (8U) +#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_SET2R_MSTCMP2_Pos (9U) +#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_SET2R_MSTCMP3_Pos (10U) +#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_SET2R_MSTCMP4_Pos (11U) +#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_SET2R_TIMEVNT1_Pos (12U) +#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_SET2R_TIMEVNT2_Pos (13U) +#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_SET2R_TIMEVNT3_Pos (14U) +#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_SET2R_TIMEVNT4_Pos (15U) +#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_SET2R_TIMEVNT5_Pos (16U) +#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_SET2R_TIMEVNT6_Pos (17U) +#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_SET2R_TIMEVNT7_Pos (18U) +#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_SET2R_TIMEVNT8_Pos (19U) +#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_SET2R_TIMEVNT9_Pos (20U) +#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_SET2R_EXTVNT1_Pos (21U) +#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_SET2R_EXTVNT2_Pos (22U) +#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_SET2R_EXTVNT3_Pos (23U) +#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_SET2R_EXTVNT4_Pos (24U) +#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_SET2R_EXTVNT5_Pos (25U) +#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_SET2R_EXTVNT6_Pos (26U) +#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_SET2R_EXTVNT7_Pos (27U) +#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_SET2R_EXTVNT8_Pos (28U) +#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_SET2R_EXTVNT9_Pos (29U) +#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_SET2R_EXTVNT10_Pos (30U) +#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */ + +#define HRTIM_SET2R_UPDATE_Pos (31U) +#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave Output 2 reset register ************************/ +#define HRTIM_RST2R_SRT_Pos (0U) +#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */ +#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */ +#define HRTIM_RST2R_RESYNC_Pos (1U) +#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */ +#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */ +#define HRTIM_RST2R_PER_Pos (2U) +#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */ +#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */ +#define HRTIM_RST2R_CMP1_Pos (3U) +#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RST2R_CMP2_Pos (4U) +#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RST2R_CMP3_Pos (5U) +#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */ +#define HRTIM_RST2R_CMP4_Pos (6U) +#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */ +#define HRTIM_RST2R_MSTPER_Pos (7U) +#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */ +#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */ +#define HRTIM_RST2R_MSTCMP1_Pos (8U) +#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */ +#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_RST2R_MSTCMP2_Pos (9U) +#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */ +#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_RST2R_MSTCMP3_Pos (10U) +#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */ +#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_RST2R_MSTCMP4_Pos (11U) +#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */ +#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */ + +#define HRTIM_RST2R_TIMEVNT1_Pos (12U) +#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */ +#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */ +#define HRTIM_RST2R_TIMEVNT2_Pos (13U) +#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */ +#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */ +#define HRTIM_RST2R_TIMEVNT3_Pos (14U) +#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */ +#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */ +#define HRTIM_RST2R_TIMEVNT4_Pos (15U) +#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */ +#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */ +#define HRTIM_RST2R_TIMEVNT5_Pos (16U) +#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */ +#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */ +#define HRTIM_RST2R_TIMEVNT6_Pos (17U) +#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */ +#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */ +#define HRTIM_RST2R_TIMEVNT7_Pos (18U) +#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */ +#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */ +#define HRTIM_RST2R_TIMEVNT8_Pos (19U) +#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */ +#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */ +#define HRTIM_RST2R_TIMEVNT9_Pos (20U) +#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */ +#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */ + +#define HRTIM_RST2R_EXTVNT1_Pos (21U) +#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */ +#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */ +#define HRTIM_RST2R_EXTVNT2_Pos (22U) +#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */ +#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */ +#define HRTIM_RST2R_EXTVNT3_Pos (23U) +#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */ +#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */ +#define HRTIM_RST2R_EXTVNT4_Pos (24U) +#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */ +#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */ +#define HRTIM_RST2R_EXTVNT5_Pos (25U) +#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */ +#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */ +#define HRTIM_RST2R_EXTVNT6_Pos (26U) +#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */ +#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */ +#define HRTIM_RST2R_EXTVNT7_Pos (27U) +#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */ +#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */ +#define HRTIM_RST2R_EXTVNT8_Pos (28U) +#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */ +#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */ +#define HRTIM_RST2R_EXTVNT9_Pos (29U) +#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */ +#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */ +#define HRTIM_RST2R_EXTVNT10_Pos (30U) +#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */ +#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */ +#define HRTIM_RST2R_UPDATE_Pos (31U) +#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */ +#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */ + +/**** Bit definition for Slave external event filtering register 1 ***********/ +#define HRTIM_EEFR1_EE1LTCH_Pos (0U) +#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */ +#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */ +#define HRTIM_EEFR1_EE1FLTR_Pos (1U) +#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */ +#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */ +#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */ +#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */ +#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */ +#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */ + +#define HRTIM_EEFR1_EE2LTCH_Pos (6U) +#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */ +#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */ +#define HRTIM_EEFR1_EE2FLTR_Pos (7U) +#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */ +#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */ +#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */ +#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */ +#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */ +#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */ + +#define HRTIM_EEFR1_EE3LTCH_Pos (12U) +#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */ +#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */ +#define HRTIM_EEFR1_EE3FLTR_Pos (13U) +#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */ +#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */ +#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */ +#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */ +#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */ +#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */ + +#define HRTIM_EEFR1_EE4LTCH_Pos (18U) +#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */ +#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */ +#define HRTIM_EEFR1_EE4FLTR_Pos (19U) +#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */ +#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */ +#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */ +#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */ +#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */ +#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */ + +#define HRTIM_EEFR1_EE5LTCH_Pos (24U) +#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */ +#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */ +#define HRTIM_EEFR1_EE5FLTR_Pos (25U) +#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */ +#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */ +#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */ +#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */ +#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */ +#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */ + +/**** Bit definition for Slave external event filtering register 2 ***********/ +#define HRTIM_EEFR2_EE6LTCH_Pos (0U) +#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */ +#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */ +#define HRTIM_EEFR2_EE6FLTR_Pos (1U) +#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */ +#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */ +#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */ +#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */ +#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */ +#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */ + +#define HRTIM_EEFR2_EE7LTCH_Pos (6U) +#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */ +#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */ +#define HRTIM_EEFR2_EE7FLTR_Pos (7U) +#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */ +#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */ +#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */ +#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */ +#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */ +#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */ + +#define HRTIM_EEFR2_EE8LTCH_Pos (12U) +#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */ +#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */ +#define HRTIM_EEFR2_EE8FLTR_Pos (13U) +#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */ +#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */ +#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */ +#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */ +#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */ +#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */ + +#define HRTIM_EEFR2_EE9LTCH_Pos (18U) +#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */ +#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */ +#define HRTIM_EEFR2_EE9FLTR_Pos (19U) +#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */ +#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */ +#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */ +#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */ +#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */ +#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */ + +#define HRTIM_EEFR2_EE10LTCH_Pos (24U) +#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */ +#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */ +#define HRTIM_EEFR2_EE10FLTR_Pos (25U) +#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */ +#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */ +#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */ +#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */ +#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */ +#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */ + +/**** Bit definition for Slave Timer reset register ***************************/ + +#define HRTIM_RSTR_TIMFCMP1_Pos (0U) +#define HRTIM_RSTR_TIMFCMP1_Msk (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos) /*!< 0x00000001 */ +#define HRTIM_RSTR_TIMFCMP1 HRTIM_RSTR_TIMFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_RSTR_UPDATE_Pos (1U) +#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */ +#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */ +#define HRTIM_RSTR_CMP2_Pos (2U) +#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */ +#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */ +#define HRTIM_RSTR_CMP4_Pos (3U) +#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */ +#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */ +#define HRTIM_RSTR_MSTPER_Pos (4U) +#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */ +#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */ +#define HRTIM_RSTR_MSTCMP1_Pos (5U) +#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */ +#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */ +#define HRTIM_RSTR_MSTCMP2_Pos (6U) +#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */ +#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */ +#define HRTIM_RSTR_MSTCMP3_Pos (7U) +#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */ +#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */ +#define HRTIM_RSTR_MSTCMP4_Pos (8U) +#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */ +#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */ +#define HRTIM_RSTR_EXTEVNT1_Pos (9U) +#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */ +#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */ +#define HRTIM_RSTR_EXTEVNT2_Pos (10U) +#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */ +#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */ +#define HRTIM_RSTR_EXTEVNT3_Pos (11U) +#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */ +#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */ +#define HRTIM_RSTR_EXTEVNT4_Pos (12U) +#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */ +#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */ +#define HRTIM_RSTR_EXTEVNT5_Pos (13U) +#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */ +#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */ +#define HRTIM_RSTR_EXTEVNT6_Pos (14U) +#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */ +#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */ +#define HRTIM_RSTR_EXTEVNT7_Pos (15U) +#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */ +#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */ +#define HRTIM_RSTR_EXTEVNT8_Pos (16U) +#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */ +#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */ +#define HRTIM_RSTR_EXTEVNT9_Pos (17U) +#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */ +#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */ +#define HRTIM_RSTR_EXTEVNT10_Pos (18U) +#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */ +#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */ +#define HRTIM_RSTR_TIMBCMP1_Pos (19U) +#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */ +#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_RSTR_TIMBCMP2_Pos (20U) +#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */ +#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_RSTR_TIMBCMP4_Pos (21U) +#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */ +#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */ +#define HRTIM_RSTR_TIMCCMP1_Pos (22U) +#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_RSTR_TIMCCMP2_Pos (23U) +#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */ +#define HRTIM_RSTR_TIMCCMP4_Pos (24U) +#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */ +#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */ +#define HRTIM_RSTR_TIMDCMP1_Pos (25U) +#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_RSTR_TIMDCMP2_Pos (26U) +#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_RSTR_TIMDCMP4_Pos (27U) +#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */ +#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */ +#define HRTIM_RSTR_TIMECMP1_Pos (28U) +#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */ +#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_RSTR_TIMECMP2_Pos (29U) +#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */ +#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_RSTR_TIMECMP4_Pos (30U) +#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */ +#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */ +#define HRTIM_RSTR_TIMFCMP2_Pos (31U) +#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */ +#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */ + +/**** Bit definition for Slave Timer Chopper register *************************/ +#define HRTIM_CHPR_CARFRQ_Pos (0U) +#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */ +#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */ +#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */ +#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */ +#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */ +#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */ + +#define HRTIM_CHPR_CARDTY_Pos (4U) +#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */ +#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */ +#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */ +#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */ +#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */ + +#define HRTIM_CHPR_STRPW_Pos (7U) +#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */ +#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */ +#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */ +#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */ +#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */ +#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */ + +/**** Bit definition for Slave Timer Capture 1 control register ***************/ +#define HRTIM_CPT1CR_SWCPT_Pos (0U) +#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */ +#define HRTIM_CPT1CR_UPDCPT_Pos (1U) +#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */ +#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U) +#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */ +#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U) +#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */ +#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U) +#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */ +#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */ +#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U) +#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */ +#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */ +#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U) +#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */ +#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */ +#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U) +#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */ +#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */ +#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U) +#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */ +#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */ +#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U) +#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */ +#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */ +#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U) +#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */ +#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */ +#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U) +#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */ +#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */ + +#define HRTIM_CPT1CR_TF1SET_Pos (0U) +#define HRTIM_CPT1CR_TF1SET_Msk (0x1UL << HRTIM_CPT1CR_TF1SET_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT1CR_TF1SET HRTIM_CPT1CR_TF1SET_Msk /*!< Timer F output 1 set */ +#define HRTIM_CPT1CR_TF1RST_Pos (1U) +#define HRTIM_CPT1CR_TF1RST_Msk (0x1UL << HRTIM_CPT1CR_TF1RST_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT1CR_TF1RST HRTIM_CPT1CR_TF1RST_Msk /*!< Timer F output 1 reset */ +#define HRTIM_CPT1CR_TIMFCMP1_Pos (2U) +#define HRTIM_CPT1CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT1CR_TIMFCMP1 HRTIM_CPT1CR_TIMFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_CPT1CR_TIMFCMP2_Pos (3U) +#define HRTIM_CPT1CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT1CR_TIMFCMP2 HRTIM_CPT1CR_TIMFCMP2_Msk /*!< Timer F compare 2 */ + +#define HRTIM_CPT1CR_TA1SET_Pos (12U) +#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */ +#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */ +#define HRTIM_CPT1CR_TA1RST_Pos (13U) +#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */ +#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */ +#define HRTIM_CPT1CR_TIMACMP1_Pos (14U) +#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */ +#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_CPT1CR_TIMACMP2_Pos (15U) +#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */ +#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */ + +#define HRTIM_CPT1CR_TB1SET_Pos (16U) +#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */ +#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */ +#define HRTIM_CPT1CR_TB1RST_Pos (17U) +#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */ +#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */ +#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U) +#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */ +#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U) +#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */ +#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */ + +#define HRTIM_CPT1CR_TC1SET_Pos (20U) +#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */ +#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */ +#define HRTIM_CPT1CR_TC1RST_Pos (21U) +#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */ +#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */ +#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U) +#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U) +#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */ + +#define HRTIM_CPT1CR_TD1SET_Pos (24U) +#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */ +#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */ +#define HRTIM_CPT1CR_TD1RST_Pos (25U) +#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */ +#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */ +#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U) +#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */ +#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U) +#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */ +#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */ + +#define HRTIM_CPT1CR_TE1SET_Pos (28U) +#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */ +#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */ +#define HRTIM_CPT1CR_TE1RST_Pos (29U) +#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */ +#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */ +#define HRTIM_CPT1CR_TIMECMP1_Pos (30U) +#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */ +#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_CPT1CR_TIMECMP2_Pos (31U) +#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */ +#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */ + +/**** Bit definition for Slave Timer Capture 2 control register ***************/ +#define HRTIM_CPT2CR_SWCPT_Pos (0U) +#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */ +#define HRTIM_CPT2CR_UPDCPT_Pos (1U) +#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */ +#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U) +#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */ +#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U) +#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */ +#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U) +#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */ +#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */ +#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U) +#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */ +#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */ +#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U) +#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */ +#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */ +#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U) +#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */ +#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */ +#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U) +#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */ +#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */ +#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U) +#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */ +#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */ +#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U) +#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */ +#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */ +#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U) +#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */ +#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */ + +#define HRTIM_CPT2CR_TF1SET_Pos (0U) +#define HRTIM_CPT2CR_TF1SET_Msk (0x1UL << HRTIM_CPT2CR_TF1SET_Pos) /*!< 0x00000001 */ +#define HRTIM_CPT2CR_TF1SET HRTIM_CPT2CR_TF1SET_Msk /*!< Timer F output 1 set */ +#define HRTIM_CPT2CR_TF1RST_Pos (1U) +#define HRTIM_CPT2CR_TF1RST_Msk (0x1UL << HRTIM_CPT2CR_TF1RST_Pos) /*!< 0x00000002 */ +#define HRTIM_CPT2CR_TF1RST HRTIM_CPT2CR_TF1RST_Msk /*!< Timer F output 1 reset */ +#define HRTIM_CPT2CR_TIMFCMP1_Pos (2U) +#define HRTIM_CPT2CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos) /*!< 0x00000004 */ +#define HRTIM_CPT2CR_TIMFCMP1 HRTIM_CPT2CR_TIMFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_CPT2CR_TIMFCMP2_Pos (3U) +#define HRTIM_CPT2CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos) /*!< 0x00000008 */ +#define HRTIM_CPT2CR_TIMFCMP2 HRTIM_CPT2CR_TIMFCMP2_Msk /*!< Timer F compare 2 */ + +#define HRTIM_CPT2CR_TA1SET_Pos (12U) +#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */ +#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */ +#define HRTIM_CPT2CR_TA1RST_Pos (13U) +#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */ +#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */ +#define HRTIM_CPT2CR_TIMACMP1_Pos (14U) +#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */ +#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_CPT2CR_TIMACMP2_Pos (15U) +#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */ +#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */ + +#define HRTIM_CPT2CR_TB1SET_Pos (16U) +#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */ +#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */ +#define HRTIM_CPT2CR_TB1RST_Pos (17U) +#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */ +#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */ +#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U) +#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */ +#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U) +#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */ +#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */ + +#define HRTIM_CPT2CR_TC1SET_Pos (20U) +#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */ +#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */ +#define HRTIM_CPT2CR_TC1RST_Pos (21U) +#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */ +#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */ +#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U) +#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U) +#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */ + +#define HRTIM_CPT2CR_TD1SET_Pos (24U) +#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */ +#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */ +#define HRTIM_CPT2CR_TD1RST_Pos (25U) +#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */ +#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */ +#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U) +#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */ +#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U) +#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */ +#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */ + +#define HRTIM_CPT2CR_TE1SET_Pos (28U) +#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */ +#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */ +#define HRTIM_CPT2CR_TE1RST_Pos (29U) +#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */ +#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */ +#define HRTIM_CPT2CR_TIMECMP1_Pos (30U) +#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */ +#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_CPT2CR_TIMECMP2_Pos (31U) +#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */ +#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */ + +/**** Bit definition for Slave Timer Output register **************************/ +#define HRTIM_OUTR_POL1_Pos (1U) +#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */ +#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */ +#define HRTIM_OUTR_IDLM1_Pos (2U) +#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */ +#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */ +#define HRTIM_OUTR_IDLES1_Pos (3U) +#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */ +#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */ +#define HRTIM_OUTR_FAULT1_Pos (4U) +#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */ +#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */ +#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */ +#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */ +#define HRTIM_OUTR_CHP1_Pos (6U) +#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */ +#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */ +#define HRTIM_OUTR_DIDL1_Pos (7U) +#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */ +#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */ + +#define HRTIM_OUTR_DTEN_Pos (8U) +#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */ +#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */ +#define HRTIM_OUTR_DLYPRTEN_Pos (9U) +#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */ +#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */ +#define HRTIM_OUTR_DLYPRT_Pos (10U) +#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */ +#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */ +#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */ +#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */ +#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */ +#define HRTIM_OUTR_BIAR_Pos (14U) +#define HRTIM_OUTR_BIAR_Msk (0x1UL << HRTIM_OUTR_BIAR_Pos) /*!< 0x00004000 */ +#define HRTIM_OUTR_BIAR HRTIM_OUTR_BIAR_Msk /*!< Slave output Balanced Idle Automatic resume */ +#define HRTIM_OUTR_POL2_Pos (17U) +#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */ +#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */ +#define HRTIM_OUTR_IDLM2_Pos (18U) +#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */ +#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */ +#define HRTIM_OUTR_IDLES2_Pos (19U) +#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */ +#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */ +#define HRTIM_OUTR_FAULT2_Pos (20U) +#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */ +#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */ +#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */ +#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */ +#define HRTIM_OUTR_CHP2_Pos (22U) +#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */ +#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */ +#define HRTIM_OUTR_DIDL2_Pos (23U) +#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */ +#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */ + +/**** Bit definition for Timerx Fault register ***************************/ +#define HRTIM_FLTR_FLT1EN_Pos (0U) +#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */ +#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */ +#define HRTIM_FLTR_FLT2EN_Pos (1U) +#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */ +#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */ +#define HRTIM_FLTR_FLT3EN_Pos (2U) +#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */ +#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */ +#define HRTIM_FLTR_FLT4EN_Pos (3U) +#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */ +#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */ +#define HRTIM_FLTR_FLT5EN_Pos (4U) +#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */ +#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */ +#define HRTIM_FLTR_FLT6EN_Pos (5U) +#define HRTIM_FLTR_FLT6EN_Msk (0x1UL << HRTIM_FLTR_FLT6EN_Pos) /*!< 0x00000020 */ +#define HRTIM_FLTR_FLT6EN HRTIM_FLTR_FLT6EN_Msk /*!< Fault 6 enable */ +#define HRTIM_FLTR_FLTLCK_Pos (31U) +#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */ +#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */ + +/**** Bit definition for HRTIM Timerx control register 2 ****************/ +#define HRTIM_TIMCR2_DCDE_Pos (0U) +#define HRTIM_TIMCR2_DCDE_Msk (0x1UL << HRTIM_TIMCR2_DCDE_Pos) /*!< 0x00000001 */ +#define HRTIM_TIMCR2_DCDE HRTIM_TIMCR2_DCDE_Msk /*!< Dual Channel DAC trigger enable */ +#define HRTIM_TIMCR2_DCDS_Pos (1U) +#define HRTIM_TIMCR2_DCDS_Msk (0x1UL << HRTIM_TIMCR2_DCDS_Pos) /*!< 0x00000002 */ +#define HRTIM_TIMCR2_DCDS HRTIM_TIMCR2_DCDS_Msk /*!< Dual Channel DAC step trigger */ +#define HRTIM_TIMCR2_DCDR_Pos (2U) +#define HRTIM_TIMCR2_DCDR_Msk (0x1UL << HRTIM_TIMCR2_DCDR_Pos) /*!< 0x00000004 */ +#define HRTIM_TIMCR2_DCDR HRTIM_TIMCR2_DCDR_Msk /*!< Dual Channel DAC reset trigger */ +#define HRTIM_TIMCR2_UDM_Pos (4U) +#define HRTIM_TIMCR2_UDM_Msk (0x1UL << HRTIM_TIMCR2_UDM_Pos) /*!< 0x00000010 */ +#define HRTIM_TIMCR2_UDM HRTIM_TIMCR2_UDM_Msk /*!< Up-Down Mode*/ +#define HRTIM_TIMCR2_ROM_Pos (6U) +#define HRTIM_TIMCR2_ROM_Msk (0x3UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x000000C0 */ +#define HRTIM_TIMCR2_ROM HRTIM_TIMCR2_ROM_Msk /*!< Roll-over Mode */ +#define HRTIM_TIMCR2_ROM_0 (0x1UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000040 */ +#define HRTIM_TIMCR2_ROM_1 (0x2UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000080 */ +#define HRTIM_TIMCR2_OUTROM_Pos (8U) +#define HRTIM_TIMCR2_OUTROM_Msk (0x3UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000300 */ +#define HRTIM_TIMCR2_OUTROM HRTIM_TIMCR2_OUTROM_Msk /*!< Output Roll-Over Mode */ +#define HRTIM_TIMCR2_OUTROM_0 (0x1UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000100 */ +#define HRTIM_TIMCR2_OUTROM_1 (0x2UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000200 */ +#define HRTIM_TIMCR2_ADROM_Pos (10U) +#define HRTIM_TIMCR2_ADROM_Msk (0x3UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000C00 */ +#define HRTIM_TIMCR2_ADROM HRTIM_TIMCR2_ADROM_Msk /*!< ADC Roll-Over Mode */ +#define HRTIM_TIMCR2_ADROM_0 (0x1UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000400 */ +#define HRTIM_TIMCR2_ADROM_1 (0x2UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000800 */ +#define HRTIM_TIMCR2_BMROM_Pos (12U) +#define HRTIM_TIMCR2_BMROM_Msk (0x3UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00003000 */ +#define HRTIM_TIMCR2_BMROM HRTIM_TIMCR2_BMROM_Msk /*!< Burst Mode Rollover Mode */ +#define HRTIM_TIMCR2_BMROM_0 (0x1UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00001000 */ +#define HRTIM_TIMCR2_BMROM_1 (0x2UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00002000 */ +#define HRTIM_TIMCR2_FEROM_Pos (14U) +#define HRTIM_TIMCR2_FEROM_Msk (0x3UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x0000C000 */ +#define HRTIM_TIMCR2_FEROM HRTIM_TIMCR2_FEROM_Msk /*!< Fault and Event Rollover Mode */ +#define HRTIM_TIMCR2_FEROM_0 (0x1UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00004000 */ +#define HRTIM_TIMCR2_FEROM_1 (0x2UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00008000 */ +#define HRTIM_TIMCR2_GTCMP1_Pos (16U) +#define HRTIM_TIMCR2_GTCMP1_Msk (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos) /*!< 0x00010000 */ +#define HRTIM_TIMCR2_GTCMP1 HRTIM_TIMCR2_GTCMP1_Msk /*!< Greater than Compare 1 PWM mode */ +#define HRTIM_TIMCR2_GTCMP3_Pos (17U) +#define HRTIM_TIMCR2_GTCMP3_Msk (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos) /*!< 0x00020000 */ +#define HRTIM_TIMCR2_GTCMP3 HRTIM_TIMCR2_GTCMP3_Msk /*!< Greater than Compare 3 PWM mode */ +#define HRTIM_TIMCR2_TRGHLF_Pos (20U) +#define HRTIM_TIMCR2_TRGHLF_Msk (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos) /*!< 0x00100000 */ +#define HRTIM_TIMCR2_TRGHLF HRTIM_TIMCR2_TRGHLF_Msk /*!< Triggered-Half mode */ + +/**** Bit definition for Slave external event filtering register 3 ***********/ +#define HRTIM_EEFR3_EEVACE_Pos (0U) +#define HRTIM_EEFR3_EEVACE_Msk (0x1UL << HRTIM_EEFR3_EEVACE_Pos) /*!< 0x00000001 */ +#define HRTIM_EEFR3_EEVACE HRTIM_EEFR3_EEVACE_Msk /*!< External Event A Counter Enable */ +#define HRTIM_EEFR3_EEVACRES_Pos (1U) +#define HRTIM_EEFR3_EEVACRES_Msk (0x1UL << HRTIM_EEFR3_EEVACRES_Pos) /*!< 0x00000002 */ +#define HRTIM_EEFR3_EEVACRES HRTIM_EEFR3_EEVACRES_Msk /*!< External Event A Counter Reset */ +#define HRTIM_EEFR3_EEVARSTM_Pos (2U) +#define HRTIM_EEFR3_EEVARSTM_Msk (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos) /*!< 0x00000004 */ +#define HRTIM_EEFR3_EEVARSTM HRTIM_EEFR3_EEVARSTM_Msk /*!< External Event A Counter Reset Mode */ +#define HRTIM_EEFR3_EEVASEL_Pos (4U) +#define HRTIM_EEFR3_EEVASEL_Msk (0xFUL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x000000F0 */ +#define HRTIM_EEFR3_EEVASEL HRTIM_EEFR3_EEVASEL_Msk /*!< External Event A Selection */ +#define HRTIM_EEFR3_EEVASEL_0 (0x1UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000010 */ +#define HRTIM_EEFR3_EEVASEL_1 (0x2UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000020 */ +#define HRTIM_EEFR3_EEVASEL_2 (0x4UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000040 */ +#define HRTIM_EEFR3_EEVASEL_3 (0x8UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000080 */ +#define HRTIM_EEFR3_EEVACNT_Pos (8U) +#define HRTIM_EEFR3_EEVACNT_Msk (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00003F00 */ +#define HRTIM_EEFR3_EEVACNT HRTIM_EEFR3_EEVACNT_Msk /*!< External Event A Selection */ +#define HRTIM_EEFR3_EEVACNT_0 (0x1UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000100 */ +#define HRTIM_EEFR3_EEVACNT_1 (0x2UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000200 */ +#define HRTIM_EEFR3_EEVACNT_2 (0x4UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000400 */ +#define HRTIM_EEFR3_EEVACNT_3 (0x8UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000800 */ +#define HRTIM_EEFR3_EEVACNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00001000 */ +#define HRTIM_EEFR3_EEVACNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00002000 */ +#define HRTIM_EEFR3_EEVBCE_Pos (16U) +#define HRTIM_EEFR3_EEVBCE_Msk (0x1UL << HRTIM_EEFR3_EEVBCE_Pos) /*!< 0x00010000 */ +#define HRTIM_EEFR3_EEVBCE HRTIM_EEFR3_EEVBCE_Msk /*!< External Event B Counter Enable */ +#define HRTIM_EEFR3_EEVBCRES_Pos (17U) +#define HRTIM_EEFR3_EEVBCRES_Msk (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos) /*!< 0x00020000 */ +#define HRTIM_EEFR3_EEVBCRES HRTIM_EEFR3_EEVBCRES_Msk /*!< External Event B Counter Reset */ +#define HRTIM_EEFR3_EEVBRSTM_Pos (18U) +#define HRTIM_EEFR3_EEVBRSTM_Msk (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos) /*!< 0x00040000 */ +#define HRTIM_EEFR3_EEVBRSTM HRTIM_EEFR3_EEVBRSTM_Msk /*!< External Event B Counter Reset Mode */ +#define HRTIM_EEFR3_EEVBSEL_Pos (20U) +#define HRTIM_EEFR3_EEVBSEL_Msk (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00F00000 */ +#define HRTIM_EEFR3_EEVBSEL HRTIM_EEFR3_EEVBSEL_Msk /*!< External Event B Selection */ +#define HRTIM_EEFR3_EEVBSEL_0 (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00100000 */ +#define HRTIM_EEFR3_EEVBSEL_1 (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00200000 */ +#define HRTIM_EEFR3_EEVBSEL_2 (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00400000 */ +#define HRTIM_EEFR3_EEVBSEL_3 (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00800000 */ +#define HRTIM_EEFR3_EEVBCNT_Pos (24U) +#define HRTIM_EEFR3_EEVBCNT_Msk (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x3F000000 */ +#define HRTIM_EEFR3_EEVBCNT HRTIM_EEFR3_EEVBCNT_Msk /*!< External Event B Counter */ +#define HRTIM_EEFR3_EEVBCNT_0 (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x01000000 */ +#define HRTIM_EEFR3_EEVBCNT_1 (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x02000000 */ +#define HRTIM_EEFR3_EEVBCNT_2 (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x04000000 */ +#define HRTIM_EEFR3_EEVBCNT_3 (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x08000000 */ +#define HRTIM_EEFR3_EEVBCNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x10000000 */ +#define HRTIM_EEFR3_EEVBCNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x20000000 */ + +/**** Bit definition for Common HRTIM Timer control register 1 ****************/ +#define HRTIM_CR1_MUDIS_Pos (0U) +#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */ +#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/ +#define HRTIM_CR1_TAUDIS_Pos (1U) +#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */ +#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/ +#define HRTIM_CR1_TBUDIS_Pos (2U) +#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */ +#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/ +#define HRTIM_CR1_TCUDIS_Pos (3U) +#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */ +#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/ +#define HRTIM_CR1_TDUDIS_Pos (4U) +#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */ +#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/ +#define HRTIM_CR1_TEUDIS_Pos (5U) +#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */ +#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/ +#define HRTIM_CR1_TFUDIS_Pos (6U) +#define HRTIM_CR1_TFUDIS_Msk (0x1UL << HRTIM_CR1_TFUDIS_Pos) /*!< 0x00000040 */ +#define HRTIM_CR1_TFUDIS HRTIM_CR1_TFUDIS_Msk /*!< Timer F update disable*/ +#define HRTIM_CR1_ADC1USRC_Pos (16U) +#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */ +#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */ +#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */ +#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */ +#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */ +#define HRTIM_CR1_ADC2USRC_Pos (19U) +#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */ +#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */ +#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */ +#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */ +#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */ +#define HRTIM_CR1_ADC3USRC_Pos (22U) +#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */ +#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */ +#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */ +#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */ +#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */ +#define HRTIM_CR1_ADC4USRC_Pos (25U) +#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */ +#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */ +#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */ +#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */ +#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */ + +/**** Bit definition for Common HRTIM Timer control register 2 ****************/ +#define HRTIM_CR2_MSWU_Pos (0U) +#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */ +#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */ +#define HRTIM_CR2_TASWU_Pos (1U) +#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */ +#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */ +#define HRTIM_CR2_TBSWU_Pos (2U) +#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */ +#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */ +#define HRTIM_CR2_TCSWU_Pos (3U) +#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */ +#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */ +#define HRTIM_CR2_TDSWU_Pos (4U) +#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */ +#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */ +#define HRTIM_CR2_TESWU_Pos (5U) +#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */ +#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */ +#define HRTIM_CR2_TFSWU_Pos (6U) +#define HRTIM_CR2_TFSWU_Msk (0x1UL << HRTIM_CR2_TFSWU_Pos) /*!< 0x00000040 */ +#define HRTIM_CR2_TFSWU HRTIM_CR2_TFSWU_Msk /*!< Timer F software update */ +#define HRTIM_CR2_MRST_Pos (8U) +#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */ +#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */ +#define HRTIM_CR2_TARST_Pos (9U) +#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */ +#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */ +#define HRTIM_CR2_TBRST_Pos (10U) +#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */ +#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */ +#define HRTIM_CR2_TCRST_Pos (11U) +#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */ +#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */ +#define HRTIM_CR2_TDRST_Pos (12U) +#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */ +#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */ +#define HRTIM_CR2_TERST_Pos (13U) +#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */ +#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */ +#define HRTIM_CR2_TFRST_Pos (14U) +#define HRTIM_CR2_TFRST_Msk (0x1UL << HRTIM_CR2_TFRST_Pos) /*!< 0x00004000 */ +#define HRTIM_CR2_TFRST HRTIM_CR2_TFRST_Msk /*!< Timer F count software reset */ +#define HRTIM_CR2_SWPA_Pos (16U) +#define HRTIM_CR2_SWPA_Msk (0x1UL << HRTIM_CR2_SWPA_Pos) /*!< 0x00010000 */ +#define HRTIM_CR2_SWPA HRTIM_CR2_SWPA_Msk /*!< Timer A swap outputs */ +#define HRTIM_CR2_SWPB_Pos (17U) +#define HRTIM_CR2_SWPB_Msk (0x1UL << HRTIM_CR2_SWPB_Pos) /*!< 0x00020000 */ +#define HRTIM_CR2_SWPB HRTIM_CR2_SWPB_Msk /*!< Timer B swap outputs */ +#define HRTIM_CR2_SWPC_Pos (18U) +#define HRTIM_CR2_SWPC_Msk (0x1UL << HRTIM_CR2_SWPC_Pos) /*!< 0x00040000 */ +#define HRTIM_CR2_SWPC HRTIM_CR2_SWPC_Msk /*!< Timer C swap outputs */ +#define HRTIM_CR2_SWPD_Pos (19U) +#define HRTIM_CR2_SWPD_Msk (0x1UL << HRTIM_CR2_SWPD_Pos) /*!< 0x00080000 */ +#define HRTIM_CR2_SWPD HRTIM_CR2_SWPD_Msk /*!< Timer D swap outputs */ +#define HRTIM_CR2_SWPE_Pos (20U) +#define HRTIM_CR2_SWPE_Msk (0x1UL << HRTIM_CR2_SWPE_Pos) /*!< 0x00100000 */ +#define HRTIM_CR2_SWPE HRTIM_CR2_SWPE_Msk /*!< Timer E swap outputs */ +#define HRTIM_CR2_SWPF_Pos (21U) +#define HRTIM_CR2_SWPF_Msk (0x1UL << HRTIM_CR2_SWPF_Pos) /*!< 0x00200000 */ +#define HRTIM_CR2_SWPF HRTIM_CR2_SWPF_Msk /*!< Timer F swap outputs */ + +/**** Bit definition for Common HRTIM Timer interrupt status register *********/ +#define HRTIM_ISR_FLT1_Pos (0U) +#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */ +#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */ +#define HRTIM_ISR_FLT2_Pos (1U) +#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */ +#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */ +#define HRTIM_ISR_FLT3_Pos (2U) +#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */ +#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */ +#define HRTIM_ISR_FLT4_Pos (3U) +#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */ +#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */ +#define HRTIM_ISR_FLT5_Pos (4U) +#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */ +#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */ +#define HRTIM_ISR_SYSFLT_Pos (5U) +#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */ +#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */ +#define HRTIM_ISR_FLT6_Pos (6U) +#define HRTIM_ISR_FLT6_Msk (0x1UL << HRTIM_ISR_FLT6_Pos) /*!< 0x00000040 */ +#define HRTIM_ISR_FLT6 HRTIM_ISR_FLT6_Msk /*!< Fault 6 interrupt flag */ +#define HRTIM_ISR_DLLRDY_Pos (16U) +#define HRTIM_ISR_DLLRDY_Msk (0x1UL << HRTIM_ISR_DLLRDY_Pos) /*!< 0x00010000 */ +#define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk /*!< DLL ready interrupt flag */ +#define HRTIM_ISR_BMPER_Pos (17U) +#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */ +#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */ + +/**** Bit definition for Common HRTIM Timer interrupt clear register **********/ +#define HRTIM_ICR_FLT1C_Pos (0U) +#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */ +#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */ +#define HRTIM_ICR_FLT2C_Pos (1U) +#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */ +#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */ +#define HRTIM_ICR_FLT3C_Pos (2U) +#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */ +#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */ +#define HRTIM_ICR_FLT4C_Pos (3U) +#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */ +#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */ +#define HRTIM_ICR_FLT5C_Pos (4U) +#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */ +#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */ +#define HRTIM_ICR_SYSFLTC_Pos (5U) +#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */ +#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */ + +#define HRTIM_ICR_FLT6C_Pos (6U) +#define HRTIM_ICR_FLT6C_Msk (0x1UL << HRTIM_ICR_FLT6C_Pos) /*!< 0x00000040 */ +#define HRTIM_ICR_FLT6C HRTIM_ICR_FLT6C_Msk /*!< Fault 6 interrupt flag clear */ + +#define HRTIM_ICR_DLLRDYC_Pos (16U) +#define HRTIM_ICR_DLLRDYC_Msk (0x1UL << HRTIM_ICR_DLLRDYC_Pos) /*!< 0x00010000 */ +#define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk /*!< DLL ready interrupt flag clear */ +#define HRTIM_ICR_BMPERC_Pos (17U) +#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */ +#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */ + +/**** Bit definition for Common HRTIM Timer interrupt enable register *********/ +#define HRTIM_IER_FLT1_Pos (0U) +#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */ +#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */ +#define HRTIM_IER_FLT2_Pos (1U) +#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */ +#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */ +#define HRTIM_IER_FLT3_Pos (2U) +#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */ +#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */ +#define HRTIM_IER_FLT4_Pos (3U) +#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */ +#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */ +#define HRTIM_IER_FLT5_Pos (4U) +#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */ +#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */ +#define HRTIM_IER_SYSFLT_Pos (5U) +#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */ +#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */ +#define HRTIM_IER_FLT6_Pos (6U) +#define HRTIM_IER_FLT6_Msk (0x1UL << HRTIM_IER_FLT6_Pos) /*!< 0x00000040 */ +#define HRTIM_IER_FLT6 HRTIM_IER_FLT6_Msk /*!< Fault 6 interrupt enable */ + +#define HRTIM_IER_DLLRDY_Pos (16U) +#define HRTIM_IER_DLLRDY_Msk (0x1UL << HRTIM_IER_DLLRDY_Pos) /*!< 0x00010000 */ +#define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk /*!< DLL ready interrupt enable */ +#define HRTIM_IER_BMPER_Pos (17U) +#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */ +#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */ + +/**** Bit definition for Common HRTIM Timer output enable register ************/ +#define HRTIM_OENR_TA1OEN_Pos (0U) +#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */ +#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */ +#define HRTIM_OENR_TA2OEN_Pos (1U) +#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */ +#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */ +#define HRTIM_OENR_TB1OEN_Pos (2U) +#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */ +#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */ +#define HRTIM_OENR_TB2OEN_Pos (3U) +#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */ +#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */ +#define HRTIM_OENR_TC1OEN_Pos (4U) +#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */ +#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */ +#define HRTIM_OENR_TC2OEN_Pos (5U) +#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */ +#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */ +#define HRTIM_OENR_TD1OEN_Pos (6U) +#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */ +#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */ +#define HRTIM_OENR_TD2OEN_Pos (7U) +#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */ +#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */ +#define HRTIM_OENR_TE1OEN_Pos (8U) +#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */ +#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */ +#define HRTIM_OENR_TE2OEN_Pos (9U) +#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */ +#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */ +#define HRTIM_OENR_TF1OEN_Pos (10U) +#define HRTIM_OENR_TF1OEN_Msk (0x1UL << HRTIM_OENR_TF1OEN_Pos) /*!< 0x00000400 */ +#define HRTIM_OENR_TF1OEN HRTIM_OENR_TF1OEN_Msk /*!< Timer F Output 1 enable */ +#define HRTIM_OENR_TF2OEN_Pos (11U) +#define HRTIM_OENR_TF2OEN_Msk (0x1UL << HRTIM_OENR_TF2OEN_Pos) /*!< 0x00000800 */ +#define HRTIM_OENR_TF2OEN HRTIM_OENR_TF2OEN_Msk /*!< Timer F Output 2 enable */ + +/**** Bit definition for Common HRTIM Timer output disable register ***********/ +#define HRTIM_ODISR_TA1ODIS_Pos (0U) +#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */ +#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */ +#define HRTIM_ODISR_TA2ODIS_Pos (1U) +#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */ +#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */ +#define HRTIM_ODISR_TB1ODIS_Pos (2U) +#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */ +#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */ +#define HRTIM_ODISR_TB2ODIS_Pos (3U) +#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */ +#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */ +#define HRTIM_ODISR_TC1ODIS_Pos (4U) +#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */ +#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */ +#define HRTIM_ODISR_TC2ODIS_Pos (5U) +#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */ +#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */ +#define HRTIM_ODISR_TD1ODIS_Pos (6U) +#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */ +#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */ +#define HRTIM_ODISR_TD2ODIS_Pos (7U) +#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */ +#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */ +#define HRTIM_ODISR_TE1ODIS_Pos (8U) +#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */ +#define HRTIM_ODISR_TE2ODIS_Pos (9U) +#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */ +#define HRTIM_ODISR_TF1ODIS_Pos (10U) +#define HRTIM_ODISR_TF1ODIS_Msk (0x1UL << HRTIM_ODISR_TF1ODIS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODISR_TF1ODIS HRTIM_ODISR_TF1ODIS_Msk /*!< Timer F Output 1 disable */ +#define HRTIM_ODISR_TF2ODIS_Pos (11U) +#define HRTIM_ODISR_TF2ODIS_Msk (0x1UL << HRTIM_ODISR_TF2ODIS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODISR_TF2ODIS HRTIM_ODISR_TF2ODIS_Msk /*!< Timer F Output 2 disable */ + +/**** Bit definition for Common HRTIM Timer output disable status register *****/ +#define HRTIM_ODSR_TA1ODS_Pos (0U) +#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */ +#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */ +#define HRTIM_ODSR_TA2ODS_Pos (1U) +#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */ +#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */ +#define HRTIM_ODSR_TB1ODS_Pos (2U) +#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */ +#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */ +#define HRTIM_ODSR_TB2ODS_Pos (3U) +#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */ +#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */ +#define HRTIM_ODSR_TC1ODS_Pos (4U) +#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */ +#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */ +#define HRTIM_ODSR_TC2ODS_Pos (5U) +#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */ +#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */ +#define HRTIM_ODSR_TD1ODS_Pos (6U) +#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */ +#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */ +#define HRTIM_ODSR_TD2ODS_Pos (7U) +#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */ +#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */ +#define HRTIM_ODSR_TE1ODS_Pos (8U) +#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */ +#define HRTIM_ODSR_TE2ODS_Pos (9U) +#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */ +#define HRTIM_ODSR_TF1ODS_Pos (10U) +#define HRTIM_ODSR_TF1ODS_Msk (0x1UL << HRTIM_ODSR_TF1ODS_Pos) /*!< 0x00000100 */ +#define HRTIM_ODSR_TF1ODS HRTIM_ODSR_TF1ODS_Msk /*!< Timer F Output 1 disable status */ +#define HRTIM_ODSR_TF2ODS_Pos (11U) +#define HRTIM_ODSR_TF2ODS_Msk (0x1UL << HRTIM_ODSR_TF2ODS_Pos) /*!< 0x00000200 */ +#define HRTIM_ODSR_TF2ODS HRTIM_ODSR_TF2ODS_Msk /*!< Timer F Output 2 disable status */ + +/**** Bit definition for Common HRTIM Timer Burst mode control register ********/ +#define HRTIM_BMCR_BME_Pos (0U) +#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */ +#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */ +#define HRTIM_BMCR_BMOM_Pos (1U) +#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */ +#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */ +#define HRTIM_BMCR_BMCLK_Pos (2U) +#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */ +#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */ +#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */ +#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */ +#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */ +#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */ +#define HRTIM_BMCR_BMPRSC_Pos (6U) +#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */ +#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */ +#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */ +#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */ +#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */ +#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */ +#define HRTIM_BMCR_BMPREN_Pos (10U) +#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */ +#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */ +#define HRTIM_BMCR_MTBM_Pos (16U) +#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */ +#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */ +#define HRTIM_BMCR_TABM_Pos (17U) +#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */ +#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */ +#define HRTIM_BMCR_TBBM_Pos (18U) +#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */ +#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */ +#define HRTIM_BMCR_TCBM_Pos (19U) +#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */ +#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */ +#define HRTIM_BMCR_TDBM_Pos (20U) +#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */ +#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */ +#define HRTIM_BMCR_TEBM_Pos (21U) +#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */ +#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */ + +#define HRTIM_BMCR_TFBM_Pos (22U) +#define HRTIM_BMCR_TFBM_Msk (0x1UL << HRTIM_BMCR_TFBM_Pos) /*!< 0x00400000 */ +#define HRTIM_BMCR_TFBM HRTIM_BMCR_TFBM_Msk /*!< Timer F Burst mode */ + +#define HRTIM_BMCR_BMSTAT_Pos (31U) +#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */ +#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */ + +/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/ +#define HRTIM_BMTRGR_SW_Pos (0U) +#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */ +#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */ +#define HRTIM_BMTRGR_MSTRST_Pos (1U) +#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */ +#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */ +#define HRTIM_BMTRGR_MSTREP_Pos (2U) +#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */ +#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */ +#define HRTIM_BMTRGR_MSTCMP1_Pos (3U) +#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */ +#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */ +#define HRTIM_BMTRGR_MSTCMP2_Pos (4U) +#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */ +#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */ +#define HRTIM_BMTRGR_MSTCMP3_Pos (5U) +#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */ +#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */ +#define HRTIM_BMTRGR_MSTCMP4_Pos (6U) +#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */ +#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */ +#define HRTIM_BMTRGR_TARST_Pos (7U) +#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */ +#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */ +#define HRTIM_BMTRGR_TAREP_Pos (8U) +#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */ +#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */ +#define HRTIM_BMTRGR_TACMP1_Pos (9U) +#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */ +#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_BMTRGR_TACMP2_Pos (10U) +#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */ +#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_BMTRGR_TBRST_Pos (11U) +#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */ +#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */ +#define HRTIM_BMTRGR_TBREP_Pos (12U) +#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */ +#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */ +#define HRTIM_BMTRGR_TBCMP1_Pos (13U) +#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */ +#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_BMTRGR_TBCMP2_Pos (14U) +#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */ +#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_BMTRGR_TCRST_Pos (15U) +#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */ +#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */ +#define HRTIM_BMTRGR_TCREP_Pos (16U) +#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */ +#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */ +#define HRTIM_BMTRGR_TCCMP1_Pos (17U) +#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */ +#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_BMTRGR_TFRST_Pos (18U) +#define HRTIM_BMTRGR_TFRST_Msk (0x1UL << HRTIM_BMTRGR_TFRST_Pos) /*!< 0x00040000 */ +#define HRTIM_BMTRGR_TFRST HRTIM_BMTRGR_TFRST_Msk /*!< Timer F reset */ +#define HRTIM_BMTRGR_TDRST_Pos (19U) +#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */ +#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */ +#define HRTIM_BMTRGR_TDREP_Pos (20U) +#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */ +#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */ +#define HRTIM_BMTRGR_TFREP_Pos (21U) +#define HRTIM_BMTRGR_TFREP_Msk (0x1UL << HRTIM_BMTRGR_TFREP_Pos) /*!< 0x00200000 */ +#define HRTIM_BMTRGR_TFREP HRTIM_BMTRGR_TFREP_Msk /*!< Timer F repetition*/ +#define HRTIM_BMTRGR_TDCMP2_Pos (22U) +#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */ +#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_BMTRGR_TFCMP1_Pos (23U) +#define HRTIM_BMTRGR_TFCMP1_Msk (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos) /*!< 0x00800000 */ +#define HRTIM_BMTRGR_TFCMP1 HRTIM_BMTRGR_TFCMP1_Msk /*!< Timer F compare 1 */ +#define HRTIM_BMTRGR_TEREP_Pos (24U) +#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */ +#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */ +#define HRTIM_BMTRGR_TECMP1_Pos (25U) +#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_BMTRGR_TECMP2_Pos (26U) +#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_BMTRGR_TAEEV7_Pos (27U) +#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */ +#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */ +#define HRTIM_BMTRGR_TDEEV8_Pos (28U) +#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */ +#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */ +#define HRTIM_BMTRGR_EEV7_Pos (29U) +#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */ +#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */ +#define HRTIM_BMTRGR_EEV8_Pos (30U) +#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */ +#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */ +#define HRTIM_BMTRGR_OCHPEV_Pos (31U) +#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */ +#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */ + +/******************* Bit definition for HRTIM_BMCMPR register ***************/ +#define HRTIM_BMCMPR_BMCMPR_Pos (0U) +#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */ +#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g491xx + * @{ + */ + +#ifndef __STM32G491xx_H +#define __STM32G491xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g4a1xx + * @{ + */ + +#ifndef __STM32G4A1xx_H +#define __STM32G4A1xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + AES_IRQn = 85, /*!< AES global interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g4xx + * @{ + */ + +#ifndef __STM32G4xx_H +#define __STM32G4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32G4) +#define STM32G4 +#endif /* STM32G4 */ + +/* Uncomment the line below according to the target STM32G4 device used in your + application + */ + +#if !defined (STM32G431xx) && !defined (STM32G441xx) && !defined (STM32G471xx) && \ + !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && \ + !defined (STM32GBK1CB) && !defined (STM32G491xx) && !defined (STM32G4A1xx) + /* #define STM32G431xx */ /*!< STM32G431xx Devices */ + /* #define STM32G441xx */ /*!< STM32G441xx Devices */ + /* #define STM32G471xx */ /*!< STM32G471xx Devices */ + /* #define STM32G473xx */ /*!< STM32G473xx Devices */ + /* #define STM32G483xx */ /*!< STM32G483xx Devices */ + /* #define STM32G474xx */ /*!< STM32G474xx Devices */ + /* #define STM32G484xx */ /*!< STM32G484xx Devices */ + /* #define STM32G491xx */ /*!< STM32G491xx Devices */ + /* #define STM32G4A1xx */ /*!< STM32G4A1xx Devices */ + /* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.2.1 + */ +#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\ + |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32G4_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32G4_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32G431xx) + #include "stm32g431xx.h" +#elif defined(STM32G441xx) + #include "stm32g441xx.h" +#elif defined(STM32G471xx) + #include "stm32g471xx.h" +#elif defined(STM32G473xx) + #include "stm32g473xx.h" +#elif defined(STM32G483xx) + #include "stm32g483xx.h" +#elif defined(STM32G474xx) + #include "stm32g474xx.h" +#elif defined(STM32G484xx) + #include "stm32g484xx.h" +#elif defined(STM32G491xx) + #include "stm32g491xx.h" +#elif defined(STM32G4A1xx) + #include "stm32g4a1xx.h" +#elif defined(STM32GBK1CB) + #include "stm32gbk1cb.h" +#else + #error "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32g4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32G4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/lib/stm32g4/include/stm32gbk1cb.h b/lib/stm32g4/include/stm32gbk1cb.h new file mode 100644 index 000000000000..76781724fa3a --- /dev/null +++ b/lib/stm32g4/include/stm32gbk1cb.h @@ -0,0 +1,13066 @@ +/** + ****************************************************************************** + * @file stm32gbk1cb.h + * @author MCD Application Team + * @brief CMSIS STM32GBK1CB Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32gbk1cb + * @{ + */ + +#ifndef __STM32GBK1CB_H +#define __STM32GBK1CB_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 16u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ +#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ +#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ +#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32G4XX_H +#define __SYSTEM_STM32G4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32G4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32G4xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32G4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/lib/stm32g4/system_stm32g4xx.c b/lib/stm32g4/system_stm32g4xx.c new file mode 100644 index 000000000000..92fc662a7061 --- /dev/null +++ b/lib/stm32g4/system_stm32g4xx.c @@ -0,0 +1,287 @@ +/** + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g4xx_system + * @{ + */ + +/** @addtogroup STM32G4xx_System_Private_Includes + * @{ + */ + +#include "stm32g4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = HSI_VALUE; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /* Configure the Vector Table location add offset address ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/lib/stm32h7/include/stm32h723xx.h b/lib/stm32h7/include/stm32h723xx.h new file mode 100644 index 000000000000..610abfdc5e4f --- /dev/null +++ b/lib/stm32h7/include/stm32h723xx.h @@ -0,0 +1,24234 @@ +/** + ****************************************************************************** + * @file stm32h723xx.h + * @author MCD Application Team + * @brief CMSIS STM32H723xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h723xx + * @{ + */ + +#ifndef STM32H723xx_H +#define STM32H723xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x080FFFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h725xx + * @{ + */ + +#ifndef STM32H725xx_H +#define STM32H725xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x080FFFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h730xx + * @{ + */ + +#ifndef STM32H730xx_H +#define STM32H730xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief OTFD register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; + __IO uint32_t REG_START_ADDR; + __IO uint32_t REG_END_ADDR; + __IO uint32_t REG_NONCER0; + __IO uint32_t REG_NONCER1; + __IO uint32_t REG_KEYR0; + __IO uint32_t REG_KEYR1; + __IO uint32_t REG_KEYR2; + __IO uint32_t REG_KEYR3; +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED1[191]; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + uint32_t RESERVED2[56]; + __IO uint32_t HWCFGR2; + __IO uint32_t HWCFGR1; + __IO uint32_t VERR; + __IO uint32_t IPIDR; + __IO uint32_t SIDR; +} OTFDEC_TypeDef; +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x0801FFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +#define OTFDEC1_BASE (D1_AHB1PERIPH_BASE + 0xB800UL) +#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL) +#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL) +#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL) +#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL) +#define OTFDEC2_BASE (D1_AHB1PERIPH_BASE + 0xBC00UL) +#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL) +#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL) +#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL) +#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL) +#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL) +#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE) +#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE) +#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE) +#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE) +#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE) + +#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE) +#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE) +#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE) +#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE) +#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h730xxQ + * @{ + */ + +#ifndef STM32H730xxQ_H +#define STM32H730xxQ_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief OTFD register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; + __IO uint32_t REG_START_ADDR; + __IO uint32_t REG_END_ADDR; + __IO uint32_t REG_NONCER0; + __IO uint32_t REG_NONCER1; + __IO uint32_t REG_KEYR0; + __IO uint32_t REG_KEYR1; + __IO uint32_t REG_KEYR2; + __IO uint32_t REG_KEYR3; +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED1[191]; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + uint32_t RESERVED2[56]; + __IO uint32_t HWCFGR2; + __IO uint32_t HWCFGR1; + __IO uint32_t VERR; + __IO uint32_t IPIDR; + __IO uint32_t SIDR; +} OTFDEC_TypeDef; +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x0801FFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +#define OTFDEC1_BASE (D1_AHB1PERIPH_BASE + 0xB800UL) +#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL) +#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL) +#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL) +#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL) +#define OTFDEC2_BASE (D1_AHB1PERIPH_BASE + 0xBC00UL) +#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL) +#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL) +#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL) +#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL) +#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL) +#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE) +#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE) +#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE) +#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE) +#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE) + +#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE) +#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE) +#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE) +#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE) +#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h733xx + * @{ + */ + +#ifndef STM32H733xx_H +#define STM32H733xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief OTFD register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; + __IO uint32_t REG_START_ADDR; + __IO uint32_t REG_END_ADDR; + __IO uint32_t REG_NONCER0; + __IO uint32_t REG_NONCER1; + __IO uint32_t REG_KEYR0; + __IO uint32_t REG_KEYR1; + __IO uint32_t REG_KEYR2; + __IO uint32_t REG_KEYR3; +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED1[191]; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + uint32_t RESERVED2[56]; + __IO uint32_t HWCFGR2; + __IO uint32_t HWCFGR1; + __IO uint32_t VERR; + __IO uint32_t IPIDR; + __IO uint32_t SIDR; +} OTFDEC_TypeDef; +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x080FFFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +#define OTFDEC1_BASE (D1_AHB1PERIPH_BASE + 0xB800UL) +#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL) +#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL) +#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL) +#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL) +#define OTFDEC2_BASE (D1_AHB1PERIPH_BASE + 0xBC00UL) +#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL) +#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL) +#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL) +#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL) +#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL) +#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE) +#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE) +#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE) +#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE) +#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE) + +#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE) +#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE) +#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE) +#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE) +#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h735xx + * @{ + */ + +#ifndef STM32H735xx_H +#define STM32H735xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief OTFD register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; + __IO uint32_t REG_START_ADDR; + __IO uint32_t REG_END_ADDR; + __IO uint32_t REG_NONCER0; + __IO uint32_t REG_NONCER1; + __IO uint32_t REG_KEYR0; + __IO uint32_t REG_KEYR1; + __IO uint32_t REG_KEYR2; + __IO uint32_t REG_KEYR3; +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED1[191]; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + uint32_t RESERVED2[56]; + __IO uint32_t HWCFGR2; + __IO uint32_t HWCFGR1; + __IO uint32_t VERR; + __IO uint32_t IPIDR; + __IO uint32_t SIDR; +} OTFDEC_TypeDef; +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x080FFFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +#define OTFDEC1_BASE (D1_AHB1PERIPH_BASE + 0xB800UL) +#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL) +#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL) +#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL) +#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL) +#define OTFDEC2_BASE (D1_AHB1PERIPH_BASE + 0xBC00UL) +#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL) +#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL) +#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL) +#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL) +#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL) +#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE) +#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE) +#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE) +#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE) +#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE) + +#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE) +#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE) +#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE) +#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE) +#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -10808,7 +10909,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -10903,7 +11004,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -11028,7 +11133,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -14185,7 +14290,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -11096,7 +11197,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -11221,7 +11326,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -14378,7 +14483,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -8836,7 +8964,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -8837,7 +8965,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -9090,7 +9218,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -9091,7 +9219,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; /* Reset CFGR register */ RCC->CFGR = 0x00000000; - /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ @@ -177,23 +192,23 @@ void SystemInit (void) RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ - RCC->PLLCKSELR = 0x00000000; + RCC->PLLCKSELR = 0x02020200; /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00000000; + RCC->PLLCFGR = 0x01FF0000; /* Reset PLL1DIVR register */ - RCC->PLL1DIVR = 0x00000000; + RCC->PLL1DIVR = 0x01010280; /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; /* Reset PLL2DIVR register */ - RCC->PLL2DIVR = 0x00000000; + RCC->PLL2DIVR = 0x01010280; /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; /* Reset PLL3DIVR register */ - RCC->PLL3DIVR = 0x00000000; + RCC->PLL3DIVR = 0x01010280; /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; @@ -231,13 +246,20 @@ void SystemInit (void) #if defined(DUAL_CORE) && defined(CORE_CM4) /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif /* VECT_TAB_SRAM */ #else + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ @@ -339,7 +361,8 @@ void SystemCoreClockUpdate (void) break; default: - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; @@ -352,7 +375,7 @@ void SystemCoreClockUpdate (void) break; default: - common_system_clock = CSI_VALUE; + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; } diff --git a/scripts/ci-build.sh b/scripts/ci-build.sh index 9d423964f8d5..e3f0e8727ffc 100755 --- a/scripts/ci-build.sh +++ b/scripts/ci-build.sh @@ -8,6 +8,7 @@ set -eu MAIN_DIR=${PWD} BUILD_DIR=${PWD}/ci_build export PATH=${BUILD_DIR}/pru-gcc/bin:${PATH} +export PATH=${BUILD_DIR}/or1k-linux-musl-cross/bin:${PATH} PYTHON=${BUILD_DIR}/python-env/bin/python PYTHON2=${BUILD_DIR}/python2-env/bin/python diff --git a/scripts/ci-install.sh b/scripts/ci-install.sh index 031b1009fd85..a7d2599a29f8 100755 --- a/scripts/ci-install.sh +++ b/scripts/ci-install.sh @@ -16,7 +16,7 @@ mkdir -p ${BUILD_DIR} ${CACHE_DIR} ###################################################################### echo -e "\n\n=============== Install system dependencies\n\n" -PKGS="virtualenv python-dev libffi-dev build-essential" +PKGS="virtualenv python2-dev libffi-dev build-essential" PKGS="${PKGS} gcc-avr avr-libc" PKGS="${PKGS} libnewlib-arm-none-eabi gcc-arm-none-eabi binutils-arm-none-eabi" PKGS="${PKGS} pv libmpfr-dev libgmp-dev libmpc-dev texinfo bison flex" @@ -35,10 +35,10 @@ if [ ! -f ${PRU_FILE} ]; then cd ${BUILD_DIR} git config --global user.email "you@example.com" git config --global user.name "Your Name" - git clone https://github.com/dinuxbg/gnupru -b 2018.03-beta-rc3 --depth 1 + git clone https://github.com/dinuxbg/gnupru -b 2023.01 --depth 1 cd gnupru export PREFIX=${PRU_DIR} - ./download-and-patch.sh 2>&1 | pv -nli 30 > ${BUILD_DIR}/gnupru-build.log + ./download-and-prepare.sh 2>&1 | pv -nli 30 > ${BUILD_DIR}/gnupru-build.log ./build.sh 2>&1 | pv -nli 30 >> ${BUILD_DIR}/gnupru-build.log cd ${BUILD_DIR} tar cfz ${PRU_FILE} pru-gcc/ @@ -47,7 +47,21 @@ else tar xfz ${PRU_FILE} fi +###################################################################### +# Install or1k-linux-musl toolchain +###################################################################### +echo -e "\n\n=============== Install or1k-linux-musl toolchain\n\n" +TOOLCHAIN=or1k-linux-musl-cross +TOOLCHAIN_ZIP=${TOOLCHAIN}.tgz +GCC_VERSION=10 +TOOLCHAIN_ZIP_V=${TOOLCHAIN}-${GCC_VERSION}.tgz +URL=https://more.musl.cc/${GCC_VERSION}/x86_64-linux-musl/ +if [ ! -f ${CACHE_DIR}/${TOOLCHAIN_ZIP_V} ]; then + curl ${URL}/${TOOLCHAIN_ZIP} -o ${CACHE_DIR}/${TOOLCHAIN_ZIP_V} +fi +cd ${BUILD_DIR} +tar xf ${CACHE_DIR}/${TOOLCHAIN_ZIP_V} ###################################################################### # Create python3 virtualenv environment ###################################################################### diff --git a/scripts/flash-ar100.py b/scripts/flash-ar100.py new file mode 100755 index 000000000000..33198e23c315 --- /dev/null +++ b/scripts/flash-ar100.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python3 +# This file may be distributed under the terms of the GNU GPLv3 license. +import mmap +import argparse +import sys + +FW_START = 0x00004000 +FW_BASE = 0x00040000 + FW_START +FW_LIMIT = 0x00054000 +FW_SIZE = FW_LIMIT - FW_BASE + +EXCEPTIONS_BASE = 0x00040000 +EXCEPTIONS_LIMIT = 0x00042000 +EXCEPTIONS_SIZE = EXCEPTIONS_LIMIT - EXCEPTIONS_BASE +EXCEPTIONS_JUMP = FW_START # All exceptions reset program +NR_OF_EXCEPTIONS = 14 + +R_CPU_CFG_PAGE_BASE = 0x01F01000 +R_CPU_CFG_PAGE_LIMIT = 0x01F02000 +R_CPU_CFG_SIZE = R_CPU_CFG_PAGE_LIMIT - R_CPU_CFG_PAGE_BASE +R_CPU_CFG_OFFSET = 0xC00 +R_CPU_CLK_OFFSET = 0x400 + +parser = argparse.ArgumentParser(description='Flash and reset SRAM A2 of A64') +parser.add_argument('filename', nargs='?', help='binary file to write') +parser.add_argument('--reset', action='store_true', help='reset the AR100') +parser.add_argument('--halt', action='store_true', help='Halt the AR100') +parser.add_argument('--bl31', action='store_true', help='write bl31') + +args = parser.parse_args() + + +def write_exception_vectors(): + print("Writing exception vectors") + with open("/dev/mem", "w+b") as f: + exc = mmap.mmap(f.fileno(), + length=EXCEPTIONS_SIZE, + offset=EXCEPTIONS_BASE) + for i in range(NR_OF_EXCEPTIONS): + add = i * 0x100 + exc[add:add + 4] = ((EXCEPTIONS_JUMP - add) >> 2).to_bytes( + 4, byteorder='little') + exc.close() + + +def assert_deassert_reset(ass): + with open("/dev/mem", "w+b") as f: + r_cpucfg = mmap.mmap(f.fileno(), + length=R_CPU_CFG_SIZE, + offset=R_CPU_CFG_PAGE_BASE) + if ass: + r_cpucfg[R_CPU_CFG_OFFSET] &= ~0x01 + if r_cpucfg[R_CPU_CFG_OFFSET] & 0x01: + print("failed to assert reset") + else: + r_cpucfg[R_CPU_CFG_OFFSET] |= 0x01 + if not (r_cpucfg[R_CPU_CFG_OFFSET] & 0x01): + print("failed to deassert reset") + r_cpucfg.close() + + +def write_file(filename): + with open(filename, "r+b") as fw: + data = fw.read() + if len(data) > FW_SIZE: + print("File does not fit in memory") + sys.exit(1) + print("Writing file to SRAM A2") + with open("/dev/mem", "w+b") as f: + sram_a2 = mmap.mmap(f.fileno(), length=FW_SIZE, offset=FW_BASE) + sram_a2[0:len(data)] = data + sram_a2.close() + + +def clear_magic_word(): + with open("/dev/mem", "w+b") as f: + sram_a2 = mmap.mmap(f.fileno(), length=FW_SIZE, offset=FW_BASE) + sram_a2[0] = 0x0 + sram_a2.close() + + +if args.reset: + print("Resetting AR100") + assert_deassert_reset(1) + assert_deassert_reset(0) + sys.exit(0) + +if args.filename: + if args.bl31: + print("writing bl31") + assert_deassert_reset(1) + write_file(args.filename) + else: + assert_deassert_reset(1) + write_exception_vectors() + write_file(args.filename) + assert_deassert_reset(0) + +if args.halt: + print("Halting AR100") + assert_deassert_reset(1) + clear_magic_word() diff --git a/scripts/flash-linux.sh b/scripts/flash-linux.sh index 56741c1723a2..bd3b4f63ce28 100755 --- a/scripts/flash-linux.sh +++ b/scripts/flash-linux.sh @@ -1,18 +1,23 @@ #!/bin/bash # This script installs the Linux MCU code to /usr/local/bin/ -[[ -z "$OUT" ]] && OUT=out/ - if [ "$EUID" -ne 0 ]; then echo "This script must be run as root" exit -1 fi set -e +# Setting build output directory +if [ -z "${1}" ]; then + out='out' +else + out=${1} +fi + # Install new micro-controller code echo "Installing micro-controller code to /usr/local/bin/" rm -f /usr/local/bin/klipper_mcu -cp ${OUT}klipper.elf /usr/local/bin/klipper_mcu +cp ${out}/klipper.elf /usr/local/bin/klipper_mcu sync # Restart (if system install script present) @@ -26,3 +31,8 @@ if [ -f /etc/init.d/klipper_mcu ]; then echo "Attempting host MCU restart..." service klipper_mcu restart fi + +if [ -f /etc/systemd/system/klipper-mcu.service ]; then + echo "Attempting host MCU restart..." + systemctl restart klipper-mcu +fi diff --git a/scripts/flash_usb.py b/scripts/flash_usb.py index 85f264e96d3e..e43c457c5cff 100755 --- a/scripts/flash_usb.py +++ b/scripts/flash_usb.py @@ -193,6 +193,7 @@ def call_picoboot(bus, addr, binfile, sudo): # Flash via Klipper modified "picoboot" def flash_picoboot(device, binfile, sudo): + ttyname, serbypath = translate_serial_to_tty(device) buspath, devpath = translate_serial_to_usb_path(device) # We need one level up to get access to busnum/devnum files usbdir = os.path.dirname(devpath) @@ -202,7 +203,10 @@ def flash_picoboot(device, binfile, sudo): bus = f.read().strip() with open(usbdir + "/devnum") as f: addr = f.read().strip() - call_picoboot(bus, addr, binfile, sudo) + if detect_canboot(devpath): + call_flashcan(serbypath, binfile) + else: + call_picoboot(bus, addr, binfile, sudo) ###################################################################### @@ -342,7 +346,7 @@ def flash_rp2040(options, binfile): 'stm32f4': flash_stm32f4, 'stm32f042': flash_stm32f4, 'stm32f072': flash_stm32f4, 'stm32g0b1': flash_stm32f4, 'stm32h7': flash_stm32f4, 'stm32l4': flash_stm32f4, - 'rp2040': flash_rp2040, + 'stm32g4': flash_stm32f4, 'rp2040': flash_rp2040, } diff --git a/scripts/graph_accelerometer.py b/scripts/graph_accelerometer.py index 8c09e8471fa0..84b313115bf7 100755 --- a/scripts/graph_accelerometer.py +++ b/scripts/graph_accelerometer.py @@ -17,35 +17,50 @@ def parse_log(logname, opts): with open(logname) as f: for header in f: - if not header.startswith('#'): + if header.startswith('#'): + continue + if header.startswith('freq,psd_x,psd_y,psd_z,psd_xyz'): + # Processed power spectral density file break - if not header.startswith('freq,psd_x,psd_y,psd_z,psd_xyz'): # Raw accelerometer data return np.loadtxt(logname, comments='#', delimiter=',') - # Power spectral density data or shaper calibration data - opts.error("File %s does not contain raw accelerometer data and therefore " - "is not supported by graph_accelerometer.py script. Please use " - "calibrate_shaper.py script to process it instead." % (logname,)) + # Parse power spectral density data + data = np.loadtxt(logname, skiprows=1, comments='#', delimiter=',') + calibration_data = shaper_calibrate.CalibrationData( + freq_bins=data[:,0], psd_sum=data[:,4], + psd_x=data[:,1], psd_y=data[:,2], psd_z=data[:,3]) + calibration_data.set_numpy(np) + return calibration_data ###################################################################### # Raw accelerometer graphing ###################################################################### -def plot_accel(data, logname): - first_time = data[0, 0] - times = data[:,0] - first_time +def plot_accel(datas, lognames): fig, axes = matplotlib.pyplot.subplots(nrows=3, sharex=True) - axes[0].set_title("\n".join(wrap("Accelerometer data (%s)" % (logname,), - MAX_TITLE_LENGTH))) + axes[0].set_title("\n".join(wrap( + "Accelerometer data (%s)" % (', '.join(lognames)), MAX_TITLE_LENGTH))) axis_names = ['x', 'y', 'z'] + for data, logname in zip(datas, lognames): + if isinstance(data, shaper_calibrate.CalibrationData): + raise error("Cannot plot raw accelerometer data using the processed" + " resonances, raw_data input is required") + first_time = data[0, 0] + times = data[:,0] - first_time + for i in range(len(axis_names)): + avg = data[:,i+1].mean() + adata = data[:,i+1] - data[:,i+1].mean() + ax = axes[i] + label = '\n'.join(wrap(logname, 60)) + ' (%+.3f mm/s^2)' % (-avg,) + ax.plot(times, adata, alpha=0.8, label=label) + axes[-1].set_xlabel('Time (s)') + fontP = matplotlib.font_manager.FontProperties() + fontP.set_size('x-small') for i in range(len(axis_names)): - avg = data[:,i+1].mean() - adata = data[:,i+1] - data[:,i+1].mean() ax = axes[i] - ax.plot(times, adata, alpha=0.8) ax.grid(True) - ax.set_ylabel('%s accel (%+.3f)\n(mm/s^2)' % (axis_names[i], -avg)) - axes[-1].set_xlabel('Time (%+.3f)\n(s)' % (-first_time,)) + ax.legend(loc='best', prop=fontP) + ax.set_ylabel('%s accel' % (axis_names[i],)) fig.tight_layout() return fig @@ -56,10 +71,15 @@ def plot_accel(data, logname): # Calculate estimated "power spectral density" def calc_freq_response(data, max_freq): + if isinstance(data, shaper_calibrate.CalibrationData): + return data helper = shaper_calibrate.ShaperCalibrate(printer=None) return helper.process_accelerometer_data(data) def calc_specgram(data, axis): + if isinstance(data, shaper_calibrate.CalibrationData): + raise error("Cannot calculate the spectrogram using the processed" + " resonances, raw_data input is required") N = data.shape[0] Fs = N / (data[-1,0] - data[0,0]) # Round up to a power of 2 for faster FFT @@ -235,9 +255,7 @@ def main(): # Draw graph if options.raw: - if len(args) > 1: - opts.error("Only 1 input is supported in raw mode") - fig = plot_accel(datas[0], args[0]) + fig = plot_accel(datas, args) elif options.specgram: if len(args) > 1: opts.error("Only 1 input is supported in specgram mode") diff --git a/scripts/install-ubuntu-22.04.sh b/scripts/install-ubuntu-22.04.sh new file mode 100644 index 000000000000..e2b9580f5b05 --- /dev/null +++ b/scripts/install-ubuntu-22.04.sh @@ -0,0 +1,102 @@ +#!/bin/bash +# This script installs Klipper on an Ubuntu 22.04 ("Jammy") machine + +PYTHONDIR="${HOME}/klippy-env" +SYSTEMDDIR="/etc/systemd/system" +KLIPPER_USER=$USER +KLIPPER_GROUP=$KLIPPER_USER + +# Step 1: Install system packages +install_packages() +{ + # Packages for python cffi + PKGLIST="virtualenv python3-dev libffi-dev build-essential" + # kconfig requirements + PKGLIST="${PKGLIST} libncurses-dev" + # hub-ctrl + PKGLIST="${PKGLIST} libusb-dev" + # AVR chip installation and building + PKGLIST="${PKGLIST} avrdude gcc-avr binutils-avr avr-libc" + # ARM chip installation and building + PKGLIST="${PKGLIST} stm32flash dfu-util libnewlib-arm-none-eabi" + PKGLIST="${PKGLIST} gcc-arm-none-eabi binutils-arm-none-eabi libusb-1.0" + + # Update system package info + report_status "Running apt-get update..." + sudo apt-get update + + # Install desired packages + report_status "Installing packages..." + sudo apt-get install --yes ${PKGLIST} +} + +# Step 2: Create python virtual environment +create_virtualenv() +{ + report_status "Updating python virtual environment..." + + # Create virtualenv if it doesn't already exist + [ ! -d ${PYTHONDIR} ] && virtualenv -p python3 ${PYTHONDIR} + + # Install/update dependencies + ${PYTHONDIR}/bin/pip install -r ${SRCDIR}/scripts/klippy-requirements.txt +} + +# Step 3: Install startup script +install_script() +{ +# Create systemd service file + KLIPPER_LOG=/tmp/klippy.log + report_status "Installing system start script..." + sudo /bin/sh -c "cat > $SYSTEMDDIR/klipper.service" << EOF +#Systemd service file for klipper +[Unit] +Description=Starts klipper on startup +After=network.target + +[Install] +WantedBy=multi-user.target + +[Service] +Type=simple +User=$KLIPPER_USER +RemainAfterExit=yes +ExecStart=${PYTHONDIR}/bin/python ${SRCDIR}/klippy/klippy.py ${HOME}/printer.cfg -l ${KLIPPER_LOG} +EOF +# Use systemctl to enable the klipper systemd service script + sudo systemctl enable klipper.service +} + +# Step 4: Start host software +start_software() +{ + report_status "Launching Klipper host software..." + sudo systemctl start klipper +} + +# Helper functions +report_status() +{ + echo -e "\n\n###### $1" +} + +verify_ready() +{ + if [ "$EUID" -eq 0 ]; then + echo "This script must not run as root" + exit -1 + fi +} + +# Force script to exit if an error occurs +set -e + +# Find SRCDIR from the pathname of this script +SRCDIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )"/.. && pwd )" + +# Run installation steps defined above +verify_ready +install_packages +create_virtualenv +install_script +start_software diff --git a/scripts/klipper-mcu-start.sh b/scripts/klipper-mcu-start.sh deleted file mode 100755 index f58a6298668a..000000000000 --- a/scripts/klipper-mcu-start.sh +++ /dev/null @@ -1,78 +0,0 @@ -#!/bin/sh -# System startup script to start the MCU Linux firmware - -### BEGIN INIT INFO -# Provides: klipper_mcu -# Required-Start: $local_fs -# Required-Stop: -# Default-Start: 3 4 5 -# Default-Stop: 0 1 2 6 -# Short-Description: Klipper_MCU daemon -# Description: Starts the MCU for Klipper. -### END INIT INFO - -PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin -DESC="klipper_mcu startup" -NAME="klipper_mcu" -KLIPPER_HOST_MCU=/usr/local/bin/klipper_mcu -KLIPPER_HOST_ARGS="-r" -PIDFILE=/var/run/klipper_mcu.pid - -. /lib/lsb/init-functions - -mcu_host_stop() -{ - # Shutdown existing Klipper instance (if applicable). The goal is to - # put the GPIO pins in a safe state. - if [ -c /tmp/klipper_host_mcu ]; then - log_daemon_msg "Attempting to shutdown host mcu..." - set -e - ( echo "FORCE_SHUTDOWN" > /tmp/klipper_host_mcu ) 2> /dev/null || ( log_action_msg "Firmware busy! Please shutdown Klipper and then retry." && exit 1 ) - sleep 1 - ( echo "FORCE_SHUTDOWN" > /tmp/klipper_host_mcu ) 2> /dev/null || ( log_action_msg "Firmware busy! Please shutdown Klipper and then retry." && exit 1 ) - sleep 1 - set +e - fi - - log_daemon_msg "Stopping klipper host mcu" $NAME - killproc -p $PIDFILE $KLIPPER_HOST_MCU -} - -mcu_host_start() -{ - [ -x $KLIPPER_HOST_MCU ] || return - - if [ -c /tmp/klipper_host_mcu ]; then - mcu_host_stop - fi - - log_daemon_msg "Starting klipper MCU" $NAME - start-stop-daemon --start --quiet --exec $KLIPPER_HOST_MCU \ - --background --pidfile $PIDFILE --make-pidfile \ - -- $KLIPPER_HOST_ARGS - log_end_msg $? -} - -case "$1" in -start) - mcu_host_start - ;; -stop) - mcu_host_stop - ;; -restart) - $0 stop - $0 start - ;; -reload|force-reload) - log_daemon_msg "Reloading configuration not supported" $NAME - log_end_msg 1 - ;; -status) - status_of_proc -p $PIDFILE $KLIPPER_HOST_MCU $NAME && exit 0 || exit $? - ;; -*) log_action_msg "Usage: /etc/init.d/klipper_mcu {start|stop|status|restart|reload|force-reload}" - exit 2 - ;; -esac -exit 0 diff --git a/scripts/klipper-mcu.service b/scripts/klipper-mcu.service new file mode 100644 index 000000000000..ca15c86ba412 --- /dev/null +++ b/scripts/klipper-mcu.service @@ -0,0 +1,21 @@ +#Systemd klipper linux mcu Service + +[Unit] +Description=Starts the MCU Linux firmware for klipper on startup +Documentation=https://www.klipper3d.org/RPi_microcontroller.html +Before=klipper.service +ConditionFileIsExecutable=/usr/local/bin/klipper_mcu + +[Install] +WantedBy=multi-user.target + +[Service] +Type=simple +Environment=KLIPPER_HOST_MCU_SERIAL=/tmp/klipper_host_mcu +RemainAfterExit=yes +ExecStart=/usr/local/bin/klipper_mcu -r -I ${KLIPPER_HOST_MCU_SERIAL} +ExecStop=sh -c 'echo "FORCE_SHUTDOWN" > ${KLIPPER_HOST_MCU_SERIAL}' +ExecStop=sleep 1 +TimeoutStopSec=2 +Restart=always +RestartSec=5 diff --git a/scripts/klippy-requirements.txt b/scripts/klippy-requirements.txt index dd46dce02d6b..52a3092350d4 100644 --- a/scripts/klippy-requirements.txt +++ b/scripts/klippy-requirements.txt @@ -4,7 +4,7 @@ # pip install -r klippy-requirements.txt cffi==1.14.6 pyserial==3.4 -greenlet==1.1.2 +greenlet==2.0.2 Jinja2==2.11.3 python-can==3.3.4 markupsafe==1.1.1 diff --git a/scripts/spi_flash/board_defs.py b/scripts/spi_flash/board_defs.py index 0bbb92695af9..df129ec8017f 100644 --- a/scripts/spi_flash/board_defs.py +++ b/scripts/spi_flash/board_defs.py @@ -116,6 +116,12 @@ 'mcu': "stm32f405xx", 'spi_bus': "spi1", "cs_pin": "PA4" + }, + 'fysetc-cheetah': { + 'mcu': "stm32f401xc", + 'spi_bus': "spi1", + "cs_pin": "PA4", + "current_firmware_path": "OLD.BIN" } } @@ -144,7 +150,8 @@ 'btt-skr-e3-dip': BOARD_DEFS['btt-skr-mini'], 'btt002-v1': BOARD_DEFS['btt-skr-mini'], 'creality-v4.2.7': BOARD_DEFS['creality-v4.2.2'], - 'btt-skr-2': BOARD_DEFS['btt-octopus-f407-v1'], + 'btt-skr-2-f407': BOARD_DEFS['btt-octopus-f407-v1'], + 'btt-skr-2-f429': BOARD_DEFS['btt-octopus-f429-v1'], 'btt-octopus-f407-v1.0': BOARD_DEFS['btt-octopus-f407-v1'], 'btt-octopus-f407-v1.1': BOARD_DEFS['btt-octopus-f407-v1'], 'btt-octopus-f429-v1.0': BOARD_DEFS['btt-octopus-f429-v1'], @@ -157,6 +164,7 @@ 'btt-skr-pro-v1.2': BOARD_DEFS['btt-skr-pro'], 'btt-gtr-v1': BOARD_DEFS['btt-gtr'], 'mks-robin-e3d': BOARD_DEFS['mks-robin-e3'], + 'fysetc-cheetah-v2': BOARD_DEFS['fysetc-cheetah'], 'fysetc-spider-v1': BOARD_DEFS['fysetc-spider'], 'fysetc-s6-v1.2': BOARD_DEFS['fysetc-spider'], 'fysetc-s6-v2': BOARD_DEFS['fysetc-spider'], diff --git a/scripts/spi_flash/spi_flash.py b/scripts/spi_flash/spi_flash.py index db1e3f592525..a3231b693219 100644 --- a/scripts/spi_flash/spi_flash.py +++ b/scripts/spi_flash/spi_flash.py @@ -1,7 +1,8 @@ #!/usr/bin/env python2 -# Module supporting uploads Klipper firmware to an SD Card via SPI +# Module supporting uploads Klipper firmware to an SD Card via SPI and SDIO # # Copyright (C) 2021 Eric Callahan +# Copyright (C) 2022 H. Gregor Molter # # This file may be distributed under the terms of the GNU GPLv3 license. import sys @@ -36,7 +37,7 @@ def output(msg): sys.stdout.write("%s" % (msg,)) sys.stdout.flush() -def calc_crc7(data): +def calc_crc7(data, with_padding=True): # G(x) = x^7 + x^3 + 1 # Shift left as we are only calculating a 7 bit CRC poly = 0b10001001 << 1 @@ -47,6 +48,8 @@ def calc_crc7(data): crc = (crc << 1) ^ poly if crc & 0x80 else crc << 1 # The sdcard protocol likes the crc left justfied with a # padded bit + if not with_padding: + return crc return crc | 1 def calc_crc16(data): @@ -89,11 +92,12 @@ def check_need_convert(board_name, config): ########################################################### # -# SPI FLash Implementation +# SPI / SDIO Flash Implementation # ########################################################### SPI_OID = 0 +SDIO_OID = 0 SPI_MODE = 0 SD_SPI_SPEED = 400000 # MCU Command Constants @@ -114,6 +118,20 @@ def check_need_convert(board_name, config): SPI_SEND_CMD = "spi_send oid=%c data=%*s" SPI_XFER_CMD = "spi_transfer oid=%c data=%*s" SPI_XFER_RESPONSE = "spi_transfer_response oid=%c response=%*s" +SDIO_CFG_CMD = "config_sdio oid=%d blocksize=%u" +SDIO_BUS_CMD = "sdio_set_bus oid=%d sdio_bus=%s" +SDIO_SEND_CMD = "sdio_send_command oid=%c cmd=%c argument=%u wait=%c" +SDIO_SEND_CMD_RESPONSE = "sdio_send_command_response oid=%c error=%c " \ + "response=%*s" +SDIO_READ_DATA="sdio_read_data oid=%c cmd=%c argument=%u" +SDIO_READ_DATA_RESPONSE="sdio_read_data_response oid=%c error=%c read=%u" +SDIO_WRITE_DATA="sdio_write_data oid=%c cmd=%c argument=%u" +SDIO_WRITE_DATA_RESPONSE="sdio_write_data_response oid=%c error=%c write=%u" +SDIO_READ_DATA_BUFFER="sdio_read_data_buffer oid=%c offset=%u len=%c" +SDIO_READ_DATA_BUFFER_RESPONSE="sdio_read_data_buffer_response oid=%c data=%*s" +SDIO_WRITE_DATA_BUFFER="sdio_write_data_buffer oid=%c offset=%u data=%*s" +SDIO_SET_SPEED="sdio_set_speed oid=%c speed=%u" + FINALIZE_CFG_CMD = "finalize_config crc=%d" class SPIFlashError(Exception): @@ -135,6 +153,40 @@ def spi_send(self, data): def spi_transfer(self, data): return self._spi_transfer_cmd.send([self.oid, data]) +class SDIODirect: + def __init__(self, ser): + self.oid = SDIO_OID + self._sdio_send_cmd = mcu.CommandQueryWrapper( + ser, SDIO_SEND_CMD, SDIO_SEND_CMD_RESPONSE, self.oid) + self._sdio_read_data = mcu.CommandQueryWrapper( + ser, SDIO_READ_DATA, SDIO_READ_DATA_RESPONSE, self.oid) + self._sdio_write_data = mcu.CommandQueryWrapper( + ser, SDIO_WRITE_DATA, SDIO_WRITE_DATA_RESPONSE, self.oid) + self._sdio_read_data_buffer = mcu.CommandQueryWrapper( + ser, SDIO_READ_DATA_BUFFER, SDIO_READ_DATA_BUFFER_RESPONSE, + self.oid) + self._sdio_write_data_buffer = mcu.CommandWrapper(ser, + SDIO_WRITE_DATA_BUFFER) + self._sdio_set_speed = mcu.CommandWrapper(ser, SDIO_SET_SPEED) + + def sdio_send_cmd(self, cmd, argument, wait): + return self._sdio_send_cmd.send([self.oid, cmd, argument, wait]) + + def sdio_read_data(self, cmd, argument): + return self._sdio_read_data.send([self.oid, cmd, argument]) + + def sdio_write_data(self, cmd, argument): + return self._sdio_write_data.send([self.oid, cmd, argument]) + + def sdio_read_data_buffer(self, offset, length=32): + return self._sdio_read_data_buffer.send([self.oid, offset, length]) + + def sdio_write_data_buffer(self, offset, data): + return self._sdio_write_data_buffer.send([self.oid, offset, data]) + + def sdio_set_speed(self, speed): + return self._sdio_set_speed.send([self.oid, speed]) + # FatFs Constants. Enums are implemented as lists. The item's index is its value DRESULT = ['RES_OK', 'RES_ERROR', 'RES_WRPRT', 'RES_NOTRDY', 'RES_PARERR'] @@ -154,8 +206,11 @@ def spi_transfer(self, data): # FAT16/32 File System Support class FatFS: - def __init__(self, ser): - self.sdcard = SDCardSPI(ser) + def __init__(self, ser, spi=True): + if spi: + self.sdcard = SDCardSPI(ser) + else: + self.sdcard = SDCardSDIO(ser) self.disk_status = STA_NO_INIT | STA_NO_DISK self.ffi_callbacks = [] self.ffi_main, self.ffi_lib = fatfs_lib.get_fatfs_ffi() @@ -429,6 +484,10 @@ def __exit__(self, exc_type=None, exc_val=None, exc_tb=None): SD_COMMANDS = { 'GO_IDLE_STATE': 0, + 'ALL_SEND_CID': 2, + 'SET_REL_ADDR': 3, + 'SET_BUS_WIDTH': 6, + 'SEL_DESEL_CARD': 7, 'SEND_IF_COND': 8, 'SEND_CSD': 9, 'SEND_CID': 10, @@ -785,6 +844,322 @@ def write_sector(self, sector, data): if err_msgs: raise OSError("\n".join(err_msgs)) +class SDCardSDIO: + def __init__(self, ser): + self.sdio = SDIODirect(ser) + self.rca = 0 + self.reactor = ser.get_reactor() + self.enable_crc = True + self.mutex = self.reactor.mutex() + self.initialized = False + self.sd_version = 0 + self.high_capacity = False + self.write_protected = False + self.total_sectors = 0 + self.card_info = collections.OrderedDict() + + def init_sd(self): + def check_for_ocr_errors(reg): + # returns False if an error flag is set + return ((reg[0]&0xFD) | (reg[1]&0xFF) | + (reg[2]&0xE0) | (reg[3]&0x08)) == 0 + with self.mutex: + if self.initialized: + return + # Send reset command (CMD0) + if not self._send_command('GO_IDLE_STATE', 0): + raise OSError( + "flash_sdcard: failed to reset SD Card\n" + "Note that older (Version 1.0) SD cards can not be\n" + "hot swapped. Execute FIRMWARE_RESTART with the card\n" + "inserted for successful initialization.") + # Check Voltage Range (CMD8). Only Cards meeting the v2.0 spec + # support this. V1.0 cards (and MMC) will return illegal command. + check_pattern = 0b1010 + resp = self._send_command_with_response( + 'SEND_IF_COND', (1 << 8) | check_pattern) + resp = resp.strip(b'\xFF') + if len(resp) != 4: + # CMD8 is illegal, this is a version 1.0 card + self.sd_version = 1 + else: + self.sd_version = 2 + if not (resp[-2] == 1 and resp[-1] == check_pattern): + raise OSError("flash_sdcard: SD Card not running in a " + "compatible voltage range") + if self.sd_version == 2: + + # Init card and come out of idle (ACMD41) + # Version 2 Cards may init before checking the OCR + # Allow vor LVDS card with 1.8v, too. + resp = self._check_command(lambda x: x[0]>>7 == 1, + 'SD_SEND_OP_COND', 0xC1100000, is_app_cmd=True, + ignoreCRC=True) + if resp is None: + raise OSError("flash_sdcard: SD Card did not come" + " out of IDLE after reset") + if len(resp) == 4: + if self.sd_version == 1: + # Check acceptable volatage range for V1 cards + if resp[1] != 0xFF: + raise OSError("flash_sdcard: card does not support" + " 3.3v range") + elif self.sd_version == 2: + # Determine if this is a high capacity sdcard + if resp[0] & 0x40: + self.high_capacity = True + else: + raise OSError("flash_sdcard: Invalid OCR Response") + if self.sd_version == 1: + # Init card and come out of idle (ACMD41) + # Version 1 Cards do this after checking the OCR + if not self._check_command(0, 'SD_SEND_OP_COND', 0, + is_app_cmd=True): + raise OSError("flash_sdcard: SD Card did not come" + " out of IDLE after reset") + + # Read out CID information register + self._process_cid_reg() + + # Get card's relative address (RCA) + resp = self._send_command_with_response('SET_REL_ADDR', 0) + # Check if bits 15:13 have some error set + if (resp[-2] & 0xe0) != 0: + raise OSError("flash_sdcard: set card's " + "relative address failed") + self.rca = resp[0]<<8 | resp[1] + + # Read out CSD information register + self._process_csd_reg() + + # Select the current card + if not self._check_command(check_for_ocr_errors, 'SEL_DESEL_CARD', + self.rca << 16, tries=1): + raise OSError("flash_sdcard: failed to select the card") + + # Set SDIO clk speed to approx. 1 MHz + self.sdio.sdio_set_speed(1000000) + + if self._check_command(check_for_ocr_errors, 'SET_BLOCKLEN', + SECTOR_SIZE, tries=5): + self.initialized = True + else: + raise OSError("flash_sdcard: failed to set block size") + + + def deinit(self): + with self.mutex: + if self.initialized: + # Reset the SD Card + try: + if not self._send_command('GO_IDLE_STATE', 0): + logging.info("flash_sdcard: failed to reset SD Card") + except Exception: + logging.exception("Error resetting SD Card") + self.initialized = False + self.sd_version = 0 + self.high_capacity = False + self.total_sectors = 0 + self.card_info.clear() + + def _check_command(self, check_func, cmd, args, is_app_cmd=False, tries=15, + ignoreCRC=False): + func = self._send_app_cmd_with_response if is_app_cmd else \ + self._send_command_with_response + while True: + resp, rt = func(cmd, args, get_rt=True, ignoreCRC=ignoreCRC) + #logging.info("flash_sdcard: Check cmd %s, response: %s" + # % (cmd, repr(resp))) + if resp and check_func(resp): + return resp + tries -= 1 + if tries < 1: + return None + self.reactor.pause(rt + .1) + + def _send_command(self, cmd, args, wait=0): + cmd_code = SD_COMMANDS[cmd] + argument = 0 + if isinstance(args, int) or isinstance(args, long): + argument = args & 0xFFFFFFFF + elif isinstance(args, list) and len(args) == 4: + argument = ((args[0] << 24) & 0xFF000000) | \ + ((args[1] << 16) & 0x00FF0000) | \ + ((args[2] << 8) & 0x0000FF00) | \ + ((args[3] << 0) & 0x000000FF) + else: + raise OSError("flash_sdcard: Invalid SD Card Command argument") + params = self.sdio.sdio_send_cmd(cmd_code, argument, wait) + #logging.debug(f'_send_command({cmd=}, {args=}, {wait=}) -> ' + # 'CMD: {cmd_code} ARG: {argument} -> {params=}') + if (wait == 0): + # Just return the error code if no response was requested + return params['error'] == 0 + return params + + def _send_command_with_response(self, cmd, args, check_error=True, + ignoreCRC=False, get_rt=False): + # Wait for a short response + params = self._send_command(cmd, args, wait=1) + response = params['response'] + if check_error: + if params['error'] != 0: + if ignoreCRC and params['error'] != 4: + response = [] + if get_rt: + return bytearray(response), params['#receive_time'] + else: + return bytearray(response) + + def _send_app_cmd_with_response(self, cmd, args, + ignoreCRC=False, get_rt=False): + # CMD55 tells the SD Card that the next command is an + # Application Specific Command. + self._send_command_with_response('APP_CMD', self.rca << 16) + return self._send_command_with_response( + cmd, args, ignoreCRC=ignoreCRC, get_rt=get_rt) + + def _process_cid_reg(self): + params = self._send_command('ALL_SEND_CID', 0, wait=2) + reg = bytearray(params['response']) + if reg is None: + raise OSError("flash_sdcard: Error reading CID register") + + cid = collections.OrderedDict() + cid['manufacturer_id'] = reg[0] + cid['oem_id'] = reg[1:3].decode(encoding='ascii', errors='ignore') + cid['product_name'] = reg[3:8].decode( + encoding='ascii', errors='ignore') + cid['product_revision'] = str(reg[8] >> 4 & 0xFF) + "." \ + + str(reg[8] & 0xFF) + cid['serial_number'] = "".join(["%02X" % (c,) for c in reg[9:13]]) + mfg_year = (((reg[13] & 0xF) << 4) | ((reg[14] >> 4) & 0xF)) + 2000 + mfg_month = reg[14] & 0xF + cid['manufacturing_date'] = "%d/%d" % (mfg_month, mfg_year) + crc = calc_crc7(reg[:15], with_padding=False) + if crc != reg[15]: + raise OSError("flash_sdcard: CID crc mismatch: 0x%02X, recd: 0x%02X" + % (crc, reg[15])) + self.card_info.update(cid) + + def _process_csd_reg(self): + params = self._send_command('SEND_CSD', self.rca << 16, wait=2) + reg = bytearray(params['response']) + if reg is None: + raise OSError("flash_sdcard: Error reading CSD register") + str_capacity = "Invalid" + max_capacity = 0 + csd_type = (reg[0] >> 6) & 0x3 + if csd_type == 0: + # Standard Capacity (CSD Version 1.0) + max_block_len = 2**(reg[5] & 0xF) + c_size = ((reg[6] & 0x3) << 10) | (reg[7] << 2) | \ + ((reg[8] >> 6) & 0x3) + c_mult = 2**((((reg[9] & 0x3) << 1) | (reg[10] >> 7)) + 2) + max_capacity = (c_size + 1) * c_mult * max_block_len + str_capacity = "%.1f MiB" % (max_capacity / (1024.0**2)) + elif csd_type == 1: + # High Capacity (CSD Version 2.0) + c_size = ((reg[7] & 0x3F) << 16) | (reg[8] << 8) | reg[9] + max_capacity = (c_size + 1) * 512 * 1024 + str_capacity = "%.1f GiB" % (max_capacity / (1024.0**3)) + else: + logging.info("sdcard: Unsupported csd type: %d" % (csd_type)) + self.write_protected = (reg[14] & 0x30) != 0 + crc = calc_crc7(reg[:15], with_padding=False) + if crc != reg[15]: + raise OSError("flash_sdcard: CSD crc mismatch: 0x%02X, recd: 0x%02X" + % (crc, reg[15])) + self.card_info['capacity'] = str_capacity + self.total_sectors = max_capacity // SECTOR_SIZE + + def print_card_info(self, print_func=logging.info): + print_func("\nSD Card Information:") + print_func("Version: %.1f" % (self.sd_version)) + print_func("SDHC/SDXC: %s" % (self.high_capacity)) + print_func("Write Protected: %s" % (self.write_protected)) + print_func("Sectors: %d" % (self.total_sectors,)) + for name, val in self.card_info.items(): + print_func("%s: %s" % (name, val)) + + def read_sector(self, sector): + buf = None + err_msg = "flash_sdcard: read error, sector %d" % (sector,) + with self.mutex: + if not 0 <= sector < self.total_sectors: + err_msg += " out of range" + elif not self.initialized: + err_msg += ", SD Card not initialized" + else: + offset = sector + if not self.high_capacity: + offset = sector * SECTOR_SIZE + + params = self.sdio.sdio_read_data( + SD_COMMANDS['READ_SINGLE_BLOCK'], offset) + if params['error'] != 0: + raise OSError( + 'Read data failed. Error code=%d' %(params['error'],) ) + if params['read'] != SECTOR_SIZE: + raise OSError( + 'Read data failed. Expected %d bytes but got %d.' % + (SECTOR_SIZE, params['read']) ) + + buf = bytearray() + offset = 0 + while SECTOR_SIZE-len(buf)>0: + rest = min(SECTOR_SIZE-len(buf), 32) + params = self.sdio.sdio_read_data_buffer( + offset, length=rest) + temp = bytearray(params['data']) + if len(temp) == 0: + raise OSError("Read zero bytes from buffer") + buf += temp + offset += len(temp) + if buf is None: + raise OSError(err_msg) + return buf + + def write_sector(self, sector, data): + with self.mutex: + if not 0 <= sector < self.total_sectors: + raise OSError( + "flash_sdcard: write error, sector number %d invalid" + % (sector)) + if not self.initialized: + raise OSError("flash_sdcard: write error, SD Card not" + " initialized") + outbuf = bytearray(data) + if len(outbuf) > SECTOR_SIZE: + raise OSError("sd_card: Cannot write sector larger" + " than %d bytes" + % (SECTOR_SIZE)) + elif len(outbuf) < SECTOR_SIZE: + outbuf += bytearray([0] * (SECTOR_SIZE - len(outbuf))) + offset = sector + if not self.high_capacity: + offset = sector * SECTOR_SIZE + + CHUNKSIZE = 32 + for i in range(0, SECTOR_SIZE, CHUNKSIZE): + self.sdio.sdio_write_data_buffer(i, outbuf[i:i+CHUNKSIZE]) + params = self.sdio.sdio_write_data( + SD_COMMANDS['WRITE_BLOCK'], offset) + if (params['error'] != 0) or (params['write'] != SECTOR_SIZE): + raise OSError( + "flash_sdcard: Error writing to sector %d"% (sector,)) + + status = self._send_command_with_response( + 'SEND_STATUS', self.rca << 16) + if len(status) != 4: + raise OSError("flash_sdcard: Failed to get status response" + " after write: %s" % (repr(status),)) + if ((status[3]>>1) & 0x0F) != 0: + # Bit 12:9 are not "0" (card is in idle) + raise OSError("flash_sdcard: Write error." + " Card is not in transfer state: 0x%02X" + % (((status[3]>>1) & 0x0F))) + SDIO_WARNING = """ This board requires a manual reboot to complete the flash process. If the board's bootloader uses SDIO mode for its SDCard, then a full @@ -896,7 +1271,7 @@ def check_need_restart(self): return True return False - def configure_mcu(self, printfunc=logging.info): + def _configure_mcu_spibus(self, printfunc=logging.info): # TODO: add commands for buttons? Or perhaps an endstop? We # just need to be able to query the status of the detect pin cs_pin = self.board_config['cs_pin'].upper() @@ -952,6 +1327,41 @@ def configure_mcu(self, printfunc=logging.info): raise SPIFlashError( "Failed to Initialize SD Card. Is it inserted?") + def _configure_mcu_sdiobus(self, printfunc=logging.info): + bus = self.board_config['sdio_bus'] + bus_enums = self.enumerations.get( + 'sdio_bus', self.enumerations.get('bus')) + pin_enums = self.enumerations.get('pin') + if bus not in bus_enums: + raise SPIFlashError("Invalid SDIO Bus: %s" % (bus,)) + bus_cmd = SDIO_BUS_CMD % (SDIO_OID, bus) + sdio_cfg_cmd = SDIO_CFG_CMD % (SDIO_OID, SECTOR_SIZE) + cfg_cmds = [ALLOC_OIDS_CMD % (1,), sdio_cfg_cmd, bus_cmd] + for cmd in cfg_cmds: + self._serial.send(cmd) + config_crc = zlib.crc32('\n'.join(cfg_cmds).encode()) & 0xffffffff + self._serial.send(FINALIZE_CFG_CMD % (config_crc,)) + config = self.get_mcu_config() + if not config["is_config"] or config["is_shutdown"]: + raise MCUConfigError("Failed to configure MCU") + printfunc("Initializing SD Card and Mounting file system...") + self.fatfs = FatFS(self._serial,spi=False) + self.reactor.pause(self.reactor.monotonic() + .5) + try: + self.fatfs.mount(printfunc) + except OSError: + logging.exception("SD Card Mount Failure") + raise SPIFlashError( + "Failed to Initialize SD Card. Is it inserted?") + + def configure_mcu(self, printfunc=logging.info): + if 'spi_bus' in self.board_config: + self._configure_mcu_spibus(printfunc=printfunc) + elif 'sdio_bus' in self.board_config: + self._configure_mcu_sdiobus(printfunc=printfunc) + else: + raise SPIFlashError("Unknown bus defined in board_defs.py.") + def sdcard_upload(self): output("Uploading Klipper Firmware to SD Card...") input_sha = hashlib.sha1() diff --git a/scripts/update_chitu.py b/scripts/update_chitu.py index 1d993b46afcc..a1ef4d8bdb59 100755 --- a/scripts/update_chitu.py +++ b/scripts/update_chitu.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # Encodes STM32 firmwares to be flashable from SD card by Chitu motherboards. # Relocate firmware to 0x08008800! diff --git a/scripts/update_mks_robin.py b/scripts/update_mks_robin.py index 6ab542422a23..fab9faa1e0b6 100755 --- a/scripts/update_mks_robin.py +++ b/scripts/update_mks_robin.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # Script to update firmware for MKS Robin bootloader # # Copyright (C) 2020 Kevin O'Connor diff --git a/src/Kconfig b/src/Kconfig index cfad688d5179..aad59e6db6d6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -4,7 +4,6 @@ mainmenu "Klipper Firmware Configuration" config LOW_LEVEL_OPTIONS bool "Enable extra low-level configuration options" - default n help Enable low-level configuration options that (if modified) may result in a build that does not function correctly. @@ -21,10 +20,14 @@ choice bool "LPC176x (Smoothieboard)" config MACH_STM32 bool "STMicroelectronics STM32" + config MACH_HC32F460 + bool "Huada Semiconductor HC32F460" config MACH_RP2040 bool "Raspberry Pi RP2040" config MACH_PRU bool "Beaglebone PRU" + config MACH_AR100 + bool "Allwinner A64 AR100" config MACH_LINUX bool "Linux process" config MACH_SIMU @@ -36,16 +39,16 @@ source "src/atsam/Kconfig" source "src/atsamd/Kconfig" source "src/lpc176x/Kconfig" source "src/stm32/Kconfig" +source "src/hc32f460/Kconfig" source "src/rp2040/Kconfig" source "src/pru/Kconfig" +source "src/ar100/Kconfig" source "src/linux/Kconfig" source "src/simulator/Kconfig" # Generic configuration options for serial ports config SERIAL bool -config SERIAL_BOOTLOADER_SIDECHANNEL - bool config SERIAL_BAUD depends on SERIAL int "Baud rate for serial port" if LOW_LEVEL_OPTIONS @@ -111,31 +114,26 @@ config INITIAL_PINS # if the hardware does not support the feature. config HAVE_GPIO bool - default n config HAVE_GPIO_ADC bool - default n config HAVE_GPIO_SPI bool - default n +config HAVE_GPIO_SDIO + bool config HAVE_GPIO_I2C bool - default n config HAVE_GPIO_HARD_PWM bool - default n config HAVE_GPIO_BITBANGING bool - default n config HAVE_STRICT_TIMING bool - default n config HAVE_CHIPID bool - default n config HAVE_STEPPER_BOTH_EDGE bool - default n +config HAVE_BOOTLOADER_REQUEST + bool config INLINE_STEPPER_HACK # Enables gcc to inline stepper_event() into the main timer irq handler diff --git a/src/Makefile b/src/Makefile index f5c32f1a81cb..dc0427c70689 100644 --- a/src/Makefile +++ b/src/Makefile @@ -5,6 +5,7 @@ src-$(CONFIG_HAVE_GPIO) += initial_pins.c gpiocmds.c stepper.c endstop.c \ trsync.c src-$(CONFIG_HAVE_GPIO_ADC) += adccmds.c src-$(CONFIG_HAVE_GPIO_SPI) += spicmds.c thermocouple.c +src-$(CONFIG_HAVE_GPIO_SDIO) += sdiocmds.c src-$(CONFIG_HAVE_GPIO_I2C) += i2ccmds.c src-$(CONFIG_HAVE_GPIO_HARD_PWM) += pwmcmds.c bb-src-$(CONFIG_HAVE_GPIO_SPI) := spi_software.c sensor_adxl345.c sensor_angle.c diff --git a/src/ar100/Kconfig b/src/ar100/Kconfig new file mode 100644 index 000000000000..fc7743da80f8 --- /dev/null +++ b/src/ar100/Kconfig @@ -0,0 +1,21 @@ +# Kconfig settings for AR100 + +if MACH_AR100 + +config AR100_SELECT + bool + default y + select HAVE_GPIO + select HAVE_GPIO_SPI + select HAVE_GPIO_BITBANGING + select HAVE_STEPPER_BOTH_EDGE + +config BOARD_DIRECTORY + string + default "ar100" + +config CLOCK_FREQ + int + default 300000000 + +endif diff --git a/src/ar100/Makefile b/src/ar100/Makefile new file mode 100644 index 000000000000..d1203a0e8b1f --- /dev/null +++ b/src/ar100/Makefile @@ -0,0 +1,45 @@ +CROSS_PREFIX=or1k-linux-musl- +dirs-y += src/generic src/ar100 lib/ar100 + +CFLAGS += -O3 +CFLAGS += -fno-builtin +CFLAGS += -fno-pie +CFLAGS += -ffreestanding +CFLAGS += -msfimm -mshftimm -msoft-div -msoft-mul +CFLAGS += -Ilib/ar100 +CFLAGS_klipper.elf := $(CFLAGS) -T src/ar100/ar100.ld +CFLAGS_klipper.elf += -Wl,--gc-sections -static +CFLAGS_klipper.elf += -Wl,--no-dynamic-linker + +SFLAGS = -nostdinc -MMD +SFLAGS += -Ilib/ar100 + +# Add source files +src-y += ar100/main.c ar100/gpio.c ar100/serial.c +src-y += ar100/util.c ar100/timer.c +src-y += generic/crc16_ccitt.c generic/timer_irq.c + +# Remove files that are not needed to save space +src-y := $(filter-out lcd_hd44780.c,$(src-y)) +src-y := $(filter-out lcd_st7920.c,$(src-y)) +src-y := $(filter-out sensor_angle.c,$(src-y)) +src-y := $(filter-out thermocouple.c,$(src-y)) + +OBJS_klipper.elf += $(OUT)lib/ar100/start.o +OBJS_klipper.elf += $(OUT)lib/ar100/runtime.o + +# Build the AR100 binary +target-y += $(OUT)ar100.bin + +$(OUT)lib/ar100/start.o: + @echo " Compiling $@" + $(Q)$(CC) $(SFLAGS) -c $(PWD)/lib/ar100/start.S -o $@ + +$(OUT)lib/ar100/runtime.o: + @echo " Compiling $@" + $(Q)$(CC) $(SFLAGS) -c $(PWD)/lib/ar100/runtime.S -o $@ + +$(OUT)ar100.bin: $(OUT)klipper.elf + @echo " Object copy $@" + $(OBJCOPY) -O binary -S --reverse-bytes 4 $(OUT)klipper.elf $@ + truncate -s %8 $@ diff --git a/src/ar100/ar100.ld b/src/ar100/ar100.ld new file mode 100644 index 000000000000..903620b55485 --- /dev/null +++ b/src/ar100/ar100.ld @@ -0,0 +1,58 @@ +OUTPUT_ARCH(or1k) +OUTPUT_FORMAT(elf32-or1k) +ENTRY (start) + +STACK_SIZE = 0x200; +SRAM_A2_SIZE = 64K; +ORIG = 0x4000; +MEMORY { + SRAM_A2 (rwx): ORIGIN = ORIG, LENGTH = SRAM_A2_SIZE +} + +SECTIONS +{ + . = ORIG; + + .text . : ALIGN(4) { + KEEP(*(.text.start)) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.text*))) + . = ALIGN(4); + } >SRAM_A2 + + .data . : ALIGN(4) { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + __data_start = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.data*))) + . = ALIGN(4); + __data_end = .; + } >SRAM_A2 + + .copy . : ALIGN(4) { + __copy_start = .; + . += __data_end - __data_start; + __copy_end = .; + . = ALIGN(4); + } >SRAM_A2 + + .bss . : ALIGN(4) { + __bss_start = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + . = ALIGN(4); + __bss_end = .; + + __stack_start = .; + . += STACK_SIZE; + __stack_end = .; + } >SRAM_A2 + + ASSERT(. <= (SRAM_A2_SIZE), "Klipper image is too large") + + /DISCARD/ : { + *(.comment*) + *(.eh_frame_hdr*) + *(.iplt*) + *(.note*) + *(.rela*) + *( .compile_time_request ) + } +} diff --git a/src/ar100/gpio.c b/src/ar100/gpio.c new file mode 100644 index 000000000000..96a731d448a9 --- /dev/null +++ b/src/ar100/gpio.c @@ -0,0 +1,127 @@ +// GPIO functions on ar100 +// +// Copyright (C) 2020-2021 Elias Bakken +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "gpio.h" +#include "command.h" +#include "internal.h" +#include "util.h" + +DECL_ENUMERATION_RANGE("pin", "PL0", 0*32, 13); +DECL_ENUMERATION_RANGE("pin", "PB0", 1*32, 10); +DECL_ENUMERATION_RANGE("pin", "PC0", 2*32, 17); +DECL_ENUMERATION_RANGE("pin", "PD0", 3*32, 25); +DECL_ENUMERATION_RANGE("pin", "PE0", 4*32, 18); +DECL_ENUMERATION_RANGE("pin", "PF0", 5*32, 7); +DECL_ENUMERATION_RANGE("pin", "PG0", 6*32, 14); +DECL_ENUMERATION_RANGE("pin", "PH0", 7*32, 12); + +#define BANK(x) (x/32) +#define PIN(x) (x%32) +#define CFG_REG(x) ((x/8)*4) +#define CFG_OFF(x) ((x%8)*4) +#define PULLUP_REG(x) 0x1C + ((x/16)*4) +#define PULLUP_OFF(x) ((x%16)*2) + +volatile uint32_t data_regs[8]; + +struct gpio_mux gpio_mux_setup(uint8_t pin, enum pin_func func){ + uint8_t bank = BANK(pin); + uint8_t p = PIN(pin); + uint32_t data_reg = PIO_BASE + bank*0x24 + 0x10; + uint32_t cfg_reg = PIO_BASE + bank*0x24 + CFG_REG(p); + uint8_t cfg_off = CFG_OFF(p); + + if(bank == 0) { // Handle R_PIO + data_reg = R_PIO_BASE + 0x10; + cfg_reg = R_PIO_BASE + CFG_REG(p); + } + + uint32_t curr_val = read_reg(cfg_reg) & ~(0xF< + +struct gpio_out { + uint8_t pin; + uint8_t bank; + uint32_t reg; +}; + +struct gpio_in { + uint8_t pin; + uint8_t bank; + uint32_t reg; +}; + +extern volatile uint32_t data_regs[8]; + + +struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up); +void gpio_in_reset(struct gpio_in pin, int8_t pull_up); +uint8_t gpio_in_read(struct gpio_in pin); + +struct gpio_out gpio_out_setup(uint8_t pin, uint8_t val); +void gpio_out_write(struct gpio_out pin, uint8_t val); +void gpio_out_reset(struct gpio_out pin, uint8_t val); +void gpio_out_toggle_noirq(struct gpio_out pin); +void gpio_out_toggle(struct gpio_out pin); +struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up); +void gpio_in_reset(struct gpio_in pin, int8_t pull_up); +uint8_t gpio_in_read(struct gpio_in pin); + +struct spi_config { + void *spi; + uint32_t spi_cr1; +}; +struct spi_config spi_setup(uint32_t bus, uint8_t mode, uint32_t rate); +void spi_prepare(struct spi_config config); +void spi_transfer(struct spi_config config, uint8_t receive_data + , uint8_t len, uint8_t *data); + +#endif diff --git a/src/ar100/internal.h b/src/ar100/internal.h new file mode 100644 index 000000000000..406a4cd2970f --- /dev/null +++ b/src/ar100/internal.h @@ -0,0 +1,34 @@ +#ifndef __AR100_INTERNAL_H +#define __AR100_INTERNAL_H + +#define R_PIO_BASE 0x01F02C00 +#define PIO_BASE 0x01C20800 + +enum pin_func { + PIO_INPUT, + PIO_OUTPUT, + PIO_ALT1, + PIO_ALT2, + PIO_ALT3, + PIO_ALT4, + PIO_ALT5, + PIO_DISABLE +}; + +struct gpio_mux { + uint32_t pin; + uint8_t bank; + uint32_t reg; +}; + +struct gpio_mux gpio_mux_setup(uint8_t pin, enum pin_func func); +static inline unsigned long mfspr(unsigned long add){ + unsigned long ret; + __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add)); + return ret; +} +static inline void mtspr(unsigned long add, unsigned long val){ + __asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val)); +} + +#endif // internal.h diff --git a/src/ar100/main.c b/src/ar100/main.c new file mode 100644 index 000000000000..2704144f3c7f --- /dev/null +++ b/src/ar100/main.c @@ -0,0 +1,157 @@ +// Main entry point for ar100 +// +// Copyright (C) 2020-2021 Elias Bakken +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include // uint32_t +#include +#include "board/misc.h" // dynmem_start +#include "board/irq.h" // irq_disable +#include "command.h" // shutdown +#include "generic/timer_irq.h" // timer_dispatch_many +#include "sched.h" // sched_main + +#include "asm/spr.h" +#include "util.h" +#include "gpio.h" +#include "serial.h" +#include "timer.h" + +DECL_CONSTANT_STR("MCU", "ar100"); + +#define RESET_VECTOR 0x0100 + +static struct task_wake console_wake; +static uint8_t receive_buf[192]; +static int receive_pos; +static char dynmem_pool[8 * 1024]; + +void * +dynmem_start(void) +{ + return dynmem_pool; +} + +void * +dynmem_end(void) +{ + return &dynmem_pool[sizeof(dynmem_pool)]; +} + +void +irq_disable(void) +{ +} + +void +irq_enable(void) +{ +} + +irqstatus_t +irq_save(void) +{ + return 0; +} + +void +irq_restore(irqstatus_t flag) +{ +} + +void +irq_wait(void) +{ + irq_poll(); +} + +void +irq_poll(void) +{ + if(timer_interrupt_pending()) { + timer_clear_interrupt(); + uint32_t next = timer_dispatch_many(); + timer_set(next); + } + if(r_uart_fifo_rcv()) + sched_wake_task(&console_wake); +} + +/**************************************************************** +* Console IO +****************************************************************/ + +// Process any incoming commands +void +console_task(void) +{ + if (!sched_check_wake(&console_wake)) + return; + + int ret = 0; + for(int i=0; i MESSAGE_MAX ? MESSAGE_MAX : len; + ret = command_find_and_dispatch(receive_buf, msglen, &pop_count); + if (ret) { + len -= pop_count; + if (len) { + memcpy(receive_buf, &receive_buf[pop_count], len); + sched_wake_task(&console_wake); + } + } + receive_pos = len; +} +DECL_TASK(console_task); + +// Encode and transmit a "response" message +void +console_sendf(const struct command_encoder *ce, va_list args) +{ + uint8_t buf[MESSAGE_MAX]; + uint_fast8_t msglen = command_encode_and_frame(buf, ce, args); + + for(int i=0; i +// +// This file may be distributed under the terms of the GNU GPLv3 license. + + +#include "serial.h" +#include "util.h" +#include "internal.h" +#include "gpio.h" + +void r_uart_init(void){ + // Setup Pins PL2, PL3 as UART IO + gpio_mux_setup(2, PIO_ALT1); + gpio_mux_setup(3, PIO_ALT1); + + // Enable clock and assert reset + clear_bit(APB0_CLK_GATING_REG, 4); + set_bit(APB0_SOFT_RST_REG, 4); + set_bit(APB0_CLK_GATING_REG, 4); + + // Setup baud rate + set_bit(R_UART_LCR, 7); // Enable setting DLH, DLL + write_reg(R_UART_DLH, 0x0); + write_reg(R_UART_DLL, 0xD); // 1 500 000 + write_reg(R_UART_LCR, 0x3); // 8 bit data length + + write_reg(R_UART_FCR, 0<<0); // Disable fifo + r_uart_getc(); // flush input + write_reg(R_UART_FCR, 1<<0); // Enable fifo +} + +char r_uart_getc(void){ + char c = (char) read_reg(R_UART_RBR); + return c; +} + +uint32_t r_uart_fifo_rcv(void){ + return read_reg(R_UART_RFL); +} + +void r_uart_putc(char c){ + while(!(read_reg(R_UART_LSR) & 1<<5)) + ; + write_reg(R_UART_THR, c); +} + +void r_uart_puts(char *s){ + while(*s){ + r_uart_putc(*s++); + } +} diff --git a/src/ar100/serial.h b/src/ar100/serial.h new file mode 100644 index 000000000000..89eca29e792b --- /dev/null +++ b/src/ar100/serial.h @@ -0,0 +1,50 @@ +#include + +#define R_UART_BASE 0x01F02800 +#define R_UART_RBR R_UART_BASE + 0x00 // UART Receive Buffer Register +#define R_UART_THR R_UART_BASE + 0x00 // UART Transmit Holding Register +#define R_UART_DLL R_UART_BASE + 0x00 // UART Divisor Latch Low Register +#define R_UART_DLH R_UART_BASE + 0x04 // UART Divisor Latch High Register +#define R_UART_IER R_UART_BASE + 0x04 // UART Interrupt Enable Register +#define R_UART_IIR R_UART_BASE + 0x08 // UART Interrupt Identity Register +#define R_UART_FCR R_UART_BASE + 0x08 // UART FIFO Control Register +#define R_UART_LCR R_UART_BASE + 0x0C // UART Line Control Register +#define R_UART_MCR R_UART_BASE + 0x10 // UART Modem Control Register +#define R_UART_LSR R_UART_BASE + 0x14 // UART Line Status Register +#define R_UART_MSR R_UART_BASE + 0x18 // UART Modem Status Register +#define R_UART_SCH R_UART_BASE + 0x1C // UART Scratch Register +#define R_UART_USR R_UART_BASE + 0x7C // UART Status Register +#define R_UART_TFL R_UART_BASE + 0x80 // UART Transmit FIFO Level +#define R_UART_RFL R_UART_BASE + 0x84 // UART_RFL +#define R_UART_HLT R_UART_BASE + 0xA4 // UART Halt TX Register + +#define UART0_BASE 0x01C28000 +#define UART0_RBR UART0_BASE + 0x00 // UART Receive Buffer Register +#define UART0_THR UART0_BASE + 0x00 // UART Transmit Holding Register +#define UART0_DLL UART0_BASE + 0x00 // UART Divisor Latch Low Register +#define UART0_DLH UART0_BASE + 0x04 // UART Divisor Latch High Register +#define UART0_IER UART0_BASE + 0x04 // UART Interrupt Enable Register +#define UART0_IIR UART0_BASE + 0x08 // UART Interrupt Identity Register +#define UART0_FCR UART0_BASE + 0x08 // UART FIFO Control Register +#define UART0_LCR UART0_BASE + 0x0C // UART Line Control Register +#define UART0_MCR UART0_BASE + 0x10 // UART Modem Control Register +#define UART0_LSR UART0_BASE + 0x14 // UART Line Status Register +#define UART0_MSR UART0_BASE + 0x18 // UART Modem Status Register +#define UART0_SCH UART0_BASE + 0x1C // UART Scratch Register +#define UART0_USR UART0_BASE + 0x7C // UART Status Register +#define UART0_TFL UART0_BASE + 0x80 // UART Transmit FIFO Level +#define UART0_RFL UART0_BASE + 0x84 // UART_RFL +#define UART0_HLT UART0_BASE + 0xA4 // UART Halt TX Register + + +#define R_PRCM_BASE 0x01F01400 +#define APB0_CLK_GATING_REG R_PRCM_BASE + 0x0028 // APB0 Clock Gating Reg +#define APB0_SOFT_RST_REG R_PRCM_BASE + 0x00B0 // APB0 SW Reset Reg + +void r_uart_init(void); +void r_uart_putc(char c); +char r_uart_getc(void); +uint32_t r_uart_fifo_rcv(void); +void uart_putc(char c); +void uart_puts(char *s); +void uart_puti(uint32_t u); diff --git a/src/ar100/timer.c b/src/ar100/timer.c new file mode 100644 index 000000000000..140d9ed0db81 --- /dev/null +++ b/src/ar100/timer.c @@ -0,0 +1,52 @@ +// Timer functions for ar100 +// +// Copyright (C) 2020-2021 Elias Bakken +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "timer.h" +#include "board/timer_irq.h" +#include "board/misc.h" + +volatile static uint32_t timer_compare; +static uint8_t interrupt_seen; + +uint8_t timer_interrupt_pending(void){ + if(interrupt_seen){ + return 0; + } + if(timer_is_before(mfspr(SPR_TICK_TTCR_ADDR), timer_compare)){ + return 0; + } + + return 1; +} +void timer_clear_interrupt(void){ + interrupt_seen = 1; +} +// Set the next timer wake up time +void timer_set(uint32_t value){ + timer_compare = value; + interrupt_seen = 0; +} + +// Return the current time (in absolute clock ticks). +uint32_t timer_read_time(void){ + return mfspr(SPR_TICK_TTCR_ADDR); +} + +void timer_reset(void){ + mtspr(SPR_TICK_TTCR_ADDR, 0); +} + +// Activate timer dispatch as soon as possible +void timer_kick(void){ + timer_set(timer_read_time() + 50); +} + +void timer_init(void){ + interrupt_seen = 1; + mtspr(SPR_TICK_TTMR_ADDR, 3<<30); // continous + timer_kick(); +} +DECL_INIT(timer_init); diff --git a/src/ar100/timer.h b/src/ar100/timer.h new file mode 100644 index 000000000000..12e897524843 --- /dev/null +++ b/src/ar100/timer.h @@ -0,0 +1,12 @@ +#include +#include "asm/spr.h" +#include "sched.h" +#include "internal.h" + +uint8_t timer_interrupt_pending(void); +void timer_set(uint32_t value); +uint32_t timer_read_time(void); +void timer_reset(void); +void timer_clear_interrupt(void); +void timer_kick(void); +void timer_init(void); diff --git a/src/ar100/util.c b/src/ar100/util.c new file mode 100644 index 000000000000..7f2f9cf71dc9 --- /dev/null +++ b/src/ar100/util.c @@ -0,0 +1,34 @@ +// Helper functions for ar100 +// +// Copyright (C) 2020-2021 Elias Bakken +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "util.h" + +void *memcpy(void *restrict dest, const void *restrict src, size_t n){ + // Typecast src and dest addresses to (char *) + char *csrc = (char *)src; + char *cdest = (char *)dest; + + // Copy contents of src[] to dest[] + for (int i=0; i +#include + +void *memcpy(void *restrict dest, const void *restrict src, size_t n); +void *memset(void *restrict dest, int c, size_t n); + +inline void write_reg(uint32_t addr, uint32_t val){ + *((volatile unsigned long *)(addr)) = val; +} + +inline uint32_t read_reg(uint32_t addr){ + return *((volatile unsigned long *)(addr)); +} + +void set_bit(uint32_t addr, uint8_t bit); + +void clear_bit(uint32_t addr, uint8_t bit); diff --git a/src/atsam/Kconfig b/src/atsam/Kconfig index af3d067df8d0..aa802072ea33 100644 --- a/src/atsam/Kconfig +++ b/src/atsam/Kconfig @@ -14,6 +14,7 @@ config ATSAM_SELECT select HAVE_STRICT_TIMING select HAVE_CHIPID select HAVE_STEPPER_BOTH_EDGE + select HAVE_BOOTLOADER_REQUEST config BOARD_DIRECTORY string @@ -65,11 +66,6 @@ config CLOCK_FREQ default 120000000 if MACH_SAM4 default 300000000 if MACH_SAME70 -config FLASH_START - hex - default 0x400000 if MACH_SAM4 || MACH_SAME70 - default 0x80000 - config FLASH_SIZE hex default 0x80000 @@ -93,6 +89,11 @@ config STACK_SIZE int default 512 +config FLASH_APPLICATION_ADDRESS + hex + default 0x400000 if MACH_SAM4 || MACH_SAME70 + default 0x80000 + choice prompt "Communication interface" config ATSAM_USB diff --git a/src/atsamd/Kconfig b/src/atsamd/Kconfig index 6162f9b84ff3..05e4c50efac6 100644 --- a/src/atsamd/Kconfig +++ b/src/atsamd/Kconfig @@ -14,6 +14,7 @@ config ATSAMD_SELECT select HAVE_STRICT_TIMING select HAVE_CHIPID select HAVE_STEPPER_BOTH_EDGE + select HAVE_BOOTLOADER_REQUEST config HAVE_SERCOM depends on HAVE_GPIO_I2C || HAVE_GPIO_SPI @@ -110,6 +111,32 @@ config STACK_SIZE int default 512 + +###################################################################### +# Bootloader +###################################################################### + +choice + prompt "Bootloader offset" + config SAMD_FLASH_START_2000 + depends on MACH_SAMD21 + bool "8KiB bootloader (Arduino Zero)" + config SAMD_FLASH_START_4000 + bool "16KiB bootloader (Arduino M0)" + config SAMD_FLASH_START_0000 + bool "No bootloader" +endchoice +config FLASH_APPLICATION_ADDRESS + hex + default 0x4000 if SAMD_FLASH_START_4000 + default 0x2000 if SAMD_FLASH_START_2000 + default 0x0000 + + +###################################################################### +# Clock +###################################################################### + choice prompt "Clock Reference" config CLOCK_REF_X32K @@ -141,22 +168,10 @@ config CLOCK_FREQ default 200000000 if SAMD51_FREQ_200 default 120000000 if MACH_SAMX5 -choice - prompt "Bootloader offset" - config FLASH_START_2000 - depends on MACH_SAMD21 - bool "8KiB bootloader (Arduino Zero)" - config FLASH_START_4000 - bool "16KiB bootloader (Arduino M0)" - config FLASH_START_0000 - bool "No bootloader" -endchoice -config FLASH_START - hex - default 0x4000 if FLASH_START_4000 - default 0x2000 if FLASH_START_2000 - default 0x0000 +###################################################################### +# Communication inteface +###################################################################### choice prompt "Communication interface" diff --git a/src/atsamd/fdcan.c b/src/atsamd/fdcan.c index c12d91db87f8..758cb4f2a71b 100644 --- a/src/atsamd/fdcan.c +++ b/src/atsamd/fdcan.c @@ -85,7 +85,7 @@ static struct fdcan_msg_ram MSG_RAM; // Transmit a packet int -canbus_send(struct canbus_msg *msg) +canhw_send(struct canbus_msg *msg) { uint32_t txfqs = CANx->TXFQS.reg; if (txfqs & CAN_TXFQS_TFQF) @@ -120,7 +120,7 @@ can_filter(uint32_t index, uint32_t id) // Setup the receive packet filter void -canbus_set_filter(uint32_t id) +canhw_set_filter(uint32_t id) { if (!CONFIG_CANBUS_FILTER) return; @@ -283,7 +283,7 @@ can_init(void) CANx->CCCR.reg &= ~CAN_CCCR_INIT; /*##-2- Configure the CAN Filter #######################################*/ - canbus_set_filter(0); + canhw_set_filter(0); /*##-3- Configure Interrupts #################################*/ armcm_enable_irq(CAN_IRQHandler, CANx_IRQn, 1); diff --git a/src/atsamd/main.c b/src/atsamd/main.c index 37b6cc8b2fe0..96af22a0ade4 100644 --- a/src/atsamd/main.c +++ b/src/atsamd/main.c @@ -14,7 +14,7 @@ void bootloader_request(void) { - if (!CONFIG_FLASH_START) + if (!CONFIG_FLASH_APPLICATION_ADDRESS) return; // Bootloader hack irq_disable(); diff --git a/src/avr/i2c.c b/src/avr/i2c.c index 370582cc7ab7..658a30a12187 100644 --- a/src/avr/i2c.c +++ b/src/avr/i2c.c @@ -27,31 +27,27 @@ static const uint8_t SCL = GPIO('D', 0), SDA = GPIO('D', 1); DECL_CONSTANT_STR("BUS_PINS_twi", "PD0,PD1"); #endif -static void -i2c_init(void) -{ - if (TWCR & (1<= 400000) + TWBR = ((CONFIG_CLOCK_FREQ / 400000) - 16) / 2; + else + TWBR = ((CONFIG_CLOCK_FREQ / 100000) - 16) / 2; + + // Enable interface + TWCR = (1< // USB_COM_vect #include // NULL #include "autoconf.h" // CONFIG_MACH_at90usb1286 -#include "board/misc.h" // bootloader_request #include "board/usb_cdc.h" // usb_notify_ep0 #include "board/usb_cdc_ep.h" // USB_CDC_EP_BULK_IN #include "pgm.h" // READP @@ -179,11 +178,6 @@ usb_set_configure(void) UEIENX = 1<= 7 + SCB_CleanDCache_by_Addr((void*)req_sig, sizeof(*req_sig)); +#endif + NVIC_SystemReset(); } void diff --git a/src/generic/canbus.c b/src/generic/canbus.c index 941ccd00b7e8..1be0ead506a8 100644 --- a/src/generic/canbus.c +++ b/src/generic/canbus.c @@ -5,22 +5,22 @@ // This file may be distributed under the terms of the GNU GPLv3 license. #include "autoconf.h" // CONFIG_CANBUS_FREQUENCY -#include "canbus.h" // canbus_send -#include "canserial.h" // canserial_send +#include "canbus.h" // canhw_send +#include "canserial.h" // canserial_notify_tx #include "command.h" // DECL_CONSTANT DECL_CONSTANT("CANBUS_FREQUENCY", CONFIG_CANBUS_FREQUENCY); int -canserial_send(struct canbus_msg *msg) +canbus_send(struct canbus_msg *msg) { - return canbus_send(msg); + return canhw_send(msg); } void -canserial_set_filter(uint32_t id) +canbus_set_filter(uint32_t id) { - canbus_set_filter(id); + canhw_set_filter(id); } void diff --git a/src/generic/canbus.h b/src/generic/canbus.h index 8032611a2e07..f21a7cc4561d 100644 --- a/src/generic/canbus.h +++ b/src/generic/canbus.h @@ -18,10 +18,12 @@ struct canbus_msg { #define CANMSG_DATA_LEN(msg) ((msg)->dlc > 8 ? 8 : (msg)->dlc) // callbacks provided by board specific code -int canbus_send(struct canbus_msg *msg); -void canbus_set_filter(uint32_t id); +int canhw_send(struct canbus_msg *msg); +void canhw_set_filter(uint32_t id); // canbus.c +int canbus_send(struct canbus_msg *msg); +void canbus_set_filter(uint32_t id); void canbus_notify_tx(void); void canbus_process_data(struct canbus_msg *msg); diff --git a/src/generic/canserial.c b/src/generic/canserial.c index 8062cfe37c39..d56235f57fe7 100644 --- a/src/generic/canserial.c +++ b/src/generic/canserial.c @@ -7,10 +7,11 @@ // This file may be distributed under the terms of the GNU GPLv3 license. #include // memcpy +#include "autoconf.h" // CONFIG_HAVE_BOOTLOADER_REQUEST #include "board/io.h" // readb #include "board/irq.h" // irq_save #include "board/misc.h" // console_sendf -#include "canbus.h" // canbus_set_uuid +#include "canbus.h" // canbus_send #include "canserial.h" // canserial_notify_tx #include "command.h" // DECL_CONSTANT #include "fasthash.h" // fasthash64 @@ -68,7 +69,7 @@ canserial_tx_task(void) break; msg.dlc = now; memcpy(msg.data, &CanData.transmit_buf[tpos], now); - int ret = canserial_send(&msg); + int ret = canbus_send(&msg); if (ret <= 0) break; tpos += now; @@ -152,7 +153,7 @@ can_process_query_unassigned(struct canbus_msg *msg) send.data[7] = CANBUS_CMD_SET_KLIPPER_NODEID; // Send with retry for (;;) { - int ret = canserial_send(&send); + int ret = canbus_send(&send); if (ret >= 0) return; } @@ -162,7 +163,7 @@ static void can_id_conflict(void) { CanData.assigned_id = 0; - canserial_set_filter(CanData.assigned_id); + canbus_set_filter(CanData.assigned_id); shutdown("Another CAN node assigned this ID"); } @@ -175,7 +176,7 @@ can_process_set_klipper_nodeid(struct canbus_msg *msg) if (can_check_uuid(msg)) { if (newid != CanData.assigned_id) { CanData.assigned_id = newid; - canserial_set_filter(CanData.assigned_id); + canbus_set_filter(CanData.assigned_id); } } else if (newid == CanData.assigned_id) { can_id_conflict(); @@ -185,7 +186,7 @@ can_process_set_klipper_nodeid(struct canbus_msg *msg) static void can_process_request_bootloader(struct canbus_msg *msg) { - if (!can_check_uuid(msg)) + if (!CONFIG_HAVE_BOOTLOADER_REQUEST || !can_check_uuid(msg)) return; bootloader_request(); } @@ -223,7 +224,7 @@ canserial_notify_rx(void) DECL_CONSTANT("RECEIVE_WINDOW", ARRAY_SIZE(CanData.receive_buf)); // Handle incoming data (called from IRQ handler) -int +void canserial_process_data(struct canbus_msg *msg) { uint32_t id = msg->id; @@ -232,7 +233,7 @@ canserial_process_data(struct canbus_msg *msg) int rpos = CanData.receive_pos; uint32_t len = CANMSG_DATA_LEN(msg); if (len > sizeof(CanData.receive_buf) - rpos) - return -1; + return; memcpy(&CanData.receive_buf[rpos], msg->data, len); CanData.receive_pos = rpos + len; canserial_notify_rx(); @@ -242,13 +243,12 @@ canserial_process_data(struct canbus_msg *msg) uint32_t pushp = CanData.admin_push_pos; if (pushp >= CanData.admin_pull_pos + ARRAY_SIZE(CanData.admin_queue)) // No space - drop message - return -1; + return; uint32_t pos = pushp % ARRAY_SIZE(CanData.admin_queue); memcpy(&CanData.admin_queue[pos], msg, sizeof(*msg)); CanData.admin_push_pos = pushp + 1; canserial_notify_rx(); } - return 0; } // Remove from the receive buffer the given number of bytes diff --git a/src/generic/canserial.h b/src/generic/canserial.h index e2f555212d57..3dd5cd9deae4 100644 --- a/src/generic/canserial.h +++ b/src/generic/canserial.h @@ -6,14 +6,10 @@ #define CANBUS_ID_ADMIN 0x3f0 #define CANBUS_ID_ADMIN_RESP 0x3f1 -// callbacks provided by board specific code -struct canbus_msg; -int canserial_send(struct canbus_msg *msg); -void canserial_set_filter(uint32_t id); - // canserial.c void canserial_notify_tx(void); -int canserial_process_data(struct canbus_msg *msg); +struct canbus_msg; +void canserial_process_data(struct canbus_msg *msg); void canserial_set_uuid(uint8_t *raw_uuid, uint32_t raw_uuid_len); #endif // canserial.h diff --git a/src/generic/serial_irq.c b/src/generic/serial_irq.c index 434a98bbe007..98910735add3 100644 --- a/src/generic/serial_irq.c +++ b/src/generic/serial_irq.c @@ -79,7 +79,7 @@ console_task(void) if (ret > 0) command_dispatch(receive_buf, pop_count); if (ret) { - if (CONFIG_SERIAL_BOOTLOADER_SIDECHANNEL && ret < 0 && pop_count == 32 + if (CONFIG_HAVE_BOOTLOADER_REQUEST && ret < 0 && pop_count == 32 && !memcmp(receive_buf, " \x1c Request Serial Bootloader!! ~", 32)) bootloader_request(); console_pop_input(pop_count); diff --git a/src/generic/usb_canbus.c b/src/generic/usb_canbus.c index 1a4ac869364b..d776d45f248a 100644 --- a/src/generic/usb_canbus.c +++ b/src/generic/usb_canbus.c @@ -112,12 +112,12 @@ static struct usbcan_data { uint8_t host_status; // Canbus data routed locally - uint8_t notify_local; + uint8_t notify_local, usb_send_busy; uint32_t assigned_id; // Data from physical canbus interface uint32_t pull_pos, push_pos; - struct canbus_msg queue[8]; + struct canbus_msg queue[32]; } UsbCan; enum { @@ -166,21 +166,25 @@ send_frame(struct canbus_msg *msg) } // Send any pending hw frames to host -static int +static void drain_hw_queue(void) { + uint32_t pull_pos = UsbCan.pull_pos; for (;;) { uint32_t push_pos = readl(&UsbCan.push_pos); - uint32_t pull_pos = UsbCan.pull_pos; - if (push_pos != pull_pos) { - uint32_t pos = pull_pos % ARRAY_SIZE(UsbCan.queue); - int ret = send_frame(&UsbCan.queue[pos]); - if (ret < 0) - return -1; - UsbCan.pull_pos = pull_pos + 1; - continue; + if (push_pos == pull_pos) { + // No more data to send + UsbCan.usb_send_busy = 0; + return; + } + uint32_t pos = pull_pos % ARRAY_SIZE(UsbCan.queue); + int ret = send_frame(&UsbCan.queue[pos]); + if (ret < 0) { + // USB is busy - retry later + UsbCan.usb_send_busy = 1; + return; } - return 0; + UsbCan.pull_pos = pull_pos = pull_pos + 1; } } @@ -189,12 +193,11 @@ usbcan_task(void) { if (!sched_check_wake(&UsbCan.wake)) return; - for (;;) { - // Send any pending hw frames to host - int ret = drain_hw_queue(); - if (ret < 0) - return; + // Send any pending hw frames to host + drain_hw_queue(); + + for (;;) { // See if previous host frame needs to be transmitted uint_fast8_t host_status = UsbCan.host_status; if (host_status & (HS_TX_HW | HS_TX_LOCAL)) { @@ -204,62 +207,55 @@ usbcan_task(void) msg.dlc = gs->can_dlc; msg.data32[0] = gs->data32[0]; msg.data32[1] = gs->data32[1]; + if (host_status & HS_TX_LOCAL) { + canserial_process_data(&msg); + UsbCan.host_status = host_status = host_status & ~HS_TX_LOCAL; + } if (host_status & HS_TX_HW) { - ret = canbus_send(&msg); + int ret = canhw_send(&msg); if (ret < 0) - return; + break; UsbCan.host_status = host_status = host_status & ~HS_TX_HW; } - if (host_status & HS_TX_LOCAL) { - ret = canserial_process_data(&msg); - if (ret < 0) { - usb_notify_bulk_out(); - return; - } - UsbCan.host_status = host_status & ~HS_TX_LOCAL; - } - continue; } // Send any previous echo frames if (host_status) { - ret = usb_send_bulk_in(&UsbCan.host_frame - , sizeof(UsbCan.host_frame)); + if (UsbCan.usb_send_busy) + // Don't send echo frame until other traffic is sent + return; + int ret = usb_send_bulk_in(&UsbCan.host_frame + , sizeof(UsbCan.host_frame)); if (ret < 0) return; UsbCan.host_status = 0; - continue; } - // See if can read a new frame from host - ret = usb_read_bulk_out(&UsbCan.host_frame, USB_CDC_EP_BULK_OUT_SIZE); - if (ret > 0) { - uint32_t id = UsbCan.host_frame.can_id; - UsbCan.host_status = HS_TX_ECHO | HS_TX_HW; - if (id == CANBUS_ID_ADMIN) - UsbCan.host_status = HS_TX_ECHO | HS_TX_HW | HS_TX_LOCAL; - else if (UsbCan.assigned_id && UsbCan.assigned_id == id) - UsbCan.host_status = HS_TX_ECHO | HS_TX_LOCAL; - continue; - } - - // No more work to be done - if (UsbCan.notify_local) { - UsbCan.notify_local = 0; - canserial_notify_tx(); - } - return; + // Read next frame from host + int ret = usb_read_bulk_out(&UsbCan.host_frame + , USB_CDC_EP_BULK_OUT_SIZE); + if (ret <= 0) + // No frame available - no more work to be done + break; + uint32_t id = UsbCan.host_frame.can_id; + UsbCan.host_status = HS_TX_ECHO | HS_TX_HW; + if (id == CANBUS_ID_ADMIN) + UsbCan.host_status = HS_TX_ECHO | HS_TX_HW | HS_TX_LOCAL; + else if (UsbCan.assigned_id && UsbCan.assigned_id == id) + UsbCan.host_status = HS_TX_ECHO | HS_TX_LOCAL; } + + if (UsbCan.notify_local && !UsbCan.usb_send_busy) + canserial_notify_tx(); } DECL_TASK(usbcan_task); int -canserial_send(struct canbus_msg *msg) +canbus_send(struct canbus_msg *msg) { - int ret = drain_hw_queue(); - if (ret < 0) + if (UsbCan.usb_send_busy) goto retry_later; - ret = send_frame(msg); + int ret = send_frame(msg); if (ret < 0) goto retry_later; UsbCan.notify_local = 0; @@ -270,7 +266,7 @@ canserial_send(struct canbus_msg *msg) } void -canserial_set_filter(uint32_t id) +canbus_set_filter(uint32_t id) { UsbCan.assigned_id = id; } diff --git a/src/generic/usb_cdc.c b/src/generic/usb_cdc.c index 40ff74ba62fc..143c213f0620 100644 --- a/src/generic/usb_cdc.c +++ b/src/generic/usb_cdc.c @@ -446,6 +446,8 @@ static uint8_t line_control_state; static void check_reboot(void) { + if (!CONFIG_HAVE_BOOTLOADER_REQUEST) + return; if (line_coding.dwDTERate == 1200 && !(line_control_state & 0x01)) // A baud of 1200 is an Arduino style request to enter the bootloader bootloader_request(); diff --git a/src/hc32f460/Kconfig b/src/hc32f460/Kconfig new file mode 100644 index 000000000000..d39bdf82a975 --- /dev/null +++ b/src/hc32f460/Kconfig @@ -0,0 +1,79 @@ +# Kconfig settings for Huada HC32F460 processor + +if MACH_HC32F460 + +config HC32F460_SELECT + bool + default y + select HAVE_GPIO + select HAVE_GPIO_ADC + select HAVE_GPIO_BITBANGING + select HAVE_STRICT_TIMING + select HAVE_GPIO_HARD_PWM + select HAVE_STEPPER_BOTH_EDGE + +config BOARD_DIRECTORY + string + default "hc32f460" + + +###################################################################### +# Communication interface +###################################################################### + +choice + prompt "Communication interface" + config HC32F460_SERIAL_PA7_PA8 + bool "Serial (PA7 & PA8) - Creality Ender 2 PRO" + select SERIAL + config HC32F460_SERIAL_PA3_PA2 + bool "Serial (PA3 & PA2) - Anycube" + select SERIAL + config HC32F460_SERIAL_PA15_PA9 + bool "Serial (PA15 & PA09) - Voxelab" + select SERIAL + config HC32F460_SERIAL_PC0_PC1 + bool "Serial (PC0 & PC1) - on LCD connector" + select SERIAL +endchoice + + +###################################################################### +# Bootloader +# bootloader moves code and then VTOR.RESET points here: +###################################################################### +config FLASH_SIZE + hex + default 0x40000 + +config FLASH_APPLICATION_ADDRESS + default 0x8000 # Aquila is 0xC000 + +config FLASH_BOOT_ADDRESS + hex + default 0x0 + +config RAM_SIZE + hex + default 0x8000 + +# use the fast RAM in the HC32F460 +config RAM_START + hex + default 0x1fff8000 + +config STACK_SIZE + int + default 1024 + + +config CLOCK_FREQ + int + default 200000000 # Voxelab uses 168000000 + + +config MCU + string + default "HC32F460" + +endif diff --git a/src/hc32f460/Makefile b/src/hc32f460/Makefile new file mode 100644 index 000000000000..c44267369362 --- /dev/null +++ b/src/hc32f460/Makefile @@ -0,0 +1,37 @@ +# hc32f460 build rules + +# Setup the toolchain +CROSS_PREFIX=arm-none-eabi- + +dirs-y += src/hc32f460 src/generic lib/hc32f460/driver/src lib/hc32f460/mcu/common + +CFLAGS += -mthumb -mcpu=cortex-m4 -Isrc/hc32f460 -Ilib/hc32f460/driver/inc -Ilib/hc32f460/mcu/common -Ilib/cmsis-core -DHC32F460 + +CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs +CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld +$(OUT)klipper.elf: $(OUT)src/generic/armcm_link.ld + +# Add source files +src-y += hc32f460/main.c +src-y += hc32f460/interrupts.c +src-y += hc32f460/gpio.c +src-y += ../lib/hc32f460/mcu/common/system_hc32f460.c +src-y += ../lib/hc32f460/driver/src/hc32f460_clk.c +src-y += ../lib/hc32f460/driver/src/hc32f460_efm.c +src-y += ../lib/hc32f460/driver/src/hc32f460_sram.c +src-y += ../lib/hc32f460/driver/src/hc32f460_utility.c +src-y += ../lib/hc32f460/driver/src/hc32f460_gpio.c +src-y += ../lib/hc32f460/driver/src/hc32f460_pwc.c +src-$(CONFIG_HAVE_GPIO_ADC) += hc32f460/adc.c ../lib/hc32f460/driver/src/hc32f460_adc.c +src-$(CONFIG_SERIAL) += hc32f460/serial.c generic/serial_irq.c ../lib/hc32f460/driver/src/hc32f460_usart.c +src-$(CONFIG_HAVE_GPIO_HARD_PWM) += hc32f460/hard_pwm.c ../lib/hc32f460/driver/src/hc32f460_timera.c +src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_timer.c +src-y += generic/armcm_reset.c generic/crc16_ccitt.c + + +# Build the additional bin output file +target-y += $(OUT)klipper.bin + +$(OUT)klipper.bin: $(OUT)klipper.elf + @echo " Creating bin file $@" + $(Q)$(OBJCOPY) -O binary $< $@ diff --git a/src/hc32f460/adc.c b/src/hc32f460/adc.c new file mode 100644 index 000000000000..ef1e58fb2a94 --- /dev/null +++ b/src/hc32f460/adc.c @@ -0,0 +1,155 @@ +// ADC functions on Huada HC32F460 +// +// Copyright (C) 2022 Steven Gotthardt +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "generic/misc.h" // timer_from_us +#include "command.h" // shutdown +#include "board/gpio.h" // gpio_adc_setup +#include "board/internal.h" // GPIO +#include "sched.h" // sched_shutdown + +// library +#include "hc32f460_adc.h" +#include "hc32f460_pwc.h" +#include "hc32f460_gpio.h" + +#define ADC_RESOLUTION_12BIT (12u) +#define ADC_RESOLUTION_10BIT (10u) +#define ADC_RESOLUTION_8BIT (8u) + +#define ADC1_RESOLUTION (ADC_RESOLUTION_12BIT) +#define ADC1_PRECISION (1ul << ADC1_RESOLUTION) + +#if ADC1_RESOLUTION == ADC_RESOLUTION_12BIT +#define AdcResolution AdcResolution_12Bit +#elif ADC1_RESOLUTION == ADC_RESOLUTION_10BIT +#define AdcResolution AdcResolution_10Bit +#else +#define AdcResolution AdcResolution_8Bit +#endif + + +/* Timeout value definitions. Found in example code */ +#define TIMEOUT_VAL (30u) + +DECL_CONSTANT("ADC_MAX", ADC1_PRECISION-1); + +// These pins can be used for ADC +static const uint8_t adc_gpio[] = { + GPIO('A', 0), // Chan 0 + GPIO('A', 1), // Chan 1 + GPIO('A', 2), // Chan 2 + GPIO('A', 3), // Chan 3 + GPIO('A', 4), // Chan 4 + GPIO('A', 5), // Chan 5 + GPIO('A', 6), // Chan 6 + GPIO('A', 7), // Chan 7 + GPIO('B', 0), // Chan 8 + GPIO('B', 1), // Chan 9 + GPIO('C', 0), // Chan 10 // TBed on TriGorilla + GPIO('C', 1), // Chan 11 // THead on TriGorilla + GPIO('C', 2), // Chan 12 + GPIO('C', 3), // Chan 13 + GPIO('C', 4), // Chan 14 // TBed on aquilla + GPIO('C', 5), // Chan 15 // THead on aquilla +}; + + +struct gpio_adc +gpio_adc_setup(uint32_t gpio) +{ + // validate pin in adc_pins table + int chan; + for (chan=0; ; chan++) + { + if (chan >= ARRAY_SIZE(adc_gpio)) + { + shutdown("Not a valid ADC pin"); + } + if (adc_gpio[chan] == gpio) + { + break; + } + } + + // set as analog + gpio_peripheral(gpio, Pin_Mode_Ana, 0); + + uint8_t sampleTime[ARRAY_SIZE(adc_gpio)] = { TIMEOUT_VAL }; // all chans + stc_adc_ch_cfg_t stcAdcChan; + stcAdcChan.u32Channel = 1 << chan; + stcAdcChan.u8Sequence = ADC_SEQ_A; // all conversions are in SEQ A + stcAdcChan.pu8SampTime = sampleTime; + ADC_AddAdcChannel(M4_ADC1, &stcAdcChan); + + return (struct gpio_adc){ .chan = chan }; +} + + +// Try to sample a value. Returns zero if sample ready, otherwise +// returns the number of clock ticks the caller should wait before +// retrying this function. +uint32_t +gpio_adc_sample(struct gpio_adc g) +{ + // true if the sequence is finished + if (ADC_GetEocFlag(M4_ADC1, ADC_SEQ_A)) + { + // all conversions are done - clear the flag + ADC_ClrEocFlag(M4_ADC1, ADC_SEQ_A); + return 0; + } + else if (M4_ADC1->STR & 1) + { + // running but not done yet + return timer_from_us(TIMEOUT_VAL/2); + } + else + { + // not running - so start + ADC_StartConvert(M4_ADC1); + } + + return timer_from_us(TIMEOUT_VAL); +} + + +// Read a value; use only after gpio_adc_sample() returns zero +uint16_t +gpio_adc_read(struct gpio_adc g) +{ + // return the one we want... + return ADC_GetValue(M4_ADC1, g.chan); +} + + +// Cancel a sample that may have been started with gpio_adc_sample() +void +gpio_adc_cancel_sample(struct gpio_adc g) +{ + ADC_StopConvert(M4_ADC1); +} + + +// The clocks are already set by the loader. +// There is ADC1 and ADC2. Sequences do all channels at once. +void +adc_init(void) +{ + // PCLK2 (ADC clock) is 'divide by 4', Max ADC clock is 60MHz + stc_adc_init_t stcAdcInit = {0}; + stcAdcInit.enResolution = AdcResolution; // see define above + stcAdcInit.enDataAlign = AdcDataAlign_Right; + stcAdcInit.enAutoClear = AdcClren_Disable; + stcAdcInit.enScanMode = AdcMode_SAOnce; + + // power-on ADC + PWC_Fcg3PeriphClockCmd(PWC_FCG3_PERIPH_ADC1, Enable); + + // only using ADC1 + ADC_Init(M4_ADC1, &stcAdcInit); +} + +DECL_INIT(adc_init); diff --git a/src/hc32f460/gpio.c b/src/hc32f460/gpio.c new file mode 100644 index 000000000000..e3b98df443f2 --- /dev/null +++ b/src/hc32f460/gpio.c @@ -0,0 +1,153 @@ +// GPIO functions on HC32F460 +// +// Copyright (C) 2022 Steven Gotthardt +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include // ffs +#include "board/irq.h" // irq_save +#include "command.h" // DECL_ENUMERATION_RANGE +#include "board/gpio.h" // gpio_out_setup +#include "internal.h" +#include "sched.h" // sched_shutdown + +#include "hc32f460_gpio.h" + + +// 64pin package +DECL_ENUMERATION_RANGE("pin", "PA0", GPIO('A', 0), 16); +DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 16); +DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 16); +DECL_ENUMERATION_RANGE("pin", "PD2", GPIO('D', 2), 1); +DECL_ENUMERATION_RANGE("pin", "PH2", PortH * 16 + 2, 1); // H: special case + + +// HC32F460 ports are in one M4_PORT - offset by 0x10 +// eg toggle: M4_PORT->POTRA + 0x10 => M4_PORT->POTRB +// 'gpio' is port (0-4) * 16 + pinPosition (0-15) +#define POTR_OFFSET offsetof(M4_PORT_TypeDef, POTRA) // output flip +#define PODR_OFFSET offsetof(M4_PORT_TypeDef, PODRA) // output data +#define PIDR_OFFSET offsetof(M4_PORT_TypeDef, PIDRA) // input data +#define POSR_OFFSET offsetof(M4_PORT_TypeDef, POSRA) // output set +#define PORR_OFFSET offsetof(M4_PORT_TypeDef, PORRA) // output reset +#define PORT_OFFSET offsetof(M4_PORT_TypeDef, PIDRB) // space between PORTS + + + +void +gpio_peripheral(uint32_t gpio, int func, int pull_up) +{ + stc_port_init_t stcPortInit; + + irqstatus_t flag = irq_save(); + + stcPortInit.enPinMode = func; + stcPortInit.enLatch = Disable; + stcPortInit.enExInt = Disable; + stcPortInit.enInvert = Disable; + stcPortInit.enPullUp = pull_up ? Enable : Disable; + stcPortInit.enPinDrv = Pin_Drv_L; + stcPortInit.enPinOType = Pin_OType_Cmos; + stcPortInit.enPinSubFunc = Disable; + + // make the port GPIO and disable the sub functionality + PORT_SetFunc(GPIO2PORT(gpio), GPIO2BIT(gpio), Func_Gpio, Disable); + PORT_Init(GPIO2PORT(gpio), GPIO2BIT(gpio), &stcPortInit); + + irq_restore(flag); +} + + +struct gpio_out +gpio_out_setup(uint32_t gpio, uint32_t val) +{ + uint32_t port = (uint32_t)M4_PORT + GPIO2PORT(gpio) * PORT_OFFSET; + struct gpio_out g = + { .gpio = gpio, .portAddress = port, .bitMask = GPIO2BIT(gpio) }; + gpio_out_reset(g, val); + + return g; +} + + +void +gpio_out_reset(struct gpio_out g, uint32_t val) +{ + irqstatus_t flag = irq_save(); + if (val) + { + uint16_t *POSRx = (uint16_t *)(g.portAddress + POSR_OFFSET); + *POSRx = g.bitMask; + } + else + { + uint16_t *PORRx = (uint16_t *)(g.portAddress + PORR_OFFSET); + *PORRx = g.bitMask; + } + + gpio_peripheral(g.gpio, Pin_Mode_Out, 0); + irq_restore(flag); +} + + +void +gpio_out_toggle_noirq(struct gpio_out g) +{ + uint16_t *POTRx = (uint16_t *)(g.portAddress + POTR_OFFSET); + *POTRx = g.bitMask; +} + + +void +gpio_out_toggle(struct gpio_out g) +{ + irqstatus_t flag = irq_save(); + gpio_out_toggle_noirq(g); + irq_restore(flag); +} + + +void +gpio_out_write(struct gpio_out g, uint32_t val) +{ + if (val) + { + uint16_t *POSRx = (uint16_t *)(g.portAddress + POSR_OFFSET); + *POSRx = g.bitMask; + } + else + { + uint16_t *PORRx = (uint16_t *)(g.portAddress + PORR_OFFSET); + *PORRx = g.bitMask; + } +} + + +struct gpio_in +gpio_in_setup(uint32_t gpio, int32_t pull_up) +{ + uint32_t port = (uint32_t)M4_PORT + GPIO2PORT(gpio) * PORT_OFFSET; + + struct gpio_in g = + { .gpio = gpio, .portAddress = port, .bitMask = GPIO2BIT(gpio) }; + gpio_in_reset(g, pull_up); + + return g; +} + + +void +gpio_in_reset(struct gpio_in g, int32_t pull_up) +{ + irqstatus_t flag = irq_save(); + gpio_peripheral(g.gpio, Pin_Mode_In, pull_up); + irq_restore(flag); +} + + +uint8_t +gpio_in_read(struct gpio_in g) +{ + uint16_t *PIDRx = (uint16_t *)(g.portAddress + PIDR_OFFSET); + return !!(*PIDRx & g.bitMask); +} diff --git a/src/hc32f460/gpio.h b/src/hc32f460/gpio.h new file mode 100644 index 000000000000..5e88a234c8f1 --- /dev/null +++ b/src/hc32f460/gpio.h @@ -0,0 +1,62 @@ +#ifndef __HC32F460_GPIO_H +#define __HC32F460_GPIO_H + +#include // uint32_t + + +struct gpio_out { + uint32_t portAddress; // M4_PORT or offset + uint16_t gpio; // the mangled pin+port + uint16_t bitMask; // the pin shifted to use in register +}; +struct gpio_out gpio_out_setup(uint32_t gpio, uint32_t val); +void gpio_out_reset(struct gpio_out g, uint32_t val); +void gpio_out_toggle_noirq(struct gpio_out g); +void gpio_out_toggle(struct gpio_out g); +void gpio_out_write(struct gpio_out g, uint32_t val); + +struct gpio_in { + uint32_t portAddress; + uint16_t gpio; + uint16_t bitMask; +}; +struct gpio_in gpio_in_setup(uint32_t gpio, int32_t pull_up); +void gpio_in_reset(struct gpio_in g, int32_t pull_up); +uint8_t gpio_in_read(struct gpio_in g); + +struct gpio_pwm { + void *timer; + uint32_t chan; +}; +struct gpio_pwm gpio_pwm_setup(uint8_t gpio, uint32_t cycle_time, uint8_t val); +void gpio_pwm_write(struct gpio_pwm g, uint32_t val); + +// all ADC operations will be on ADC1 +struct gpio_adc { + uint32_t chan; +}; +struct gpio_adc gpio_adc_setup(uint32_t gpio); +uint32_t gpio_adc_sample(struct gpio_adc g); +uint16_t gpio_adc_read(struct gpio_adc g); +void gpio_adc_cancel_sample(struct gpio_adc g); + +struct spi_config { + void *spi; + uint32_t spi_cr1; +}; +struct spi_config spi_setup(uint32_t bus, uint8_t mode, uint32_t rate); +void spi_prepare(struct spi_config config); +void spi_transfer(struct spi_config config, uint8_t receive_data + , uint8_t len, uint8_t *data); + +struct i2c_config { + void *i2c; + uint8_t addr; +}; + +struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); +void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); + +#endif // gpio.h diff --git a/src/hc32f460/hard_pwm.c b/src/hc32f460/hard_pwm.c new file mode 100644 index 000000000000..9d3387e604d6 --- /dev/null +++ b/src/hc32f460/hard_pwm.c @@ -0,0 +1,164 @@ +// Hardware PWM support on HC32F460 +// +// Copyright (C) 2022 Steven Gotthardt +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" +#include "board/irq.h" // irq_save +#include "command.h" // shutdown +#include "board/gpio.h" // gpio_pwm_write +#include "internal.h" // GPIO +#include "sched.h" // sched_shutdown + +// library +#include "hc32f460_timera.h" +#include "hc32f460_pwc.h" +#include "hc32f460_gpio.h" + + +#define MAX_PWM ((1 << 16) - 1) +DECL_CONSTANT("PWM_MAX", MAX_PWM); + +// timer A (general purpose) has 6 units and each has 8 PWM +// M4_TMRA_TypeDef* timer; + +struct gpio_pwm_info { + uint8_t gpio; + uint8_t unit; // 6 units in Timer A + en_timera_channel_t chan; +}; + +// Timer A (general purpose) is only timer used +// These are for pin function 4 only +// Some PWM come out on more than 1 pin +// 64pin package +static const struct gpio_pwm_info pwm_mapping[] = { + {GPIO('A', 0), 2, TimeraCh1}, + {GPIO('A', 1), 2, TimeraCh2}, + {GPIO('A', 2), 2, TimeraCh3}, + {GPIO('A', 3), 2, TimeraCh4}, + {GPIO('A', 5), 2, TimeraCh1}, + {GPIO('A', 8), 1, TimeraCh1}, + {GPIO('A', 9), 1, TimeraCh2}, + {GPIO('A',10), 1, TimeraCh3}, + {GPIO('A',11), 1, TimeraCh4}, + {GPIO('A',13), 2, TimeraCh5}, + {GPIO('A',14), 2, TimeraCh6}, + {GPIO('A',15), 2, TimeraCh1}, + {GPIO('B', 0), 1, TimeraCh6}, + {GPIO('B', 1), 1, TimeraCh7}, + {GPIO('B', 2), 1, TimeraCh8}, + {GPIO('B', 3), 2, TimeraCh2}, + {GPIO('B', 4), 3, TimeraCh1}, + {GPIO('B', 5), 3, TimeraCh2}, + {GPIO('B', 6), 4, TimeraCh1}, + {GPIO('B', 7), 4, TimeraCh2}, + {GPIO('B', 8), 4, TimeraCh3}, + {GPIO('B', 9), 4, TimeraCh4}, + {GPIO('B',10), 2, TimeraCh3}, + {GPIO('B',12), 1, TimeraCh8}, + {GPIO('B',13), 1, TimeraCh5}, + {GPIO('B',14), 1, TimeraCh6}, + {GPIO('B',15), 1, TimeraCh7}, + {GPIO('C', 0), 2, TimeraCh5}, + {GPIO('C', 1), 2, TimeraCh6}, + {GPIO('C', 2), 2, TimeraCh7}, + {GPIO('C', 3), 2, TimeraCh8}, + {GPIO('C', 6), 3, TimeraCh1}, + {GPIO('C', 7), 3, TimeraCh2}, + {GPIO('C', 8), 3, TimeraCh3}, + {GPIO('C', 9), 3, TimeraCh4}, + {GPIO('C',10), 2, TimeraCh7}, + {GPIO('C',11), 2, TimeraCh8}, + {GPIO('C',13), 4, TimeraCh8}, + {GPIO('C',14), 4, TimeraCh5}, + {GPIO('C',15), 4, TimeraCh6}, + {GPIO('D', 2), 2, TimeraCh4}, +}; + + +struct gpio_pwm +gpio_pwm_setup(uint8_t gpio, uint32_t cycle_time, uint8_t val) +{ + // Find gpio pin in pwm_regs table + const struct gpio_pwm_info* p = pwm_mapping; + for (;; p++) { + if (p >= &pwm_mapping[ARRAY_SIZE(pwm_mapping)]) + shutdown("Not a valid PWM pin"); + if (p->gpio == gpio) + break; + } + + // select registers - could make it programmatic + // All TimerA power control bits are in PWC_FCG2 + M4_TMRA_TypeDef *timerA; + switch (p->unit) + { + default: + case 1: + timerA = M4_TMRA1; + PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIMA1, Enable); + break; + case 2: + timerA = M4_TMRA2; + PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIMA2, Enable); + break; + case 3: + timerA = M4_TMRA3; + PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIMA3, Enable); + break; + case 4: + timerA = M4_TMRA4; + PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIMA4, Enable); + break; + case 5: + timerA = M4_TMRA5; + PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIMA5, Enable); + break; + case 6: + timerA = M4_TMRA6; + PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIMA6, Enable); + break; + } + + // set the function - only using #4 (Func_Tima0) + PORT_SetFunc(GPIO2PORT(gpio), GPIO2PIN(gpio), Func_Tima0, Disable); + + /* Configuration timera unit 1 base structure */ + stc_timera_base_init_t stcTimeraInit; + stcTimeraInit.enClkDiv = TimeraPclkDiv128; // 128 chosen - use below + stcTimeraInit.enCntMode = TimeraCountModeTriangularWave; + stcTimeraInit.enCntDir = TimeraCountDirUp; + stcTimeraInit.enSyncStartupEn = Disable; + stcTimeraInit.u16PeriodVal = cycle_time / 2U / 128U / 2; + TIMERA_BaseInit(timerA, &stcTimeraInit); + + /* Configuration timera unit 1 compare structure */ + stc_timera_compare_init_t stcTimerCompareInit; + stcTimerCompareInit.u16CompareVal = stcTimeraInit.u16PeriodVal * 4u / 5u; + stcTimerCompareInit.enStartCountOutput = TimeraCountStartOutputHigh; + stcTimerCompareInit.enStopCountOutput = TimeraCountStopOutputHigh; + stcTimerCompareInit.enCompareMatchOutput = TimeraCompareMatchOutputReverse; + stcTimerCompareInit.enPeriodMatchOutput = TimeraPeriodMatchOutputKeep; + stcTimerCompareInit.enSpecifyOutput = TimeraSpecifyOutputInvalid; + stcTimerCompareInit.enCacheEn = Disable; + stcTimerCompareInit.enTriangularTroughTransEn = Enable; + stcTimerCompareInit.enTriangularCrestTransEn = Disable; + stcTimerCompareInit.u16CompareCacheVal = stcTimerCompareInit.u16CompareVal; + TIMERA_CompareInit(timerA, p->chan, &stcTimerCompareInit); + TIMERA_CompareCmd(timerA, p->chan, Enable); + + // default setup - all disabled + stc_timera_hw_startup_config_t stcTimeraHwConfig = { 0 }; + TIMERA_HwStartupConfig(timerA, &stcTimeraHwConfig); + + return (struct gpio_pwm){.timer = timerA, .chan = p->chan}; +} + + +void +gpio_pwm_write(struct gpio_pwm g, uint32_t val) +{ + TIMERA_SetCompareValue(g.timer, g.chan, (uint16_t)val); +} diff --git a/src/hc32f460/internal.h b/src/hc32f460/internal.h new file mode 100644 index 000000000000..dd02f9f3c9d2 --- /dev/null +++ b/src/hc32f460/internal.h @@ -0,0 +1,29 @@ +#ifndef __HC32F460_INTERNAL_H +#define __HC32F460_INTERNAL_H + + +// Local definitions for Huada HC32F460 + +#include "autoconf.h" +#include "hc32f460.h" + +// The HC32F460 library uses a port address and a shifted pin bit +// eg en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin); +// see hc32f460_gpio.h + + +// encode and decode gpio ports and pins +#define GPIO(PORT, NUM) (((PORT)-'A') * 16 + (NUM)) +#define GPIO2PORT(GPIO) ((GPIO) / 16) +#define GPIO2BIT(GPIO) (1<<((GPIO) % 16)) +#define GPIO2PIN(GPIO) ((GPIO) % 16) + +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +void gpio_peripheral(uint32_t pin, int func, int pull_up); + +// from local interrupts.c - helper +void IrqRegistration(en_int_src_t irqSrc, IRQn_Type irqType); + +#endif // internal.h diff --git a/src/hc32f460/interrupts.c b/src/hc32f460/interrupts.c new file mode 100644 index 000000000000..fb93648fbb1e --- /dev/null +++ b/src/hc32f460/interrupts.c @@ -0,0 +1,29 @@ +// Interrupt support for HC32F460 +// The library interrupt support is huge and redefines systick +// +// Copyright (C) 2022 Steven Gotthardt +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "hc32f460.h" + +#define IRQ_PRIORITY_DEFAULT 15u + +/* the interrupts on the hc32f460 can be 're-assigned' + The author can choose the irqType (IRQ000_Handler, etc...) + that the source (irqSrc) triggers + */ + +void IrqRegistration(en_int_src_t irqSrc, IRQn_Type irqType) +{ + stc_intc_sel_field_t *stcIntSel = (stc_intc_sel_field_t *) + ((uint32_t)(&M4_INTC->SEL0) + (4u * irqType)); + + // what is the source of the selected interrupt? (USART, etc...) + stcIntSel->INTSEL = irqSrc; + + // set priority and enable + NVIC_SetPriority(irqType, IRQ_PRIORITY_DEFAULT); + NVIC_ClearPendingIRQ(irqType); + NVIC_EnableIRQ(irqType); +} diff --git a/src/hc32f460/main.c b/src/hc32f460/main.c new file mode 100644 index 000000000000..a641667f2816 --- /dev/null +++ b/src/hc32f460/main.c @@ -0,0 +1,28 @@ +// Code to setup clocks on Huada HC32F460 +// +// Copyright (C) 2022 Steven Gotthardt +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" // CONFIG_MACH_AVR +#include "sched.h" +#include "system_hc32f460.h" + + +/**************************************************************** + * Startup + ****************************************************************/ + +// Main entry point - called from armcm_boot.c:ResetHandler() +void __attribute__((noreturn)) +armcm_main(void) +{ + // sets the system clock speed variable for library use + SystemInit(); + + // manage the system + sched_main(); + + // never get here + for (;;) ; +} diff --git a/src/hc32f460/serial.c b/src/hc32f460/serial.c new file mode 100644 index 000000000000..45f6b89f59d3 --- /dev/null +++ b/src/hc32f460/serial.c @@ -0,0 +1,189 @@ +// HC32F460 serial +// +// Copyright (C) 2022 Steven Gotthardt +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" // CONFIG_SERIAL_BAUD + +#include "command.h" // DECL_CONSTANT_STR +#include "internal.h" +#include "sched.h" // DECL_INIT +#include "generic/serial_irq.h" +#include "generic/armcm_boot.h" + +#include "hc32f460_usart.h" +#include "hc32f460_gpio.h" +#include "hc32f460_pwc.h" + + +#define USART_BAUDRATE (CONFIG_SERIAL_BAUD) + + +// Aquila 1.0.3 pins for TX, RX to CH304 on PA15 and PA09 +// for the LCD connector: TX, RX on PC00 and PC01 +#if CONFIG_HC32F460_SERIAL_PA15_PA9 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA15,PA9"); + #define USART_RX_PORT (PortA) + #define USART_RX_PIN (Pin15) + #define USART_TX_PORT (PortA) + #define USART_TX_PIN (Pin09) + +#elif CONFIG_HC32F460_SERIAL_PC0_PC1 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PC0,PC1"); + #define USART_RX_PORT (PortC) + #define USART_RX_PIN (Pin00) + #define USART_TX_PORT (PortC) + #define USART_TX_PIN (Pin01) + +#elif CONFIG_HC32F460_SERIAL_PA3_PA2 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2"); + #define USART_RX_PORT (PortA) + #define USART_RX_PIN (Pin03) + #define USART_TX_PORT (PortA) + #define USART_TX_PIN (Pin02) + +#elif CONFIG_HC32F460_SERIAL_PA7_PA8 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA7,PA8"); + #define USART_RX_PORT (PortA) + #define USART_RX_PIN (Pin07) + #define USART_TX_PORT (PortA) + #define USART_TX_PIN (Pin08) +#endif + +// use USART 1 for serial connection +#define USARTx M4_USART1 +#define USART_ENABLE (PWC_FCG1_PERIPH_USART1 | PWC_FCG1_PERIPH_USART2 | \ + PWC_FCG1_PERIPH_USART3 | PWC_FCG1_PERIPH_USART4) + +#define USART_RX_FUNC Func_Usart1_Rx +#define USART_TX_FUNC Func_Usart1_Tx +#define USART_RI_NUM INT_USART1_RI +#define USART_TI_NUM INT_USART1_TI +#define USART_EI_NUM INT_USART1_EI +#define USART_TCI_NUM INT_USART1_TCI + + +void +serialError(void) +{ + if (Set == USART_GetStatus(USARTx, UsartFrameErr)) + { + USART_ClearStatus(USARTx, UsartFrameErr); + + // use it anyway + serial_rx_byte(USARTx->DR_f.RDR); + } + + if (Set == USART_GetStatus(USARTx, UsartOverrunErr)) + { + USART_ClearStatus(USARTx, UsartOverrunErr); + } +} +DECL_ARMCM_IRQ(serialError, Int001_IRQn); + + +void +serialTxComplete(void) +{ + USART_FuncCmd(USARTx, UsartTx, Disable); + USART_FuncCmd(USARTx, UsartTxCmpltInt, Disable); +} +DECL_ARMCM_IRQ(serialTxComplete, Int003_IRQn); + + +void +serialRx(void) +{ + uint16_t data = USART_RecData(USARTx); + + // call to klipper generic/serial_irq function + serial_rx_byte(data); +} +DECL_ARMCM_IRQ(serialRx, Int000_IRQn); + + +void +serialTxEmpty(void) +{ + uint8_t data2send; + + // use helper from generic - zero means byte ready + if (!serial_get_tx_byte(&data2send)) + { + //USARTx->DR_f.TDR = data2send; + USART_SendData(USARTx, data2send); + } + else + { + // no more data - stop the interrupt + USART_FuncCmd(USARTx, UsartTxCmpltInt, Enable); + USART_FuncCmd(USARTx, UsartTxEmptyInt, Disable); + } +} +DECL_ARMCM_IRQ(serialTxEmpty, Int002_IRQn); + + +// called by generic framework +void +serial_enable_tx_irq(void) +{ + /* Enable TX && TX empty interrupt */ + USART_FuncCmd(USARTx, UsartTxAndTxEmptyInt, Enable); +} + + +void +serial_init(void) +{ + const stc_usart_uart_init_t stcInitCfg = { + UsartIntClkCkNoOutput, + UsartClkDiv_1, + UsartDataBits8, + UsartDataLsbFirst, + UsartOneStopBit, + UsartParityNone, + UsartSampleBit16, + UsartStartBitFallEdge, + UsartRtsEnable, + }; + + // Function Clock Control - USART enable (sets bit to a 0) + PWC_Fcg1PeriphClockCmd(USART_ENABLE, Enable); + + /* Initialize port pins for USART IO - Disable = NO subfunction */ + PORT_SetFunc(USART_RX_PORT, USART_RX_PIN, USART_RX_FUNC, Disable); + PORT_SetFunc(USART_TX_PORT, USART_TX_PIN, USART_TX_FUNC, Disable); + + /* Initialize UART */ + USART_UART_Init(USARTx, &stcInitCfg); + + /* Set baudrate */ + USART_SetBaudrate(USARTx, USART_BAUDRATE); + + /* A word on interrupts in HC32F460 + In other vendors (STM) the irqs are assigned names in the vector list + eg: USART1_IRQn but HC32F460 has numbered IRQs: IRQ000_IRQn IRQ143_IRQn + Using INT_USART1_RI from hc32f460.h put in to IRQn->INTSEL + if n = 5 then the USART1_RI iterrupt will be at IRQ005_IRQn + For the specific case of each USART there are 5 separate irqs to map + */ + + /* Set USART RX IRQ */ + IrqRegistration(USART_RI_NUM, Int000_IRQn); + + /* Set USART err */ + IrqRegistration(USART_EI_NUM, Int001_IRQn); + + /* Set USART TX IRQ */ + IrqRegistration(USART_TI_NUM, Int002_IRQn); + + /* Set USART TX complete IRQ */ + IrqRegistration(USART_TCI_NUM, Int003_IRQn); + + /* Enable RX && RX interrupt function */ + USART_FuncCmd(USARTx, UsartRx, Enable); + USART_FuncCmd(USARTx, UsartRxInt, Enable); +} + +DECL_INIT(serial_init); diff --git a/src/initial_pins.c b/src/initial_pins.c index cd478508c682..af01b3acc7ed 100644 --- a/src/initial_pins.c +++ b/src/initial_pins.c @@ -16,6 +16,8 @@ DECL_CTR("DECL_INITIAL_PINS " __stringify(CONFIG_INITIAL_PINS)); void initial_pins_setup(void) { + if (sizeof(CONFIG_INITIAL_PINS) <= 1) + return; int i; for (i=0; i // open -#include // I2C_SLAVE +#include // I2C_SLAVE i2c_msg +#include // i2c_rdwr_ioctl_data I2C_M_RD I2C_FUNC_I2C #include // snprintf #include // ioctl #include // write @@ -42,6 +43,13 @@ i2c_open(uint32_t bus, uint8_t addr) report_errno("open i2c", fd); goto fail; } + // Test for I2C_RDWR support + unsigned long i2c_funcs; // datatype from ioctl spec. + ioctl(fd, I2C_FUNCS, &i2c_funcs); + if ((i2c_funcs & I2C_FUNC_I2C) == 0) { + report_errno("i2c does not support I2C_RDWR", fd); + goto fail; + } int ret = ioctl(fd, I2C_SLAVE, addr); if (ret < 0) { report_errno("ioctl i2c", fd); @@ -73,7 +81,7 @@ i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr) // dtparam=i2c_baudrate= int fd = i2c_open(bus, addr); - return (struct i2c_config){.fd=fd}; + return (struct i2c_config){.fd=fd, .addr=addr}; } void @@ -91,12 +99,29 @@ void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *data) { - if(reg_len != 0) - i2c_write(config, reg_len, reg); - int ret = read(config.fd, data, read_len); - if (ret != read_len) { - if (ret < 0) - report_errno("read value i2c", ret); + struct i2c_rdwr_ioctl_data i2c_data; + struct i2c_msg msgs[2]; + + if(reg_len != 0) { + msgs[0].addr = config.addr; + msgs[0].flags = 0x0; + msgs[0].len = reg_len; + msgs[0].buf = reg; + i2c_data.nmsgs = 2; + i2c_data.msgs = &msgs[0]; + } else { + i2c_data.nmsgs = 1; + i2c_data.msgs = &msgs[1]; + } + + msgs[1].addr = config.addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = read_len; + msgs[1].buf = data; + + int ret = ioctl(config.fd, I2C_RDWR, &i2c_data); + + if(ret < 0) { try_shutdown("Unable to read i2c device"); } } diff --git a/src/linux/internal.h b/src/linux/internal.h index 001a90720ccf..db841ac91d84 100644 --- a/src/linux/internal.h +++ b/src/linux/internal.h @@ -6,7 +6,7 @@ #include // uint32_t #include "autoconf.h" // CONFIG_CLOCK_FREQ -#define MAX_GPIO_LINES 256 +#define MAX_GPIO_LINES 288 #define GPIO(PORT, NUM) ((PORT) * MAX_GPIO_LINES + (NUM)) #define GPIO2PORT(PIN) ((PIN) / MAX_GPIO_LINES) #define GPIO2PIN(PIN) ((PIN) % MAX_GPIO_LINES) diff --git a/src/linux/main.c b/src/linux/main.c index 4c5478ebf6ca..f9ea3f6daaa8 100644 --- a/src/linux/main.c +++ b/src/linux/main.c @@ -4,10 +4,11 @@ // // This file may be distributed under the terms of the GNU GPLv3 license. -#include // sched_setscheduler +#include // sched_setscheduler sched_get_priority_max #include // fprintf #include // memset #include // getopt +#include // mlockall MCL_CURRENT MCL_FUTURE #include "board/misc.h" // console_sendf #include "command.h" // DECL_CONSTANT #include "internal.h" // console_setup @@ -25,12 +26,18 @@ realtime_setup(void) { struct sched_param sp; memset(&sp, 0, sizeof(sp)); - sp.sched_priority = 1; + sp.sched_priority = sched_get_priority_max(SCHED_FIFO) / 2; int ret = sched_setscheduler(0, SCHED_FIFO, &sp); if (ret < 0) { report_errno("sched_setscheduler", ret); return -1; } + // Lock ourselves into memory + ret = mlockall(MCL_CURRENT | MCL_FUTURE); + if (ret) { + report_errno("mlockall", ret); + return -1; + } return 0; } @@ -62,7 +69,8 @@ main(int argc, char **argv) // Parse program args orig_argv = argv; int opt, watchdog = 0, realtime = 0; - while ((opt = getopt(argc, argv, "wr")) != -1) { + char *serial = "/tmp/klipper_host_mcu"; + while ((opt = getopt(argc, argv, "wrI:")) != -1) { switch (opt) { case 'w': watchdog = 1; @@ -70,8 +78,11 @@ main(int argc, char **argv) case 'r': realtime = 1; break; + case 'I': + serial = optarg; + break; default: - fprintf(stderr, "Usage: %s [-w] [-r]\n", argv[0]); + fprintf(stderr, "Usage: %s [-w] [-r] [-I path]\n", argv[0]); return -1; } } @@ -82,7 +93,7 @@ main(int argc, char **argv) if (ret) return ret; } - int ret = console_setup("/tmp/klipper_host_mcu"); + int ret = console_setup(serial); if (ret) return -1; if (watchdog) { diff --git a/src/lpc176x/Kconfig b/src/lpc176x/Kconfig index 2579029aab9c..79c3b3006c01 100644 --- a/src/lpc176x/Kconfig +++ b/src/lpc176x/Kconfig @@ -14,7 +14,7 @@ config LPC_SELECT select HAVE_CHIPID select HAVE_GPIO_HARD_PWM select HAVE_STEPPER_BOTH_EDGE - select SERIAL_BOOTLOADER_SIDECHANNEL + select HAVE_BOOTLOADER_REQUEST config BOARD_DIRECTORY string @@ -58,15 +58,28 @@ config STACK_SIZE int default 512 -config SMOOTHIEWARE_BOOTLOADER - bool "Target board uses Smoothieware bootloader" - default y -config FLASH_START +###################################################################### +# Bootloader +###################################################################### + +choice + prompt "Bootloader offset" + config LPC_FLASH_START_4000 + bool "16KiB bootloader (Smoothieware bootloader)" + config LPC_FLASH_START_0000 + bool "No bootloader" +endchoice +config FLASH_APPLICATION_ADDRESS hex - default 0x4000 if SMOOTHIEWARE_BOOTLOADER + default 0x4000 if LPC_FLASH_START_4000 default 0x0000 + +###################################################################### +# Communication inteface +###################################################################### + choice prompt "Communication interface" config LPC_USB diff --git a/src/lpc176x/main.c b/src/lpc176x/main.c index 7aa2855245fc..7fd05c5d2df6 100644 --- a/src/lpc176x/main.c +++ b/src/lpc176x/main.c @@ -44,7 +44,7 @@ DECL_INIT(watchdog_init); void bootloader_request(void) { - if (!CONFIG_SMOOTHIEWARE_BOOTLOADER) + if (!CONFIG_FLASH_APPLICATION_ADDRESS) return; try_request_canboot(); // Disable USB and pause for 5ms so host recognizes a disconnect diff --git a/src/lpc176x/usbserial.c b/src/lpc176x/usbserial.c index 858475ebaec1..7a54c84db3b6 100644 --- a/src/lpc176x/usbserial.c +++ b/src/lpc176x/usbserial.c @@ -5,7 +5,6 @@ // This file may be distributed under the terms of the GNU GPLv3 license. #include // memcpy -#include "autoconf.h" // CONFIG_SMOOTHIEWARE_BOOTLOADER #include "board/armcm_boot.h" // armcm_enable_irq #include "board/armcm_timer.h" // udelay #include "board/misc.h" // timer_read_time diff --git a/src/rp2040/Kconfig b/src/rp2040/Kconfig index 69b1cd58e77f..ba6f00f80db4 100644 --- a/src/rp2040/Kconfig +++ b/src/rp2040/Kconfig @@ -1,4 +1,4 @@ -# Kconfig settings for STM32 processors +# Kconfig settings for RP2040 processors if MACH_RP2040 @@ -14,6 +14,7 @@ config RP2040_SELECT select HAVE_CHIPID select HAVE_GPIO_HARD_PWM select HAVE_STEPPER_BOTH_EDGE + select HAVE_BOOTLOADER_REQUEST config BOARD_DIRECTORY string @@ -66,7 +67,7 @@ choice config RP2040_FLASH_START_4000 bool "16KiB bootloader" endchoice -config FLASH_START +config FLASH_APPLICATION_ADDRESS hex default 0x10004000 if RP2040_FLASH_START_4000 default 0x10000100 diff --git a/src/rp2040/Makefile b/src/rp2040/Makefile index 47954c9a322b..71ed90a0cc0a 100644 --- a/src/rp2040/Makefile +++ b/src/rp2040/Makefile @@ -9,9 +9,10 @@ CFLAGS += -mcpu=cortex-m0plus -mthumb -Ilib/cmsis-core CFLAGS += -Ilib/rp2040 -Ilib/rp2040/cmsis_include -Ilib/fast-hash -Ilib/can2040 # Add source files -src-y += rp2040/main.c rp2040/gpio.c rp2040/adc.c generic/crc16_ccitt.c +src-y += rp2040/main.c rp2040/watchdog.c rp2040/gpio.c +src-y += rp2040/adc.c rp2040/timer.c rp2040/bootrom.c src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c -src-y += generic/timer_irq.c rp2040/timer.c rp2040/bootrom.c +src-y += generic/timer_irq.c generic/crc16_ccitt.c src-$(CONFIG_USBSERIAL) += rp2040/usbserial.c generic/usb_cdc.c src-$(CONFIG_USBSERIAL) += rp2040/chipid.c src-$(CONFIG_SERIAL) += rp2040/serial.c generic/serial_irq.c @@ -44,7 +45,7 @@ $(OUT)klipper.uf2: $(OUT)klipper.elf $(OUT)lib/rp2040/elf2uf2/elf2uf2 @echo " Creating uf2 file $@" $(Q)$(OUT)lib/rp2040/elf2uf2/elf2uf2 $< $@ -target-$(CONFIG_RP2040_HAVE_STAGE2) += $(OUT)klipper.uf2 +rptarget-$(CONFIG_RP2040_HAVE_STAGE2) := $(OUT)klipper.uf2 rplink-$(CONFIG_RP2040_HAVE_STAGE2) := $(OUT)src/rp2040/rp2040_link.ld stage2-$(CONFIG_RP2040_HAVE_STAGE2) := $(OUT)stage2.o @@ -53,10 +54,11 @@ $(OUT)klipper.bin: $(OUT)klipper.elf @echo " Creating bin file $@" $(Q)$(OBJCOPY) -O binary $< $@ -target-$(CONFIG_RP2040_HAVE_BOOTLOADER) += $(OUT)klipper.bin +rptarget-$(CONFIG_RP2040_HAVE_BOOTLOADER) := $(OUT)klipper.bin rplink-$(CONFIG_RP2040_HAVE_BOOTLOADER) := $(OUT)src/generic/armcm_link.ld # Set klipper.elf linker rules +target-y += $(rptarget-y) CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs -T $(rplink-y) OBJS_klipper.elf += $(stage2-y) $(OUT)klipper.elf: $(stage2-y) $(rplink-y) @@ -66,6 +68,6 @@ lib/rp2040_flash/rp2040_flash: @echo " Building rp2040_flash" $(Q)make -C lib/rp2040_flash rp2040_flash -flash: $(OUT)klipper.uf2 lib/rp2040_flash/rp2040_flash +flash: $(rptarget-y) lib/rp2040_flash/rp2040_flash @echo " Flashing $< to $(FLASH_DEVICE)" - $(Q)$(PYTHON) ./scripts/flash_usb.py -t $(CONFIG_MCU) -d "$(FLASH_DEVICE)" $(if $(NOSUDO),--no-sudo) $(OUT)klipper.uf2 + $(Q)$(PYTHON) ./scripts/flash_usb.py -t $(CONFIG_MCU) -d "$(FLASH_DEVICE)" $(if $(NOSUDO),--no-sudo) $(rptarget-y) diff --git a/src/rp2040/can.c b/src/rp2040/can.c index 9c42cf36c26e..6cae2a7fb800 100644 --- a/src/rp2040/can.c +++ b/src/rp2040/can.c @@ -26,7 +26,7 @@ static struct can2040 cbus; // Transmit a packet int -canbus_send(struct canbus_msg *msg) +canhw_send(struct canbus_msg *msg) { int ret = can2040_transmit(&cbus, (void*)msg); if (ret < 0) @@ -36,7 +36,7 @@ canbus_send(struct canbus_msg *msg) // Setup the receive packet filter void -canbus_set_filter(uint32_t id) +canhw_set_filter(uint32_t id) { // Filter not implemented (and not necessary) } diff --git a/src/rp2040/main.c b/src/rp2040/main.c index c14e2759b3e1..0b144d0bba0c 100644 --- a/src/rp2040/main.c +++ b/src/rp2040/main.c @@ -9,7 +9,6 @@ #include "generic/armcm_reset.h" // try_request_canboot #include "hardware/structs/clocks.h" // clock_hw_t #include "hardware/structs/pll.h" // pll_hw_t -#include "hardware/structs/psm.h" // psm_hw #include "hardware/structs/resets.h" // sio_hw #include "hardware/structs/watchdog.h" // watchdog_hw #include "hardware/structs/xosc.h" // xosc_hw @@ -17,30 +16,6 @@ #include "sched.h" // sched_main -/**************************************************************** - * watchdog handler - ****************************************************************/ - -void -watchdog_reset(void) -{ - watchdog_hw->load = 0x800000; // ~350ms -} -DECL_TASK(watchdog_reset); - -void -watchdog_init(void) -{ - psm_hw->wdsel = PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS|PSM_WDSEL_XOSC_BITS); - watchdog_reset(); - watchdog_hw->ctrl = (WATCHDOG_CTRL_PAUSE_DBG0_BITS - | WATCHDOG_CTRL_PAUSE_DBG1_BITS - | WATCHDOG_CTRL_PAUSE_JTAG_BITS - | WATCHDOG_CTRL_ENABLE_BITS); -} -DECL_INIT(watchdog_init); - - /**************************************************************** * Bootloader ****************************************************************/ diff --git a/src/rp2040/usbserial.c b/src/rp2040/usbserial.c index aafe53ef8f35..e63e590dc640 100644 --- a/src/rp2040/usbserial.c +++ b/src/rp2040/usbserial.c @@ -96,7 +96,8 @@ int_fast8_t usb_read_ep0_setup(void *data, uint_fast8_t max_len) { if (!(usb_hw->intr & USB_INTR_SETUP_REQ_BITS)) { - usb_hw->inte = USB_INTE_BUFF_STATUS_BITS | USB_INTE_SETUP_REQ_BITS; + usb_hw->inte = (USB_INTE_BUFF_STATUS_BITS | USB_INTE_SETUP_REQ_BITS + | USB_INTE_BUS_RESET_BITS); return -1; } usb_dpram->ep_buf_ctrl[0].in = 0; @@ -168,6 +169,7 @@ usb_set_configure(void) // The rp2040 USB has an errata causing it to sometimes not connect // after a reset. The following code has extracts from the PICO SDK. +static uint8_t need_errata; static struct task_wake usb_errata_wake; // Workaround for rp2040-e5 errata @@ -253,7 +255,7 @@ USB_Handler(void) { uint32_t ints = usb_hw->ints; if (ints & USB_INTS_SETUP_REQ_BITS) { - usb_hw->inte = USB_INTE_BUFF_STATUS_BITS; + usb_hw->inte = USB_INTE_BUFF_STATUS_BITS | USB_INTE_BUS_RESET_BITS; usb_notify_ep0(); } if (ints & USB_INTS_BUFF_STATUS_BITS) { @@ -272,8 +274,10 @@ USB_Handler(void) } } if (ints & USB_INTS_BUS_RESET_BITS) { + usb_hw->dev_addr_ctrl = 0; usb_hw->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; - sched_wake_task(&usb_errata_wake); + if (need_errata) + sched_wake_task(&usb_errata_wake); } } @@ -317,11 +321,12 @@ usbserial_init(void) uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET)); uint32_t version = ((chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB); + need_errata = (version == 1); // Enable irqs usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS; usb_hw->inte = (USB_INTE_BUFF_STATUS_BITS | USB_INTE_SETUP_REQ_BITS - | (version == 1 ? USB_INTE_BUS_RESET_BITS: 0)); + | USB_INTE_BUS_RESET_BITS); armcm_enable_irq(USB_Handler, USBCTRL_IRQ_IRQn, 1); // Enable USB pullup diff --git a/src/rp2040/watchdog.c b/src/rp2040/watchdog.c new file mode 100644 index 000000000000..dda7aa55654b --- /dev/null +++ b/src/rp2040/watchdog.c @@ -0,0 +1,29 @@ +// Watchdog code on rp2040 +// +// Copyright (C) 2021-2022 Kevin O'Connor +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include // uint32_t +#include "hardware/structs/psm.h" // psm_hw +#include "hardware/structs/watchdog.h" // watchdog_hw +#include "sched.h" // DECL_TASK + +void +watchdog_reset(void) +{ + watchdog_hw->load = 0x800000; // ~350ms +} +DECL_TASK(watchdog_reset); + +void +watchdog_init(void) +{ + psm_hw->wdsel = PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS|PSM_WDSEL_XOSC_BITS); + watchdog_reset(); + watchdog_hw->ctrl = (WATCHDOG_CTRL_PAUSE_DBG0_BITS + | WATCHDOG_CTRL_PAUSE_DBG1_BITS + | WATCHDOG_CTRL_PAUSE_JTAG_BITS + | WATCHDOG_CTRL_ENABLE_BITS); +} +DECL_INIT(watchdog_init); diff --git a/src/sdiocmds.c b/src/sdiocmds.c new file mode 100644 index 000000000000..d9c020b4baa2 --- /dev/null +++ b/src/sdiocmds.c @@ -0,0 +1,166 @@ +// Commands for sending messages on an SDIO bus +// +// Copyright (C) 2022 H. Gregor Molter +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include // memcpy +#include "board/gpio.h" // gpio_in_setup +#include "board/sdio.h" // sdio_setup +#include "basecmd.h" // oid_alloc +#include "command.h" // DECL_COMMAND +#include "sched.h" // DECL_SHUTDOWN + +struct sdiodev_s { + struct sdio_config sdio_config; + uint32_t blocksize; + uint32_t speed; + uint8_t data_buffer[4096]; +}; + +#define TIMEOUT_MSEC 500 + +void +command_config_sdio(uint32_t *args) +{ + struct sdiodev_s *sdio = oid_alloc(args[0], command_config_sdio + , sizeof(*sdio)); + sdio->blocksize = args[1]; + sdio->speed = 400000; // Initial speed set to ~400khz +} +DECL_COMMAND(command_config_sdio, "config_sdio oid=%c blocksize=%u"); + +struct sdiodev_s * +sdiodev_oid_lookup(uint8_t oid) +{ + return oid_lookup(oid, command_config_sdio); +} + +void +command_sdio_set_bus(uint32_t *args) +{ + struct sdiodev_s *sdio = sdiodev_oid_lookup(args[0]); + sdio->sdio_config = sdio_setup(args[1]); +} +DECL_COMMAND(command_sdio_set_bus, "sdio_set_bus oid=%c sdio_bus=%u"); + +void +command_sdio_set_speed(uint32_t *args) +{ + struct sdiodev_s *sdio = sdiodev_oid_lookup(args[0]); + sdio->speed = args[1]; + sdio_set_speed(sdio->sdio_config, sdio->speed); +} +DECL_COMMAND(command_sdio_set_speed, "sdio_set_speed oid=%c speed=%u"); + +void +command_sdio_send_command(uint32_t *args) +{ + uint8_t oid = args[0]; + uint8_t cmd = args[1]; + uint32_t argument = args[2]; + uint8_t wait = args[3]; + struct sdiodev_s *sdio = sdiodev_oid_lookup(oid); + uint8_t response[16]; + uint8_t response_len = 0; + uint8_t err = sdio_send_command(sdio->sdio_config, cmd, argument, wait + , response, &response_len); + sendf("sdio_send_command_response oid=%c error=%c response=%*s" + , oid, err, response_len, response); +} +DECL_COMMAND(command_sdio_send_command + , "sdio_send_command oid=%c cmd=%c argument=%u wait=%c"); + +void +command_sdio_read_data(uint32_t *args) +{ + uint8_t oid = args[0]; + uint8_t cmd = args[1]; + uint32_t argument = args[2]; + uint32_t data_len = 0; + struct sdiodev_s *sdio = sdiodev_oid_lookup(oid); + uint32_t timeout = TIMEOUT_MSEC*sdio->speed/1000; + uint8_t err = sdio_prepare_data_transfer(sdio->sdio_config, 1, 1 + , sdio->blocksize, timeout); + if (err == 0) { + err = sdio_send_command(sdio->sdio_config, cmd, argument + , 1, NULL, NULL); + if (err == 0) { + data_len = sdio->blocksize; + if (data_len <= sizeof(sdio->data_buffer)) { + err = sdio_read_data(sdio->sdio_config, sdio->data_buffer + , 1, sdio->blocksize); + } else { + data_len = 0; + } + } + } + sendf("sdio_read_data_response oid=%c error=%c read=%u" + , oid, err, data_len); +} +DECL_COMMAND(command_sdio_read_data + , "sdio_read_data oid=%c cmd=%c argument=%u"); + +void +command_sdio_write_data(uint32_t *args) +{ + uint8_t oid = args[0]; + uint8_t cmd = args[1]; + uint32_t argument = args[2]; + uint32_t data_len = 0; + struct sdiodev_s *sdio = sdiodev_oid_lookup(oid); + uint32_t timeout = TIMEOUT_MSEC*sdio->speed/1000; + uint8_t err = sdio_prepare_data_transfer(sdio->sdio_config, 0, 1 + , sdio->blocksize, timeout); + if (err == 0) { + err = sdio_send_command(sdio->sdio_config, cmd, argument + , 1, NULL, NULL); + if (err == 0) { + data_len = sdio->blocksize; + if (data_len <= sizeof(sdio->data_buffer)) { + err = sdio_write_data(sdio->sdio_config, sdio->data_buffer + , 1, sdio->blocksize); + } else { + data_len = 0; + } + } + } + sendf("sdio_write_data_response oid=%c error=%c write=%u" + , oid, err, data_len); +} +DECL_COMMAND(command_sdio_write_data + , "sdio_write_data oid=%c cmd=%c argument=%u"); + +void +command_sdio_read_data_buffer(uint32_t *args) +{ + uint8_t oid = args[0]; + uint32_t offset = args[1]; + uint8_t len = args[2]; + struct sdiodev_s *sdio = sdiodev_oid_lookup(oid); + uint8_t *buf = &(sdio->data_buffer[offset]); + + if (offset + len > sizeof(sdio->data_buffer)) { + len = 0; + } + sendf("sdio_read_data_buffer_response oid=%c data=%*s", oid, len, buf); +} +DECL_COMMAND(command_sdio_read_data_buffer + , "sdio_read_data_buffer oid=%c offset=%u len=%c"); + +void +command_sdio_write_data_buffer(uint32_t *args) +{ + uint8_t oid = args[0]; + uint32_t offset = args[1]; + uint8_t write_data_len = args[2]; + uint8_t *write_data = command_decode_ptr(args[3]); + struct sdiodev_s *sdio = sdiodev_oid_lookup(oid); + uint8_t *buf = &(sdio->data_buffer[offset]); + + if (offset + write_data_len <= sizeof(sdio->data_buffer)) { + memcpy(buf, write_data, write_data_len); + } +} +DECL_COMMAND(command_sdio_write_data_buffer + , "sdio_write_data_buffer oid=%c offset=%u data=%*s"); diff --git a/src/sdiocmds.h b/src/sdiocmds.h new file mode 100644 index 000000000000..24ec9811c952 --- /dev/null +++ b/src/sdiocmds.h @@ -0,0 +1,8 @@ +#ifndef __SDIOCMDS_H +#define __SDIOCMDS_H + +#include // uint8_t + +struct sdiodev_s *sdiodev_oid_lookup(uint8_t oid); + +#endif // sdiocmds.h diff --git a/src/sensor_mpu9250.c b/src/sensor_mpu9250.c index d7f3092867ce..51df5a711d31 100644 --- a/src/sensor_mpu9250.c +++ b/src/sensor_mpu9250.c @@ -1,5 +1,6 @@ // Support for gathering acceleration data from mpu9250 chip // +// Copyright (C) 2023 Matthew Swabey // Copyright (C) 2022 Harry Beyel // Copyright (C) 2020-2021 Kevin O'Connor // @@ -24,6 +25,7 @@ #define AR_USER_CTRL 0x6A #define AR_FIFO_COUNT_H 0x72 #define AR_FIFO 0x74 +#define AR_INT_STATUS 0x3A #define SET_ENABLE_FIFO 0x08 #define SET_DISABLE_FIFO 0x00 @@ -35,15 +37,17 @@ #define SET_PWR_2_ACCEL 0x07 // only enable accelerometers #define SET_PWR_2_NONE 0x3F // disable all sensors +#define FIFO_OVERFLOW_INT 0x10 + #define BYTES_PER_FIFO_ENTRY 6 struct mpu9250 { struct timer timer; uint32_t rest_ticks; struct i2cdev_s *i2c; - uint16_t sequence, limit_count; + uint16_t sequence, limit_count, fifo_max, fifo_pkts_bytes; uint8_t flags, data_count; - // data size must be <= 255 due to i2c api + // msg size must be <= 255 due to Klipper api // = SAMPLES_PER_BLOCK (from mpu9250.py) * BYTES_PER_FIFO_ENTRY + 1 uint8_t data[48]; }; @@ -55,14 +59,16 @@ enum { static struct task_wake mpu9250_wake; // Reads the fifo byte count from the device. -uint16_t +static uint16_t get_fifo_status (struct mpu9250 *mp) { - uint8_t regs[] = {AR_FIFO_COUNT_H}; + uint8_t reg[] = {AR_FIFO_COUNT_H}; uint8_t msg[2]; - i2c_read(mp->i2c->i2c_config, sizeof(regs), regs, 2, msg); + i2c_read(mp->i2c->i2c_config, sizeof(reg), reg, sizeof(msg), msg); msg[0] = 0x1F & msg[0]; // discard 3 MSB per datasheet - return (((uint16_t)msg[0]) << 8 | msg[1]); + uint16_t bytes_to_read = ((uint16_t)msg[0]) << 8 | msg[1]; + if (bytes_to_read > mp->fifo_max) mp->fifo_max = bytes_to_read; + return bytes_to_read; } // Event handler that wakes mpu9250_task() periodically @@ -120,42 +126,30 @@ mp9250_reschedule_timer(struct mpu9250 *mp) static void mp9250_query(struct mpu9250 *mp, uint8_t oid) { - // Check fifo status - uint16_t fifo_bytes = get_fifo_status(mp); - if (fifo_bytes >= AR_FIFO_SIZE - BYTES_PER_FIFO_ENTRY) - mp->limit_count++; - - // Read data - // FIFO data are: [Xh, Xl, Yh, Yl, Zh, Zl] - uint8_t reg = AR_FIFO; - uint8_t bytes_to_read = fifo_bytes < sizeof(mp->data) - mp->data_count ? - fifo_bytes & 0xFF : - (sizeof(mp->data) - mp->data_count) & 0xFF; + // Find remaining space in report buffer + uint8_t data_space = sizeof(mp->data) - mp->data_count; - // round down to nearest full packet of data - bytes_to_read = bytes_to_read / BYTES_PER_FIFO_ENTRY * BYTES_PER_FIFO_ENTRY; + // If not enough bytes to fill report read MPU FIFO's fill + if (mp->fifo_pkts_bytes < data_space) { + mp->fifo_pkts_bytes = get_fifo_status(mp) / BYTES_PER_FIFO_ENTRY + * BYTES_PER_FIFO_ENTRY; + } - // Extract x, y, z measurements into data holder and report - if (bytes_to_read > 0) { + // If we have enough bytes to fill the buffer do it and send report + if (mp->fifo_pkts_bytes >= data_space) { + uint8_t reg = AR_FIFO; i2c_read(mp->i2c->i2c_config, sizeof(reg), ®, - bytes_to_read, &mp->data[mp->data_count]); - mp->data_count += bytes_to_read; - - // report data when buffer is full - if (mp->data_count + BYTES_PER_FIFO_ENTRY > sizeof(mp->data)) { - mp9250_report(mp, oid); - } + data_space, &mp->data[mp->data_count]); + mp->data_count += data_space; + mp->fifo_pkts_bytes -= data_space; + mp9250_report(mp, oid); } - // check if we need to run the task again (more packets in fifo?) - if ( bytes_to_read > 0 && - bytes_to_read / BYTES_PER_FIFO_ENTRY < - fifo_bytes / BYTES_PER_FIFO_ENTRY) { - // more data still ready in the fifo buffer + // If we have enough bytes remaining to fill another report wake again + // otherwise schedule timed wakeup + if (mp->fifo_pkts_bytes > data_space) { sched_wake_task(&mpu9250_wake); - } - else if (mp->flags & AX_RUNNING) { - // No more fifo data, but actively running. Sleep until next check + } else if (mp->flags & AX_RUNNING) { sched_del_timer(&mp->timer); mp->flags &= ~AX_PENDING; mp9250_reschedule_timer(mp); @@ -182,6 +176,9 @@ mp9250_start(struct mpu9250 *mp, uint8_t oid) msg[1] = SET_USER_FIFO_EN; // enable FIFO buffer access i2c_write(mp->i2c->i2c_config, sizeof(msg), msg); + uint8_t int_reg[] = {AR_INT_STATUS}; // clear FIFO overflow flag + i2c_read(mp->i2c->i2c_config, sizeof(int_reg), int_reg, 1, msg); + msg[0] = AR_FIFO_EN; msg[1] = SET_ENABLE_FIFO; // enable accel output to FIFO i2c_write(mp->i2c->i2c_config, sizeof(msg), msg); @@ -203,18 +200,24 @@ mp9250_stop(struct mpu9250 *mp, uint8_t oid) i2c_write(mp->i2c->i2c_config, sizeof(msg), msg); uint32_t end2_time = timer_read_time(); - // Drain any measurements still in fifo - uint16_t fifo_bytes = get_fifo_status(mp); - while (fifo_bytes >= BYTES_PER_FIFO_ENTRY) { - mp9250_query(mp, oid); - fifo_bytes = get_fifo_status(mp); - } + // Detect if a FIFO overrun occured + uint8_t int_reg[] = {AR_INT_STATUS}; + uint8_t int_msg; + i2c_read(mp->i2c->i2c_config, sizeof(int_reg), int_reg, sizeof(int_msg), + &int_msg); + if (int_msg & FIFO_OVERFLOW_INT) + mp->limit_count++; // Report final data if (mp->data_count > 0) mp9250_report(mp, oid); + uint16_t bytes_to_read = get_fifo_status(mp); mp9250_status(mp, oid, end1_time, end2_time, - fifo_bytes / BYTES_PER_FIFO_ENTRY); + bytes_to_read / BYTES_PER_FIFO_ENTRY); + + // Uncomment and rebuilt to check for FIFO overruns when tuning + //output("mpu9240 limit_count=%u fifo_max=%u", + // mp->limit_count, mp->fifo_max); } void @@ -232,8 +235,11 @@ command_query_mpu9250(uint32_t *args) mp->timer.waketime = args[1]; mp->rest_ticks = args[2]; mp->flags = AX_HAVE_START; - mp->sequence = mp->limit_count = 0; + mp->sequence = 0; + mp->limit_count = 0; mp->data_count = 0; + mp->fifo_max = 0; + mp->fifo_pkts_bytes = 0; sched_add_timer(&mp->timer); } DECL_COMMAND(command_query_mpu9250, @@ -245,12 +251,12 @@ command_query_mpu9250_status(uint32_t *args) struct mpu9250 *mp = oid_lookup(args[0], command_config_mpu9250); uint8_t msg[2]; uint32_t time1 = timer_read_time(); - uint8_t regs[] = {AR_FIFO_COUNT_H}; - i2c_read(mp->i2c->i2c_config, 1, regs, 2, msg); + uint8_t reg[] = {AR_FIFO_COUNT_H}; + i2c_read(mp->i2c->i2c_config, sizeof(reg), reg, sizeof(msg), msg); uint32_t time2 = timer_read_time(); msg[0] = 0x1F & msg[0]; // discard 3 MSB - uint16_t fifo_bytes = (((uint16_t)msg[0]) << 8) | msg[1]; - mp9250_status(mp, args[0], time1, time2, fifo_bytes / BYTES_PER_FIFO_ENTRY); + mp9250_status(mp, args[0], time1, time2, mp->fifo_pkts_bytes + / BYTES_PER_FIFO_ENTRY); } DECL_COMMAND(command_query_mpu9250_status, "query_mpu9250_status oid=%c"); diff --git a/src/stm32/Kconfig b/src/stm32/Kconfig index 9cdb3c312071..5d82f9c3f6db 100644 --- a/src/stm32/Kconfig +++ b/src/stm32/Kconfig @@ -7,14 +7,15 @@ config STM32_SELECT default y select HAVE_GPIO select HAVE_GPIO_ADC - select HAVE_GPIO_I2C if !(MACH_STM32F031 || MACH_STM32H7) + select HAVE_GPIO_I2C if !(MACH_STM32F031) select HAVE_GPIO_SPI if !MACH_STM32F031 + select HAVE_GPIO_SDIO if MACH_STM32F4 select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32G0 || MACH_STM32H7 select HAVE_GPIO_BITBANGING if !MACH_STM32F031 select HAVE_STRICT_TIMING select HAVE_CHIPID select HAVE_STEPPER_BOTH_EDGE - select SERIAL_BOOTLOADER_SIDECHANNEL + select HAVE_BOOTLOADER_REQUEST config BOARD_DIRECTORY string @@ -65,9 +66,28 @@ choice bool "STM32F072" select MACH_STM32F0 select MACH_STM32F0x2 + config MACH_STM32G070 + bool "STM32G070" + select MACH_STM32G0 + select MACH_STM32G07x + config MACH_STM32G071 + bool "STM32G071" + select MACH_STM32G0 + select MACH_STM32G07x + config MACH_STM32G0B0 + bool "STM32G0B0" + select MACH_STM32G0 + select MACH_STM32G0Bx config MACH_STM32G0B1 bool "STM32G0B1" select MACH_STM32G0 + select MACH_STM32G0Bx + config MACH_STM32G431 + bool "STM32G431" + select MACH_STM32G4 + config MACH_STM32H723 + bool "STM32H723" + select MACH_STM32H7 config MACH_STM32H743 bool "STM32H743" select MACH_STM32H7 @@ -77,6 +97,14 @@ choice config MACH_STM32L412 bool "STM32L412" select MACH_STM32L4 + config MACH_N32G452 + bool "Nation N32G452" + select MACH_N32G45x + select MACH_STM32F1 + config MACH_N32G455 + bool "Nation N32G455" + select MACH_N32G45x + select MACH_STM32F1 endchoice config MACH_STM32F103x6 @@ -93,6 +121,12 @@ config MACH_STM32F4 bool config MACH_STM32G0 bool +config MACH_STM32G07x + bool +config MACH_STM32G0Bx + bool +config MACH_STM32G4 + bool config MACH_STM32H7 bool config MACH_STM32F0x2 # F042, F072 series @@ -101,10 +135,12 @@ config MACH_STM32F4x5 # F405, F407, F429 series bool config MACH_STM32L4 bool +config MACH_N32G45x + bool config HAVE_STM32_USBFS bool - default y if MACH_STM32F0x2 || MACH_STM32G0 || MACH_STM32L4 - default y if (MACH_STM32F103 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL + default y if MACH_STM32F0x2 || MACH_STM32G0Bx || MACH_STM32L4 || MACH_STM32G4 + default y if (MACH_STM32F1 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL config HAVE_STM32_USBOTG bool default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32H7 @@ -113,12 +149,12 @@ config HAVE_STM32_CANBUS default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2 config HAVE_STM32_FDCANBUS bool - default y if MACH_STM32G0 || MACH_STM32H7 + default y if MACH_STM32G0B1 || MACH_STM32H7 || MACH_STM32G4 config HAVE_STM32_USBCANBUS bool depends on HAVE_STM32_USBFS || HAVE_STM32_USBOTG depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS - depends on !MACH_STM32F103 + depends on !MACH_STM32F1 default y config MCU @@ -134,10 +170,16 @@ config MCU default "stm32f407xx" if MACH_STM32F407 default "stm32f429xx" if MACH_STM32F429 default "stm32f446xx" if MACH_STM32F446 + default "stm32g070xx" if MACH_STM32G070 + default "stm32g071xx" if MACH_STM32G071 + default "stm32g0b0xx" if MACH_STM32G0B0 default "stm32g0b1xx" if MACH_STM32G0B1 + default "stm32g431xx" if MACH_STM32G431 + default "stm32h723xx" if MACH_STM32H723 default "stm32h743xx" if MACH_STM32H743 default "stm32h750xx" if MACH_STM32H750 default "stm32l412xx" if MACH_STM32L412 + default "stm32f103xe" if MACH_N32G45x config CLOCK_FREQ int @@ -149,8 +191,11 @@ config CLOCK_FREQ default 168000000 if MACH_STM32F4x5 default 180000000 if MACH_STM32F446 default 64000000 if MACH_STM32G0 + default 150000000 if MACH_STM32G431 default 400000000 if MACH_STM32H7 # 400Mhz is max Klipper currently supports default 80000000 if MACH_STM32L412 + default 64000000 if MACH_N32G45x && STM32_CLOCK_REF_INTERNAL + default 128000000 if MACH_N32G45x config FLASH_SIZE hex @@ -158,11 +203,12 @@ config FLASH_SIZE default 0x8000 if MACH_STM32F042 default 0x20000 if MACH_STM32F070 || MACH_STM32F072 default 0x10000 if MACH_STM32F103 || MACH_STM32L412 # Flash size of stm32f103x8 (64KiB) - default 0x40000 if MACH_STM32F2 || MACH_STM32F401 + default 0x40000 if MACH_STM32F2 || MACH_STM32F401 || MACH_STM32H723 default 0x80000 if MACH_STM32F4x5 || MACH_STM32F446 - default 0x20000 if MACH_STM32G0B1 + default 0x20000 if MACH_STM32G0 || MACH_STM32G431 default 0x20000 if MACH_STM32H750 default 0x200000 if MACH_STM32H743 + default 0x20000 if MACH_N32G45x config FLASH_BOOT_ADDRESS hex @@ -179,12 +225,15 @@ config RAM_SIZE default 0x4000 if MACH_STM32F070 || MACH_STM32F072 default 0x2800 if MACH_STM32F103x6 default 0x5000 if MACH_STM32F103 && !MACH_STM32F103x6 # Ram size of stm32f103x8 + default 0x8000 if MACH_STM32G431 default 0xa000 if MACH_STM32L412 default 0x20000 if MACH_STM32F207 default 0x10000 if MACH_STM32F401 default 0x20000 if MACH_STM32F4x5 || MACH_STM32F446 - default 0x24000 if MACH_STM32G0B1 + default 0x9000 if MACH_STM32G07x + default 0x24000 if MACH_STM32G0Bx default 0x20000 if MACH_STM32H7 + default 0x10000 if MACH_N32G45x config STACK_SIZE int @@ -200,6 +249,15 @@ config STM32F103GD_DISABLE_SWD and PA14 pins from being available. Selecting this option disables SWD at startup and thus makes these pins available. +config STM32_DFU_ROM_ADDRESS + hex + default 0 if !USB + default 0x1fffc400 if MACH_STM32F042 + default 0x1fffc800 if MACH_STM32F072 + default 0x1fff0000 if MACH_STM32F4 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4 + default 0x1ff09800 if MACH_STM32H7 + default 0 + ###################################################################### # Bootloader @@ -208,11 +266,11 @@ config STM32F103GD_DISABLE_SWD choice prompt "Bootloader offset" config STM32_FLASH_START_2000 - bool "8KiB bootloader" if MACH_STM32F103 || MACH_STM32F070 || MACH_STM32G0 || MACH_STM32F0x2 + bool "8KiB bootloader" if MACH_STM32F1 || MACH_STM32F070 || MACH_STM32G0 || MACH_STM32F0x2 config STM32_FLASH_START_5000 bool "20KiB bootloader" if MACH_STM32F103 config STM32_FLASH_START_7000 - bool "28KiB bootloader" if MACH_STM32F103 + bool "28KiB bootloader" if MACH_STM32F1 config STM32_FLASH_START_8000 bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4 config STM32_FLASH_START_8800 @@ -231,12 +289,12 @@ choice config STM32_FLASH_START_4000 bool "16KiB bootloader (HID Bootloader)" if MACH_STM32F207 || MACH_STM32F401 || MACH_STM32F4x5 || MACH_STM32F103 || MACH_STM32F072 config STM32_FLASH_START_20000 - bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 + bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723 config STM32_FLASH_START_0000 bool "No bootloader" endchoice -config FLASH_START +config FLASH_APPLICATION_ADDRESS hex default 0x8000800 if STM32_FLASH_START_800 default 0x8001000 if STM32_FLASH_START_1000 @@ -254,7 +312,7 @@ config FLASH_START config ARMCM_RAM_VECTORTABLE bool - default y if MACH_STM32F0 && FLASH_START != 0x8000000 + default y if MACH_STM32F0 && FLASH_APPLICATION_ADDRESS != 0x8000000 default n @@ -310,7 +368,7 @@ choice select USBSERIAL config STM32_USB_PB14_PB15 bool "USB (on PB14/PB15)" - depends on MACH_STM32H7 + depends on MACH_STM32H743 || MACH_STM32H750 select USBSERIAL config STM32_SERIAL_USART1 bool "Serial (on USART1 PA10/PA9)" @@ -322,7 +380,10 @@ choice bool "Serial (on USART2 PA3/PA2)" if LOW_LEVEL_OPTIONS select SERIAL config STM32_SERIAL_USART2_ALT_PA15_PA14 - bool "Serial (on USART2 PA15/PA14)" if LOW_LEVEL_OPTIONS && MACH_STM32F0 + bool "Serial (on USART2 PA15/PA14)" if LOW_LEVEL_OPTIONS && (MACH_STM32F0 || MACH_STM32G4) + select SERIAL + config STM32_SERIAL_USART2_ALT_PB4_PB3 + bool "Serial (on USART2 PB4/PB3)" if LOW_LEVEL_OPTIONS && MACH_STM32G4 select SERIAL config STM32_SERIAL_USART2_ALT_PD6_PD5 bool "Serial (on USART2 PD6/PD5)" if LOW_LEVEL_OPTIONS && !MACH_STM32F0 @@ -339,6 +400,10 @@ choice bool "Serial (on UART4 PA0/PA1)" depends on MACH_STM32H7 select SERIAL + config STM32_SERIAL_USART5 + bool "Serial (on USART5 PD2/PD3)" if LOW_LEVEL_OPTIONS + depends on MACH_STM32G0Bx + select SERIAL config STM32_CANBUS_PA11_PA12 bool "CAN bus (on PA11/PA12)" depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS @@ -347,6 +412,10 @@ choice bool "CAN bus (on PA9/PA10)" if LOW_LEVEL_OPTIONS depends on HAVE_STM32_CANBUS && MACH_STM32F042 select CANSERIAL + config STM32_CANBUS_PA11_PB9 + bool "CAN bus (on PA11/PB9)" + depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS + select CANSERIAL config STM32_MMENU_CANBUS_PB8_PB9 bool "CAN bus (on PB8/PB9)" if LOW_LEVEL_OPTIONS depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS @@ -361,7 +430,7 @@ choice select CANSERIAL config STM32_MMENU_CANBUS_PB12_PB13 bool "CAN bus (on PB12/PB13)" if LOW_LEVEL_OPTIONS - depends on HAVE_STM32_CANBUS && MACH_STM32F4 + depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || HAVE_STM32_FDCANBUS select CANSERIAL config STM32_MMENU_CANBUS_PD0_PD1 bool "CAN bus (on PD0/PD1)" if LOW_LEVEL_OPTIONS @@ -396,7 +465,7 @@ choice depends on HAVE_STM32_CANBUS && MACH_STM32F4 config STM32_CMENU_CANBUS_PB12_PB13 bool "CAN bus (on PB12/PB13)" - depends on HAVE_STM32_CANBUS && MACH_STM32F4 + depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || HAVE_STM32_FDCANBUS config STM32_CMENU_CANBUS_PD0_PD1 bool "CAN bus (on PD0/PD1)" depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS diff --git a/src/stm32/Makefile b/src/stm32/Makefile index 8514a8df5451..e5dac2aac2d0 100644 --- a/src/stm32/Makefile +++ b/src/stm32/Makefile @@ -6,9 +6,11 @@ CROSS_PREFIX=arm-none-eabi- dirs-y += src/stm32 src/generic lib/fast-hash dirs-$(CONFIG_MACH_STM32F0) += lib/stm32f0 dirs-$(CONFIG_MACH_STM32F1) += lib/stm32f1 +dirs-$(CONFIG_MACH_N32G45x) += lib/n32g45x dirs-$(CONFIG_MACH_STM32F2) += lib/stm32f2 dirs-$(CONFIG_MACH_STM32F4) += lib/stm32f4 dirs-$(CONFIG_MACH_STM32G0) += lib/stm32g0 +dirs-$(CONFIG_MACH_STM32G4) += lib/stm32g4 dirs-$(CONFIG_MACH_STM32H7) += lib/stm32h7 dirs-$(CONFIG_MACH_STM32L4) += lib/stm32l4 @@ -16,10 +18,13 @@ MCU := $(shell echo $(CONFIG_MCU)) MCU_UPPER := $(shell echo $(CONFIG_MCU) | tr a-z A-Z | tr X x) CFLAGS-$(CONFIG_MACH_STM32F0) += -mcpu=cortex-m0 -Ilib/stm32f0/include -CFLAGS-$(CONFIG_MACH_STM32F1) += -mcpu=cortex-m3 -Ilib/stm32f1/include +CFLAGS-$(CONFIG_MACH_STM32F103) += -mcpu=cortex-m3 +CFLAGS-$(CONFIG_MACH_N32G45x) += -mcpu=cortex-m4 -Ilib/n32g45x/include +CFLAGS-$(CONFIG_MACH_STM32F1) += -Ilib/stm32f1/include CFLAGS-$(CONFIG_MACH_STM32F2) += -mcpu=cortex-m3 -Ilib/stm32f2/include CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include CFLAGS-$(CONFIG_MACH_STM32G0) += -mcpu=cortex-m0plus -Ilib/stm32g0/include +CFLAGS-$(CONFIG_MACH_STM32G4) += -mcpu=cortex-m4 -Ilib/stm32g4/include CFLAGS-$(CONFIG_MACH_STM32H7) += -mcpu=cortex-m7 -Ilib/stm32h7/include CFLAGS-$(CONFIG_MACH_STM32L4) += -mcpu=cortex-m4 -Ilib/stm32l4/include CFLAGS += $(CFLAGS-y) -D$(MCU_UPPER) -mthumb -Ilib/cmsis-core -Ilib/fast-hash @@ -29,15 +34,18 @@ CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld $(OUT)klipper.elf: $(OUT)src/generic/armcm_link.ld # Add source files -src-y += stm32/watchdog.c stm32/gpio.c stm32/clockline.c generic/crc16_ccitt.c +src-y += stm32/watchdog.c stm32/gpio.c stm32/clockline.c stm32/dfu_reboot.c +src-y += generic/crc16_ccitt.c src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c src-$(CONFIG_MACH_STM32F0) += ../lib/stm32f0/system_stm32f0xx.c src-$(CONFIG_MACH_STM32F0) += generic/timer_irq.c stm32/stm32f0_timer.c src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0.c stm32/gpioperiph.c src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0_adc.c stm32/stm32f0_i2c.c -src-$(CONFIG_MACH_STM32F1) += ../lib/stm32f1/system_stm32f1xx.c -src-$(CONFIG_MACH_STM32F1) += stm32/stm32f1.c generic/armcm_timer.c -src-$(CONFIG_MACH_STM32F1) += stm32/adc.c stm32/i2c.c +src-$(CONFIG_MACH_STM32F103) += ../lib/stm32f1/system_stm32f1xx.c +src-$(CONFIG_MACH_STM32F103) += stm32/adc.c +src-$(CONFIG_MACH_N32G45x) += ../lib/stm32f1/system_stm32f1xx.c +src-$(CONFIG_MACH_N32G45x) += ../lib/n32g45x/n32g45x_adc.c stm32/n32g45x_adc.c +src-$(CONFIG_MACH_STM32F1) += stm32/stm32f1.c generic/armcm_timer.c stm32/i2c.c src-$(CONFIG_MACH_STM32F2) += ../lib/stm32f2/system_stm32f2xx.c src-$(CONFIG_MACH_STM32F2) += stm32/stm32f4.c generic/armcm_timer.c src-$(CONFIG_MACH_STM32F2) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c @@ -47,9 +55,14 @@ src-$(CONFIG_MACH_STM32F4) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c src-$(CONFIG_MACH_STM32G0) += generic/timer_irq.c stm32/stm32f0_timer.c src-$(CONFIG_MACH_STM32G0) += stm32/stm32g0.c stm32/gpioperiph.c src-$(CONFIG_MACH_STM32G0) += stm32/stm32f0_adc.c stm32/stm32f0_i2c.c +src-$(CONFIG_MACH_STM32G4) += ../lib/stm32g4/system_stm32g4xx.c +src-$(CONFIG_MACH_STM32G4) += stm32/stm32g4.c generic/armcm_timer.c +src-$(CONFIG_MACH_STM32G4) += stm32/gpioperiph.c stm32/stm32h7_adc.c +src-$(CONFIG_MACH_STM32G4) += stm32/stm32f0_i2c.c src-$(CONFIG_MACH_STM32H7) += ../lib/stm32h7/system_stm32h7xx.c src-$(CONFIG_MACH_STM32H7) += stm32/stm32h7.c generic/armcm_timer.c src-$(CONFIG_MACH_STM32H7) += stm32/gpioperiph.c stm32/stm32h7_adc.c +src-$(CONFIG_MACH_STM32H7) += stm32/stm32f0_i2c.c src-$(CONFIG_MACH_STM32L4) += ../lib/stm32l4/system_stm32l4xx.c src-$(CONFIG_MACH_STM32L4) += stm32/stm32l4.c generic/armcm_timer.c src-$(CONFIG_MACH_STM32L4) += stm32/gpioperiph.c @@ -57,12 +70,15 @@ src-$(CONFIG_MACH_STM32L4) += stm32/stm32h7_adc.c stm32/stm32f0_i2c.c spi-src-y := stm32/spi.c spi-src-$(CONFIG_MACH_STM32H7) := stm32/stm32h7_spi.c src-$(CONFIG_HAVE_GPIO_SPI) += $(spi-src-y) +sdio-src-y := stm32/sdio.c +src-$(CONFIG_HAVE_GPIO_SDIO) += $(sdio-src-y) usb-src-$(CONFIG_HAVE_STM32_USBFS) := stm32/usbfs.c usb-src-$(CONFIG_HAVE_STM32_USBOTG) := stm32/usbotg.c src-$(CONFIG_USBSERIAL) += $(usb-src-y) stm32/chipid.c generic/usb_cdc.c serial-src-y := stm32/serial.c serial-src-$(CONFIG_MACH_STM32F0) := stm32/stm32f0_serial.c serial-src-$(CONFIG_MACH_STM32G0) := stm32/stm32f0_serial.c +serial-src-$(CONFIG_MACH_STM32G4) := stm32/stm32f0_serial.c serial-src-$(CONFIG_MACH_STM32H7) := stm32/stm32f0_serial.c src-$(CONFIG_SERIAL) += $(serial-src-y) generic/serial_irq.c canbus-src-y := generic/canserial.c ../lib/fast-hash/fasthash.c @@ -87,7 +103,7 @@ lib/hidflash/hid-flash: flash: $(OUT)klipper.bin lib/hidflash/hid-flash @echo " Flashing $< to $(FLASH_DEVICE)" - $(Q)$(PYTHON) ./scripts/flash_usb.py -t $(CONFIG_MCU) -d "$(FLASH_DEVICE)" -s "$(CONFIG_FLASH_START)" $(if $(NOSUDO),--no-sudo) $(OUT)klipper.bin + $(Q)$(PYTHON) ./scripts/flash_usb.py -t $(CONFIG_MCU) -d "$(FLASH_DEVICE)" -s "$(CONFIG_FLASH_APPLICATION_ADDRESS)" $(if $(NOSUDO),--no-sudo) $(OUT)klipper.bin serialflash: $(OUT)klipper.bin @echo " Flashing $< to $(FLASH_DEVICE) via stm32flash" diff --git a/src/stm32/can.c b/src/stm32/can.c index 665338ad7ef1..dc9153282090 100644 --- a/src/stm32/can.c +++ b/src/stm32/can.c @@ -49,6 +49,7 @@ #if CONFIG_MACH_STM32F0 #define SOC_CAN CAN + #define FILTER_CAN CAN #define CAN_RX0_IRQn CEC_CAN_IRQn #define CAN_RX1_IRQn CEC_CAN_IRQn #define CAN_TX_IRQn CEC_CAN_IRQn @@ -58,6 +59,7 @@ #if CONFIG_MACH_STM32F1 #define SOC_CAN CAN1 + #define FILTER_CAN CAN1 #define CAN_RX0_IRQn CAN1_RX0_IRQn #define CAN_RX1_IRQn CAN1_RX1_IRQn #define CAN_TX_IRQn CAN1_TX_IRQn @@ -69,12 +71,14 @@ #if (CONFIG_STM32_CANBUS_PA11_PA12 || CONFIG_STM32_CANBUS_PB8_PB9 \ || CONFIG_STM32_CANBUS_PD0_PD1 || CONFIG_STM32_CANBUS_PI9_PH13) #define SOC_CAN CAN1 + #define FILTER_CAN CAN1 #define CAN_RX0_IRQn CAN1_RX0_IRQn #define CAN_RX1_IRQn CAN1_RX1_IRQn #define CAN_TX_IRQn CAN1_TX_IRQn #define CAN_SCE_IRQn CAN1_SCE_IRQn #elif CONFIG_STM32_CANBUS_PB5_PB6 || CONFIG_STM32_CANBUS_PB12_PB13 #define SOC_CAN CAN2 + #define FILTER_CAN CAN1 #define CAN_RX0_IRQn CAN2_RX0_IRQn #define CAN_RX1_IRQn CAN2_RX1_IRQn #define CAN_TX_IRQn CAN2_TX_IRQn @@ -92,7 +96,7 @@ // Transmit a packet int -canbus_send(struct canbus_msg *msg) +canhw_send(struct canbus_msg *msg) { uint32_t tsr = SOC_CAN->TSR; if (!(tsr & (CAN_TSR_TME0|CAN_TSR_TME1|CAN_TSR_TME2))) { @@ -129,34 +133,39 @@ canbus_send(struct canbus_msg *msg) // Setup the receive packet filter void -canbus_set_filter(uint32_t id) +canhw_set_filter(uint32_t id) { + CAN_TypeDef *fcan = FILTER_CAN; /* Select the start slave bank */ - SOC_CAN->FMR |= CAN_FMR_FINIT; + uint32_t fmr = fcan->FMR; + if (FILTER_CAN != SOC_CAN) + // Using CAN2 with filter on CAN1 - assign CAN2 to first filter + fmr &= ~CAN_FMR_CAN2SB; + fcan->FMR = fmr | CAN_FMR_FINIT; /* Initialisation mode for the filter */ - SOC_CAN->FA1R = 0; + fcan->FA1R = 0; if (CONFIG_CANBUS_FILTER) { uint32_t mask = CAN_TI0R_STID | CAN_TI0R_IDE | CAN_TI0R_RTR; - SOC_CAN->sFilterRegister[0].FR1 = CANBUS_ID_ADMIN << CAN_RI0R_STID_Pos; - SOC_CAN->sFilterRegister[0].FR2 = mask; - SOC_CAN->sFilterRegister[1].FR1 = (id + 1) << CAN_RI0R_STID_Pos; - SOC_CAN->sFilterRegister[1].FR2 = mask; - SOC_CAN->sFilterRegister[2].FR1 = id << CAN_RI0R_STID_Pos; - SOC_CAN->sFilterRegister[2].FR2 = mask; + fcan->sFilterRegister[0].FR1 = CANBUS_ID_ADMIN << CAN_RI0R_STID_Pos; + fcan->sFilterRegister[0].FR2 = mask; + fcan->sFilterRegister[1].FR1 = (id + 1) << CAN_RI0R_STID_Pos; + fcan->sFilterRegister[1].FR2 = mask; + fcan->sFilterRegister[2].FR1 = id << CAN_RI0R_STID_Pos; + fcan->sFilterRegister[2].FR2 = mask; } else { - SOC_CAN->sFilterRegister[0].FR1 = 0; - SOC_CAN->sFilterRegister[0].FR2 = 0; + fcan->sFilterRegister[0].FR1 = 0; + fcan->sFilterRegister[0].FR2 = 0; id = 0; } /* 32-bit scale for the filter */ - SOC_CAN->FS1R = (1<<0) | (1<<1) | (1<<2); + fcan->FS1R = (1<<0) | (1<<1) | (1<<2); /* Filter activation */ - SOC_CAN->FA1R = (1<<0) | (id ? (1<<1) | (1<<2) : 0); + fcan->FA1R = (1<<0) | (id ? (1<<1) | (1<<2) : 0); /* Leave the initialisation mode for the filter */ - SOC_CAN->FMR &= ~CAN_FMR_FINIT; + fcan->FMR = fmr & ~CAN_FMR_FINIT; } // This function handles CAN global interrupts @@ -241,7 +250,11 @@ compute_btr(uint32_t pclock, uint32_t bitrate) void can_init(void) { + // Enable clock enable_pclock((uint32_t)SOC_CAN); + if (FILTER_CAN != SOC_CAN) + // Also enable CAN1 clock if using CAN2 with filter on CAN1 + enable_pclock((uint32_t)FILTER_CAN); gpio_peripheral(GPIO_Rx, CAN_FUNCTION, 1); gpio_peripheral(GPIO_Tx, CAN_FUNCTION, 0); @@ -268,7 +281,7 @@ can_init(void) ; /*##-2- Configure the CAN Filter #######################################*/ - canbus_set_filter(0); + canhw_set_filter(0); /*##-3- Configure Interrupts #################################*/ armcm_enable_irq(CAN_IRQHandler, CAN_RX0_IRQn, 0); diff --git a/src/stm32/dfu_reboot.c b/src/stm32/dfu_reboot.c new file mode 100644 index 000000000000..68f023d17a3a --- /dev/null +++ b/src/stm32/dfu_reboot.c @@ -0,0 +1,57 @@ +// Reboot into stm32 ROM dfu bootloader +// +// Copyright (C) 2019-2022 Kevin O'Connor +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "internal.h" // NVIC_SystemReset +#include "board/irq.h" // irq_disable + +// Many stm32 chips have a USB capable "DFU bootloader" in their ROM. +// In order to invoke that bootloader it is necessary to reset the +// chip and jump to a chip specific hardware address. +// +// To reset the chip, the dfu_reboot() code sets a flag in memory (at +// an arbitrary position that is unlikely to be overwritten during a +// chip reset), and resets the chip. If dfu_reboot_check() sees that +// flag on the next boot it will perform a code jump to the ROM +// address. + +// Location of ram address to set internal flag +#if CONFIG_MACH_STM32H7 + #define USB_BOOT_FLAG_ADDR (0x24000000 + 0x8000) // Place flag in "AXI SRAM" +#else + #define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024) +#endif + +// Signature to set in memory to flag that a dfu reboot is requested +#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT" + +// Flag that bootloader is desired and reboot +void +dfu_reboot(void) +{ + if (!CONFIG_STM32_DFU_ROM_ADDRESS || !CONFIG_HAVE_BOOTLOADER_REQUEST) + return; + irq_disable(); + uint64_t *bflag = (void*)USB_BOOT_FLAG_ADDR; + *bflag = USB_BOOT_FLAG; +#if CONFIG_MACH_STM32H7 + SCB_CleanDCache_by_Addr((void*)bflag, sizeof(*bflag)); +#endif + NVIC_SystemReset(); +} + +// Check if rebooting into system DFU Bootloader +void +dfu_reboot_check(void) +{ + if (!CONFIG_STM32_DFU_ROM_ADDRESS || !CONFIG_HAVE_BOOTLOADER_REQUEST) + return; + if (*(uint64_t*)USB_BOOT_FLAG_ADDR != USB_BOOT_FLAG) + return; + *(uint64_t*)USB_BOOT_FLAG_ADDR = 0; + uint32_t *sysbase = (uint32_t*)CONFIG_STM32_DFU_ROM_ADDRESS; + asm volatile("mov sp, %0\n bx %1" + : : "r"(sysbase[0]), "r"(sysbase[1])); +} diff --git a/src/stm32/fdcan.c b/src/stm32/fdcan.c index 7b81bb6faf32..9198c7dc002f 100644 --- a/src/stm32/fdcan.c +++ b/src/stm32/fdcan.c @@ -22,6 +22,10 @@ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA11,PA12"); #define GPIO_Rx GPIO('A', 11) #define GPIO_Tx GPIO('A', 12) +#elif CONFIG_STM32_CANBUS_PA11_PB9 + DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA11,PB9"); + #define GPIO_Rx GPIO('A', 11) + #define GPIO_Tx GPIO('B', 9) #elif CONFIG_STM32_CANBUS_PB8_PB9 DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9"); #define GPIO_Rx GPIO('B', 8) @@ -42,9 +46,14 @@ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3"); #define GPIO_Rx GPIO('C', 2) #define GPIO_Tx GPIO('C', 3) +#elif CONFIG_STM32_CANBUS_PB12_PB13 + DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13"); + #define GPIO_Rx GPIO('B', 12) + #define GPIO_Tx GPIO('B', 13) #endif -#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3) +#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3 \ + || CONFIG_STM32_CANBUS_PB12_PB13) #define SOC_CAN FDCAN1 #define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1) #else @@ -55,7 +64,7 @@ #if CONFIG_MACH_STM32G0 #define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn #define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number -#elif CONFIG_MACH_STM32H7 +#elif CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4 #define CAN_IT0_IRQn FDCAN1_IT0_IRQn #define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number #endif @@ -97,7 +106,7 @@ struct fdcan_ram_layout { // Transmit a packet int -canbus_send(struct canbus_msg *msg) +canhw_send(struct canbus_msg *msg) { uint32_t txfqs = SOC_CAN->TXFQS; if (txfqs & FDCAN_TXFQS_TFQF) @@ -132,7 +141,7 @@ can_filter(uint32_t index, uint32_t id) // Setup the receive packet filter void -canbus_set_filter(uint32_t id) +canhw_set_filter(uint32_t id) { if (!CONFIG_CANBUS_FILTER) return; @@ -152,7 +161,7 @@ canbus_set_filter(uint32_t id) #if CONFIG_MACH_STM32G0 SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos | 0x02 << FDCAN_RXGFC_ANFS_Pos); -#elif CONFIG_MACH_STM32H7 +#elif CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4 uint32_t flssa = (uint32_t)MSG_RAM.FLS - SRAMCAN_BASE; SOC_CAN->SIDFC = flssa | ((id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos); SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos; @@ -280,7 +289,7 @@ can_init(void) SOC_CAN->NBTP = btr; -#if CONFIG_MACH_STM32H7 +#if CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4 /* Setup message RAM addresses */ uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - SRAMCAN_BASE; SOC_CAN->RXF0C = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << FDCAN_RXF0C_F0S_Pos); @@ -295,7 +304,7 @@ can_init(void) SOC_CAN->CCCR &= ~FDCAN_CCCR_INIT; /*##-2- Configure the CAN Filter #######################################*/ - canbus_set_filter(0); + canhw_set_filter(0); /*##-3- Configure Interrupts #################################*/ armcm_enable_irq(CAN_IRQHandler, CAN_IT0_IRQn, 1); diff --git a/src/stm32/gpioperiph.c b/src/stm32/gpioperiph.c index 06cdaa0550f8..ef421c772006 100644 --- a/src/stm32/gpioperiph.c +++ b/src/stm32/gpioperiph.c @@ -6,7 +6,7 @@ #include "internal.h" // gpio_peripheral -// Set the mode and extended function of a pin +// Set the mode, extended function and speed of a pin void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) { @@ -16,7 +16,8 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) gpio_clock_enable(regs); // Configure GPIO - uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8; + uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf; + uint32_t od = (mode >> 8) & 0x1, hs = (mode >> 9) & 0x1; uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0; uint32_t pos = gpio % 16, af_reg = pos / 8; uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift; @@ -33,6 +34,6 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup) // stm32f4 is ~50Mhz at 40pF // stm32g0 is ~30Mhz at 50pF // stm32h7 is ~85Mhz at 50pF - uint32_t ospeed = CONFIG_MACH_STM32F0 ? 0x01 : 0x02; + uint32_t ospeed = hs ? 0x03 : (CONFIG_MACH_STM32F0 ? 0x01 : 0x02); regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (ospeed << m_shift); } diff --git a/src/stm32/hard_pwm.c b/src/stm32/hard_pwm.c index 449de8b9ba63..a15b1c375568 100644 --- a/src/stm32/hard_pwm.c +++ b/src/stm32/hard_pwm.c @@ -20,7 +20,7 @@ struct gpio_pwm_info { }; static const struct gpio_pwm_info pwm_regs[] = { -#if CONFIG_MACH_STM32F103 +#if CONFIG_MACH_STM32F1 {TIM2, GPIO('A', 0), 1, GPIO_FUNCTION(2)}, {TIM2, GPIO('A', 1), 2, GPIO_FUNCTION(2)}, {TIM2, GPIO('A', 2), 3, GPIO_FUNCTION(2)}, @@ -117,10 +117,12 @@ static const struct gpio_pwm_info pwm_regs[] = { {TIM1, GPIO('B', 3), 2, GPIO_FUNCTION(1)}, {TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)}, {TIM3, GPIO('B', 5), 2, GPIO_FUNCTION(1)}, + #if CONFIG_MACH_STM32G0Bx {TIM4, GPIO('B', 6), 1, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 7), 2, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 8), 3, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 9), 4, GPIO_FUNCTION(9)}, + #endif {TIM15, GPIO('B', 14), 1, GPIO_FUNCTION(5)}, {TIM15, GPIO('B', 15), 2, GPIO_FUNCTION(5)}, {TIM15, GPIO('C', 1), 1, GPIO_FUNCTION(2)}, @@ -134,10 +136,12 @@ static const struct gpio_pwm_info pwm_regs[] = { {TIM14, GPIO('C', 12), 1, GPIO_FUNCTION(2)}, {TIM16, GPIO('D', 0), 1, GPIO_FUNCTION(2)}, {TIM17, GPIO('D', 1), 1, GPIO_FUNCTION(2)}, + #if CONFIG_MACH_STM32G0Bx {TIM4, GPIO('D', 12), 1, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 13), 2, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 14), 3, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 15), 4, GPIO_FUNCTION(2)}, + #endif {TIM3, GPIO('E', 3), 1, GPIO_FUNCTION(1)}, {TIM3, GPIO('E', 4), 2, GPIO_FUNCTION(1)}, {TIM3, GPIO('E', 5), 3, GPIO_FUNCTION(1)}, diff --git a/src/stm32/internal.h b/src/stm32/internal.h index 38d005aef66d..0422bf65aedc 100644 --- a/src/stm32/internal.h +++ b/src/stm32/internal.h @@ -14,6 +14,8 @@ #include "stm32f4xx.h" #elif CONFIG_MACH_STM32G0 #include "stm32g0xx.h" +#elif CONFIG_MACH_STM32G4 +#include "stm32g4xx.h" #elif CONFIG_MACH_STM32H7 #include "stm32h7xx.h" #elif CONFIG_MACH_STM32L4 @@ -30,6 +32,7 @@ extern GPIO_TypeDef * const digital_regs[]; #define GPIO_INPUT 0 #define GPIO_OUTPUT 1 #define GPIO_OPEN_DRAIN 0x100 +#define GPIO_HIGH_SPEED 0x200 #define GPIO_FUNCTION(fn) (2 | ((fn) << 4)) #define GPIO_ANALOG 3 void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup); @@ -38,6 +41,10 @@ void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup); void enable_pclock(uint32_t periph_base); int is_enabled_pclock(uint32_t periph_base); +// dfu_reboot.c +void dfu_reboot(void); +void dfu_reboot_check(void); + // stm32??.c struct cline { volatile uint32_t *en, *rst; uint32_t bit; }; struct cline lookup_clock_line(uint32_t periph_base); diff --git a/src/stm32/n32g45x_adc.c b/src/stm32/n32g45x_adc.c new file mode 100644 index 000000000000..d27e70c9e445 --- /dev/null +++ b/src/stm32/n32g45x_adc.c @@ -0,0 +1,185 @@ +// ADC functions on N32G45x +// +// Copyright (C) 2022-2023 Alexey Golyshin +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "board/irq.h" // irq_save +#include "board/misc.h" // timer_from_us +#include "command.h" // shutdown +#include "compiler.h" // ARRAY_SIZE +#include "generic/armcm_timer.h" // udelay +#include "gpio.h" // gpio_adc_setup +#include "internal.h" // GPIO +#include "sched.h" // sched_shutdown +#include "n32g45x_adc.h" // ADC + +DECL_CONSTANT("ADC_MAX", 4095); + +#define ADC_TEMPERATURE_PIN 0xfe +DECL_ENUMERATION("pin", "ADC_TEMPERATURE", ADC_TEMPERATURE_PIN); + +static const uint8_t adc_pins[] = { + // ADC1 + 0, GPIO('A', 0), GPIO('A', 1), GPIO('A', 6), + GPIO('A', 3), GPIO('F', 4), 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + ADC_TEMPERATURE_PIN, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + // ADC2 + 0, GPIO('A', 4), GPIO('A', 5), GPIO('B', 1), + GPIO('A', 7), GPIO('C', 4), GPIO('C', 0), GPIO('C', 1), + GPIO('C', 2), GPIO('C', 3), GPIO('F', 2), GPIO('A', 2), + GPIO('C', 5), GPIO('B', 2), 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +#if CONFIG_MACH_N32G455 // ADC3/4 for G455 only + // ADC3 + 0, GPIO('B', 11), GPIO('E', 9), GPIO('E', 13), + GPIO('E', 12), GPIO('B', 13), GPIO('E', 8), GPIO('D', 10), + GPIO('D', 11), GPIO('D', 12), GPIO('D', 13), GPIO('D', 14), + GPIO('B', 0), GPIO('E', 7), GPIO('E', 10), GPIO('E', 11), + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + // ADC4 + 0, GPIO('E', 14), GPIO('E', 15), GPIO('B', 12), + GPIO('B', 14), GPIO('B', 15), 0, 0, + 0, 0, 0, 0, + GPIO('D', 8), GPIO('D', 9), 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +#endif +}; + +// Perform calibration +static void +adc_calibrate(ADC_Module *adc) +{ + adc->CTRL2 = CTRL2_AD_ON_SET; + while (!(adc->CTRL3 & ADC_FLAG_RDY)) + ; + adc->CTRL3 &= (~ADC_CTRL3_BPCAL_MSK); + udelay(10); + adc->CTRL2 = CTRL2_AD_ON_SET | CTRL2_CAL_SET; + while (adc->CTRL2 & CTRL2_CAL_SET) + ; +} + +struct gpio_adc +gpio_adc_setup(uint32_t pin) +{ + // Find pin in adc_pins table + int chan; + for (chan=0; ; chan++) { + if (chan >= ARRAY_SIZE(adc_pins)) + shutdown("Not a valid ADC pin"); + if (adc_pins[chan] == pin) + break; + } + + // Determine which ADC block to use + ADC_Module *adc; + if ((chan >> 5) == 0) + adc = NS_ADC1; + if ((chan >> 5) == 1) + adc = NS_ADC2; + if ((chan >> 5) == 2) + adc = NS_ADC3; + if ((chan >> 5) == 3) + adc = NS_ADC4; + chan &= 0x1F; + + // Enable the ADC + uint32_t reg_temp; + reg_temp = ADC_RCC_AHBPCLKEN; + reg_temp |= (RCC_AHB_PERIPH_ADC1 | RCC_AHB_PERIPH_ADC2 | + RCC_AHB_PERIPH_ADC3 | RCC_AHB_PERIPH_ADC4); + ADC_RCC_AHBPCLKEN = reg_temp; + + reg_temp = ADC_RCC_CFG2; + reg_temp &= CFG2_ADCPLLPRES_RESET_MASK; + reg_temp |= RCC_ADCPLLCLK_DIV1; + reg_temp &= RCC_ADCPLLCLK_DISABLE; + ADC_RCC_CFG2 = reg_temp; + + reg_temp = ADC_RCC_CFG2; + reg_temp &= CFG2_ADCHPRES_RESET_MASK; + reg_temp |= RCC_ADCHCLK_DIV16; + ADC_RCC_CFG2 = reg_temp; + + ADC_InitType ADC_InitStructure; + ADC_InitStructure.WorkMode = ADC_WORKMODE_INDEPENDENT; + ADC_InitStructure.MultiChEn = 0; + ADC_InitStructure.ContinueConvEn = 0; + ADC_InitStructure.ExtTrigSelect = ADC_EXT_TRIGCONV_NONE; + ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R; + ADC_InitStructure.ChsNumber = 1; + ADC_Init(adc, &ADC_InitStructure); + + adc_calibrate(adc); + + if (pin == ADC_TEMPERATURE_PIN) { + NS_ADC1->CTRL2 |= CTRL2_TSVREFE_SET; + VREF1P2_CTRL |= (1<<10); + } else { + gpio_peripheral(pin, GPIO_ANALOG, 0); + } + + return (struct gpio_adc){ .adc = adc, .chan = chan }; +} + +// Try to sample a value. Returns zero if sample ready, otherwise +// returns the number of clock ticks the caller should wait before +// retrying this function. +uint32_t +gpio_adc_sample(struct gpio_adc g) +{ + ADC_Module *adc = g.adc; + uint32_t sr = adc->STS; + if (sr & ADC_STS_STR) { + if (!(sr & ADC_STS_ENDC) || adc->RSEQ3 != g.chan) + // Conversion still in progress or busy on another channel + goto need_delay; + // Conversion ready + return 0; + } + // ADC timing: clock=4Mhz, Tconv=12.5, Tsamp=41.5, total=13.500us + ADC_ConfigRegularChannel(adc, g.chan, 1, ADC_SAMP_TIME_41CYCLES5); + adc->CTRL2 |= CTRL2_AD_ON_SET; + adc->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET; + +need_delay: + return timer_from_us(20); +} + +// Read a value; use only after gpio_adc_sample() returns zero +uint16_t +gpio_adc_read(struct gpio_adc g) +{ + ADC_Module *adc = g.adc; + adc->STS &= ~ADC_STS_ENDC; + adc->STS &= ~ADC_STS_STR; + adc->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET; + uint16_t result = adc->DAT; + return result; +} + +// Cancel a sample that may have been started with gpio_adc_sample() +void +gpio_adc_cancel_sample(struct gpio_adc g) +{ + ADC_Module *adc = g.adc; + irqstatus_t flag = irq_save(); + if (adc->STS & ADC_STS_STR) + gpio_adc_read(g); + irq_restore(flag); +} diff --git a/src/stm32/sdio.c b/src/stm32/sdio.c new file mode 100644 index 000000000000..c64bca383c86 --- /dev/null +++ b/src/stm32/sdio.c @@ -0,0 +1,414 @@ +// SDIO functions on STM32 +// +// Copyright (C) 2022 H. Gregor Molter +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "board/io.h" // readb, writeb +#include "command.h" // shutdown +#include "sdio.h" // sdio_setup +#include "internal.h" // gpio_peripheral +#include "sched.h" // sched_shutdown +#include "generic/armcm_timer.h" // udelay + +struct sdio_info { + SDIO_TypeDef *sdio; + uint8_t clk_pin, cmd_pin, dat0_pin, dat1_pin, dat2_pin, dat3_pin, function; +}; + +enum { + SDIO_OK = 0, + SDIO_ERROR = 1, + SDIO_TIMEOUT = 2, + SDIO_CMD_RESPONSE_TIMEOUT = 3, + SDIO_CRC_FAIL = 4, + SDIO_WRONG_CMD_RESPONSE = 5, + SDIO_WRONG_BLOCKSIZE = 6, + SDIO_DATA_TIMEOUT = 7, + SDIO_READ_OVERRUN = 8, + SDIO_WRITE_UNDERRUN = 9, + SDIO_NO_DATA_MEMORY = 10, +}; + +enum { + SDIO_CARDVER_UNKNOWN = 0, + SDIO_CARDVER_1X = 1, + SDIO_CARDVER_2X = 2 +}; + +enum { + SDIO_CARDTYPE_UNKNOWN = 0, + SDIO_CARDTYPE_SDHC_SDXC = 1, + SDIO_CARDTYPE_SDSC = 2 +}; + +enum { + SDIO_WAIT_NO_RESPONSE = 0, + SDIO_WAIT_SHORT_RESPONSE = 1, + SDIO_WAIT_LONG_RESPONSE = 2 +}; + +// PINS: CLK -> PC12 , CMD -> PD2, +// DAT0 -> PC8, DAT1 -> PC9, DAT2 -> PC10, DAT3 -> PC11 +DECL_ENUMERATION("sdio_bus", "sdio", 0); +DECL_CONSTANT_STR("BUS_PINS_sdio", "PC12,PD2,PC8,PC9,PC10,PC11"); + +#define SDIO_FUNCTION GPIO_FUNCTION(12) + +static const struct sdio_info sdio_bus[] = { + { SDIO, GPIO('C', 12), GPIO('D', 2), GPIO('C', 8), + GPIO('C', 9), GPIO('C', 10), GPIO('C', 11), SDIO_FUNCTION }, +}; + +#define SDIO_CLK_FREQ 48000000 +#define SDIO_INIT_CLK 400000 +#define SDIO_MAX_TIMEOUT 500 // Wait for at least 500ms before a timeout occurs +#define CLKCR_CLEAR_MASK (SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV | \ + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS | SDIO_CLKCR_NEGEDGE | \ + SDIO_CLKCR_HWFC_EN) +#define DCTRL_CLEAR_MASK (SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR | \ + SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE) +#define CMD_CLEAR_MASK (SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP | \ + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND | SDIO_CMD_CPSMEN | \ + SDIO_CMD_SDIOSUSPEND) +#define SDIO_CLOCK_BYPASS_DISABLE 0 +#define SDIO_CLOCK_EDGE_RISING 0 +#define SDIO_CLOCK_POWER_SAVE_DISABLE 0 +#define SDIO_BUS_WIDE_1B 0 +#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 +#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0 +#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN +#define SDIO_CMD_FLAGS (SDIO_STA_CCRCFAIL | SDIO_STA_CTIMEOUT | \ + SDIO_STA_CMDREND | SDIO_STA_CMDSENT) +#define SDIO_STATIC_FLAGS (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | \ + SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT | SDIO_STA_TXUNDERR | \ + SDIO_STA_RXOVERR | SDIO_STA_CMDREND | SDIO_STA_CMDSENT | \ + SDIO_STA_DATAEND | SDIO_STA_DBCKEND | SDIO_STA_SDIOIT) + +struct sdio_config +sdio_setup(uint32_t bus) +{ + if (bus >= ARRAY_SIZE(sdio_bus)) + shutdown("Invalid sdio bus"); + + // Enable SDIO + SDIO_TypeDef *sdio = sdio_bus[bus].sdio; + if (!is_enabled_pclock((uint32_t)sdio)) { + // Enable clock + enable_pclock((uint32_t)sdio); + // Initialize pins + gpio_peripheral( + sdio_bus[bus].dat0_pin, sdio_bus[bus].function|GPIO_HIGH_SPEED, 1); + gpio_peripheral( + sdio_bus[bus].dat1_pin, sdio_bus[bus].function|GPIO_HIGH_SPEED, 1); + gpio_peripheral( + sdio_bus[bus].dat2_pin, sdio_bus[bus].function|GPIO_HIGH_SPEED, 1); + gpio_peripheral( + sdio_bus[bus].dat3_pin, sdio_bus[bus].function|GPIO_HIGH_SPEED, 1); + gpio_peripheral( + sdio_bus[bus].cmd_pin, sdio_bus[bus].function|GPIO_HIGH_SPEED, 1); + gpio_peripheral( + sdio_bus[bus].clk_pin, sdio_bus[bus].function|GPIO_HIGH_SPEED, 1); + } + + struct sdio_config sdio_config = { .sdio = sdio }; + + // Setup SDIO with 1 bit width first and slow clock ~400 kHz + sdio_set_speed(sdio_config, SDIO_INIT_CLK); + + // Disable clk + CLEAR_BIT(sdio->CLKCR, SDIO_CLKCR_CLKEN); + // Set power state to _on_ + sdio->POWER = SDIO_POWER_PWRCTRL; + // Wait for 2ms (standard: at least 1ms) to settle + udelay(2000); + // Enable Clk + SET_BIT(sdio->CLKCR, SDIO_CLKCR_CLKEN); + + return sdio_config; +} + +uint32_t +sdio_get_cmd_error(struct sdio_config sdio, uint32_t flags) +{ + SDIO_TypeDef *regs = sdio.sdio; + + // wait for a timeout (max. SDIO_MAX_TIMEOUT) in msec. + // 8 cycles is the instruction cycles for the loop below. + uint32_t sta; + uint32_t count = SDIO_MAX_TIMEOUT * (SystemCoreClock / 8U / 1000U); + do { + if (count-- == 0) { + return SDIO_TIMEOUT; + } + sta = regs->STA; + } while ((sta & flags) == 0 || (sta & SDIO_STA_CMDACT) != 0); + + regs->ICR = SDIO_CMD_FLAGS; + + if (sta & SDIO_STA_CTIMEOUT) { + return SDIO_CMD_RESPONSE_TIMEOUT; + } + if (sta & SDIO_STA_CCRCFAIL) { + return SDIO_CRC_FAIL; + } + + return SDIO_OK; +} + +uint8_t +sdio_send_command(struct sdio_config sdio_config, uint8_t cmd, + uint32_t argument, uint8_t wait, uint8_t *response_data, + uint8_t *response_data_len) +{ + SDIO_TypeDef *sdio = sdio_config.sdio; + uint32_t wait_flags = 0; // valid for SDIO_WAIT_NO_RESPONSE + uint32_t sta_flags = (wait == SDIO_WAIT_NO_RESPONSE) ? + SDIO_STA_CMDSENT : SDIO_STA_CCRCFAIL | SDIO_STA_CMDREND | \ + SDIO_STA_CTIMEOUT; + + if (wait == SDIO_WAIT_SHORT_RESPONSE) { + wait_flags = SDIO_CMD_WAITRESP_0; + } else if (wait == SDIO_WAIT_LONG_RESPONSE) { + wait_flags = SDIO_CMD_WAITRESP; + } + + // Step 1: Send command and argument + // CMD and State Machine enabled. + // Wait for response like specified by wait_flags. + uint32_t cmdreg = (cmd & 0x3F) | wait_flags | SDIO_CMD_CPSMEN; + sdio->ARG = argument; + MODIFY_REG(sdio->CMD, CMD_CLEAR_MASK, cmdreg); + + // Step 2: Wait until response + // wait for a timeout (max. SDIO_MAX_TIMEOUT) in msec. + // 8 cycles is the instruction cycles for the loop below. + uint32_t sta; + uint32_t count = SDIO_MAX_TIMEOUT * (SystemCoreClock / 8U / 1000U); + do { + if (count-- == 0) { + return SDIO_TIMEOUT; + } + sta = sdio->STA; + } while ((sta & sta_flags) == 0 || (sta & SDIO_STA_CMDACT) != 0); + + sdio->ICR = SDIO_CMD_FLAGS; + + // Step 3: Store response_data and check for short and long responses + // timeout and crc. + if (response_data != NULL) { + if (wait == SDIO_WAIT_SHORT_RESPONSE) { + response_data[0] = (uint8_t) ((sdio->RESP1 >> 24) & 0xFF); + response_data[1] = (uint8_t) ((sdio->RESP1 >> 16) & 0xFF); + response_data[2] = (uint8_t) ((sdio->RESP1 >> 8) & 0xFF); + response_data[3] = (uint8_t) ((sdio->RESP1) & 0xFF); + *response_data_len = 4; + } else if (wait == SDIO_WAIT_LONG_RESPONSE) { + // TODO Inverse? + response_data[0] = (uint8_t) ((sdio->RESP1 >> 24) & 0xFF); + response_data[1] = (uint8_t) ((sdio->RESP1 >> 16) & 0xFF); + response_data[2] = (uint8_t) ((sdio->RESP1 >> 8) & 0xFF); + response_data[3] = (uint8_t) ((sdio->RESP1) & 0xFF); + response_data[4] = (uint8_t) ((sdio->RESP2 >> 24) & 0xFF); + response_data[5] = (uint8_t) ((sdio->RESP2 >> 16) & 0xFF); + response_data[6] = (uint8_t) ((sdio->RESP2 >> 8) & 0xFF); + response_data[7] = (uint8_t) ((sdio->RESP2) & 0xFF); + response_data[8] = (uint8_t) ((sdio->RESP3 >> 24) & 0xFF); + response_data[9] = (uint8_t) ((sdio->RESP3 >> 16) & 0xFF); + response_data[10] = (uint8_t) ((sdio->RESP3 >> 8) & 0xFF); + response_data[11] = (uint8_t) ((sdio->RESP3) & 0xFF); + response_data[12] = (uint8_t) ((sdio->RESP4 >> 24) & 0xFF); + response_data[13] = (uint8_t) ((sdio->RESP4 >> 16) & 0xFF); + response_data[14] = (uint8_t) ((sdio->RESP4 >> 8) & 0xFF); + response_data[15] = (uint8_t) ((sdio->RESP4) & 0xFF); + *response_data_len = 16; + } + } + + if (wait != SDIO_WAIT_NO_RESPONSE) { + // CTIMEOUT and CCRCFAIL check only for short or long responses. + if (sta & SDIO_STA_CTIMEOUT) { + return SDIO_CMD_RESPONSE_TIMEOUT; + } + if (sta & SDIO_STA_CCRCFAIL) { + return SDIO_CRC_FAIL; + } + } + + // Step 4: For a short response check the response cmd field, too. + if (wait == SDIO_WAIT_SHORT_RESPONSE) { + if (sdio->RESPCMD != cmd) { + return SDIO_WRONG_CMD_RESPONSE; + } + } + + return SDIO_OK; +} + +uint32_t +sdio_get_dctrl_blocksize(uint32_t value) +{ + switch(value) { + case 1: return 0U; + case 2: return SDIO_DCTRL_DBLOCKSIZE_0; + case 4: return SDIO_DCTRL_DBLOCKSIZE_1; + case 8: return SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_0; + case 16: return SDIO_DCTRL_DBLOCKSIZE_2; + case 32: return SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_0; + case 64: return SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_1; + case 128: return SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_1| \ + SDIO_DCTRL_DBLOCKSIZE_0; + case 256: return SDIO_DCTRL_DBLOCKSIZE_3; + case 512: return SDIO_DCTRL_DBLOCKSIZE_3|SDIO_DCTRL_DBLOCKSIZE_0; + case 1024: return SDIO_DCTRL_DBLOCKSIZE_3|SDIO_DCTRL_DBLOCKSIZE_1; + case 2048: return SDIO_DCTRL_DBLOCKSIZE_3|SDIO_DCTRL_DBLOCKSIZE_1| \ + SDIO_DCTRL_DBLOCKSIZE_0; + case 4096: return SDIO_DCTRL_DBLOCKSIZE_3|SDIO_DCTRL_DBLOCKSIZE_2; + case 8192: return SDIO_DCTRL_DBLOCKSIZE_3|SDIO_DCTRL_DBLOCKSIZE_2| \ + SDIO_DCTRL_DBLOCKSIZE_0; + case 16384: return SDIO_DCTRL_DBLOCKSIZE_3|SDIO_DCTRL_DBLOCKSIZE_2| \ + SDIO_DCTRL_DBLOCKSIZE_1; + } + return SDIO_DCTRL_DBLOCKSIZE_Msk; +} + +uint8_t +sdio_prepare_data_transfer(struct sdio_config sdio_config, uint8_t read, + uint32_t numblocks, uint32_t blocksize, uint32_t timeout) +{ + SDIO_TypeDef *sdio = sdio_config.sdio; + uint32_t dctrl_blocksize = sdio_get_dctrl_blocksize(blocksize); + uint32_t reg = dctrl_blocksize | ((read > 0) ? + SDIO_DCTRL_DTDIR : 0U) | SDIO_DCTRL_DTEN; + + if (dctrl_blocksize == SDIO_DCTRL_DBLOCKSIZE_Msk) + return SDIO_WRONG_BLOCKSIZE; + + sdio->DCTRL = 0; + sdio->DTIMER = timeout; + sdio->DLEN = numblocks*blocksize; + MODIFY_REG(sdio->DCTRL, DCTRL_CLEAR_MASK, reg); + return SDIO_OK; +} + +uint8_t +sdio_read_data(struct sdio_config sdio_config, uint8_t *data, + uint32_t numblocks, uint32_t blocksize) +{ + // Read data by polling + SDIO_TypeDef *sdio = sdio_config.sdio; + uint32_t data_remaining = numblocks*blocksize; + uint8_t *buf = data; + + if (data == NULL) { + return SDIO_NO_DATA_MEMORY; + } + + while ((sdio->STA & (SDIO_STA_RXOVERR | SDIO_STA_DCRCFAIL | + SDIO_STA_DTIMEOUT | SDIO_STA_DATAEND)) == 0) { + if ((sdio->STA & SDIO_STA_RXDAVL) != 0) { + uint32_t tmp = sdio->FIFO; + for (uint8_t i=0; (i<4) && (data_remaining>0); i++) { + *buf = (uint8_t)(tmp & 0xFF); + buf++; + data_remaining--; + tmp >>= 8U; + } + } + } + + uint32_t sta = sdio->STA; + sdio->ICR = SDIO_STATIC_FLAGS; + + if (sta & SDIO_STA_DTIMEOUT) { + return SDIO_DATA_TIMEOUT; + } + if (sta & SDIO_STA_DCRCFAIL) { + return SDIO_CRC_FAIL; + } + if (sta & SDIO_STA_RXOVERR) { + return SDIO_READ_OVERRUN; + } + + // Empty FIFO and clear flags again + while (((sdio->STA & SDIO_STA_RXDAVL) != 0) && (data_remaining > 0)) { + uint32_t tmp = sdio->FIFO; + for (uint8_t i=0; (i<4) && (data_remaining>0); i++) { + *buf = (uint8_t)(tmp & 0xFF); + buf++; + data_remaining--; + tmp >>= 8U; + } + } + + sdio->ICR = SDIO_STATIC_FLAGS; + return SDIO_OK; +} + +uint8_t +sdio_write_data(struct sdio_config sdio_config, uint8_t *data, + uint32_t numblocks, uint32_t blocksize) +{ + // Write data by polling + SDIO_TypeDef *sdio = sdio_config.sdio; + uint32_t data_remaining = numblocks*blocksize; + uint8_t *buf = data; + + if (data == NULL) { + return SDIO_NO_DATA_MEMORY; + } + + while ((sdio->STA & (SDIO_STA_TXUNDERR | SDIO_STA_DCRCFAIL | + SDIO_STA_DTIMEOUT | SDIO_STA_DATAEND)) == 0) { + if ((sdio->STA & SDIO_STA_TXFIFOF) == 0) { + uint32_t tmp = 0; + for (uint8_t i=0; (i<4) && (data_remaining>0); i++) { + tmp |= ((uint32_t)(*buf) << (i<<3)); + buf++; + data_remaining--; + } + sdio->FIFO = tmp; + } + } + + uint32_t sta = sdio->STA; + sdio->ICR = SDIO_STATIC_FLAGS; + + if (sta & SDIO_STA_DTIMEOUT) { + return SDIO_DATA_TIMEOUT; + } + if (sta & SDIO_STA_DCRCFAIL) { + return SDIO_CRC_FAIL; + } + if (sta & SDIO_STA_TXUNDERR) { + return SDIO_WRITE_UNDERRUN; + } + + return SDIO_OK; +} + +void +sdio_send_cmd(struct sdio_config sdio_config, uint8_t cmd, uint32_t argument, + uint8_t wait) +{ + SDIO_TypeDef *sdio = sdio_config.sdio; + + sdio->ARG = argument; + //CMD and State Machine enabled. Wait for response like specified. + uint32_t cmdreg = (cmd & 0x3F) | ((wait & 0xC0)) | SDIO_CMD_CPSMEN; + + MODIFY_REG(sdio->CMD, CMD_CLEAR_MASK, cmdreg); +} + +void +sdio_set_speed(struct sdio_config sdio_config, uint32_t speed) +{ + SDIO_TypeDef *sdio = sdio_config.sdio; + + uint8_t clkdiv = (SDIO_CLK_FREQ/speed)-2; + + uint32_t sdio_confreg = SDIO_CLOCK_EDGE_RISING | \ + SDIO_CLOCK_BYPASS_DISABLE | SDIO_CLOCK_POWER_SAVE_DISABLE | \ + SDIO_BUS_WIDE_1B | SDIO_HARDWARE_FLOW_CONTROL_DISABLE | (clkdiv & 0xFF); + MODIFY_REG(sdio->CLKCR, CLKCR_CLEAR_MASK, sdio_confreg); +} diff --git a/src/stm32/sdio.h b/src/stm32/sdio.h new file mode 100644 index 000000000000..eaf6596fe162 --- /dev/null +++ b/src/stm32/sdio.h @@ -0,0 +1,25 @@ +#ifndef __STM32_SDIO_H +#define __STM32_SDIO_H + +#include // uint32_t + +struct sdio_config { + void *sdio; +}; +struct sdio_config sdio_setup(uint32_t bus); +void sdio_send_cmd(struct sdio_config sdio, uint8_t cmd, uint32_t argument + , uint8_t wait); +uint8_t sdio_send_command(struct sdio_config sdio_config, uint8_t cmd + , uint32_t argument, uint8_t wait + , uint8_t *response_data + , uint8_t *response_data_len); +uint8_t sdio_prepare_data_transfer(struct sdio_config sdio_config, uint8_t read + , uint32_t numblocks, uint32_t blocksize + , uint32_t timeout); +uint8_t sdio_read_data(struct sdio_config sdio_config, uint8_t *data + , uint32_t numblocks, uint32_t blocksize); +uint8_t sdio_write_data(struct sdio_config sdio_config, uint8_t *data + , uint32_t numblocks, uint32_t blocksize); +void sdio_set_speed(struct sdio_config sdio_config, uint32_t speed); + +#endif // sdio.h diff --git a/src/stm32/spi.c b/src/stm32/spi.c index 52ec69e1d546..17a842322100 100644 --- a/src/stm32/spi.c +++ b/src/stm32/spi.c @@ -21,14 +21,17 @@ DECL_ENUMERATION("spi_bus", "spi1", 1); DECL_CONSTANT_STR("BUS_PINS_spi1", "PA6,PA7,PA5"); DECL_ENUMERATION("spi_bus", "spi1a", 2); DECL_CONSTANT_STR("BUS_PINS_spi1a", "PB4,PB5,PB3"); -#if !CONFIG_MACH_STM32F1 +#if CONFIG_MACH_STM32G4 + DECL_ENUMERATION("spi_bus", "spi2_PA10_PA11_PF1", 3); + DECL_CONSTANT_STR("BUS_PINS_spi2_PA10_PA11_PF1", "PA10,PA11,PF1"); +#elif !CONFIG_MACH_STM32F1 DECL_ENUMERATION("spi_bus", "spi2a", 3); DECL_CONSTANT_STR("BUS_PINS_spi2a", "PC2,PC3,PB10"); #endif #ifdef SPI3 DECL_ENUMERATION("spi_bus", "spi3", 4); DECL_CONSTANT_STR("BUS_PINS_spi3", "PB4,PB5,PB3"); - #if CONFIG_MACH_STM32F4 + #if CONFIG_MACH_STM32F4 || CONFIG_MACH_STM32G4 DECL_ENUMERATION("spi_bus", "spi3a", 5); DECL_CONSTANT_STR("BUS_PINS_spi3a", "PC11,PC12,PC10"); #ifdef SPI4 @@ -51,10 +54,14 @@ static const struct spi_info spi_bus[] = { { SPI2, GPIO('B', 14), GPIO('B', 15), GPIO('B', 13), SPI_FUNCTION }, { SPI1, GPIO('A', 6), GPIO('A', 7), GPIO('A', 5), SPI_FUNCTION }, { SPI1, GPIO('B', 4), GPIO('B', 5), GPIO('B', 3), SPI_FUNCTION }, +#if CONFIG_MACH_STM32G4 + { SPI2, GPIO('A', 10), GPIO('A', 11), GPIO('F', 1), SPI_FUNCTION }, +#else { SPI2, GPIO('C', 2), GPIO('C', 3), GPIO('B', 10), SPI_FUNCTION }, +#endif #ifdef SPI3 { SPI3, GPIO('B', 4), GPIO('B', 5), GPIO('B', 3), GPIO_FUNCTION(6) }, - #if CONFIG_MACH_STM32F4 + #if CONFIG_MACH_STM32F4 || CONFIG_MACH_STM32G4 { SPI3, GPIO('C', 11), GPIO('C', 12), GPIO('C', 10), GPIO_FUNCTION(6) }, #ifdef SPI4 { SPI4, GPIO('E', 13), GPIO('E', 14), GPIO('E', 12), GPIO_FUNCTION(5) }, @@ -79,8 +86,9 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate) gpio_peripheral(spi_bus[bus].mosi_pin, spi_bus[bus].function, 0); gpio_peripheral(spi_bus[bus].sck_pin, spi_bus[bus].function, 0); - // Configure CR2 on stm32 f0/g0/l4 -#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 + // Configure CR2 on stm32 f0/g0/l4/g4 +#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 \ + || CONFIG_MACH_STM32G4 spi->CR2 = SPI_CR2_FRXTH | (7 << SPI_CR2_DS_Pos); #endif } diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c index e63f1b5b44c3..72fc1645e08a 100644 --- a/src/stm32/stm32f0.c +++ b/src/stm32/stm32f0.c @@ -134,39 +134,12 @@ hsi14_setup(void) * Bootloader ****************************************************************/ -#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024) -#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT" - -// Flag that bootloader is desired and reboot -static void -usb_reboot_for_dfu_bootloader(void) -{ - irq_disable(); - *(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG; - NVIC_SystemReset(); -} - -// Check if rebooting into system DFU Bootloader -static void -check_usb_dfu_bootloader(void) -{ - if (!CONFIG_USB || !CONFIG_MACH_STM32F0x2 - || *(uint64_t*)USB_BOOT_FLAG_ADDR != USB_BOOT_FLAG) - return; - *(uint64_t*)USB_BOOT_FLAG_ADDR = 0; - uint32_t *sysbase = (uint32_t*)0x1fffc400; - if (CONFIG_MACH_STM32F072) - sysbase = (uint32_t*)0x1fffc800; - asm volatile("mov sp, %0\n bx %1" - : : "r"(sysbase[0]), "r"(sysbase[1])); -} - // Handle reboot requests void bootloader_request(void) { try_request_canboot(); - usb_reboot_for_dfu_bootloader(); + dfu_reboot(); } @@ -193,7 +166,7 @@ enable_ram_vectortable(void) void armcm_main(void) { - check_usb_dfu_bootloader(); + dfu_reboot_check(); SystemInit(); enable_pclock(SYSCFG_BASE); diff --git a/src/stm32/stm32f0_i2c.c b/src/stm32/stm32f0_i2c.c index 418e1c1ec111..48c3ae3e7747 100644 --- a/src/stm32/stm32f0_i2c.c +++ b/src/stm32/stm32f0_i2c.c @@ -16,38 +16,69 @@ struct i2c_info { }; #if CONFIG_MACH_STM32F0 -DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); -DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); -DECL_ENUMERATION("i2c_bus", "i2c1_PF1_PF0", 1); -DECL_CONSTANT_STR("BUS_PINS_i2c1_PF1_PF0", "PF1,PF0"); -DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 2); -DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); -// Deprecated "i2c1a" style mappings -DECL_ENUMERATION("i2c_bus", "i2c1", 0); -DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7"); -DECL_ENUMERATION("i2c_bus", "i2c1a", 1); -DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0"); - -#elif CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 -DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); -DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); -DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1); -DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); -#if CONFIG_MACH_STM32G0 -#define GPIO_AF_INDEX 6 -DECL_ENUMERATION("i2c_bus", "i2c3_PB3_PB4", 2); -DECL_CONSTANT_STR("BUS_PINS_i2c3_PB3_PB4", "PB3,PB4"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); + DECL_ENUMERATION("i2c_bus", "i2c1_PF1_PF0", 1); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PF1_PF0", "PF1,PF0"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 2); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); + // Deprecated "i2c1a" style mappings + DECL_ENUMERATION("i2c_bus", "i2c1", 0); + DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7"); + DECL_ENUMERATION("i2c_bus", "i2c1a", 1); + DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0"); +#elif CONFIG_MACH_STM32G0 + DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); + DECL_ENUMERATION("i2c_bus", "i2c1_PA9_PA10", 2); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PA9_PA10", "PA9,PA10"); + DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 3); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11"); + DECL_ENUMERATION("i2c_bus", "i2c2_PB13_PB14", 4); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PB13_PB14", "PB13,PB14"); + #ifdef I2C3 + DECL_ENUMERATION("i2c_bus", "i2c3_PB3_PB4", 5); + DECL_CONSTANT_STR("BUS_PINS_i2c3_PB3_PB4", "PB3,PB4"); + #endif #elif CONFIG_MACH_STM32L4 -#define GPIO_AF_INDEX 4 -DECL_ENUMERATION("i2c_bus", "i2c3_PA7_PB4", 2); -DECL_CONSTANT_STR("BUS_PINS_i2c3_PA7_PB4", "PA7,PB4"); -#endif -DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 3); -DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11"); -DECL_ENUMERATION("i2c_bus", "i2c2_PB13_PB14", 4); -DECL_CONSTANT_STR("BUS_PINS_i2c2_PB13_PB14", "PB13,PB14"); -DECL_ENUMERATION("i2c_bus", "i2c1_PA9_PA10", 5); -DECL_CONSTANT_STR("BUS_PINS_i2c1_PA9_PA10", "PA9,PA10"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); + DECL_ENUMERATION("i2c_bus", "i2c1_PA9_PA10", 2); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PA9_PA10", "PA9,PA10"); + DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 3); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11"); + DECL_ENUMERATION("i2c_bus", "i2c2_PB13_PB14", 4); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PB13_PB14", "PB13,PB14"); + DECL_ENUMERATION("i2c_bus", "i2c3_PA7_PB4", 5); + DECL_CONSTANT_STR("BUS_PINS_i2c3_PA7_PB4", "PA7,PB4"); +#elif CONFIG_MACH_STM32G4 + DECL_ENUMERATION("i2c_bus", "i2c1_PA13_PA14", 0); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PA13_PA14", "PA13,PA14"); + DECL_ENUMERATION("i2c_bus", "i2c1_PA15_PA14", 1); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PA15_PA14", "PA15,PA14"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB7", 2); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB7", "PB8,PB7"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 3); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); + DECL_ENUMERATION("i2c_bus", "i2c2_PA9_PA8", 4); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PA9_PA8", "PA9,PA8"); + DECL_ENUMERATION("i2c_bus", "i2c2_PC4_PF0", 5); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PC4_PF0", "PC4,PF0"); + DECL_ENUMERATION("i2c_bus", "i2c3_PC8_PC9", 6); + DECL_CONSTANT_STR("BUS_PINS_i2c3_PC8_PC9", "PC8,PC9"); + DECL_ENUMERATION("i2c_bus", "i2c3_PC8_PC11", 7); + DECL_CONSTANT_STR("BUS_PINS_i2c3_PC8_PC11", "PC8,PC11"); +#elif CONFIG_MACH_STM32H7 + DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); + DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1); + DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); + DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 2); + DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11"); #endif static const struct i2c_info i2c_bus[] = { @@ -55,18 +86,35 @@ static const struct i2c_info i2c_bus[] = { { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) }, { I2C1, GPIO('F', 1), GPIO('F', 0), GPIO_FUNCTION(1) }, { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(1) }, - -#elif CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 - { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(GPIO_AF_INDEX) }, - { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(GPIO_AF_INDEX) }, -#if CONFIG_MACH_STM32G0 - { I2C3, GPIO('B', 3), GPIO('B', 4), GPIO_FUNCTION(GPIO_AF_INDEX) }, +#elif CONFIG_MACH_STM32G0 + { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(6) }, + { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(6) }, + { I2C1, GPIO('A', 9), GPIO('A', 10), GPIO_FUNCTION(6) }, + { I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(6) }, + { I2C2, GPIO('B', 13), GPIO('B', 14), GPIO_FUNCTION(6) }, + #ifdef I2C3 + { I2C3, GPIO('B', 3), GPIO('B', 4), GPIO_FUNCTION(6) }, + #endif #elif CONFIG_MACH_STM32L4 - { I2C3, GPIO('A', 7), GPIO('B', 4), GPIO_FUNCTION(GPIO_AF_INDEX) }, -#endif - { I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(GPIO_AF_INDEX) }, - { I2C2, GPIO('B', 13), GPIO('B', 14), GPIO_FUNCTION(GPIO_AF_INDEX) }, - { I2C1, GPIO('A', 9), GPIO('A', 10), GPIO_FUNCTION(GPIO_AF_INDEX) }, + { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(4) }, + { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(4) }, + { I2C1, GPIO('A', 9), GPIO('A', 10), GPIO_FUNCTION(4) }, + { I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(4) }, + { I2C2, GPIO('B', 13), GPIO('B', 14), GPIO_FUNCTION(4) }, + { I2C3, GPIO('A', 7), GPIO('B', 4), GPIO_FUNCTION(4) }, +#elif CONFIG_MACH_STM32G4 + { I2C1, GPIO('A', 13), GPIO('A', 14), GPIO_FUNCTION(4) }, + { I2C1, GPIO('A', 15), GPIO('A', 14), GPIO_FUNCTION(4) }, + { I2C1, GPIO('B', 8), GPIO('B', 7), GPIO_FUNCTION(4) }, + { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(4) }, + { I2C2, GPIO('A', 9), GPIO('A', 8), GPIO_FUNCTION(4) }, + { I2C2, GPIO('C', 4), GPIO('F', 0), GPIO_FUNCTION(4) }, + { I2C3, GPIO('C', 8), GPIO('C', 9), GPIO_FUNCTION(8) }, + { I2C3, GPIO('C', 8), GPIO('C', 11), GPIO_FUNCTION(8) }, +#elif CONFIG_MACH_STM32H7 + { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(4) }, + { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(4) }, + { I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(4) }, #endif }; diff --git a/src/stm32/stm32f0_serial.c b/src/stm32/stm32f0_serial.c index f7f17dfc43bb..e48960f1163c 100644 --- a/src/stm32/stm32f0_serial.c +++ b/src/stm32/stm32f0_serial.c @@ -16,28 +16,38 @@ DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9"); #define GPIO_Rx GPIO('A', 10) #define GPIO_Tx GPIO('A', 9) - #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32H7 ? 7 : 1) + #define USARTx_FUNCTION GPIO_FUNCTION( \ + (CONFIG_MACH_STM32H7 | CONFIG_MACH_STM32G4) ? 7 : 1) #define USARTx USART1 #define USARTx_IRQn USART1_IRQn #elif CONFIG_STM32_SERIAL_USART1_ALT_PB7_PB6 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB7,PB6"); #define GPIO_Rx GPIO('B', 7) #define GPIO_Tx GPIO('B', 6) - #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32H7 ? 7 : 0) + #define USARTx_FUNCTION GPIO_FUNCTION( \ + (CONFIG_MACH_STM32H7 | CONFIG_MACH_STM32G4) ? 7 : 0) #define USARTx USART1 #define USARTx_IRQn USART1_IRQn #elif CONFIG_STM32_SERIAL_USART2 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2"); #define GPIO_Rx GPIO('A', 3) #define GPIO_Tx GPIO('A', 2) - #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32H7 ? 7 : 1) + #define USARTx_FUNCTION GPIO_FUNCTION( \ + (CONFIG_MACH_STM32H7 | CONFIG_MACH_STM32G4) ? 7 : 1) #define USARTx USART2 #define USARTx_IRQn USART2_IRQn #elif CONFIG_STM32_SERIAL_USART2_ALT_PA15_PA14 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA15,PA14"); #define GPIO_Rx GPIO('A', 15) #define GPIO_Tx GPIO('A', 14) - #define USARTx_FUNCTION GPIO_FUNCTION(1) + #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32G4 ? 7 : 1) + #define USARTx USART2 + #define USARTx_IRQn USART2_IRQn +#elif CONFIG_STM32_SERIAL_USART2_ALT_PB4_PB3 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB4,PB3"); + #define GPIO_Rx GPIO('B', 4) + #define GPIO_Tx GPIO('B', 3) + #define USARTx_FUNCTION GPIO_FUNCTION(7) #define USARTx USART2 #define USARTx_IRQn USART2_IRQn #elif CONFIG_STM32_SERIAL_USART2_ALT_PD6_PD5 @@ -68,6 +78,13 @@ #define USARTx_FUNCTION GPIO_FUNCTION(8) #define USARTx UART4 #define USARTx_IRQn UART4_IRQn +#elif CONFIG_STM32_SERIAL_USART5 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD2,PD3"); + #define GPIO_Rx GPIO('D', 2) + #define GPIO_Tx GPIO('D', 3) + #define USARTx_FUNCTION GPIO_FUNCTION(3) + #define USARTx USART5 + #define USARTx_IRQn USART5_IRQn #endif #if CONFIG_MACH_STM32F031 @@ -77,14 +94,23 @@ #endif #if CONFIG_MACH_STM32G0 - // The stm32g0 has slightly different register names - #define USART2_IRQn USART2_LPUART2_IRQn + // Some of the stm32g0 MCUs have slightly different register names + #if CONFIG_MACH_STM32G0B1 + #define USART2_IRQn USART2_LPUART2_IRQn + #define USART3_IRQn USART3_4_5_6_LPUART1_IRQn + #define USART4_IRQn USART3_4_5_6_LPUART1_IRQn + #define USART5_IRQn USART3_4_5_6_LPUART1_IRQn + #define USART6_IRQn USART3_4_5_6_LPUART1_IRQn + #endif #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE #define USART_ISR_RXNE USART_ISR_RXNE_RXFNE #define USART_ISR_TXE USART_ISR_TXE_TXFNF #define USART_BRR_DIV_MANTISSA_Pos 4 #define USART_BRR_DIV_FRACTION_Pos 0 +#elif CONFIG_MACH_STM32G4 + #define USART_BRR_DIV_MANTISSA_Pos 4 + #define USART_BRR_DIV_FRACTION_Pos 0 #elif CONFIG_MACH_STM32H7 // The stm32h7 has slightly different register names #define USART_ISR_RXNE USART_ISR_RXNE_RXFNE diff --git a/src/stm32/stm32f0_timer.c b/src/stm32/stm32f0_timer.c index 4f5e6d38285b..f4a963964c56 100644 --- a/src/stm32/stm32f0_timer.c +++ b/src/stm32/stm32f0_timer.c @@ -20,14 +20,19 @@ ****************************************************************/ // Use 32bit TIM2 timer if available (otherwise use 16bit TIM3 timer) -#ifdef TIM2 -#define TIMx TIM2 -#define TIMx_IRQn TIM2_IRQn -#define HAVE_TIMER_32BIT 1 -#else -#define TIMx TIM3 -#define TIMx_IRQn TIM3_IRQn -#define HAVE_TIMER_32BIT 0 +#if defined(TIM2) + #define TIMx TIM2 + #define TIMx_IRQn TIM2_IRQn + #define HAVE_TIMER_32BIT 1 +#elif defined(TIM3) + #define TIMx TIM3 + #define TIMx_IRQn TIM3_IRQn + #define HAVE_TIMER_32BIT 0 +#endif + +// Some chips have slightly different register names +#if CONFIG_MACH_STM32G0B0 + #define TIM3_IRQn TIM3_TIM4_IRQn #endif static inline uint32_t diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index 4f1dc084b86a..fd3eb0bae56b 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -138,8 +138,8 @@ enable_clock_stm32f446(void) while (!(PWR->CSR & PWR_CSR_ODSWRDY)) ; - // Enable 48Mhz USB clock - if (CONFIG_USB) { + // Enable 48Mhz USB clock for USB or for SDIO + if (CONFIG_USB || CONFIG_HAVE_GPIO_SDIO) { uint32_t ref = (CONFIG_STM32_CLOCK_REF_INTERNAL ? 16000000 : CONFIG_CLOCK_REF_FREQ); uint32_t plls_base = 2000000, plls_freq = FREQ_USB * 4; @@ -153,6 +153,14 @@ enable_clock_stm32f446(void) ; RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL; + } else { + // Reset value just in case the booloader modified the default value + RCC->DCKCFGR2 = 0; + } + + // Set SDIO clk to PLL48CLK + if (CONFIG_HAVE_GPIO_SDIO) { + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, 0); } #endif } @@ -204,30 +212,6 @@ usb_hid_bootloader(void) NVIC_SystemReset(); } -#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 4096) -#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT" - -// Flag that bootloader is desired and reboot -static void -usb_reboot_for_dfu_bootloader(void) -{ - irq_disable(); - *(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG; - NVIC_SystemReset(); -} - -// Check if rebooting into system DFU Bootloader -static void -check_usb_dfu_bootloader(void) -{ - if (!CONFIG_USB || *(uint64_t*)USB_BOOT_FLAG_ADDR != USB_BOOT_FLAG) - return; - *(uint64_t*)USB_BOOT_FLAG_ADDR = 0; - uint32_t *sysbase = (uint32_t*)0x1fff0000; - asm volatile("mov sp, %0\n bx %1" - : : "r"(sysbase[0]), "r"(sysbase[1])); -} - // Handle reboot requests void bootloader_request(void) @@ -235,7 +219,7 @@ bootloader_request(void) try_request_canboot(); if (CONFIG_STM32_FLASH_START_4000) usb_hid_bootloader(); - usb_reboot_for_dfu_bootloader(); + dfu_reboot(); } @@ -247,7 +231,7 @@ bootloader_request(void) void armcm_main(void) { - check_usb_dfu_bootloader(); + dfu_reboot_check(); // Run SystemInit() and then restore VTOR SystemInit(); diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c index c243743be754..7408612ade2e 100644 --- a/src/stm32/stm32g0.c +++ b/src/stm32/stm32g0.c @@ -32,14 +32,30 @@ lookup_clock_line(uint32_t periph_base) uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400); return (struct cline){.en=&RCC->AHBENR, .rst=&RCC->AHBRSTR, .bit=bit}; } +#ifdef USART5_BASE + if (periph_base == USART5_BASE) + return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<8}; +#endif +#ifdef USART6_BASE + if (periph_base == USART6_BASE) + return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<9}; +#endif +#if defined(FDCAN1_BASE) || defined(FDCAN2_BASE) if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE)) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12}; +#endif +#ifdef USB_BASE if (periph_base == USB_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13}; +#endif +#ifdef CRS_BASE if (periph_base == CRS_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16}; +#endif +#ifdef I2C3_BASE if (periph_base == I2C3_BASE) return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<23}; +#endif if (periph_base == TIM1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11}; if (periph_base == SPI1_BASE) @@ -56,8 +72,8 @@ lookup_clock_line(uint32_t periph_base) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18}; if (periph_base == ADC1_BASE) return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20}; - if (periph_base >= APBPERIPH_BASE && periph_base <= LPTIM1_BASE) - { + if (periph_base >= APBPERIPH_BASE + && periph_base < APBPERIPH_BASE + 32*0x400) { uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400); return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit}; } @@ -102,8 +118,11 @@ clock_setup(void) } pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos; pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos; - pllcfgr |= (pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos; - RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN; +#ifdef RCC_PLLCFGR_PLLQ + pllcfgr |= ((pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos) + | RCC_PLLCFGR_PLLQEN; +#endif + RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN; RCC->CR |= RCC_CR_PLLON; // Wait for PLL lock @@ -115,8 +134,10 @@ clock_setup(void) while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2 << RCC_CFGR_SWS_Pos)) ; +#ifdef USB_BASE // Use PLLQCLK for USB (setting USBSEL=2 works in practice) RCC->CCIPR2 = 2 << RCC_CCIPR2_USBSEL_Pos; +#endif } @@ -124,36 +145,12 @@ clock_setup(void) * Bootloader ****************************************************************/ -#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024) -#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT" - -// Flag that bootloader is desired and reboot -static void -usb_reboot_for_dfu_bootloader(void) -{ - irq_disable(); - *(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG; - NVIC_SystemReset(); -} - -// Check if rebooting into system DFU Bootloader -static void -check_usb_dfu_bootloader(void) -{ - if (!CONFIG_USB || *(uint64_t*)USB_BOOT_FLAG_ADDR != USB_BOOT_FLAG) - return; - *(uint64_t*)USB_BOOT_FLAG_ADDR = 0; - uint32_t *sysbase = (uint32_t*)0x1fff0000; - asm volatile("mov sp, %0\n bx %1" - : : "r"(sysbase[0]), "r"(sysbase[1])); -} - // Handle USB reboot requests void bootloader_request(void) { try_request_canboot(); - usb_reboot_for_dfu_bootloader(); + dfu_reboot(); } @@ -181,10 +178,13 @@ armcm_main(void) RCC->APBENR1 = 0x00000000; RCC->APBENR2 = 0x00000000; - check_usb_dfu_bootloader(); + dfu_reboot_check(); - // Set flash latency - FLASH->ACR = (2<ACR = acr; // Configure main clock clock_setup(); diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c new file mode 100644 index 000000000000..aed9ed8fa396 --- /dev/null +++ b/src/stm32/stm32g4.c @@ -0,0 +1,172 @@ +// Code to setup clocks and gpio on stm32g4 +// +// Copyright (C) 2019 Kevin O'Connor +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ +#include "board/armcm_boot.h" // VectorTable +#include "board/irq.h" // irq_disable +#include "board/misc.h" // bootloader_request +#include "command.h" // DECL_CONSTANT_STR +#include "internal.h" // enable_pclock +#include "sched.h" // sched_main + +#define FREQ_PERIPH_DIV 1 +#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV) + +// Map a peripheral address to its enable bits +struct cline +lookup_clock_line(uint32_t periph_base) +{ + if (periph_base < APB2PERIPH_BASE) { + uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400; + if (pos < 32) { + return (struct cline){.en = &RCC->APB1ENR1, + .rst = &RCC->APB1RSTR1, + .bit = 1 << pos}; + } else { + return (struct cline){.en = &RCC->APB1ENR2, + .rst = &RCC->APB1RSTR2, + .bit = 1 << (pos - 32)}; + } + } else if (periph_base < AHB1PERIPH_BASE) { + uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400; + return (struct cline){.en = &RCC->APB2ENR, + .rst = &RCC->APB2RSTR, + .bit = 1 << pos}; + + } else if (periph_base < AHB2PERIPH_BASE) { + uint32_t pos = (periph_base - AHB1PERIPH_BASE) / 0x400; + return (struct cline){.en = &RCC->AHB1ENR, + .rst = &RCC->AHB1RSTR, + .bit = 1 << pos}; + + } else { + if (periph_base == ADC12_COMMON_BASE) + return (struct cline){.en = &RCC->AHB2ENR, + .rst = &RCC->AHB2RSTR, + .bit = RCC_AHB2ENR_ADC12EN}; + uint32_t pos = (periph_base - AHB2PERIPH_BASE) / 0x400; + return (struct cline){.en = &RCC->AHB2ENR, + .rst = &RCC->AHB2RSTR, + .bit = 1 << pos}; + } +} + +// Return the frequency of the given peripheral clock +uint32_t +get_pclock_frequency(uint32_t periph_base) +{ + return FREQ_PERIPH; +} + +// Enable a GPIO peripheral clock +void +gpio_clock_enable(GPIO_TypeDef *regs) +{ + uint32_t rcc_pos = ((uint32_t)regs - GPIOA_BASE) / 0x400; + RCC->AHB2ENR |= 1 << rcc_pos; + RCC->AHB2ENR; +} + +#if !CONFIG_STM32_CLOCK_REF_INTERNAL +DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1"); +#endif + +static void +enable_clock_stm32g4(void) +{ + uint32_t pll_base = 4000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr; + if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { + // Configure 150Mhz PLL from external crystal (HSE) + uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base - 1; + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; + pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos); + } else { + // Configure 150Mhz PLL from internal 16Mhz oscillator (HSI) + uint32_t div = 16000000 / pll_base - 1; + pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos); + RCC->CR |= RCC_CR_HSION; + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; + } + RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos) + | (0 << RCC_PLLCFGR_PLLR_Pos)); + RCC->CR |= RCC_CR_PLLON; + + // Enable 48Mhz USB clock using clock recovery + if (CONFIG_USBSERIAL) { + RCC->CRRCR |= RCC_CRRCR_HSI48ON; + while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) + ; + enable_pclock(CRS_BASE); + CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + } +} + +// Main clock setup called at chip startup +static void +clock_setup(void) +{ + enable_clock_stm32g4(); + + // Set flash latency + uint32_t latency = ((CONFIG_CLOCK_FREQ>150000000) ? FLASH_ACR_LATENCY_5WS : + ((CONFIG_CLOCK_FREQ>120000000) ? FLASH_ACR_LATENCY_4WS : + ((CONFIG_CLOCK_FREQ>90000000) ? FLASH_ACR_LATENCY_3WS : + ((CONFIG_CLOCK_FREQ>60000000) ? FLASH_ACR_LATENCY_2WS : + ((CONFIG_CLOCK_FREQ>30000000) ? FLASH_ACR_LATENCY_1WS : + FLASH_ACR_LATENCY_0WS))))); + FLASH->ACR = (latency | FLASH_ACR_ICEN | FLASH_ACR_DCEN + | FLASH_ACR_PRFTEN | FLASH_ACR_DBG_SWEN); + + enable_pclock(PWR_BASE); + PWR->CR3 |= PWR_CR3_APC; // allow gpio pullup/down + + // Wait for PLL lock + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; + + RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; + + // Switch system clock to PLL + RCC->CFGR = RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV1 | RCC_CFGR_PPRE2_DIV1 + | RCC_CFGR_SW_PLL; + while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) + ; +} + + +/**************************************************************** + * Bootloader + ****************************************************************/ + +// Handle USB reboot requests +void +bootloader_request(void) +{ + dfu_reboot(); +} + + +/**************************************************************** + * Startup + ****************************************************************/ + +// Main entry point - called from armcm_boot.c:ResetHandler() +void +armcm_main(void) +{ + dfu_reboot_check(); + + // Run SystemInit() and then restore VTOR + SystemInit(); + SCB->VTOR = (uint32_t)VectorTable; + + clock_setup(); + + sched_main(); +} diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index d24d07b7f7a0..387e47dd9eab 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -40,6 +40,9 @@ lookup_clock_line(uint32_t periph_base) uint32_t bit = 1 << ((periph_base - D2_AHB2PERIPH_BASE) / 0x400); return (struct cline){.en=&RCC->AHB2ENR, .rst=&RCC->AHB2RSTR, .bit=bit}; } else if (periph_base >= D2_AHB1PERIPH_BASE) { + if (periph_base == ADC12_COMMON_BASE) + return (struct cline){.en = &RCC->AHB1ENR, .rst = &RCC->AHB1RSTR, + .bit = RCC_AHB1ENR_ADC12EN}; uint32_t bit = 1 << ((periph_base - D2_AHB1PERIPH_BASE) / 0x400); return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit}; } else if (periph_base >= D2_APB2PERIPH_BASE) { @@ -83,10 +86,11 @@ DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); static void clock_setup(void) { +#if !CONFIG_MACH_STM32H723 // Ensure USB OTG ULPI is not enabled CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN); CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN); - +#endif // Set this despite correct defaults. // "The software has to program the supply configuration in PWR control // register 3" (pg. 259) @@ -143,7 +147,11 @@ clock_setup(void) // Enable VOS0 (overdrive) if (CONFIG_CLOCK_FREQ > 400000000) { RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; +#if !CONFIG_MACH_STM32H723 SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN; +#else + PWR->CR3 |= PWR_CR3_BYPASS; +#endif while (!(PWR->D3CR & PWR_D3CR_VOSRDY)) ; } @@ -203,36 +211,12 @@ clock_setup(void) * Bootloader ****************************************************************/ -#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024) -#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT" - -// Flag that bootloader is desired and reboot -static void -usb_reboot_for_dfu_bootloader(void) -{ - irq_disable(); - *(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG; - NVIC_SystemReset(); -} - -// Check if rebooting into system DFU Bootloader -static void -check_usb_dfu_bootloader(void) -{ - if (!CONFIG_USB || *(uint64_t*)USB_BOOT_FLAG_ADDR != USB_BOOT_FLAG) - return; - *(uint64_t*)USB_BOOT_FLAG_ADDR = 0; - uint32_t *sysbase = (uint32_t*)0x1FF09800; - asm volatile("mov sp, %0\n bx %1" - : : "r"(sysbase[0]), "r"(sysbase[1])); -} - // Handle reboot requests void bootloader_request(void) { try_request_canboot(); - usb_reboot_for_dfu_bootloader(); + dfu_reboot(); } @@ -250,9 +234,15 @@ armcm_main(void) RCC->D2CCIP1R = 0x00000000; RCC->D2CCIP2R = 0x00000000; RCC->D3CCIPR = 0x00000000; + RCC->APB1LENR = 0x00000000; + RCC->APB1HENR = 0x00000000; + RCC->APB2ENR = 0x00000000; + RCC->APB3ENR = 0x00000000; + RCC->APB4ENR = 0x00000000; + SCB->VTOR = (uint32_t)VectorTable; - check_usb_dfu_bootloader(); + dfu_reboot_check(); clock_setup(); diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c index d873dfb8385c..57d4b15c7fab 100644 --- a/src/stm32/stm32h7_adc.c +++ b/src/stm32/stm32h7_adc.c @@ -1,54 +1,24 @@ -// ADC functions on STM32H7 +// Analog to digital (ADC) on stm32h7 and similar chips // // Copyright (C) 2020 Konstantin Vogel +// Copyright (C) 2022 Kevin O'Connor // // This file may be distributed under the terms of the GNU GPLv3 license. #include "board/irq.h" // irq_save #include "board/misc.h" // timer_from_us #include "command.h" // shutdown -#include "compiler.h" // ARRAY_SIZE -#include "generic/armcm_timer.h" // udelay #include "gpio.h" // gpio_adc_setup #include "internal.h" // GPIO #include "sched.h" // sched_shutdown -#if CONFIG_MACH_STM32H7 -#define ADCIN_BANK_SIZE (20) -#define RCC_AHBENR_ADC (RCC->AHB1ENR) -#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN) -#define ADC_CKMODE (0b11) -#define ADC_ATICKS (0b101) -#define ADC_RES (0b110) -#define ADC_TS (ADC3_COMMON) - -// Number of samples is 2^OVERSAMPLES_EXPONENT (exponent can be 0-10) -#define OVERSAMPLES_EXPONENT 3 -#define OVERSAMPLES (1 << OVERSAMPLES_EXPONENT) -#define ADC_MEAS_DELAY (1 + 2.3666*OVERSAMPLES) - -// LDORDY registers are missing from CMSIS (only available on revision V!) -#define ADC_ISR_LDORDY_Pos (12U) -#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) -#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk - -#else // stm32l4 -#define RCC_AHBENR_ADC (RCC->AHB2ENR) -#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN) -#define ADC_CKMODE (0) -#define ADC_ATICKS (0b100) -#define ADC_RES (0b00) -#define ADC_TS (ADC12_COMMON) - -#define OVERSAMPLES (0) -#define ADC_MEAS_DELAY (10) -#endif - #define ADC_TEMPERATURE_PIN 0xfe DECL_ENUMERATION("pin", "ADC_TEMPERATURE", ADC_TEMPERATURE_PIN); DECL_CONSTANT("ADC_MAX", 4095); +#define ADCIN_BANK_SIZE 20 + // GPIOs like A0_C are not covered! // This always gives the pin connected to the positive channel static const uint8_t adc_pins[] = { @@ -113,9 +83,54 @@ static const uint8_t adc_pins[] = { GPIO('H', 3), // ADC3_INP14 GPIO('H', 4), // ADC3_INP15 GPIO('H', 5), // ADC3_INP16 + #if CONFIG_MACH_STM32H723 + ADC_TEMPERATURE_PIN, + 0, + #else 0, // Vbat/4 ADC_TEMPERATURE_PIN,// VSENSE + #endif 0, // VREFINT +#elif CONFIG_MACH_STM32G4 + 0, // [0] vssa + GPIO('A', 0), // [1] + GPIO('A', 1), // [2] + GPIO('A', 2), // [3] + GPIO('A', 3), // [4] + GPIO('B', 14), // [5] + GPIO('C', 0), // [6] + GPIO('C', 1), // [7] + GPIO('C', 2), // [8] + GPIO('C', 3), // [9] + GPIO('F', 0), // [10] + GPIO('B', 12), // [11] + GPIO('B', 1), // [12] + 0, // [13] opamp + GPIO('B', 11), // [14] + GPIO('B', 0), // [15] + ADC_TEMPERATURE_PIN, // [16] vtemp + 0, // [17] vbat/3 + 0, // [18] vref + 0, + 0, // [0] vssa ADC 2 + GPIO('A', 0), // [1] + GPIO('A', 1), // [2] + GPIO('A', 6), // [3] + GPIO('A', 7), // [4] + GPIO('C', 4), // [5] + GPIO('C', 0), // [6] + GPIO('C', 1), // [7] + GPIO('C', 2), // [8] + GPIO('C', 3), // [9] + GPIO('F', 1), // [10] + GPIO('C', 5), // [11] + GPIO('B', 2), // [12] + GPIO('A', 5), // [13] + GPIO('B', 11), // [14] + GPIO('B', 15), // [15] + 0, // [16] opamp + GPIO('A', 4), // [17] + 0, // [18] opamp #else // stm32l4 0, // vref GPIO('C', 0), // ADC12_IN1 .. 16 @@ -139,9 +154,21 @@ static const uint8_t adc_pins[] = { #endif }; +// ADC timing +#define ADC_CKMODE 0b11 +#define ADC_ATICKS 0b110 +#define ADC_ATICKS_H723_ADC3 0b111 +// stm32h7: clock=25Mhz, Tsamp=387.5, Tconv=394, total=15.76us +// stm32h723 adc3: clock=50Mhz, Tsamp=640.5, Tconv=653, total=13.06us +// stm32l4: clock=20Mhz, Tsamp=247.5, Tconv=260, total=13.0us +// stm32g4: clock=37.5Mhz, Tsamp=247.5, Tconv=260, total=6.933us -// ADC timing: -// ADC clock=30Mhz, Tconv=6.5, Tsamp=64.5, total=2.3666us*OVERSAMPLES +// Handle register name differences between chips +#if CONFIG_MACH_STM32H723 + #define PCSEL PCSEL_RES0 +#elif CONFIG_MACH_STM32G4 + #define ADC_CCR_TSEN ADC_CCR_VSENSESEL +#endif struct gpio_adc gpio_adc_setup(uint32_t pin) @@ -155,112 +182,85 @@ gpio_adc_setup(uint32_t pin) break; } - // Determine which ADC block to use, enable peripheral clock - // (SYSCLK 480Mhz) /HPRE(2) /CKMODE divider(4) /additional divider(2) - // (ADC clock 30Mhz) + // Determine which ADC block to use and enable its clock ADC_TypeDef *adc; + ADC_Common_TypeDef *adc_common; #ifdef ADC3 - if (chan >= 2 * ADCIN_BANK_SIZE){ - adc = ADC3; - if (!is_enabled_pclock(ADC3_BASE)) { - enable_pclock(ADC3_BASE); - } - MODIFY_REG(ADC3_COMMON->CCR, ADC_CCR_CKMODE_Msk, - ADC_CKMODE << ADC_CCR_CKMODE_Pos); + if (chan >= 2 * ADCIN_BANK_SIZE) { chan -= 2 * ADCIN_BANK_SIZE; - } else if (chan >= ADCIN_BANK_SIZE){ - adc = ADC2; - RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN; - MODIFY_REG(ADC12_COMMON->CCR, ADC_CCR_CKMODE_Msk, - ADC_CKMODE << ADC_CCR_CKMODE_Pos); + adc = ADC3; + adc_common = ADC3_COMMON; + } else +#endif +#ifdef ADC2 + if (chan >= ADCIN_BANK_SIZE) { chan -= ADCIN_BANK_SIZE; + adc = ADC2; + adc_common = ADC12_COMMON; } else #endif { adc = ADC1; - RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN; - MODIFY_REG(ADC12_COMMON->CCR, ADC_CCR_CKMODE_Msk, - ADC_CKMODE << ADC_CCR_CKMODE_Pos); + adc_common = ADC12_COMMON; } + if (!is_enabled_pclock((uint32_t)adc_common)) + enable_pclock((uint32_t)adc_common); + MODIFY_REG(adc_common->CCR, ADC_CCR_CKMODE_Msk, + ADC_CKMODE << ADC_CCR_CKMODE_Pos); // Enable the ADC - if (!(adc->CR & ADC_CR_ADEN)){ - // Pwr - // Exit deep power down - MODIFY_REG(adc->CR, ADC_CR_DEEPPWD_Msk, 0); - // Switch on voltage regulator - adc->CR |= ADC_CR_ADVREGEN; -#ifdef ADC_ISR_LDORDY - while(!(adc->ISR & ADC_ISR_LDORDY)) - ; -#else // stm32l4 lacks ldordy, delay to spec instead + if (!(adc->CR & ADC_CR_ADEN)) { + // Switch on voltage regulator and wait for it to stabilize + uint32_t cr = ADC_CR_ADVREGEN; + adc->CR = cr; uint32_t end = timer_read_time() + timer_from_us(20); while (timer_is_before(timer_read_time(), end)) ; -#endif - // Set Boost mode for 25Mhz < ADC clock <= 50Mhz -#ifdef ADC_CR_BOOST - MODIFY_REG(adc->CR, ADC_CR_BOOST_Msk, 0b11 << ADC_CR_BOOST_Pos); + // Setup chip specific flags + uint32_t aticks = ADC_ATICKS; +#if CONFIG_MACH_STM32H7 + if (CONFIG_MACH_STM32H723 && adc == ADC3) { + aticks = ADC_ATICKS_H723_ADC3; + } else { + // Use linear calibration on stm32h7 + cr |= ADC_CR_ADCALLIN; + // Set boost mode on stm32h7 (adc clock is at 25Mhz) + cr |= 0b10 << ADC_CR_BOOST_Pos; + // Set 12bit samples on the stm32h7 + adc->CFGR = ADC_CFGR_JQDIS | (0b110 << ADC_CFGR_RES_Pos); + } #endif - // Calibration - // Set calibration mode to Single ended (not differential) - MODIFY_REG(adc->CR, ADC_CR_ADCALDIF_Msk, 0); - // Enable linearity calibration -#ifdef ADC_CR_ADCALLIN - MODIFY_REG(adc->CR, ADC_CR_ADCALLIN_Msk, ADC_CR_ADCALLIN); -#endif - // Start the calibration - MODIFY_REG(adc->CR, ADC_CR_ADCAL_Msk, ADC_CR_ADCAL); - while(adc->CR & ADC_CR_ADCAL) + // Perform adc calibration + adc->CR = cr | ADC_CR_ADCAL; + while (adc->CR & ADC_CR_ADCAL) ; // Enable ADC - // "Clear the ADRDY bit in the ADC_ISR register by writing ‘1’" - adc->ISR |= ADC_ISR_ADRDY; + adc->ISR = ADC_ISR_ADRDY; adc->ISR; // Dummy read to make sure write is flushed adc->CR |= ADC_CR_ADEN; - while(!(adc->ISR & ADC_ISR_ADRDY)) + while (!(adc->ISR & ADC_ISR_ADRDY)) ; - // Set 64.5 ADC clock cycles sample time for every channel - // (Reference manual pg.940) - uint32_t aticks = ADC_ATICKS; - // Channel 0-9 - adc->SMPR1 = (aticks | (aticks << 3) | (aticks << 6) - | (aticks << 9) | (aticks << 12) | (aticks << 15) - | (aticks << 18) | (aticks << 21) | (aticks << 24) - | (aticks << 27)); - // Channel 10-19 - adc->SMPR2 = (aticks | (aticks << 3) | (aticks << 6) - | (aticks << 9) | (aticks << 12) | (aticks << 15) - | (aticks << 18) | (aticks << 21) | (aticks << 24) - | (aticks << 27)); - // Disable Continuous Mode - MODIFY_REG(adc->CFGR, ADC_CFGR_CONT_Msk, 0); - // Set to 12 bit - MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES << ADC_CFGR_RES_Pos); -#if CONFIG_MACH_STM32H7 - // Set hardware oversampling - MODIFY_REG(adc->CFGR2, ADC_CFGR2_ROVSE_Msk, ADC_CFGR2_ROVSE); - MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSR_Msk, - (OVERSAMPLES - 1) << ADC_CFGR2_OVSR_Pos); - MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk, - OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos); -#else // stm32l4 - adc->CFGR |= ADC_CFGR_JQDIS | ADC_CFGR_OVRMOD; -#endif + // Set ADC clock cycles sample time for every channel + uint32_t av = (aticks | (aticks << 3) | (aticks << 6) + | (aticks << 9) | (aticks << 12) | (aticks << 15) + | (aticks << 18) | (aticks << 21) | (aticks << 24) + | (aticks << 27)); + adc->SMPR1 = av; + adc->SMPR2 = av; } if (pin == ADC_TEMPERATURE_PIN) { - ADC_TS->CCR |= ADC_CCR_TSEN; + adc_common->CCR |= ADC_CCR_TSEN; } else { gpio_peripheral(pin, GPIO_ANALOG, 0); } - // Preselect (connect) channel -#ifdef ADC_PCSEL_PCSEL + // Setup preselect (connect) channel on stm32h7 +#if CONFIG_MACH_STM32H7 adc->PCSEL |= (1 << chan); #endif return (struct gpio_adc){ .adc = adc, .chan = chan }; @@ -273,20 +273,19 @@ uint32_t gpio_adc_sample(struct gpio_adc g) { ADC_TypeDef *adc = g.adc; - // Conversion ready - // EOC flag is cleared by hardware when reading DR - // the channel condition only works if this ist the only channel - // on the sequence and length set to 1 (ADC_SQR1_L = 0000) - if (adc->ISR & ADC_ISR_EOC && adc->SQR1 == (g.chan << ADC_SQR1_SQ1_Pos)) - return 0; - // Conversion started but not ready or wrong channel - if (adc->CR & ADC_CR_ADSTART) - return timer_from_us(10); + uint32_t cr = adc->CR; + if (cr & ADC_CR_ADSTART) + goto need_delay; + if (adc->ISR & ADC_ISR_EOC) { + if (adc->SQR1 == (g.chan << ADC_SQR1_SQ1_Pos)) + return 0; + goto need_delay; + } // Start sample adc->SQR1 = (g.chan << ADC_SQR1_SQ1_Pos); - adc->CR |= ADC_CR_ADSTART; - // Should take 2.3666us, add 1us for clock synchronisation etc. - return timer_from_us(ADC_MEAS_DELAY); + adc->CR = cr | ADC_CR_ADSTART; +need_delay: + return timer_from_us(20); } // Read a value; use only after gpio_adc_sample() returns zero @@ -303,9 +302,12 @@ gpio_adc_cancel_sample(struct gpio_adc g) { ADC_TypeDef *adc = g.adc; irqstatus_t flag = irq_save(); - // ADSTART is not as long true as SR_STRT on stm32f4 - if ((adc->CR & ADC_CR_ADSTART || adc->ISR & ADC_ISR_EOC) - && adc->SQR1 == (g.chan << ADC_SQR1_SQ1_Pos)) - gpio_adc_read(g); + if (adc->SQR1 == (g.chan << ADC_SQR1_SQ1_Pos)) { + uint32_t cr = adc->CR; + if (cr & ADC_CR_ADSTART) + adc->CR = (cr & ~ADC_CR_ADSTART) | ADC_CR_ADSTP; + if (adc->ISR & ADC_ISR_EOC) + gpio_adc_read(g); + } irq_restore(flag); } diff --git a/src/stm32/stm32l4.c b/src/stm32/stm32l4.c index 8fb50a23ea8d..7db15fff0ba2 100644 --- a/src/stm32/stm32l4.c +++ b/src/stm32/stm32l4.c @@ -7,7 +7,7 @@ #include "autoconf.h" // CONFIG_CLOCK_REF_FREQ #include "board/armcm_boot.h" // VectorTable #include "board/irq.h" // irq_disable -#include "board/usb_cdc.h" // usb_request_bootloader +#include "board/misc.h" // bootloader_request #include "command.h" // DECL_CONSTANT_STR #include "internal.h" // enable_pclock #include "sched.h" // sched_main @@ -42,7 +42,7 @@ lookup_clock_line(uint32_t periph_base) .rst = &RCC->AHB1RSTR, .bit = 1 << pos}; - } else if (periph_base == ADC1_BASE) { + } else if (periph_base == ADC12_COMMON_BASE) { return (struct cline){.en = &RCC->AHB2ENR, .rst = &RCC->AHB2RSTR, .bit = RCC_AHB2ENR_ADCEN}; @@ -68,25 +68,6 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHB2ENR; } -#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 4096) -#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT" - -// Handle USB reboot requests -void -usb_request_bootloader(void) -{ - irq_disable(); - // System DFU Bootloader - *(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG; - NVIC_SystemReset(); -} - -void -bootloader_request(void) -{ - usb_request_bootloader(); -} - #if !CONFIG_STM32_CLOCK_REF_INTERNAL DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PC14,PC15"); #endif @@ -154,16 +135,28 @@ clock_setup(void) ; } + +/**************************************************************** + * Bootloader + ****************************************************************/ + +// Handle USB reboot requests +void +bootloader_request(void) +{ + dfu_reboot(); +} + + +/**************************************************************** + * Startup + ****************************************************************/ + // Main entry point - called from armcm_boot.c:ResetHandler() void armcm_main(void) { - if (CONFIG_USBSERIAL && *(uint64_t*)USB_BOOT_FLAG_ADDR == USB_BOOT_FLAG) { - *(uint64_t*)USB_BOOT_FLAG_ADDR = 0; - uint32_t *sysbase = (uint32_t*)0x1fff0000; - asm volatile("mov sp, %0\n bx %1" - : : "r"(sysbase[0]), "r"(sysbase[1])); - } + dfu_reboot_check(); // Run SystemInit() and then restore VTOR SystemInit(); diff --git a/src/stm32/usbfs.c b/src/stm32/usbfs.c index cfe709513734..fda2ce9d299c 100644 --- a/src/stm32/usbfs.c +++ b/src/stm32/usbfs.c @@ -15,7 +15,7 @@ #include "internal.h" // GPIO #include "sched.h" // DECL_INIT -#if CONFIG_MACH_STM32F103 +#if CONFIG_MACH_STM32F1 || CONFIG_MACH_STM32G4 // Transfer memory is accessed with 32bits, but contains only 16bits of data typedef volatile uint32_t epmword_t; #define WSIZE 2 @@ -29,9 +29,14 @@ // Transfer memory is accessed with 32bits and contains 32bits of data typedef volatile uint32_t epmword_t; #define WSIZE 4 - #define USBx_IRQn USB_UCPD1_2_IRQn + #define USBx_IRQn USB_IRQn +#endif - // The stm32g0 has slightly different register names +// The stm32g0 has slightly different register names +#if CONFIG_MACH_STM32G0 + #if CONFIG_MACH_STM32G0B1 + #define USB_IRQn USB_UCPD1_2_IRQn + #endif #define USB USB_DRD_FS #define USB_PMAADDR USB_DRD_PMAADDR #define USB_EPADDR_FIELD USB_CHEP_ADDR diff --git a/src/stm32/usbotg.c b/src/stm32/usbotg.c index d65511061f0f..7482925606e5 100644 --- a/src/stm32/usbotg.c +++ b/src/stm32/usbotg.c @@ -15,21 +15,31 @@ #include "sched.h" // DECL_INIT #if CONFIG_STM32_USB_PB14_PB15 -#define USB_PERIPH_BASE USB_OTG_HS_PERIPH_BASE -#define OTG_IRQn OTG_HS_IRQn -#define USBOTGEN RCC_AHB1ENR_USB1OTGHSEN -#define GPIO_D_NEG GPIO('B', 14) -#define GPIO_D_POS GPIO('B', 15) -#define GPIO_FUNC GPIO_FUNCTION(12) -DECL_CONSTANT_STR("RESERVE_PINS_USB1", "PB14,PB15"); + #define IS_OTG_HS 1 + #define GPIO_D_NEG GPIO('B', 14) + #define GPIO_D_POS GPIO('B', 15) + #define GPIO_FUNC GPIO_FUNCTION(12) + DECL_CONSTANT_STR("RESERVE_PINS_USB1", "PB14,PB15"); #else -#define USB_PERIPH_BASE USB_OTG_FS_PERIPH_BASE -#define OTG_IRQn OTG_FS_IRQn -#define USBOTGEN RCC_AHB1ENR_USB2OTGHSEN -#define GPIO_D_NEG GPIO('A', 11) -#define GPIO_D_POS GPIO('A', 12) -#define GPIO_FUNC GPIO_FUNCTION(10) -DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12"); + #if CONFIG_MACH_STM32H723 + #define IS_OTG_HS 1 + #else + #define IS_OTG_HS 0 + #endif + #define GPIO_D_NEG GPIO('A', 11) + #define GPIO_D_POS GPIO('A', 12) + #define GPIO_FUNC GPIO_FUNCTION(10) + DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12"); +#endif + +#if IS_OTG_HS + #define USB_PERIPH_BASE USB_OTG_HS_PERIPH_BASE + #define OTG_IRQn OTG_HS_IRQn + #define USBOTGEN RCC_AHB1ENR_USB1OTGHSEN +#else + #define USB_PERIPH_BASE USB_OTG_FS_PERIPH_BASE + #define OTG_IRQn OTG_FS_IRQn + #define USBOTGEN RCC_AHB1ENR_USB2OTGHSEN #endif static void @@ -387,11 +397,11 @@ OTG_FS_IRQHandler(void) } if (sts & USB_OTG_GINTSTS_IEPINT) { // Can transmit data - disable irq and notify endpoint - uint32_t daint = OTGD->DAINT; - OTGD->DAINTMSK &= ~daint; - if (daint & (1 << 0)) + uint32_t daint = OTGD->DAINT, msk = OTGD->DAINTMSK, pend = daint & msk; + OTGD->DAINTMSK = msk & ~daint; + if (pend & (1 << 0)) usb_notify_ep0(); - if (daint & (1 << USB_CDC_EP_BULK_IN)) + if (pend & (1 << USB_CDC_EP_BULK_IN)) usb_notify_bulk_in(); } } diff --git a/test/configs/ar100.config b/test/configs/ar100.config new file mode 100644 index 000000000000..5abf7bf6ea40 --- /dev/null +++ b/test/configs/ar100.config @@ -0,0 +1,2 @@ +# Base config file for the ar100 CPU +CONFIG_MACH_AR100=y diff --git a/test/configs/hc32f460-serial-PA3PA2.config b/test/configs/hc32f460-serial-PA3PA2.config new file mode 100644 index 000000000000..bef42ba7e856 --- /dev/null +++ b/test/configs/hc32f460-serial-PA3PA2.config @@ -0,0 +1,3 @@ +# Base config file for boards using HC32F460 +CONFIG_MACH_HC32F460=y +CONFIG_HC32F460_SERIAL_PA3_PA2=y diff --git a/test/configs/stm32g431.config b/test/configs/stm32g431.config new file mode 100644 index 000000000000..79f1816cb225 --- /dev/null +++ b/test/configs/stm32g431.config @@ -0,0 +1,3 @@ +# Base config file for STM32G431 ARM processor +CONFIG_MACH_STM32=y +CONFIG_MACH_STM32G431=y diff --git a/test/configs/stm32h723.config b/test/configs/stm32h723.config new file mode 100644 index 000000000000..0a6e03abfa1f --- /dev/null +++ b/test/configs/stm32h723.config @@ -0,0 +1,3 @@ +# Base config file for STM32H723 ARM processor +CONFIG_MACH_STM32=y +CONFIG_MACH_STM32H723=y diff --git a/test/configs/stm32l412.config b/test/configs/stm32l412.config new file mode 100644 index 000000000000..9e76d645ef9d --- /dev/null +++ b/test/configs/stm32l412.config @@ -0,0 +1,3 @@ +# Base config file for STM32L412 ARM processor +CONFIG_MACH_STM32=y +CONFIG_MACH_STM32L412=y diff --git a/test/klippy/gcode_arcs.test b/test/klippy/gcode_arcs.test index 2be4efc9c251..658ccad0b00e 100644 --- a/test/klippy/gcode_arcs.test +++ b/test/klippy/gcode_arcs.test @@ -2,10 +2,49 @@ DICTIONARY atmega2560.dict CONFIG gcode_arcs.cfg -# Home and move in arcs +# Home and move in XY arc G28 +G90 G1 X20 Y20 Z20 G2 X125 Y32 Z20 E1 I10.5 J10.5 # XY+Z arc move G2 X20 Y20 Z10 E1 I10.5 J10.5 + +# allowable commands +G2 X20 Y20 I0 J10 +G2 X20 Y20 J10 +G2 X20 Y20 I10 J0 +G2 X20 Y20 I10 + +# Home and move in XZ arc +G28 +G90 +G1 X20 Y20 Z20 +G18 +G2 X125 Y20 Z32 E1 I10.5 K10.5 + +# XZ+Y arc move +G2 X20 Y10 Z20 E1 I10.5 K10.5 + +# allowable commands +G2 X20 Y20 I0 K10 +G2 X20 Y20 K10 +G2 X20 Y20 I10 K0 +G2 X20 Y20 I10 + +# Home and move in YZ arc +G28 +G90 +G1 X20 Y20 Z20 +G19 +G2 X20 Y125 Z32 E1 J10.5 K10.5 + +# YZ+X arc move +G2 X10 Y20 Z20 E1 J10.5 K10.5 + +# allowable commands +G2 X20 Y20 J0 K10 +G2 X20 Y20 K10 +G2 X20 Y20 J10 K0 +G2 X20 Y20 J10 diff --git a/test/klippy/printers.test b/test/klippy/printers.test index 243a95a111c5..7194eb46dc69 100644 --- a/test/klippy/printers.test +++ b/test/klippy/printers.test @@ -31,6 +31,7 @@ CONFIG ../../config/printer-anycubic-i3-mega-2017.cfg CONFIG ../../config/printer-anycubic-kossel-2016.cfg CONFIG ../../config/printer-anycubic-kossel-plus-2017.cfg CONFIG ../../config/printer-bq-hephestos-2014.cfg +CONFIG ../../config/printer-creality-cr5pro-ht-2022.cfg CONFIG ../../config/printer-creality-cr10-v3-2020.cfg CONFIG ../../config/printer-creality-cr10s-2017.cfg CONFIG ../../config/printer-creality-cr20-2018.cfg @@ -41,6 +42,7 @@ CONFIG ../../config/printer-flashforge-creator-pro-2018.cfg CONFIG ../../config/printer-hiprecy-leo-2019.cfg CONFIG ../../config/printer-longer-lk4-pro-2019.cfg CONFIG ../../config/printer-lulzbot-mini1-2016.cfg +CONFIG ../../config/printer-lulzbot-mini2-2018.cfg CONFIG ../../config/printer-lulzbot-taz6-2017.cfg CONFIG ../../config/printer-lulzbot-taz6-dual-v3-2017.cfg CONFIG ../../config/printer-makergear-m2-2012.cfg @@ -119,6 +121,11 @@ CONFIG ../../config/printer-modix-big60-2020.cfg DICTIONARY samd51p20.dict CONFIG ../../config/generic-duet3-mini.cfg +# Printers using the SAM E70 +DICTIONARY same70q20b.dict +CONFIG ../../config/generic-duet3-6hc.cfg +CONFIG ../../config/generic-duet3-6xd.cfg + # Printers using the lpc176x DICTIONARY lpc176x.dict CONFIG ../../config/generic-azteeg-x5-mini-v3.cfg @@ -147,6 +154,9 @@ CONFIG ../../config/generic-bigtreetech-skr-mini-e3-v2.0.cfg CONFIG ../../config/generic-bigtreetech-skr-mini-mz.cfg CONFIG ../../config/printer-anycubic-vyper-2021.cfg CONFIG ../../config/printer-monoprice-select-mini-v1-2016.cfg +CONFIG ../../config/printer-sovol-sv05-2022.cfg +CONFIG ../../config/printer-sovol-sv06-2022.cfg +CONFIG ../../config/printer-sunlu-t3-2022.cfg # Printers using the stm32f103 via serial DICTIONARY stm32f103-serial.dict @@ -166,6 +176,7 @@ CONFIG ../../config/printer-creality-ender2pro-2021.cfg CONFIG ../../config/printer-creality-ender3-s1-2021.cfg CONFIG ../../config/printer-creality-ender3-s1plus-2022.cfg CONFIG ../../config/printer-creality-ender3-v2-2020.cfg +CONFIG ../../config/printer-creality-ender3-v2-neo-2022.cfg CONFIG ../../config/printer-creality-ender3max-2021.cfg CONFIG ../../config/printer-creality-ender3pro-2020.cfg CONFIG ../../config/printer-creality-ender5pro-2020.cfg @@ -178,16 +189,20 @@ CONFIG ../../config/printer-flsun-q5-2020.cfg CONFIG ../../config/printer-flsun-qqs-2020.cfg CONFIG ../../config/printer-fokoos-odin5-f3-2021.cfg CONFIG ../../config/printer-geeetech-301-2019.cfg +CONFIG ../../config/printer-kingroon-kp3s-2020.cfg CONFIG ../../config/printer-tronxy-x5sa-v6-2019.cfg CONFIG ../../config/printer-tronxy-x5sa-pro-2020.cfg CONFIG ../../config/printer-tronxy-xy-2-Pro-2020.cfg CONFIG ../../config/printer-twotrees-sapphire-plus-sp-5-v1-2020.cfg CONFIG ../../config/printer-twotrees-sapphire-plus-sp-5-v1.1-2021.cfg CONFIG ../../config/printer-twotrees-sapphire-pro-sp-3-2020.cfg +CONFIG ../../config/printer-voxelab-aquila-2021.cfg # Printers using the stm32f401 DICTIONARY stm32f401.dict +CONFIG ../../config/generic-fysetc-cheetah-v2.0.cfg CONFIG ../../config/printer-artillery-sidewinder-x2-2022.cfg +CONFIG ../../config/printer-elegoo-neptune3-pro-2023.cfg # Printers using the stm32f405 DICTIONARY stm32f405.dict @@ -205,7 +220,7 @@ CONFIG ../../config/generic-mellow-fly-cdy-v3.cfg CONFIG ../../config/generic-mellow-super-infinty-hv.cfg CONFIG ../../config/generic-mks-robin-nano-v3.cfg CONFIG ../../config/generic-prusa-buddy.cfg -CONFIG ../../config/generic-th3d-ezboard-lite-v2.0.cfg +CONFIG ../../config/generic-th3d-ezboard-v2.0.cfg CONFIG ../../config/printer-biqu-b1-se-plus-2022.cfg CONFIG ../../config/printer-prusa-mini-plus-2020.cfg @@ -216,21 +231,35 @@ CONFIG ../../config/generic-fysetc-s6.cfg CONFIG ../../config/generic-fysetc-s6-v2.cfg CONFIG ../../config/generic-fysetc-spider.cfg CONFIG ../../config/generic-mks-rumba32-v1.0.cfg +CONFIG ../../config/printer-ratrig-v-minion-2021.cfg + +# Printers using the stm32h723 +DICTIONARY stm32h723.dict +CONFIG ../../config/generic-bigtreetech-octopus-max-ez.cfg # Printers using the stm32h743 DICTIONARY stm32h743.dict CONFIG ../../config/printer-biqu-bx-2021.cfg +CONFIG ../../config/generic-bigtreetech-skr-3.cfg # Printers using the stm32g0b1 DICTIONARY stm32g0b1.dict CONFIG ../../config/generic-bigtreetech-manta-m4p.cfg -CONFIG ../../config/generic-bigtreetech-manta-m8p.cfg +CONFIG ../../config/generic-bigtreetech-manta-m5p.cfg +CONFIG ../../config/generic-bigtreetech-manta-m8p-v1.0.cfg +CONFIG ../../config/generic-bigtreetech-manta-m8p-v1.1.cfg +CONFIG ../../config/generic-bigtreetech-manta-e3ez.cfg CONFIG ../../config/generic-bigtreetech-skr-mini-e3-v3.0.cfg # Printers using the rp2040 DICTIONARY rp2040.dict CONFIG ../../config/generic-bigtreetech-skr-pico-v1.0.cfg +# Anycubic Printers using trigorilla board with the hc32f460 +DICTIONARY hc32f460-serial-PA3PA2.dict +CONFIG ../../config/printer-anycubic-kobra-go-2022.cfg +CONFIG ../../config/printer-anycubic-kobra-plus-2022.cfg + # Printers using the PRU DICTIONARY pru.dict host=linuxprocess.dict CONFIG ../../config/generic-cramps.cfg diff --git a/test/klippy/tmc.cfg b/test/klippy/tmc.cfg index ffdb93f39c37..4ae85f440eb1 100644 --- a/test/klippy/tmc.cfg +++ b/test/klippy/tmc.cfg @@ -84,6 +84,17 @@ cs_pin: PK1 run_current: .5 sense_resistor: 0.220 +[stepper_z2] +step_pin: PH1 +dir_pin: PA2 +enable_pin: !PA3 +microsteps: 16 +rotation_distance: 8 + +[tmc2240 stepper_z2] +cs_pin: PK3 +run_current: .5 + [mcu] serial: /dev/ttyACM0 diff --git a/test/klippy/tmc.test b/test/klippy/tmc.test index 440534634548..d8af0e6aa9ed 100644 --- a/test/klippy/tmc.test +++ b/test/klippy/tmc.test @@ -19,6 +19,7 @@ DUMP_TMC STEPPER=stepper_y DUMP_TMC STEPPER=stepper_y1 DUMP_TMC STEPPER=stepper_z DUMP_TMC STEPPER=stepper_z1 +DUMP_TMC STEPPER=stepper_z2 ; Test INIT_TMC commands INIT_TMC STEPPER=stepper_x @@ -27,6 +28,7 @@ INIT_TMC STEPPER=stepper_y INIT_TMC STEPPER=stepper_y1 INIT_TMC STEPPER=stepper_z INIT_TMC STEPPER=stepper_z1 +INIT_TMC STEPPER=stepper_z2 ; Test SET_TMC_CURRENT commands SET_TMC_CURRENT STEPPER=stepper_x CURRENT=.7 @@ -35,6 +37,7 @@ SET_TMC_CURRENT STEPPER=stepper_y CURRENT=.7 SET_TMC_CURRENT STEPPER=stepper_y1 CURRENT=.7 SET_TMC_CURRENT STEPPER=stepper_z CURRENT=.7 SET_TMC_CURRENT STEPPER=stepper_z1 CURRENT=.7 +SET_TMC_CURRENT STEPPER=stepper_z2 CURRENT=.6 ; Test SET_TMC_FIELD commands SET_TMC_FIELD STEPPER=stepper_x FIELD=intpol VALUE=0 @@ -43,3 +46,4 @@ SET_TMC_FIELD STEPPER=stepper_y FIELD=intpol VALUE=0 SET_TMC_FIELD STEPPER=stepper_y1 FIELD=intpol VALUE=0 SET_TMC_FIELD STEPPER=stepper_z FIELD=intpol VALUE=0 SET_TMC_FIELD STEPPER=stepper_z1 FIELD=intpol VALUE=0 +SET_TMC_FIELD STEPPER=stepper_z2 FIELD=intpol VALUE=0