Single precision instruction on double precision register value

[philippuk]

Assembly code to produce this issue and the output of different RISC-V implementation

fclass.s s0, fa3
----------------------------------------
Reg_name  Spike             RVEMU             FORVIS            SAIL              
x8/s0/fp  200               4                 200               200  

fadd.s  fa6, fs9, fa3
----------------------------------------
Reg_name  Spike             RVEMU             FORVIS            SAIL              
f16/fa6   nan               0                 ffffffff7fc00000  ffffffff7fc00000  

fnmadd.s ft9, fa7, ft0, fs10
----------------------------------------
Reg_name  Spike             RVEMU             FORVIS            SAIL              
f29/ft9   nan               -0                ffffffff7fc00000  ffffffff7fc00000  

What happened?
Using the reset vector and the assembly listed above, I obtained different register output for the single precision instruction on double precision register value comparing with other RISC-V Simulator. For example, the first test cases fclass.s incorrectly identify the value as negative subnormal number rather than quiet NaN. The following two test cases also demonstrate the cases where the instructions did not handle the double precision value correctly by returning NaN value.

Reset vector

	fscsr	zero
	li    x1,       0
	li    x2,       0
	li    x3,       0
	li    x4,       0
	li    x5,       0
	li    x6,       0
	li    x7,       0
	li    x8,       0
	li    x9,       0
	li    x10,      0
	li    x11,      0
	li    x12,      0
	li    x13,      0
	li    x14,      0
	li    x15,      0
	li    x16,      0
	li    x17,      0
	li    x18,      0
	li    x19,      0
	li    x20,      0
	li    x21,      0
	li    x22,      0
	li    x23,      0
	li    x24,      0
	li    x25,      0
	li    x26,      0
	li    x27,      0
	li    x28,      0
	li    x29,      0
	li    x30,      0
	li    x31,      0
	fcvt.d.w    f0, x0
	fcvt.d.w    f1, x0
	fcvt.d.w    f2, x0
	fcvt.d.w    f3, x0
	fcvt.d.w    f4, x0
	fcvt.d.w    f5, x0
	fcvt.d.w    f6, x0
	fcvt.d.w    f7, x0
	fcvt.d.w    f8, x0
	fcvt.d.w    f9, x0
	fcvt.d.w    f10, x0
	fcvt.d.w    f11, x0
	fcvt.d.w    f12, x0
	fcvt.d.w    f13, x0
	fcvt.d.w    f14, x0
	fcvt.d.w    f15, x0
	fcvt.d.w    f16, x0
	fcvt.d.w    f17, x0
	fcvt.d.w    f18, x0
	fcvt.d.w    f19, x0
	fcvt.d.w    f20, x0
	fcvt.d.w    f21, x0
	fcvt.d.w    f22, x0
	fcvt.d.w    f23, x0
	fcvt.d.w    f24, x0
	fcvt.d.w    f25, x0
	fcvt.d.w    f26, x0
	fcvt.d.w    f27, x0
	fcvt.d.w    f28, x0
	fcvt.d.w    f29, x0
	fcvt.d.w    f30, x0
	fcvt.d.w    f31, x0

[lenawanel]

I think this should be fixed by #36