Trap return address question

[Paulo-D2000]

At

rvemu-for-book/step05/src/trap.rs

Line 34 in 58991b0

let exception_pc = cpu.pc.wrapping_sub(4);

shouldn't the sepc / mepc get loaded with the NEXT instruction PC ? so PC, instead of PC-4 ? After the sret / mret the program would loop back on itself doing the same ecall....

Eg:
0x80000000: ecall, pc is 0x80000004, stvec / mtvec = pc-4 = 0x80000000
... jump to supervisor / machine trap handler
sret / mret from the trap handler
PC = sepc / mepc = 0x80000000 = ecall (again
0x80000000: ecall, pc is 0x80000004, stvec / mtvec = pc-4 = 0x80000000
.... infinite loop...

[Paulo-D2000]

Confirmed this might be a bug since rvemu does use PC not PC-4... https://github.com/d0iasm/rvemu/blob/main/src/interrupt.rs#L45