Question : why read/write SIE register is different from other register?

[huangzixun123]

Excuse me ,I am a new hand, and the particularity of SIE confuses me a lot.
Could me tell me why read/write SIE register is different from other register?

    /// Load a value from a CSR.
    pub fn load_csr(&self, addr: usize) -> u64 {
        match addr {
            SIE => self.csrs[MIE] & self.csrs[MIDELEG],
            _ => self.csrs[addr],
        }
    }

    /// Store a value to a CSR.
    pub fn store_csr(&mut self, addr: usize, value: u64) {
        match addr {
            SIE => {
                self.csrs[MIE] =
                    (self.csrs[MIE] & !self.csrs[MIDELEG]) | (value & self.csrs[MIDELEG]);
            }
            _ => self.csrs[addr] = value,
        }
    }

[xobs]

The SIE and UIE registers are identical copies of the MIE register, except some bits are reserved and cannot be updated.

This is showing how the SIE register offers only partial access when writing to the underlying MIE bits.