diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json
index 5c000811..7148be52 100644
--- a/.devcontainer/devcontainer.json
+++ b/.devcontainer/devcontainer.json
@@ -8,9 +8,9 @@
 	// 	"dockerfile": "open.Dockerfile",
 	// },
 	// Latex container for course materials
-	"name": "Latex",
+	"name": "Computer Architecture Open Source Toolchain Dev",
 	"build": {
-		"dockerfile": "latex.Dockerfile",
+		"dockerfile": "open.Dockerfile",
 	},
 	"customizations": {
 		"vscode": {
@@ -18,7 +18,9 @@
 				"GitHub.vscode-pull-request-github",
 				"james-yu.latex-workshop",
 				"GitHub.copilot",
-				"Bito.Bito"
+				"mshr-h.veriloghdl",
+				"ms-azuretools.vscode-docker",
+				"GitHub.copilot-chat"
 			]
 		}
 	},
@@ -26,7 +28,7 @@
 		"--rm",
 		"--privileged"
 	],
-	// "mounts": ["type=bind,source=/dev,target=/dev"],
+	"mounts": ["type=bind,source=/dev,target=/dev"],
 	// "customizations": {
 	// 	"vscode": {
 	// 		"extensions": [
diff --git a/.devcontainer/open.Dockerfile b/.devcontainer/open.Dockerfile
index f2865eab..631e4056 100644
--- a/.devcontainer/open.Dockerfile
+++ b/.devcontainer/open.Dockerfile
@@ -2,7 +2,7 @@
 FROM ubuntu:22.04
 
 LABEL maintainer="stefan_dan.ciocirlan@upb.ro"
-LABEL version="0.1"
+LABEL version="0.2"
 LABEL description="The open source toolchain docker image for the Computer Architecture course"
 
 # for apt-get
@@ -10,18 +10,39 @@ LABEL description="The open source toolchain docker image for the Computer Archi
 ARG DEBIAN_FRONTEND=noninteractive
 ENV TZ=Europe/Bucharest
 
+# Update Ubuntu Software repository
+# https://stackoverflow.com/questions/39760663/docker-ubuntu-bin-sh-1-locale-gen-not-found
+# https://askubuntu.com/questions/162391/how-do-i-fix-my-locale-issue/229512#229512
 RUN apt-get update && \
     apt-get upgrade -y && \
-    apt-get install -y nano git unzip wget gedit make gcc g++
+    apt-get install -y locales && \
+    locale-gen "en_US.UTF-8" && \
+    dpkg-reconfigure locales
+
+# install basic tools
+RUN apt-get install -y curl sudo zip unzip wget git make gcc g++ nano
+
+# intall texlive-full
+RUN apt-get install -y texlive-full dvipng cm-super
+
 # install gtkwave through apt-get
 # https://github.com/gtkwave/gtkwave
-RUN apt-get install -y gtkwave
-
+# RUN apt-get install -y gtkwave
 # install icaurs
 # https://github.com/steveicarus/iverilog
-RUN apt-get install -y iverilog
-
+# RUN apt-get install -y iverilog
 # install yosys
-RUN apt-get install -y yosys
+# RUN apt-get install -y yosys
 # install verilator
-RUN apt-get install -y verilator
+# RUN apt-get install -y verilator
+RUN apt-get install -y iverilog yosys verilator gtkwave
+
+# install python3 and pip3 for Pygments
+RUN apt-get install -y python3 python3-pip && \
+    pip3 install Pygments
+
+# install java and graphviz
+# RUN apt-get install -y openjdk-19-jre graphviz
+
+# install C/C++ development tools
+# RUN apt-get install -y build-essential gdb clang-format 
\ No newline at end of file
diff --git a/chapters/verilog/behavioral/assigments/alu/.gitignore b/assignments/combinational/alu/.gitignore
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/.gitignore
rename to assignments/combinational/alu/.gitignore
diff --git a/chapters/verilog/behavioral/assigments/alu/Makefile b/assignments/combinational/alu/Makefile
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/Makefile
rename to assignments/combinational/alu/Makefile
diff --git a/assignments/combinational/alu/README.md b/assignments/combinational/alu/README.md
new file mode 100644
index 00000000..155cda8e
--- /dev/null
+++ b/assignments/combinational/alu/README.md
@@ -0,0 +1,31 @@
+# ALU
+Implementați un ALU.
+
+Intările ALU sunt:
+ - i_w_op1 - primul operand (4 biți)
+ - i_w_op2 - al doilea operand (4 biți)
+ - i_w_opsel - operația selectată pentru a fi executată de către ALU (2 biți)
+
+Ieșirea ALU este:
+ - o_w_out - rezultatul operației între cei doi operanzi (4 biți)
+
+Apăsați butonul "evaluate" din VPL pentru a afla operațile pe care trebuie sa le implementați pentru fiecare valoare a intrării i_w_opsel.
+
+Operatiile posibile sunt:
+ - ADDITION - Adunare între cei doi operanzi
+ - SUBTRACTION - Scaderea celui de al doilea operand din primul operand
+ - MULTIPLY - Înmulțirea celor doi operanzi și reținerea în rezultat a celor mai puți semnificativi 4 biți
+ - DIVIDE - Împărțirea primului operand de către al doilea operand
+ - MODULUS - Restul împărțirii primului operand de către al doilea operand
+ - LEFT_SHIFT - Shiftarea la stânga a primului operand cu valoarea celui de al doilea operand
+ - RIGHT_SHIFT - Shiftarea la dreapta a primului operand cu valoarea celui de al doilea operand
+ - ARITHMETIC_RIGHT_SHIFT -Shiftarea aritmetică la dreapta a primului operand cu valoarea celui de al doilea operand
+ - BITWISE_NAND - ȘI-NU între biți celor doi operanzi pe aceleași poziții
+ - BITWISE_NOR - SAU_NU între biți celor doi operanzi pe aceleași poziții
+ - BITWISE_AND - ȘI între biți celor doi operanzi pe aceleași poziții
+ - BITWISE_OR - SAU între biți celor doi operanzi pe aceleași poziții
+ - BITWISE_XOR - SAU-EXCLUSIV între biți celor doi operanzi pe aceleași poziții
+ - COMPARE_EQUAL - Dacă cei doi operazi sunt egali rezultatul va avea valoarea 4'd1 astfel 4'd0.
+ - COMPARE_LESS_THAN - Dacă primul operand este mai mic ca al doilea operand rezultatul va avea valoarea 4'd1 astfel 4'd0.
+ - COMPARE_GREATER_THAN - Dacă primul operand este mai mare ca al doilea operand rezultatul va avea valoarea 4'd1 astfel 4'd0.
+
diff --git a/chapters/verilog/behavioral/assigments/alu/alu.v b/assignments/combinational/alu/alu.v
similarity index 67%
rename from chapters/verilog/behavioral/assigments/alu/alu.v
rename to assignments/combinational/alu/alu.v
index 1170bd30..32a61ccf 100644
--- a/chapters/verilog/behavioral/assigments/alu/alu.v
+++ b/assignments/combinational/alu/alu.v
@@ -4,7 +4,5 @@ module alu(
     input wire [3:0] i_w_op2,
     input wire [1:0 ] i_w_sel
 );
-    
-    //TODO: Implement the digital logic for the 7-segment display
 
 endmodule
\ No newline at end of file
diff --git a/chapters/verilog/behavioral/assigments/alu/bigalu.v b/assignments/combinational/alu/bigalu.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/bigalu.v
rename to assignments/combinational/alu/bigalu.v
diff --git a/chapters/verilog/behavioral/assigments/alu/evaluate_alu.v b/assignments/combinational/alu/evaluate_alu.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/evaluate_alu.v
rename to assignments/combinational/alu/evaluate_alu.v
diff --git a/chapters/verilog/basic/assigments/mux/grade.sh b/assignments/combinational/alu/grade.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/grade.sh
rename to assignments/combinational/alu/grade.sh
diff --git a/chapters/verilog/behavioral/assigments/alu/sol.v b/assignments/combinational/alu/sol.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/sol.v
rename to assignments/combinational/alu/sol.v
diff --git a/chapters/verilog/behavioral/assigments/alu/test_alu.v b/assignments/combinational/alu/test_alu.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/test_alu.v
rename to assignments/combinational/alu/test_alu.v
diff --git a/chapters/verilog/behavioral/assigments/alu/test_sol.v b/assignments/combinational/alu/test_sol.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/test_sol.v
rename to assignments/combinational/alu/test_sol.v
diff --git a/chapters/verilog/behavioral/assigments/alu/vpl_evaluate.sh b/assignments/combinational/alu/vpl_evaluate.sh
old mode 100755
new mode 100644
similarity index 90%
rename from chapters/verilog/behavioral/assigments/alu/vpl_evaluate.sh
rename to assignments/combinational/alu/vpl_evaluate.sh
index 5ebd0208..1b815e6b
--- a/chapters/verilog/behavioral/assigments/alu/vpl_evaluate.sh
+++ b/assignments/combinational/alu/vpl_evaluate.sh
@@ -19,7 +19,7 @@ else
     variation=$(expr $variation - 1)
 fi
 
-op_vector=('ADDITION' 'SUBTRACTION' 'AND' 'OR' 'XOR' 'LEFT_SHIFT' 'RIGHT_SHIFT' 'ARITHMETIC_RIGHT_SHIFT' 'MULTIPLY' 'DIVIDE' 'MODULUS' 'COMPARE_EQUAL' 'COMPARE_LESS_THAN' 'COMPARE_GREATER_THAN' 'NAND' 'NOR')
+op_vector=('ADDITION' 'SUBTRACTION' 'BITWISE_AND' 'BITWISE_OR' 'BITWISE_XOR' 'LEFT_SHIFT' 'RIGHT_SHIFT' 'ARITHMETIC_RIGHT_SHIFT' 'MULTIPLY' 'DIVIDE' 'MODULUS' 'COMPARE_EQUAL' 'COMPARE_LESS_THAN' 'COMPARE_GREATER_THAN' 'BITWISE_NAND' 'BITWISE_NOR')
 op_sel=()
 op_value=$variation
 i=0
diff --git a/chapters/verilog/behavioral/assigments/alu/vpl_run.sh b/assignments/combinational/alu/vpl_run.sh
old mode 100755
new mode 100644
similarity index 85%
rename from chapters/verilog/behavioral/assigments/alu/vpl_run.sh
rename to assignments/combinational/alu/vpl_run.sh
index 1b58c8fb..52480096
--- a/chapters/verilog/behavioral/assigments/alu/vpl_run.sh
+++ b/assignments/combinational/alu/vpl_run.sh
@@ -18,7 +18,7 @@ else
 fi
 
 
-op_vector=('ADDITION' 'SUBTRACTION' 'AND' 'OR' 'XOR' 'LEFT_SHIFT' 'RIGHT_SHIFT' 'ARITHMETIC_RIGHT_SHIFT' 'MULTIPLY' 'DIVIDE' 'MODULUS' 'COMPARE_EQUAL' 'COMPARE_LESS_THAN' 'COMPARE_GREATER_THAN' 'NAND' 'NOR')
+op_vector=('ADDITION' 'SUBTRACTION' 'BITWISE_AND' 'BITWISE_OR' 'BITWISE_XOR' 'LEFT_SHIFT' 'RIGHT_SHIFT' 'ARITHMETIC_RIGHT_SHIFT' 'MULTIPLY' 'DIVIDE' 'MODULUS' 'COMPARE_EQUAL' 'COMPARE_LESS_THAN' 'COMPARE_GREATER_THAN' 'BITWISE_NAND' 'BITWISE_NOR')
 op_sel=()
 op_value=\$variation
 i=0
diff --git a/chapters/verilog/behavioral/assigments/led7/.gitignore b/assignments/combinational/comb/.gitignore
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/.gitignore
rename to assignments/combinational/comb/.gitignore
diff --git a/chapters/verilog/operators/assigments/comb/Makefile b/assignments/combinational/comb/Makefile
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/Makefile
rename to assignments/combinational/comb/Makefile
diff --git a/assignments/combinational/comb/README.md b/assignments/combinational/comb/README.md
new file mode 100644
index 00000000..b36edb43
--- /dev/null
+++ b/assignments/combinational/comb/README.md
@@ -0,0 +1,26 @@
+# True Table
+
+Implmentați modulul verilog pentru tabelul de adevăr dat.
+
+Veți avea 3 intrări:
+ - i_w_a
+ - i_w_b
+ - i_w_c
+
+Veți avea o singură ieșire:
+ - o_w_out
+
+Apăsați butonul "evaluate" din VPL pentru a afla tabelul de adevăr pe care trebuie să îl implementați.
+
+Exemplu de tabel:
+
+| i_w_a | i_w_b | i_w_c | o_w_out |
+|-------|-------|-------|---------|
+|     0 |     0 |     0 |       1 |
+|     0 |     0 |     1 |       1 |
+|     0 |     1 |     0 |       1 |
+|     0 |     1 |     1 |       0 |
+|     1 |     0 |     0 |       0 |
+|     1 |     0 |     1 |       0 |
+|     1 |     1 |     0 |       0 |
+|     1 |     1 |     1 |       0 |
\ No newline at end of file
diff --git a/chapters/verilog/operators/assigments/comb/comb.v b/assignments/combinational/comb/comb.v
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/comb.v
rename to assignments/combinational/comb/comb.v
diff --git a/chapters/verilog/operators/assigments/comb/evaluate_comb.v b/assignments/combinational/comb/evaluate_comb.v
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/evaluate_comb.v
rename to assignments/combinational/comb/evaluate_comb.v
diff --git a/chapters/verilog/behavioral/assigments/alu/grade.sh b/assignments/combinational/comb/grade.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/behavioral/assigments/alu/grade.sh
rename to assignments/combinational/comb/grade.sh
diff --git a/chapters/verilog/operators/assigments/comb/mux.v b/assignments/combinational/comb/mux.v
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/mux.v
rename to assignments/combinational/comb/mux.v
diff --git a/chapters/verilog/operators/assigments/comb/sol.v b/assignments/combinational/comb/sol.v
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/sol.v
rename to assignments/combinational/comb/sol.v
diff --git a/chapters/verilog/operators/assigments/comb/test_comb.v b/assignments/combinational/comb/test_comb.v
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/test_comb.v
rename to assignments/combinational/comb/test_comb.v
diff --git a/chapters/verilog/operators/assigments/comb/test_sol.v b/assignments/combinational/comb/test_sol.v
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/test_sol.v
rename to assignments/combinational/comb/test_sol.v
diff --git a/chapters/verilog/operators/assigments/comb/vpl_evaluate.sh b/assignments/combinational/comb/vpl_evaluate.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/vpl_evaluate.sh
rename to assignments/combinational/comb/vpl_evaluate.sh
diff --git a/chapters/verilog/operators/assigments/comb/vpl_run.sh b/assignments/combinational/comb/vpl_run.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/vpl_run.sh
rename to assignments/combinational/comb/vpl_run.sh
diff --git a/chapters/verilog/operators/assigments/comb/.gitignore b/assignments/combinational/led7/.gitignore
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/.gitignore
rename to assignments/combinational/led7/.gitignore
diff --git a/chapters/verilog/behavioral/assigments/led7/Makefile b/assignments/combinational/led7/Makefile
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/Makefile
rename to assignments/combinational/led7/Makefile
diff --git a/assignments/combinational/led7/README.md b/assignments/combinational/led7/README.md
new file mode 100644
index 00000000..4a5f3082
--- /dev/null
+++ b/assignments/combinational/led7/README.md
@@ -0,0 +1,32 @@
+# 7-LED Segment DIGIT
+Implementați un modul verilog care să afișeze in funcție de o intrare de selecție una din cele 4 cifre date (XYZT).
+
+Intrările modulului sunt:
+ - i_w_sel - ce cifră se va afișa (2 biți)
+
+Ieșirele modulului sunt:
+ - o_w_ca - linia ca din 7-led segment
+ - o_w_cb - linia cb din 7-led segment
+ - o_w_cc - linia cc din 7-led segment
+ - o_w_cd - linia cd din 7-led segment
+ - o_w_ce - linia ce din 7-led segment
+ - o_w_cf - linia cf din 7-led segment
+ - o_w_cg - linia cg din 7-led segment
+
+Ca sa aflați cele 4 cifre XYZT apăsați butonul "evaluate" din VPL.
+
+Pentru valorile i_w_sel:
+ - i_w_sel = 2'd0, se va afișa cifra T
+ - i_w_sel = 2'd1, se va afișa cifra Z
+ - i_w_sel = 2'd2, se va afișa cifra Y
+ - i_w_sel = 2'd3, se va afișa cifra X
+
+Avem un 7-led segment cu anod comun și ieșirele vor fi active când vor avea valoarea 1'b0.
+
+Mai jos puteți vedea cum sunt poziționate linile cx ale 7-led segment.
+
+![7-LED-SEGMENT](media/led7.jpg)
+
+Mai jos puteți vedea cum sunt afișate cifrele zecimale pe un 7-led segment.
+
+![7-LED-DIGITS](media/7leddigits.png)
\ No newline at end of file
diff --git a/chapters/verilog/behavioral/assigments/led7/evaluate_led7.v b/assignments/combinational/led7/evaluate_led7.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/evaluate_led7.v
rename to assignments/combinational/led7/evaluate_led7.v
diff --git a/chapters/verilog/behavioral/assigments/led7/led7.v b/assignments/combinational/led7/led7.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/led7.v
rename to assignments/combinational/led7/led7.v
diff --git a/chapters/verilog/behavioral/assigments/led7/led7conv.v b/assignments/combinational/led7/led7conv.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/led7conv.v
rename to assignments/combinational/led7/led7conv.v
diff --git a/chapters/verilog/behavioral/assigments/led7/7leddigits.png b/assignments/combinational/led7/media/7leddigits.png
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/7leddigits.png
rename to assignments/combinational/led7/media/7leddigits.png
diff --git a/chapters/verilog/behavioral/assigments/led7/led7jpg b/assignments/combinational/led7/media/led7.jpg
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/led7jpg
rename to assignments/combinational/led7/media/led7.jpg
diff --git a/chapters/verilog/behavioral/assigments/led7/sol.v b/assignments/combinational/led7/sol.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/sol.v
rename to assignments/combinational/led7/sol.v
diff --git a/chapters/verilog/behavioral/assigments/led7/test_led7.v b/assignments/combinational/led7/test_led7.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/test_led7.v
rename to assignments/combinational/led7/test_led7.v
diff --git a/chapters/verilog/behavioral/assigments/led7/test_sol.v b/assignments/combinational/led7/test_sol.v
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/test_sol.v
rename to assignments/combinational/led7/test_sol.v
diff --git a/chapters/verilog/behavioral/assigments/led7/vpl_evaluate.sh b/assignments/combinational/led7/vpl_evaluate.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/vpl_evaluate.sh
rename to assignments/combinational/led7/vpl_evaluate.sh
diff --git a/chapters/verilog/behavioral/assigments/led7/vpl_run.sh b/assignments/combinational/led7/vpl_run.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/vpl_run.sh
rename to assignments/combinational/led7/vpl_run.sh
diff --git a/chapters/verilog/behavioral/assigments/led7/grade.sh b/assignments/common/grade.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/behavioral/assigments/led7/grade.sh
rename to assignments/common/grade.sh
diff --git a/assignments/common/variation.sh b/assignments/common/variation.sh
new file mode 100644
index 00000000..3dfa5317
--- /dev/null
+++ b/assignments/common/variation.sh
@@ -0,0 +1,12 @@
+#!/bin/bash
+variation=$(date +"%d%H")
+# make sure variation is a number
+variation=$(expr $variation + 0)
+# variation will be the same for 2 consecutive hours
+if [ $((variation % 2)) == 0 ]; then
+    variation=variation
+else
+    variation=$(expr $variation - 1)
+fi
+
+echo $variation
\ No newline at end of file
diff --git a/assignments/projects/fpu/.gitignore b/assignments/projects/fpu/.gitignore
new file mode 100644
index 00000000..a9d3f221
--- /dev/null
+++ b/assignments/projects/fpu/.gitignore
@@ -0,0 +1,4 @@
+*.vvp
+*.vcd
+vpl_execution
+fpu
\ No newline at end of file
diff --git a/assignments/projects/fpu/Makefile b/assignments/projects/fpu/Makefile
new file mode 100644
index 00000000..bbb6ce66
--- /dev/null
+++ b/assignments/projects/fpu/Makefile
@@ -0,0 +1,36 @@
+COMPILER=iverilog
+INTERPRETER=vvp
+FLAGS=-Wall -Winfloop
+TOP_MODULE=fpu
+TOP_SIM_MODULE=test_${TOP_MODULE}
+TOP_EVALUATE_MODULE=evaluate_${TOP_MODULE}
+OTHER_SOURCES=
+RESULT_FILE=result.out
+EVALUATE_FILE=evaluate.out
+GRADE_SCRIPT=grade.sh
+EVALUATE_FLAGS=+INPUT_FILE=$(RESULT_FILE)
+GENERATOR_COMPILER=g++ -std=c++20
+GENERATOR_SOURCE=fpu.cpp
+GENERATOR_BINARY=fpu
+
+all: build
+
+build:
+	$(COMPILER) $(FLAGS) $(TOP_MODULE).v $(TOP_SIM_MODULE).v $(OTHER_SOURCES) -o $(TOP_MODULE).vvp
+
+build_evaluate:
+	$(GENERATOR_COMPILER) -o $(GENERATOR_BINARY) $(GENERATOR_SOURCE)
+	./$(GENERATOR_BINARY) $(RESULT_FILE)
+	$(COMPILER) $(FLAGS) ${TOP_MODULE}.v ${TOP_EVALUATE_MODULE}.v $(OTHER_SOURCES) -o $(TOP_EVALUATE_MODULE).vvp
+
+run: build
+	$(INTERPRETER) $(TOP_MODULE).vvp
+
+run_evaluate: build_evaluate
+	$(INTERPRETER) $(TOP_EVALUATE_MODULE).vvp $(EVALUATE_FLAGS) > $(EVALUATE_FILE) 2>&1
+
+evaluate: run_evaluate
+	./${GRADE_SCRIPT} $(EVALUATE_FILE)
+
+clean:
+	rm *.vvp $(DUMP_VCD_FILE) $(EVALUATE_FILE) $(RESULT_FILE) $(GENERATOR_BINARY)
diff --git a/assignments/projects/fpu/README.md b/assignments/projects/fpu/README.md
new file mode 100644
index 00000000..313f72e9
--- /dev/null
+++ b/assignments/projects/fpu/README.md
@@ -0,0 +1,36 @@
+# FPU
+
+Implmentați modulul verilog pentru un FPU (floating point unit) cu 2 operanzi 32-bits IEEE754.
+
+Intrările sunt:
+ - i_w_op1 - primul operand (32 de biți)
+ - i_w_op2 - al doilea operand (32 biți)
+ - i_w_opsel - linie de selecție a operației (3 biți)
+
+Ieșirea este:
+ - o_w_out - rezultatul operației între cei doi operanzi (32 biți)
+
+Operațiile sunt:
+
+| Operation Code (i_w_opsel) | Operation       | Result  |
+|--------------------------|-----------------|-------|
+| 000                      | Addition        | op1 + op2    |
+| 001                      | Subtraction     | op1 - op2    |
+| 010                      | Multiplication  | op1 * op2     |
+| 011                      | Division        | op1 / op2     |
+| 100                      | Negation        | -op1     |
+| 101                      | Absolute Value  | \|op1\|   |
+| 110                      | Less than       | op1 < op2    |
+| 111                      | Equal           | op1 == op2   |
+
+Standardul IEEE754 poate fi găsit la următorul [link](https://curs.upb.ro/2024/mod/resource/view.php?id=46321).
+
+Pentru a vă ajuta în rezolvare avem următoarele materiale video:
+ - [Reprezentare IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EdT8OQWyXc9MvafVmUvP1_wBW3bESoQJ7kAXzvPbNLJyYg?e=rXFLan&nav=eyJwbGF5YmFja09wdGlvbnMiOnt9LCJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJTdHJlYW1XZWJBcHAiLCJyZWZlcnJhbE1vZGUiOiJtaXMiLCJyZWZlcnJhbFZpZXciOiJwb3N0cm9sbC1jb3B5bGluayIsInJlZmVycmFsUGxheWJhY2tTZXNzaW9uSWQiOiJlN2FhMThmZi02ZDk0LTQ5YWMtYWM0NC0yMDRmNGMyNTA4MjEifX0%3D)
+ - [Adunare IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EZ1mlBsUVxRApccFv7Rj4JQBrZwYJ1JCb80YVsfhyqgWkw?nav=eyJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJPbmVEcml2ZUZvckJ1c2luZXNzIiwicmVmZXJyYWxBcHBQbGF0Zm9ybSI6IldlYiIsInJlZmVycmFsTW9kZSI6InZpZXciLCJyZWZlcnJhbFZpZXciOiJNeUZpbGVzTGlua0NvcHkifX0&e=t23cOK)
+ - [Scădere IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EYp6Tk2nUONPiySrwgjl83EBahG2wOaPyreZWE2EQ3mFDw?nav=eyJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJPbmVEcml2ZUZvckJ1c2luZXNzIiwicmVmZXJyYWxBcHBQbGF0Zm9ybSI6IldlYiIsInJlZmVycmFsTW9kZSI6InZpZXciLCJyZWZlcnJhbFZpZXciOiJNeUZpbGVzTGlua0NvcHkifX0&e=lVwmop)
+ - [Înmulțire IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EcWX-oXDWU5KnyecEDasxjoBHSzzf-8NvoZyCfo8Ca_9fg?nav=eyJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJPbmVEcml2ZUZvckJ1c2luZXNzIiwicmVmZXJyYWxBcHBQbGF0Zm9ybSI6IldlYiIsInJlZmVycmFsTW9kZSI6InZpZXciLCJyZWZlcnJhbFZpZXciOiJNeUZpbGVzTGlua0NvcHkifX0&e=qbElkD)
+ - [Împărțire 1 IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EVWvarvhvUZAlG80QO32SaQByTHOZLsjb5z6TDz1iio1gg?nav=eyJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJPbmVEcml2ZUZvckJ1c2luZXNzIiwicmVmZXJyYWxBcHBQbGF0Zm9ybSI6IldlYiIsInJlZmVycmFsTW9kZSI6InZpZXciLCJyZWZlcnJhbFZpZXciOiJNeUZpbGVzTGlua0NvcHkifX0&e=pm3lPI)
+ - [Împărțire 2 IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EaU-1JasofxGpIesR43Od7wBQI93emIt51zO4YVaFstI4Q?nav=eyJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJPbmVEcml2ZUZvckJ1c2luZXNzIiwicmVmZXJyYWxBcHBQbGF0Zm9ybSI6IldlYiIsInJlZmVycmFsTW9kZSI6InZpZXciLCJyZWZlcnJhbFZpZXciOiJNeUZpbGVzTGlua0NvcHkifX0&e=HNlxCk)
+ - [Operații Relaționale IEEE754](https://ctipub-my.sharepoint.com/:v:/g/personal/stefan_dan_ciocirlan_upb_ro/EeCqdJoCAaxBq0f0fjSPbTMBbRsiFfuubVkHrR7qb4Aa4A?nav=eyJyZWZlcnJhbEluZm8iOnsicmVmZXJyYWxBcHAiOiJPbmVEcml2ZUZvckJ1c2luZXNzIiwicmVmZXJyYWxBcHBQbGF0Zm9ybSI6IldlYiIsInJlZmVycmFsTW9kZSI6InZpZXciLCJyZWZlcnJhbFZpZXciOiJNeUZpbGVzTGlua0NvcHkifX0&e=eXKb4E)
+ - [Rounding IEEE754](https://youtu.be/wbxSTxhTmrs?t=529)
diff --git a/assignments/projects/fpu/evaluate_fpu.v b/assignments/projects/fpu/evaluate_fpu.v
new file mode 100644
index 00000000..0142b317
--- /dev/null
+++ b/assignments/projects/fpu/evaluate_fpu.v
@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+module evaluate_fpu();
+    //Inputs
+    reg[31:0] l_r_op1;
+    reg[31:0] l_r_op2;
+    reg[2:0] l_r_sel;
+    reg[2:0] l_r_aux_sel;
+
+    //Outputs
+    wire[31:0] l_w_out;
+
+    //Expected outputs
+    reg[31:0] l_r_out;
+    
+    //local variables for loop
+    integer i, j, k;
+    integer file_descriptor;
+    integer scan_result;
+    reg[127:0] input_file;
+    
+    //Module initialization
+    fpu uut (
+        .o_w_out(l_w_out),
+        .i_w_op1(l_r_op1),
+        .i_w_op2(l_r_op2),
+        .i_w_opsel(l_r_sel)
+    );
+
+    //Simulation tests
+    initial begin
+
+        //get from the command line the input file
+        if (!$value$plusargs("INPUT_FILE=%s", input_file)) begin
+            $display("Error: You must specify the input file");
+            $finish;
+        end
+
+        for (i=0; i<8; i=i+1) begin
+            l_r_sel = i;
+            file_descriptor = $fopen(input_file, "r");
+            if (file_descriptor == 0) begin
+                $display("Error opening file");
+                $finish;
+            end
+            #5;
+
+            while (!$feof(file_descriptor)) begin
+                scan_result = $fscanf(file_descriptor, "%h ", l_r_op1);
+                scan_result = $fscanf(file_descriptor, "%h ", l_r_op2);
+                scan_result = $fscanf(file_descriptor, "%h ", l_r_aux_sel);
+                scan_result = $fscanf(file_descriptor, "%h\n", l_r_out);
+
+                if (l_r_aux_sel == l_r_sel) begin
+                    #5;
+                    if (l_r_out !== l_w_out) begin
+                        $display("Error: (hex_values) l_w_out = %0h correct %0h, op1 = %0h, op2 = %0h, sel = %0h", l_w_out, l_r_out, l_r_op1, l_r_op2, l_r_sel);
+                    end else begin
+                        $display("OK");
+                    end
+                    #5;
+                end
+            end
+            $fclose(file_descriptor);
+            #5;
+        end
+        //finish the simulation
+        $finish;
+    end
+endmodule
diff --git a/assignments/projects/fpu/fpu.cpp b/assignments/projects/fpu/fpu.cpp
new file mode 100644
index 00000000..9d3ec38e
--- /dev/null
+++ b/assignments/projects/fpu/fpu.cpp
@@ -0,0 +1,109 @@
+#include <iostream>
+#include <fstream>
+#include <random>
+#include <limits>
+#include <bitset>
+#include <sstream>
+#include <iomanip>
+#include <fenv.h>
+
+/*
+| Operation Code (i_w_sel) | Operation       |
+|--------------------------|-----------------|
+| 000                      | Addition        |
+| 001                      | Subtraction     |
+| 010                      | Multiplication  |
+| 011                      | Division        |
+| 100                      | Negation        |
+| 101                      | Absolute Value  |
+| 110                      | Less than       |
+| 111                      | Equal           |
+*/
+
+std::string floatToBinary(float value) {
+    union {
+        float input;
+        int output;
+    } data;
+    data.input = value;
+    std::bitset<sizeof(float) * 8> bits(data.output);
+    return bits.to_string();
+}
+
+std::string intToBinary(int value, int bits) {
+    std::bitset<32> bitset(value);
+    return bitset.to_string().substr(32 - bits, bits);
+}
+
+std::string floatToHex(float value) {
+    union {
+        float input;
+        int output;
+    } data;
+    data.input = value;
+    std::stringstream ss;
+    ss << std::hex << std::setw(8) << std::setfill('0') << data.output;
+    return ss.str();
+}
+
+std::string intToHex(int value, int hex_digits = 8) {
+    std::stringstream ss;
+    ss << std::hex << std::setw(hex_digits) << std::setfill('0') << value;
+    return ss.str();
+}
+
+int main(int argc, char* argv[]) {
+    if (argc != 2) {
+        std::cerr << "Usage: " << argv[0] << " <output_file>" << std::endl;
+        return 1;
+    }
+    std::string output_file = argv[1];
+    fesetround(FE_TONEAREST);
+    std::mt19937 gen(0);
+    std::normal_distribution<float> normal_dis(0.0f, 1e3);
+
+
+    std::ofstream outfile(output_file);
+    if (!outfile) {
+        std::cerr << "Error opening file for writing" << std::endl;
+        return 1;
+    }
+    
+    for (int i = 0; i < 1000; i++) {
+        float a = normal_dis(gen);
+        float b = normal_dis(gen);
+        float result;
+        for (int i_w_sel = 0; i_w_sel < 8; i_w_sel++) {
+            switch (i_w_sel) {
+                case 0:
+                    result = a + b;
+                    break;
+                case 1:
+                    result = a - b;
+                    break;
+                case 2:
+                    result = a * b;
+                    break;
+                case 3:
+                    result = a / b;
+                    break;
+                case 4:
+                    result = -a;
+                    break;
+                case 5:
+                    result = std::abs(a);
+                    break;
+                case 6:
+                    result = a < b;
+                    break;
+                case 7:
+                    if (a < b) a = b;
+                    result = a == b;
+                    break;
+            }
+            outfile << floatToHex(a) << " " << floatToHex(b) << " " << intToHex(i_w_sel, 1) << " " << floatToHex(result) << std::endl;
+        }
+    }
+    outfile.close();
+    return 0;
+}
\ No newline at end of file
diff --git a/assignments/projects/fpu/fpu.v b/assignments/projects/fpu/fpu.v
new file mode 100644
index 00000000..2fd5c4e8
--- /dev/null
+++ b/assignments/projects/fpu/fpu.v
@@ -0,0 +1,8 @@
+module fpu(
+    output wire [31:0] o_w_out,
+    input wire [31:0] i_w_op1,
+    input wire [31:0] i_w_op2,
+    input wire [2:0] i_w_opsel
+);
+
+endmodule
\ No newline at end of file
diff --git a/chapters/verilog/operators/assigments/comb/grade.sh b/assignments/projects/fpu/grade.sh
old mode 100755
new mode 100644
similarity index 100%
rename from chapters/verilog/operators/assigments/comb/grade.sh
rename to assignments/projects/fpu/grade.sh
diff --git a/assignments/projects/fpu/test_fpu.v b/assignments/projects/fpu/test_fpu.v
new file mode 100644
index 00000000..2b9d68d7
--- /dev/null
+++ b/assignments/projects/fpu/test_fpu.v
@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+module test_fpu;
+    //Inputs
+    reg[31:0] l_r_op1;
+    reg[31:0] l_r_op2;
+    reg[2:0] l_r_sel;
+
+    //Outputs
+    wire[31:0] l_w_out;
+    
+    //local variables for loop
+    integer i, j, k;
+    
+    //Module initialization
+    fpu uut (
+        .o_w_out(l_w_out),
+        .i_w_op1(l_r_op1),
+        .i_w_op2(l_r_op2),
+        .i_w_opsel(l_r_sel)
+    );
+
+    //Simulation tests
+    initial begin
+        // monitor varibles changes in values
+        $monitor(
+            "Time = %0t, ", $time,
+            "l_w_out = %0h, ", l_w_out,
+            "l_r_op1 = %0h, ", l_r_op1,
+            "l_r_op2 = %0h, ", l_r_op2,
+            "l_r_sel = %0h, ", l_r_sel
+            );
+        
+        l_r_op1 = 32'b0010;
+        l_r_op2 = 32'b0100;
+        l_r_sel = 3'b000;
+        #10;
+        l_r_sel = 3'b01;
+        #10;
+        l_r_sel = 3'b10;
+        #10;
+        l_r_sel = 3'b11;
+        #10;
+        //finish the simulation
+        $finish;
+    end
+endmodule
diff --git a/assignments/projects/fpu/vpl_evaluate.sh b/assignments/projects/fpu/vpl_evaluate.sh
new file mode 100644
index 00000000..50829f97
--- /dev/null
+++ b/assignments/projects/fpu/vpl_evaluate.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+#
+# vpl_evaluate.sh script 
+
+source common_script.sh
+
+TOP_MODULE=fpu
+TOP_EVALUATE_MODULE=evaluate_${TOP_MODULE}
+OTHER_SOURCES=
+maxGrade=100
+RESULT_FILE=result.out
+EVALUATE_FILE=evaluate.out
+GRADE_SCRIPT=grade.sh
+EVALUATE_FLAGS="+INPUT_FILE=${RESULT_FILE}"
+GENERATOR_COMPILER="g++ -std=c++20"
+GENERATOR_SOURCE=fpu.cpp
+GENERATOR_BINARY=fpu
+
+
+# Build the generator code
+$GENERATOR_COMPILER $GENERATOR_SOURCE -o $GENERATOR_BINARY
+chmod +x $GENERATOR_BINARY
+
+# Generate the testbench
+./$GENERATOR_BINARY ${RESULT_FILE}
+
+# BUILD the code
+iverilog ${TOP_MODULE}.v ${TOP_EVALUATE_MODULE}.v ${OTHER_SOURCES} -o ${TOP_EVALUATE_MODULE}.vvp
+# RUN the code
+vvp ${TOP_EVALUATE_MODULE}.vvp  ${EVALUATE_FLAGS} > ${EVALUATE_FILE} 2>&1
+
+
+#--- remove multiple spaces --- 
+cat ${EVALUATE_FILE} | sed 's/  */ /g' > dummy.out
+mv dummy.out ${EVALUATE_FILE}
+
+#--- remove blank lines ---
+cat ${EVALUATE_FILE} | sed '/^\s*$/d' > dummy.out
+mv dummy.out ${EVALUATE_FILE}
+
+# Calculate number of correct test versus wrong test
+correct_test_no=$(awk '$1=="OK" { print $0 }' ${EVALUATE_FILE} | wc -l | awk '{ print $1 }')
+test_no=$(wc -l ${EVALUATE_FILE} | awk '{ print $1 }')
+grade=$( expr $correct_test_no \* 100 / $test_no)
+
+echo "#!/bin/bash" > vpl_execution
+
+# if not max grade print the first error line
+if (( $grade < $maxGrade )) ; then
+text=$(awk '$1!="OK" { print $0 }' ${EVALUATE_FILE} | awk 'NR==1 { print $0 }')
+echo "echo '$text' " >> vpl_execution
+echo $text
+fi
+
+echo "echo 'Grade :=>> $grade' " >> vpl_execution
+ 
+chmod +x vpl_execution
\ No newline at end of file
diff --git a/assignments/projects/fpu/vpl_run.sh b/assignments/projects/fpu/vpl_run.sh
new file mode 100644
index 00000000..dda6e69b
--- /dev/null
+++ b/assignments/projects/fpu/vpl_run.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# vpl_run.sh script 
+
+cat > vpl_execution <<EEOOFF
+#!/bin/bash
+
+# Variables
+TOP_MODULE=fpu
+TOP_SIM_MODULE=test_\$TOP_MODULE
+OTHER_SOURCES=
+
+
+# Generate the testbench
+iverilog -o \${TOP_MODULE}.vvp \${TOP_MODULE}.v \${TOP_SIM_MODULE}.v \${OTHER_SOURCES}
+# Run the testbench
+vvp \${TOP_MODULE}.vvp &> user.out
+# SHOW the output
+cat user.out
+
+EEOOFF
+
+chmod +x vpl_execution
\ No newline at end of file
diff --git a/assignments/sequential/flagram/.gitignore b/assignments/sequential/flagram/.gitignore
new file mode 100644
index 00000000..683b9244
--- /dev/null
+++ b/assignments/sequential/flagram/.gitignore
@@ -0,0 +1,3 @@
+*.vvp
+*.vcd
+vpl_execution
\ No newline at end of file
diff --git a/assignments/sequential/flagram/README.md b/assignments/sequential/flagram/README.md
new file mode 100644
index 00000000..5d8578a5
--- /dev/null
+++ b/assignments/sequential/flagram/README.md
@@ -0,0 +1,33 @@
+# FLAG-RAM
+Implementati un modul ce va contine o memorie RAM (4 biti de adresare si 4 biti de date) si un registru de flag-uri ce va contine informatii despre ultimul cuvant citit din memoria RAM. Modulul ram este dat si prezent in fisierul "ram.v" (NU MODIFICATI, DOAR INSTANTIATI IN MODULUL VOSTRU). O implementare de registrul este prezenta in fisierul "register.v" (Folosirea lui este optionala).
+
+Modulul de implementat are urmatoarele intrari:
+ - i_w_clk - ceas
+ - i_w_address -  adresa de memorie ram
+ - i_w_data - data de intrare pe 4 biti
+ - i_w_we - daca se scrie in RAM
+ - i_w_oe - daca se afiseaza din RAM
+ - i_w_flag_out - daca se afiseaza valorea registrului flag (activ pozitiv 1'b1)
+
+Ieșirea modulului este:
+ - o_w_out - datele citite din RAM sau valoarea registrului flag
+
+Ordinea de prioritate a operaților este (i_w_we > i_w_oe > i_w_flag_out).
+
+Registrul flag va avea 4 biti si va avea de implementat 4 flag-uri. Veti afla flag-urile de implementat si pozitia lor dupa apasarea butonului "evaluate" din VPL.
+
+Flag-uri posibile:
+ - Z - if all bits are unset
+ - S - if the sign bit is set (MSB)
+ - E - if it has an even number of bits set
+ - O - if it has an odd number of bits set
+ - C3 - if the bit on the position 3 is set
+ - S3 - if the bit on the position 3 is set
+ - G4 - if the data value is greater than 4
+ - L4 - if the data value is lower than 4
+ - POW - if the data value is a power of 2 (1,4,8,16)
+ - SMAX - if the data value is the maximum signed value
+ - SMIN - if the data value is the minimum signed value
+ - MAX - if the data value is the maximum unsigned value
+ - PAL - if the data value is a binary palindrome (0110 -1, 1010-0)
+ - SB2 - if there are at least 2 consecutive bits set (1100-1, 0101-0)
\ No newline at end of file
diff --git a/assignments/sequential/fsm/.gitignore b/assignments/sequential/fsm/.gitignore
new file mode 100644
index 00000000..683b9244
--- /dev/null
+++ b/assignments/sequential/fsm/.gitignore
@@ -0,0 +1,3 @@
+*.vvp
+*.vcd
+vpl_execution
\ No newline at end of file
diff --git a/assignments/sequential/fsm/README.md b/assignments/sequential/fsm/README.md
new file mode 100644
index 00000000..49195ce1
--- /dev/null
+++ b/assignments/sequential/fsm/README.md
@@ -0,0 +1,16 @@
+# FSM
+Se dorește proiectarea unui FSM capabil să recunoască o SECVENTA de caractere data.
+
+FSM va avea ca intrări:
+ - i_w_in pe 2 biti, valoarea 2'd0 reprezinta caracterul 'a', 2'd1 caracterul 'b', 2'd2 caracterul 'c', 2'd3 caracterul 'd'
+ - i_w_clk - ceas
+ - i_w_reset - reset activ poztiv (1) va reseta starea automatului
+
+FSM va avea ca iesire:
+ - o_w_out - daca SECVENTA data a fost detectata in cadrul sirului de caracter primit la intrare
+
+Veti afla SECVENTA de caractere dupa apasarea butonului "evaluate" din VPL.
+
+SECVENTA poate sa fie o expresie regulata formata dintr-un singur grup si un singur operator special, exemple:
+ - a(bc)+
+ - a(ab)*
\ No newline at end of file
diff --git a/assignments/sequential/opregister/.gitignore b/assignments/sequential/opregister/.gitignore
new file mode 100644
index 00000000..683b9244
--- /dev/null
+++ b/assignments/sequential/opregister/.gitignore
@@ -0,0 +1,3 @@
+*.vvp
+*.vcd
+vpl_execution
\ No newline at end of file
diff --git a/assignments/sequential/opregister/README.md b/assignments/sequential/opregister/README.md
new file mode 100644
index 00000000..34927cf0
--- /dev/null
+++ b/assignments/sequential/opregister/README.md
@@ -0,0 +1,31 @@
+# Operation Register
+Sa se implementeze un registru multifunctional.
+
+Intrarile registrului sunt:
+ - i_w_clk - ceas
+ - i_w_reset - reset pe valoare pozitiva (1)
+ - i_w_data -  date de intrare pe 4 biti
+ - i_w_we - daca se scrie in registru
+ - i_w_oe - daca se afiseaza in registru
+ - i_w_sel - selectie asupra unui operatii pe registru
+
+Iesirea registrului este:
+ - o_w_out este activa doar cand i_w_oe este activ (1), altfel  o_w_out va avea valoarea 4'b0000. (4 biți)
+
+Prioritatea funcțiilor registrului sunt: i_w_we, i_w_sel, i_w_oe. (daca i_w_we si i_w_oe sunt active in acelasi timp se va face doar scrierea in registru a valorii i_w_data)
+
+Operatiile pe care va trebui sa le implementati in functie de valoarea i_w_sel le veti afla doar dupa apasarea butonului "evaluate" din VPL.
+
+Operatiile posibile sunt: 
+ - SHR1 - Shift right by one
+ - SHL1 - Shift left by one
+ - SAR1 - Shift right arithmetic by one
+ - ROTR1 - Rotate right by one
+ - ROTL1 - Rotate left by one
+ - REDUCE_BITWISE_OR - OR all bits
+ - REDUCE_BITWISE_XOR - XOR all bits
+ - REDUCE_BITWISE_AND - AND all bits
+ - NEG - Two's complement
+ - NOT - One's Complement
+ - INC - Increment by one
+ - DEC - Decrement by one
\ No newline at end of file
diff --git a/chapters/verilog/basic/assigments/mux/.gitignore b/assignments/sim/mux/.gitignore
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/.gitignore
rename to assignments/sim/mux/.gitignore
diff --git a/chapters/verilog/basic/assigments/mux/Makefile b/assignments/sim/mux/Makefile
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/Makefile
rename to assignments/sim/mux/Makefile
diff --git a/chapters/verilog/basic/assigments/mux/README.md b/assignments/sim/mux/README.md
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/README.md
rename to assignments/sim/mux/README.md
diff --git a/chapters/verilog/basic/assigments/mux/evaluate_mux.v b/assignments/sim/mux/evaluate_mux.v
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/evaluate_mux.v
rename to assignments/sim/mux/evaluate_mux.v
diff --git a/assignments/sim/mux/grade.sh b/assignments/sim/mux/grade.sh
new file mode 100644
index 00000000..b2bf0835
--- /dev/null
+++ b/assignments/sim/mux/grade.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+if [[ $# -ne 1 ]]; then
+    echo 'Too many/few arguments, expecting one' >&2
+    exit 1
+fi
+
+EVALUATE_FILE=$1
+#--- remove multiple spaces --- 
+cat $EVALUATE_FILE | sed 's/  */ /g' > dummy.out
+mv dummy.out $EVALUATE_FILE
+
+#--- remove blank lines ---
+cat $EVALUATE_FILE | sed '/^\s*$/d' > dummy.out
+mv dummy.out $EVALUATE_FILE
+
+# Calculate number of correct test versus wrong test
+correct_test_no=$(awk '$1=="OK" { print $0 }' $EVALUATE_FILE | wc -l | awk '{ print $1 }')
+test_no=$(wc -l $EVALUATE_FILE| awk '{ print $1 }')
+grade=$( expr $correct_test_no \* 100 / $test_no)
+
+echo $grade
\ No newline at end of file
diff --git a/chapters/verilog/basic/assigments/mux/mux.v b/assignments/sim/mux/mux.v
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/mux.v
rename to assignments/sim/mux/mux.v
diff --git a/chapters/verilog/basic/assigments/mux/solution_mux.v b/assignments/sim/mux/solution_mux.v
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/solution_mux.v
rename to assignments/sim/mux/solution_mux.v
diff --git a/chapters/verilog/basic/assigments/mux/test_mux.v b/assignments/sim/mux/test_mux.v
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/test_mux.v
rename to assignments/sim/mux/test_mux.v
diff --git a/chapters/verilog/basic/assigments/mux/test_solution_mux.v b/assignments/sim/mux/test_solution_mux.v
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/test_solution_mux.v
rename to assignments/sim/mux/test_solution_mux.v
diff --git a/chapters/verilog/basic/assigments/mux/vpl_evaluate.sh b/assignments/sim/mux/vpl_evaluate.sh
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/vpl_evaluate.sh
rename to assignments/sim/mux/vpl_evaluate.sh
diff --git a/chapters/verilog/basic/assigments/mux/vpl_run.sh b/assignments/sim/mux/vpl_run.sh
similarity index 100%
rename from chapters/verilog/basic/assigments/mux/vpl_run.sh
rename to assignments/sim/mux/vpl_run.sh
diff --git a/chapters/verilog/basic/drills/README.md b/chapters/verilog/basic/drills/README.md
index 24c9a6f3..58ec7499 100644
--- a/chapters/verilog/basic/drills/README.md
+++ b/chapters/verilog/basic/drills/README.md
@@ -16,20 +16,3 @@
 
 ## 4. **Comparator** pe un bit.
   Acesta are două intrări și trei ieșiri (pentru mai mic, egal și mai mare). Soluția se află în repo-ul materiei [GitHub](https://github.com/cs-pub-ro/computer-architecture/tree/main/chapters/verilog/basic/drills/tasks/comparator). Simulați și încărcați pe FPGA.
-
-
-## Test
-  Aveți următorul tabel de adevăr:
-
-  | a | b | c | f |
-  | - | - | - | - |
-  | 0 | 0 | 0 | 1 |
-  | 0 | 0 | 1 | 0 |
-  | 0 | 1 | 0 | 0 |
-  | 0 | 1 | 1 | 0 |
-  | 1 | 0 | 0 | 1 |
-  | 1 | 0 | 1 | 1 |
-  | 1 | 1 | 0 | 1 |
-  | 1 | 1 | 1 | 0 |
-
-  Intrările sunt: `a`, `b`, `c`, iar ieșirea este `f`. Implementați modulul Verilog definit de acest tabel de adevăr.
diff --git a/chapters/verilog/behavioral/assigments/alu/README.md b/chapters/verilog/behavioral/assigments/alu/README.md
deleted file mode 100644
index ddc13631..00000000
--- a/chapters/verilog/behavioral/assigments/alu/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-Implmentați modulul verilog pentru un ALU (arithmetic logic unit) cu 2 operanzi i_w_op1 și i_w_op2 pe 4 biți fiecare, cu rezultatul pe 4 biți o_w_out și o linie de selecție pe 2 biți a operație i_w_sel.
-Apăsați butonul run din VPL pentru a afla operațile pe care trebuie sa le implementați pentru fiecare selecție.
\ No newline at end of file
diff --git a/chapters/verilog/behavioral/assigments/led7/README.md b/chapters/verilog/behavioral/assigments/led7/README.md
deleted file mode 100644
index afff8da5..00000000
--- a/chapters/verilog/behavioral/assigments/led7/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-Implmentați modulul verilog pentru afisarea 7-led-segment dat prin iesirile o_w_ca, o_w_cb, o_w_cc, o_w_cd, o_w_ce, o_w_cf, o_w_cg pentru 4 cifre ce vor fi selectate in functie de i_w_in. Linile cx sunt active pe valoarea 0.
-Pentru numarul XYZT, pentru i_w_in=0 se va afisa cifra T, pentru i_w_in=1 cifra Z, pentru i_w_in=2 cifra Y, pentru i_w_in=3 cifra X. apasati run din VPL pentru a afla numarul vostru.
\ No newline at end of file
diff --git a/chapters/verilog/behavioral/drills/README.md b/chapters/verilog/behavioral/drills/README.md
index 24394291..2e2f2384 100644
--- a/chapters/verilog/behavioral/drills/README.md
+++ b/chapters/verilog/behavioral/drills/README.md
@@ -25,11 +25,4 @@ Pentru mai multe detalii asupra acestui tip de modul, consultați pagina de [Wik
     - _Hint_: Câți biți au ieșirea sumatorului și a multiplicatorului? Dar a UAL-ului? 
     - _Hint_: Pentru selecția dintre ieșirea sumatorului și cea a multiplicatorului se poate folosi atribuirea continuă sau se poate implementa un modul multiplexor 2:1 
     - Pentru o utilizare mai generală, implementați un UAL cu operatori cu dimensiune variabilă. 
-      - _Hint_: Pentru a-l implementa, este necesară implementarea unui multiplicator parametrizat - atenție la dimensiunea semnalelor!  
-
-## TEST
-
-1. Implmentați modulul verilog pentru afisarea 7-led-segment dat prin iesirile o_w_ca, o_w_cb, o_w_cc, o_w_cd, o_w_ce, o_w_cf, o_w_cg pentru 4 cifre ce vor fi selectate in functie de i_w_in.
-Pentru numarul XYZT, pentru i_w_in=0 se va afisa cifra T, pentru i_w_in=1 cifra Z, pentru i_w_in=2 cifra Y, pentru i_w_in=3 cifra X.
-
-2. Implmentați modulul verilog pentru un ALU (arithmetic logic unit) cu 2 operanzi i_w_op1 și i_w_op2 pe 4 biți fiecare, cu rezultatul pe 4 biți o_w_out și o linie de selecție pe 2 biți a operație i_w_sel.
\ No newline at end of file
+      - _Hint_: Pentru a-l implementa, este necesară implementarea unui multiplicator parametrizat - atenție la dimensiunea semnalelor!  
\ No newline at end of file
diff --git a/chapters/verilog/operators/assigments/comb/README.md b/chapters/verilog/operators/assigments/comb/README.md
deleted file mode 100644
index 85d553a3..00000000
--- a/chapters/verilog/operators/assigments/comb/README.md
+++ /dev/null
@@ -1 +0,0 @@
-Implmentați modulul verilog pentru tabelul de adevăr dat. Apăsați butonul run din VPL pentru a afla tabelul de adevăr pe care trebuie să îl implementați.
\ No newline at end of file
diff --git a/config.yaml b/config.yaml
index aabbf806..6e23db43 100644
--- a/config.yaml
+++ b/config.yaml
@@ -191,6 +191,37 @@ docusaurus:
           path: /build/embed_reveal
           subsections:
             - 0 Introducere: intro/intro.mdx
+      - Evaluare:
+          path: assignments
+          subsections:
+            - Test Circuite Combinaționale:
+                path: combinational
+                extra:
+                  - led7/media/
+                subsections:
+                  - True Table/: comb/
+                  - 7 LED Segment/: led7/
+                  - ALU/: alu/
+            - Test Circuite Secvențiale:
+                path: sequential
+                subsections:
+                  - FSM/: fsm/
+                  - Operation Register/: opregister/
+                  - Flag RAM/: flagram/
+            # - Test Calculator Didactic:
+            #     path: cpu
+            #     subsections:
+            #       - 1/: 1/
+            #       - 2/: 2/
+            #       - 3/: 3/
+            - Teme:
+                path: projects
+                subsections:
+                  - FPU/: fpu/
+            # - Examen AB:
+            #     path: exam
+            #     subsections:
+            #       - 1/: 1/
       
     static_assets:
       - slides/intro: /build/make_assets/chapters/intro/soc/slides/_site