README

FieldProgrammableWristWatch is a digital alarm clock/stopwatch, written in verilog, for the spartan3 educational boards, as a final project for the EC311 - Intro to Logic Design

Has 4 modes, watch this presentation for info.
https://prezi.com/secure/8d9e460ec28fd1a739b2795e7a33448a035d261f/?utm_source=share&utm_campaign=shareprezi&utm_medium=email

The code would be easily portable to other FPGAs, but the clocks would be all off, for your reference, the Spartan3 used has a 50MHz clock.