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first FPGA with merged TPARs #60

Merged
merged 22 commits into from
Sep 10, 2024
Merged

first FPGA with merged TPARs #60

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2aab847
add dict that tracks TPAR merging scheme
jasonfan393 Mar 26, 2024
d7a1288
changes to add tf_merge_streamer
jasonfan393 Jul 19, 2024
4f15dff
add stream signals to tb
jasonfan393 Jul 19, 2024
27d60ab
add functioning tb
jasonfan393 Mar 28, 2024
40d5fc9
change merging scheme to be consistent with FPGA2
jasonfan393 May 10, 2024
2a92141
add split flags
jasonfan393 Jul 19, 2024
4ebe133
remove some magic numbers
jasonfan393 May 23, 2024
0456322
small fixes
jasonfan393 Jun 3, 2024
6627311
change inner AS size for disks
jasonfan393 Jun 3, 2024
2d6ecf3
change split flag for 2 fpga projects to an int
jasonfan393 Jul 19, 2024
8c8bf82
add more flags
jasonfan393 Jul 29, 2024
b75ffe5
fix some bugs
jasonfan393 Jul 29, 2024
6edfa77
fix fixme
jasonfan393 Jul 29, 2024
eae4a76
small fix
jasonfan393 Jul 29, 2024
175d3cb
fix bugs
jasonfan393 Jul 29, 2024
d2b3d65
update for TPAR addr size
jasonfan393 Jul 29, 2024
07d04fc
update to remove hardcoded dict
jasonfan393 Jul 29, 2024
f18a631
add missing change from commit
jasonfan393 Jul 29, 2024
de44eeb
only gen dictionary for split projects
jasonfan393 Jul 29, 2024
c617d87
add default value for mpar_dict for other projects
jasonfan393 Jul 30, 2024
04753f7
add missing split tags
jasonfan393 Jul 30, 2024
c122146
address comment
jasonfan393 Sep 9, 2024
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24 changes: 18 additions & 6 deletions TrackletGraph.py
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -210,10 +210,7 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f
elif mem.mtype == "AllStubs" or mem.mtype == "InputLink":
mem.bitwidth = 36
elif mem.mtype == "AllInnerStubs":
if disk>-1:
mem.bitwidth = 52
else:
mem.bitwidth = 51
mem.bitwidth = 51
elif mem.mtype == "DTCLink":
mem.bitwidth = 39
elif mem.mtype == "StubPairs":
Expand Down Expand Up @@ -637,17 +634,32 @@ def get_proc_module(self, instance_name, verbose=True):
print("WARNING!! Cannot find module", instance_name,"!!")
return None

def get_all_module_units(self, module):
def get_all_module_units(self, module, split = 0):
"Return all the ProcModule objects of a given type"
modules = {}
for instance_name in self.__proc_dict:
#FIXME
if instance_name.startswith(module+"_") or instance_name.startswith("VMSMER_"):
if split == 2:
if instance_name.startswith(module+"_") or instance_name.startswith("VMSMER_"):
modules[instance_name]=self.__proc_dict[instance_name]
elif instance_name.startswith(module+"_"):
modules[instance_name]=self.__proc_dict[instance_name]
if not modules:
print("WARNING!! Cannot find any modules with name starting with", module,"!!")
else:
return modules
def get_MPAR_dict(self):
#returns a dict which containing info related to the mergining
#of TPROJ memories for split FPGA projects
MPAR_dict = {}
PC_dict = self.get_all_module_units("PC")
for key, value in PC_dict.items():
iTCs = key[7:]
seed = key[3:7]
if seed not in MPAR_dict:
MPAR_dict[seed] = []
MPAR_dict[seed].append(iTCs)
return MPAR_dict

def get_mem_module(self, instance_name, verbose=True):
" Return a MemModule object given the instance name "
Expand Down
34 changes: 17 additions & 17 deletions WriteHDLUtils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1192,7 +1192,7 @@ def parseProcFunction(proc_name, fname_def):
return arg_types_list, arg_names_list, templ_pars_list

def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
f_matchArgPortNames, first_of_type, extraports,delay,split=False):
f_matchArgPortNames, first_of_type, extraports,delay,split=0):
####
# function name

Expand Down Expand Up @@ -1352,7 +1352,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
if "DL" in memory.inst and "AS" not in memory.inst: # DTCLink
string_mem_ports += writeProcDTCLinkRHSPorts(tmp_argname,memory)
else:
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory)
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory, split=split)

if portname.replace("outer","").find("out") != -1:
if memory.isFIFO():
Expand All @@ -1362,7 +1362,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
if portname.find("trackpar") != -1 and (module.mtype == "TrackletCalculator" or module.mtype == "TrackletProcessor"):
string_mem_ports += writeProcMemoryLHSPorts(tmp_argname,memory,split)
elif portname.find("trackpar") != -1 and module.mtype == "PurgeDuplicates":
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory)
string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory,split=split)

# Remove the already added module and name from the lists
portNameList.remove(portname)
Expand Down Expand Up @@ -1397,17 +1397,17 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
return str_ctrl_wire,module_str

################################
def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, split = False):
def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, split = 0):
if module.mtype == 'InputRouter':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_IR,
matchArgPortNames_IR,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'VMRouter':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_VMR,
matchArgPortNames_VMR,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'VMRouterCM':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_VMRCM,
Expand All @@ -1417,7 +1417,7 @@ def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, s
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_TE,
matchArgPortNames_TE,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'TrackletProcessor':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_TP,
Expand All @@ -1427,51 +1427,51 @@ def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, s
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_TC,
matchArgPortNames_TC,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'ProjectionRouter':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_PR,
matchArgPortNames_PR,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'MatchEngine':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_ME,
matchArgPortNames_ME,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'MatchCalculator':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_MC,
matchArgPortNames_MC,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'MatchProcessor':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_MP,
matchArgPortNames_MP,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'FitTrack':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_FT,
matchArgPortNames_FT,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'TrackBuilder':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_TB,
matchArgPortNames_TB,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'PurgeDuplicate':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_PD,
matchArgPortNames_PD,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'ProjectionCalculator':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_PC,
matchArgPortNames_PC,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
elif module.mtype == 'VMSMERouter':
return writeModuleInst_generic(module, hls_src_dir,
writeTemplatePars_VMSMER,
matchArgPortNames_VMSMER,
first_of_type, extraports, delay)
first_of_type, extraports, delay, split)
else:
raise ValueError(module.mtype + " is unknown.")
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