From 2aab84766fd9681dc9222a7a24e933c6f5e331ea Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Tue, 26 Mar 2024 11:49:01 -0400 Subject: [PATCH 01/22] add dict that tracks TPAR merging scheme --- WriteVHDLSyntax.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index a15846c..06dc0a2 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -1,10 +1,20 @@ from builtins import range from TrackletGraph import MemModule, ProcModule, MemTypeInfoByKey - +#following dictionary tracks which trackletparameters are grouped together by merging module +MPARdict = { + "L5L6" : ["ABCD"] + "L2L3" : ["ABCD"] + "L3L4" : ["AB","CD"] + "L2D1" : ["ABCD"] + "L1D1" : ["ABCD","EFGH"] + "D1D2" : ["ABCD"] + "D3D4" : ["ABCD"] + "L1L2" : ["ABCD","JLK","DF","GI","E","H"] +} def getVMStubNCopy(memmod): mem = memmod.inst; - + if "VMSTE" in mem: proc = memmod.downstreams[0].inst; if "L1L2" in proc: @@ -50,7 +60,6 @@ def getVMStubNCopy(memmod): return "Error no match for "+mem else: return "Wrong memory module:"+mem - def writeTopPreamble(all=True): From d7a12881fdcd20f2b8419813d83f68b45a4e733e Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Fri, 19 Jul 2024 10:30:56 -0400 Subject: [PATCH 02/22] changes to add tf_merge_streamer --- WriteVHDLSyntax.py | 81 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 67 insertions(+), 14 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 06dc0a2..3796caa 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -2,14 +2,14 @@ from TrackletGraph import MemModule, ProcModule, MemTypeInfoByKey #following dictionary tracks which trackletparameters are grouped together by merging module MPARdict = { - "L5L6" : ["ABCD"] - "L2L3" : ["ABCD"] - "L3L4" : ["AB","CD"] - "L2D1" : ["ABCD"] - "L1D1" : ["ABCD","EFGH"] - "D1D2" : ["ABCD"] - "D3D4" : ["ABCD"] - "L1L2" : ["ABCD","JLK","DF","GI","E","H"] + "L5L6" : ["ABCD"], + "L2L3" : ["ABCD"], + "L3L4" : ["AB","CD"], + "L2D1" : ["ABCD"], + "L1D1" : ["ABCD","EFGH"], + "D1D2" : ["ABCD"], + "D3D4" : ["ABCD"], + "L1L2" : ["ABC","JLK","DF","GI","E","H"] } def getVMStubNCopy(memmod): @@ -459,7 +459,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay_portlist_0 = "" delay_portlist = "" delay2_portlist = "" - #FIXME if "MPAR" in mem and not "in" in mem: interface = 0 @@ -467,7 +466,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl if "AS" in mem and not "in" in mem: interface = 0 extraports = False - + merge_parameterlist = "" + merge_portlist = "" # Write wires if delay > 0: if not memInfo.is_binned: @@ -494,7 +494,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_din : " wirelist += "t_"+mtypeB+"_DATA;\n" - if interface != 1 : + if not (interface == 1 and not split): if memInfo.is_binned : wirelist += " signal "+mem+"_A_enb : " wirelist += "t_"+mtypeB+"_A1b;\n" @@ -643,8 +643,53 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay_portlist += " wea_out => "+mem+"_wea_delay,\n" delay_portlist += " addra_out => "+mem+"_writeaddr_delay,\n" delay_portlist += " dina_out => "+mem+"_din_delay,\n" - - + if "TPAR" in mem: + addrwidth = 10 + ramwidth = 73 + numpages = 8 + seed = mem.split("_")[1][:-1] + iTC = mem.split("_")[1][-1] + for PCgroup in MPARdict[seed]: + if iTC == PCgroup[0]: + numInputs = len(PCgroup) + merge_parameterlist += " RAM_WIDTH => "+str(ramwidth)+",\n" + merge_parameterlist += " NUM_PAGES => "+str(numpages)+",\n" + merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" + merge_parameterlist += " NUM_EXTRA_BITS => 2,\n" + merge_portlist += " bx_in => TP_bx_out_0,\n" + merge_portlist += " rst => '0',\n" + merge_portlist += " clk => clk,\n" + merge_portlist += " enb_arr => open,\n" + merge_portlist += " bx_out => open,\n" + merge_portlist += " merged_dout => MTPAR_"+seed+PCgroup+"_stream_V_dout,\n" + for i in range(4): merge_portlist += " din"+str(i)+"=>TPAR_"+seed+PCgroup[i%numInputs]+"_V_dout,\n" + for i in range(4): merge_portlist += " nent"+str(i)+"=>TPAR_"+seed+PCgroup[i%numInputs]+"_AV_dout_nent,\n" + for i in range(numInputs): merge_portlist += " addr_arr("+str(((i+1)*addrwidth)-1)+" downto "+ str(i*addrwidth)+ ")=>TPAR_"+seed+PCgroup[i%numInputs]+"_V_readaddr,\n" + mem_str += " MERGE_STREAM_TPAR"+seed+PCgroup+" : entity work.tf_merge_streamer\n" + mem_str += " generic map (\n"+merge_parameterlist.rstrip(",\n")+"\n )\n" + mem_str += " port map (\n"+merge_portlist.rstrip(",\n")+"\n );\n\n" + + elif "AS" in mem and "n1" in mem: + addrwidth = 10 + ramwidth = 36 + numpages = 8 + numInputs = 1 + merge_parameterlist += " RAM_WIDTH => "+str(ramwidth)+",\n" + merge_parameterlist += " NUM_PAGES => "+str(numpages)+",\n" + merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" + merge_parameterlist += " NUM_EXTRA_BITS => 0,\n" + merge_portlist += " bx_in => TP_bx_out_0,\n" + merge_portlist += " rst => '0',\n" + merge_portlist += " clk => clk,\n" + merge_portlist += " enb_arr => open,\n" + merge_portlist += " bx_out => open,\n" + merge_portlist += " merged_dout => "+mem+"_stream_V_dout,\n" + for i in range(4): merge_portlist += " din"+str(i)+"=>" +mem+"_V_dout,\n" + for i in range(4): merge_portlist += " nent"+str(i)+"=>" +mem+"_AV_dout_nent,\n" + for i in range(numInputs): merge_portlist += " addr_arr("+str(((i+1)*addrwidth)-1)+" downto "+ str(i*addrwidth)+ ")=>"+mem+"_V_readaddr,\n" + mem_str += " STREAM_"+mem+" : entity work.tf_merge_streamer\n" + mem_str += " generic map (\n"+merge_parameterlist.rstrip(",\n")+"\n )\n" + mem_str += " port map (\n"+merge_portlist.rstrip(",\n")+"\n );\n\n" portlist += " clkb => clk,\n" portlist += " rstb => '0',\n" portlist += " regceb => '1',\n" @@ -819,7 +864,6 @@ def writeDTCLinkLHSPorts_interface(mtypeB, memDict): string_input_mems += " "+mem+"_link_read : out t_"+mtypeB+"_1b;\n" return string_input_mems - def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): """ # Top-level interface: output memories' ports. @@ -848,6 +892,15 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): string_output_mems += " "+mem+"_enb_nent : out t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" + elif "AS" in mtypeB: #AS/TPAR at interface need to go through merging module + string_output_mems += " "+mem+"_stream_V_dout : out std_logic_vector(36 downto 0);\n" + elif "TPAR" in mtypeB: + seed = mem.split("_")[1][:-1] + itc = mem.split("_")[1][-1] + print(itc) + for PCgroup in MPARdict[seed]: + if itc == PCgroup[0]: + string_output_mems += " MTPAR_"+seed+PCgroup+"_stream_V_dout : out std_logic_vector(75 downto 0);\n" else: string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" From 4f15dff9c372e3e14b714354d4d6a25b8cd636f9 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Fri, 19 Jul 2024 10:31:38 -0400 Subject: [PATCH 03/22] add stream signals to tb --- WriteVHDLSyntax.py | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 3796caa..5430e4a 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -894,7 +894,7 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" elif "AS" in mtypeB: #AS/TPAR at interface need to go through merging module string_output_mems += " "+mem+"_stream_V_dout : out std_logic_vector(36 downto 0);\n" - elif "TPAR" in mtypeB: + elif "TPAR" in mtypeB: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] print(itc) @@ -1009,8 +1009,6 @@ def writeTBConstants(memDict, memInfoDict, procs, emData_dir, sector, split): string_constants += " constant inputFileNameEnding".ljust(str_len) + ": string := \"_" + sector + ".dat\"; -- " + sector + " specifies the nonant/sector the testvectors represent\n" string_constants += " constant outputFileNameEnding".ljust(str_len) + ": string := \".txt\";\n" string_constants += " constant debugFileNameEnding".ljust(str_len) + ": string := \".debug.txt\";\n\n" - string_constants += " signal dummy : STD_LOGIC := '0';\n\n -- dummy tb signal for inputs into sectorproc\n" - string_constants += " signal dummyaddr : t_as_36_addr := (others => '0');\n\n -- dummy tb signal for inputs into sectorproc" return string_constants @@ -1115,6 +1113,11 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += ("t_"+mtypeB+"_NENT").ljust(str_len2)+":= (others => '0'); -- (#page)(#bin)\n" string_ctrl_signals += (" signal "+mem+"_AV_dout_mask").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n" + elif split and "TPAR" in mem: + seed = mem.split("_")[1][:-1] + itc = mem.split("_")[1][-1] + if MPARdict[seed][0] == itc: + string_ctrl_signals +=" signal MPAR_"+seed+MPARdict[seed] +": std_logic_vector(75 downto 0) := (others=> '0') ;\n" else: string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" @@ -1134,7 +1137,9 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi if memMod.is_binned: if "VMSME_D" in mem: disk = "DISK" - + if "AS" in mem and "n1" in mem: + string_ctrl_signals += " signal "+mem+"_stream_V_dout : std_logic_vector(36 downto 0) := (others => '0');\n" + continue string_ctrl_signals += (" signal "+mem+"_wea").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" string_ctrl_signals += (" signal "+mem+"_writeaddr").ljust(str_len)+": " @@ -1211,6 +1216,8 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc memList = memDict[mtypeB] for memMod in memList: mem = memMod.inst + if split and ("AS" in mtypeB and "n1" in mem): + string_output += (" "+mem+"_stream_V_dout").ljust(str_len) + "=> "+mem+"_stream_V_dout,\n" if memInfo.is_initial: if "DL" in mtypeB and "AS" not in mtypeB: # Special case for DTCLink as it has FIFO input string_input += (" "+mem+"_link_AV_dout").ljust(str_len) + "=> "+mem+"_link_AV_dout,\n" @@ -1242,6 +1249,11 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_output += (" "+mem+"_enb_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" + elif ("TPAR" in mem) and split: + seed = mem.split("_")[1][:-1] + itc = mem.split("_")[1][-1] + if MPARdict[seed][0] == itc: + string_output += (" MTPAR_"+seed+MPARdict[seed]+"_stream_V_dout").ljust(str_len) + "=> MTPAR_"+seed+MPARdict[seed]+"_stream_V_dout,\n" else: string_output += (" "+mem+"_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" From 27d60ab8bf9dbd374cd52b20d936c3f8f619d16c Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Thu, 28 Mar 2024 17:49:35 -0400 Subject: [PATCH 04/22] add functioning tb --- WriteVHDLSyntax.py | 81 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 19 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 5430e4a..46cc550 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -504,7 +504,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "t_"+mtypeB+"_ADATA;\n" else: wirelist += " signal "+mem+"_enb : " - wirelist += "t_"+mtypeB+"_1b;\n" + wirelist += "t_"+mtypeB+"_1b := '1';\n" #FIXME remove this wirelist += " signal "+mem+"_V_readaddr : " wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_V_dout : " @@ -649,9 +649,9 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl numpages = 8 seed = mem.split("_")[1][:-1] iTC = mem.split("_")[1][-1] - for PCgroup in MPARdict[seed]: - if iTC == PCgroup[0]: - numInputs = len(PCgroup) + for PCGroup in MPARdict[seed]: + if iTC == PCGroup[0]: + numInputs = len(PCGroup) merge_parameterlist += " RAM_WIDTH => "+str(ramwidth)+",\n" merge_parameterlist += " NUM_PAGES => "+str(numpages)+",\n" merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" @@ -661,11 +661,11 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" merge_portlist += " bx_out => open,\n" - merge_portlist += " merged_dout => MTPAR_"+seed+PCgroup+"_stream_V_dout,\n" - for i in range(4): merge_portlist += " din"+str(i)+"=>TPAR_"+seed+PCgroup[i%numInputs]+"_V_dout,\n" - for i in range(4): merge_portlist += " nent"+str(i)+"=>TPAR_"+seed+PCgroup[i%numInputs]+"_AV_dout_nent,\n" - for i in range(numInputs): merge_portlist += " addr_arr("+str(((i+1)*addrwidth)-1)+" downto "+ str(i*addrwidth)+ ")=>TPAR_"+seed+PCgroup[i%numInputs]+"_V_readaddr,\n" - mem_str += " MERGE_STREAM_TPAR"+seed+PCgroup+" : entity work.tf_merge_streamer\n" + merge_portlist += " merged_dout => MTPAR_"+seed+PCGroup+"_stream_V_dout,\n" + for i in range(4): merge_portlist += " din"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_V_dout,\n" + for i in range(4): merge_portlist += " nent"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_AV_dout_nent,\n" + for i in range(numInputs): merge_portlist += " addr_arr("+str(((i+1)*addrwidth)-1)+" downto "+ str(i*addrwidth)+ ")=>TPAR_"+seed+PCGroup[i%numInputs]+"_V_readaddr,\n" + mem_str += " MERGE_STREAM_TPAR"+seed+PCGroup+" : entity work.tf_merge_streamer\n" mem_str += " generic map (\n"+merge_parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+merge_portlist.rstrip(",\n")+"\n );\n\n" @@ -897,10 +897,9 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): elif "TPAR" in mtypeB: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] - print(itc) - for PCgroup in MPARdict[seed]: - if itc == PCgroup[0]: - string_output_mems += " MTPAR_"+seed+PCgroup+"_stream_V_dout : out std_logic_vector(75 downto 0);\n" + for PCGroup in MPARdict[seed]: + if itc == PCGroup[0]: + string_output_mems += " MTPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector(75 downto 0);\n" else: string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" @@ -1116,8 +1115,9 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi elif split and "TPAR" in mem: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] - if MPARdict[seed][0] == itc: - string_ctrl_signals +=" signal MPAR_"+seed+MPARdict[seed] +": std_logic_vector(75 downto 0) := (others=> '0') ;\n" + for PCGroup in MPARdict[seed]: + if PCGroup[0] == itc: + string_ctrl_signals +=" signal MTPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector(75 downto 0) := (others=> '0') ;\n" else: string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" @@ -1216,8 +1216,6 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc memList = memDict[mtypeB] for memMod in memList: mem = memMod.inst - if split and ("AS" in mtypeB and "n1" in mem): - string_output += (" "+mem+"_stream_V_dout").ljust(str_len) + "=> "+mem+"_stream_V_dout,\n" if memInfo.is_initial: if "DL" in mtypeB and "AS" not in mtypeB: # Special case for DTCLink as it has FIFO input string_input += (" "+mem+"_link_AV_dout").ljust(str_len) + "=> "+mem+"_link_AV_dout,\n" @@ -1252,13 +1250,16 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc elif ("TPAR" in mem) and split: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] - if MPARdict[seed][0] == itc: - string_output += (" MTPAR_"+seed+MPARdict[seed]+"_stream_V_dout").ljust(str_len) + "=> MTPAR_"+seed+MPARdict[seed]+"_stream_V_dout,\n" + for PCGroup in MPARdict[seed]: + if PCGroup[0] == itc: + string_output += (" MTPAR_"+seed+PCGroup+"_stream_V_dout").ljust(str_len) + "=> MTPAR_"+seed+PCGroup+"_stream_V_dout,\n" else: string_output += (" "+mem+"_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" string_output += (" "+mem+"_V_dout").ljust(str_len) + "=> "+mem+"_dout,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> "+mem+"_AV_dout_nent,\n" + elif split and ("AS" in mtypeB and "n1" in mem): + string_output += (" "+mem+"_stream_V_dout").ljust(str_len) + "=> "+mem+"_stream_V_dout,\n" else: string_debug += (" "+mem+"_wea").ljust(str_len) + "=> "+mem+"_wea,\n" string_debug += (" "+mem+"_writeaddr").ljust(str_len) + "=> "+mem+"_writeaddr,\n" @@ -1294,6 +1295,22 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi for memMod in memList: mem = memMod.inst + if ("AS" in mem and "n1" in mem): #FIXME this is not good + width = 37 + str_len = 16 # length of string for formatting purposes + string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" + string_mem += " generic map (\n" + string_mem += " FILE_NAME".ljust(str_len)+"=> FILE_OUT_"+mtypeB+"&\""+mem+"\"&outputFileNameEnding,\n" + string_mem += " FIFO_WIDTH".ljust(str_len)+"=> " + str(width) + "\n" + string_mem += " )\n" + string_mem += " port map (\n" + string_mem += " CLK".ljust(str_len)+"=> CLK,\n" + string_mem += " DONE".ljust(str_len)+"=> TP_DONE,\n" + string_mem += " WRITE_EN".ljust(str_len)+"=> ("+mem+"_stream_V_dout(" + str(width - 1) + ")),\n" + string_mem += " FULL_NEG".ljust(str_len)+'=> open,\n' + string_mem += " DATA".ljust(str_len)+"=> "+mem+"_stream_V_dout\n" + string_mem += " );\n" + continue string_mem += " write"+mem+" : entity work.FileWriter\n" string_mem += " generic map (\n" @@ -1343,6 +1360,32 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned): mem = memMod.inst + if ("TPAR" in mem) or ("AS" in mem and "n1" in mem): #FIXME this is not good + width = 0 + if "TPAR" in mem: + width=76 + seed = mem.split("_")[1][:-1] + itc = mem.split("_")[1][-1] + for PCGroup in MPARdict[seed]: + if PCGroup[0] != itc: continue + mem = "MTPAR_" + seed + PCGroup + else: + width=37 + if "MTPAR" not in mem: continue #FIXME also not good + str_len = 16 # length of string for formatting purposes + string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" + string_mem += " generic map (\n" + string_mem += " FILE_NAME".ljust(str_len)+"=> FILE_OUT_"+mtypeB+"&\""+mem+"\"&outputFileNameEnding,\n" + string_mem += " FIFO_WIDTH".ljust(str_len)+"=> " + str(width) + "\n" + string_mem += " )\n" + string_mem += " port map (\n" + string_mem += " CLK".ljust(str_len)+"=> CLK,\n" + string_mem += " DONE".ljust(str_len)+"=> TP_DONE,\n" + string_mem += " WRITE_EN".ljust(str_len)+"=> ("+mem+"_stream_V_dout(" + str(width - 1) + ")),\n" + string_mem += " FULL_NEG".ljust(str_len)+'=> open,\n' + string_mem += " DATA".ljust(str_len)+"=> "+mem+"_stream_V_dout\n" + string_mem += " );\n" + continue string_mem += " write"+mem+" : entity work.FileWriterFromRAM" + ("Binned\n" if is_binned else "\n") string_mem += " generic map (\n" string_mem += " FILE_NAME".ljust(str_len)+"=> FILE_OUT_"+mtypeB+"&\""+mem+"\"&outputFileNameEnding,\n" From 40d5fc951661c8be74a4f964a7033619efca1677 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Fri, 10 May 2024 13:21:10 -0400 Subject: [PATCH 05/22] change merging scheme to be consistent with FPGA2 --- WriteVHDLSyntax.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 46cc550..a684468 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -9,7 +9,7 @@ "L1D1" : ["ABCD","EFGH"], "D1D2" : ["ABCD"], "D3D4" : ["ABCD"], - "L1L2" : ["ABC","JLK","DF","GI","E","H"] + "L1L2" : ["ABC","JKL","DE","G","F","HI"] } def getVMStubNCopy(memmod): From 2a921412909339e63f058a6b51408670a1aeb49b Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Fri, 19 Jul 2024 10:32:18 -0400 Subject: [PATCH 06/22] add split flags --- WriteVHDLSyntax.py | 28 +++++++++++++--------------- generator_hdl.py | 12 ++++++------ 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index a684468..100b618 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -14,7 +14,6 @@ def getVMStubNCopy(memmod): mem = memmod.inst; - if "VMSTE" in mem: proc = memmod.downstreams[0].inst; if "L1L2" in proc: @@ -60,7 +59,6 @@ def getVMStubNCopy(memmod): return "Error no match for "+mem else: return "Wrong memory module:"+mem - def writeTopPreamble(all=True): string_preamble = "--! Standard libraries\n" @@ -504,7 +502,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "t_"+mtypeB+"_ADATA;\n" else: wirelist += " signal "+mem+"_enb : " - wirelist += "t_"+mtypeB+"_1b := '1';\n" #FIXME remove this + wirelist += "t_"+mtypeB+"_1b := '1';\n" #FIXME send a read enable from merge module wirelist += " signal "+mem+"_V_readaddr : " wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_V_dout : " @@ -527,14 +525,13 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "STD_LOGIC;\n" wirelist += " signal "+mem+"_index : " wirelist += "STD_LOGIC_VECTOR(31 downto 0);\n" - if memInfo.has_numEntries_out: if memInfo.is_binned: disk="" if "VMSME_D" in mem: disk="DISK" wirelist += " signal "+mem+"_AV_dout_mask : " - wirelist += "t_"+mtypeB+"_MASK"+disk+"; -- (#page)(#bin)\n" + wirelist += "t_"+mtypeB+"_MASK"+disk+"; -- (#page)(#bin)\n" wirelist += " signal "+mem+"_enb_nent : " wirelist += "t_"+mtypeB+"_1b;\n" wirelist += " signal "+mem+"_V_addr_nent : " @@ -643,7 +640,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay_portlist += " wea_out => "+mem+"_wea_delay,\n" delay_portlist += " addra_out => "+mem+"_writeaddr_delay,\n" delay_portlist += " dina_out => "+mem+"_din_delay,\n" - if "TPAR" in mem: + # add merge_stream modules if split and TPAR or AS + if "TPAR" in mem and split: addrwidth = 10 ramwidth = 73 numpages = 8 @@ -669,7 +667,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl mem_str += " generic map (\n"+merge_parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+merge_portlist.rstrip(",\n")+"\n );\n\n" - elif "AS" in mem and "n1" in mem: + elif "AS" in mem and "n1" in mem and split: addrwidth = 10 ramwidth = 36 numpages = 8 @@ -864,7 +862,7 @@ def writeDTCLinkLHSPorts_interface(mtypeB, memDict): string_input_mems += " "+mem+"_link_read : out t_"+mtypeB+"_1b;\n" return string_input_mems -def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): +def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split): """ # Top-level interface: output memories' ports. # Inputs: @@ -892,9 +890,9 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): string_output_mems += " "+mem+"_enb_nent : out t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" - elif "AS" in mtypeB: #AS/TPAR at interface need to go through merging module + elif "AS" in mtypeB and split: #AS/TPAR at interface need to go through merging module string_output_mems += " "+mem+"_stream_V_dout : out std_logic_vector(36 downto 0);\n" - elif "TPAR" in mtypeB: + elif "TPAR" in mtypeB and split: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: @@ -1137,7 +1135,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi if memMod.is_binned: if "VMSME_D" in mem: disk = "DISK" - if "AS" in mem and "n1" in mem: + if "AS" in mem and "n1" in mem and split: string_ctrl_signals += " signal "+mem+"_stream_V_dout : std_logic_vector(36 downto 0) := (others => '0');\n" continue string_ctrl_signals += (" signal "+mem+"_wea").ljust(str_len)+": " @@ -1278,7 +1276,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc return string_fwblock_inst -def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_binned, is_cm): +def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_binned, is_cm, split): """ # VHDL test bench: write the loop that writes the input to the intermediate RAM memories to text files # Inputs: @@ -1295,7 +1293,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi for memMod in memList: mem = memMod.inst - if ("AS" in mem and "n1" in mem): #FIXME this is not good + if ("AS" in mem and "n1" in mem and split): #FIXME this is not good width = 37 str_len = 16 # length of string for formatting purposes string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" @@ -1339,7 +1337,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi return string_mem -def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned): +def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, split): """ # VHDL test bench: write the loop that writes the output from the end-of-chain BRAM memories to text files # Inputs: @@ -1360,7 +1358,7 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned): mem = memMod.inst - if ("TPAR" in mem) or ("AS" in mem and "n1" in mem): #FIXME this is not good + if (("TPAR" in mem) or ("AS" in mem and "n1" in mem)) and split: #FIXME this is not good width = 0 if "TPAR" in mem: width=76 diff --git a/generator_hdl.py b/generator_hdl.py index d94df3d..5bd7dcb 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -88,7 +88,7 @@ def writeProcModules(proc_list, hls_src_dir, extraports, delay, split = False): ######################################## # Top function interface ######################################## -def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, extraports, delay, streamIO=False): +def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, extraports, delay, split, streamIO=False): """ # topmodule_name: name of the top module # process_list: list of all processing functions in the block (in this function, this list is @@ -139,7 +139,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, string_output_mems += writeTrackStreamRHSPorts_interface(mtypeB, memDict) else: if not (("TPROJ" in mtypeB or "VMSME" in mtypeB) and args.split): - string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,memDict) + string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,memDict, split) elif extraports: # Debug ports corresponding to BRAM inputs. @@ -149,7 +149,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, ASmemDict = {mtypeB : []} for mem in memList: if "n1" in mem.inst: ASmemDict[mtypeB].append(mem) - string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo, ASmemDict) + string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo, ASmemDict, split) string_topmod_interface += string_ctrl_signals string_topmod_interface += string_input_mems @@ -188,7 +188,7 @@ def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraport # Top function interface string_topmod_interface = writeTopModule_interface(topfunc, process_list, - memDict, memInfoDict, extraports, delay) + memDict, memInfoDict, extraports, delay, split) string_src = "" string_src += writeTopPreamble() @@ -296,13 +296,13 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split): if memInfo.isFIFO: string_final += string_tmp else: - string_final += writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, memInfo.bxbitwidth, memInfo.is_binned) + string_final += writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, memInfo.bxbitwidth, memInfo.is_binned, split) elif not memInfo.is_initial: # intermediate memories if memInfo.isFIFO: string_intermediate += string_tmp else: is_cm = memInfo.downstream_mtype_short in ("TP", "MP") - string_intermediate += writeTBMemoryWriteInstance(mtypeB, memList, proc, up_proc, memInfo.bxbitwidth, memInfo.is_binned, is_cm) + string_intermediate += writeTBMemoryWriteInstance(mtypeB, memList, proc, up_proc, memInfo.bxbitwidth, memInfo.is_binned, is_cm, split) string_write = " -- Write signals to output .txt files\n\n" string_write += " writeIntermediateRAMs : if INST_TOP_TF = 1 generate\n" From 4ebe1338efcfef98a6de2b6f28c49b4eef84fe8f Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Thu, 23 May 2024 12:38:17 -0400 Subject: [PATCH 07/22] remove some magic numbers --- WriteVHDLSyntax.py | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 100b618..b629393 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -643,7 +643,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl # add merge_stream modules if split and TPAR or AS if "TPAR" in mem and split: addrwidth = 10 - ramwidth = 73 + ramwidth = memInfo.bitwidth numpages = 8 seed = mem.split("_")[1][:-1] iTC = mem.split("_")[1][-1] @@ -669,7 +669,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl elif "AS" in mem and "n1" in mem and split: addrwidth = 10 - ramwidth = 36 + ramwidth = memInfo.bitwidth numpages = 8 numInputs = 1 merge_parameterlist += " RAM_WIDTH => "+str(ramwidth)+",\n" @@ -891,13 +891,13 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split): string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" elif "AS" in mtypeB and split: #AS/TPAR at interface need to go through merging module - string_output_mems += " "+mem+"_stream_V_dout : out std_logic_vector(36 downto 0);\n" + string_output_mems += " "+mem+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth)+" downto 0);\n" elif "TPAR" in mtypeB and split: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if itc == PCGroup[0]: - string_output_mems += " MTPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector(75 downto 0);\n" + string_output_mems += " MTPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth+3)+" downto 0);\n" else: string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" @@ -1115,7 +1115,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if PCGroup[0] == itc: - string_ctrl_signals +=" signal MTPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector(75 downto 0) := (others=> '0') ;\n" + string_ctrl_signals +=" signal MTPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector("+str(memMod.bitwidth+3)+" downto 0) := (others=> '0') ;\n" else: string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" @@ -1136,7 +1136,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi if "VMSME_D" in mem: disk = "DISK" if "AS" in mem and "n1" in mem and split: - string_ctrl_signals += " signal "+mem+"_stream_V_dout : std_logic_vector(36 downto 0) := (others => '0');\n" + string_ctrl_signals += " signal "+mem+"_stream_V_dout : std_logic_vector("+str(memMod.bitwidth)+" downto 0) := (others => '0');\n" continue string_ctrl_signals += (" signal "+mem+"_wea").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" @@ -1293,8 +1293,9 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi for memMod in memList: mem = memMod.inst - if ("AS" in mem and "n1" in mem and split): #FIXME this is not good - width = 37 + if ("AS" in mem and "n1" in mem and split): + #FIXME rewrite this to be a separate function + width = memMod.bxbitwidth + 1 str_len = 16 # length of string for formatting purposes string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" string_mem += " generic map (\n" @@ -1361,14 +1362,14 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, if (("TPAR" in mem) or ("AS" in mem and "n1" in mem)) and split: #FIXME this is not good width = 0 if "TPAR" in mem: - width=76 + width= memMod.bitwidth + 4 seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if PCGroup[0] != itc: continue mem = "MTPAR_" + seed + PCGroup else: - width=37 + width= memMod.bitwidth + 1 if "MTPAR" not in mem: continue #FIXME also not good str_len = 16 # length of string for formatting purposes string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" From 045632255ec5079e56e84f0d665a322d0c878bc2 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 3 Jun 2024 14:02:21 -0400 Subject: [PATCH 08/22] small fixes --- WriteVHDLSyntax.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index b629393..3b55d09 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -897,7 +897,7 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split): itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if itc == PCGroup[0]: - string_output_mems += " MTPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth+3)+" downto 0);\n" + string_output_mems += " MTPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth+2)+" downto 0);\n" else: string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" @@ -1115,7 +1115,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if PCGroup[0] == itc: - string_ctrl_signals +=" signal MTPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector("+str(memMod.bitwidth+3)+" downto 0) := (others=> '0') ;\n" + string_ctrl_signals +=" signal MTPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector("+str(memMod.bitwidth+2)+" downto 0) := (others=> '0') ;\n" else: string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" @@ -1295,7 +1295,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi mem = memMod.inst if ("AS" in mem and "n1" in mem and split): #FIXME rewrite this to be a separate function - width = memMod.bxbitwidth + 1 + width = memMod.bitwidth + 1 str_len = 16 # length of string for formatting purposes string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" string_mem += " generic map (\n" @@ -1362,7 +1362,7 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, if (("TPAR" in mem) or ("AS" in mem and "n1" in mem)) and split: #FIXME this is not good width = 0 if "TPAR" in mem: - width= memMod.bitwidth + 4 + width= memMod.bitwidth + 3 seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: From 6627311e12772bf1f92cb505a7b99c69d18ed65e Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 3 Jun 2024 15:33:12 -0400 Subject: [PATCH 09/22] change inner AS size for disks --- TrackletGraph.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index 9d5d10c..b7faf37 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -210,10 +210,7 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f elif mem.mtype == "AllStubs" or mem.mtype == "InputLink": mem.bitwidth = 36 elif mem.mtype == "AllInnerStubs": - if disk>-1: - mem.bitwidth = 52 - else: - mem.bitwidth = 51 + mem.bitwidth = 51 elif mem.mtype == "DTCLink": mem.bitwidth = 39 elif mem.mtype == "StubPairs": From 2d6ecf3446e30b1a1acba5ba5a54b2a5a86b667d Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Fri, 19 Jul 2024 10:47:31 -0400 Subject: [PATCH 10/22] change split flag for 2 fpga projects to an int --- WriteVHDLSyntax.py | 44 ++++++++++++++++++++++---------------------- generator_hdl.py | 8 ++++---- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 3b55d09..08d9173 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -185,7 +185,7 @@ def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned mem = memMod.inst - if split and "in" not in mem: + if split == 2 and "in" not in mem: continue if "DL" in mtypeB and "AS" not in mtypeB: # Special case for DTC links that reads from FIFOs @@ -492,7 +492,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_din : " wirelist += "t_"+mtypeB+"_DATA;\n" - if not (interface == 1 and not split): + if not (interface == 1 and not split == 1): if memInfo.is_binned : wirelist += " signal "+mem+"_A_enb : " wirelist += "t_"+mtypeB+"_A1b;\n" @@ -641,7 +641,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay_portlist += " addra_out => "+mem+"_writeaddr_delay,\n" delay_portlist += " dina_out => "+mem+"_din_delay,\n" # add merge_stream modules if split and TPAR or AS - if "TPAR" in mem and split: + if "TPAR" in mem and split == 1: addrwidth = 10 ramwidth = memInfo.bitwidth numpages = 8 @@ -659,7 +659,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" merge_portlist += " bx_out => open,\n" - merge_portlist += " merged_dout => MTPAR_"+seed+PCGroup+"_stream_V_dout,\n" + merge_portlist += " merged_dout => MPAR_"+seed+PCGroup+"_stream_V_dout,\n" for i in range(4): merge_portlist += " din"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_V_dout,\n" for i in range(4): merge_portlist += " nent"+str(i)+"=>TPAR_"+seed+PCGroup[i%numInputs]+"_AV_dout_nent,\n" for i in range(numInputs): merge_portlist += " addr_arr("+str(((i+1)*addrwidth)-1)+" downto "+ str(i*addrwidth)+ ")=>TPAR_"+seed+PCGroup[i%numInputs]+"_V_readaddr,\n" @@ -667,7 +667,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl mem_str += " generic map (\n"+merge_parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+merge_portlist.rstrip(",\n")+"\n );\n\n" - elif "AS" in mem and "n1" in mem and split: + elif "AS" in mem and "n1" in mem and split == 1: addrwidth = 10 ramwidth = memInfo.bitwidth numpages = 8 @@ -892,12 +892,12 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split): string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" elif "AS" in mtypeB and split: #AS/TPAR at interface need to go through merging module string_output_mems += " "+mem+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth)+" downto 0);\n" - elif "TPAR" in mtypeB and split: + elif "TPAR" in mtypeB and split == 1: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if itc == PCGroup[0]: - string_output_mems += " MTPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth+2)+" downto 0);\n" + string_output_mems += " MPAR_"+seed+PCGroup+"_stream_V_dout : out std_logic_vector("+str(memMod.bitwidth+2)+" downto 0);\n" else: string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" @@ -978,7 +978,7 @@ def writeTBConstants(memDict, memInfoDict, procs, emData_dir, sector, split): mem_delay = procs.index(memInfo.downstream_mtype_short) # The delay in number of bx. The initial process of the chain will have 0 delay, the second have 1 bx delay etc. #FIXME - hack for fpga2 project - if split: + if split == 2: mem_delay = 0 string_constants += (" constant " + memInfo.mtype_short + "_DELAY").ljust(str_len) + ": integer := " + str(mem_delay) + "; --! Number of BX delays\n" @@ -1052,7 +1052,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi # Loop over all memory types string_ctrl_signals += "\n -- Signals matching ports of top-level VHDL\n" for mtypeB in memDict: - if split and ("TPROJ" in mtypeB or "VMSME" in mtypeB): + if split == 1 and ("TPROJ" in mtypeB or "VMSME" in mtypeB): continue memInfo = memInfoDict[mtypeB] @@ -1110,12 +1110,12 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += ("t_"+mtypeB+"_NENT").ljust(str_len2)+":= (others => '0'); -- (#page)(#bin)\n" string_ctrl_signals += (" signal "+mem+"_AV_dout_mask").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n" - elif split and "TPAR" in mem: + elif split == 1 and "TPAR" in mem: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if PCGroup[0] == itc: - string_ctrl_signals +=" signal MTPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector("+str(memMod.bitwidth+2)+" downto 0) := (others=> '0') ;\n" + string_ctrl_signals +=" signal MPAR_"+seed+PCGroup +"_stream_V_dout: std_logic_vector("+str(memMod.bitwidth+2)+" downto 0) := (others=> '0') ;\n" else: string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" @@ -1135,7 +1135,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi if memMod.is_binned: if "VMSME_D" in mem: disk = "DISK" - if "AS" in mem and "n1" in mem and split: + if "AS" in mem and "n1" in mem and split == 1: string_ctrl_signals += " signal "+mem+"_stream_V_dout : std_logic_vector("+str(memMod.bitwidth)+" downto 0) := (others => '0');\n" continue string_ctrl_signals += (" signal "+mem+"_wea").ljust(str_len)+": " @@ -1208,7 +1208,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_debug = "" for mtypeB in memDict: - if split and ("VMSME" in mtypeB or "TPROJ" in mtypeB): + if split == 1 and ("VMSME" in mtypeB or "TPROJ" in mtypeB): continue memInfo = memInfoDict[mtypeB] memList = memDict[mtypeB] @@ -1245,18 +1245,18 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_output += (" "+mem+"_enb_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" - elif ("TPAR" in mem) and split: + elif ("TPAR" in mem) and split == 1: seed = mem.split("_")[1][:-1] itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if PCGroup[0] == itc: - string_output += (" MTPAR_"+seed+PCGroup+"_stream_V_dout").ljust(str_len) + "=> MTPAR_"+seed+PCGroup+"_stream_V_dout,\n" + string_output += (" MPAR_"+seed+PCGroup+"_stream_V_dout").ljust(str_len) + "=> MPAR_"+seed+PCGroup+"_stream_V_dout,\n" else: string_output += (" "+mem+"_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" string_output += (" "+mem+"_V_dout").ljust(str_len) + "=> "+mem+"_dout,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> "+mem+"_AV_dout_nent,\n" - elif split and ("AS" in mtypeB and "n1" in mem): + elif split ==1 and ("AS" in mtypeB and "n1" in mem): string_output += (" "+mem+"_stream_V_dout").ljust(str_len) + "=> "+mem+"_stream_V_dout,\n" else: string_debug += (" "+mem+"_wea").ljust(str_len) + "=> "+mem+"_wea,\n" @@ -1293,7 +1293,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi for memMod in memList: mem = memMod.inst - if ("AS" in mem and "n1" in mem and split): + if ("AS" in mem and "n1" in mem and split == 1): #FIXME rewrite this to be a separate function width = memMod.bitwidth + 1 str_len = 16 # length of string for formatting purposes @@ -1359,7 +1359,7 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, mem = memMod.inst - if (("TPAR" in mem) or ("AS" in mem and "n1" in mem)) and split: #FIXME this is not good + if (("TPAR" in mem) or ("AS" in mem and "n1" in mem)) and split == 1: #FIXME FPGA1 hack width = 0 if "TPAR" in mem: width= memMod.bitwidth + 3 @@ -1367,10 +1367,10 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, itc = mem.split("_")[1][-1] for PCGroup in MPARdict[seed]: if PCGroup[0] != itc: continue - mem = "MTPAR_" + seed + PCGroup + mem = "MPAR_" + seed + PCGroup else: width= memMod.bitwidth + 1 - if "MTPAR" not in mem: continue #FIXME also not good + if "MPAR" not in mem: continue #FIXME also not good str_len = 16 # length of string for formatting purposes string_mem += " write"+mem+" : entity work.FileWriterFIFO\n" string_mem += " generic map (\n" @@ -1627,12 +1627,12 @@ def writeProcMemoryLHSPorts(argname,mem,split = False): """ string_mem_ports = "" - if ("TPROJ" in mem.inst) and split: #set TPROJ and VMSME to open for a split-FPGA project + if ("TPROJ" in mem.inst) and split == 1: #set TPROJ and VMSME to open for a split-FPGA project string_mem_ports += " "+argname+"_dataarray_data_V_ce0 => open,\n" string_mem_ports += " "+argname+"_dataarray_data_V_we0 => open,\n" string_mem_ports += " "+argname+"_dataarray_data_V_address0 => open,\n" string_mem_ports += " "+argname+"_dataarray_data_V_d0 => open,\n" - elif ("VMSME" in mem.inst and split): + elif ("VMSME" in mem.inst and split == 1): string_mem_ports += " "+argname+"_dataarray_0_data_V_ce0 => open,\n" string_mem_ports += " "+argname+"_dataarray_0_data_V_we0 => open,\n" string_mem_ports += " "+argname+"_dataarray_0_data_V_address0 => open,\n" diff --git a/generator_hdl.py b/generator_hdl.py index 5bd7dcb..d4bc074 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -220,7 +220,7 @@ def writeTBMemoryReads(memDict, memInfoDict, initial_proc, split): for mtypeB in memDict: memInfo = memInfoDict[mtypeB] memList = memDict[mtypeB] - if split and ("VMSME" in mtypeB or "TPROJ" in mtypeB): + if split == 1 and ("VMSME" in mtypeB or "TPROJ" in mtypeB): continue if memInfo.is_initial: first_mem = True if initial_proc in memInfo.downstream_mtype_short and not found_first_mem else False # first memory of the chain @@ -273,7 +273,7 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split): string_final = "" for mtypeB in memDict: - if split and ("VMSME" in mtypeB or "TPROJ" in mtypeB): + if split == 1 and ("VMSME" in mtypeB or "TPROJ" in mtypeB): continue memList = memDict[mtypeB] memInfo = memInfoDict[mtypeB] @@ -450,8 +450,8 @@ def getMemPrintDirectory(fname): help="Add debug ports corresponding to all BRAM inputs") parser.add_argument('-de', '--delay', type=int, default=0, help="Number of pipeline stages in between processing and memory modules to include, setting 0 does not include pipeline modules") - parser.add_argument('-sp', '--split', action='store_true', - help="enables split-fpga project") + parser.add_argument('-sp', '--split', type =int, default=0, + help="enables split-fpga project, a value of 1 for first-fpga project, 2 for second-fpga, 0 for single fpga projects") parser.add_argument('-f2', '--fpga2', action='store_true', help="enables split-fpga2 project") From 8c8bf82c8693655d589caedf5054f1412c024219 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 11:05:47 -0400 Subject: [PATCH 11/22] add more flags --- TrackletGraph.py | 6 ++++++ WriteVHDLSyntax.py | 2 +- generator_hdl.py | 24 +++++++++++++----------- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index b7faf37..d6d5150 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -848,6 +848,12 @@ def add_connected_proc_modules(aMemModule, ProcList=[], MemList=[]): #def count_proc_steps_downstream(aProcModule, ProcList=[]): + @staticmethod + def get_PC_dict(): + #returns a dict which containing info related to the mergining + #of TPROJ memories for split FPGA projects + PC_dict = {} + return PC_dict @staticmethod def get_slice_around_proc(aProcModule, nStepsUp=0, nStepsDown=0): """ Get a slice of the tracklet project that centers around the diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 08d9173..f0b86bb 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -618,7 +618,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay2_portlist += " reset => reset,\n" #FIXME if not "in" in mem : - if "VMSMER" in memmod.upstreams[0].mtype_short() or "PC" in memmod.upstreams[0].mtype_short(): + if ("VMSMER" in memmod.upstreams[0].mtype_short() or "PC" in memmod.upstreams[0].mtype_short()) and split == 2: delay2_portlist += " done => PC_done,\n" delay2_portlist += " bx_out => PC_bx_out,\n" else: diff --git a/generator_hdl.py b/generator_hdl.py index d4bc074..3dbef4e 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -31,7 +31,7 @@ # Memories ######################################## -def writeMemoryModules(memDict, memInfoDict, extraports , delay, fpga2, split = False): +def writeMemoryModules(memDict, memInfoDict, extraports , delay, split = 0): """ # Inputs: # memDict = dictionary of memories organised by type @@ -47,7 +47,7 @@ def writeMemoryModules(memDict, memInfoDict, extraports , delay, fpga2, split = # FIFO memories are not instantiated in top-level (at end of chain?) if memInfo.isFIFO: continue - if (("VMSME" in mtypeB and split) or ("TPROJ" in mtypeB and split)) and not fpga2: + if (("VMSME" in mtypeB and split == 1) or ("TPROJ" in mtypeB and split == 1)): continue string_wires_inst, string_mem_inst = writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = delay, split = split) @@ -59,7 +59,7 @@ def writeMemoryModules(memDict, memInfoDict, extraports , delay, fpga2, split = ######################################## # Processing modules ######################################## -def writeProcModules(proc_list, hls_src_dir, extraports, delay, split = False): +def writeProcModules(proc_list, hls_src_dir, extraports, delay, split = 0): """ # proc_list: a list of processing modules # hls_src_dir: string pointing to the HLS directory, used to extract constants @@ -75,6 +75,8 @@ def writeProcModules(proc_list, hls_src_dir, extraports, delay, split = False): proc_type_list = [] for aProcMod in proc_list: + if "PC" in aProcMod.mtype and split == 1: + continue if not aProcMod.mtype in proc_type_list: # Is this aProcMod the first of its type proc_wire_inst,proc_func_inst = writeModuleInstance(aProcMod, hls_src_dir, True, extraports, delay, split) proc_type_list.append(aProcMod.mtype) @@ -138,14 +140,14 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, if memInfo.isFIFO: string_output_mems += writeTrackStreamRHSPorts_interface(mtypeB, memDict) else: - if not (("TPROJ" in mtypeB or "VMSME" in mtypeB) and args.split): + if not (("TPROJ" in mtypeB or "VMSME" in mtypeB) and args.split == 1): string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,memDict, split) elif extraports: # Debug ports corresponding to BRAM inputs. string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, extraports) - if (memInfo.mtype_long == "AllStubs" and args.split): #for split fpga we want AS sent to second device + if (memInfo.mtype_long == "AllStubs" and args.split == 1): #for split fpga we want AS sent to second device ASmemDict = {mtypeB : []} for mem in memList: if "n1" in mem.inst: ASmemDict[mtypeB].append(mem) @@ -161,7 +163,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, ######################################## # Top file ######################################## -def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraports, delay, fpga2, split = False): +def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraports, delay, split = False): """ # Inputs: # memDict = dictionary of memories organised by type @@ -172,7 +174,7 @@ def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraport # Write memories string_memWires = "" string_memModules = "" - memWires_inst,memModules_inst = writeMemoryModules(memDict, memInfoDict, extraports, delay, fpga2, split) + memWires_inst,memModules_inst = writeMemoryModules(memDict, memInfoDict, extraports, delay, split) string_memWires += memWires_inst string_memModules += memModules_inst @@ -453,9 +455,6 @@ def getMemPrintDirectory(fname): parser.add_argument('-sp', '--split', type =int, default=0, help="enables split-fpga project, a value of 1 for first-fpga project, 2 for second-fpga, 0 for single fpga projects") - parser.add_argument('-f2', '--fpga2', action='store_true', - help="enables split-fpga2 project") - parser.add_argument('--memprints_dir', type=str, default="../../../../../MemPrints/", help="Directory where emulation printouts are stored") parser.add_argument('-ng','--no_graph', action='store_true', @@ -494,6 +493,9 @@ def getMemPrintDirectory(fname): process_list.extend(process) memory_list.extend(memory) + PC_dict = TrackletGraph.get_PC_dict() + + print(PC_dict) # Remove duplicates from the process and module list process_list = list(set(process_list)) memory_list = list(set(memory_list)) @@ -565,7 +567,7 @@ def getMemPrintDirectory(fname): ############### # Top File string_topfile = writeTopFile(topfunc, process_list, - memDict, memInfoDict, args.hls_dir, args.extraports, args.delay, args.fpga2, args.split) + memDict, memInfoDict, args.hls_dir, args.extraports, args.delay, args.split) ############### # Test bench From b75ffe5cc7de0f901423f4ca930182c7fb5577c9 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 13:30:06 -0400 Subject: [PATCH 12/22] fix some bugs --- WriteVHDLSyntax.py | 24 +++++++++++++----------- generator_hdl.py | 26 ++++++++++++++++---------- 2 files changed, 29 insertions(+), 21 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index f0b86bb..4454002 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -525,7 +525,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "STD_LOGIC;\n" wirelist += " signal "+mem+"_index : " wirelist += "STD_LOGIC_VECTOR(31 downto 0);\n" - if memInfo.has_numEntries_out: + if memInfo.has_numEntries_out or (split == 1 and "AS" in mem): if memInfo.is_binned: disk="" if "VMSME_D" in mem: @@ -654,7 +654,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_parameterlist += " NUM_PAGES => "+str(numpages)+",\n" merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" merge_parameterlist += " NUM_EXTRA_BITS => 2,\n" - merge_portlist += " bx_in => TP_bx_out_0,\n" + merge_portlist += " bx_in => TP_bx_out,\n" merge_portlist += " rst => '0',\n" merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" @@ -676,7 +676,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl merge_parameterlist += " NUM_PAGES => "+str(numpages)+",\n" merge_parameterlist += " NUM_INPUTS => "+str(numInputs)+",\n" merge_parameterlist += " NUM_EXTRA_BITS => 0,\n" - merge_portlist += " bx_in => TP_bx_out_0,\n" + merge_portlist += " bx_in => TP_bx_out,\n" merge_portlist += " rst => '0',\n" merge_portlist += " clk => clk,\n" merge_portlist += " enb_arr => open,\n" @@ -699,10 +699,11 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " sync_nent => PC_start,\n" elif "MPAR" in mem and "in" not in mem: portlist += " sync_nent => "+mem+"_start,\n" + elif "AS" in mem and "n1" in mem and split == 1: + portlist += " sync_nent => TP_L1L2A_start,\n" else: portlist += " sync_nent => "+sync_signal+",\n" - - if memmod.has_numEntries_out: + if memmod.has_numEntries_out or ("n1" in mem and split == 1): if memList[0].is_binned: ncopy = getVMStubNCopy(memmod); portlist += " enb => (" @@ -777,21 +778,22 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl return wirelist,mem_str -def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, delay = 0): +def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, delay = 0, split = 0): """ # Top-level interface: control signals """ final_proc_short = final_procs[0].split("_")[0] - string_ctrl_signals = "" string_ctrl_signals += " clk : in std_logic;\n" string_ctrl_signals += " reset : in std_logic;\n" string_ctrl_signals += " "+initial_proc+"_start : in std_logic;\n" string_ctrl_signals += " "+initial_proc+"_bx_in : in std_logic_vector(2 downto 0);\n" - string_ctrl_signals += " "+initial_proc+"_bx_out : out std_logic_vector(2 downto 0);\n" - string_ctrl_signals += " "+initial_proc+"_bx_out_vld : out std_logic;\n" - string_ctrl_signals += " "+initial_proc+"_done : out std_logic;\n" + if split == 2: + string_ctrl_signals += " "+initial_proc+"_bx_out : out std_logic_vector(2 downto 0);\n" + string_ctrl_signals += " "+initial_proc+"_bx_out_vld : out std_logic;\n" + string_ctrl_signals += " "+initial_proc+"_done : out std_logic;\n" + string_ctrl_signals += " "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n" string_ctrl_signals += " "+final_proc_short+"_bx_out_vld : out std_logic;\n" string_ctrl_signals += " "+final_proc_short+"_done : out std_logic;\n" @@ -1696,7 +1698,7 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0): string_mem_ports += " "+argname+"_dataarray_data_V_q"+str(portindex)+" => " string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_V_dout,\n" - if mem.has_numEntries_out and portindex == 0: + if (mem.has_numEntries_out and portindex == 0): if mem.is_binned: string_mem_ports += " "+argname+"_nentries_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_nent,\n" string_mem_ports += " "+argname+"_nentries_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_nent,\n" diff --git a/generator_hdl.py b/generator_hdl.py index 3dbef4e..e4c9571 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -43,6 +43,12 @@ def writeMemoryModules(memDict, memInfoDict, extraports , delay, split = 0): # Loop over memory type for mtypeB in memDict: memList = memDict[mtypeB] + if split == 1 and "AS" in mtypeB: + tempList = [] + for mem in memList: + if "n2" not in mem.inst: + tempList.append(mem) + memList = tempList memInfo = memInfoDict[mtypeB] # FIFO memories are not instantiated in top-level (at end of chain?) if memInfo.isFIFO: @@ -75,7 +81,7 @@ def writeProcModules(proc_list, hls_src_dir, extraports, delay, split = 0): proc_type_list = [] for aProcMod in proc_list: - if "PC" in aProcMod.mtype and split == 1: + if ("PC" in aProcMod.mtype or "VMSMER" in aProcMod.mtype) and split == 1: continue if not aProcMod.mtype in proc_type_list: # Is this aProcMod the first of its type proc_wire_inst,proc_func_inst = writeModuleInstance(aProcMod, hls_src_dir, True, extraports, delay, split) @@ -118,11 +124,11 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, if extraports and (not proc.is_last): notfinal_procs_tmp[proc.mtype_short()] = None # Use dictionary as set notfinal_procs = notfinal_procs_tmp.keys() - + final_procs.sort() string_topmod_interface = writeTopModuleOpener(topmodule_name) # Write control signals - string_ctrl_signals = writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, delay = delay) + string_ctrl_signals = writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, delay = delay, split = split) string_input_mems = "" string_output_mems = "" @@ -149,8 +155,9 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, if (memInfo.mtype_long == "AllStubs" and args.split == 1): #for split fpga we want AS sent to second device ASmemDict = {mtypeB : []} - for mem in memList: - if "n1" in mem.inst: ASmemDict[mtypeB].append(mem) + for mem in memList: + if "n1" in mem.inst: + ASmemDict[mtypeB].append(mem) string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo, ASmemDict, split) string_topmod_interface += string_ctrl_signals @@ -443,7 +450,7 @@ def getMemPrintDirectory(fname): help="Detector region. A: all, L: barrel, D: disk") parser.add_argument('--uut', type=str, default=None, help="Unit Under Test") - parser.add_argument('--mut', type=str, choices=["IR","VMR", "TE", "TC", "PR", "PC", "ME", "MC", "FT"], default=None, help="Module Under Test") + parser.add_argument('--mut', type=str, choices=["IR","VMR", "TE", "TC", "PR","TP", "PC", "ME", "MC", "FT"], default=None, help="Module Under Test") parser.add_argument('-u', '--nupstream', type=int, default=0, help="Number of upstream processing steps to include") parser.add_argument('-d', '--ndownstream', type=int, default=0, @@ -482,8 +489,9 @@ def getMemPrintDirectory(fname): if args.mut is not None: # Get all module units of a given type - mutModules = tracklet.get_all_module_units(args.mut) - + mutModules = tracklet.get_all_module_units(args.mut,args.split) + for mut in mutModules: + print(mut) # Get the slices around each of the modules process_list = [] memory_list = [] @@ -495,11 +503,9 @@ def getMemPrintDirectory(fname): PC_dict = TrackletGraph.get_PC_dict() - print(PC_dict) # Remove duplicates from the process and module list process_list = list(set(process_list)) memory_list = list(set(memory_list)) - # Correct mem.is_initial & mem.is_final, as loop over mutModules overwrites them incorrectly. for mem in memory_list: if mem.is_initial: From 6edfa77c937d561a4c193a532d153b56d4adb01a Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 13:30:17 -0400 Subject: [PATCH 13/22] fix fixme --- TrackletGraph.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index d6d5150..47e1b89 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -634,12 +634,15 @@ def get_proc_module(self, instance_name, verbose=True): print("WARNING!! Cannot find module", instance_name,"!!") return None - def get_all_module_units(self, module): + def get_all_module_units(self, module, split = 0): "Return all the ProcModule objects of a given type" modules = {} for instance_name in self.__proc_dict: #FIXME - if instance_name.startswith(module+"_") or instance_name.startswith("VMSMER_"): + if split == 2: + if instance_name.startswith(module+"_") or instance_name.startswith("VMSMER_"): + modules[instance_name]=self.__proc_dict[instance_name] + elif instance_name.startswith(module+"_"): modules[instance_name]=self.__proc_dict[instance_name] if not modules: print("WARNING!! Cannot find any modules with name starting with", module,"!!") From eae4a76113201eb4d56152c1b5cbaa1e7d0be49b Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 13:49:38 -0400 Subject: [PATCH 14/22] small fix --- WriteVHDLSyntax.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 4454002..4fe91ab 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -701,6 +701,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " sync_nent => "+mem+"_start,\n" elif "AS" in mem and "n1" in mem and split == 1: portlist += " sync_nent => TP_L1L2A_start,\n" + elif "TPAR" in mem and split == 1: + portlist += " sync_nent => TP_done,\n" else: portlist += " sync_nent => "+sync_signal+",\n" if memmod.has_numEntries_out or ("n1" in mem and split == 1): From 175d3cbf91b3e1a64699751642863495abeb1094 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 14:27:48 -0400 Subject: [PATCH 15/22] fix bugs --- WriteHDLUtils.py | 4 ++-- WriteVHDLSyntax.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/WriteHDLUtils.py b/WriteHDLUtils.py index cfaa736..3eb3c2a 100644 --- a/WriteHDLUtils.py +++ b/WriteHDLUtils.py @@ -1352,7 +1352,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars, if "DL" in memory.inst and "AS" not in memory.inst: # DTCLink string_mem_ports += writeProcDTCLinkRHSPorts(tmp_argname,memory) else: - string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory) + string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory, split=split) if portname.replace("outer","").find("out") != -1: if memory.isFIFO(): @@ -1362,7 +1362,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars, if portname.find("trackpar") != -1 and (module.mtype == "TrackletCalculator" or module.mtype == "TrackletProcessor"): string_mem_ports += writeProcMemoryLHSPorts(tmp_argname,memory,split) elif portname.find("trackpar") != -1 and module.mtype == "PurgeDuplicates": - string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory) + string_mem_ports += writeProcMemoryRHSPorts(tmp_argname,memory,split=split) # Remove the already added module and name from the lists portNameList.remove(portname) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 4fe91ab..8298347 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -1661,7 +1661,7 @@ def writeProcMemoryLHSPorts(argname,mem,split = False): return string_mem_ports -def writeProcMemoryRHSPorts(argname,mem,portindex=0): +def writeProcMemoryRHSPorts(argname,mem,portindex=0, split = 0): """ # Processing module port assignment: inputs from memories """ @@ -1707,7 +1707,7 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0): string_mem_ports += " "+argname+"_nentries_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_AV_dout_nent,\n" for i in range(0,2**mem.bxbitwidth): nrz = 8 - if mem.var()[0] == "D" : + if mem.var()[0] == "D" and split == 2: nrz = 16 for j in range(0,nrz): string_mem_ports += " "+argname+"_binmask8_"+str(i)+"_V_"+str(j)+" => (" From d2b3d656e35f29d10fe4254de7459879bac377aa Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 17:02:04 -0400 Subject: [PATCH 16/22] update for TPAR addr size --- WriteVHDLSyntax.py | 42 +++++++++++++++++++++++++----------------- generator_hdl.py | 7 +++---- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 8298347..a9cacc0 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -192,7 +192,7 @@ def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned string_mem += " read" + mem + " : entity work.FileReaderFIFO\n" string_mem += " generic map (\n" memtmp = mem.replace("twoS","2S") - string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_DL&\""+ memtmp + "\"&inputFileNameEnding,\n" + string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_DL_39&\""+ memtmp + "\"&inputFileNameEnding,\n" string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n" string_mem += " FIFO_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n" string_mem += " DEBUG".ljust(str_len) + "=> true,\n" @@ -461,7 +461,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl if "MPAR" in mem and not "in" in mem: interface = 0 extraports = False - if "AS" in mem and not "in" in mem: + if "AS" in mem and not "in" in mem and split == 2: interface = 0 extraports = False merge_parameterlist = "" @@ -485,7 +485,9 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_din_delay : " wirelist += "t_"+mtypeB+"_DATA;\n" - if (interface != -1 and not extraports): + if (interface != -1 and not extraports) or (split == 1 and "TPAR" in mem): + if "TPAR" in mem: + wirelist += " signal "+mem+"_dummy : std_logic_vector(1 downto 0);\n" wirelist += " signal "+mem+"_wea : " wirelist += "t_"+mtypeB+"_1b;\n" wirelist += " signal "+mem+"_writeaddr : " @@ -813,7 +815,7 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del return string_ctrl_signals -def writeMemoryLHSPorts_interface(memList, mtypeB, extraports=False): +def writeMemoryLHSPorts_interface(memList, mtypeB, extraports=False,split = 0): """ # Top-level interface: input memories' ports. """ @@ -840,7 +842,7 @@ def writeMemoryLHSPorts_interface(memList, mtypeB, extraports=False): if "in" not in mem: continue if "AS" in mem: - if "in" not in mem: + if "in" not in mem and split == 2: continue string_input_mems += " "+mem+"_wea : "+direction+" t_"+mtypeB+"_1b;\n" @@ -1042,10 +1044,10 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += (" signal "+mid_proc+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n" string_ctrl_signals += (" signal "+mid_proc+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n" string_ctrl_signals += (" signal "+mid_proc+"_done").ljust(str_len)+": std_logic := '0';\n" - string_ctrl_signals += (" signal "+final_procs[0].mtype_short()+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n" - string_ctrl_signals += (" signal "+final_procs[0].mtype_short()+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n" - string_ctrl_signals += (" signal "+final_procs[0].mtype_short()+"_done").ljust(str_len)+": std_logic := '0';\n" - if final_procs[0].mtype_short().startswith("FT"): + string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n" + string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n" + string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_done").ljust(str_len)+": std_logic := '0';\n" + if final_procs[-1].mtype_short().startswith("FT"): for final_proc in final_procs: string_ctrl_signals += (" signal "+final_proc.inst+"_last_track").ljust(str_len)+": std_logic := '0';\n" string_ctrl_signals += (" signal "+final_proc.inst+"_last_track_vld").ljust(str_len)+": std_logic := '0';\n" @@ -1182,7 +1184,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc """ str_len = 35 # length of string for formatting purposes - string_fwblock_inst = " sectorProcFull : if INST_TOP_TF = 1 generate\n" if notfinal_procs or final_procs[0].mtype_short() == initial_proc else " sectorProc : if INST_TOP_TF = 0 generate\n" + string_fwblock_inst = " sectorProcFull : if INST_TOP_TF = 1 generate\n" if notfinal_procs or final_procs[-1].mtype_short() == initial_proc else " sectorProc : if INST_TOP_TF = 0 generate\n" string_fwblock_inst += " begin\n" string_fwblock_inst += " uut : entity work." + topfunc + "\n" string_fwblock_inst += " port map(\n" @@ -1190,10 +1192,10 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_fwblock_inst += " reset".ljust(str_len) + "=> reset,\n" string_fwblock_inst += (" " + initial_proc + "_start").ljust(str_len) + "=> " + initial_proc + "_start,\n" string_fwblock_inst += (" " + initial_proc + "_bx_in").ljust(str_len) + "=> " + initial_proc + "_bx_in,\n" - string_fwblock_inst += (" " + final_procs[0].mtype_short() + "_bx_out").ljust(str_len) + "=> " + final_procs[0].mtype_short() + "_bx_out,\n" - string_fwblock_inst += (" " + final_procs[0].mtype_short() + "_bx_out_vld").ljust(str_len) + "=> " + final_procs[0].mtype_short() + "_bx_out_vld,\n" - string_fwblock_inst += (" " + final_procs[0].mtype_short() + "_done").ljust(str_len) + "=> " + final_procs[0].mtype_short() + "_done,\n" - if final_procs[0].mtype_short().startswith("FT"): + string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_bx_out").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out,\n" + string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_bx_out_vld").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out_vld,\n" + string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_done").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_done,\n" + if final_procs[-1].mtype_short().startswith("FT"): for final_proc in final_procs : string_fwblock_inst += (" " + final_proc.inst + "_last_track").ljust(str_len) + "=> " + final_proc.inst + "_last_track,\n" string_fwblock_inst += (" " + final_proc.inst + "_last_track_vld").ljust(str_len) + "=> " + final_proc.inst + "_last_track_vld,\n" @@ -1276,7 +1278,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_fwblock_inst += string_output[:-2]+"\n" # Remove the last comma string_fwblock_inst += " );\n" - string_fwblock_inst += " end generate sectorProcFull;\n\n" if notfinal_procs or final_procs[0].mtype_short() == initial_proc else " end generate sectorProc;\n\n" + string_fwblock_inst += " end generate sectorProcFull;\n\n" if notfinal_procs or final_procs[-1].mtype_short() == initial_proc else " end generate sectorProc;\n\n" return string_fwblock_inst @@ -1653,8 +1655,14 @@ def writeProcMemoryLHSPorts(argname,mem,split = False): string_mem_ports += " "+argname+"_dataarray_data_V_ce0 => open,\n" string_mem_ports += " "+argname+"_dataarray_data_V_we0 => " string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_wea,\n" - string_mem_ports += " "+argname+"_dataarray_data_V_address0 => " - string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_writeaddr,\n" + if "TPAR" in mem.inst and split == 1 : #FIXME TPAR addr from TP should be 10 bits + string_mem_ports += " "+argname+"_dataarray_data_V_address0(9 downto 0) => " + string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_writeaddr,\n" + string_mem_ports += " "+argname+"_dataarray_data_V_address0(11 downto 10) => " + string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_dummy,\n" + else: + string_mem_ports += " "+argname+"_dataarray_data_V_address0 => " + string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_writeaddr,\n" string_mem_ports += " "+argname+"_dataarray_data_V_d0 => " string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_din,\n" diff --git a/generator_hdl.py b/generator_hdl.py index e4c9571..420b810 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -140,7 +140,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, if "DL" in mtypeB: # DTCLink string_input_mems += writeDTCLinkLHSPorts_interface(mtypeB, memDict) else: - string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB) + string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, split = split) elif memInfo.is_final: # Output arguments if memInfo.isFIFO: @@ -148,10 +148,9 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, else: if not (("TPROJ" in mtypeB or "VMSME" in mtypeB) and args.split == 1): string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,memDict, split) - elif extraports: # Debug ports corresponding to BRAM inputs. - string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, extraports) + string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, extraports, split = split) if (memInfo.mtype_long == "AllStubs" and args.split == 1): #for split fpga we want AS sent to second device ASmemDict = {mtypeB : []} @@ -355,7 +354,7 @@ def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrint string_header += writeTBPreamble() string_header += writeTBOpener(tbfunc) - string_constants = writeTBConstants(memDict, memInfoDict, notfinal_procs+[final_procs[0].mtype_short()], memPrintsDir, sector, split) + string_constants = writeTBConstants(memDict, memInfoDict, notfinal_procs+[final_procs[-1].mtype_short()], memPrintsDir, sector, split) # A bodge for TrackBuilder to write TF concatenated track+stub data. # (Needed to compare with emData/). if 'TW_104' in memInfoDict.keys(): From 07d04fcec2b50452b074de6cabc5fcdcde402301 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 17:33:11 -0400 Subject: [PATCH 17/22] update to remove hardcoded dict --- TrackletGraph.py | 18 ++++++++++++------ WriteVHDLSyntax.py | 21 +++++---------------- 2 files changed, 17 insertions(+), 22 deletions(-) diff --git a/TrackletGraph.py b/TrackletGraph.py index 47e1b89..4c6c212 100644 --- a/TrackletGraph.py +++ b/TrackletGraph.py @@ -648,6 +648,18 @@ def get_all_module_units(self, module, split = 0): print("WARNING!! Cannot find any modules with name starting with", module,"!!") else: return modules + def get_MPAR_dict(self): + #returns a dict which containing info related to the mergining + #of TPROJ memories for split FPGA projects + MPAR_dict = {} + PC_dict = self.get_all_module_units("PC") + for key, value in PC_dict.items(): + iTCs = key[7:] + seed = key[3:7] + if seed not in MPAR_dict: + MPAR_dict[seed] = [] + MPAR_dict[seed].append(iTCs) + return MPAR_dict def get_mem_module(self, instance_name, verbose=True): " Return a MemModule object given the instance name " @@ -851,12 +863,6 @@ def add_connected_proc_modules(aMemModule, ProcList=[], MemList=[]): #def count_proc_steps_downstream(aProcModule, ProcList=[]): - @staticmethod - def get_PC_dict(): - #returns a dict which containing info related to the mergining - #of TPROJ memories for split FPGA projects - PC_dict = {} - return PC_dict @staticmethod def get_slice_around_proc(aProcModule, nStepsUp=0, nStepsDown=0): """ Get a slice of the tracklet project that centers around the diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index a9cacc0..29581f5 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -1,16 +1,5 @@ from builtins import range from TrackletGraph import MemModule, ProcModule, MemTypeInfoByKey -#following dictionary tracks which trackletparameters are grouped together by merging module -MPARdict = { - "L5L6" : ["ABCD"], - "L2L3" : ["ABCD"], - "L3L4" : ["AB","CD"], - "L2D1" : ["ABCD"], - "L1D1" : ["ABCD","EFGH"], - "D1D2" : ["ABCD"], - "D3D4" : ["ABCD"], - "L1L2" : ["ABC","JKL","DE","G","F","HI"] -} def getVMStubNCopy(memmod): mem = memmod.inst; @@ -411,7 +400,7 @@ def writeMemoryUtil(memDict, memInfoDict): return ss; -def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, split = False): +def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, split = False, MPARdict = 0): """ # Declaration of memories of type "mtype" (e.g. TPROJ) & associated wires # Inputs: @@ -868,7 +857,7 @@ def writeDTCLinkLHSPorts_interface(mtypeB, memDict): string_input_mems += " "+mem+"_link_read : out t_"+mtypeB+"_1b;\n" return string_input_mems -def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split): +def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0): """ # Top-level interface: output memories' ports. # Inputs: @@ -1015,7 +1004,7 @@ def writeTBConstants(memDict, memInfoDict, procs, emData_dir, sector, split): return string_constants -def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs, split = False): +def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs, split = False, MPARdict = 0): """ # VHDL test bench: write control signals @@ -1169,7 +1158,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi return string_ctrl_signals -def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_procs, notfinal_procs = [], split = False): +def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_procs, notfinal_procs = [], split = False, MPARdict = 0): """ # VHDL test bench: write the instantiation of the top level SectorProcessor FW @@ -1344,7 +1333,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi return string_mem -def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, split): +def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned, split, MPARdict = 0): """ # VHDL test bench: write the loop that writes the output from the end-of-chain BRAM memories to text files # Inputs: From f18a63139a8069df66d30d08b3740a89e67fb9b9 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 17:37:35 -0400 Subject: [PATCH 18/22] add missing change from commit --- generator_hdl.py | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/generator_hdl.py b/generator_hdl.py index 420b810..8c19bbd 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -31,7 +31,7 @@ # Memories ######################################## -def writeMemoryModules(memDict, memInfoDict, extraports , delay, split = 0): +def writeMemoryModules(memDict, memInfoDict, extraports , delay, split = 0, MPARdict = 0): """ # Inputs: # memDict = dictionary of memories organised by type @@ -56,7 +56,7 @@ def writeMemoryModules(memDict, memInfoDict, extraports , delay, split = 0): if (("VMSME" in mtypeB and split == 1) or ("TPROJ" in mtypeB and split == 1)): continue - string_wires_inst, string_mem_inst = writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = delay, split = split) + string_wires_inst, string_mem_inst = writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = delay, split = split, MPARdict = MPARdict) string_wires += string_wires_inst string_mem += string_mem_inst @@ -96,7 +96,7 @@ def writeProcModules(proc_list, hls_src_dir, extraports, delay, split = 0): ######################################## # Top function interface ######################################## -def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, extraports, delay, split, streamIO=False): +def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, extraports, delay, split, streamIO=False, MPARdict = 0): """ # topmodule_name: name of the top module # process_list: list of all processing functions in the block (in this function, this list is @@ -147,7 +147,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, string_output_mems += writeTrackStreamRHSPorts_interface(mtypeB, memDict) else: if not (("TPROJ" in mtypeB or "VMSME" in mtypeB) and args.split == 1): - string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,memDict, split) + string_output_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo,memDict, split, MPARdict = MPARdict) elif extraports: # Debug ports corresponding to BRAM inputs. string_input_mems += writeMemoryLHSPorts_interface(memList, mtypeB, extraports, split = split) @@ -157,7 +157,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, for mem in memList: if "n1" in mem.inst: ASmemDict[mtypeB].append(mem) - string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo, ASmemDict, split) + string_input_mems += writeMemoryRHSPorts_interface(mtypeB, memInfo, ASmemDict, split, MPARdict = MPARdict) string_topmod_interface += string_ctrl_signals string_topmod_interface += string_input_mems @@ -169,7 +169,7 @@ def writeTopModule_interface(topmodule_name, process_list, memDict, memInfoDict, ######################################## # Top file ######################################## -def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraports, delay, split = False): +def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraports, delay, split = False, MPARdict = 0): """ # Inputs: # memDict = dictionary of memories organised by type @@ -180,7 +180,7 @@ def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraport # Write memories string_memWires = "" string_memModules = "" - memWires_inst,memModules_inst = writeMemoryModules(memDict, memInfoDict, extraports, delay, split) + memWires_inst,memModules_inst = writeMemoryModules(memDict, memInfoDict, extraports, delay, split, MPARdict) string_memWires += memWires_inst string_memModules += memModules_inst @@ -196,7 +196,7 @@ def writeTopFile(topfunc, process_list, memDict, memInfoDict, hls_dir, extraport # Top function interface string_topmod_interface = writeTopModule_interface(topfunc, process_list, - memDict, memInfoDict, extraports, delay, split) + memDict, memInfoDict, extraports, delay, split, MPARdict=MPARdict) string_src = "" string_src += writeTopPreamble() @@ -247,7 +247,7 @@ def writeTBMemoryReads(memDict, memInfoDict, initial_proc, split): # string_read += "\n" return string_read -def writeFWBlockInstantiation(topfunc, memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split): +def writeFWBlockInstantiation(topfunc, memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split,MPARdict): """ # topfunc: name of the top module # memDict: dictionary of memories organised by type @@ -264,12 +264,12 @@ def writeFWBlockInstantiation(topfunc, memDict, memInfoDict, initial_proc, final # Instantiate both the "normal" and the "Full" topfunc = topfunc[:-4] if topfunc[-4:] == "Full" else topfunc if initial_proc not in final_procs[0].mtype_short(): # For a single module the normal and the full are the same - string_instantiaion += writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_procs,split=split) - string_instantiaion += writeFWBlockInstance(topfunc+"Full", memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split=split) + string_instantiaion += writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_procs,split=split,MPARdict=MPARdict) + string_instantiaion += writeFWBlockInstance(topfunc+"Full", memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split=split,MPARdict=MPARdict) return string_instantiaion -def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split): +def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split, MPARdict): """ # memDict: dictionary of memories organised by type # & no. of bits (TPROJ_58 etc.) @@ -304,7 +304,7 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split): if memInfo.isFIFO: string_final += string_tmp else: - string_final += writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, memInfo.bxbitwidth, memInfo.is_binned, split) + string_final += writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, memInfo.bxbitwidth, memInfo.is_binned, split, MPARdict = MPARdict) elif not memInfo.is_initial: # intermediate memories if memInfo.isFIFO: string_intermediate += string_tmp @@ -323,7 +323,7 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split): return string_write -def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrintsDir, sector="04", split = False): +def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrintsDir, sector="04", split = False, MPARdict = 0): """ # Inputs: # tbfunc: name of the testbench @@ -361,15 +361,15 @@ def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrint fileTF = open("bodge/TF_tb_constants.vhd.bodge") string_constants += fileTF.read(); - string_ctrl_signals = writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split) + string_ctrl_signals = writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split, MPARdict) string_begin = writeTBEntityBegin() string_mem_read = writeTBMemoryReads(memDict, memInfoDict, initial_proc,split) string_mem_stim = writeTBMemoryStimulusProcess(initial_proc) - string_fwblock_inst = writeFWBlockInstantiation(topfunc, memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split=split) + string_fwblock_inst = writeFWBlockInstantiation(topfunc, memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split=split,MPARdict=MPARdict) - string_mem_write = writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split) + string_mem_write = writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split,MPARdict) string_tb = "" string_tb += string_header @@ -489,8 +489,6 @@ def getMemPrintDirectory(fname): # Get all module units of a given type mutModules = tracklet.get_all_module_units(args.mut,args.split) - for mut in mutModules: - print(mut) # Get the slices around each of the modules process_list = [] memory_list = [] @@ -500,7 +498,7 @@ def getMemPrintDirectory(fname): process_list.extend(process) memory_list.extend(memory) - PC_dict = TrackletGraph.get_PC_dict() + MPARdict = tracklet.get_MPAR_dict() # Remove duplicates from the process and module list process_list = list(set(process_list)) @@ -572,13 +570,13 @@ def getMemPrintDirectory(fname): ############### # Top File string_topfile = writeTopFile(topfunc, process_list, - memDict, memInfoDict, args.hls_dir, args.extraports, args.delay, args.split) + memDict, memInfoDict, args.hls_dir, args.extraports, args.delay, args.split, MPARdict = MPARdict) ############### # Test bench tb_name = "tb_tf_top" string_testbench = writeTestBench( - tb_name, topfunc, process_list, memDict, memInfoDict, args.memprints_dir, split = args.split) + tb_name, topfunc, process_list, memDict, memInfoDict, args.memprints_dir, split = args.split, MPARdict = MPARdict) ############### # tcl string_tcl = writeTcl(args.projname, topfunc, args.memprints_dir) From de44eebededab29dd72ccc98c97c9526ac57e0b4 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 17:41:44 -0400 Subject: [PATCH 19/22] only gen dictionary for split projects --- generator_hdl.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generator_hdl.py b/generator_hdl.py index 8c19bbd..eef550d 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -498,7 +498,8 @@ def getMemPrintDirectory(fname): process_list.extend(process) memory_list.extend(memory) - MPARdict = tracklet.get_MPAR_dict() + if args.split == 1 : + MPARdict = tracklet.get_MPAR_dict() # Remove duplicates from the process and module list process_list = list(set(process_list)) From c617d874f0c099d51c7f3520a28ceb963293dfc1 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 20:20:16 -0400 Subject: [PATCH 20/22] add default value for mpar_dict for other projects --- generator_hdl.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generator_hdl.py b/generator_hdl.py index eef550d..66ee73b 100755 --- a/generator_hdl.py +++ b/generator_hdl.py @@ -500,7 +500,8 @@ def getMemPrintDirectory(fname): if args.split == 1 : MPARdict = tracklet.get_MPAR_dict() - + else: + MPARdict = None # Remove duplicates from the process and module list process_list = list(set(process_list)) memory_list = list(set(memory_list)) From 04753f7c6a49a1781b83221e0d5b302916b27d9c Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 29 Jul 2024 20:37:25 -0400 Subject: [PATCH 21/22] add missing split tags --- WriteHDLUtils.py | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/WriteHDLUtils.py b/WriteHDLUtils.py index 3eb3c2a..677eade 100644 --- a/WriteHDLUtils.py +++ b/WriteHDLUtils.py @@ -1192,7 +1192,7 @@ def parseProcFunction(proc_name, fname_def): return arg_types_list, arg_names_list, templ_pars_list def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars, - f_matchArgPortNames, first_of_type, extraports,delay,split=False): + f_matchArgPortNames, first_of_type, extraports,delay,split=0): #### # function name @@ -1397,17 +1397,17 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars, return str_ctrl_wire,module_str ################################ -def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, split = False): +def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, split = 0): if module.mtype == 'InputRouter': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_IR, matchArgPortNames_IR, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'VMRouter': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_VMR, matchArgPortNames_VMR, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'VMRouterCM': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_VMRCM, @@ -1417,7 +1417,7 @@ def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, s return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_TE, matchArgPortNames_TE, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'TrackletProcessor': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_TP, @@ -1427,51 +1427,51 @@ def writeModuleInstance(module, hls_src_dir, first_of_type, extraports, delay, s return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_TC, matchArgPortNames_TC, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'ProjectionRouter': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_PR, matchArgPortNames_PR, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'MatchEngine': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_ME, matchArgPortNames_ME, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'MatchCalculator': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_MC, matchArgPortNames_MC, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'MatchProcessor': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_MP, matchArgPortNames_MP, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'FitTrack': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_FT, matchArgPortNames_FT, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'TrackBuilder': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_TB, matchArgPortNames_TB, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'PurgeDuplicate': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_PD, matchArgPortNames_PD, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'ProjectionCalculator': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_PC, matchArgPortNames_PC, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) elif module.mtype == 'VMSMERouter': return writeModuleInst_generic(module, hls_src_dir, writeTemplatePars_VMSMER, matchArgPortNames_VMSMER, - first_of_type, extraports, delay) + first_of_type, extraports, delay, split) else: raise ValueError(module.mtype + " is unknown.") From c122146b6b5e4b93727314fa385fbcbe1ac5ea70 Mon Sep 17 00:00:00 2001 From: Jason Fan Date: Mon, 9 Sep 2024 12:40:16 -0400 Subject: [PATCH 22/22] address comment --- WriteVHDLSyntax.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 29581f5..5c05333 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -181,7 +181,7 @@ def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned string_mem += " read" + mem + " : entity work.FileReaderFIFO\n" string_mem += " generic map (\n" memtmp = mem.replace("twoS","2S") - string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_DL_39&\""+ memtmp + "\"&inputFileNameEnding,\n" + string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_"+mtypeB+"&\""+ memtmp + "\"&inputFileNameEnding,\n" string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n" string_mem += " FIFO_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n" string_mem += " DEBUG".ljust(str_len) + "=> true,\n"