From 431087a63da443d75750f44a9cffaec18d7735c4 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 19 Feb 2024 06:38:21 -0500 Subject: [PATCH 1/6] Converted to new unbinned memory. --- WriteVHDLSyntax.py | 64 +++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 35 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 2240545..040ff3e 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -461,8 +461,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += " signal "+mem+"_AV_dout : " wirelist += "t_"+mtypeB+"_ADATA;\n" else: - wirelist += " signal "+mem+"_enb : " - wirelist += "t_"+mtypeB+"_1b;\n" wirelist += " signal "+mem+"_V_readaddr : " wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_V_dout : " @@ -501,10 +499,11 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl # Write parameters parameterlist += " RAM_WIDTH => "+bitwidth+",\n" parameterlist += " NUM_PAGES => "+str(num_pages)+",\n" - parameterlist += " INIT_FILE => \"\",\n" - parameterlist += " INIT_HEX => true,\n" - parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n" - parameterlist += " NAME => \""+mem+"\",\n" + if memInfo.is_binned: + parameterlist += " INIT_FILE => \"\",\n" + parameterlist += " INIT_HEX => true,\n" + parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n" + parameterlist += " NAME => \""+mem+"\",\n" if delay > 0: delay_parameterlist +=" DELAY => " + str(delay) +",\n" #enable to use non-default delay value @@ -537,25 +536,19 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl #FIXME implement delay for disks # Write ports - portlist += " clka => clk,\n" + portlist += " clk => clk,\n" if delay > 0: - if memInfo.is_binned : - portlist += " wea => "+mem+"_wea_delay,\n" - portlist += " addra => "+mem+"_writeaddr_delay,\n" - portlist += " dina => "+mem+"_din_delay,\n" - else: - portlist += " wea => "+mem+"_wea_delay,\n" - portlist += " addra => "+mem+"_writeaddr_delay,\n" - portlist += " dina => "+mem+"_din_delay,\n" + portlist += " wea => "+mem+"_wea_delay,\n" + portlist += " addra => "+mem+"_writeaddr_delay,\n" + portlist += " dina => "+mem+"_din_delay,\n" + if not memInfo.is_binned: + portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out_0,\n" else: - if memInfo.is_binned : - portlist += " wea => "+mem+"_wea,\n" - portlist += " addra => "+mem+"_writeaddr,\n" - portlist += " dina => "+mem+"_din,\n" - else: - portlist += " wea => "+mem+"_wea,\n" - portlist += " addra => "+mem+"_writeaddr,\n" - portlist += " dina => "+mem+"_din,\n" + portlist += " wea => "+mem+"_wea,\n" + portlist += " addra => "+mem+"_writeaddr,\n" + portlist += " dina => "+mem+"_din,\n" + if not memInfo.is_binned: + portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out_0,\n" if delay > 0: delay_portlist_0 += " clk => clk,\n" delay_portlist_0 += " wea => "+mem+"_wea,\n" @@ -573,14 +566,12 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay_portlist += " dina_out => "+mem+"_din_delay,\n" - portlist += " clkb => clk,\n" portlist += " rstb => '0',\n" - portlist += " regceb => '1',\n" if not memInfo.is_binned : - portlist += " enb => "+mem+"_enb,\n" portlist += " addrb => "+mem+"_V_readaddr,\n" portlist += " doutb => "+mem+"_V_dout,\n" - portlist += " sync_nent => "+sync_signal+",\n" + if memInfo.is_binned: + portlist += " sync_nent => "+sync_signal+",\n" if memList[0].has_numEntries_out: if memList[0].is_binned: @@ -751,7 +742,8 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" else: - string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" + if not memInfo.is_binned: + string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" string_output_mems += " "+mem+"_V_dout : out t_"+mtypeB+"_DATA;\n" if memInfo.has_numEntries_out: @@ -957,8 +949,6 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += (" signal "+mem+"_AV_dout_mask").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n" else: - string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " - string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" string_ctrl_signals += (" signal "+mem+"_readaddr").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_ADDR").ljust(str_len2)+":= (others => '0');\n" string_ctrl_signals += (" signal "+mem+"_dout").ljust(str_len)+": " @@ -1053,7 +1043,6 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc for memMod in memList: mem = memMod.inst if split and ("AS" in mtypeB and "n1" in mem): - string_output += (" "+mem+"_enb").ljust(str_len) + "=> dummy,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> dummy_AS_36_addr,\n" string_output += (" "+mem+"_V_dout").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" @@ -1087,7 +1076,6 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" else: - string_output += (" "+mem+"_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" string_output += (" "+mem+"_V_dout").ljust(str_len) + "=> "+mem+"_dout,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> "+mem+"_AV_dout_nent,\n" @@ -1180,7 +1168,10 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned): string_mem += " CLK".ljust(str_len)+"=> CLK,\n" string_mem += " ADDR".ljust(str_len)+"=> "+mem+"_readaddr,\n" string_mem += " DATA".ljust(str_len)+"=> "+mem+"_dout,\n" - string_mem += " READ_EN".ljust(str_len)+"=> "+mem+"_enb,\n" + if is_binned: + string_mem += " READ_EN".ljust(str_len)+"=> "+mem+"_enb,\n" + else: + string_mem += " READ_EN".ljust(str_len)+"=> '1',\n" if "VMSME" not in mem: #FIXME string_mem += " NENT_ARR".ljust(str_len)+"=> "+mem+"_A" + ("A" if is_binned else "") + "V_dout_nent,\n" else: @@ -1365,8 +1356,11 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0): string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_AV_dout("+str(instance)+"),\n" else: string_mem_ports = "" - string_mem_ports += " "+argname+"_dataarray_data_V_ce"+str(portindex)+" => " - string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_enb,\n" + if mem.is_binned: + string_mem_ports += " "+argname+"_dataarray_data_V_ce"+str(portindex)+" => " + string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_enb,\n" + else: + string_mem_ports += " "+argname+"_dataarray_data_V_ce"+str(portindex)+" => open,\n" string_mem_ports += " "+argname+"_dataarray_data_V_address"+str(portindex)+" => " string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_V_readaddr,\n" string_mem_ports += " "+argname+"_dataarray_data_V_q"+str(portindex)+" => " From 6d6b4c8a04a2f1129f75e19d4e2313d13078bf02 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 19 Feb 2024 11:18:15 -0500 Subject: [PATCH 2/6] Added more instances of CreateStartSignal. --- WriteHDLUtils.py | 28 ++++++++++------- WriteVHDLSyntax.py | 77 ++++++++++++++++++++++++---------------------- 2 files changed, 57 insertions(+), 48 deletions(-) diff --git a/WriteHDLUtils.py b/WriteHDLUtils.py index aace892..0104599 100644 --- a/WriteHDLUtils.py +++ b/WriteHDLUtils.py @@ -1131,17 +1131,23 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars, assert(module.mtype in ['InputRouter', 'VMRouterCM', 'TrackletProcessor', 'MatchProcessor', 'FitTrack', 'TrackBuilder', 'PurgeDuplicate']) + if not hasattr(writeModuleInst_generic, "modules_with_ports_added"): + writeModuleInst_generic.modules_with_ports_added = set() + # Add internal BX wire and start registers str_ctrl_wire = "" str_ctrl_func = "" - if first_of_type and not module.is_last: - for mem in module.downstreams: - if mem.bxbitwidth != 1: continue - oneProcDownMem = mem - break - ctrl_wire_inst,ctrl_func_inst = writeStartSwitchAndInternalBX(module,oneProcDownMem,extraports,delay) - str_ctrl_wire += ctrl_wire_inst - str_ctrl_func += ctrl_func_inst + oneProcUpMem = None + for mem in module.upstreams: + if mem.bxbitwidth != 1: continue + if mem.upstreams[0] is None: continue + oneProcUpMem = mem + break + ports_added = (module.mtype in writeModuleInst_generic.modules_with_ports_added) + ctrl_wire_inst,ctrl_func_inst = writeStartSwitchAndInternalBX(module,oneProcUpMem,extraports or ports_added,delay) + str_ctrl_wire += ctrl_wire_inst + str_ctrl_func += ctrl_func_inst + writeModuleInst_generic.modules_with_ports_added.add(module.mtype) # Update here if the function name is not exactly the same as the module type @@ -1182,14 +1188,14 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars, for mem in module.upstreams: if mem.bxbitwidth != 1: continue if mem.is_initial: - string_bx_in += writeProcBXPort(module.mtype_short(),True,True,delay) + string_bx_in += writeProcBXPort(module.inst,module.mtype_short(),True) break else: - string_bx_in += writeProcBXPort(mem.upstreams[0].mtype_short(),True,False,delay) + string_bx_in += writeProcBXPort(module.inst,mem.upstreams[0].mtype_short(),True) break elif argtype == "BXType&" or argtype == "BXType &": # Could change this in the HLS instead if first_of_type: - string_bx_out += writeProcBXPort(module.mtype_short(),False,False,delay) # output bx + string_bx_out += writeProcBXPort(module.inst,module.mtype_short(),False) # output bx elif "table" in argname: # For TE innerPS = ("_L1" in module.inst and "_L2" in module.inst) \ or ("_L2" in module.inst and "_L3" in module.inst) \ diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 040ff3e..1cc4333 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -406,13 +406,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl interface = int(memInfo.is_final) - int(memInfo.is_initial) - if interface == 1: - assert memInfo.upstream_mtype_short != "" - sync_signal = memInfo.upstream_mtype_short+"_done" - else: - assert memInfo.downstream_mtype_short != "" - sync_signal = memInfo.downstream_mtype_short+"_start" - for memmod in memList: nmem = 0 @@ -425,6 +418,13 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl if "VMSME_D" in mem: disk="DISK" + if interface == 1: + assert memInfo.upstream_mtype_short != "" + sync_signal = memmod.upstreams[0].inst+"_done" + else: + assert memInfo.downstream_mtype_short != "" + sync_signal = memmod.downstreams[0].inst+"_start" + parameterlist = "" portlist = "" delay_parameterlist = "" @@ -542,13 +542,13 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " addra => "+mem+"_writeaddr_delay,\n" portlist += " dina => "+mem+"_din_delay,\n" if not memInfo.is_binned: - portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out_0,\n" + portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out,\n" else: portlist += " wea => "+mem+"_wea,\n" portlist += " addra => "+mem+"_writeaddr,\n" portlist += " dina => "+mem+"_din,\n" if not memInfo.is_binned: - portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out_0,\n" + portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out,\n" if delay > 0: delay_portlist_0 += " clk => clk,\n" delay_portlist_0 += " wea => "+mem+"_wea,\n" @@ -1240,31 +1240,40 @@ def writeLUTCombination(lut, argname, portlist, parameterlist): def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0): """ # Top-level: control (start/done) & Bx signals for use by given module - # Inputs: processing module & memory that is downstream of it. + # Inputs: processing module & memory that is upstream of it. """ - mtype = module.mtype_short() - mtype_down = mem.downstreams[0].mtype_short() - startsignal_parameter_list = "" + first_proc = (mem is None) + mtype = module.inst + mtype_up = None + + if first_proc: + mtype_up = module.mtype_short() + else: + mtype_up = mem.upstreams[0].mtype_short() + int_ctrl_wire = "" - if not extraports: - int_ctrl_wire += " signal "+mtype+"_done : std_logic := '0';\n" - int_ctrl_wire += " signal "+mtype+"_bx_out : std_logic_vector(2 downto 0);\n" - int_ctrl_wire += " signal "+mtype+"_bx_out_vld : std_logic;\n" - int_ctrl_wire += " signal "+mtype_down+"_start : std_logic := '0';\n" + if not first_proc and not extraports: + int_ctrl_wire += " signal "+mtype_up+"_done : std_logic := '0';\n" + int_ctrl_wire += " signal "+mtype_up+"_bx_out : std_logic_vector(2 downto 0);\n" + int_ctrl_wire += " signal "+mtype_up+"_bx_out_vld : std_logic;\n" + int_ctrl_wire += " signal "+mtype+"_bx_in : std_logic_vector(2 downto 0);\n" + int_ctrl_wire += " signal "+mtype+"_start : std_logic := '0';\n" int_ctrl_func = " LATCH_"+mtype+": entity work.CreateStartSignal\n" if delay > 0: - startsignal_parameter_list +=" DELAY => " + str(delay*2) +",\n" + startsignal_parameter_list = " DELAY => " + str(delay*2) +",\n" int_ctrl_func += " generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n )\n" int_ctrl_func += " port map (\n" int_ctrl_func += " clk => clk,\n" int_ctrl_func += " reset => reset,\n" - int_ctrl_func += " done => "+mtype+"_done,\n" - if delay > 0: - int_ctrl_wire += " signal "+mtype+"_bx_out_0 : std_logic_vector(2 downto 0);\n" - int_ctrl_func += " bx_out => "+mtype+"_bx_out_0,\n" - int_ctrl_func += " bx => "+mtype+"_bx_out,\n" - int_ctrl_func += " start => "+mtype_down+"_start\n" + if first_proc: + int_ctrl_func += " done => "+mtype_up+"_start,\n" + int_ctrl_func += " bx_out => "+mtype_up+"_bx_in,\n" + else: + int_ctrl_func += " done => "+mtype_up+"_done,\n" + int_ctrl_func += " bx_out => "+mtype_up+"_bx_out,\n" + int_ctrl_func += " bx => "+mtype+"_bx_in,\n" + int_ctrl_func += " start => "+mtype+"_start\n" int_ctrl_func += " );\n\n" return int_ctrl_wire,int_ctrl_func @@ -1276,7 +1285,7 @@ def writeProcControlSignalPorts(module,first_of_type): string_ctrl_ports = "" string_ctrl_ports += " ap_clk => clk,\n" string_ctrl_ports += " ap_rst => reset,\n" - string_ctrl_ports += " ap_start => "+module.mtype_short()+"_start,\n" + string_ctrl_ports += " ap_start => "+module.inst+"_start,\n" string_ctrl_ports += " ap_idle => open,\n" string_ctrl_ports += " ap_ready => open,\n" if first_of_type: @@ -1286,22 +1295,16 @@ def writeProcControlSignalPorts(module,first_of_type): return string_ctrl_ports -def writeProcBXPort(modName,isInput,isInitial,delay): +def writeProcBXPort(modName,shortModName,isInput): """ # Processing module port assignment: BX ports """ bx_str = "" - if isInput and isInitial: + if isInput: bx_str += " bx_V => "+modName+"_bx_in,\n" - elif isInput and not isInitial: - bx_str += " bx_V => "+modName+"_bx_out,\n" - elif not isInput: - if delay==0: - bx_str += " bx_o_V => "+modName+"_bx_out,\n" - bx_str += " bx_o_V_ap_vld => "+modName+"_bx_out_vld,\n" - else: - bx_str += " bx_o_V => "+modName+"_bx_out_0,\n" - bx_str += " bx_o_V_ap_vld => "+modName+"_bx_out_vld,\n" + else: + bx_str += " bx_o_V => "+shortModName+"_bx_out,\n" + bx_str += " bx_o_V_ap_vld => "+shortModName+"_bx_out_vld,\n" return bx_str def writeProcMemoryLHSPorts(argname,mem,split = False): From 792c41b832fb8c4f99aaf6d2b7e4b0e266c6b9da Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Mon, 19 Feb 2024 12:53:20 -0500 Subject: [PATCH 3/6] Use CreateStartSignal to make BX signals for unbinned memories. --- WriteVHDLSyntax.py | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 1cc4333..c8b56a8 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -428,11 +428,16 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl parameterlist = "" portlist = "" delay_parameterlist = "" + delay2_parameterlist = "" delay_portlist_0 = "" delay_portlist = "" + delay2_portlist = "" # Write wires if delay > 0: + if not memInfo.is_binned: + wirelist += " signal "+mem+"_bx : " + wirelist += "std_logic_vector(2 downto 0);\n" wirelist += " signal "+mem+"_wea_delay_0 : " wirelist += "t_"+mtypeB+"_1b;\n" wirelist += " signal "+mem+"_writeaddr_delay_0 : " @@ -505,6 +510,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n" parameterlist += " NAME => \""+mem+"\",\n" if delay > 0: + delay2_parameterlist +=" DELAY => " + str(delay*2) +",\n" delay_parameterlist +=" DELAY => " + str(delay) +",\n" #enable to use non-default delay value delay_parameterlist +=" NUM_PAGES => "+str(num_pages)+",\n" @@ -542,7 +548,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl portlist += " addra => "+mem+"_writeaddr_delay,\n" portlist += " dina => "+mem+"_din_delay,\n" if not memInfo.is_binned: - portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out,\n" + portlist += " bxa => "+mem+"_bx,\n" else: portlist += " wea => "+mem+"_wea,\n" portlist += " addra => "+mem+"_writeaddr,\n" @@ -550,6 +556,12 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl if not memInfo.is_binned: portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out,\n" if delay > 0: + delay2_portlist += " clk => clk,\n" + delay2_portlist += " reset => reset,\n" + delay2_portlist += " done => '0',\n" + delay2_portlist += " bx_out => "+memmod.upstreams[0].mtype_short()+"_bx_out,\n" + delay2_portlist += " bx => "+mem+"_bx,\n" + delay2_portlist += " start => open,\n" delay_portlist_0 += " clk => clk,\n" delay_portlist_0 += " wea => "+mem+"_wea,\n" delay_portlist_0 += " addra => "+mem+"_writeaddr,\n" @@ -630,6 +642,10 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl mem_str += " generic map (\n"+parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+portlist.rstrip(",\n")+"\n );\n\n" if delay > 0: + if not memInfo.is_binned: + mem_str += " "+mem+"_BX_GEN : entity work.CreateStartSignal\n" + mem_str += " generic map (\n"+delay2_parameterlist.rstrip(",\n")+"\n )\n" + mem_str += " port map (\n"+delay2_portlist.rstrip(",\n")+"\n );\n\n" mem_str += " "+mem+"_DELAY : entity work.tf_pipe_delay\n" mem_str += " generic map (\n"+delay_parameterlist.rstrip(",\n")+"\n )\n" mem_str += " port map (\n"+delay_portlist.rstrip(",\n")+"\n );\n\n" From 2bd2c95fa604a0041a5655839da4f2fba7cf1952 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Wed, 6 Mar 2024 05:48:27 -0500 Subject: [PATCH 4/6] Removed suffix. --- WriteVHDLSyntax.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index c8b56a8..877ced5 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -666,10 +666,7 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del string_ctrl_signals += " reset : in std_logic;\n" string_ctrl_signals += " "+initial_proc+"_start : in std_logic;\n" string_ctrl_signals += " "+initial_proc+"_bx_in : in std_logic_vector(2 downto 0);\n" - if delay > 0: - string_ctrl_signals += " "+final_proc_short+"_bx_out_0 : out std_logic_vector(2 downto 0);\n" - else: - string_ctrl_signals += " "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n" + string_ctrl_signals += " "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n" string_ctrl_signals += " "+final_proc_short+"_bx_out_vld : out std_logic;\n" string_ctrl_signals += " "+final_proc_short+"_done : out std_logic;\n" if final_proc_short == "FT": @@ -1030,7 +1027,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_fwblock_inst += " reset".ljust(str_len) + "=> reset,\n" string_fwblock_inst += (" " + initial_proc + "_start").ljust(str_len) + "=> " + initial_proc + "_start,\n" string_fwblock_inst += (" " + initial_proc + "_bx_in").ljust(str_len) + "=> " + initial_proc + "_bx_in,\n" - string_fwblock_inst += (" " + final_proc_short + "_bx_out_0").ljust(str_len) + "=> " + final_proc_short + "_bx_out,\n" + string_fwblock_inst += (" " + final_proc_short + "_bx_out").ljust(str_len) + "=> " + final_proc_short + "_bx_out,\n" string_fwblock_inst += (" " + final_proc_short + "_bx_out_vld").ljust(str_len) + "=> " + final_proc_short + "_bx_out_vld,\n" string_fwblock_inst += (" " + final_proc_short + "_done").ljust(str_len) + "=> " + final_proc_short + "_done,\n" if final_proc_short.startswith("FT"): From 973a31c23bff45dc691fa7a59c14a74b940ef8a0 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Tue, 21 May 2024 06:15:18 -0400 Subject: [PATCH 5/6] Revert "Converted to new unbinned memory." This reverts commit 431087a63da443d75750f44a9cffaec18d7735c4. --- WriteVHDLSyntax.py | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 877ced5..72bb33f 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -466,6 +466,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl wirelist += " signal "+mem+"_AV_dout : " wirelist += "t_"+mtypeB+"_ADATA;\n" else: + wirelist += " signal "+mem+"_enb : " + wirelist += "t_"+mtypeB+"_1b;\n" wirelist += " signal "+mem+"_V_readaddr : " wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n" wirelist += " signal "+mem+"_V_dout : " @@ -504,11 +506,10 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl # Write parameters parameterlist += " RAM_WIDTH => "+bitwidth+",\n" parameterlist += " NUM_PAGES => "+str(num_pages)+",\n" - if memInfo.is_binned: - parameterlist += " INIT_FILE => \"\",\n" - parameterlist += " INIT_HEX => true,\n" - parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n" - parameterlist += " NAME => \""+mem+"\",\n" + parameterlist += " INIT_FILE => \"\",\n" + parameterlist += " INIT_HEX => true,\n" + parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n" + parameterlist += " NAME => \""+mem+"\",\n" if delay > 0: delay2_parameterlist +=" DELAY => " + str(delay*2) +",\n" delay_parameterlist +=" DELAY => " + str(delay) +",\n" @@ -542,19 +543,15 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl #FIXME implement delay for disks # Write ports - portlist += " clk => clk,\n" + portlist += " clka => clk,\n" if delay > 0: portlist += " wea => "+mem+"_wea_delay,\n" portlist += " addra => "+mem+"_writeaddr_delay,\n" portlist += " dina => "+mem+"_din_delay,\n" - if not memInfo.is_binned: - portlist += " bxa => "+mem+"_bx,\n" else: portlist += " wea => "+mem+"_wea,\n" portlist += " addra => "+mem+"_writeaddr,\n" portlist += " dina => "+mem+"_din,\n" - if not memInfo.is_binned: - portlist += " bxa => "+memInfo.upstream_mtype_short+"_bx_out,\n" if delay > 0: delay2_portlist += " clk => clk,\n" delay2_portlist += " reset => reset,\n" @@ -578,12 +575,14 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl delay_portlist += " dina_out => "+mem+"_din_delay,\n" + portlist += " clkb => clk,\n" portlist += " rstb => '0',\n" + portlist += " regceb => '1',\n" if not memInfo.is_binned : + portlist += " enb => "+mem+"_enb,\n" portlist += " addrb => "+mem+"_V_readaddr,\n" portlist += " doutb => "+mem+"_V_dout,\n" - if memInfo.is_binned: - portlist += " sync_nent => "+sync_signal+",\n" + portlist += " sync_nent => "+sync_signal+",\n" if memList[0].has_numEntries_out: if memList[0].is_binned: @@ -755,8 +754,7 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict): string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n" string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n" else: - if not memInfo.is_binned: - string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" + string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n" string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n" string_output_mems += " "+mem+"_V_dout : out t_"+mtypeB+"_DATA;\n" if memInfo.has_numEntries_out: @@ -962,6 +960,8 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi string_ctrl_signals += (" signal "+mem+"_AV_dout_mask").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n" else: + string_ctrl_signals += (" signal "+mem+"_enb").ljust(str_len)+": " + string_ctrl_signals += ("t_"+mtypeB+"_1b").ljust(str_len2)+":= '0';\n" string_ctrl_signals += (" signal "+mem+"_readaddr").ljust(str_len)+": " string_ctrl_signals += ("t_"+mtypeB+"_ADDR").ljust(str_len2)+":= (others => '0');\n" string_ctrl_signals += (" signal "+mem+"_dout").ljust(str_len)+": " @@ -1056,6 +1056,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc for memMod in memList: mem = memMod.inst if split and ("AS" in mtypeB and "n1" in mem): + string_output += (" "+mem+"_enb").ljust(str_len) + "=> dummy,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> dummy_AS_36_addr,\n" string_output += (" "+mem+"_V_dout").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" @@ -1089,6 +1090,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n" else: + string_output += (" "+mem+"_enb").ljust(str_len) + "=> "+mem+"_enb,\n" string_output += (" "+mem+"_V_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n" string_output += (" "+mem+"_V_dout").ljust(str_len) + "=> "+mem+"_dout,\n" string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> "+mem+"_AV_dout_nent,\n" @@ -1181,10 +1183,7 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned): string_mem += " CLK".ljust(str_len)+"=> CLK,\n" string_mem += " ADDR".ljust(str_len)+"=> "+mem+"_readaddr,\n" string_mem += " DATA".ljust(str_len)+"=> "+mem+"_dout,\n" - if is_binned: - string_mem += " READ_EN".ljust(str_len)+"=> "+mem+"_enb,\n" - else: - string_mem += " READ_EN".ljust(str_len)+"=> '1',\n" + string_mem += " READ_EN".ljust(str_len)+"=> "+mem+"_enb,\n" if "VMSME" not in mem: #FIXME string_mem += " NENT_ARR".ljust(str_len)+"=> "+mem+"_A" + ("A" if is_binned else "") + "V_dout_nent,\n" else: @@ -1372,11 +1371,8 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0): string_mem_ports += mem.mtype_short() + "_" + mem.var()+"_AV_dout("+str(instance)+"),\n" else: string_mem_ports = "" - if mem.is_binned: - string_mem_ports += " "+argname+"_dataarray_data_V_ce"+str(portindex)+" => " - string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_enb,\n" - else: - string_mem_ports += " "+argname+"_dataarray_data_V_ce"+str(portindex)+" => open,\n" + string_mem_ports += " "+argname+"_dataarray_data_V_ce"+str(portindex)+" => " + string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_enb,\n" string_mem_ports += " "+argname+"_dataarray_data_V_address"+str(portindex)+" => " string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_V_readaddr,\n" string_mem_ports += " "+argname+"_dataarray_data_V_q"+str(portindex)+" => " From 1bfa947bc26fa16ea6e8d3ea5dda875202fdeb40 Mon Sep 17 00:00:00 2001 From: Andrew Hart Date: Tue, 21 May 2024 06:21:57 -0400 Subject: [PATCH 6/6] Define default value of depth. --- WriteVHDLSyntax.py | 1 + 1 file changed, 1 insertion(+) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 72bb33f..6a55c1e 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -1420,6 +1420,7 @@ def writeLUTPorts(argname,lut): def writeLUTParameters(argname, lut, innerPS, outerPS): parameterlist = "" + depth = 0 width = 0 if "in" in argname: width = 1