diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile index 60f77af59f1..0e43e045754 100644 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile +++ b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile @@ -4,7 +4,7 @@ input_file = mem/in.txt proj_path = ../../../../proj hls_script_path = ../../script -all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion +all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input $(core_dir): @mkdir cgn mem @@ -32,9 +32,6 @@ add_common_files: hdl_add_files: $(core_file) cd hdl; ln -s ../../../hdl/*.vhd . -lut_inclusion: - @python3 scripts/lut_copy.py - $(input_file): $(core_dir) @python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsCMBarrel/InputStubs -o $(input_file) @@ -53,4 +50,4 @@ sim: $(input_file) $(core_file) $(core_dir) @cd $(hls_script_path); vivado -mode batch -source runSim.tcl @python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt -.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input lut_inclusion core_patch +.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl index bc2b45bff58..b6f27fa0f2d 100644 --- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl +++ b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl @@ -1,16 +1,11 @@ set_property SOURCE_SET sources_1 [get_filesets sim_1] add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt -set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl ]] -append lut_script "/pre_msim.tcl" -add_files -fileset utils_1 -norecurse $lut_script -#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1] -#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt -set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]" -eval ${pre_path} # Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. set_property source_mgmt_mode None [current_project] set_property top top [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] +set_property target_language VHDL [current_project] +set_property simulator_language VHDL [current_project] # Re-enabling previously disabled source management mode. set_property source_mgmt_mode All [current_project] diff --git a/IntegrationTests/DualFPGA/firmware/Makefile b/IntegrationTests/DualFPGA/firmware/Makefile new file mode 100644 index 00000000000..98cbee6dba1 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/Makefile @@ -0,0 +1,65 @@ +core_file_fpga1 = scripts/xciMaker_fpga1 +core_file_fpga2 = scripts/xciMaker_fpga2 +core_dir = cgn +input_file_fpga1 = mem/in_fpga1.txt +input_file_fpga2 = mem/in_fpga2.txt +fpga1_hls_script_path = ../../CombinedConfig_FPGA1/script +fpga2_hls_script_path = ../../CombinedConfig_FPGA2/script + +all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2 + +fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1 + +fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2 + +$(core_dir): + @mkdir cgn mem + @mkdir cgn/f1 + @mkdir cgn/f2 + @cd mem; ln -s ../../../../emData/LUTsSplit LUTs + @cd mem; ln -s ../../../../emData/MemPrintsSplit MemPrintsSplit + @cd hdl; ln -s ../../../common common + +$(core_file_fpga1): $(core_dir) + make -C $(fpga1_hls_script_path) -j 24 Work + @python3 scripts/include_cores.py -s $(fpga1_hls_script_path) -o $(core_file_fpga1) -f f1 + +$(core_file_fpga2): $(core_dir) + make -C $(fpga2_hls_script_path) -j 24 Work + @python3 scripts/include_cores.py -s $(fpga2_hls_script_path) -o $(core_file_fpga2) -f f2 + +kfin_adj: + @python3 scripts/kf_link_mod.py + +xciCreation_fpga1: $(core_file_fpga1) + make -f $(core_file_fpga1) -j 8 all + +xciCreation_fpga2: $(core_file_fpga2) + make -f $(core_file_fpga2) -j 8 all + +add_common_files: + @if [ ! -d ucf ]; then mkdir ucf; fi + @cd ucf; ln -s ../../../common/ucf/*.tcl . + @cd scripts; ln -s ../../../common/script/emp/* . + +hdl_add_files_fpga1: $(core_file) + cd hdl; ln -s ../../../CombinedConfig_FPGA1/hdl/SectorProcessor.vhd SectorProcessor_f1.vhd + cd hdl; ln -s ../../../CombinedConfig_FPGA1/hdl/memUtil_pkg.vhd memUtil_pkg_f1.vhd + +hdl_add_files_fpga2: $(core_file) + cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/SectorProcessor.vhd SectorProcessor_f2.vhd + cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/memUtil_pkg.vhd memUtil_pkg_f2.vhd + +$(input_file_fpga1): $(core_dir) + @python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsSplit/InputStubs -o $(input_file_fpga1) + +$(input_file_fpga2): $(core_dir) + @python3 scripts/convert_emData2EMP_Link_FPGA2.py -d mem/MemPrintsSplit/ -o $(input_file_fpga2) + +apollo_input_fpga1: $(input_file_fpga1) + @python3 scripts/split_emp_input.py -i $(input_file_fpga1) -o mem/in_fpga1_ + +apollo_input_fpga2: $(input_file_fpga2) + @python3 scripts/split_emp_input.py -i $(input_file_fpga2) -o mem/in_fpga2_ + +.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2 diff --git a/IntegrationTests/DualFPGA/firmware/cfg/apollo.dep b/IntegrationTests/DualFPGA/firmware/cfg/apollo.dep new file mode 100644 index 00000000000..9b584fa4ed1 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/apollo.dep @@ -0,0 +1,15 @@ +# common for both FPGAs + + +src -c emp-fwk:components/datapath emp_data_types.vhd +src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd + +include -c ipbus-firmware:components/ipbus_slaves ipbus_syncreg_v.dep ipbus_ctrlreg_v.dep ipbus_reg_v.dep ipbus_freq_ctr.dep + +#src ../constrs/floorplan_emp + +include -c emp-fwk:components/links/slink slink.dep + +addrtab -c emp-fwk:components/payload emp_payload.xml + + diff --git a/IntegrationTests/DualFPGA/firmware/cfg/apollo_f1.dep b/IntegrationTests/DualFPGA/firmware/cfg/apollo_f1.dep new file mode 100644 index 00000000000..e148de02ae2 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/apollo_f1.dep @@ -0,0 +1,8 @@ + +include payload_f1.dep +src emp_project_decl_f1.vhd +setup ../ucf/ip.tcl + +include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep + +include apollo.dep diff --git a/IntegrationTests/DualFPGA/firmware/cfg/apollo_f2.dep b/IntegrationTests/DualFPGA/firmware/cfg/apollo_f2.dep new file mode 100644 index 00000000000..8b350763918 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/apollo_f2.dep @@ -0,0 +1,8 @@ + +include payload_f2.dep +src emp_project_decl_f2.vhd +setup ../ucf/ip.tcl + +include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p2_2.dep + +include apollo.dep diff --git a/IntegrationTests/DualFPGA/firmware/cfg/payload_f1.dep b/IntegrationTests/DualFPGA/firmware/cfg/payload_f1.dep new file mode 100644 index 00000000000..84d8f7b3d92 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/payload_f1.dep @@ -0,0 +1,29 @@ +#Payload and top level +src payload_f1.vhd +src tf1_wrapper.vhd +src linktosecproc.vhd +src secproc1tolink.vhd +src --vhdl2008 SectorProcessor_f1.vhd +#src common/hdl/emp/pkgs/tf_interface_pkg.vhd +src memUtil_pkg_f1.vhd +src memUtil_aux_pkg_f1.vhd +src common/hdl/emp/pkgs/GCU_utils.vhd +src conv_pkg_f1.vhd +include -c firmware-hls:KalmanFilter/common components.dep + +#Track Builder dependencies +src common/hdl/CreateStartSignal.vhd +#src --vhdl2008 common/hdl/tf_lut.vhd +src --vhdl2008 common/hdl/tf_mem_bin.vhd +src --vhdl2008 common/hdl/tf_mem_format.vhd +src --vhdl2008 common/hdl/tf_mem.vhd +src --vhdl2008 common/hdl/tf_merge_streamer.vhd +src common/hdl/tf_pkg.vhd +src --vhdl2008 common/hdl/tf_pipe_delay.vhd + +################ +# Include Cores +################ +iprepo * +src ../cgn/f1/*/*/*.xci + diff --git a/IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep b/IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep new file mode 100644 index 00000000000..2f1f21ed7ca --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep @@ -0,0 +1,40 @@ +src memUtil_pkg_f2.vhd +src memUtil_aux_pkg_f2.vhd +src payload_f2.vhd +src linktosecproc2.vhd +src sp2_mem_writer.vhd +src tf2_wrapper.vhd +src --vhdl2008 SectorProcessor_f2.vhd +src tf_to_kf.vhd +src kf_wrapper.vhd +src common/hdl/emp/pkgs/tf_interface_pkg.vhd +src kf_input_merger.vhd + +# KF +include -c firmware-hls:KalmanFilter/kfin components.dep +include -c firmware-hls:KalmanFilter/kf components.dep +include -c firmware-hls:KalmanFilter/kfout components.dep +include -c firmware-hls:KalmanFilter/tq components.dep +include -c firmware-hls:KalmanFilter/common components.dep + +#Tracklet dependencies +src common/hdl/CreateStartSignal.vhd +#src --vhdl2008 common/hdl/tf_lut.vhd +src --vhdl2008 common/hdl/tf_mem_bin.vhd +src --vhdl2008 common/hdl/tf_mem_format.vhd +src --vhdl2008 common/hdl/tf_mem.vhd +src --vhdl2008 common/hdl/tf_mem_tproj.vhd +src --vhdl2008 common/hdl/tf_mem_tpar.vhd +src --vhdl2008 common/hdl/mem_reader.vhd +src common/hdl/tf_pkg.vhd +src --vhdl2008 common/hdl/tf_pipe_delay.vhd + +#Floorplan +src ../ucf/floorplan_f2.tcl + +################ +# Include Cores +################ +iprepo * +src ../cgn/f2/*/*/*.xci + diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep new file mode 100644 index 00000000000..f264ced65d4 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep @@ -0,0 +1,14 @@ +#don't include cm_v2_p1_2 since without decoder, it will have unresolved tcds2 dependencies +@fpga_position = "1" +@fpga_speed_grade = "-2-e" + +include payload_f1.dep +setup ../ucf/vsim_f1.tcl + +include -c emp-fwk:boards/testbench top.dep + +src tb_decl_f1.vhd +src emp_project_decl_f1.vhd +src -c emp-fwk:components/links/slink emp_slink_types.vhd + +include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep new file mode 100644 index 00000000000..46f6cc74a58 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep @@ -0,0 +1,14 @@ +#don't include cm_v2_p1_2 since without decoder, it will have unresolved tcds2 dependencies +@fpga_position = "2" +@fpga_speed_grade = "-2-e" + +include payload_f2.dep +setup ../ucf/vsim_f2.tcl + +include -c emp-fwk:boards/testbench top.dep + +src tb_decl_f2.vhd +src emp_project_decl_f2.vhd +src -c emp-fwk:components/links/slink emp_slink_types.vhd + +include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep diff --git a/IntegrationTests/DualFPGA/firmware/hdl/conv_pkg_f1.vhd b/IntegrationTests/DualFPGA/firmware/hdl/conv_pkg_f1.vhd new file mode 100644 index 00000000000..a39bbb608b1 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/conv_pkg_f1.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; + +use work.emp_data_types.all; +use work.hybrid_data_types.all; + +package conv_pkg_f1 is + + function conv_single (l : ldata) + return t_packet; + +end package conv_pkg_f1; + +package body conv_pkg_f1 is + + function conv_single(l : ldata) return t_packet is + variable s : t_packet; + begin + s.valid := l(68).valid; + s.start_of_orbit := l(68).start_of_orbit; + s.start := l(68).start; + s.last := l(68).last; + return s; + end; + +end package body conv_pkg_f1; + + + + diff --git a/IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f1.vhd b/IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f1.vhd new file mode 100644 index 00000000000..e668189a92c --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f1.vhd @@ -0,0 +1,71 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +use work.emp_framework_decl.all; +use work.emp_device_types.all; +use work.emp_slink_types.all; + +package emp_project_decl is + + constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"12345678"; + + -- Latency buffer size + constant LB_ADDR_WIDTH : integer := 10; + + -- Clock setup + constant CLOCK_COMMON_RATIO : integer := 36; + constant CLOCK_RATIO : integer := 6; + constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz + + -- Readdjust if latency changes for FPGA1 algorithm + constant PAYLOAD_LATENCY : integer := 140; + + -- F1 transmits to F2 on inter-fpga links + constant REGION_CONF : region_conf_array_t := ( + 0 => kDummyRegion, -- service c2c + 1 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 2 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 3 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 4 => kDummyRegion, -- not routed + 5 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 6 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 7 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 8 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 9 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 10 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 11 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 12 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 13 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 14 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga + 15 => kDummyRegion, -- not routed +------cross +----- all MGTs instantiated bidirectionally for now + 16 => kDummyRegion, -- not routed + 17 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 18 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 19 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 20 => kDummyRegion, -- not routed + 21 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 22 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 23 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 24 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 25 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 26 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 27 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 28 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 29 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 30 => (gty25, buf, no_fmt, buf, gty25), -- firefly + 31 => kDummyRegion, -- service tcds + + others => kDummyRegion + ); + + -- Specify the slink quad using the corresponding region conf ID + -- Specify slink channels to enable using the channel mask + constant SLINK_CONF : slink_conf_array_t := ( + others => kNoSlink + ); + + +end emp_project_decl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f2.vhd b/IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f2.vhd new file mode 100644 index 00000000000..28ff3ec8bf9 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f2.vhd @@ -0,0 +1,71 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +use work.emp_framework_decl.all; +use work.emp_device_types.all; +use work.emp_slink_types.all; + +package emp_project_decl is + + constant PAYLOAD_REV : std_logic_vector(31 downto 0) := X"12345678"; + + -- Latency buffer size + constant LB_ADDR_WIDTH : integer := 10; + + -- Clock setup + constant CLOCK_COMMON_RATIO : integer := 36; + constant CLOCK_RATIO : integer := 6; + constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz + + -- Only used by nullalgo + constant PAYLOAD_LATENCY : integer := 891; --was 823 + + -- F2 receives from F1 on inter-fpga links + constant REGION_CONF : region_conf_array_t := ( + 0 => kDummyRegion, -- service c2c + 1 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 2 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 3 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 4 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 5 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 6 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 7 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 8 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 9 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 10 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 11 => kDummyRegion, -- not routed + 12 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 13 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 14 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga + 15 => kDummyRegion, -- not routed +------cross +----- all MGTs instantiated bidirectionally for now + 16 => kDummyRegion, -- not routed + 17 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 18 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 19 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 20 => kDummyRegion, -- not routed + 21 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 22 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 23 => (no_mgt, no_buf, no_fmt, buf, gty25), -- firefly + 24 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 25 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 26 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 27 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 28 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 29 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 30 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly + 31 => kDummyRegion, -- service tcds + + others => kDummyRegion + ); + + -- Specify the slink quad using the corresponding region conf ID + -- Specify slink channels to enable using the channel mask + constant SLINK_CONF : slink_conf_array_t := ( + others => kNoSlink + ); + + +end emp_project_decl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/kf_input_merger.vhd b/IntegrationTests/DualFPGA/firmware/hdl/kf_input_merger.vhd new file mode 100644 index 00000000000..499e24ff111 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/kf_input_merger.vhd @@ -0,0 +1,303 @@ +--=========================================================================== +--! @file kf_input_merger.vhd +--! @brief Temporary module to merge input to KF until DR is ready +--! @author Michael Oshiro +--! @date 2024-05-14 +--! @version v.1.0 +--=========================================================================== + + --TODO: move some of this kludge to separate files + +--BEGIN Common Types + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.tf_interface_pkg.all; +use work.hybrid_data_types.all; +use work.hybrid_data_formats.all; +use work.hybrid_config.all; + +package KfMergeTypes is + constant width_tracktb : natural := (2 + widthTBseedType + widthTBinv2R + + widthTBphi0 + widthTBz0 + widthTBcot); + constant width_stubtb : natural := (2 + widthTBtrackId + widthTBstubId + + widthTBr + widthTBphi + widthTBz); + constant width_channeltb : natural := (width_tracktb + (width_stubtb * maxNumProjectionLayers)); + constant width_stubstb : natural := width_stubtb * maxNumProjectionLayers; +end KfMergeTypes; + +--END Common Types + +--BEGIN RAM + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.tf_interface_pkg.all; +use work.hybrid_data_types.all; +use work.hybrid_data_formats.all; +use work.hybrid_config.all; + +use work.KfMergeTypes.all; + + +entity kf_merge_ram is + generic ( + depth : natural := 54 + ); + port ( + clk : in std_logic; + rst : in std_logic; + din : in std_logic_vector(width_channeltb-1 downto 0); + write_enable : in boolean; + read_enable : in boolean; + empty : out boolean; + dout : out std_logic_vector(width_channeltb-1 downto 0) + ); +end entity kf_merge_ram; + +architecture rtl of kf_merge_ram is + + type t_ram is array(0 to depth-1) of std_logic_vector(width_channeltb-1 downto 0); + + signal ram : t_ram := (others => (others => '0' )); + attribute ram_style : string; + attribute ram_style of ram : signal is "block"; + signal write_address : integer range 0 to depth-1; + signal read_address : integer range 0 to depth-1; + signal full : boolean; + +begin + + process_ramwrite : process (clk) is + begin + if (rising_edge(clk)) then + + --assign addresses and ram + if (rst = '1') then + write_address <= 0; + read_address <= 0; + elsif (write_enable and (not read_enable) and (not full)) then + ram(write_address) <= din; + write_address <= write_address + 1; + read_address <= write_address; + elsif (read_enable and not write_enable) then + if (write_address /= 0) then + write_address <= write_address - 1; + end if; + if (read_address /= 0) then + read_address <= read_address - 1; + end if; + end if; + + --assign dout + if (write_enable and read_enable) then + dout <= din; + else + dout <= ram(read_address); + end if; + + end if; --rising_edge(clk) + end process; + + empty <= true when write_address = 0 else false; + full <= true when write_address = (depth-1) else false; + +end architecture rtl; + +--END RAM + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.tf_interface_pkg.all; +use work.hybrid_data_types.all; +use work.hybrid_data_formats.all; +use work.hybrid_config.all; + +use work.KfMergeTypes.all; + +--BEGIN WRAPPER + +entity kf_input_merger is + port ( + clk : in std_logic; + din : in t_channlesTB(numTW_104 - 1 downto 0); + dout : out t_channlesTB(numNodesKF - 1 downto 0) + ); +end entity kf_input_merger; + +architecture rtl of kf_input_merger is + + constant loc_cot : natural := width_stubstb; + constant loc_z0 : natural := width_stubstb+widthTBcot; + constant loc_phi0 : natural := width_stubstb+widthTBcot+widthTBz0; + constant loc_inv2r : natural := width_stubstb+widthTBcot+widthTBz0+widthTBphi0; + constant loc_seedtype : natural := width_stubstb+widthTBcot+widthTBz0+widthTBphi0+widthTBinv2R; + constant loc_valid : natural := width_stubstb+widthTBcot+widthTBz0+widthTBphi0+widthTBinv2R+widthTBseedType; + constant loc_reset : natural := width_stubstb+widthTBcot+widthTBz0+widthTBphi0+widthTBinv2R+widthTBseedType+1; + + constant loc_stub_phi : natural := widthTBz; + constant loc_stub_r : natural := widthTBz+widthTBphi; + constant loc_stub_stubid : natural := widthTBz+widthTBphi+widthTBr; + constant loc_stub_trackid : natural := widthTBz+widthTBphi+widthTBr+widthTBstubId; + constant loc_stub_valid : natural := widthTBz+widthTBphi+widthTBr+widthTBstubId+widthTBtrackId; + constant loc_stub_reset : natural := widthTBz+widthTBphi+widthTBr+widthTBstubId+widthTBtrackId+1; + + function tchanneltb_to_stdlogicvector (tb_data : t_channelTB) return std_logic_vector is + variable ret : std_logic_vector(width_channeltb-1 downto 0) := (others => '0'); + begin + ret(loc_reset) := tb_data.track.reset; + ret(loc_valid) := tb_data.track.valid; + ret(loc_valid-1 downto loc_seedtype) := tb_data.track.seedType; + ret(loc_seedtype-1 downto loc_inv2r) := tb_data.track.inv2R; + ret(loc_inv2r-1 downto loc_phi0) := tb_data.track.phi0; + ret(loc_phi0-1 downto loc_z0) := tb_data.track.z0; + ret(loc_z0-1 downto loc_cot) := tb_data.track.cot; + for istub in 0 to maxNumProjectionLayers-1 loop + ret(loc_stub_reset+(istub*width_stubtb)) := tb_data.stubs(istub).reset; + ret(loc_stub_valid+(istub*width_stubtb)) := tb_data.stubs(istub).valid; + ret(loc_stub_valid-1+istub*width_stubtb downto loc_stub_trackid+istub*width_stubtb) := tb_data.stubs(istub).trackId; + ret(loc_stub_trackid-1+istub*width_stubtb downto loc_stub_stubid+istub*width_stubtb) := tb_data.stubs(istub).stubId; + ret(loc_stub_stubid-1+istub*width_stubtb downto loc_stub_r+istub*width_stubtb) := tb_data.stubs(istub).r; + ret(loc_stub_r-1+istub*width_stubtb downto loc_stub_phi+istub*width_stubtb) := tb_data.stubs(istub).phi; + ret(loc_stub_phi-1+istub*width_stubtb downto istub*width_stubtb) := tb_data.stubs(istub).z; + end loop; + return ret; + end function; + + function stdlogicvector_to_tchanneltb (ram_data : std_logic_vector) return t_channelTB is + variable ret : t_channelTB; + begin + ret.track.reset := ram_data(loc_reset); + ret.track.valid := ram_data(loc_valid); + ret.track.seedType := ram_data(loc_valid-1 downto loc_seedtype); + ret.track.inv2R := ram_data(loc_seedtype-1 downto loc_inv2r); + ret.track.phi0 := ram_data(loc_inv2r-1 downto loc_phi0); + ret.track.z0 := ram_data(loc_phi0-1 downto loc_z0); + ret.track.cot := ram_data(loc_z0-1 downto loc_cot); + for istub in 0 to maxNumProjectionLayers-1 loop + ret.stubs(istub).reset := ram_data(loc_stub_reset+(istub*width_stubtb)); + ret.stubs(istub).valid := ram_data(loc_stub_valid+(istub*width_stubtb)); + ret.stubs(istub).trackId := ram_data(loc_stub_valid-1+istub*width_stubtb downto loc_stub_trackid+istub*width_stubtb); + ret.stubs(istub).stubId := ram_data(loc_stub_trackid-1+istub*width_stubtb downto loc_stub_stubid+istub*width_stubtb); + ret.stubs(istub).r := ram_data(loc_stub_stubid-1+istub*width_stubtb downto loc_stub_r+istub*width_stubtb); + ret.stubs(istub).phi := ram_data(loc_stub_r-1+istub*width_stubtb downto loc_stub_phi+istub*width_stubtb); + ret.stubs(istub).z := ram_data(loc_stub_phi-1+istub*width_stubtb downto istub*width_stubtb); + end loop; + return ret; + end function; + + --these RAMs are really wide (~500 bits) so want as little depth as possible + constant ram_depth : integer := 54; + subtype t_address is integer range 0 to ram_depth-1; + type t_arr_address is array(0 to din'length-1) of t_address; + type t_arr_bool is array(0 to din'length-1) of boolean; + type t_arr_ramdata is array(0 to din'length-1) of std_logic_vector(width_channeltb-1 downto 0); + + signal write_enable : t_arr_bool; + signal read_enable : t_arr_bool; + signal ram_empty : t_arr_bool; + + --signal write_addr : t_arr_address; + --signal read_addr : t_arr_address; + signal ram_in : t_channlesTB(numTW_104 - 1 downto 0); + signal ram_out_raw : t_arr_ramdata; + signal ram_out : t_channlesTB(numTW_104 - 1 downto 0); + + signal bx_change : std_logic; + + --this defines merging scheme + --currently merge first 4 seeds (L1L2, L2L3, L3L4, L5L6) + --and second 4 seeds (D1D2, D3D4, L1D1, L2D1) + type t_kf_mergesubscheme is array(0 to 3) of integer range 0 to 7; + type t_kf_mergescheme is array(0 to 1) of t_kf_mergesubscheme; + constant seed_merge : t_kf_mergescheme := ((0,1,2,3), + (4,5,6,7)); + +begin + + bx_change <= din(0).track.reset; + + -- generate RAMs + generate_ram : for iseedtype in 0 to (din'length-1) generate + ram_1 : entity work.kf_merge_ram + generic map( + depth => ram_depth + ) + port map( + clk => clk, + rst => bx_change, + din => tchanneltb_to_stdlogicvector(ram_in(iseedtype)), + write_enable => write_enable(iseedtype), + read_enable => read_enable(iseedtype), + empty => ram_empty(iseedtype), + dout => ram_out_raw(iseedtype) + ); + ram_out(iseedtype) <= stdlogicvector_to_tchanneltb(ram_out_raw(iseedtype)); + end generate generate_ram; + + -- handle writing to RAMs + process_ramwrite : process (clk) is + begin + if (rising_edge(clk)) then + for iseedtype in 0 to (din'length-1) loop + if (din(iseedtype).track.valid = '1' or + (din(iseedtype).track.reset = '1' and (iseedtype = 0 or iseedtype = 4))) then + ram_in(iseedtype) <= din(iseedtype); + write_enable(iseedtype) <= true; + else + write_enable(iseedtype) <= false; + end if; + end loop; + end if; + end process; + + -- handle reading from RAMs + process_ramread : process (clk) is + begin + if (rising_edge(clk)) then + for ikfchannel in 0 to (numNodesKF-1) loop + if not ram_empty(seed_merge(ikfchannel)(0)) then + dout(ikfchannel) <= ram_out(seed_merge(ikfchannel)(0)); + read_enable(seed_merge(ikfchannel)(0)) <= true; + read_enable(seed_merge(ikfchannel)(1)) <= false; + read_enable(seed_merge(ikfchannel)(2)) <= false; + read_enable(seed_merge(ikfchannel)(3)) <= false; + elsif not ram_empty(seed_merge(ikfchannel)(1)) then + dout(ikfchannel) <= ram_out(seed_merge(ikfchannel)(1)); + read_enable(seed_merge(ikfchannel)(0)) <= false; + read_enable(seed_merge(ikfchannel)(1)) <= true; + read_enable(seed_merge(ikfchannel)(2)) <= false; + read_enable(seed_merge(ikfchannel)(3)) <= false; + elsif not ram_empty(seed_merge(ikfchannel)(2)) then + dout(ikfchannel) <= ram_out(seed_merge(ikfchannel)(2)); + read_enable(seed_merge(ikfchannel)(0)) <= false; + read_enable(seed_merge(ikfchannel)(1)) <= false; + read_enable(seed_merge(ikfchannel)(2)) <= true; + read_enable(seed_merge(ikfchannel)(3)) <= false; + elsif not ram_empty(seed_merge(ikfchannel)(3)) then + dout(ikfchannel) <= ram_out(seed_merge(ikfchannel)(3)); + read_enable(seed_merge(ikfchannel)(0)) <= false; + read_enable(seed_merge(ikfchannel)(1)) <= false; + read_enable(seed_merge(ikfchannel)(2)) <= false; + read_enable(seed_merge(ikfchannel)(3)) <= true; + else + dout(ikfchannel) <= nulll; + read_enable(seed_merge(ikfchannel)(0)) <= false; + read_enable(seed_merge(ikfchannel)(1)) <= false; + read_enable(seed_merge(ikfchannel)(2)) <= false; + read_enable(seed_merge(ikfchannel)(3)) <= false; + end if; + end loop; + end if; + end process; + +end architecture rtl; + +--END WRAPPER + diff --git a/IntegrationTests/DualFPGA/firmware/hdl/kf_wrapper.vhd b/IntegrationTests/DualFPGA/firmware/hdl/kf_wrapper.vhd new file mode 100644 index 00000000000..75781682c82 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/kf_wrapper.vhd @@ -0,0 +1,64 @@ +------------------------------------------------------------------------------- +-- Title : kf wrapper +-- Project : +------------------------------------------------------------------------------- +-- File : kf_top.vhd +-- Author : Filippo Marini +-- Company : University of Colorado Boulder +-- Created : 2022-11-04 +-- Last update: 2023-02-24 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2022 University of Colorado Boulder +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2022-11-04 1.0 fmarini Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +use work.hybrid_data_formats.all; +use work.hybrid_config.all; +use work.hybrid_data_types.all; + +entity kf_wrapper is + port ( + clk_i : in std_logic; + kfin_i : in t_channlesTB(numNodesKF - 1 downto 0); + kfout_o : out t_frames(numLinksTFP - 1 downto 0) + ); +end entity kf_wrapper; + +architecture rtl of kf_wrapper is + + signal s_kfin_dout : t_channelsZHT(numNodesKF - 1 downto 0); + signal s_kf_dout : t_channelsKF(numNodesKF - 1 downto 0); + +begin -- architecture rtl + + kfin_top_1 : entity work.kfin_top + port map ( + clk => clk_i, + kfin_din => kfin_i, + kfin_dout => s_kfin_dout + ); + + kf_top_1 : entity work.kf_top + port map ( + clk => clk_i, + kf_din => s_kfin_dout, + kf_dout => s_kf_dout + ); + + kfout_top_1 : entity work.kfout_top + port map ( + clk => clk_i, + kfout_din => s_kf_dout, + kfout_dout => kfout_o + ); + +end architecture rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/linktosecproc.vhd b/IntegrationTests/DualFPGA/firmware/hdl/linktosecproc.vhd new file mode 100644 index 00000000000..c6fc13c7d7c --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/linktosecproc.vhd @@ -0,0 +1,176 @@ +------------------------------------------------------------------------------- +-- Title : link to sector processor +-- Project : +------------------------------------------------------------------------------- +-- File : linktosecproc.vhd +-- Author : Filippo Marini +-- Company : University of Colorado Boulder +-- Created : 2022-06-27 +-- Last update: 2023-04-06 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2022 University of Colorado Boulder +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2022-06-27 1.0 fmarini Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.emp_data_types.all; +use work.emp_device_decl.all; +use work.emp_ttc_decl.all; +-- emp thomas +-- use work.hybrid_tools.all; +-- use work.hybrid_config.all; +-- use work.hybrid_data_types.all; +-- use work.tracklet_config.all; +-- use work.tracklet_data_types.all; +-- emp US +use work.tf_pkg.all; +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f1.all; + +entity linktosecproc is + port ( + clk_i : in std_logic; + rst_i : in std_logic; + ttc_i : in ttc_stuff_array(N_REGION - 1 downto 0); + din_i : in ldata(4 * N_REGION - 1 downto 0); + ir_start_o : out std_logic; + bx_o : out std_logic_vector(2 downto 0); + DL_39_link_AV_dout : out t_arr_DL_39_DATA; + DL_39_link_empty_neg : out t_arr_DL_39_1b; + DL_39_link_read : in t_arr_DL_39_1b + ); +end entity linktosecproc; + +architecture rtl of linktosecproc is + + -- signal s_tracklet_reset : t_resets(numPPquads - 1 downto 0); + -- signal s_tracklet_isol : t_stubsDTC; + -- signal s_tracklet_data : t_datas(numInputsIR - 1 downto 0); + signal s_ir_start : std_logic; + signal s_ir_start_srff : std_logic; + signal s_din_d : ldata(4 * N_REGION - 1 downto 0); + signal s_din_dd : ldata(4 * N_REGION - 1 downto 0); + +begin -- architecture rtl + + -- tracklet_isolation_in_1 : entity work.tracklet_isolation_in + -- port map ( + -- clk => clk_i, + -- in_ttc => ttc_i, + -- in_din => din_i, + -- in_reset => s_tracklet_reset, + -- in_dout => s_tracklet_isol + -- ); + + -- tracklet_format_in_1 : entity work.tracklet_format_in + -- port map ( + -- clk => clk_i, + -- in_reset => s_tracklet_reset, + -- in_din => s_tracklet_isol, + -- in_dout => s_tracklet_data + -- ); + + GEN_DELAYED_DATA: for i in 68 to 107 generate + p_delay_data: process (clk_i) is + begin -- process p_delay_data + if rising_edge(clk_i) then -- rising clock edge + s_din_d(i).data <= din_i(i).data; + s_din_dd(i).data <= s_din_d(i).data; + s_din_d(i).valid <= din_i(i).valid; + end if; + end process p_delay_data; + end generate GEN_DELAYED_DATA; + + ----------------------------------------------------------------------------- + -- Connect input link data to IR in Sector Processor + ----------------------------------------------------------------------------- + DL_39_link_AV_DOUT(PS10G_1_A) <= s_din_dd(68).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_1_B) <= s_din_dd(69).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_2_A) <= s_din_dd(70).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_2_B) <= s_din_dd(71).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_3_A) <= s_din_dd(72).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_3_B) <= s_din_dd(73).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_4_A) <= s_din_dd(74).data(38 downto 0); + DL_39_link_AV_DOUT(PS10G_4_B) <= s_din_dd(75).data(38 downto 0); + DL_39_link_AV_DOUT(PS_1_A) <= s_din_dd(76).data(38 downto 0); + DL_39_link_AV_DOUT(PS_1_B) <= s_din_dd(77).data(38 downto 0); + DL_39_link_AV_DOUT(PS_2_A) <= s_din_dd(78).data(38 downto 0); + DL_39_link_AV_DOUT(PS_2_B) <= s_din_dd(79).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_1_A) <= s_din_dd(84).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_1_B) <= s_din_dd(85).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_2_A) <= s_din_dd(86).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_2_B) <= s_din_dd(87).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_3_A) <= s_din_dd(88).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_3_B) <= s_din_dd(89).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_4_A) <= s_din_dd(90).data(38 downto 0); + DL_39_link_AV_DOUT(negPS10G_4_B) <= s_din_dd(91).data(38 downto 0); + DL_39_link_AV_DOUT(negPS_1_A) <= s_din_dd(92).data(38 downto 0); + DL_39_link_AV_DOUT(negPS_1_B) <= s_din_dd(93).data(38 downto 0); + DL_39_link_AV_DOUT(negPS_2_A) <= s_din_dd(94).data(38 downto 0); + DL_39_link_AV_DOUT(negPS_2_B) <= s_din_dd(95).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_1_A) <= s_din_dd(96).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_1_B) <= s_din_dd(97).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_2_A) <= s_din_dd(98).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_2_B) <= s_din_dd(99).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_3_A) <= s_din_dd(100).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_3_B) <= s_din_dd(101).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_4_A) <= s_din_dd(102).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_4_B) <= s_din_dd(103).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_5_A) <= s_din_dd(104).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_5_B) <= s_din_dd(105).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_6_A) <= s_din_dd(106).data(38 downto 0); + DL_39_link_AV_DOUT(twoS_6_B) <= s_din_dd(107).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_1_A) <= s_din_dd(108).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_1_B) <= s_din_dd(109).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_2_A) <= s_din_dd(110).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_2_B) <= s_din_dd(111).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_3_A) <= s_din_dd(112).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_3_B) <= s_din_dd(113).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_4_A) <= s_din_dd(114).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_4_B) <= s_din_dd(115).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_5_A) <= s_din_dd(116).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_5_B) <= s_din_dd(117).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_6_A) <= s_din_dd(118).data(38 downto 0); + DL_39_link_AV_DOUT(neg2S_6_B) <= s_din_dd(119).data(38 downto 0); + + ----------------------------------------------------------------------------- + -- Generate start signal + ----------------------------------------------------------------------------- + set_reset_ffd_1 : entity work.set_reset_ffd + port map ( + clk_i => clk_i, + set_i => s_din_d(68).valid, + reset_i => rst_i, + q_o => s_ir_start_srff + ); + + + s_ir_start <= s_din_d(68).valid or s_ir_start_srff; + ir_start_o <= s_ir_start; + + p_bx_count : process (clk_i) is + variable v_bx : natural; + variable v_word_count : natural := 1; + begin -- process p_bx_count + if rising_edge(clk_i) then -- rising clock edge + if s_ir_start = '1' then + if v_word_count < MAX_ENTRIES then + v_word_count := v_word_count + 1; + else + v_word_count := 1; + v_bx := v_bx + 1; + end if; + end if; + bx_o <= std_logic_vector(to_unsigned(v_bx, bx_o'length)); + end if; + end process p_bx_count; + +end architecture rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/linktosecproc2.vhd b/IntegrationTests/DualFPGA/firmware/hdl/linktosecproc2.vhd new file mode 100644 index 00000000000..13dabdb9821 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/linktosecproc2.vhd @@ -0,0 +1,238 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.emp_data_types.all; +use work.emp_project_decl.all; +use work.emp_device_decl.all; + +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f2.all; + +entity linktosecproc2 is + port( + clk : in std_logic; + rst : in std_logic; + d : in ldata(4 * N_REGION - 1 downto 0); + AS_36_link_data : out t_arr_AS_36_37b; + MPAR_73_link_data : out t_arr_MTPAR_73_76b; + bx_link_data : out std_logic_vector(2 downto 0); + AS_36_link_valid : out t_arr_AS_36_1b; + MPAR_73_link_valid : out t_arr_MTPAR_73_1b; + bx_link_valid : out std_logic + ); + +end linktosecproc2; + +architecture rtl of linktosecproc2 is + + signal bx_link_data_int : std_logic_vector(2 downto 0) := "000"; + signal AS_signals : std_logic_vector(48*37 - 1 downto 0); + signal MTPAR_signals : std_logic_vector(15*76 - 1 downto 0); + +begin + + --Quad0: 0, 1, 2, 3 Dummy + --Quad1: 4, 5, 6, 7 + --Quad2: 8, 9, *10*,*11 + --Quad3: 12,13,14,15 + --Quad4: 16,17,18,19 + --Quad5: 20,21,22,23 + --Quad6: 24,25,26,27 + --Quad7: 28*,*29,30,31 + --Quad8: 32,33,34,35 + --Quad9: 36,37,38,39 + --Quad10: 40,41,42,43 + --Quad11: 44,45,46,47 Dummy + --Quad12: 48,49,50,51 + --Quad13: 52,53,54,55 + --Quad14: 56,57,58,59* + --Quad15: 60,61,62,63 Dummy + + AS_signals(63 + 0*64 downto 0 + 0*64) <= d(59).data(63 downto 0); + AS_signals(63 + 1*64 downto 0 + 1*64) <= d(58).data(63 downto 0); + AS_signals(63 + 2*64 downto 0 + 2*64) <= d(57).data(63 downto 0); + AS_signals(63 + 3*64 downto 0 + 3*64) <= d(56).data(63 downto 0); + AS_signals(63 + 4*64 downto 0 + 4*64) <= d(55).data(63 downto 0); + AS_signals(63 + 5*64 downto 0 + 5*64) <= d(54).data(63 downto 0); + AS_signals(63 + 6*64 downto 0 + 6*64) <= d(53).data(63 downto 0); + AS_signals(63 + 7*64 downto 0 + 7*64) <= d(52).data(63 downto 0); + AS_signals(63 + 8*64 downto 0 + 8*64) <= d(51).data(63 downto 0); + AS_signals(63 + 9*64 downto 0 + 9*64) <= d(50).data(63 downto 0); + AS_signals(63 + 10*64 downto 0 + 10*64) <= d(49).data(63 downto 0); + AS_signals(63 + 11*64 downto 0 + 11*64) <= d(48).data(63 downto 0); + + AS_signals(63 + 12*64 downto 0 + 12*64) <= d(43).data(63 downto 0); + AS_signals(63 + 13*64 downto 0 + 13*64) <= d(42).data(63 downto 0); + AS_signals(63 + 14*64 downto 0 + 14*64) <= d(41).data(63 downto 0); + AS_signals(63 + 15*64 downto 0 + 15*64) <= d(40).data(63 downto 0); + AS_signals(63 + 16*64 downto 0 + 16*64) <= d(39).data(63 downto 0); + AS_signals(63 + 17*64 downto 0 + 17*64) <= d(38).data(63 downto 0); + AS_signals(63 + 18*64 downto 0 + 18*64) <= d(37).data(63 downto 0); + AS_signals(63 + 19*64 downto 0 + 19*64) <= d(36).data(63 downto 0); + AS_signals(63 + 20*64 downto 0 + 20*64) <= d(35).data(63 downto 0); + AS_signals(63 + 21*64 downto 0 + 21*64) <= d(34).data(63 downto 0); + AS_signals(63 + 22*64 downto 0 + 22*64) <= d(33).data(63 downto 0); + AS_signals(63 + 23*64 downto 0 + 23*64) <= d(32).data(63 downto 0); + AS_signals(63 + 24*64 downto 0 + 24*64) <= d(31).data(63 downto 0); + AS_signals(63 + 25*64 downto 0 + 25*64) <= d(30).data(63 downto 0); + AS_signals(63 + 26*64 downto 0 + 26*64) <= d(29).data(63 downto 0); + AS_signals(63 + 27*64 - 16 downto 0 + 27*64) <= d(28).data(63 - 16 downto 0); + + MTPAR_signals(63 + 0*64 downto 0 + 0*64) <= d(27).data(63 downto 0); + MTPAR_signals(63 + 1*64 downto 0 + 1*64) <= d(26).data(63 downto 0); + MTPAR_signals(63 + 2*64 downto 0 + 2*64) <= d(25).data(63 downto 0); + MTPAR_signals(63 + 3*64 downto 0 + 3*64) <= d(24).data(63 downto 0); + MTPAR_signals(63 + 4*64 downto 0 + 4*64) <= d(23).data(63 downto 0); + MTPAR_signals(63 + 5*64 downto 0 + 5*64) <= d(22).data(63 downto 0); + MTPAR_signals(63 + 6*64 downto 0 + 6*64) <= d(21).data(63 downto 0); + MTPAR_signals(63 + 7*64 downto 0 + 7*64) <= d(20).data(63 downto 0); + MTPAR_signals(63 + 8*64 downto 0 + 8*64) <= d(19).data(63 downto 0); + MTPAR_signals(63 + 9*64 downto 0 + 9*64) <= d(18).data(63 downto 0); + MTPAR_signals(63 + 10*64 downto 0 + 10*64) <= d(17).data(63 downto 0); + MTPAR_signals(63 + 11*64 downto 0 + 11*64) <= d(16).data(63 downto 0); + MTPAR_signals(63 + 12*64 downto 0 + 12*64) <= d(15).data(63 downto 0); + MTPAR_signals(63 + 13*64 downto 0 + 13*64) <= d(14).data(63 downto 0); + MTPAR_signals(63 + 14*64 downto 0 + 14*64) <= d(13).data(63 downto 0); + MTPAR_signals(63 + 15*64 downto 0 + 15*64) <= d(12).data(63 downto 0); + MTPAR_signals(63 + 16*64 downto 0 + 16*64) <= d(11).data(63 downto 0); + MTPAR_signals(63 + 17*64 - 12 downto 0 + 17*64) <= d(10).data(63 - 12 downto 0); + + AS_36_link_data(L1PHIAn1) <= AS_signals(36 downto 0); + AS_36_link_data(L1PHIBn1) <= AS_signals(73 downto 37); + AS_36_link_data(L1PHICn1) <= AS_signals(110 downto 74); + AS_36_link_data(L1PHIDn1) <= AS_signals(147 downto 111); + AS_36_link_data(L1PHIEn1) <= AS_signals(184 downto 148); + AS_36_link_data(L1PHIFn1) <= AS_signals(221 downto 185); + AS_36_link_data(L1PHIGn1) <= AS_signals(258 downto 222); + AS_36_link_data(L1PHIHn1) <= AS_signals(295 downto 259); + AS_36_link_data(L2PHIAn1) <= AS_signals(332 downto 296); + AS_36_link_data(L2PHIBn1) <= AS_signals(369 downto 333); + AS_36_link_data(L2PHICn1) <= AS_signals(406 downto 370); + AS_36_link_data(L2PHIDn1) <= AS_signals(443 downto 407); + AS_36_link_data(L3PHIAn1) <= AS_signals(480 downto 444); + AS_36_link_data(L3PHIBn1) <= AS_signals(517 downto 481); + AS_36_link_data(L3PHICn1) <= AS_signals(554 downto 518); + AS_36_link_data(L3PHIDn1) <= AS_signals(591 downto 555); + AS_36_link_data(L4PHIAn1) <= AS_signals(628 downto 592); + AS_36_link_data(L4PHIBn1) <= AS_signals(665 downto 629); + AS_36_link_data(L4PHICn1) <= AS_signals(702 downto 666); + AS_36_link_data(L4PHIDn1) <= AS_signals(739 downto 703); + AS_36_link_data(L5PHIAn1) <= AS_signals(776 downto 740); + AS_36_link_data(L5PHIBn1) <= AS_signals(813 downto 777); + AS_36_link_data(L5PHICn1) <= AS_signals(850 downto 814); + AS_36_link_data(L5PHIDn1) <= AS_signals(887 downto 851); + AS_36_link_data(L6PHIAn1) <= AS_signals(924 downto 888); + AS_36_link_data(L6PHIBn1) <= AS_signals(961 downto 925); + AS_36_link_data(L6PHICn1) <= AS_signals(998 downto 962); + AS_36_link_data(L6PHIDn1) <= AS_signals(1035 downto 999); + AS_36_link_data(D1PHIAn1) <= AS_signals(1072 downto 1036); + AS_36_link_data(D1PHIBn1) <= AS_signals(1109 downto 1073); + AS_36_link_data(D1PHICn1) <= AS_signals(1146 downto 1110); + AS_36_link_data(D1PHIDn1) <= AS_signals(1183 downto 1147); + AS_36_link_data(D2PHIAn1) <= AS_signals(1220 downto 1184); + AS_36_link_data(D2PHIBn1) <= AS_signals(1257 downto 1221); + AS_36_link_data(D2PHICn1) <= AS_signals(1294 downto 1258); + AS_36_link_data(D2PHIDn1) <= AS_signals(1331 downto 1295); + AS_36_link_data(D3PHIAn1) <= AS_signals(1368 downto 1332); + AS_36_link_data(D3PHIBn1) <= AS_signals(1405 downto 1369); + AS_36_link_data(D3PHICn1) <= AS_signals(1442 downto 1406); + AS_36_link_data(D3PHIDn1) <= AS_signals(1479 downto 1443); + AS_36_link_data(D4PHIAn1) <= AS_signals(1516 downto 1480); + AS_36_link_data(D4PHIBn1) <= AS_signals(1553 downto 1517); + AS_36_link_data(D4PHICn1) <= AS_signals(1590 downto 1554); + AS_36_link_data(D4PHIDn1) <= AS_signals(1627 downto 1591); + AS_36_link_data(D5PHIAn1) <= AS_signals(1664 downto 1628); + AS_36_link_data(D5PHIBn1) <= AS_signals(1701 downto 1665); + AS_36_link_data(D5PHICn1) <= AS_signals(1738 downto 1702); + AS_36_link_data(D5PHIDn1) <= AS_signals(1775 downto 1739); + + --Note that since some AS words are built from data on multiple input links, + --only the valid from the first input is used + AS_36_link_valid(L1PHIAn1) <= d(59).valid; + AS_36_link_valid(L1PHIBn1) <= d(59).valid; + AS_36_link_valid(L1PHICn1) <= d(58).valid; + AS_36_link_valid(L1PHIDn1) <= d(58).valid; + AS_36_link_valid(L1PHIEn1) <= d(57).valid; + AS_36_link_valid(L1PHIFn1) <= d(57).valid; + AS_36_link_valid(L1PHIGn1) <= d(56).valid; + AS_36_link_valid(L1PHIHn1) <= d(55).valid; + AS_36_link_valid(L2PHIAn1) <= d(55).valid; + AS_36_link_valid(L2PHIBn1) <= d(54).valid; + AS_36_link_valid(L2PHICn1) <= d(54).valid; + AS_36_link_valid(L2PHIDn1) <= d(53).valid; + AS_36_link_valid(L3PHIAn1) <= d(53).valid; + AS_36_link_valid(L3PHIBn1) <= d(52).valid; + AS_36_link_valid(L3PHICn1) <= d(51).valid; + AS_36_link_valid(L3PHIDn1) <= d(51).valid; + AS_36_link_valid(L4PHIAn1) <= d(50).valid; + AS_36_link_valid(L4PHIBn1) <= d(50).valid; + AS_36_link_valid(L4PHICn1) <= d(49).valid; + AS_36_link_valid(L4PHIDn1) <= d(49).valid; + AS_36_link_valid(L5PHIAn1) <= d(48).valid; + AS_36_link_valid(L5PHIBn1) <= d(43).valid; + AS_36_link_valid(L5PHICn1) <= d(43).valid; + AS_36_link_valid(L5PHIDn1) <= d(42).valid; + AS_36_link_valid(L6PHIAn1) <= d(42).valid; + AS_36_link_valid(L6PHIBn1) <= d(41).valid; + AS_36_link_valid(L6PHICn1) <= d(40).valid; + AS_36_link_valid(L6PHIDn1) <= d(40).valid; + AS_36_link_valid(D1PHIAn1) <= d(39).valid; + AS_36_link_valid(D1PHIBn1) <= d(39).valid; + AS_36_link_valid(D1PHICn1) <= d(38).valid; + AS_36_link_valid(D1PHIDn1) <= d(38).valid; + AS_36_link_valid(D2PHIAn1) <= d(37).valid; + AS_36_link_valid(D2PHIBn1) <= d(36).valid; + AS_36_link_valid(D2PHICn1) <= d(36).valid; + AS_36_link_valid(D2PHIDn1) <= d(35).valid; + AS_36_link_valid(D3PHIAn1) <= d(35).valid; + AS_36_link_valid(D3PHIBn1) <= d(34).valid; + AS_36_link_valid(D3PHICn1) <= d(34).valid; + AS_36_link_valid(D3PHIDn1) <= d(33).valid; + AS_36_link_valid(D4PHIAn1) <= d(32).valid; + AS_36_link_valid(D4PHIBn1) <= d(32).valid; + AS_36_link_valid(D4PHICn1) <= d(31).valid; + AS_36_link_valid(D4PHIDn1) <= d(31).valid; + AS_36_link_valid(D5PHIAn1) <= d(30).valid; + AS_36_link_valid(D5PHIBn1) <= d(29).valid; + AS_36_link_valid(D5PHICn1) <= d(29).valid; + AS_36_link_valid(D5PHIDn1) <= d(28).valid; + + MPAR_73_link_data(L1L2ABC) <= MTPAR_signals(75 downto 0); + MPAR_73_link_data(L1L2DE) <= MTPAR_signals(151 downto 76); + MPAR_73_link_data(L1L2F) <= MTPAR_signals(227 downto 152); + MPAR_73_link_data(L1L2G) <= MTPAR_signals(303 downto 228); + MPAR_73_link_data(L1L2HI) <= MTPAR_signals(379 downto 304); + MPAR_73_link_data(L1L2JKL) <= MTPAR_signals(455 downto 380); + MPAR_73_link_data(L2L3ABCD) <= MTPAR_signals(531 downto 456); + MPAR_73_link_data(L3L4AB) <= MTPAR_signals(607 downto 532); + MPAR_73_link_data(L3L4CD) <= MTPAR_signals(683 downto 608); + MPAR_73_link_data(L5L6ABCD) <= MTPAR_signals(759 downto 684); + MPAR_73_link_data(D1D2ABCD) <= MTPAR_signals(835 downto 760); + MPAR_73_link_data(D3D4ABCD) <= MTPAR_signals(911 downto 836); + MPAR_73_link_data(L1D1ABCD) <= MTPAR_signals(987 downto 912); + MPAR_73_link_data(L1D1EFGH) <= MTPAR_signals(1063 downto 988); + MPAR_73_link_data(L2D1ABCD) <= MTPAR_signals(1139 downto 1064); + + MPAR_73_link_valid(L1L2ABC) <= d(27).valid; + MPAR_73_link_valid(L1L2DE) <= d(26).valid; + MPAR_73_link_valid(L1L2F) <= d(25).valid; + MPAR_73_link_valid(L1L2G) <= d(24).valid; + MPAR_73_link_valid(L1L2HI) <= d(23).valid; + MPAR_73_link_valid(L1L2JKL) <= d(22).valid; + MPAR_73_link_valid(L2L3ABCD) <= d(20).valid; + MPAR_73_link_valid(L3L4AB) <= d(19).valid; + MPAR_73_link_valid(L3L4CD) <= d(18).valid; + MPAR_73_link_valid(L5L6ABCD) <= d(17).valid; + MPAR_73_link_valid(D1D2ABCD) <= d(16).valid; + MPAR_73_link_valid(D3D4ABCD) <= d(14).valid; + MPAR_73_link_valid(L1D1ABCD) <= d(13).valid; + MPAR_73_link_valid(L1D1EFGH) <= d(12).valid; + MPAR_73_link_valid(L2D1ABCD) <= d(11).valid; + + --latch bx_link_data when not valid + bx_link_data_int <= d(9).data(2 downto 0) when (d(9).valid='1') else bx_link_data_int; + bx_link_data <= bx_link_data_int; + bx_link_valid <= d(9).valid; + +end rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/memUtil_aux_pkg_f1.vhd b/IntegrationTests/DualFPGA/firmware/hdl/memUtil_aux_pkg_f1.vhd new file mode 100644 index 00000000000..37809686c94 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/memUtil_aux_pkg_f1.vhd @@ -0,0 +1,21 @@ +--! Standard libraries +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--! User packages +use work.memUtil_Pkg.all; + +package memUtil_aux_pkg_f1 is + + -- ########################### Types ########################### + + type enum_AS_37 is (L1PHIAn1,L1PHIBn1,L1PHICn1,L1PHIDn1,L1PHIEn1,L1PHIFn1,L1PHIGn1,L1PHIHn1,L2PHIAn1,L2PHIBn1,L2PHICn1,L2PHIDn1,L3PHIAn1,L3PHIBn1,L3PHICn1,L3PHIDn1,L4PHIAn1,L4PHIBn1,L4PHICn1,L4PHIDn1,L5PHIAn1,L5PHIBn1,L5PHICn1,L5PHIDn1,L6PHIAn1,L6PHIBn1,L6PHICn1,L6PHIDn1,D1PHIAn1,D1PHIBn1,D1PHICn1,D1PHIDn1,D2PHIAn1,D2PHIBn1,D2PHICn1,D2PHIDn1,D3PHIAn1,D3PHIBn1,D3PHICn1,D3PHIDn1,D4PHIAn1,D4PHIBn1,D4PHICn1,D4PHIDn1,D5PHIAn1,D5PHIBn1,D5PHICn1,D5PHIDn1); + + type enum_MPAR_76 is (L1L2ABC,L1L2DE,L1L2F,L1L2G,L1L2HI,L1L2JKL,L2L3ABCD,L3L4AB,L3L4CD,L5L6ABCD,D1D2ABCD,D3D4ABCD,L1D1ABCD,L1D1EFGH,L2D1ABCD); + + type t_arr_DL_39_1b is array(enum_DL_39) of std_logic; + type t_arr_DL_39_DATA is array(enum_DL_39) of std_logic_vector(38 downto 0); + type t_arr_AS_37_DATA is array(enum_AS_37) of std_logic_vector(36 downto 0); + type t_arr_MPAR_76_DATA is array(enum_MPAR_76) of std_logic_vector(75 downto 0); + +end package memUtil_aux_pkg_f1; + diff --git a/IntegrationTests/DualFPGA/firmware/hdl/memUtil_aux_pkg_f2.vhd b/IntegrationTests/DualFPGA/firmware/hdl/memUtil_aux_pkg_f2.vhd new file mode 100644 index 00000000000..c92e1ba81f5 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/memUtil_aux_pkg_f2.vhd @@ -0,0 +1,35 @@ +--! Standard libraries +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--! User packages +use work.memUtil_Pkg.all; + +package memUtil_aux_pkg_f2 is + + -- ########################### Types ########################### + + type enum_AS_36_f1 is (L1PHIAn1,L1PHIBn1,L1PHICn1,L1PHIDn1,L1PHIEn1,L1PHIFn1,L1PHIGn1,L1PHIHn1,L2PHIAn1,L2PHIBn1,L2PHICn1,L2PHIDn1,L3PHIAn1,L3PHIBn1,L3PHICn1,L3PHIDn1,L4PHIAn1,L4PHIBn1,L4PHICn1,L4PHIDn1,L5PHIAn1,L5PHIBn1,L5PHICn1,L5PHIDn1,L6PHIAn1,L6PHIBn1,L6PHICn1,L6PHIDn1,D1PHIAn1,D1PHIBn1,D1PHICn1,D1PHIDn1,D2PHIAn1,D2PHIBn1,D2PHICn1,D2PHIDn1,D3PHIAn1,D3PHIBn1,D3PHICn1,D3PHIDn1,D4PHIAn1,D4PHIBn1,D4PHICn1,D4PHIDn1,D5PHIAn1,D5PHIBn1,D5PHICn1,D5PHIDn1); + + type enum_MTPAR_73 is (L1L2ABC,L1L2DE,L1L2F,L1L2G,L1L2HI,L1L2JKL,L2L3ABCD,L3L4AB,L3L4CD,L5L6ABCD,D1D2ABCD,D3D4ABCD,L1D1ABCD,L1D1EFGH,L2D1ABCD); + + type t_arr_AS_36_1b is array(enum_AS_36_f1) of std_logic; + type t_arr_AS_36_37b is array(enum_AS_36_f1) of std_logic_vector(36 downto 0); + type t_arr_AS_36_ADDR is array(enum_AS_36_f1) of std_logic_vector(9 downto 0); + type t_arr_AS_36_DATA is array(enum_AS_36_f1) of std_logic_vector(35 downto 0); + + type t_arr_MTPAR_73_1b is array(enum_MTPAR_73) of std_logic; + type t_arr_MTPAR_73_76b is array(enum_MTPAR_73) of std_logic_vector(75 downto 0); + type t_arr_MTPAR_73_ADDR is array(enum_MTPAR_73) of std_logic_vector(11 downto 0); + type t_arr_MTPAR_73_DATA is array(enum_MTPAR_73) of std_logic_vector(72 downto 0); + + type t_arr_TW_104_1b is array(enum_TW_104) of std_logic; + type t_arr_TW_104_DATA is array(enum_TW_104) of std_logic_vector(103 downto 0); + + type t_arr_BW_46_1b is array(enum_BW_46) of std_logic; + type t_arr_BW_46_DATA is array(enum_BW_46) of std_logic_vector(45 downto 0); + + type t_arr_DW_49_1b is array(enum_DW_49) of std_logic; + type t_arr_DW_49_DATA is array(enum_DW_49) of std_logic_vector(48 downto 0); + +end package memUtil_aux_pkg_f2; + diff --git a/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd b/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd new file mode 100644 index 00000000000..8665c0244d3 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd @@ -0,0 +1,111 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.ipbus.all; +use work.emp_data_types.all; +use work.emp_project_decl.all; +use work.emp_device_decl.all; +use work.emp_ttc_decl.all; +use work.emp_slink_types.all; +-- TF +use work.tf_pkg.all; +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f1.all; +use work.hybrid_data_types.all; +use work.conv_pkg_f1.all; + +entity emp_payload is + port( + clk : in std_logic; -- ipbus signals + rst : in std_logic; + ipb_in : in ipb_wbus; + ipb_out : out ipb_rbus; + clk40 : in std_logic; + clk_payload : in std_logic_vector(2 downto 0); + rst_payload : in std_logic_vector(2 downto 0); + clk_p : in std_logic; -- data clock + rst_loc : in std_logic_vector(N_REGION - 1 downto 0); + clken_loc : in std_logic_vector(N_REGION - 1 downto 0); + ctrs : in ttc_stuff_array; + bc0 : out std_logic; + d : in ldata(4 * N_REGION - 1 downto 0); -- data in + q : out ldata(4 * N_REGION - 1 downto 0); -- data out + gpio : out std_logic_vector(29 downto 0); -- IO to mezzanine connector + gpio_en : out std_logic_vector(29 downto 0); -- IO to mezzanine connector (three-state enables) + slink_q : out slink_input_data_quad_array(SLINK_MAX_QUADS-1 downto 0); + backpressure : in std_logic_vector(SLINK_MAX_QUADS-1 downto 0) + ); + +end emp_payload; + +architecture rtl of emp_payload is + + signal s_IR_data : t_arr_DL_39_DATA; + signal s_ir_start : std_logic; + signal s_bx : std_logic_vector(2 downto 0); + signal tp_bx : std_logic_vector(2 downto 0); + signal s_TP_bx_out_vld : std_logic; + signal AS_37_stream : t_arr_AS_37_DATA; + signal MPAR_76_stream : t_arr_MPAR_76_DATA; + +begin + + ----------------------------------------------------------------------------- + -- EMP ports + ----------------------------------------------------------------------------- + slink_q <= (others => SLINK_INPUT_DATA_ARRAY_NULL); + gpio <= (others => '0'); + gpio_en <= (others => '0'); + ipb_out <= IPB_RBUS_NULL; + bc0 <= '0'; + + ----------------------------------------------------------------------------- + -- Link to Sector Processor formatter + ----------------------------------------------------------------------------- + linktosecproc_1 : entity work.linktosecproc + port map ( + clk_i => clk_p, + rst_i => rst, + ttc_i => ctrs, + din_i => d, + ir_start_o => s_ir_start, + bx_o => s_bx, + DL_39_link_AV_dout => s_IR_data, + DL_39_link_empty_neg => open, + DL_39_link_read => (others => '0') + ); + + ----------------------------------------------------------------------------- + -- Sector Processor + ----------------------------------------------------------------------------- + tf1_wrapper_1 : entity work.tf1_wrapper + port map ( + clk => clk_p, + reset => rst, + IR_start => s_ir_start, + IR_bx_in => s_bx, + TP_bx_out_0 => tp_bx, + TP_bx_out_vld => s_TP_bx_out_vld, + TP_done => open, + DL_39_link_AV_dout => s_IR_data, + DL_39_link_empty_neg => (others => '1'), + DL_39_link_read => open, + AS_37_stream_V_dout => AS_37_stream, + MPAR_76_stream_V_dout => MPAR_76_stream + ); + + ----------------------------------------------------------------------------- + -- Link formatter + ----------------------------------------------------------------------------- + secproc1tolink_1 : entity work.secproc1tolink + port map ( + clk => clk_p, + rst => rst, + TP_bx_out => tp_bx, + AS_37_stream_V_dout => AS_37_stream, + MPAR_76_stream_V_dout => MPAR_76_stream, + node_packet => conv_single(d), + q => q + ); + +end rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/payload_f2.vhd b/IntegrationTests/DualFPGA/firmware/hdl/payload_f2.vhd new file mode 100644 index 00000000000..dff32eb4792 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/payload_f2.vhd @@ -0,0 +1,204 @@ +-- dummy project for testing +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.ipbus.all; +use work.emp_data_types.all; +use work.emp_project_decl.all; + +use work.emp_device_decl.all; +use work.emp_ttc_decl.all; + +use work.emp_slink_types.all; + +use work.tf_pkg.all; +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f2.all; +use work.tf_interface_pkg.all; +use work.hybrid_data_types.all; +use work.hybrid_config.all; +use work.hybrid_data_formats.all; + +entity emp_payload is + port( + clk : in std_logic; -- ipbus signals + rst : in std_logic; + ipb_in : in ipb_wbus; + ipb_out : out ipb_rbus; + clk40 : in std_logic; + clk_payload : in std_logic_vector(2 downto 0); + rst_payload : in std_logic_vector(2 downto 0); + clk_p : in std_logic; -- data clock + rst_loc : in std_logic_vector(N_REGION - 1 downto 0); + clken_loc : in std_logic_vector(N_REGION - 1 downto 0); + ctrs : in ttc_stuff_array; + bc0 : out std_logic; + d : in ldata(4 * N_REGION - 1 downto 0); -- data in + q : out ldata(4 * N_REGION - 1 downto 0); -- data out + gpio : out std_logic_vector(29 downto 0); -- IO to mezzanine connector + gpio_en : out std_logic_vector(29 downto 0); -- IO to mezzanine connector (three-state enables) + slink_q : out slink_input_data_quad_array(SLINK_MAX_QUADS-1 downto 0); + backpressure : in std_logic_vector(SLINK_MAX_QUADS-1 downto 0) + ); + +end emp_payload; + +architecture rtl of emp_payload is + + signal AS_36_link_data : t_arr_AS_36_37b; + signal MPAR_73_link_data : t_arr_MTPAR_73_76b; + signal AS_36_link_valid : t_arr_AS_36_1b; + signal MPAR_73_link_valid : t_arr_MTPAR_73_1b; + signal bx_link_data : std_logic_vector(2 downto 0); + signal bx_link_valid : std_logic; + signal PC_start : std_logic; + signal PC_bx_in : std_logic_vector(2 downto 0); + signal AS_36_wea : t_arr_AS_36_1b; + signal AS_36_writeaddr : t_arr_AS_36_ADDR; + signal AS_36_din : t_arr_AS_36_DATA; + signal MPAR_73_wea : t_arr_MTPAR_73_1b; + signal MPAR_73_writeaddr : t_arr_MTPAR_73_ADDR; + signal MPAR_73_din : t_arr_MTPAR_73_DATA; + signal s_tftokf : t_channlesTB(numTW_104 - 1 downto 0); + signal s_kfin : t_channlesTB(numNodesKF - 1 downto 0); + signal s_kfout : t_frames(numLinksTFP - 1 downto 0); + signal s_tfout : ldata(numLinksTFP - 1 downto 0); + signal FT_bx_out_0 : std_logic_vector(2 downto 0); + signal FT_bx_out_vld : std_logic; + signal FT_done : std_logic; + signal FT_last_track : std_logic; + signal FT_last_track_vld : std_logic; + signal TW_104_stream_AV_din : t_arr_TW_104_DATA; + signal TW_104_stream_A_write : t_arr_TW_104_1b; + signal DW_49_stream_AV_din : t_arr_DW_49_DATA; + signal DW_49_stream_A_write : t_arr_DW_49_1b; + signal BW_46_stream_AV_din : t_arr_BW_46_DATA; + signal BW_46_stream_A_write : t_arr_BW_46_1b; + +begin + + ----------------------------------------------------------------------------- + -- Link to Sector Processor Formatter + ----------------------------------------------------------------------------- + linktosecproc2_1 : entity work.linktosecproc2 + port map ( + clk => clk_p, + rst => rst, + d => d, + AS_36_link_data => AS_36_link_data, + MPAR_73_link_data => MPAR_73_link_data, + bx_link_data => bx_link_data, + AS_36_link_valid => AS_36_link_valid, + MPAR_73_link_valid => MPAR_73_link_valid, + bx_link_valid => bx_link_valid + ); + + ----------------------------------------------------------------------------- + -- Drive memory writes for SectorProcessor + ----------------------------------------------------------------------------- + sp2_mem_writer_1 : entity work.sp2_mem_writer + port map ( + clk => clk_p, + reset => rst, + AS_36_link_data => AS_36_link_data, + MPAR_73_link_data => MPAR_73_link_data, + bx_link_data => bx_link_data, + AS_36_link_valid => AS_36_link_valid, + MPAR_73_link_valid => MPAR_73_link_valid, + bx_link_valid => bx_link_valid, + AS_36_wea => AS_36_wea, + AS_36_writeaddr => AS_36_writeaddr, + AS_36_din => AS_36_din, + MPAR_73_wea => MPAR_73_wea, + MPAR_73_writeaddr => MPAR_73_writeaddr, + MPAR_73_din => MPAR_73_din, + PC_start => PC_start, + PC_bx_in => PC_bx_in + ); + + ----------------------------------------------------------------------------- + -- FPGA2 Sector Processor (PC/VMSMER -> MP -> TB) + ----------------------------------------------------------------------------- + tf2_wrapper_1 : entity work.tf2_wrapper + port map ( + clk => clk_p, + reset => rst, + PC_start => PC_start, + PC_bx_in => PC_bx_in, + PC_bx_out => open, + PC_bx_out_vld => open, + PC_done => open, + FT_bx_out => FT_bx_out_0, + FT_bx_out_vld => FT_bx_out_vld, + FT_done => FT_done, + FT_last_track => FT_last_track, + FT_last_track_vld => FT_last_track_vld, + AS_36_wea => AS_36_wea, + AS_36_writeaddr => AS_36_writeaddr, + AS_36_din => AS_36_din, + MPAR_73_wea => MPAR_73_wea, + MPAR_73_writeaddr => MPAR_73_writeaddr, + MPAR_73_din => MPAR_73_din, + TW_104_stream_AV_din => TW_104_stream_AV_din, + TW_104_stream_A_full_neg => (others => '1'), + TW_104_stream_A_write => TW_104_stream_A_write, + DW_49_stream_AV_din => DW_49_stream_AV_din, + DW_49_stream_A_full_neg => (others => '1'), + DW_49_stream_A_write => DW_49_stream_A_write, + BW_46_stream_AV_din => BW_46_stream_AV_din, + BW_46_stream_A_full_neg => (others => '1'), + BW_46_stream_A_write => BW_46_stream_A_write + ); + + ----------------------------------------------------------------------------- + -- Sector Processor to KF formatter + ----------------------------------------------------------------------------- + tf_to_kf_1 : entity work.tf_to_kf + port map ( + clk_i => clk_p, + TW_104_data_i => TW_104_stream_AV_din, + TW_104_valid_i => TW_104_stream_A_write, + DW_49_data_i => DW_49_stream_AV_din, + DW_49_valid_i => DW_49_stream_A_write, + BW_46_data_i => BW_46_stream_AV_din, + BW_46_valid_i => BW_46_stream_A_write, + kf_reset_i => FT_bx_out_vld, + tftokf_o => s_tftokf + ); + + ----------------------------------------------------------------------------- + -- KF Input merger (to be replaced by DR) + ----------------------------------------------------------------------------- + kf_input_merger_1 : entity work.kf_input_merger + port map ( + clk => clk_p, + din => s_tftokf, + dout => s_kfin + ); + + ----------------------------------------------------------------------------- + -- KF + ----------------------------------------------------------------------------- + kf_wrapper_1 : entity work.kf_wrapper + port map ( + clk_i => clk_p, + kfin_i => s_kfin, + kfout_o => s_kfout + ); + + ----------------------------------------------------------------------------- + -- Output step + ----------------------------------------------------------------------------- + kfout_isolation_out_1 : entity work.kfout_isolation_out + port map ( + clk => clk_p, + out_packet => conv_f2(d), + out_din => s_kfout, + out_dout => s_tfout + ); + + q(92) <= s_tfout(0); + q(93) <= s_tfout(1); + +end rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/secproc1tolink.vhd b/IntegrationTests/DualFPGA/firmware/hdl/secproc1tolink.vhd new file mode 100644 index 00000000000..3eb9431f832 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/secproc1tolink.vhd @@ -0,0 +1,183 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.emp_data_types.all; +use work.emp_project_decl.all; +use work.emp_device_decl.all; + +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f1.all; +use work.hybrid_data_types.all; + +entity secproc1tolink is + port( + clk : in std_logic; + rst : in std_logic; + TP_bx_out : in std_logic_vector(2 downto 0); + AS_37_stream_V_dout : in t_arr_AS_37_DATA; + MPAR_76_stream_V_dout : in t_arr_MPAR_76_DATA; + node_packet : in t_packet; + q : out ldata(4 * N_REGION - 1 downto 0) + ); + +end secproc1tolink; + +architecture rtl of secproc1tolink is + + signal bx_out : std_logic_vector(2 downto 0) := "111"; + + constant dataword_length : integer := 64; + constant n_interfpga_links : integer := 64; + signal AS_counter : integer := 0; + signal MPAR_counter : integer := 0; + signal AS_signals : std_logic_vector(dataword_length * 28 - 1 downto 0); + signal MPAR_signals : std_logic_vector(dataword_length * 18 - 1 downto 0); + signal sr : t_packets( PAYLOAD_LATENCY - 1 downto 0 ) := ( others => ( others => '0' ) ); + +begin + + AS_signals(1775 downto 0) <= AS_37_stream_V_dout(L1PHIAn1) & + AS_37_stream_V_dout(L1PHIBn1) & + AS_37_stream_V_dout(L1PHICn1) & + AS_37_stream_V_dout(L1PHIDn1) & + AS_37_stream_V_dout(L1PHIEn1) & + AS_37_stream_V_dout(L1PHIFn1) & + AS_37_stream_V_dout(L1PHIGn1) & + AS_37_stream_V_dout(L1PHIHn1) & + AS_37_stream_V_dout(L2PHIAn1) & + AS_37_stream_V_dout(L2PHIBn1) & + AS_37_stream_V_dout(L2PHICn1) & + AS_37_stream_V_dout(L2PHIDn1) & + AS_37_stream_V_dout(L3PHIAn1) & + AS_37_stream_V_dout(L3PHIBn1) & + AS_37_stream_V_dout(L3PHICn1) & + AS_37_stream_V_dout(L3PHIDn1) & + AS_37_stream_V_dout(L4PHIAn1) & + AS_37_stream_V_dout(L4PHIBn1) & + AS_37_stream_V_dout(L4PHICn1) & + AS_37_stream_V_dout(L4PHIDn1) & + AS_37_stream_V_dout(L5PHIAn1) & + AS_37_stream_V_dout(L5PHIBn1) & + AS_37_stream_V_dout(L5PHICn1) & + AS_37_stream_V_dout(L5PHIDn1) & + AS_37_stream_V_dout(L6PHIAn1) & + AS_37_stream_V_dout(L6PHIBn1) & + AS_37_stream_V_dout(L6PHICn1) & + AS_37_stream_V_dout(L6PHIDn1) & + AS_37_stream_V_dout(D1PHIAn1) & + AS_37_stream_V_dout(D1PHIBn1) & + AS_37_stream_V_dout(D1PHICn1) & + AS_37_stream_V_dout(D1PHIDn1) & + AS_37_stream_V_dout(D2PHIAn1) & + AS_37_stream_V_dout(D2PHIBn1) & + AS_37_stream_V_dout(D2PHICn1) & + AS_37_stream_V_dout(D2PHIDn1) & + AS_37_stream_V_dout(D3PHIAn1) & + AS_37_stream_V_dout(D3PHIBn1) & + AS_37_stream_V_dout(D3PHICn1) & + AS_37_stream_V_dout(D3PHIDn1) & + AS_37_stream_V_dout(D4PHIAn1) & + AS_37_stream_V_dout(D4PHIBn1) & + AS_37_stream_V_dout(D4PHICn1) & + AS_37_stream_V_dout(D4PHIDn1) & + AS_37_stream_V_dout(D5PHIAn1) & + AS_37_stream_V_dout(D5PHIBn1) & + AS_37_stream_V_dout(D5PHICn1) & + AS_37_stream_V_dout(D5PHIDn1); + + MPAR_signals(1139 downto 0) <= MPAR_76_stream_V_dout(L1L2ABC) & + MPAR_76_stream_V_dout(L1L2DE) & + MPAR_76_stream_V_dout(L1L2F) & + MPAR_76_stream_V_dout(L1L2G) & + MPAR_76_stream_V_dout(L1L2HI) & + MPAR_76_stream_V_dout(L1L2JKL) & + MPAR_76_stream_V_dout(L2L3ABCD) & + MPAR_76_stream_V_dout(L3L4AB) & + MPAR_76_stream_V_dout(L3L4CD) & + MPAR_76_stream_V_dout(L5L6ABCD) & + MPAR_76_stream_V_dout(D1D2ABCD) & + MPAR_76_stream_V_dout(D3D4ABCD) & + MPAR_76_stream_V_dout(L1D1ABCD) & + MPAR_76_stream_V_dout(L1D1EFGH) & + MPAR_76_stream_V_dout(L2D1ABCD); + + process( clk ) is + begin + if rising_edge( clk ) then + sr <= sr( sr'high - 1 downto 0 ) & node_packet; + end if; + end process; + + q(4).data(63 downto 0) <= AS_signals(63 + 0*64 downto 0 + 0*64); + q(5).data(63 downto 0) <= AS_signals(63 + 1*64 downto 0 + 1*64); + q(6).data(63 downto 0) <= AS_signals(63 + 2*64 downto 0 + 2*64); + q(7).data(63 downto 0) <= AS_signals(63 + 3*64 downto 0 + 3*64); + q(8).data(63 downto 0) <= AS_signals(63 + 4*64 downto 0 + 4*64); + q(9).data(63 downto 0) <= AS_signals(63 + 5*64 downto 0 + 5*64); + q(10).data(63 downto 0) <= AS_signals(63 + 6*64 downto 0 + 6*64); + q(11).data(63 downto 0) <= AS_signals(63 + 7*64 downto 0 + 7*64); + q(12).data(63 downto 0) <= AS_signals(63 + 8*64 downto 0 + 8*64); + q(13).data(63 downto 0) <= AS_signals(63 + 9*64 downto 0 + 9*64); + q(14).data(63 downto 0) <= AS_signals(63 + 10*64 downto 0 + 10*64); + q(15).data(63 downto 0) <= AS_signals(63 + 11*64 downto 0 + 11*64); + + q(20).data(63 downto 0) <= AS_signals(63 + 12*64 downto 0 + 12*64); + q(21).data(63 downto 0) <= AS_signals(63 + 13*64 downto 0 + 13*64); + q(22).data(63 downto 0) <= AS_signals(63 + 14*64 downto 0 + 14*64); + q(23).data(63 downto 0) <= AS_signals(63 + 15*64 downto 0 + 15*64); + q(24).data(63 downto 0) <= AS_signals(63 + 16*64 downto 0 + 16*64); + q(25).data(63 downto 0) <= AS_signals(63 + 17*64 downto 0 + 17*64); + q(26).data(63 downto 0) <= AS_signals(63 + 18*64 downto 0 + 18*64); + q(27).data(63 downto 0) <= AS_signals(63 + 19*64 downto 0 + 19*64); + q(28).data(63 downto 0) <= AS_signals(63 + 20*64 downto 0 + 20*64); + q(29).data(63 downto 0) <= AS_signals(63 + 21*64 downto 0 + 21*64); + q(30).data(63 downto 0) <= AS_signals(63 + 22*64 downto 0 + 22*64); + q(31).data(63 downto 0) <= AS_signals(63 + 23*64 downto 0 + 23*64); + q(32).data(63 downto 0) <= AS_signals(63 + 24*64 downto 0 + 24*64); + q(33).data(63 downto 0) <= AS_signals(63 + 25*64 downto 0 + 25*64); + q(34).data(63 downto 0) <= AS_signals(63 + 26*64 downto 0 + 26*64); + q(35).data(63 - 16 downto 0) <= AS_signals(63 + 27*64 - 16 downto 0 + 27*64); + q(35).data(63 downto 63-15) <= (others => '0'); + + --although we are just sending this to FPGA2, FPGA2 uses the control signals + --to determine its outputs control signals, so we should synchronize these + control_signals1 : for i in 4 to 15 generate + q(i).start_of_orbit <= sr(sr'high).start_of_orbit; + q(i).start <= sr(sr'high).start; + q(i).last <= sr(sr'high).last; + q(i).valid <= sr(sr'high).valid; + end generate; + control_signals2 : for i in 20 to 54 generate + q(i).start_of_orbit <= sr(sr'high).start_of_orbit; + q(i).start <= sr(sr'high).start; + q(i).last <= sr(sr'high).last; + q(i).valid <= sr(sr'high).valid; + end generate; + + --15 76bit signals can be accomodated by 18 64bit signals, this will leave + --12 empty bits in the last data word + q(36).data(63 downto 0) <= MPAR_signals(63 + 0*64 downto 0 + 0*64); + q(37).data(63 downto 0) <= MPAR_signals(63 + 1*64 downto 0 + 1*64); + q(38).data(63 downto 0) <= MPAR_signals(63 + 2*64 downto 0 + 2*64); + q(39).data(63 downto 0) <= MPAR_signals(63 + 3*64 downto 0 + 3*64); + q(40).data(63 downto 0) <= MPAR_signals(63 + 4*64 downto 0 + 4*64); + q(41).data(63 downto 0) <= MPAR_signals(63 + 5*64 downto 0 + 5*64); + q(42).data(63 downto 0) <= MPAR_signals(63 + 6*64 downto 0 + 6*64); + q(43).data(63 downto 0) <= MPAR_signals(63 + 7*64 downto 0 + 7*64); + q(44).data(63 downto 0) <= MPAR_signals(63 + 8*64 downto 0 + 8*64); + q(45).data(63 downto 0) <= MPAR_signals(63 + 9*64 downto 0 + 9*64); + q(46).data(63 downto 0) <= MPAR_signals(63 + 10*64 downto 0 + 10*64); + q(47).data(63 downto 0) <= MPAR_signals(63 + 11*64 downto 0 + 11*64); + q(48).data(63 downto 0) <= MPAR_signals(63 + 12*64 downto 0 + 12*64); + q(49).data(63 downto 0) <= MPAR_signals(63 + 13*64 downto 0 + 13*64); + q(50).data(63 downto 0) <= MPAR_signals(63 + 14*64 downto 0 + 14*64); + q(51).data(63 downto 0) <= MPAR_signals(63 + 15*64 downto 0 + 15*64); + q(52).data(63 downto 0) <= MPAR_signals(63 + 16*64 downto 0 + 16*64); + q(53).data(63 - 12 downto 0) <= MPAR_signals(63 + 17*64 - 12 downto 0 + 17*64); + q(53).data(63 downto 63-11) <= (others => '0'); + + q(54).data(2 downto 0) <= bx_out; + q(54).data(63 downto 3) <= (others => '0'); + +end rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/sp2_mem_writer.vhd b/IntegrationTests/DualFPGA/firmware/hdl/sp2_mem_writer.vhd new file mode 100644 index 00000000000..d684c8bde66 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/sp2_mem_writer.vhd @@ -0,0 +1,174 @@ +--=========================================================================== +--! @file sp2_mem_writer.vhd +--! @brief Simple module to coordinate writing to FPGA2 SP input memories +--! @author Michael Oshiro +--! @date 2024-04-16 +--! @version v.1.0 +--=========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f2.all; + +entity sp2_mem_writer is + port ( + clk : in std_logic; + reset : in std_logic; + AS_36_link_data : in t_arr_AS_36_37b; + MPAR_73_link_data : in t_arr_MTPAR_73_76b; + bx_link_data : in std_logic_vector(2 downto 0); + AS_36_link_valid : in t_arr_AS_36_1b; + MPAR_73_link_valid : in t_arr_MTPAR_73_1b; + bx_link_valid : in std_logic; + AS_36_wea : out t_arr_AS_36_1b; + AS_36_writeaddr : out t_arr_AS_36_ADDR; + AS_36_din : out t_arr_AS_36_DATA; + MPAR_73_wea : out t_arr_MTPAR_73_1b; + MPAR_73_writeaddr : out t_arr_MTPAR_73_ADDR; + MPAR_73_din : out t_arr_MTPAR_73_DATA; + PC_start : out std_logic; + PC_bx_in : out std_logic_vector(2 downto 0) + ); +end entity sp2_mem_writer; + +architecture rtl of sp2_mem_writer is + + type t_arr_AS_36_7b is array(enum_AS_36_f1) of std_logic_vector(6 downto 0); + type t_arr4_7b is array(0 to 3) of std_logic_vector(6 downto 0); + type t_arr_MTPAR_73_arr4_7b is array(enum_MTPAR_73) of t_arr4_7b; + type t_arr_MTPAR_73_2b is array(enum_MTPAR_73) of std_logic_vector(1 downto 0); + + signal AS_36_adr : t_arr_AS_36_7b := (others => "0000000"); + signal MPAR_73_adr : t_arr_MTPAR_73_arr4_7b := (others => (others => "0000000")); + signal MPAR_73_pge : t_arr_MTPAR_73_2b := (others => "00"); + signal bx_prev : std_logic_vector(2 downto 0) := "000"; + signal bx_change : std_logic_vector(2 downto 0) := "000"; + signal AS_36_wea_int : t_arr_AS_36_1b := (others => '0'); + signal MPAR_73_wea_int : t_arr_MTPAR_73_1b := (others => '0'); + signal AS_36_din_int : t_arr_AS_36_DATA := (others => (others => '0')); + signal MPAR_73_din_int : t_arr_MTPAR_73_DATA := (others => (others => '0')); + signal PC_start_int : std_logic := '0'; + + signal AS_36_wea_pipeline0 : t_arr_AS_36_1b := (others => '0'); + signal AS_36_writeaddr_pipeline0 : t_arr_AS_36_ADDR := (others => (others => '0')); + signal AS_36_din_pipeline0 : t_arr_AS_36_DATA := (others => (others => '0')); + signal MPAR_73_wea_pipeline0 : t_arr_MTPAR_73_1b := (others => '0'); + signal MPAR_73_writeaddr_pipeline0 : t_arr_MTPAR_73_ADDR := (others => (others => '0')); + signal MPAR_73_din_pipeline0 : t_arr_MTPAR_73_DATA := (others => (others => '0')); + signal PC_bx_in_pipeline0 : std_logic_vector(2 downto 0) := "000"; + signal PC_start_pipeline0 : std_logic := '0'; + + signal AS_36_wea_pipeline : t_arr_AS_36_1b := (others => '0'); + signal AS_36_writeaddr_pipeline : t_arr_AS_36_ADDR := (others => (others => '0')); + signal AS_36_din_pipeline : t_arr_AS_36_DATA := (others => (others => '0')); + signal MPAR_73_wea_pipeline : t_arr_MTPAR_73_1b := (others => '0'); + signal MPAR_73_writeaddr_pipeline : t_arr_MTPAR_73_ADDR := (others => (others => '0')); + signal MPAR_73_din_pipeline : t_arr_MTPAR_73_DATA := (others => (others => '0')); + signal PC_bx_in_pipeline : std_logic_vector(2 downto 0) := "000"; + signal PC_start_pipeline : std_logic := '0'; + +begin -- architecture rtl + + p_writemem : process (clk) is + + begin -- process p_writemem + if rising_edge(clk) then -- rising clock edge + + --Convert streamed AllStubs data into memory inputs for SectorProcessor + --write enable and data in are set directly from link data + --address is updated on next clock after each write and set to 0 after BX change + for i in AS_36_link_data'range loop + if (AS_36_link_valid(i) = '1' and AS_36_link_data(i)(36) = '1') then + AS_36_wea_int(i) <= '1'; + AS_36_din_int(i) <= AS_36_link_data(i)(35 downto 0); + else + AS_36_wea_int(i) <= '0'; + end if; + + if (bx_change /= "000") then + AS_36_adr(i) <= "0000000"; + elsif (AS_36_wea_int(i) = '1') then + AS_36_adr(i) <= std_logic_vector(unsigned(AS_36_adr(i))+1); + end if; + end loop; --AS_36 loop + + --Convert streamed MergedParameters data into memory inputs for SectorProcessor + --write enable, data, and top two address non-bx bits in are set directly from link data + --addresses for each of the four "pages" are managed by separate counters, which are + --updated after each write and reset on BX change + for i in MPAR_73_link_data'range loop + if (MPAR_73_link_valid(i) = '1' and MPAR_73_link_data(i)(75) = '1') then + MPAR_73_wea_int(i) <= '1'; + MPAR_73_din_int(i) <= MPAR_73_link_data(i)(72 downto 0); + MPAR_73_pge(i) <= MPAR_73_link_data(i)(74 downto 73); + --TODO check order of valid and page bits in first FPGA project + else + MPAR_73_wea_int(i) <= '0'; + end if; + + if (bx_change /= "000") then + MPAR_73_adr(i)(0) <= "0000000"; + MPAR_73_adr(i)(1) <= "0000000"; + MPAR_73_adr(i)(2) <= "0000000"; + MPAR_73_adr(i)(3) <= "0000000"; + elsif (MPAR_73_wea_int(i) = '1') then + MPAR_73_adr(i)(to_integer(unsigned(MPAR_73_pge(i)))) + <= std_logic_vector(unsigned(MPAR_73_adr(i)(to_integer(unsigned(MPAR_73_pge(i)))))+1); + end if; + end loop; --MPAR_73 loop + + if (bx_change /= "000") then + PC_start_int <= '1'; + --else + -- PC_start <= '0'; + end if; + + bx_prev <= bx_link_data; + + end if; --rising clock edge + end process p_writemem; + + --build full memory addresses based on word, page, and BX + g_as_address : for i in AS_36_writeaddr'range generate + AS_36_writeaddr_pipeline0(i) <= bx_prev & AS_36_adr(i); + end generate g_as_address; + + g_mpar_address : for i in MPAR_73_writeaddr'range generate + MPAR_73_writeaddr_pipeline0(i) <= bx_prev & MPAR_73_pge(i) & MPAR_73_adr(i)(to_integer(unsigned(MPAR_73_pge(i)))); + end generate g_mpar_address; + + bx_change <= bx_prev xor bx_link_data; + AS_36_wea_pipeline0 <= AS_36_wea_int; + MPAR_73_wea_pipeline0 <= MPAR_73_wea_int; + AS_36_din_pipeline0 <= AS_36_din_int; + MPAR_73_din_pipeline0 <= MPAR_73_din_int; + PC_bx_in_pipeline0 <= std_logic_vector(unsigned(bx_prev)-1); + PC_start_pipeline0 <= PC_start_int; + --PC_bx_in <= bx_prev; + + p_pipeline : process (clk) is + begin -- process p_pipeline + if rising_edge(clk) then -- rising clock edge + AS_36_wea_pipeline <= AS_36_wea_pipeline0; + AS_36_writeaddr_pipeline <= AS_36_writeaddr_pipeline0; + AS_36_din_pipeline <= AS_36_din_pipeline0; + MPAR_73_wea_pipeline <= MPAR_73_wea_pipeline0; + MPAR_73_writeaddr_pipeline <= MPAR_73_writeaddr_pipeline0; + MPAR_73_din_pipeline <= MPAR_73_din_pipeline0; + PC_bx_in_pipeline <= PC_bx_in_pipeline0; + PC_start_pipeline <= PC_start_pipeline0; + + AS_36_wea <= AS_36_wea_pipeline; + AS_36_writeaddr <= AS_36_writeaddr_pipeline; + AS_36_din <= AS_36_din_pipeline; + MPAR_73_wea <= MPAR_73_wea_pipeline; + MPAR_73_writeaddr <= MPAR_73_writeaddr_pipeline; + MPAR_73_din <= MPAR_73_din_pipeline; + PC_bx_in <= PC_bx_in_pipeline; + PC_start <= PC_start_pipeline; + end if; + end process; + +end architecture rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tb_decl_f1.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tb_decl_f1.vhd new file mode 100644 index 00000000000..ef364355065 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/tb_decl_f1.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +use work.emp_project_decl.all; + +package tb_decl is + + +constant SOURCE_FILE : string := "in_fpga1.txt"; +constant SINK_FILE : string := "out.txt"; + +constant PLAYBACK_LENGTH : integer := 100 * 108; +constant CAPTURE_LENGTH : integer := 100 * 108; +constant WAIT_CYCLES_AT_START: integer := 0; +constant PLAYBACK_OFFSET : integer := 0; +constant CAPTURE_OFFSET : integer := PAYLOAD_LATENCY + 3; + +constant PLAYBACK_LOOP : boolean := false; +constant STRIP_HEADER : boolean := false; +constant INSERT_HEADER : boolean := false; + + +end package; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tb_decl_f2.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tb_decl_f2.vhd new file mode 100644 index 00000000000..4d52347c3f5 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/tb_decl_f2.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +use work.emp_project_decl.all; + +package tb_decl is + + +constant SOURCE_FILE : string := "in_fpga2.txt"; +constant SINK_FILE : string := "out.txt"; + +constant PLAYBACK_LENGTH : integer := 100 * 108; +constant CAPTURE_LENGTH : integer := 100 * 108; +constant WAIT_CYCLES_AT_START: integer := 0; +constant PLAYBACK_OFFSET : integer := 0; +constant CAPTURE_OFFSET : integer := PAYLOAD_LATENCY + 3; + +constant PLAYBACK_LOOP : boolean := false; +constant STRIP_HEADER : boolean := false; +constant INSERT_HEADER : boolean := false; + + +end package; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd new file mode 100644 index 00000000000..47401b6fa5f --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd @@ -0,0 +1,266 @@ +------------------------------------------------------------------------------- +-- Title : tf wrapper +-- Project : +------------------------------------------------------------------------------- +-- File : tf_wrapper.vhd +-- Author : Michael Oshiro +-- Company : Cornell University +-- Created : 2024-01-19 +-- Last update: 2024-01-19 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: Simple module to pack/unpack SectorProcessor inputs into vectors +------------------------------------------------------------------------------- +-- Copyright (c) 2024 Cornell University +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2022-01-19 1.0 oshiro Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f1.all; + +entity tf1_wrapper is + port ( + clk : in std_logic; + reset : in std_logic; + IR_start : in std_logic; + IR_bx_in : in std_logic_vector(2 downto 0); + TP_bx_out_0 : out std_logic_vector(2 downto 0); + TP_bx_out_vld : out std_logic; + TP_done : out std_logic; + DL_39_link_AV_dout : in t_arr_DL_39_DATA; + DL_39_link_empty_neg : in t_arr_DL_39_1b; + DL_39_link_read : out t_arr_DL_39_1b; + AS_37_stream_V_dout : out t_arr_AS_37_DATA; + MPAR_76_stream_V_dout : out t_arr_MPAR_76_DATA + ); +end entity tf1_wrapper; + +architecture rtl of tf1_wrapper is + +begin -- architecture rtl + + SectorProcessor_1 : entity work.SectorProcessor + port map ( + clk => clk, + reset => reset, + IR_start => IR_start, + IR_bx_in => IR_bx_in, + TP_bx_out => TP_bx_out_0, + TP_bx_out_vld => TP_bx_out_vld, + TP_done => TP_done, + DL_PS10G_1_A_link_AV_dout => DL_39_link_AV_dout(PS10G_1_A), + DL_PS10G_1_A_link_empty_neg => DL_39_link_empty_neg(PS10G_1_A), + DL_PS10G_1_A_link_read => DL_39_link_read(PS10G_1_A), + DL_PS10G_1_B_link_AV_dout => DL_39_link_AV_dout(PS10G_1_B), + DL_PS10G_1_B_link_empty_neg => DL_39_link_empty_neg(PS10G_1_B), + DL_PS10G_1_B_link_read => DL_39_link_read(PS10G_1_B), + DL_PS10G_2_A_link_AV_dout => DL_39_link_AV_dout(PS10G_2_A), + DL_PS10G_2_A_link_empty_neg => DL_39_link_empty_neg(PS10G_2_A), + DL_PS10G_2_A_link_read => DL_39_link_read(PS10G_2_A), + DL_PS10G_2_B_link_AV_dout => DL_39_link_AV_dout(PS10G_2_B), + DL_PS10G_2_B_link_empty_neg => DL_39_link_empty_neg(PS10G_2_B), + DL_PS10G_2_B_link_read => DL_39_link_read(PS10G_2_B), + DL_PS10G_3_A_link_AV_dout => DL_39_link_AV_dout(PS10G_3_A), + DL_PS10G_3_A_link_empty_neg => DL_39_link_empty_neg(PS10G_3_A), + DL_PS10G_3_A_link_read => DL_39_link_read(PS10G_3_A), + DL_PS10G_3_B_link_AV_dout => DL_39_link_AV_dout(PS10G_3_B), + DL_PS10G_3_B_link_empty_neg => DL_39_link_empty_neg(PS10G_3_B), + DL_PS10G_3_B_link_read => DL_39_link_read(PS10G_3_B), + DL_PS10G_4_A_link_AV_dout => DL_39_link_AV_dout(PS10G_4_A), + DL_PS10G_4_A_link_empty_neg => DL_39_link_empty_neg(PS10G_4_A), + DL_PS10G_4_A_link_read => DL_39_link_read(PS10G_4_A), + DL_PS10G_4_B_link_AV_dout => DL_39_link_AV_dout(PS10G_4_B), + DL_PS10G_4_B_link_empty_neg => DL_39_link_empty_neg(PS10G_4_B), + DL_PS10G_4_B_link_read => DL_39_link_read(PS10G_4_B), + DL_PS_1_A_link_AV_dout => DL_39_link_AV_dout(PS_1_A), + DL_PS_1_A_link_empty_neg => DL_39_link_empty_neg(PS_1_A), + DL_PS_1_A_link_read => DL_39_link_read(PS_1_A), + DL_PS_1_B_link_AV_dout => DL_39_link_AV_dout(PS_1_B), + DL_PS_1_B_link_empty_neg => DL_39_link_empty_neg(PS_1_B), + DL_PS_1_B_link_read => DL_39_link_read(PS_1_B), + DL_PS_2_A_link_AV_dout => DL_39_link_AV_dout(PS_2_A), + DL_PS_2_A_link_empty_neg => DL_39_link_empty_neg(PS_2_A), + DL_PS_2_A_link_read => DL_39_link_read(PS_2_A), + DL_PS_2_B_link_AV_dout => DL_39_link_AV_dout(PS_2_B), + DL_PS_2_B_link_empty_neg => DL_39_link_empty_neg(PS_2_B), + DL_PS_2_B_link_read => DL_39_link_read(PS_2_B), + DL_negPS10G_1_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_1_A), + DL_negPS10G_1_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_1_A), + DL_negPS10G_1_A_link_read => DL_39_link_read(negPS10G_1_A), + DL_negPS10G_1_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_1_B), + DL_negPS10G_1_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_1_B), + DL_negPS10G_1_B_link_read => DL_39_link_read(negPS10G_1_B), + DL_negPS10G_2_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_2_A), + DL_negPS10G_2_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_2_A), + DL_negPS10G_2_A_link_read => DL_39_link_read(negPS10G_2_A), + DL_negPS10G_2_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_2_B), + DL_negPS10G_2_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_2_B), + DL_negPS10G_2_B_link_read => DL_39_link_read(negPS10G_2_B), + DL_negPS10G_3_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_3_A), + DL_negPS10G_3_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_3_A), + DL_negPS10G_3_A_link_read => DL_39_link_read(negPS10G_3_A), + DL_negPS10G_3_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_3_B), + DL_negPS10G_3_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_3_B), + DL_negPS10G_3_B_link_read => DL_39_link_read(negPS10G_3_B), + DL_negPS10G_4_A_link_AV_dout => DL_39_link_AV_dout(negPS10G_4_A), + DL_negPS10G_4_A_link_empty_neg => DL_39_link_empty_neg(negPS10G_4_A), + DL_negPS10G_4_A_link_read => DL_39_link_read(negPS10G_4_A), + DL_negPS10G_4_B_link_AV_dout => DL_39_link_AV_dout(negPS10G_4_B), + DL_negPS10G_4_B_link_empty_neg => DL_39_link_empty_neg(negPS10G_4_B), + DL_negPS10G_4_B_link_read => DL_39_link_read(negPS10G_4_B), + DL_negPS_1_A_link_AV_dout => DL_39_link_AV_dout(negPS_1_A), + DL_negPS_1_A_link_empty_neg => DL_39_link_empty_neg(negPS_1_A), + DL_negPS_1_A_link_read => DL_39_link_read(negPS_1_A), + DL_negPS_1_B_link_AV_dout => DL_39_link_AV_dout(negPS_1_B), + DL_negPS_1_B_link_empty_neg => DL_39_link_empty_neg(negPS_1_B), + DL_negPS_1_B_link_read => DL_39_link_read(negPS_1_B), + DL_negPS_2_A_link_AV_dout => DL_39_link_AV_dout(negPS_2_A), + DL_negPS_2_A_link_empty_neg => DL_39_link_empty_neg(negPS_2_A), + DL_negPS_2_A_link_read => DL_39_link_read(negPS_2_A), + DL_negPS_2_B_link_AV_dout => DL_39_link_AV_dout(negPS_2_B), + DL_negPS_2_B_link_empty_neg => DL_39_link_empty_neg(negPS_2_B), + DL_negPS_2_B_link_read => DL_39_link_read(negPS_2_B), + DL_twoS_1_A_link_AV_dout => DL_39_link_AV_dout(twoS_1_A), + DL_twoS_1_A_link_empty_neg => DL_39_link_empty_neg(twoS_1_A), + DL_twoS_1_A_link_read => DL_39_link_read(twoS_1_A), + DL_twoS_1_B_link_AV_dout => DL_39_link_AV_dout(twoS_1_B), + DL_twoS_1_B_link_empty_neg => DL_39_link_empty_neg(twoS_1_B), + DL_twoS_1_B_link_read => DL_39_link_read(twoS_1_B), + DL_twoS_2_A_link_AV_dout => DL_39_link_AV_dout(twoS_2_A), + DL_twoS_2_A_link_empty_neg => DL_39_link_empty_neg(twoS_2_A), + DL_twoS_2_A_link_read => DL_39_link_read(twoS_2_A), + DL_twoS_2_B_link_AV_dout => DL_39_link_AV_dout(twoS_2_B), + DL_twoS_2_B_link_empty_neg => DL_39_link_empty_neg(twoS_2_B), + DL_twoS_2_B_link_read => DL_39_link_read(twoS_2_B), + DL_twoS_3_A_link_AV_dout => DL_39_link_AV_dout(twoS_3_A), + DL_twoS_3_A_link_empty_neg => DL_39_link_empty_neg(twoS_3_A), + DL_twoS_3_A_link_read => DL_39_link_read(twoS_3_A), + DL_twoS_3_B_link_AV_dout => DL_39_link_AV_dout(twoS_3_B), + DL_twoS_3_B_link_empty_neg => DL_39_link_empty_neg(twoS_3_B), + DL_twoS_3_B_link_read => DL_39_link_read(twoS_3_B), + DL_twoS_4_A_link_AV_dout => DL_39_link_AV_dout(twoS_4_A), + DL_twoS_4_A_link_empty_neg => DL_39_link_empty_neg(twoS_4_A), + DL_twoS_4_A_link_read => DL_39_link_read(twoS_4_A), + DL_twoS_4_B_link_AV_dout => DL_39_link_AV_dout(twoS_4_B), + DL_twoS_4_B_link_empty_neg => DL_39_link_empty_neg(twoS_4_B), + DL_twoS_4_B_link_read => DL_39_link_read(twoS_4_B), + DL_twoS_5_A_link_AV_dout => DL_39_link_AV_dout(twoS_5_A), + DL_twoS_5_A_link_empty_neg => DL_39_link_empty_neg(twoS_5_A), + DL_twoS_5_A_link_read => DL_39_link_read(twoS_5_A), + DL_twoS_5_B_link_AV_dout => DL_39_link_AV_dout(twoS_5_B), + DL_twoS_5_B_link_empty_neg => DL_39_link_empty_neg(twoS_5_B), + DL_twoS_5_B_link_read => DL_39_link_read(twoS_5_B), + DL_twoS_6_A_link_AV_dout => DL_39_link_AV_dout(twoS_6_A), + DL_twoS_6_A_link_empty_neg => DL_39_link_empty_neg(twoS_6_A), + DL_twoS_6_A_link_read => DL_39_link_read(twoS_6_A), + DL_twoS_6_B_link_AV_dout => DL_39_link_AV_dout(twoS_6_B), + DL_twoS_6_B_link_empty_neg => DL_39_link_empty_neg(twoS_6_B), + DL_twoS_6_B_link_read => DL_39_link_read(twoS_6_B), + DL_neg2S_1_A_link_AV_dout => DL_39_link_AV_dout(neg2S_1_A), + DL_neg2S_1_A_link_empty_neg => DL_39_link_empty_neg(neg2S_1_A), + DL_neg2S_1_A_link_read => DL_39_link_read(neg2S_1_A), + DL_neg2S_1_B_link_AV_dout => DL_39_link_AV_dout(neg2S_1_B), + DL_neg2S_1_B_link_empty_neg => DL_39_link_empty_neg(neg2S_1_B), + DL_neg2S_1_B_link_read => DL_39_link_read(neg2S_1_B), + DL_neg2S_2_A_link_AV_dout => DL_39_link_AV_dout(neg2S_2_A), + DL_neg2S_2_A_link_empty_neg => DL_39_link_empty_neg(neg2S_2_A), + DL_neg2S_2_A_link_read => DL_39_link_read(neg2S_2_A), + DL_neg2S_2_B_link_AV_dout => DL_39_link_AV_dout(neg2S_2_B), + DL_neg2S_2_B_link_empty_neg => DL_39_link_empty_neg(neg2S_2_B), + DL_neg2S_2_B_link_read => DL_39_link_read(neg2S_2_B), + DL_neg2S_3_A_link_AV_dout => DL_39_link_AV_dout(neg2S_3_A), + DL_neg2S_3_A_link_empty_neg => DL_39_link_empty_neg(neg2S_3_A), + DL_neg2S_3_A_link_read => DL_39_link_read(neg2S_3_A), + DL_neg2S_3_B_link_AV_dout => DL_39_link_AV_dout(neg2S_3_B), + DL_neg2S_3_B_link_empty_neg => DL_39_link_empty_neg(neg2S_3_B), + DL_neg2S_3_B_link_read => DL_39_link_read(neg2S_3_B), + DL_neg2S_4_A_link_AV_dout => DL_39_link_AV_dout(neg2S_4_A), + DL_neg2S_4_A_link_empty_neg => DL_39_link_empty_neg(neg2S_4_A), + DL_neg2S_4_A_link_read => DL_39_link_read(neg2S_4_A), + DL_neg2S_4_B_link_AV_dout => DL_39_link_AV_dout(neg2S_4_B), + DL_neg2S_4_B_link_empty_neg => DL_39_link_empty_neg(neg2S_4_B), + DL_neg2S_4_B_link_read => DL_39_link_read(neg2S_4_B), + DL_neg2S_5_A_link_AV_dout => DL_39_link_AV_dout(neg2S_5_A), + DL_neg2S_5_A_link_empty_neg => DL_39_link_empty_neg(neg2S_5_A), + DL_neg2S_5_A_link_read => DL_39_link_read(neg2S_5_A), + DL_neg2S_5_B_link_AV_dout => DL_39_link_AV_dout(neg2S_5_B), + DL_neg2S_5_B_link_empty_neg => DL_39_link_empty_neg(neg2S_5_B), + DL_neg2S_5_B_link_read => DL_39_link_read(neg2S_5_B), + DL_neg2S_6_A_link_AV_dout => DL_39_link_AV_dout(neg2S_6_A), + DL_neg2S_6_A_link_empty_neg => DL_39_link_empty_neg(neg2S_6_A), + DL_neg2S_6_A_link_read => DL_39_link_read(neg2S_6_A), + DL_neg2S_6_B_link_AV_dout => DL_39_link_AV_dout(neg2S_6_B), + DL_neg2S_6_B_link_empty_neg => DL_39_link_empty_neg(neg2S_6_B), + DL_neg2S_6_B_link_read => DL_39_link_read(neg2S_6_B), + AS_L1PHIAn1_stream_V_dout => AS_37_stream_V_dout(L1PHIAn1), + AS_L1PHIBn1_stream_V_dout => AS_37_stream_V_dout(L1PHIBn1), + AS_L1PHICn1_stream_V_dout => AS_37_stream_V_dout(L1PHICn1), + AS_L1PHIDn1_stream_V_dout => AS_37_stream_V_dout(L1PHIDn1), + AS_L1PHIEn1_stream_V_dout => AS_37_stream_V_dout(L1PHIEn1), + AS_L1PHIFn1_stream_V_dout => AS_37_stream_V_dout(L1PHIFn1), + AS_L1PHIGn1_stream_V_dout => AS_37_stream_V_dout(L1PHIGn1), + AS_L1PHIHn1_stream_V_dout => AS_37_stream_V_dout(L1PHIHn1), + AS_L2PHIAn1_stream_V_dout => AS_37_stream_V_dout(L2PHIAn1), + AS_L2PHIBn1_stream_V_dout => AS_37_stream_V_dout(L2PHIBn1), + AS_L2PHICn1_stream_V_dout => AS_37_stream_V_dout(L2PHICn1), + AS_L2PHIDn1_stream_V_dout => AS_37_stream_V_dout(L2PHIDn1), + AS_L3PHIAn1_stream_V_dout => AS_37_stream_V_dout(L3PHIAn1), + AS_L3PHIBn1_stream_V_dout => AS_37_stream_V_dout(L3PHIBn1), + AS_L3PHICn1_stream_V_dout => AS_37_stream_V_dout(L3PHICn1), + AS_L3PHIDn1_stream_V_dout => AS_37_stream_V_dout(L3PHIDn1), + AS_L4PHIAn1_stream_V_dout => AS_37_stream_V_dout(L4PHIAn1), + AS_L4PHIBn1_stream_V_dout => AS_37_stream_V_dout(L4PHIBn1), + AS_L4PHICn1_stream_V_dout => AS_37_stream_V_dout(L4PHICn1), + AS_L4PHIDn1_stream_V_dout => AS_37_stream_V_dout(L4PHIDn1), + AS_L5PHIAn1_stream_V_dout => AS_37_stream_V_dout(L5PHIAn1), + AS_L5PHIBn1_stream_V_dout => AS_37_stream_V_dout(L5PHIBn1), + AS_L5PHICn1_stream_V_dout => AS_37_stream_V_dout(L5PHICn1), + AS_L5PHIDn1_stream_V_dout => AS_37_stream_V_dout(L5PHIDn1), + AS_L6PHIAn1_stream_V_dout => AS_37_stream_V_dout(L6PHIAn1), + AS_L6PHIBn1_stream_V_dout => AS_37_stream_V_dout(L6PHIBn1), + AS_L6PHICn1_stream_V_dout => AS_37_stream_V_dout(L6PHICn1), + AS_L6PHIDn1_stream_V_dout => AS_37_stream_V_dout(L6PHIDn1), + AS_D1PHIAn1_stream_V_dout => AS_37_stream_V_dout(D1PHIAn1), + AS_D1PHIBn1_stream_V_dout => AS_37_stream_V_dout(D1PHIBn1), + AS_D1PHICn1_stream_V_dout => AS_37_stream_V_dout(D1PHICn1), + AS_D1PHIDn1_stream_V_dout => AS_37_stream_V_dout(D1PHIDn1), + AS_D2PHIAn1_stream_V_dout => AS_37_stream_V_dout(D2PHIAn1), + AS_D2PHIBn1_stream_V_dout => AS_37_stream_V_dout(D2PHIBn1), + AS_D2PHICn1_stream_V_dout => AS_37_stream_V_dout(D2PHICn1), + AS_D2PHIDn1_stream_V_dout => AS_37_stream_V_dout(D2PHIDn1), + AS_D3PHIAn1_stream_V_dout => AS_37_stream_V_dout(D3PHIAn1), + AS_D3PHIBn1_stream_V_dout => AS_37_stream_V_dout(D3PHIBn1), + AS_D3PHICn1_stream_V_dout => AS_37_stream_V_dout(D3PHICn1), + AS_D3PHIDn1_stream_V_dout => AS_37_stream_V_dout(D3PHIDn1), + AS_D4PHIAn1_stream_V_dout => AS_37_stream_V_dout(D4PHIAn1), + AS_D4PHIBn1_stream_V_dout => AS_37_stream_V_dout(D4PHIBn1), + AS_D4PHICn1_stream_V_dout => AS_37_stream_V_dout(D4PHICn1), + AS_D4PHIDn1_stream_V_dout => AS_37_stream_V_dout(D4PHIDn1), + AS_D5PHIAn1_stream_V_dout => AS_37_stream_V_dout(D5PHIAn1), + AS_D5PHIBn1_stream_V_dout => AS_37_stream_V_dout(D5PHIBn1), + AS_D5PHICn1_stream_V_dout => AS_37_stream_V_dout(D5PHICn1), + AS_D5PHIDn1_stream_V_dout => AS_37_stream_V_dout(D5PHIDn1), + MPAR_L1L2ABC_stream_V_dout => MPAR_76_stream_V_dout(L1L2ABC), + MPAR_L1L2DE_stream_V_dout => MPAR_76_stream_V_dout(L1L2DE), + MPAR_L1L2F_stream_V_dout => MPAR_76_stream_V_dout(L1L2F), + MPAR_L1L2G_stream_V_dout => MPAR_76_stream_V_dout(L1L2G), + MPAR_L1L2HI_stream_V_dout => MPAR_76_stream_V_dout(L1L2HI), + MPAR_L1L2JKL_stream_V_dout => MPAR_76_stream_V_dout(L1L2JKL), + MPAR_L2L3ABCD_stream_V_dout => MPAR_76_stream_V_dout(L2L3ABCD), + MPAR_L3L4AB_stream_V_dout => MPAR_76_stream_V_dout(L3L4AB), + MPAR_L3L4CD_stream_V_dout => MPAR_76_stream_V_dout(L3L4CD), + MPAR_L5L6ABCD_stream_V_dout => MPAR_76_stream_V_dout(L5L6ABCD), + MPAR_D1D2ABCD_stream_V_dout => MPAR_76_stream_V_dout(D1D2ABCD), + MPAR_D3D4ABCD_stream_V_dout => MPAR_76_stream_V_dout(D3D4ABCD), + MPAR_L1D1ABCD_stream_V_dout => MPAR_76_stream_V_dout(L1D1ABCD), + MPAR_L1D1EFGH_stream_V_dout => MPAR_76_stream_V_dout(L1D1EFGH), + MPAR_L2D1ABCD_stream_V_dout => MPAR_76_stream_V_dout(L2D1ABCD) + ); + +end architecture rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd new file mode 100644 index 00000000000..a6fd7fac4f7 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd @@ -0,0 +1,432 @@ +------------------------------------------------------------------------------- +-- Title : tf wrapper +-- Project : +------------------------------------------------------------------------------- +-- File : tf_wrapper.vhd +-- Author : Michael Oshiro +-- Company : Cornell University +-- Created : 2024-01-19 +-- Last update: 2024-01-19 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: Simple module to pack/unpack SectorProcessor inputs into vectors +------------------------------------------------------------------------------- +-- Copyright (c) 2024 Cornell University +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2022-01-19 1.0 oshiro Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f2.all; + +entity tf2_wrapper is + port ( + clk : in std_logic; + reset : in std_logic; + PC_start : in std_logic; + PC_bx_in : in std_logic_vector(2 downto 0); + PC_bx_out : out std_logic_vector(2 downto 0); + PC_bx_out_vld : out std_logic; + PC_done : out std_logic; + FT_bx_out : out std_logic_vector(2 downto 0); + FT_bx_out_vld : out std_logic; + FT_done : out std_logic; + FT_last_track : out std_logic; + FT_last_track_vld : out std_logic; + AS_36_wea : in t_arr_AS_36_1b; + AS_36_writeaddr : in t_arr_AS_36_ADDR; + AS_36_din : in t_arr_AS_36_DATA; + MPAR_73_wea : in t_arr_MTPAR_73_1b; + MPAR_73_writeaddr : in t_arr_MTPAR_73_ADDR; + MPAR_73_din : in t_arr_MTPAR_73_DATA; + TW_104_stream_AV_din : out t_arr_TW_104_DATA; + TW_104_stream_A_full_neg : in t_arr_TW_104_1b; + TW_104_stream_A_write : out t_arr_TW_104_1b; + DW_49_stream_AV_din : out t_arr_DW_49_DATA; + DW_49_stream_A_full_neg : in t_arr_DW_49_1b; + DW_49_stream_A_write : out t_arr_DW_49_1b; + BW_46_stream_AV_din : out t_arr_BW_46_DATA; + BW_46_stream_A_full_neg : in t_arr_BW_46_1b; + BW_46_stream_A_write : out t_arr_BW_46_1b + ); +end entity tf2_wrapper; + +architecture rtl of tf2_wrapper is + +begin -- architecture rtl + + SectorProcessor_1 : entity work.SectorProcessor + port map ( + clk => clk, + reset => reset, + PC_start => PC_start, + PC_bx_in => PC_bx_in, + PC_bx_out => PC_bx_out, + PC_bx_out_vld => PC_bx_out_vld, + PC_done => PC_done, + FT_bx_out => FT_bx_out, + FT_bx_out_vld => FT_bx_out_vld, + FT_done => FT_done, + FT_L1L2_last_track => FT_last_track, + FT_L1L2_last_track_vld => FT_last_track_vld, + FT_L2L3_last_track => open, + FT_L2L3_last_track_vld => open, + FT_L3L4_last_track => open, + FT_L3L4_last_track_vld => open, + FT_L5L6_last_track => open, + FT_L5L6_last_track_vld => open, + FT_D1D2_last_track => open, + FT_D1D2_last_track_vld => open, + FT_D3D4_last_track => open, + FT_D3D4_last_track_vld => open, + FT_L1D1_last_track => open, + FT_L1D1_last_track_vld => open, + FT_L2D1_last_track => open, + FT_L2D1_last_track_vld => open, + AS_L1PHIAin_wea => AS_36_wea(L1PHIAn1), + AS_L1PHIAin_writeaddr => AS_36_writeaddr(L1PHIAn1), + AS_L1PHIAin_din => AS_36_din(L1PHIAn1), + AS_L1PHIBin_wea => AS_36_wea(L1PHIBn1), + AS_L1PHIBin_writeaddr => AS_36_writeaddr(L1PHIBn1), + AS_L1PHIBin_din => AS_36_din(L1PHIBn1), + AS_L1PHICin_wea => AS_36_wea(L1PHICn1), + AS_L1PHICin_writeaddr => AS_36_writeaddr(L1PHICn1), + AS_L1PHICin_din => AS_36_din(L1PHICn1), + AS_L1PHIDin_wea => AS_36_wea(L1PHIDn1), + AS_L1PHIDin_writeaddr => AS_36_writeaddr(L1PHIDn1), + AS_L1PHIDin_din => AS_36_din(L1PHIDn1), + AS_L1PHIEin_wea => AS_36_wea(L1PHIEn1), + AS_L1PHIEin_writeaddr => AS_36_writeaddr(L1PHIEn1), + AS_L1PHIEin_din => AS_36_din(L1PHIEn1), + AS_L1PHIFin_wea => AS_36_wea(L1PHIFn1), + AS_L1PHIFin_writeaddr => AS_36_writeaddr(L1PHIFn1), + AS_L1PHIFin_din => AS_36_din(L1PHIFn1), + AS_L1PHIGin_wea => AS_36_wea(L1PHIGn1), + AS_L1PHIGin_writeaddr => AS_36_writeaddr(L1PHIGn1), + AS_L1PHIGin_din => AS_36_din(L1PHIGn1), + AS_L1PHIHin_wea => AS_36_wea(L1PHIHn1), + AS_L1PHIHin_writeaddr => AS_36_writeaddr(L1PHIHn1), + AS_L1PHIHin_din => AS_36_din(L1PHIHn1), + AS_L2PHIAin_wea => AS_36_wea(L2PHIAn1), + AS_L2PHIAin_writeaddr => AS_36_writeaddr(L2PHIAn1), + AS_L2PHIAin_din => AS_36_din(L2PHIAn1), + AS_L2PHIBin_wea => AS_36_wea(L2PHIBn1), + AS_L2PHIBin_writeaddr => AS_36_writeaddr(L2PHIBn1), + AS_L2PHIBin_din => AS_36_din(L2PHIBn1), + AS_L2PHICin_wea => AS_36_wea(L2PHICn1), + AS_L2PHICin_writeaddr => AS_36_writeaddr(L2PHICn1), + AS_L2PHICin_din => AS_36_din(L2PHICn1), + AS_L2PHIDin_wea => AS_36_wea(L2PHIDn1), + AS_L2PHIDin_writeaddr => AS_36_writeaddr(L2PHIDn1), + AS_L2PHIDin_din => AS_36_din(L2PHIDn1), + AS_L3PHIAin_wea => AS_36_wea(L3PHIAn1), + AS_L3PHIAin_writeaddr => AS_36_writeaddr(L3PHIAn1), + AS_L3PHIAin_din => AS_36_din(L3PHIAn1), + AS_L3PHIBin_wea => AS_36_wea(L3PHIBn1), + AS_L3PHIBin_writeaddr => AS_36_writeaddr(L3PHIBn1), + AS_L3PHIBin_din => AS_36_din(L3PHIBn1), + AS_L3PHICin_wea => AS_36_wea(L3PHICn1), + AS_L3PHICin_writeaddr => AS_36_writeaddr(L3PHICn1), + AS_L3PHICin_din => AS_36_din(L3PHICn1), + AS_L3PHIDin_wea => AS_36_wea(L3PHIDn1), + AS_L3PHIDin_writeaddr => AS_36_writeaddr(L3PHIDn1), + AS_L3PHIDin_din => AS_36_din(L3PHIDn1), + AS_L4PHIAin_wea => AS_36_wea(L4PHIAn1), + AS_L4PHIAin_writeaddr => AS_36_writeaddr(L4PHIAn1), + AS_L4PHIAin_din => AS_36_din(L4PHIAn1), + AS_L4PHIBin_wea => AS_36_wea(L4PHIBn1), + AS_L4PHIBin_writeaddr => AS_36_writeaddr(L4PHIBn1), + AS_L4PHIBin_din => AS_36_din(L4PHIBn1), + AS_L4PHICin_wea => AS_36_wea(L4PHICn1), + AS_L4PHICin_writeaddr => AS_36_writeaddr(L4PHICn1), + AS_L4PHICin_din => AS_36_din(L4PHICn1), + AS_L4PHIDin_wea => AS_36_wea(L4PHIDn1), + AS_L4PHIDin_writeaddr => AS_36_writeaddr(L4PHIDn1), + AS_L4PHIDin_din => AS_36_din(L4PHIDn1), + AS_L5PHIAin_wea => AS_36_wea(L5PHIAn1), + AS_L5PHIAin_writeaddr => AS_36_writeaddr(L5PHIAn1), + AS_L5PHIAin_din => AS_36_din(L5PHIAn1), + AS_L5PHIBin_wea => AS_36_wea(L5PHIBn1), + AS_L5PHIBin_writeaddr => AS_36_writeaddr(L5PHIBn1), + AS_L5PHIBin_din => AS_36_din(L5PHIBn1), + AS_L5PHICin_wea => AS_36_wea(L5PHICn1), + AS_L5PHICin_writeaddr => AS_36_writeaddr(L5PHICn1), + AS_L5PHICin_din => AS_36_din(L5PHICn1), + AS_L5PHIDin_wea => AS_36_wea(L5PHIDn1), + AS_L5PHIDin_writeaddr => AS_36_writeaddr(L5PHIDn1), + AS_L5PHIDin_din => AS_36_din(L5PHIDn1), + AS_L6PHIAin_wea => AS_36_wea(L6PHIAn1), + AS_L6PHIAin_writeaddr => AS_36_writeaddr(L6PHIAn1), + AS_L6PHIAin_din => AS_36_din(L6PHIAn1), + AS_L6PHIBin_wea => AS_36_wea(L6PHIBn1), + AS_L6PHIBin_writeaddr => AS_36_writeaddr(L6PHIBn1), + AS_L6PHIBin_din => AS_36_din(L6PHIBn1), + AS_L6PHICin_wea => AS_36_wea(L6PHICn1), + AS_L6PHICin_writeaddr => AS_36_writeaddr(L6PHICn1), + AS_L6PHICin_din => AS_36_din(L6PHICn1), + AS_L6PHIDin_wea => AS_36_wea(L6PHIDn1), + AS_L6PHIDin_writeaddr => AS_36_writeaddr(L6PHIDn1), + AS_L6PHIDin_din => AS_36_din(L6PHIDn1), + AS_D1PHIAin_wea => AS_36_wea(D1PHIAn1), + AS_D1PHIAin_writeaddr => AS_36_writeaddr(D1PHIAn1), + AS_D1PHIAin_din => AS_36_din(D1PHIAn1), + AS_D1PHIBin_wea => AS_36_wea(D1PHIBn1), + AS_D1PHIBin_writeaddr => AS_36_writeaddr(D1PHIBn1), + AS_D1PHIBin_din => AS_36_din(D1PHIBn1), + AS_D1PHICin_wea => AS_36_wea(D1PHICn1), + AS_D1PHICin_writeaddr => AS_36_writeaddr(D1PHICn1), + AS_D1PHICin_din => AS_36_din(D1PHICn1), + AS_D1PHIDin_wea => AS_36_wea(D1PHIDn1), + AS_D1PHIDin_writeaddr => AS_36_writeaddr(D1PHIDn1), + AS_D1PHIDin_din => AS_36_din(D1PHIDn1), + AS_D2PHIAin_wea => AS_36_wea(D2PHIAn1), + AS_D2PHIAin_writeaddr => AS_36_writeaddr(D2PHIAn1), + AS_D2PHIAin_din => AS_36_din(D2PHIAn1), + AS_D2PHIBin_wea => AS_36_wea(D2PHIBn1), + AS_D2PHIBin_writeaddr => AS_36_writeaddr(D2PHIBn1), + AS_D2PHIBin_din => AS_36_din(D2PHIBn1), + AS_D2PHICin_wea => AS_36_wea(D2PHICn1), + AS_D2PHICin_writeaddr => AS_36_writeaddr(D2PHICn1), + AS_D2PHICin_din => AS_36_din(D2PHICn1), + AS_D2PHIDin_wea => AS_36_wea(D2PHIDn1), + AS_D2PHIDin_writeaddr => AS_36_writeaddr(D2PHIDn1), + AS_D2PHIDin_din => AS_36_din(D2PHIDn1), + AS_D3PHIAin_wea => AS_36_wea(D3PHIAn1), + AS_D3PHIAin_writeaddr => AS_36_writeaddr(D3PHIAn1), + AS_D3PHIAin_din => AS_36_din(D3PHIAn1), + AS_D3PHIBin_wea => AS_36_wea(D3PHIBn1), + AS_D3PHIBin_writeaddr => AS_36_writeaddr(D3PHIBn1), + AS_D3PHIBin_din => AS_36_din(D3PHIBn1), + AS_D3PHICin_wea => AS_36_wea(D3PHICn1), + AS_D3PHICin_writeaddr => AS_36_writeaddr(D3PHICn1), + AS_D3PHICin_din => AS_36_din(D3PHICn1), + AS_D3PHIDin_wea => AS_36_wea(D3PHIDn1), + AS_D3PHIDin_writeaddr => AS_36_writeaddr(D3PHIDn1), + AS_D3PHIDin_din => AS_36_din(D3PHIDn1), + AS_D4PHIAin_wea => AS_36_wea(D4PHIAn1), + AS_D4PHIAin_writeaddr => AS_36_writeaddr(D4PHIAn1), + AS_D4PHIAin_din => AS_36_din(D4PHIAn1), + AS_D4PHIBin_wea => AS_36_wea(D4PHIBn1), + AS_D4PHIBin_writeaddr => AS_36_writeaddr(D4PHIBn1), + AS_D4PHIBin_din => AS_36_din(D4PHIBn1), + AS_D4PHICin_wea => AS_36_wea(D4PHICn1), + AS_D4PHICin_writeaddr => AS_36_writeaddr(D4PHICn1), + AS_D4PHICin_din => AS_36_din(D4PHICn1), + AS_D4PHIDin_wea => AS_36_wea(D4PHIDn1), + AS_D4PHIDin_writeaddr => AS_36_writeaddr(D4PHIDn1), + AS_D4PHIDin_din => AS_36_din(D4PHIDn1), + AS_D5PHIAin_wea => AS_36_wea(D5PHIAn1), + AS_D5PHIAin_writeaddr => AS_36_writeaddr(D5PHIAn1), + AS_D5PHIAin_din => AS_36_din(D5PHIAn1), + AS_D5PHIBin_wea => AS_36_wea(D5PHIBn1), + AS_D5PHIBin_writeaddr => AS_36_writeaddr(D5PHIBn1), + AS_D5PHIBin_din => AS_36_din(D5PHIBn1), + AS_D5PHICin_wea => AS_36_wea(D5PHICn1), + AS_D5PHICin_writeaddr => AS_36_writeaddr(D5PHICn1), + AS_D5PHICin_din => AS_36_din(D5PHICn1), + AS_D5PHIDin_wea => AS_36_wea(D5PHIDn1), + AS_D5PHIDin_writeaddr => AS_36_writeaddr(D5PHIDn1), + AS_D5PHIDin_din => AS_36_din(D5PHIDn1), + MPAR_L1L2ABCin_wea => MPAR_73_wea(L1L2ABC), + MPAR_L1L2ABCin_writeaddr => MPAR_73_writeaddr(L1L2ABC), + MPAR_L1L2ABCin_din => MPAR_73_din(L1L2ABC), + MPAR_L1L2DEin_wea => MPAR_73_wea(L1L2DE), + MPAR_L1L2DEin_writeaddr => MPAR_73_writeaddr(L1L2DE), + MPAR_L1L2DEin_din => MPAR_73_din(L1L2DE), + MPAR_L1L2Fin_wea => MPAR_73_wea(L1L2F), + MPAR_L1L2Fin_writeaddr => MPAR_73_writeaddr(L1L2F), + MPAR_L1L2Fin_din => MPAR_73_din(L1L2F), + MPAR_L1L2Gin_wea => MPAR_73_wea(L1L2G), + MPAR_L1L2Gin_writeaddr => MPAR_73_writeaddr(L1L2G), + MPAR_L1L2Gin_din => MPAR_73_din(L1L2G), + MPAR_L1L2HIin_wea => MPAR_73_wea(L1L2HI), + MPAR_L1L2HIin_writeaddr => MPAR_73_writeaddr(L1L2HI), + MPAR_L1L2HIin_din => MPAR_73_din(L1L2HI), + MPAR_L1L2JKLin_wea => MPAR_73_wea(L1L2JKL), + MPAR_L1L2JKLin_writeaddr => MPAR_73_writeaddr(L1L2JKL), + MPAR_L1L2JKLin_din => MPAR_73_din(L1L2JKL), + MPAR_L2L3ABCDin_wea => MPAR_73_wea(L2L3ABCD), + MPAR_L2L3ABCDin_writeaddr => MPAR_73_writeaddr(L2L3ABCD), + MPAR_L2L3ABCDin_din => MPAR_73_din(L2L3ABCD), + MPAR_L3L4ABin_wea => MPAR_73_wea(L3L4AB), + MPAR_L3L4ABin_writeaddr => MPAR_73_writeaddr(L3L4AB), + MPAR_L3L4ABin_din => MPAR_73_din(L3L4AB), + MPAR_L3L4CDin_wea => MPAR_73_wea(L3L4CD), + MPAR_L3L4CDin_writeaddr => MPAR_73_writeaddr(L3L4CD), + MPAR_L3L4CDin_din => MPAR_73_din(L3L4CD), + MPAR_L5L6ABCDin_wea => MPAR_73_wea(L5L6ABCD), + MPAR_L5L6ABCDin_writeaddr => MPAR_73_writeaddr(L5L6ABCD), + MPAR_L5L6ABCDin_din => MPAR_73_din(L5L6ABCD), + MPAR_D1D2ABCDin_wea => MPAR_73_wea(D1D2ABCD), + MPAR_D1D2ABCDin_writeaddr => MPAR_73_writeaddr(D1D2ABCD), + MPAR_D1D2ABCDin_din => MPAR_73_din(D1D2ABCD), + MPAR_D3D4ABCDin_wea => MPAR_73_wea(D3D4ABCD), + MPAR_D3D4ABCDin_writeaddr => MPAR_73_writeaddr(D3D4ABCD), + MPAR_D3D4ABCDin_din => MPAR_73_din(D3D4ABCD), + MPAR_L1D1ABCDin_wea => MPAR_73_wea(L1D1ABCD), + MPAR_L1D1ABCDin_writeaddr => MPAR_73_writeaddr(L1D1ABCD), + MPAR_L1D1ABCDin_din => MPAR_73_din(L1D1ABCD), + MPAR_L1D1EFGHin_wea => MPAR_73_wea(L1D1EFGH), + MPAR_L1D1EFGHin_writeaddr => MPAR_73_writeaddr(L1D1EFGH), + MPAR_L1D1EFGHin_din => MPAR_73_din(L1D1EFGH), + MPAR_L2D1ABCDin_wea => MPAR_73_wea(L2D1ABCD), + MPAR_L2D1ABCDin_writeaddr => MPAR_73_writeaddr(L2D1ABCD), + MPAR_L2D1ABCDin_din => MPAR_73_din(L2D1ABCD), + TW_L1L2_stream_AV_din => TW_104_stream_AV_din(L1L2), + TW_L1L2_stream_A_full_neg => TW_104_stream_A_full_neg(L1L2), + TW_L1L2_stream_A_write => TW_104_stream_A_write(L1L2), + TW_L2L3_stream_AV_din => TW_104_stream_AV_din(L2L3), + TW_L2L3_stream_A_full_neg => TW_104_stream_A_full_neg(L2L3), + TW_L2L3_stream_A_write => TW_104_stream_A_write(L2L3), + TW_L3L4_stream_AV_din => TW_104_stream_AV_din(L3L4), + TW_L3L4_stream_A_full_neg => TW_104_stream_A_full_neg(L3L4), + TW_L3L4_stream_A_write => TW_104_stream_A_write(L3L4), + TW_L5L6_stream_AV_din => TW_104_stream_AV_din(L5L6), + TW_L5L6_stream_A_full_neg => TW_104_stream_A_full_neg(L5L6), + TW_L5L6_stream_A_write => TW_104_stream_A_write(L5L6), + TW_D1D2_stream_AV_din => TW_104_stream_AV_din(D1D2), + TW_D1D2_stream_A_full_neg => TW_104_stream_A_full_neg(D1D2), + TW_D1D2_stream_A_write => TW_104_stream_A_write(D1D2), + TW_D3D4_stream_AV_din => TW_104_stream_AV_din(D3D4), + TW_D3D4_stream_A_full_neg => TW_104_stream_A_full_neg(D3D4), + TW_D3D4_stream_A_write => TW_104_stream_A_write(D3D4), + TW_L1D1_stream_AV_din => TW_104_stream_AV_din(L1D1), + TW_L1D1_stream_A_full_neg => TW_104_stream_A_full_neg(L1D1), + TW_L1D1_stream_A_write => TW_104_stream_A_write(L1D1), + TW_L2D1_stream_AV_din => TW_104_stream_AV_din(L2D1), + TW_L2D1_stream_A_full_neg => TW_104_stream_A_full_neg(L2D1), + TW_L2D1_stream_A_write => TW_104_stream_A_write(L2D1), + DW_L1L2_D1_stream_AV_din => DW_49_stream_AV_din(L1L2_D1), + DW_L1L2_D1_stream_A_full_neg => DW_49_stream_A_full_neg(L1L2_D1), + DW_L1L2_D1_stream_A_write => DW_49_stream_A_write(L1L2_D1), + DW_L1L2_D2_stream_AV_din => DW_49_stream_AV_din(L1L2_D2), + DW_L1L2_D2_stream_A_full_neg => DW_49_stream_A_full_neg(L1L2_D2), + DW_L1L2_D2_stream_A_write => DW_49_stream_A_write(L1L2_D2), + DW_L1L2_D3_stream_AV_din => DW_49_stream_AV_din(L1L2_D3), + DW_L1L2_D3_stream_A_full_neg => DW_49_stream_A_full_neg(L1L2_D3), + DW_L1L2_D3_stream_A_write => DW_49_stream_A_write(L1L2_D3), + DW_L1L2_D4_stream_AV_din => DW_49_stream_AV_din(L1L2_D4), + DW_L1L2_D4_stream_A_full_neg => DW_49_stream_A_full_neg(L1L2_D4), + DW_L1L2_D4_stream_A_write => DW_49_stream_A_write(L1L2_D4), + DW_L2L3_D1_stream_AV_din => DW_49_stream_AV_din(L2L3_D1), + DW_L2L3_D1_stream_A_full_neg => DW_49_stream_A_full_neg(L2L3_D1), + DW_L2L3_D1_stream_A_write => DW_49_stream_A_write(L2L3_D1), + DW_L2L3_D2_stream_AV_din => DW_49_stream_AV_din(L2L3_D2), + DW_L2L3_D2_stream_A_full_neg => DW_49_stream_A_full_neg(L2L3_D2), + DW_L2L3_D2_stream_A_write => DW_49_stream_A_write(L2L3_D2), + DW_L2L3_D3_stream_AV_din => DW_49_stream_AV_din(L2L3_D3), + DW_L2L3_D3_stream_A_full_neg => DW_49_stream_A_full_neg(L2L3_D3), + DW_L2L3_D3_stream_A_write => DW_49_stream_A_write(L2L3_D3), + DW_L2L3_D4_stream_AV_din => DW_49_stream_AV_din(L2L3_D4), + DW_L2L3_D4_stream_A_full_neg => DW_49_stream_A_full_neg(L2L3_D4), + DW_L2L3_D4_stream_A_write => DW_49_stream_A_write(L2L3_D4), + DW_L3L4_D1_stream_AV_din => DW_49_stream_AV_din(L3L4_D1), + DW_L3L4_D1_stream_A_full_neg => DW_49_stream_A_full_neg(L3L4_D1), + DW_L3L4_D1_stream_A_write => DW_49_stream_A_write(L3L4_D1), + DW_L3L4_D2_stream_AV_din => DW_49_stream_AV_din(L3L4_D2), + DW_L3L4_D2_stream_A_full_neg => DW_49_stream_A_full_neg(L3L4_D2), + DW_L3L4_D2_stream_A_write => DW_49_stream_A_write(L3L4_D2), + DW_D1D2_D3_stream_AV_din => DW_49_stream_AV_din(D1D2_D3), + DW_D1D2_D3_stream_A_full_neg => DW_49_stream_A_full_neg(D1D2_D3), + DW_D1D2_D3_stream_A_write => DW_49_stream_A_write(D1D2_D3), + DW_D1D2_D4_stream_AV_din => DW_49_stream_AV_din(D1D2_D4), + DW_D1D2_D4_stream_A_full_neg => DW_49_stream_A_full_neg(D1D2_D4), + DW_D1D2_D4_stream_A_write => DW_49_stream_A_write(D1D2_D4), + DW_D1D2_D5_stream_AV_din => DW_49_stream_AV_din(D1D2_D5), + DW_D1D2_D5_stream_A_full_neg => DW_49_stream_A_full_neg(D1D2_D5), + DW_D1D2_D5_stream_A_write => DW_49_stream_A_write(D1D2_D5), + DW_D3D4_D1_stream_AV_din => DW_49_stream_AV_din(D3D4_D1), + DW_D3D4_D1_stream_A_full_neg => DW_49_stream_A_full_neg(D3D4_D1), + DW_D3D4_D1_stream_A_write => DW_49_stream_A_write(D3D4_D1), + DW_D3D4_D2_stream_AV_din => DW_49_stream_AV_din(D3D4_D2), + DW_D3D4_D2_stream_A_full_neg => DW_49_stream_A_full_neg(D3D4_D2), + DW_D3D4_D2_stream_A_write => DW_49_stream_A_write(D3D4_D2), + DW_D3D4_D5_stream_AV_din => DW_49_stream_AV_din(D3D4_D5), + DW_D3D4_D5_stream_A_full_neg => DW_49_stream_A_full_neg(D3D4_D5), + DW_D3D4_D5_stream_A_write => DW_49_stream_A_write(D3D4_D5), + DW_L1D1_D2_stream_AV_din => DW_49_stream_AV_din(L1D1_D2), + DW_L1D1_D2_stream_A_full_neg => DW_49_stream_A_full_neg(L1D1_D2), + DW_L1D1_D2_stream_A_write => DW_49_stream_A_write(L1D1_D2), + DW_L1D1_D3_stream_AV_din => DW_49_stream_AV_din(L1D1_D3), + DW_L1D1_D3_stream_A_full_neg => DW_49_stream_A_full_neg(L1D1_D3), + DW_L1D1_D3_stream_A_write => DW_49_stream_A_write(L1D1_D3), + DW_L1D1_D4_stream_AV_din => DW_49_stream_AV_din(L1D1_D4), + DW_L1D1_D4_stream_A_full_neg => DW_49_stream_A_full_neg(L1D1_D4), + DW_L1D1_D4_stream_A_write => DW_49_stream_A_write(L1D1_D4), + DW_L1D1_D5_stream_AV_din => DW_49_stream_AV_din(L1D1_D5), + DW_L1D1_D5_stream_A_full_neg => DW_49_stream_A_full_neg(L1D1_D5), + DW_L1D1_D5_stream_A_write => DW_49_stream_A_write(L1D1_D5), + DW_L2D1_D2_stream_AV_din => DW_49_stream_AV_din(L2D1_D2), + DW_L2D1_D2_stream_A_full_neg => DW_49_stream_A_full_neg(L2D1_D2), + DW_L2D1_D2_stream_A_write => DW_49_stream_A_write(L2D1_D2), + DW_L2D1_D3_stream_AV_din => DW_49_stream_AV_din(L2D1_D3), + DW_L2D1_D3_stream_A_full_neg => DW_49_stream_A_full_neg(L2D1_D3), + DW_L2D1_D3_stream_A_write => DW_49_stream_A_write(L2D1_D3), + DW_L2D1_D4_stream_AV_din => DW_49_stream_AV_din(L2D1_D4), + DW_L2D1_D4_stream_A_full_neg => DW_49_stream_A_full_neg(L2D1_D4), + DW_L2D1_D4_stream_A_write => DW_49_stream_A_write(L2D1_D4), + BW_L1L2_L3_stream_AV_din => BW_46_stream_AV_din(L1L2_L3), + BW_L1L2_L3_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L3), + BW_L1L2_L3_stream_A_write => BW_46_stream_A_write(L1L2_L3), + BW_L1L2_L4_stream_AV_din => BW_46_stream_AV_din(L1L2_L4), + BW_L1L2_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L4), + BW_L1L2_L4_stream_A_write => BW_46_stream_A_write(L1L2_L4), + BW_L1L2_L5_stream_AV_din => BW_46_stream_AV_din(L1L2_L5), + BW_L1L2_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L5), + BW_L1L2_L5_stream_A_write => BW_46_stream_A_write(L1L2_L5), + BW_L1L2_L6_stream_AV_din => BW_46_stream_AV_din(L1L2_L6), + BW_L1L2_L6_stream_A_full_neg => BW_46_stream_A_full_neg(L1L2_L6), + BW_L1L2_L6_stream_A_write => BW_46_stream_A_write(L1L2_L6), + BW_L2L3_L1_stream_AV_din => BW_46_stream_AV_din(L2L3_L1), + BW_L2L3_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L2L3_L1), + BW_L2L3_L1_stream_A_write => BW_46_stream_A_write(L2L3_L1), + BW_L2L3_L4_stream_AV_din => BW_46_stream_AV_din(L2L3_L4), + BW_L2L3_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L2L3_L4), + BW_L2L3_L4_stream_A_write => BW_46_stream_A_write(L2L3_L4), + BW_L2L3_L5_stream_AV_din => BW_46_stream_AV_din(L2L3_L5), + BW_L2L3_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L2L3_L5), + BW_L2L3_L5_stream_A_write => BW_46_stream_A_write(L2L3_L5), + BW_L3L4_L1_stream_AV_din => BW_46_stream_AV_din(L3L4_L1), + BW_L3L4_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L1), + BW_L3L4_L1_stream_A_write => BW_46_stream_A_write(L3L4_L1), + BW_L3L4_L2_stream_AV_din => BW_46_stream_AV_din(L3L4_L2), + BW_L3L4_L2_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L2), + BW_L3L4_L2_stream_A_write => BW_46_stream_A_write(L3L4_L2), + BW_L3L4_L5_stream_AV_din => BW_46_stream_AV_din(L3L4_L5), + BW_L3L4_L5_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L5), + BW_L3L4_L5_stream_A_write => BW_46_stream_A_write(L3L4_L5), + BW_L3L4_L6_stream_AV_din => BW_46_stream_AV_din(L3L4_L6), + BW_L3L4_L6_stream_A_full_neg => BW_46_stream_A_full_neg(L3L4_L6), + BW_L3L4_L6_stream_A_write => BW_46_stream_A_write(L3L4_L6), + BW_L5L6_L1_stream_AV_din => BW_46_stream_AV_din(L5L6_L1), + BW_L5L6_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L1), + BW_L5L6_L1_stream_A_write => BW_46_stream_A_write(L5L6_L1), + BW_L5L6_L2_stream_AV_din => BW_46_stream_AV_din(L5L6_L2), + BW_L5L6_L2_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L2), + BW_L5L6_L2_stream_A_write => BW_46_stream_A_write(L5L6_L2), + BW_L5L6_L3_stream_AV_din => BW_46_stream_AV_din(L5L6_L3), + BW_L5L6_L3_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L3), + BW_L5L6_L3_stream_A_write => BW_46_stream_A_write(L5L6_L3), + BW_L5L6_L4_stream_AV_din => BW_46_stream_AV_din(L5L6_L4), + BW_L5L6_L4_stream_A_full_neg => BW_46_stream_A_full_neg(L5L6_L4), + BW_L5L6_L4_stream_A_write => BW_46_stream_A_write(L5L6_L4), + BW_D1D2_L1_stream_AV_din => BW_46_stream_AV_din(D1D2_L1), + BW_D1D2_L1_stream_A_full_neg => BW_46_stream_A_full_neg(D1D2_L1), + BW_D1D2_L1_stream_A_write => BW_46_stream_A_write(D1D2_L1), + BW_D1D2_L2_stream_AV_din => BW_46_stream_AV_din(D1D2_L2), + BW_D1D2_L2_stream_A_full_neg => BW_46_stream_A_full_neg(D1D2_L2), + BW_D1D2_L2_stream_A_write => BW_46_stream_A_write(D1D2_L2), + BW_D3D4_L1_stream_AV_din => BW_46_stream_AV_din(D3D4_L1), + BW_D3D4_L1_stream_A_full_neg => BW_46_stream_A_full_neg(D3D4_L1), + BW_D3D4_L1_stream_A_write => BW_46_stream_A_write(D3D4_L1), + BW_L2D1_L1_stream_AV_din => BW_46_stream_AV_din(L2D1_L1), + BW_L2D1_L1_stream_A_full_neg => BW_46_stream_A_full_neg(L2D1_L1), + BW_L2D1_L1_stream_A_write => BW_46_stream_A_write(L2D1_L1) + ); + +end architecture rtl; diff --git a/IntegrationTests/DualFPGA/firmware/hdl/tf_to_kf.vhd b/IntegrationTests/DualFPGA/firmware/hdl/tf_to_kf.vhd new file mode 100644 index 00000000000..fdcce010404 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/hdl/tf_to_kf.vhd @@ -0,0 +1,154 @@ +------------------------------------------------------------------------------- +-- Title : tf to kf +-- Project : +------------------------------------------------------------------------------- +-- File : tf_to_kf.vhd +-- Author : Filippo Marini +-- Company : University of Colorado Boulder +-- Created : 2022-11-02 +-- Last update: 2022-11-03 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: Module to convert between TB output format and KF input format. +-- One day, Duplicate Removal may replace this +------------------------------------------------------------------------------- +-- Copyright (c) 2022 University of Colorado Boulder +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2022-11-02 1.0 fmarini Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +use work.tf_pkg.all; +use work.memUtil_pkg.all; +use work.memUtil_aux_pkg_f2.all; +use work.tf_interface_pkg.all; + +use work.hybrid_data_types.all; +use work.hybrid_data_formats.all; +use work.hybrid_tools.all; + +entity tf_to_kf is + port ( + clk_i : in std_logic; + TW_104_data_i : in t_arr_TW_104_data; + TW_104_valid_i : in t_arr_TW_104_1b; + DW_49_data_i : in t_arr_DW_49_DATA; + DW_49_valid_i : in t_arr_DW_49_1b; + BW_46_data_i : in t_arr_BW_46_DATA; + BW_46_valid_i : in t_arr_BW_46_1b; + kf_reset_i : in std_logic; + tftokf_o : out t_channlesTB(numTW_104 - 1 downto 0) + ); +end entity tf_to_kf; + +architecture rtl of tf_to_kf is + + constant widthTrackletLmap : natural := 24; + constant widthTBInOutIndex : natural := 20; + + type t_arr_stub_1b is array(0 to 3) of std_logic; + type t_arr_stub_DW is array(0 to 3) of enum_DW_49; + type t_arr_stub_BW is array(0 to 3) of enum_BW_46; + type t_arr_seed_arr_stub_1b is array(enum_TW_104) of t_arr_stub_1b; + type t_arr_seed_arr_stub_DW is array(enum_TW_104) of t_arr_stub_DW; + type t_arr_seed_arr_stub_BW is array(enum_TW_104) of t_arr_stub_BW; + + --constants used to look up which barrel/disk stubs should be assigned to which seed type + --10 indicates barrel, 11 disk, 0X invalid + constant disk_stub_valid : t_arr_seed_arr_stub_1b := (('1','1','1','1'), --L1L2 + ('1','1','1','1'), --L2L3 + ('1','1','0','0'), --L3L4 + ('0','0','0','0'), --L5L6 + ('1','1','1','0'), --D1D2 + ('1','1','1','0'), --D3D4 + ('1','1','1','1'), --L1D1 + ('1','1','1','0') --L2D1 + ); + + + constant disk_stub_lut : t_arr_seed_arr_stub_DW := ((L1L2_D1,L1L2_D2,L1L2_D3,L1L2_D4), --L1L2 + (L2L3_D1,L2L3_D2,L2L3_D3,L2L3_D4), --L2L3 + (L3L4_D1,L3L4_D2,L1L2_D1,L1L2_D1), --L3L4 + (L1L2_D1,L1L2_D1,L1L2_D1,L1L2_D1), --L5L6 + (D1D2_D3,D1D2_D4,D1D2_D5,L1L2_D1), --D1D2 + (D3D4_D1,D3D4_D2,D3D4_D5,L1L2_D1), --D3D4 + (L1D1_D2,L1D1_D3,L1D1_D4,L1D1_D5), --L1D1 + (L2D1_D2,L2D1_D3,L2D1_D4,L1L2_D1) --L2D1 + ); + constant barrel_stub_valid : t_arr_seed_arr_stub_1b := (('1','1','1','1'), --L1L2 + ('1','1','1','0'), --L2L3 + ('1','1','1','1'), --L3L4 + ('1','1','1','1'), --L5L6 + ('1','1','0','0'), --D1D2 + ('1','0','0','0'), --D3D4 + ('0','0','0','0'), --L1D1 + ('1','0','0','0') --L2D1 + ); + constant barrel_stub_lut : t_arr_seed_arr_stub_BW := ((L1L2_L3,L1L2_L4,L1L2_L5,L1L2_L6), --L1L2 + (L2L3_L1,L2L3_L4,L2L3_L5,L1L2_L3), --L2L3 + (L3L4_L1,L3L4_L2,L3L4_L5,L3L4_L6), --L3L4 + (L5L6_L1,L5L6_L2,L5L6_L3,L5L6_L4), --L5L6 + (D1D2_L1,D1D2_L2,L1L2_L3,L1L2_L3), --D1D2 + (D3D4_L1,L1L2_L3,L1L2_L3,L1L2_L3), --D3D4 + (L1L2_L3,L1L2_L3,L1L2_L3,L1L2_L3), --L1D1 + (L2D1_L1,L1L2_L3,L1L2_L3,L1L2_L3) --L2D1 + ); + +begin -- architecture rtl + + p_tf_to_kf : process (clk_i) is + + + begin -- process p_tf_to_kf + if rising_edge(clk_i) then -- rising clock edge + --this style of loop not recommended for synthesis, but seems to be used elsewhere + for i in TW_104_data_i'range loop + tftokf_o(enum_TW_104'pos(i)) <= nulll; + tftokf_o(enum_TW_104'pos(i)).track.reset <= kf_reset_i; + if TW_104_valid_i(i) = '1' then + tftokf_o(enum_TW_104'pos(i)).track.valid <= TW_104_data_i(i)(1 + widthTBseedType + WidthTBInOutIndex + widthTBinv2R + widthTBphi0 + widthTBz0 + widthTBcot + widthTrackletLmap - 1); + tftokf_o(enum_TW_104'pos(i)).track.seedtype <= TW_104_data_i(i)(widthTBseedType + widthTBInOutIndex + widthTBinv2R + widthTBphi0 + widthTBz0 + widthTBcot + widthTrackletLmap - 1 downto widthTBInOutIndex + widthTBinv2R + widthTBphi0 + widthTBz0 + widthTBcot + widthTrackletLmap); + tftokf_o(enum_TW_104'pos(i)).track.inv2R <= TW_104_data_i(i)(widthTBinv2R + widthTBphi0 + widthTBz0 + widthTBcot + widthTrackletLmap - 1 downto widthTBphi0 + widthTBz0 + widthTBcot + widthTrackletLmap); + tftokf_o(enum_TW_104'pos(i)).track.phi0 <= TW_104_data_i(i)(widthTBphi0 + widthTBz0 + widthTBcot + widthTrackletLmap - 1 downto widthTBz0 + widthTBcot + widthTrackletLmap); + tftokf_o(enum_TW_104'pos(i)).track.z0 <= TW_104_data_i(i)(widthTBz0 + widthTBcot + widthTrackletLmap - 1 downto widthTBcot + widthTrackletLmap); + tftokf_o(enum_TW_104'pos(i)).track.cot <= TW_104_data_i(i)(widthTBcot + widthTrackletLmap - 1 downto widthTrackletLmap); + --barrel + for j in 0 to 3 loop + if (barrel_stub_valid(i)(j) = '1') then + tftokf_o(enum_TW_104'pos(i)).stubs(j).reset <= kf_reset_i; + tftokf_o(enum_TW_104'pos(i)).stubs(j).valid <= BW_46_data_i(barrel_stub_lut(i)(j))(1 + widthTBtrackId + widthTBstubId + widthsTBr(0) + widthsTBphi(0) + widthsTBz(0) - 1); + tftokf_o(enum_TW_104'pos(i)).stubs(j).trackId <= BW_46_data_i(barrel_stub_lut(i)(j))(widthTBtrackId + widthTBstubId + widthsTBr(0) + widthsTBphi(0) + widthsTBz(0) - 1 downto widthTBstubId + widthsTBr(0) + widthsTBphi(0) + widthsTBz(0)); + tftokf_o(enum_TW_104'pos(i)).stubs(j).stubId <= BW_46_data_i(barrel_stub_lut(i)(j))(widthTBstubId + widthsTBr(0) + widthsTBphi(0) + widthsTBz(0) - 1 downto widthsTBr(0) + widthsTBphi(0) + widthsTBz(0)); + tftokf_o(enum_TW_104'pos(i)).stubs(j).r <= resize(BW_46_data_i(barrel_stub_lut(i)(j))(widthsTBr(0) + widthsTBphi(0) + widthsTBz(0) - 1 downto widthsTBphi(0) + widthsTBz(0)), widthTBr); + tftokf_o(enum_TW_104'pos(i)).stubs(j).phi <= resize(BW_46_data_i(barrel_stub_lut(i)(j))(widthsTBphi(0) + widthsTBz(0) - 1 downto widthsTBz(0)), widthTBphi); + tftokf_o(enum_TW_104'pos(i)).stubs(j).z <= resize(BW_46_data_i(barrel_stub_lut(i)(j))(widthsTBz(0) - 1 downto 0), widthTBz); + else + tftokf_o(enum_TW_104'pos(i)).stubs(j).reset <= kf_reset_i; + tftokf_o(enum_TW_104'pos(i)).stubs(j).valid <= '0'; + end if; + end loop; + --disk + for j in 0 to 3 loop + if (disk_stub_valid(i)(j) = '1') then + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).reset <= kf_reset_i; + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).valid <= DW_49_data_i(disk_stub_lut(i)(j))(1 + widthTBtrackId + widthTBstubId + widthsTBr(2) + widthsTBphi(2) + widthsTBz(2) - 1); + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).trackId <= DW_49_data_i(disk_stub_lut(i)(j))(widthTBtrackId + widthTBstubId + widthsTBr(2) + widthsTBphi(2) + widthsTBz(2) - 1 downto widthTBstubId + widthsTBr(2) + widthsTBphi(2) + widthsTBz(2)); + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).stubId <= DW_49_data_i(disk_stub_lut(i)(j))(widthTBstubId + widthsTBr(2) + widthsTBphi(2) + widthsTBz(2) - 1 downto widthsTBr(2) + widthsTBphi(2) + widthsTBz(2)); + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).r <= resize(DW_49_data_i(disk_stub_lut(i)(j))(widthsTBr(2) + widthsTBphi(2) + widthsTBz(2) - 1 downto widthsTBphi(2) + widthsTBz(2)), widthTBr); + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).phi <= resize(DW_49_data_i(disk_stub_lut(i)(j))(widthsTBphi(2) + widthsTBz(2) - 1 downto widthsTBz(2)), widthTBphi); + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).z <= resize(DW_49_data_i(disk_stub_lut(i)(j))(widthsTBz(2) - 1 downto 0), widthTBz); + else + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).reset <= kf_reset_i; + tftokf_o(enum_TW_104'pos(i)).stubs(j+4).valid <= '0'; + end if; + end loop; + end if; + end loop; -- i + end if; + end process p_tf_to_kf; + +end architecture rtl; diff --git a/IntegrationTests/DualFPGA/firmware/scripts/convert_emData2EMP_Link.py b/IntegrationTests/DualFPGA/firmware/scripts/convert_emData2EMP_Link.py new file mode 100644 index 00000000000..473a90689ec --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/scripts/convert_emData2EMP_Link.py @@ -0,0 +1,120 @@ +import argparse +import os + +# Run with python3 in work/proj/ +# Converts InputRouter input data from emData to EMP format + +def parseArguments(): + # Create argument parser + parser = argparse.ArgumentParser(description="Convert an emData/ memory data file into a EMP format file. Link-file mapping is done editing the header of the script.") + + # Optional arguments + parser.add_argument("-d", "--directory", dest="inputDir", help="directory containing input data", type=str, default="emData/MemPrintsReduced/InputStubs/") + parser.add_argument("-o","--outFile", dest="outFile", help="output file name", type=str, default="Link_EMP.txt") + + # Parse arguments + args = parser.parse_args() + + return args + +# Files in order in which they are referred to in memUtil_pkg.vhd. +# with key being channel number. +channel_names = ['PS10G_1_A','PS10G_1_B','PS10G_2_A','PS10G_2_B','PS10G_3_A', + 'PS10G_3_B','PS10G_4_A','PS10G_4_B','PS_1_A','PS_1_B','PS_2_A', + 'PS_2_B','negPS10G_1_A','negPS10G_1_B','negPS10G_2_A', + 'negPS10G_2_B','negPS10G_3_A','negPS10G_3_B','negPS10G_4_A', + 'negPS10G_4_B','negPS_1_A','negPS_1_B','negPS_2_A','negPS_2_B', + '2S_1_A','2S_1_B','2S_2_A','2S_2_B','2S_3_A','2S_3_B', + '2S_4_A','2S_4_B','2S_5_A','2S_5_B','2S_6_A','2S_6_B', + 'neg2S_1_A','neg2S_1_B','neg2S_2_A','neg2S_2_B','neg2S_3_A', + 'neg2S_3_B','neg2S_4_A','neg2S_4_B','neg2S_5_A','neg2S_5_B', + 'neg2S_6_A','neg2S_6_B'] + +channel_numbers = [68,69,70,71,72,73,74,75,76,77,78,79,84,85,86,87,88,89,90,91,92,93, + 94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111, + 112,113,114,115,116,117,118,119] + +mapping = {} +for ich in range(len(channel_names)): + mapping[channel_numbers[ich]] = "Link_DL_"+channel_names[ich]+"_04.dat" + +#channels = ["q00c0","q00c1","q00c2","q00c3","q01c0","q01c1","q01c2","q01c3","q02c0","q02c1","q02c2","q02c3","q03c0","q03c1","q03c2","q03c3"] + +empWordLen=16 # Hex chars in an EMP data word +clksInTM=108 # Length of TM period in clock cycles +clksInGap=6 # Gap when no valid data sent. + +if __name__ == '__main__': + + args = parseArguments() + + outFile = open(args.outFile, 'w') + + allData = {} + for chan, fileName in mapping.items(): + file = open(args.inputDir + "/" + fileName, 'r') + lines = file.readlines() + for line in lines: + words = line.split() + if len(words) == 6: + eventNumber = int(words[5]) + allData[(eventNumber,chan)] = [] + if len(words) == 3: + addr = words[0] + data = words[2] + empData = data[2:].zfill(empWordLen) + allData[(eventNumber,chan)].append(empData) + + outFile.write("ID: x0\n") + outFile.write("Metadata: (strobe,) start of orbit, start of packet, end of packet, valid\n") + outFile.write("\n") + outFile.write(" Link ") + for chan in mapping: + outFile.write("%s " %(str(chan).zfill(3))) + outFile.write("\n") + + gapData = "0000000000000000" + nullData = "0000000000000000" + md_null = "0000" + md_valid = "0001" + md_soe = "0101" + md_soo = "1101" + md_eoe = "0011" + iClk = 0 + + for event in range(1+eventNumber): + for iFrame in range(0,clksInTM): + iFrameCorr = iFrame - clksInGap + iClk += 1 + outFile.write("Frame %s " %(str(iClk-1).zfill(4))) + for chan in mapping: + theKey = (event,chan) + empDataList = allData[theKey] + if (iFrame < clksInGap): + outFile.write("%s " %md_null) + outFile.write("%s " %gapData) + elif (iFrameCorr < len(empDataList)): + if (event == 0) : + if (iFrameCorr == 0) : + outFile.write("%s " %md_soo) + elif (iFrame == clksInTM - 1) : + outFile.write("%s " %md_eoe) + else : + outFile.write("%s " %md_valid) + else : + if (iFrameCorr == 0) : + outFile.write("%s " %md_soe) + elif (iFrame == clksInTM - 1) : + outFile.write("%s " %md_eoe) + else : + outFile.write("%s " %md_valid) + outFile.write("%s " %empDataList[iFrameCorr]) + else: + if (iFrame == clksInTM - 1) : + outFile.write("%s " %md_eoe) + else : + outFile.write("%s " %md_valid) + outFile.write("%s " %nullData) + outFile.write("\n") + print("Output written to file ",args.outFile) + diff --git a/IntegrationTests/DualFPGA/firmware/scripts/convert_emData2EMP_Link_FPGA2.py b/IntegrationTests/DualFPGA/firmware/scripts/convert_emData2EMP_Link_FPGA2.py new file mode 100644 index 00000000000..7da8c2e3e41 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/scripts/convert_emData2EMP_Link_FPGA2.py @@ -0,0 +1,211 @@ +#!/usr/bin/env python +#Script that generates merged TPAR and AS inputs to second FPGA project +#as they would appear coming from first FPGA link +#Run with python from IntegrationTests/DualFPGA/firmware/ + +import argparse +import os + +#constants + +#TPARs stored of list of list of names, where inner list indicates merging +TPAR_NAMES = [['L1L2A','L1L2B','L1L2C'],['L1L2D','L1L2E'],['L1L2F'],['L1L2G'], + ['L1L2H','L1L2I'],['L1L2J','L1L2K','L1L2L'], + ['L2L3A','L2L3B','L2L3C','L2L3D'],['L3L4A','L3L4B'], + ['L3L4C','L3L4D'],['L5L6A','L5L6B','L5L6C','L5L6D'], + ['D1D2A','D1D2B','D1D2C','D1D2D'], + ['D3D4A','D3D4B','D3D4C','D3D4D'], + ['L1D1A','L1D1B','L1D1C','L1D1D'], + ['L1D1E','L1D1F','L1D1G','L1D1H'], + ['L2D1A','L2D1B','L2D1C','L2D1D']] + +AS_NAMES = ['L1PHIA','L1PHIB','L1PHIC','L1PHID','L1PHIE','L1PHIF','L1PHIG', + 'L1PHIH','L2PHIA','L2PHIB','L2PHIC','L2PHID','L3PHIA','L3PHIB', + 'L3PHIC','L3PHID','L4PHIA','L4PHIB','L4PHIC','L4PHID','L5PHIA', + 'L5PHIB','L5PHIC','L5PHID','L6PHIA','L6PHIB','L6PHIC','L6PHID', + 'D1PHIA','D1PHIB','D1PHIC','D1PHID','D2PHIA','D2PHIB','D2PHIC', + 'D2PHID','D3PHIA','D3PHIB','D3PHIC','D3PHID','D4PHIA','D4PHIB', + 'D4PHIC','D4PHID','D5PHIA','D5PHIB','D5PHIC','D5PHID'] + +MERGE_WORDS = ['00','01','10','11'] + +AS_LINK_INDICES = [59,58,57,56,55,54,53,52,51,50,49,48,43,42,41,40,39,38,37, + 36,35,34,33,32,31,30,29,28] + +AS_LINK_LAST_SIZE_DIFF = 16 + +TPAR_LINK_INDICES = [27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10] + +TPAR_LINK_LAST_SIZE_DIFF = 12 + +LINKS_USED = [9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29, + 30,31,32,33,34,35,36,37,38,39,40,41,42,43,48,49,50,51,52,53,54, + 55,56,57,58,59] + +#helper functions + +def parseArguments(): + '''Parse arguments and return arguments object''' + # Create argument parser + parser = argparse.ArgumentParser( + description="Convert a emData/ memory data files into EMP format file") + + # Optional arguments + parser.add_argument("-d", "--directory", dest="inputDir", + help="directory containing input data", type=str, + default="emData/MemPrintsReduced/") + parser.add_argument("-o","--outFile", dest="outFile", + help="output file name", type=str, default="Link_EMP.txt") + + # Parse arguments + args = parser.parse_args() + + return args + +def get_words_for_event(filename, event_number, word_length): + '''Get the data words for a given event. Returns a list of bytes''' + words = [] + + with open(filename) as input_file: + lines = input_file.readlines() + current_event = False + past_event = False + for line in lines: + if not current_event: + #N.B. past_event is used to avoid matching later events ex. Event : 11 to Event : 1 + if (('Event : '+str(event_number)) in line) and not past_event: + current_event = True + elif current_event: + if not ('Event : ' in line): + line_terms = line.split(' ') + bit_string = '' + if len(line_terms)==3: + bit_string = (line_terms[1]).replace('|','') + else: + bit_string = (line_terms[2]).replace('|','') + words.append(bit_string) + else: + current_event = False + past_event = True + + return words + +def get_word_or_empty(words, type_index, word_index, length): + '''Get words[type_index][word_index] or 0 string of length length''' + if len(words[type_index]) > word_index: + return words[type_index][word_index] + return ''.join(['0' for i in range(length)]) + +def write_emp_input(args): + '''Write input for second FPGA''' + output_file = open(args.outFile, 'w') + + output_file.write("ID: x0\n") + output_file.write("Metadata: (strobe,) start of orbit, start of packet, end of packet, valid\n") + output_file.write("\n") + output_file.write(" Link ") + for chan in LINKS_USED: + output_file.write("%s " %(str(chan).zfill(3))) + output_file.write("\n") + + word_index = 0 + + for ievent in range(100): + + #extract list AS/TPAR words for each event, where first index is AS type and second is word in event + as_words = [] + tpar_words = [] + for as_name in AS_NAMES: + event_words = get_words_for_event( + args.inputDir+'/Stubs/AllStubs_AS_'+as_name+'n1_04.dat',ievent,36) + for iword in range(len(event_words)): + event_words[iword] = '1'+event_words[iword] + as_words.append(event_words) + for tpar_name_group in TPAR_NAMES: + tpar_words_group = [] + merge_index = 0 + for tpar_name in tpar_name_group: + event_words = get_words_for_event( + args.inputDir+'/TrackletParameters/TrackletParameters_TPAR_'+tpar_name+'_04.dat', + ievent,73) + for iword in range(len(event_words)): + event_words[iword] = '1'+MERGE_WORDS[merge_index]+event_words[iword] + tpar_words_group += event_words + merge_index += 1 + tpar_words.append(tpar_words_group) + + for iword in range(108): + + #merge AS/TPAR data into two giant strings for this clock cycle + as_string = '' + tpar_string = '' + for ias in range(len(AS_NAMES)): + if (iword >= 6): + as_string = get_word_or_empty(as_words, ias, iword-6, 37) + as_string + else: + as_string = ''.join(['0' for i in range(37)]) + as_string + for itpar in range(len(TPAR_NAMES)): + if (iword >= 6): + tpar_string = get_word_or_empty(tpar_words, itpar, iword-6, 76) + tpar_string + else: + tpar_string = ''.join(['0' for i in range(76)]) + tpar_string + + link_data = {} + + #Slice words into links + for ilink in range(len(AS_LINK_INDICES)): + if ilink != (len(AS_LINK_INDICES)-1): + start_idx = len(as_string)-(ilink+1)*64 + end_idx = len(as_string)-ilink*64 + link_data[AS_LINK_INDICES[ilink]] = as_string[start_idx:end_idx] + else: + end_idx = len(as_string)-ilink*64 + padding = ''.join(['0' for i in range(64-end_idx)]) + link_data[AS_LINK_INDICES[ilink]] = padding+as_string[:end_idx] + for ilink in range(len(TPAR_LINK_INDICES)): + if ilink != (len(TPAR_LINK_INDICES)-1): + start_idx = len(tpar_string)-(ilink+1)*64 + end_idx = len(tpar_string)-ilink*64 + link_data[TPAR_LINK_INDICES[ilink]] = tpar_string[start_idx:end_idx] + else: + end_idx = len(tpar_string)-ilink*64 + padding = ''.join(['0' for i in range(64-end_idx)]) + link_data[TPAR_LINK_INDICES[ilink]] = padding+tpar_string[:end_idx] + if (iword >= 6): + link_data[9]=''.join(['0' for i in range(61)])+bin(ievent % 4)[2:] + else: + link_data[9]=''.join(['0' for i in range(64)]) + + #Convert link data to hex and write + # + output_file.write('Frame %s ' %(str(word_index).zfill(4))) + for link in LINKS_USED: + if (word_index % 108) < 6: + output_file.write('%s ' %'0000') + elif (word_index % 108) == 6: + if (word_index == 6): + output_file.write('%s ' %'1101') + else: + output_file.write('%s ' %'0101') + elif (word_index % 108) == 107: + output_file.write('%s ' %'0011') + else: + output_file.write('%s ' %'0001') + output_file.write('%s '%(hex(int(link_data[link],2))[2:]).zfill(16)) + output_file.write('\n') + word_index += 1 + + output_file.close() + + print("Output written to file ",args.outFile) + +def check_emp_output(args): + '''Check output from first FPGA project''' + #TODO write this, for now, manually check output is permutation of the first FPGA output + +if __name__ == '__main__': + + args = parseArguments() + write_emp_input(args) + + diff --git a/IntegrationTests/DualFPGA/firmware/scripts/setup_project.sh b/IntegrationTests/DualFPGA/firmware/scripts/setup_project.sh new file mode 100644 index 00000000000..0bd8dfb8ba6 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/scripts/setup_project.sh @@ -0,0 +1,55 @@ +#/bin/bash +set -e -x + +# uses ssh key authentication for gitlab.cern.ch, make sure you have that set up + +PROJ_DIR=dual_fpga_2 + +[ -d ${PROJ_DIR} ] && rm -rf ${PROJ_DIR} +ipbb init ${PROJ_DIR} +cd ${PROJ_DIR} +ipbb -e add git ssh://git@gitlab.cern.ch:7999/p2-xware/firmware/emp-fwk.git -b v0.9.0-alpha2 +ipbb -e add git https://github.com/apollo-lhc/CM_FPGA_FW -b v3.0.0 + + +ipbb add git https://gitlab.cern.ch/ttc/legacy_ttc.git -b v2.1 +ipbb add git ssh://git@gitlab.cern.ch:7999/cms-tcds/cms-tcds2-firmware.git -b v0_1_1 +ipbb add git ssh://git@gitlab.cern.ch:7999/hptd/tclink.git -r fda0bcf +ipbb add git https://github.com/ipbus/ipbus-firmware -b v1.9 +ipbb add git ssh://git@gitlab.cern.ch:7999/dth_p1-v2/slinkrocket_ips.git -b v03.12 +ipbb add git ssh://git@gitlab.cern.ch:7999/dth_p1-v2/slinkrocket.git -b v03.12 +ipbb add git ssh://git@github.com/cms-l1tk/firmware-hls.git -b dual_fpga + +export PATH=/opt/cactus/bin/uhal/tools:$PATH +export LD_LIBRARY_PATH=/opt/cactus/lib:${LD_LIBRARY_PATH} + +BASEDIR=$(pwd) + +export COLUMNS=120 + +# FPGA 1 Simulation +ipbb proj create vivado vsim_f1 firmware-hls:IntegrationTests/DualFPGA/ vsim_f1.dep +cd proj/vsim_f1/ +ipbb vivado generate-project --single + +cd $BASEDIR +# FPGA 1 +ipbb proj create vivado tf_f1 firmware-hls:IntegrationTests/DualFPGA/ apollo_f1.dep +cd proj/tf_f1/ +ipbb ipbus gendecoders +ipbb vivado generate-project --single +ipbb vivado synth -j16 impl -j16 package + +cd $BASEDIR +# FPGA 2 Simulation +ipbb proj create vivado vsim_f2 firmware-hls:IntegrationTests/DualFPGA/ vsim_f2.dep +cd proj/vsim_f2/ +ipbb vivado generate-project --single + +cd $BASEDIR +# FPGA 2 +ipbb proj create vivado tf_f2 firmware-hls:IntegrationTests/DualFPGA/ apollo_f2.dep +cd proj/tf_f2/ +ipbb ipbus gendecoders +ipbb vivado generate-project --single +ipbb vivado synth -j16 impl -j16 package diff --git a/IntegrationTests/DualFPGA/firmware/ucf/floorplan_f2.tcl b/IntegrationTests/DualFPGA/firmware/ucf/floorplan_f2.tcl new file mode 100644 index 00000000000..c0aafdd7355 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/ucf/floorplan_f2.tcl @@ -0,0 +1,1839 @@ +#this XDC contains physical constraints for the second FPGA project + +#temporary delete_pblocks for pblocks in previous versions of this script to avoid left-over shenanigans that will confuse vivado + +delete_pblocks -quiet pblock_payload_MPD4BD5B pblock_payload_MPD4CD5C pblock_payload_FMpipeline1 pblock_payload_MPL6AL6B pblock_payload_MPL6CL6D +delete_pblocks -quiet pblock_payload_MPL1to6 pblock_payload_MPD1to5 pblock_payload_FTset1 pblock_payload_FTset2 pblock_payload_FTMPset1 pblock_payload_FTMPset2 + +#normal delete_pblocks +delete_pblocks -quiet pblock_payload_MPL1A pblock_payload_MPL1B pblock_payload_MPL1C pblock_payload_MPL1D pblock_payload_MPL1E pblock_payload_MPL1F pblock_payload_MPL1G pblock_payload_MPL1H pblock_payload_MPL2A pblock_payload_MPL2B pblock_payload_MPL2C pblock_payload_MPL2D pblock_payload_MPL3A pblock_payload_MPL3B pblock_payload_MPL3C pblock_payload_MPL3D pblock_payload_MPL4A pblock_payload_MPL4B pblock_payload_MPL4C pblock_payload_MPL4D pblock_payload_MPL5A pblock_payload_MPL5B pblock_payload_MPL5C pblock_payload_MPL5D pblock_payload_MPL6A pblock_payload_MPL6B pblock_payload_MPL6C pblock_payload_MPL6D pblock_payload_MPD1A pblock_payload_MPD1B pblock_payload_MPD1C pblock_payload_MPD1D pblock_payload_MPD2A pblock_payload_MPD2B pblock_payload_MPD2C pblock_payload_MPD2D pblock_payload_MPD3A pblock_payload_MPD3B pblock_payload_MPD3C pblock_payload_MPD3D pblock_payload_MPD4A pblock_payload_MPD4B pblock_payload_MPD4C pblock_payload_MPD4D pblock_payload_MPD5A pblock_payload_MPD5B pblock_payload_MPD5C pblock_payload_MPD5D +delete_pblocks -quiet pblock_payload_MPD4AD5AMem pblock_payload_MPD4BD5BMem pblock_payload_MPD4CD5CMem pblock_payload_MPD4DD5DMem pblock_payload_MPL1AL2AMem pblock_payload_MPL1BL2BMem pblock_payload_MPL1CL2CMem pblock_payload_MPL1DL2DMem +delete_pblocks -quiet pblock_payload_FTL1L2 pblock_payload_FTL2L3 pblock_payload_FTL3L4 pblock_payload_FTL5L6 pblock_payload_FTD1D2 pblock_payload_FTD3D4 pblock_payload_FTL1D1 pblock_payload_FTL2D1 pblock_payload_KF pblock_payload_KFout +delete_pblocks -quiet pblock_payload_PCVMSMERs +delete_pblocks -quiet pblock_payload_MPA1 pblock_payload_MPB1 pblock_payload_MPC1 pblock_payload_MPD1 pblock_payload_MPA2 pblock_payload_MPB2 pblock_payload_MPC2 pblock_payload_MPD2 + +# ----------------------------------------------------------------------------- +# add_rects_to_pblock -- +# +# Adds a set of rectangular ranges of sites to a pblock. +# The ranges are passed in a dictionary. Only the ranges matching the user-defined patterns are added +# This is modified from the EMP central version to include URAMs +# +# Arguments: +# aPBlock The pblock +# aRects Dictionary of rectangular areas +# Results: +# The result is that of the command being redone. Also repla +proc add_rects_to_pblock_mod {aPBlock aRects} { + + set lSitePatterns [list SLICE DSP* URAM* RAM* GT*CHANNEL*] + + set lToAdd [list] + foreach lType $lSitePatterns { + dict for {lId lRange} [dict filter $aRects key $lType] { + lappend lToAdd $lRange + } + } + + puts "Adding to $aPBlock rectangles $lToAdd" + resize_pblock $aPBlock -add $lToAdd +} + +proc add_uram_rects_to_pblock {aPBlock aRects} { + + set lSitePatterns [list URAM*] + + set lToAdd [list] + foreach lType $lSitePatterns { + dict for {lId lRange} [dict filter $aRects key $lType] { + lappend lToAdd $lRange + } + } + + puts "Adding to $aPBlock URAM rectangles $lToAdd" + resize_pblock $aPBlock -add $lToAdd +} + +proc add_bram_rects_to_pblock {aPBlock aRects} { + + set lSitePatterns [list RAM*] + + set lToAdd [list] + foreach lType $lSitePatterns { + dict for {lId lRange} [dict filter $aRects key $lType] { + lappend lToAdd $lRange + } + } + + puts "Adding to $aPBlock URAM rectangles $lToAdd" + resize_pblock $aPBlock -add $lToAdd +} + +proc add_nonram_rects_to_pblock {aPBlock aRects} { + + set lSitePatterns [list SLICE DSP*] + + set lToAdd [list] + foreach lType $lSitePatterns { + dict for {lId lRange} [dict filter $aRects key $lType] { + lappend lToAdd $lRange + } + } + + puts "Adding to $aPBlock rectangles $lToAdd" + resize_pblock $aPBlock -add $lToAdd +} + +#these are from region_constraints_toolbox (called in ex. area_constraints.tcl) +#maybe one day actually make some method that emulates the logic in +#create_quad_pblocks that automates the calculation in case something changes, +#but certainly don't want to re-call create_quad_pblocks +set lLeftBoundary 851 +set lRightBoundary 4278 + +#define parents + +set lpblock_payload_MPL1to6 [create_pblock pblock_payload_MPL1to6] +set lpblock_payload_MPD1to5 [create_pblock pblock_payload_MPD1to5] +set lpblock_payload_FTset1 [create_pblock pblock_payload_FTset1] +set lpblock_payload_FTset2 [create_pblock pblock_payload_FTset2] + +set lpblock_payload_MPL1to6L [create_pblock pblock_payload_MPL1to6L] +set lpblock_payload_MPL1to6H [create_pblock pblock_payload_MPL1to6H] +set lpblock_payload_MPD1to5A [create_pblock pblock_payload_MPD1to5A] +set lpblock_payload_MPD1to5B [create_pblock pblock_payload_MPD1to5B] +set lpblock_payload_MPD1to5C [create_pblock pblock_payload_MPD1to5C] +set lpblock_payload_MPD1to5D [create_pblock pblock_payload_MPD1to5D] + +set lpblock_payload_MPL1to6AL [create_pblock pblock_payload_MPL1to6AL] +set lpblock_payload_MPL1to6BL [create_pblock pblock_payload_MPL1to6BL] +set lpblock_payload_MPL1to6CL [create_pblock pblock_payload_MPL1to6CL] +set lpblock_payload_MPL1to6DL [create_pblock pblock_payload_MPL1to6DL] +set lpblock_payload_MPL1to6AH [create_pblock pblock_payload_MPL1to6AH] +set lpblock_payload_MPL1to6BH [create_pblock pblock_payload_MPL1to6BH] +set lpblock_payload_MPL1to6CH [create_pblock pblock_payload_MPL1to6CH] +set lpblock_payload_MPL1to6DH [create_pblock pblock_payload_MPL1to6DH] + + +#PC/VMSMER pblock + +set lpblock_payload_PCVMSMERDs [create_pblock pblock_payload_PCVMSMERDs] +add_cells_to_pblock [get_pblocks pblock_payload_PCVMSMERDs] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_D1D2* \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_D3D4* \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_L1D1* \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_L2D1* \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_L2L3* \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSMER_D* \ + ]] + +set lpblock_payload_PCVMSMERLs [create_pblock pblock_payload_PCVMSMERLs] +add_cells_to_pblock [get_pblocks pblock_payload_PCVMSMERLs] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_L1L2* \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_L3L4* \ + payload/tf2_wrapper_1/SectorProcessor_1/PC_L5L6* \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2*in \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L3L4*in \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L5L6*in \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSMER_L* \ + ]] + +set lpblock_payload_sp2_mem_writer [create_pblock pblock_payload_sp2_mem_writer] +add_cells_to_pblock [get_pblocks pblock_payload_sp2_mem_writer] [get_cells -quiet [list \ + payload/sp2_mem_writer_1/* \ + ]] + +#MP pblocks + +set lpblock_payload_MPL1A [create_pblock pblock_payload_MPL1A] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIA \ + ]] + +set lpblock_payload_MPL1B [create_pblock pblock_payload_MPL1B] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIB \ + ]] + +set lpblock_payload_MPL1C [create_pblock pblock_payload_MPL1C] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIC \ + ]] + +set lpblock_payload_MPL1D [create_pblock pblock_payload_MPL1D] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHID \ + ]] + +set lpblock_payload_MPL1E [create_pblock pblock_payload_MPL1E] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1E] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIEn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIEn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIE \ + ]] + +set lpblock_payload_MPL1F [create_pblock pblock_payload_MPL1F] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1F] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIFn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIFn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIF \ + ]] + +set lpblock_payload_MPL1G [create_pblock pblock_payload_MPL1G] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1G] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIGn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIGn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIG \ + ]] + +set lpblock_payload_MPL1H [create_pblock pblock_payload_MPL1H] +add_cells_to_pblock [get_pblocks pblock_payload_MPL1H] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L1PHIHn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L1PHIHn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L1PHIH \ + ]] + +set lpblock_payload_MPL2A [create_pblock pblock_payload_MPL2A] +add_cells_to_pblock [get_pblocks pblock_payload_MPL2A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L2PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L2PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L2PHIA \ + ]] + +set lpblock_payload_MPL2B [create_pblock pblock_payload_MPL2B] +add_cells_to_pblock [get_pblocks pblock_payload_MPL2B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L2PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L2PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_L3L4CD_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_L5L6ABCD_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_D1D2ABCD_L2PHIB \ + ]] + +set lpblock_payload_MPL2C [create_pblock pblock_payload_MPL2C] +add_cells_to_pblock [get_pblocks pblock_payload_MPL2C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L2PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L2PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L2PHIC \ + ]] + +set lpblock_payload_MPL2D [create_pblock pblock_payload_MPL2D] +add_cells_to_pblock [get_pblocks pblock_payload_MPL2D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L2PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L2PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L2PHID \ + ]] + +set lpblock_payload_MPL3A [create_pblock pblock_payload_MPL3A] +add_cells_to_pblock [get_pblocks pblock_payload_MPL3A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L3PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L3PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L3PHIA \ + ]] + +set lpblock_payload_MPL3B [create_pblock pblock_payload_MPL3B] +add_cells_to_pblock [get_pblocks pblock_payload_MPL3B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L3PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L3PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L3PHIB \ + ]] + +set lpblock_payload_MPL3C [create_pblock pblock_payload_MPL3C] +add_cells_to_pblock [get_pblocks pblock_payload_MPL3C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L3PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L3PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L3PHIC \ + ]] + +set lpblock_payload_MPL3D [create_pblock pblock_payload_MPL3D] +add_cells_to_pblock [get_pblocks pblock_payload_MPL3D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L3PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L3PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L3PHID \ + ]] + +set lpblock_payload_MPL4A [create_pblock pblock_payload_MPL4A] +add_cells_to_pblock [get_pblocks pblock_payload_MPL4A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L4PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L4PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L4PHIA \ + ]] + +set lpblock_payload_MPL4B [create_pblock pblock_payload_MPL4B] +add_cells_to_pblock [get_pblocks pblock_payload_MPL4B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L4PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L4PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L4PHIB \ + ]] + +set lpblock_payload_MPL4C [create_pblock pblock_payload_MPL4C] +add_cells_to_pblock [get_pblocks pblock_payload_MPL4C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L4PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L4PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L4PHIC \ + ]] + +set lpblock_payload_MPL4D [create_pblock pblock_payload_MPL4D] +add_cells_to_pblock [get_pblocks pblock_payload_MPL4D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L4PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L4PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L4PHID \ + ]] + +set lpblock_payload_MPL5A [create_pblock pblock_payload_MPL5A] +add_cells_to_pblock [get_pblocks pblock_payload_MPL5A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L5PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L5PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L5PHIA \ + ]] + +set lpblock_payload_MPL5B [create_pblock pblock_payload_MPL5B] +add_cells_to_pblock [get_pblocks pblock_payload_MPL5B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L5PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L5PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L5PHIB \ + ]] + +set lpblock_payload_MPL5C [create_pblock pblock_payload_MPL5C] +add_cells_to_pblock [get_pblocks pblock_payload_MPL5C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L5PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L5PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L5PHIC \ + ]] + +set lpblock_payload_MPL5D [create_pblock pblock_payload_MPL5D] +add_cells_to_pblock [get_pblocks pblock_payload_MPL5D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L5PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L5PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L5PHID \ + ]] + +set lpblock_payload_MPL6A [create_pblock pblock_payload_MPL6A] +add_cells_to_pblock [get_pblocks pblock_payload_MPL6A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L6PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L6PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L6PHIA \ + ]] + +set lpblock_payload_MPL6B [create_pblock pblock_payload_MPL6B] +add_cells_to_pblock [get_pblocks pblock_payload_MPL6B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L6PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L6PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L6PHIB \ + ]] + +set lpblock_payload_MPL6C [create_pblock pblock_payload_MPL6C] +add_cells_to_pblock [get_pblocks pblock_payload_MPL6C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L6PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L6PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L6PHIC \ + ]] + +set lpblock_payload_MPL6D [create_pblock pblock_payload_MPL6D] +add_cells_to_pblock [get_pblocks pblock_payload_MPL6D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_L6PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_L6PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_L6PHID \ + ]] + +set lpblock_payload_MPD1A [create_pblock pblock_payload_MPD1A] +add_cells_to_pblock [get_pblocks pblock_payload_MPD1A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D1PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D1PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D1PHIA \ + ]] + +set lpblock_payload_MPD1B [create_pblock pblock_payload_MPD1B] +add_cells_to_pblock [get_pblocks pblock_payload_MPD1B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D1PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D1PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D1PHIB \ + ]] + +set lpblock_payload_MPD1C [create_pblock pblock_payload_MPD1C] +add_cells_to_pblock [get_pblocks pblock_payload_MPD1C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D1PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D1PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D1PHIC \ + ]] + +set lpblock_payload_MPD1D [create_pblock pblock_payload_MPD1D] +add_cells_to_pblock [get_pblocks pblock_payload_MPD1D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D1PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D1PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D1PHID \ + ]] + +set lpblock_payload_MPD2A [create_pblock pblock_payload_MPD2A] +add_cells_to_pblock [get_pblocks pblock_payload_MPD2A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D2PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D2PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D2PHIA \ + ]] + +set lpblock_payload_MPD2B [create_pblock pblock_payload_MPD2B] +add_cells_to_pblock [get_pblocks pblock_payload_MPD2B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D2PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D2PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D2PHIB \ + ]] + +set lpblock_payload_MPD2C [create_pblock pblock_payload_MPD2C] +add_cells_to_pblock [get_pblocks pblock_payload_MPD2C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D2PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D2PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D2PHIC \ + ]] + +set lpblock_payload_MPD2D [create_pblock pblock_payload_MPD2D] +add_cells_to_pblock [get_pblocks pblock_payload_MPD2D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D2PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D2PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D2PHID \ + ]] + +set lpblock_payload_MPD3A [create_pblock pblock_payload_MPD3A] +add_cells_to_pblock [get_pblocks pblock_payload_MPD3A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D3PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D3PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D3PHIA \ + ]] + +set lpblock_payload_MPD3B [create_pblock pblock_payload_MPD3B] +add_cells_to_pblock [get_pblocks pblock_payload_MPD3B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D3PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D3PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D3PHIB \ + ]] + +set lpblock_payload_MPD3C [create_pblock pblock_payload_MPD3C] +add_cells_to_pblock [get_pblocks pblock_payload_MPD3C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D3PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D3PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D3PHIC \ + ]] + +set lpblock_payload_MPD3D [create_pblock pblock_payload_MPD3D] +add_cells_to_pblock [get_pblocks pblock_payload_MPD3D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D3PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D3PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D3PHID \ + ]] + +set lpblock_payload_MPD4A [create_pblock pblock_payload_MPD4A] +add_cells_to_pblock [get_pblocks pblock_payload_MPD4A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D4PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D4PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D4PHIA \ + ]] + +set lpblock_payload_MPD4B [create_pblock pblock_payload_MPD4B] +add_cells_to_pblock [get_pblocks pblock_payload_MPD4B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D4PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D4PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D4PHIB \ + ]] + +set lpblock_payload_MPD4C [create_pblock pblock_payload_MPD4C] +add_cells_to_pblock [get_pblocks pblock_payload_MPD4C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D4PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D4PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D4PHIC \ + ]] + +set lpblock_payload_MPD4D [create_pblock pblock_payload_MPD4D] +add_cells_to_pblock [get_pblocks pblock_payload_MPD4D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D4PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D4PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D4PHID \ + ]] + +set lpblock_payload_MPD5A [create_pblock pblock_payload_MPD5A] +add_cells_to_pblock [get_pblocks pblock_payload_MPD5A] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D5PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D5PHIAn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D5PHIA \ + ]] + +set lpblock_payload_MPD5B [create_pblock pblock_payload_MPD5B] +add_cells_to_pblock [get_pblocks pblock_payload_MPD5B] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D5PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D5PHIBn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D5PHIB \ + ]] + +set lpblock_payload_MPD5C [create_pblock pblock_payload_MPD5C] +add_cells_to_pblock [get_pblocks pblock_payload_MPD5C] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D5PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D5PHICn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D5PHIC \ + ]] + +set lpblock_payload_MPD5D [create_pblock pblock_payload_MPD5D] +add_cells_to_pblock [get_pblocks pblock_payload_MPD5D] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_D5PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/VMSME_D5PHIDn2 \ + payload/tf2_wrapper_1/SectorProcessor_1/MPROJ_*_D5PHID \ + ]] + +set lpblock_payload_ASin [create_pblock pblock_payload_ASin] +add_cells_to_pblock [get_pblocks pblock_payload_ASin] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_*in \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_*in_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/AS_*in_DELAY0 \ + ]] + +#FT pblocks + +set lpblock_payload_FTL1L2 [create_pblock pblock_payload_FTL1L2] +add_cells_to_pblock [get_pblocks pblock_payload_FTL1L2] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L1L2 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2ABC \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2DE \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2F \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2G \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2HI \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2JKL \ + ]] + +set lpblock_payload_FTL2L3 [create_pblock pblock_payload_FTL2L3] +add_cells_to_pblock [get_pblocks pblock_payload_FTL2L3] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L2L3 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L2L3ABCD \ + ]] + +set lpblock_payload_FTL3L4 [create_pblock pblock_payload_FTL3L4] +add_cells_to_pblock [get_pblocks pblock_payload_FTL3L4] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L3L4 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L3L4AB \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L3L4CD \ + ]] + +set lpblock_payload_FTL5L6 [create_pblock pblock_payload_FTL5L6] +add_cells_to_pblock [get_pblocks pblock_payload_FTL5L6] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L5L6 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L5L6ABCD \ + ]] + +set lpblock_payload_FTD1D2 [create_pblock pblock_payload_FTD1D2] +add_cells_to_pblock [get_pblocks pblock_payload_FTD1D2] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_D1D2 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_D1D2ABCD \ + ]] + +set lpblock_payload_FTD3D4 [create_pblock pblock_payload_FTD3D4] +add_cells_to_pblock [get_pblocks pblock_payload_FTD3D4] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_D3D4 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_D3D4ABCD \ + ]] + +set lpblock_payload_FTL1D1 [create_pblock pblock_payload_FTL1D1] +add_cells_to_pblock [get_pblocks pblock_payload_FTL1D1] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L1D1 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1D1ABCD \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1D1EFGH \ + ]] + +set lpblock_payload_FTL2D1 [create_pblock pblock_payload_FTL2D1] +add_cells_to_pblock [get_pblocks pblock_payload_FTL2D1] [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L2D1 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L2D1ABCD \ + ]] + +#KF pblocks + +set lpblock_payload_kf_input_merger [create_pblock pblock_payload_kf_input_merger] +add_cells_to_pblock [get_pblocks pblock_payload_kf_input_merger] [get_cells -quiet [list \ + payload/kf_input_merger_1 \ + ]] + +set lpblock_payload_KF [create_pblock pblock_payload_KF] +add_cells_to_pblock [get_pblocks pblock_payload_KF] [get_cells -quiet [list \ + payload/kf_wrapper_1/kf_top_1 \ + payload/kf_wrapper_1/kfin_top_1 \ + payload/kfout_isolation_out_1 \ + ]] + +set lpblock_payload_KFout [create_pblock pblock_payload_KFout] +add_cells_to_pblock [get_pblocks pblock_payload_KFout] [get_cells -quiet [list \ + payload/kf_wrapper_1/kfout_top_1 \ + ]] + + +#set parents + +set_property PARENT pblock_payload_MPL1to6L [get_pblocks [list \ + pblock_payload_MPL1A \ + pblock_payload_MPL1B \ + pblock_payload_MPL1C \ + pblock_payload_MPL1D \ + pblock_payload_MPL2A \ + pblock_payload_MPL2B \ + pblock_payload_MPL3A \ + pblock_payload_MPL3B \ + pblock_payload_MPL4A \ + pblock_payload_MPL4B \ + pblock_payload_MPL5A \ + pblock_payload_MPL5B \ + pblock_payload_MPL6A \ + pblock_payload_MPL6B \ + ]] + +set_property PARENT pblock_payload_MPL1to6H [get_pblocks [list \ + pblock_payload_MPL1E \ + pblock_payload_MPL1F \ + pblock_payload_MPL1G \ + pblock_payload_MPL1H \ + pblock_payload_MPL2C \ + pblock_payload_MPL2D \ + pblock_payload_MPL3C \ + pblock_payload_MPL3D \ + pblock_payload_MPL4C \ + pblock_payload_MPL4D \ + pblock_payload_MPL5C \ + pblock_payload_MPL5D \ + pblock_payload_MPL6C \ + pblock_payload_MPL6D \ + ]] + +set_property PARENT pblock_payload_MPL1to6AL [get_pblocks [list \ + pblock_payload_MPL1A \ + pblock_payload_MPL1E \ + pblock_payload_MPL2A \ + pblock_payload_MPL3A \ + ]] + + +set_property PARENT pblock_payload_MPL1to6AH [get_pblocks [list \ + pblock_payload_MPL4A \ + pblock_payload_MPL5A \ + pblock_payload_MPL6A \ + ]] + + +set_property PARENT pblock_payload_MPL1to6BL [get_pblocks [list \ + pblock_payload_MPL1B \ + pblock_payload_MPL1F \ + pblock_payload_MPL2B \ + pblock_payload_MPL3B \ + ]] +set_property PARENT pblock_payload_MPL1to6BH [get_pblocks [list \ + pblock_payload_MPL1B \ + pblock_payload_MPL5B \ + pblock_payload_MPL6B \ + ]] + + +set_property PARENT pblock_payload_MPL1to6CL [get_pblocks [list \ + pblock_payload_MPL1C \ + pblock_payload_MPL1G \ + pblock_payload_MPL2C \ + pblock_payload_MPL3C \ + ]] + +set_property PARENT pblock_payload_MPL1to6CH [get_pblocks [list \ + pblock_payload_MPL4C \ + pblock_payload_MPL5C \ + pblock_payload_MPL6C \ + ]] + +set_property PARENT pblock_payload_MPL1to6DL [get_pblocks [list \ + pblock_payload_MPL1D \ + pblock_payload_MPL1H \ + pblock_payload_MPL2D \ + pblock_payload_MPL3D \ + ]] + +set_property PARENT pblock_payload_MPL1to6DH [get_pblocks [list \ + pblock_payload_MPL4D \ + pblock_payload_MPL5D \ + pblock_payload_MPL6D \ + ]] + +set_property PARENT pblock_payload_MPD1to5A [get_pblocks [list \ + pblock_payload_MPD1A \ + pblock_payload_MPD2A \ + pblock_payload_MPD3A \ + pblock_payload_MPD4A \ + pblock_payload_MPD5A \ + ]] + +set_property PARENT pblock_payload_MPD1to5B [get_pblocks [list \ + pblock_payload_MPD1B \ + pblock_payload_MPD2B \ + pblock_payload_MPD3B \ + pblock_payload_MPD4B \ + pblock_payload_MPD5B \ + ]] + +set_property PARENT pblock_payload_MPD1to5C [get_pblocks [list \ + pblock_payload_MPD1C \ + pblock_payload_MPD2C \ + pblock_payload_MPD3C \ + pblock_payload_MPD4C \ + pblock_payload_MPD5C \ + ]] + +set_property PARENT pblock_payload_MPD1to5D [get_pblocks [list \ + pblock_payload_MPD1D \ + pblock_payload_MPD2D \ + pblock_payload_MPD3D \ + pblock_payload_MPD4D \ + pblock_payload_MPD5D \ + ]] + +set_property PARENT pblock_payload_FTset1 [get_pblocks [list \ + pblock_payload_FTL1L2 \ + pblock_payload_FTL3L4 \ + pblock_payload_FTL5L6 \ + ]] + +set_property PARENT pblock_payload_FTset2 [get_pblocks [list \ + pblock_payload_FTL2L3 \ + pblock_payload_FTD1D2 \ + pblock_payload_FTD3D4 \ + pblock_payload_FTL1D1 \ + pblock_payload_FTL2D1 \ + ]] + + +set_property USER_CLUSTER cluster_payload_MPL1PHIA [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIA_DELAY0/di_pipe_reg[1]* \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHIB [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIB_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHIC [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIC_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHID [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHID_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHIE [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIE_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIE_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIE_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIE_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIE_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIE_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHIF [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIF_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIF_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIF_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIF_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIF_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIF_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHIG [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIG_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIG_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIG_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIG_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIG_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIG_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL1PHIH [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIH_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIH_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIH_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIH_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIH_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIH_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL2PHIA [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIA_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL2PHIB [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIB_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL2PHIC [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIC_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL2PHID [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHID_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL3PHIA [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIA_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL3PHIB [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIB_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL3PHIC [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIC_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL3PHID [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHID_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL4PHIA [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIA_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL4PHIB [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIB_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL4PHIC [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIC_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL4PHID [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHID_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL5PHIA [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIA_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL5PHIB [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIB_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL5PHIC [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIC_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL5PHID [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHID_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL6PHIA [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIA_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIA_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL6PHIB [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIB_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIB_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL6PHIC [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIC_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIC_DELAY0 \ + ]] + +set_property USER_CLUSTER cluster_payload_MPL6PHID [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/MP_L6PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHID_DELAY0 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHID_DELAY0 \ + ]] + +#set_property USER_CLUSTER cluster_payload_MPD1PHIA [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHIA \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIA_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD1PHIB [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHIB \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIB_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD1PHIC [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHIC \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIC_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD1PHID [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D1PHID \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHID_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD2PHIA [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHIA \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIA_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD2PHIB [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHIB \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIB_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD2PHIC [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHIC \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIC_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD2PHID [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D2PHID \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHID_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD3PHIA [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHIA \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIA_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD3PHIB [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHIB \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIB_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD3PHIC [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHIC \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIC_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD3PHID [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D3PHID \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHID_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD4PHIA [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHIA \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIA_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD4PHIB [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHIB \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIB_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD4PHIC [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHIC \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIC_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD4PHID [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D4PHID \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHID_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD5PHIA [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHIA \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIA_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIA_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD5PHIB [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHIB \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIB_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIB_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD5PHIC [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHIC \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIC_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIC_DELAY0 \ +# ]] + +#set_property USER_CLUSTER cluster_payload_MPD5PHID [get_cells -quiet [list \ +# payload/tf2_wrapper_1/SectorProcessor_1/MP_D5PHID \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHID_DELAY0 \ +# payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHID_DELAY0 \ +# ]] + +set_property USER_CLUSTER cluster_payload_FTL1L2 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L1L2 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_L6PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1L2_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2ABC \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2DE \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2F \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2G \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2HI \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1L2JKL \ + ]] + +set_property USER_CLUSTER cluster_payload_FTL2L3 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L2L3 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2L3_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L2L3ABCD \ + ]] + +set_property USER_CLUSTER cluster_payload_FTL3L4 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L3L4 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_L6PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L3L4_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L3L4AB \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L3L4CD \ + ]] + +set_property USER_CLUSTER cluster_payload_FTL5L6 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L5L6 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_L4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L5L6_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L5L6ABCD \ + ]] + +set_property USER_CLUSTER cluster_payload_FTD1D2 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_D1D2 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_L2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D1D2_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_D1D2ABCD \ + ]] + +set_property USER_CLUSTER cluster_payload_FTD3D4 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_D3D4 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_D3D4_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_D3D4ABCD \ + ]] + +set_property USER_CLUSTER cluster_payload_FTL1D1 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L1D1 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_D5PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L1D1_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1D1ABCD \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L1D1EFGH \ + ]] + +set_property USER_CLUSTER cluster_payload_FTL2D1 [get_cells -quiet [list \ + payload/tf2_wrapper_1/SectorProcessor_1/FT_L2D1 \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIE \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIF \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIG \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_L1PHIH \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D2PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D3PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIA \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIB \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHIC \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_D4PHID \ + payload/tf2_wrapper_1/SectorProcessor_1/FM_L2D1_*_DELAY \ + payload/tf2_wrapper_1/SectorProcessor_1/MPAR_L2D1ABCD \ + ]] + + + +# +#set constraints + +# +#set pblock_payload_MPL1to6Lrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=0 && ROW_INDEX<=3 && COLUMN_INDEX<=3}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6L $pblock_payload_MPL1to6Lrect +# +#set pblock_payload_MPL1to6Hrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=0 && ROW_INDEX<=3 && COLUMN_INDEX>=4}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6H $pblock_payload_MPL1to6Hrect +# +#set pblock_payload_MPALrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==0 && COLUMN_INDEX<=3 && COLUMN_INDEX>=1}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6AL $pblock_payload_MPALrect +# +#set pblock_payload_MPBLrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==1 && COLUMN_INDEX<=3 && COLUMN_INDEX>=1}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6BL $pblock_payload_MPBLrect +# +#set pblock_payload_MPCLrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==2 && COLUMN_INDEX<=3 && COLUMN_INDEX>=1}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6CL $pblock_payload_MPCLrect +# +#set pblock_payload_MPDLrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==3 && COLUMN_INDEX<=3 && COLUMN_INDEX>=1}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6DL $pblock_payload_MPDLrect +# +#set pblock_payload_MPAHrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==0 && COLUMN_INDEX<=5 && COLUMN_INDEX>=4}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6AH $pblock_payload_MPAHrect +# +#set pblock_payload_MPBHrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==1 && COLUMN_INDEX<=5 && COLUMN_INDEX>=4}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6BH $pblock_payload_MPBHrect +# +#set pblock_payload_MPCHrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==2 && COLUMN_INDEX<=5 && COLUMN_INDEX>=4}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6CH $pblock_payload_MPCHrect +# +#set pblock_payload_MPDHrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX==3 && COLUMN_INDEX<=5 && COLUMN_INDEX>=4}] -f "RPM_X <= 4000 && RPM_X >= 1000"]] +#add_rects_to_pblock_mod $lpblock_payload_MPL1to6DH $pblock_payload_MPDHrect +# +set pblock_payload_MPL1Arect [find_rects [get_sites -f "RPM_Y >= 0 && RPM_Y <= 62 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1A $pblock_payload_MPL1Arect +# +set pblock_payload_MPL1Brect [find_rects [get_sites -f "RPM_Y >= 62 && RPM_Y <=124 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1B $pblock_payload_MPL1Brect +# +set pblock_payload_MPL1Crect [find_rects [get_sites -f "RPM_Y >=124 && RPM_Y <= 186 && RPM_X >= 900 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1C $pblock_payload_MPL1Crect +# +set pblock_payload_MPL1Drect [find_rects [get_sites -f "RPM_Y >= 186 && RPM_Y <= 248 && RPM_X >= 900 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1D $pblock_payload_MPL1Drect +# +set pblock_payload_MPL1Erect [find_rects [get_sites -f "RPM_Y >= 248 && RPM_Y <= 310 && RPM_X >= 900 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1E $pblock_payload_MPL1Erect +# +set pblock_payload_MPL1Frect [find_rects [get_sites -f "RPM_Y >= 310 && RPM_Y <= 372 && RPM_X >= 900 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1F $pblock_payload_MPL1Frect +# +set pblock_payload_MPL1Grect [find_rects [get_sites -f "RPM_Y >= 372 && RPM_Y <= 434 && RPM_X >= 900 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1G $pblock_payload_MPL1Grect +# +set pblock_payload_MPL1Hrect [find_rects [get_sites -f "RPM_Y >= 434 && RPM_Y <= 496 && RPM_X >= 900 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL1H $pblock_payload_MPL1Hrect +# +set pblock_payload_MPL2Arect [find_rects [get_sites -f "RPM_Y >= 0 && RPM_Y <= 62 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL2A $pblock_payload_MPL2Arect +# +set pblock_payload_MPL2Brect [find_rects [get_sites -f "RPM_Y >= 62 && RPM_Y <=124 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL2B $pblock_payload_MPL2Brect +# +set pblock_payload_MPL2Crect [find_rects [get_sites -f "RPM_Y >=124 && RPM_Y <= 186 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL2C $pblock_payload_MPL2Crect +# +set pblock_payload_MPL2Drect [find_rects [get_sites -f "RPM_Y >= 186 && RPM_Y <= 248 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL2D $pblock_payload_MPL2Drect +# +set pblock_payload_MPL3Arect [find_rects [get_sites -f "RPM_Y >= 248 && RPM_Y <= 310 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL3A $pblock_payload_MPL3Arect +# +set pblock_payload_MPL3Brect [find_rects [get_sites -f "RPM_Y >= 310 && RPM_Y <= 372 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL3B $pblock_payload_MPL3Brect +# +set pblock_payload_MPL3Crect [find_rects [get_sites -f "RPM_Y >= 372 && RPM_Y <= 434 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL3C $pblock_payload_MPL3Crect +# +set pblock_payload_MPL3Drect [find_rects [get_sites -f "RPM_Y >= 434 && RPM_Y <= 496 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL3D $pblock_payload_MPL3Drect +# +set pblock_payload_MPL4Arect [find_rects [get_sites -f "RPM_Y >= 496 && RPM_Y <= 559 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL4A $pblock_payload_MPL4Arect +# +set pblock_payload_MPL4Brect [find_rects [get_sites -f "RPM_Y >= 496 && RPM_Y <= 559 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPL4B $pblock_payload_MPL4Brect +# +set pblock_payload_MPL4Crect [find_rects [get_sites -f "RPM_Y >= 496 && RPM_Y <= 559 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL4C $pblock_payload_MPL4Crect +# +set pblock_payload_MPL4Drect [find_rects [get_sites -f "RPM_Y >= 496 && RPM_Y <= 621 && RPM_X >= 3300 && RPM_X <= 3700"]] +add_rects_to_pblock_mod $lpblock_payload_MPL4D $pblock_payload_MPL4Drect +# +set pblock_payload_MPL5Arect [find_rects [get_sites -f "RPM_Y >= 0 && RPM_Y <= 62 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL5A $pblock_payload_MPL5Arect +# +set pblock_payload_MPL5Brect [find_rects [get_sites -f "RPM_Y >= 62 && RPM_Y <=124 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL5B $pblock_payload_MPL5Brect +# +set pblock_payload_MPL5Crect [find_rects [get_sites -f "RPM_Y >=124 && RPM_Y <= 186 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL5C $pblock_payload_MPL5Crect +# +set pblock_payload_MPL5Drect [find_rects [get_sites -f "RPM_Y >= 186 && RPM_Y <= 248 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL5D $pblock_payload_MPL5Drect +# +set pblock_payload_MPL6Arect [find_rects [get_sites -f "RPM_Y >= 248 && RPM_Y <= 310 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL6A $pblock_payload_MPL6Arect +# +set pblock_payload_MPL6Brect [find_rects [get_sites -f "RPM_Y >= 310 && RPM_Y <= 372 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL6B $pblock_payload_MPL6Brect +# +set pblock_payload_MPL6Crect [find_rects [get_sites -f "RPM_Y >= 372 && RPM_Y <= 434 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL6C $pblock_payload_MPL6Crect +# +set pblock_payload_MPL6Drect [find_rects [get_sites -f "RPM_Y >= 434 && RPM_Y <= 496 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPL6D $pblock_payload_MPL6Drect +# +#set pblock_payload_MPD1to5Arect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=4 && ROW_INDEX<=4}] -f "RPM_X <= 4200 && RPM_X >= 800"]] +#add_rects_to_pblock_mod $lpblock_payload_MPD1to5A $pblock_payload_MPD1to5Arect +# +#set pblock_payload_MPD1to5Drect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=5 && ROW_INDEX<=5}] -f "RPM_X <= 4200 && RPM_X >= 800"]] +#add_rects_to_pblock_mod $lpblock_payload_MPD1to5D $pblock_payload_MPD1to5Drect +# +#set pblock_payload_MPD1to5Brect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=6 && ROW_INDEX<=6}] -f "RPM_X <= 4200 && RPM_X >= 800"]] +#add_rects_to_pblock_mod $lpblock_payload_MPD1to5B $pblock_payload_MPD1to5Brect +# +#set pblock_payload_MPD1to5Crect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=7 && ROW_INDEX<=7}] -f "RPM_X <= 4200 && RPM_X >= 800"]] +#add_rects_to_pblock_mod $lpblock_payload_MPD1to5C $pblock_payload_MPD1to5Crect +# +# +set pblock_payload_MPD1Arect [find_rects [get_sites -f "RPM_Y >= 559 && RPM_Y <= 620 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD1A $pblock_payload_MPD1Arect +# +set pblock_payload_MPD1Brect [find_rects [get_sites -f "RPM_Y >= 621 && RPM_Y <= 682 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD1B $pblock_payload_MPD1Brect +# +set pblock_payload_MPD1Crect [find_rects [get_sites -f "RPM_Y >= 683 && RPM_Y <= 744 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD1C $pblock_payload_MPD1Crect +# +set pblock_payload_MPD1Drect [find_rects [get_sites -f "RPM_Y >= 745 && RPM_Y <= 806 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD1D $pblock_payload_MPD1Drect +# +set pblock_payload_MPD2Arect [find_rects [get_sites -f "RPM_Y >= 807 && RPM_Y <= 868 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD2A $pblock_payload_MPD2Arect +# +set pblock_payload_MPD2Brect [find_rects [get_sites -f "RPM_Y >= 869 && RPM_Y <= 930 && RPM_X >= 800 && RPM_X <= 1700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD2B $pblock_payload_MPD2Brect +# +set pblock_payload_MPD2Crect [find_rects [get_sites -f "RPM_Y >= 559 && RPM_Y <= 620 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPD2C $pblock_payload_MPD2Crect +# +set pblock_payload_MPD2Drect [find_rects [get_sites -f "RPM_Y >= 621 && RPM_Y <= 682 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPD2D $pblock_payload_MPD2Drect +# +set pblock_payload_MPD3Arect [find_rects [get_sites -f "RPM_Y >= 683 && RPM_Y <= 744 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPD3A $pblock_payload_MPD3Arect +# +set pblock_payload_MPD3Brect [find_rects [get_sites -f "RPM_Y >= 745 && RPM_Y <= 806 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPD3B $pblock_payload_MPD3Brect +# +set pblock_payload_MPD3Crect [find_rects [get_sites -f "RPM_Y >= 807 && RPM_Y <= 868 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPD3C $pblock_payload_MPD3Crect +# +set pblock_payload_MPD3Drect [find_rects [get_sites -f "RPM_Y >= 869 && RPM_Y <= 930 && RPM_X >= 1700 && RPM_X <= 2500"]] +add_rects_to_pblock_mod $lpblock_payload_MPD3D $pblock_payload_MPD3Drect +# +set pblock_payload_MPD4Arect [find_rects [get_sites -f "RPM_Y >= 559 && RPM_Y <= 620 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPD4A $pblock_payload_MPD4Arect +# +set pblock_payload_MPD4Brect [find_rects [get_sites -f "RPM_Y >= 621 && RPM_Y <= 682 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPD4B $pblock_payload_MPD4Brect +# +set pblock_payload_MPD4Crect [find_rects [get_sites -f "RPM_Y >= 683 && RPM_Y <= 744 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPD4C $pblock_payload_MPD4Crect +# +set pblock_payload_MPD4Drect [find_rects [get_sites -f "RPM_Y >= 745 && RPM_Y <= 806 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPD4D $pblock_payload_MPD4Drect +# +set pblock_payload_MPD5Arect [find_rects [get_sites -f "RPM_Y >= 807 && RPM_Y <= 868 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPD5A $pblock_payload_MPD5Arect +# +set pblock_payload_MPD5Brect [find_rects [get_sites -f "RPM_Y >= 869 && RPM_Y <= 930 && RPM_X >= 2500 && RPM_X <= 3300"]] +add_rects_to_pblock_mod $lpblock_payload_MPD5B $pblock_payload_MPD5Brect +# +set pblock_payload_MPD5Crect [find_rects [get_sites -f "RPM_Y >= 621 && RPM_Y <= 744 && RPM_X >= 3300 && RPM_X <= 3700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD5C $pblock_payload_MPD5Crect +# +set pblock_payload_MPD5Drect [find_rects [get_sites -f "RPM_Y >= 745 && RPM_Y <= 864 && RPM_X >= 3300 && RPM_X <= 3700"]] +add_rects_to_pblock_mod $lpblock_payload_MPD5D $pblock_payload_MPD5Drect + +# +# +#set pblock_payload_FTset1rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=0 && ROW_INDEX<=3}] -f "RPM_X <= 800"]] +#add_rects_to_pblock_mod $lpblock_payload_FTset1 $pblock_payload_FTset1rect +# +#set pblock_payload_FTset2rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=4 && ROW_INDEX<=7}] -f "RPM_X <= 800"]] +#add_rects_to_pblock_mod $lpblock_payload_FTset2 $pblock_payload_FTset2rect + +set pblock_payload_FTL1L2rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=4 && ROW_INDEX<=4}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTL1L2 $pblock_payload_FTL1L2rect + +set pblock_payload_FTD1D2rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=5 && ROW_INDEX<=5}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTD1D2 $pblock_payload_FTD1D2rect + +set pblock_payload_FTD3D4rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=6 && ROW_INDEX<=6}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTD3D4 $pblock_payload_FTD3D4rect + +set pblock_payload_FTL1D1rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=7 && ROW_INDEX<=7}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTL1D1 $pblock_payload_FTL1D1rect + +set pblock_payload_FTL2D1rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=7 && ROW_INDEX<=7}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTL2D1 $pblock_payload_FTL2D1rect + +set pblock_payload_FTL2L3rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=3 && ROW_INDEX<=3}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTL2L3 $pblock_payload_FTL2L3rect + +set pblock_payload_FTL3L4rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=2 && ROW_INDEX<=2}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTL3L4 $pblock_payload_FTL3L4rect + +set pblock_payload_FTL5L6rect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=1 && ROW_INDEX<=1}] -f "RPM_X <= 800"]] +add_rects_to_pblock_mod $lpblock_payload_FTL5L6 $pblock_payload_FTL5L6rect + + +set pblock_payload_KFrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=8 && ROW_INDEX<=9}] -f "RPM_X >= $lLeftBoundary && RPM_X <= $lRightBoundary"]] +add_rects_to_pblock_mod $lpblock_payload_KF $pblock_payload_KFrect + +set pblock_payload_KFoutrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=10 && ROW_INDEX<=11}] -f "RPM_X >= $lLeftBoundary && RPM_X <= $lRightBoundary"]] +add_rects_to_pblock_mod $lpblock_payload_KFout $pblock_payload_KFoutrect + +set pblock_payload_ASinrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX<=7}] -f "RPM_X >= 4000"]] +add_rects_to_pblock_mod $lpblock_payload_ASin $pblock_payload_ASinrect + +set pblock_payload_KFinputmergerrect [find_rects [get_sites -f "RPM_X <= 1200 && RPM_Y>=496 && RPM_Y <= 992"]] +add_rects_to_pblock_mod $lpblock_payload_kf_input_merger $pblock_payload_KFinputmergerrect + + +set pblock_payload_PCVMSMERDsrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=4 && ROW_INDEX<=7}] -f "RPM_X >= 4200"]] +add_rects_to_pblock_mod $lpblock_payload_PCVMSMERDs $pblock_payload_PCVMSMERDsrect + +set pblock_payload_PCVMSMERLsrect [find_rects [get_sites -of [get_clock_regions -f {ROW_INDEX>=0 && ROW_INDEX<=3}] -f "RPM_X >= 4000"]] +add_rects_to_pblock_mod $lpblock_payload_PCVMSMERLs $pblock_payload_PCVMSMERLsrect + +set pblock_payload_sp2_mem_writerrect [find_rects [get_sites -f "RPM_X >= 800 ]] +add_rects_to_pblock_mod $lpblock_payload_sp2_mem_writer $pblock_payload_sp2_mem_writerrect + +#change only payload pblocks to be hard constraints +set_property IS_SOFT FALSE [get_pblocks pblock_payload_*] + +#set_property MAX_FANOUT 10000 [get_nets payload/kf_wrapper_1/kfout_top_1/OutObjectsToPacketsInstance/g1[0].RAMreset*] +#set_property MAX_FANOUT 10000 [get_nets payload/kf_wrapper_1/kfout_top_1/OutObjectsToPacketsInstance/g1[1].RAMreset*] diff --git a/IntegrationTests/DualFPGA/firmware/ucf/ip.tcl b/IntegrationTests/DualFPGA/firmware/ucf/ip.tcl new file mode 100644 index 00000000000..b7a9bbb65db --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/ucf/ip.tcl @@ -0,0 +1,4 @@ +catch {get_property ip_repo_paths [current_project]} curr_ip_path +set set_ip_path "set_property ip_repo_paths {${curr_ip_path} ../../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/cgn/} \[\current_project\]" +eval ${set_ip_path} +update_ip_catalog diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl new file mode 100644 index 00000000000..bd2bcfe54fa --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl @@ -0,0 +1,11 @@ +set_property SOURCE_SET sources_1 [get_filesets sim_1] +add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga1.txt + +# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. +set_property source_mgmt_mode None [current_project] +set_property top top [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +set_property target_language VHDL [current_project] +set_property simulator_language VHDL [current_project] +# Re-enabling previously disabled source management mode. +set_property source_mgmt_mode All [current_project] diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl new file mode 100644 index 00000000000..336efc644a8 --- /dev/null +++ b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl @@ -0,0 +1,11 @@ +set_property SOURCE_SET sources_1 [get_filesets sim_1] +add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga2.txt + +# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. +set_property source_mgmt_mode None [current_project] +set_property top top [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +set_property target_language VHDL [current_project] +set_property simulator_language VHDL [current_project] +# Re-enabling previously disabled source management mode. +set_property source_mgmt_mode All [current_project] diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile index 2d41486f8b8..6fbec263cac 100644 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile +++ b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile @@ -4,7 +4,7 @@ input_file = mem/in.txt proj_path = ../../../../proj hls_script_path = ../../script -all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion +all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input $(core_dir): @mkdir cgn mem @@ -32,9 +32,6 @@ add_common_files: hdl_add_files: $(core_file) cd hdl; ln -s ../../../hdl/*.vhd . -lut_inclusion: - @python3 scripts/lut_copy.py - $(input_file): $(core_dir) @python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsReducedCM/InputStubs -o $(input_file) @@ -53,4 +50,4 @@ sim: $(input_file) $(core_file) $(core_dir) @cd $(hls_script_path); vivado -mode batch -source runSim.tcl @python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt -.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input lut_inclusion core_patch +.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl index b590379fe07..4db8b33251a 100644 --- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl +++ b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl @@ -1,16 +1,11 @@ set_property SOURCE_SET sources_1 [get_filesets sim_1] add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/mem/in.txt -set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl ]] -append lut_script "/pre_msim.tcl" -add_files -fileset utils_1 -norecurse $lut_script -#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1] -#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt -set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]" -eval ${pre_path} # Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. set_property source_mgmt_mode None [current_project] set_property top top [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] +set_property target_language VHDL [current_project] +set_property simulator_language VHDL [current_project] # Re-enabling previously disabled source management mode. set_property source_mgmt_mode All [current_project] diff --git a/IntegrationTests/common/cfg/qsim.dep b/IntegrationTests/common/cfg/qsim.dep index c448086b216..0ddc6209970 100644 --- a/IntegrationTests/common/cfg/qsim.dep +++ b/IntegrationTests/common/cfg/qsim.dep @@ -3,7 +3,6 @@ # Dependancies include -c emp-fwk:boards/testbench top.dep -setup ../scripts/pre_qsim.tcl include payload.dep src common/hdl/emp/tb_decl.vhd diff --git a/IntegrationTests/common/cfg/vsim.dep b/IntegrationTests/common/cfg/vsim.dep index 8f982110dc3..61199b21ce7 100644 --- a/IntegrationTests/common/cfg/vsim.dep +++ b/IntegrationTests/common/cfg/vsim.dep @@ -15,6 +15,5 @@ src -c emp-fwk:components/links/slink emp_slink_types.vhd #src -c emp-fwk:components/framework emp_framework_decl.vhd #src -u sim ../mem/in.txt -src -u sim ../scripts/pre_msim.tcl include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2.dep diff --git a/IntegrationTests/common/hdl/emp/pkgs/tf_interface_pkg.vhd b/IntegrationTests/common/hdl/emp/pkgs/tf_interface_pkg.vhd index 321aca85cde..4847dcb9bf7 100644 --- a/IntegrationTests/common/hdl/emp/pkgs/tf_interface_pkg.vhd +++ b/IntegrationTests/common/hdl/emp/pkgs/tf_interface_pkg.vhd @@ -36,6 +36,9 @@ package tf_interface_pkg is function conv (l : ldata) return t_packets; + function conv_f2 (l : ldata) + return t_packets; + end package tf_interface_pkg; package body tf_interface_pkg is @@ -52,6 +55,18 @@ package body tf_interface_pkg is return s; end; + function conv_f2(l : ldata) return t_packets is + variable s : t_packets(numLinksTFP - 1 downto 0); + begin + for k in s'range loop + s(k).valid := l(k+10).valid; + s(k).start_of_orbit := l(k+10).start_of_orbit; + s(k).start := l(k+10).start; + s(k).last := l(k+10).last; + end loop; + return s; + end; + end package body tf_interface_pkg; diff --git a/IntegrationTests/common/script/emp/compare_emp_outputs_fpga1.py b/IntegrationTests/common/script/emp/compare_emp_outputs_fpga1.py new file mode 100644 index 00000000000..4baef787c36 --- /dev/null +++ b/IntegrationTests/common/script/emp/compare_emp_outputs_fpga1.py @@ -0,0 +1,508 @@ +#!/usr/bin/env python +'''@package docstring +Script to cross-check EMP-style outputs from FPGA1 (AllStubs and MergedTrackletParameters) +''' + +import argparse +import math + +class Bitmap: + '''class to work with bit data''' + #Note internally, bitmap is stored as binary string with MSB first + + char_to_bool = {'0' : False, '1' : True} + bool_to_char = {False : '0', True : '1'} + + @staticmethod + def trim_zeros(value): + '''Returns value with MSB zeros removed + + value binary string + ''' + last_one = value.find('1') + if last_one == -1: + return '0' + return value[last_one:] + + @staticmethod + def zero_pad(value,length): + '''Returns value padded until it is at least length + + value binary string + length int minimum length + ''' + if len(value)0: + value = zero_pad(value, length) + if value[0]=='0': + return int(self.value,2) + else: + return -1*((~self).to_int()+1) + + def undigitize(self, is_signed, nbits, granularity): + '''Returns float representing bitmap content + + is_signed whether bitmap represents signed or unsigned value + nbits number of bits + granularity digitization granularity + ''' + int_value = 0 + if is_signed: + int_value = self.to_signedint(nbits) + else: + int_value = self.to_int() + return (int_value+0.5)*granularity + + def substring(self, end, start): + '''Returns sub-bitmap from start inclusively to end noninclusively + + start int starting index of bitmap + end int ending index of bitmap + ''' + start = len(self.value)-start + end = len(self.value)-end + return Bitmap(self.value[end:start]) + +def fix_phi_range(phi): + '''Forces an angle into the range (-pi,pi)''' + while phi>3.1416: + phi -= 2.0*3.1416 + while phi<-3.1416: + phi += 2.0*3.1416 + return phi + +def get_bin_mean(index, bin_boundaries): + '''undigitize value based on bin_boundaries, returning the mean fr the + bin the digitized value falls into. If it is in the uppermost bin + (extending to infinity), the lower bin boundary is given. + + index int, digitized value + bin_boundaries list of floats, digitization bin boundaries + the last bin extends from the last entry in the + list to infinity + ''' + if index<0: + raise ValueError('Input to get_bin_mean must be unsigned.') + if index>=(len(bin_boundaries)-1): + return bin_boundaries[len(bin_boundaries)-1] + return (bin_boundaries[index]+bin_boundaries[index+1])/2.0 + +class KfTrack: + '''Class to store data corresponding to a track written by Kalman Filter''' + + def __init__(self, hex_string): + '''Initialize KF track from hex string + + hex_string string of hex characters representing track + ''' + self.bits = Bitmap(hex_string) + valid = ((self.bits >> 95) & Bitmap('0x1')) + invr = ((self.bits >> 80) & Bitmap('0x7FFF')) + phi0 = ((self.bits >> 68) & Bitmap('0xFFF')) + chi2rphi = ((self.bits >> 64) & Bitmap('0xF')) + tanl = ((self.bits >> 48) & Bitmap('0xFFFF')) + z0 = ((self.bits >> 36) & Bitmap('0xFFF')) + chi2rz = ((self.bits >> 32) & Bitmap('0xF')) + d0 = ((self.bits >> 19) & Bitmap('0x1FFF')) + bendchi2 = ((self.bits >> 16) & Bitmap('0x7')) + hitpattern = ((self.bits >> 9) & Bitmap('0x7F')) + tqmva = ((self.bits >> 6) & Bitmap('0x7')) + extramva = ((self.bits >> 0) & Bitmap('0x3F')) + self.valid = bool(valid.to_int()) + self.invr = invr.undigitize(True,15,2.60212e-7)*2.0 #/cm + self.phi0 = fix_phi_range(phi0.undigitize(True,12,0.000340885)) + self.chi2rphi = get_bin_mean(chi2rphi.to_int(),CHI2RXBINS) + self.tanl = tanl.undigitize(True,16,1.0/2.0**12) + self.z0 = z0.undigitize(True,12,0.00999469) #cm + self.chi2rz = get_bin_mean(chi2rz.to_int(),CHI2RXBINS) + self.d0 = d0.undigitize(True,13,3.757580e-3) #cm + self.bendchi2 = get_bin_mean(bendchi2.to_int(),CHI2BENDBINS) + self.hitpattern = hitpattern.to_int() + self.tqmva = tqmva.to_int() + self.extramva = extramva.to_int() + self.pt = 0.299792458*3.8112*0.01/self.invr #GeV + self.eta = math.asinh(self.tanl) + + def __eq__(self, other): + '''Equality operation that checks exact match between fields + + other KfTrack to compare + ''' + return (self.valid==other.valid and self.invr==other.invr and + self.phi0==other.phi0 and self.chi2rphi==other.chi2rphi and + self.tanl==other.tanl and self.z0==other.z0 and + self.chi2rz==other.chi2rz and self.d0==other.d0 and + self.bendchi2==other.bendchi2 and self.hitpattern==other.hitpattern and + self.tqmva==other.tqmva and self.extramva==other.extramva) + +def loose_compare(track1, track2, verbose=False): + '''Compares track1 and track2 allowing small differences. Returns true if + the two tracks are very similar (see thresholds below). + + track1 KfTrack, first track to compare + track2 KfTrack, second track to comapre + verbose bool used for debugging/extra information + ''' + INVR_THRESHOLD = 0.001 + PHI0_THRESHOLD = 0.001 + CHI2RPHI_THRESHOLD = 1.0 + TANL_THRESHOLD = 0.01 + Z0_THRESHOLD = 0.2 + CHI2RZ_THRESHOLD = 1.0 + D0_THRESHOLD = 0.1 + BENDCHI2_THRESHOLD = 0.5 + TQMVA_THRESHOLD = 1.5 + similar = True + if (track1.valid != track2.valid): + if (verbose): + print('valid bit differs ('+str(track1.valid)+','+str(track2.valid)+')') + similar = False + if (abs(track1.invr-track2.invr)>INVR_THRESHOLD): + if (verbose): + print('1/R differs ('+str(track1.invr)+','+str(track2.invr)+')') + similar = False + if (abs(track1.phi0-track2.phi0)>PHI0_THRESHOLD): + if (verbose): + print('phi differs ('+str(track1.phi0)+','+str(track2.phi0)+')') + similar = False + if (abs(track1.chi2rphi-track2.chi2rphi)>CHI2RPHI_THRESHOLD): + if (verbose): + print('chi^2(r-phi) differs ('+str(track1.chi2rphi)+','+str(track2.chi2rphi)+')') + similar = False + if (abs(track1.tanl-track2.tanl)>TANL_THRESHOLD): + if (verbose): + print('tanL differs ('+str(track1.tanl)+','+str(track2.tanl)+')') + similar = False + if (abs(track1.z0-track2.z0)>Z0_THRESHOLD): + if (verbose): + print('z0 differs ('+str(track1.z0)+','+str(track2.z0)+')') + similar = False + if (abs(track1.chi2rz-track2.chi2rz)>CHI2RZ_THRESHOLD): + if (verbose): + print('chi^2(r-z) differs ('+str(track1.chi2rz)+','+str(track2.chi2rz)+')') + similar = False + if (abs(track1.d0-track2.d0)>D0_THRESHOLD): + if (verbose): + print('d0 differs ('+str(track1.d0)+','+str(track2.d0)+')') + similar = False + if (abs(track1.bendchi2-track2.bendchi2)>BENDCHI2_THRESHOLD): + if (verbose): + print('bendchi2 differs ('+str(track1.bendchi2)+','+str(track2.bendchi2)+')') + similar = False + if (track1.hitpattern != track2.hitpattern): + if (verbose): + print('hit pattern differs ('+hex(track1.hitpattern)+','+hex(track2.hitpattern)+')') + similar = False + if (abs(track1.tqmva-track2.tqmva)>TQMVA_THRESHOLD): + if (verbose): + print('Quality MVA differs ('+str(track1.tqmva)+','+str(track2.tqmva)+')') + similar = False + if (track1.extramva != track2.extramva): + if (verbose): + print('Extra MVA bits differ ('+str(track1.extramva)+','+str(track2.extramva)+')') + similar = False + return similar + +def get_empdata(filename, channel, first_frame, last_frame): + '''Gets hex string from EMP data in file with filename for a specific frame + and channel. Returns list of hex strings + + filename string, name of file to open + channel int, channel number in file (i.e. column, not column number) + first_frame int, first frame to read (inclusive) + last_frame int, last frame to read (not inclusive). + ''' + interested_frames = [] + with open(filename,'r') as input_file: + content = input_file.read().split('\n') + for iframe in range(first_frame,last_frame): + interested_frames.append(content[iframe+4]) + data = [] + for frame in interested_frames: + data.append(frame.split()[channel*2+3]) + return data + +def trim_empdata(data): + '''Removes trailing all-zero strings from EMP data + + data list of strings of hex characters ex. from get_empdata + ''' + while data[-1] == '0000000000000000': + data.pop() + if len(data)==0: + return data + return data + +def empdata_to_kftracks(data): + '''Convert EMP data (64-bit words) to (96-bit) track finder tracks. Returns + list of KfTrack objects + + data list of 64-bit (16 char) hex strings representing data from EMP + ''' + if (len(data)%3 == 0): + kf_tracks = [] + for iframe in range(0,len(data),3): + kf_tracks.append(KfTrack(data[iframe]+data[iframe+1][:8])) + kf_tracks.append(KfTrack(data[iframe+1][8:]+data[iframe+2])) + return kf_tracks + if (len(data)%3 == 2): + kf_tracks = [] + for iframe in range(0,len(data)-2,3): + kf_tracks.append(KfTrack(data[iframe]+data[iframe+1][:8])) + kf_tracks.append(KfTrack(data[iframe+1][8:]+data[iframe+2])) + kf_tracks.append(KfTrack(data[-2]+data[-1][:8])) + return kf_tracks + else: + print(data) + raise ValueError('Unexpected EMP data length.') + +def interpret_fpga1output(filename, event): + '''Reads EMP data output of FPGA1 for a given event and formats the output + as a list of lists of AS data and merged TPAR data + + filename name of file to read + event event in file + ''' + #setup output + offset = 3 + result = [] + for AS_index in range(48): + result.append([]) + for MPAR_index in range(15): + result.append([]) + result.append([]) #for BX + + #read EMP input + data_channels = dict() + for channel in range(4,55): + #currently setup for simulation column numbering, may need to change for real apollo + if channel < 16: + channel_in_file = channel-4 + elif channel < 20: + continue + else: + channel_in_file = channel-8 + data_channels[channel] = get_empdata(filename, channel_in_file, + 108*event+offset, 108*(event+1)-6+offset) + for clock_cycle in range(102): + #parse EMP into pieces + AS_string = '' #48 + MPAR_string = '' #15 + BX_string = '' + for channel in range(35,3,-1): + if channel<20 and channel>15: + continue + if channel==35: + #skip first 16 bits + AS_string += data_channels[channel][clock_cycle][4:] + else: + AS_string += data_channels[channel][clock_cycle] + for channel in range(53,35,-1): + if channel==53: + #skip first 12 bits + MPAR_string += data_channels[channel][clock_cycle][3:] + else: + MPAR_string += data_channels[channel][clock_cycle] + BX_string = data_channels[54][clock_cycle][15] + AS_bitmap = Bitmap(AS_string) + MPAR_bitmap = Bitmap(MPAR_string) + #reassemble pieces + for AS_index in range(48): + reverse_index = 47-AS_index + result[AS_index].append( + AS_bitmap.substring((reverse_index+1)*37,reverse_index*37).to_hexstring()) + for MPAR_index in range(15): + reverse_index = 14-MPAR_index + result[MPAR_index+48].append( + MPAR_bitmap.substring((reverse_index+1)*76,reverse_index*76).to_hexstring()) + result[48+15].append(BX_string) + + return result + +if __name__=='__main__': + + parser = argparse.ArgumentParser() + parser.add_argument('-e','--emu_filename',default='mem/pre.txt') + #parser.add_argument('-c','--cmp_filename',default='mem/out.txt') + args = parser.parse_args() + + results = interpret_fpga1output('mem/tf1_sim_out.txt',0) + for i in range(len(results)): + print('Bit strings') + print(results[i]) + + #n_event = 100 + #n_track = 0 + #n_fail_event = 0 + #n_fail_track = 0 + + ##Do comparison + #if (print_event < 0): + # for ievent in range(100): + # initial_frame = ievent*108+6 + # final_frame = (ievent+1)*108-1 + + # emu_tracks = [] + # sim_tracks = [] + # if not args.reducedconfig: + # emu_tracks += empdata_to_kftracks(trim_empdata(get_empdata(args.emu_filename, 7, initial_frame, final_frame))) + # emu_tracks += empdata_to_kftracks(trim_empdata(get_empdata(args.emu_filename, 6, initial_frame, final_frame))) + # sim_tracks += empdata_to_kftracks(trim_empdata(get_empdata(args.cmp_filename, 0, initial_frame, final_frame))) + # sim_tracks += empdata_to_kftracks(trim_empdata(get_empdata(args.cmp_filename, 1, initial_frame, final_frame))) + # else: + # emu_tracks += empdata_to_kftracks(trim_empdata(get_empdata(args.emu_filename, 7, initial_frame, final_frame))) + # sim_tracks += empdata_to_kftracks(trim_empdata(get_empdata(args.cmp_filename, 1, initial_frame, final_frame))) + + # n_event_fail_track = 0 + # fail_reason = '' + + # if len(emu_tracks)!=len(sim_tracks): + # fail_reason += ('Different number of tracks ('+str(len(emu_tracks))+','+str(len(sim_tracks))+'). ') + # n_event_fail_track += len(emu_tracks) + # else: + # for itrack in range(len(emu_tracks)): + # comp = (emu_tracks[itrack]==sim_tracks[itrack]) + # if not args.strictcompare: + # comp = loose_compare(emu_tracks[itrack], sim_tracks[itrack], True) + # if not comp: + # fail_reason += ('Track '+str(itrack)+' differs. ') + # n_event_fail_track += 1 + + # n_track += len(emu_tracks) + # n_fail_track += n_event_fail_track + # if (n_event_fail_track>0): + # n_fail_event += 1 + # print('Event '+str(ievent)+' does not match. '+fail_reason) + # + # print('Failing events: '+str(n_fail_event)+'/'+str(n_event)) + # print('Failing tracks: '+str(n_fail_track)+'/'+str(n_track)) + # + ##Do printout + #else: + # for ievent in range(print_event,print_event+1): + # initial_frame = ievent*108+6 + # final_frame = (ievent+1)*108-1 + # if not args.reducedconfig: + # emu_tracks = empdata_to_kftracks(trim_empdata(get_empdata(args.emu_filename, 7, initial_frame, final_frame))) + # sim_tracks = empdata_to_kftracks(trim_empdata(get_empdata(args.cmp_filename, 0, initial_frame, final_frame))) + # print('Emu tracks (+eta):') + # for track in emu_tracks: + # print_track_info(track) + # print('Sim tracks (+eta):') + # for track in sim_tracks: + # print_track_info(track) + # emu_tracks = empdata_to_kftracks(trim_empdata(get_empdata(args.emu_filename, 6, initial_frame, final_frame))) + # sim_tracks = empdata_to_kftracks(trim_empdata(get_empdata(args.cmp_filename, 1, initial_frame, final_frame))) + # print('Emu tracks (-eta):') + # for track in emu_tracks: + # print_track_info(track) + # print('Sim tracks (-eta):') + # for track in sim_tracks: + # print_track_info(track) + # else: + # emu_tracks = empdata_to_kftracks(trim_empdata(get_empdata(args.emu_filename, 7, initial_frame, final_frame))) + # sim_tracks = empdata_to_kftracks(trim_empdata(get_empdata(args.cmp_filename, 1, initial_frame, final_frame))) + # print('Emu tracks:') + # for track in emu_tracks: + # print_track_info(track) + # print('Sim tracks:') + # for track in sim_tracks: + # print_track_info(track) + + diff --git a/IntegrationTests/common/script/emp/include_cores.py b/IntegrationTests/common/script/emp/include_cores.py index 794c66d05e3..780cc4d426a 100644 --- a/IntegrationTests/common/script/emp/include_cores.py +++ b/IntegrationTests/common/script/emp/include_cores.py @@ -8,16 +8,18 @@ # Optional arguments parser.add_argument("-s", "--script_path", dest="scriptPath", help="directory containing compiled HLS", type=str, default="../../IRtoTB/script") +parser.add_argument("-o", "--output_file", dest="outputFile", help="script that will add HLS to project", type=str, default="scripts/xciMaker") +parser.add_argument("-f", "--sub_path", dest="subPath", help="location within cgn to copy HLS IPs", type=str, default="") # Parse arguments args = parser.parse_args() # List of things to substitute to get the cores nickname -sub_froms = ["solution_", "InputRouterTop_IR_DTC", "VMRouterCMTop", "VMRouterTop", "TrackletEngine", "TrackletCalculator", "TrackletProcessor", "ProjectionRouterTop", "MatchEngineTop", "MatchCalculator", "MatchProcessor", "TrackBuilder"] -sub_tos = ["", "IR", "VMR", "VMR", "TE", "TC", "TP", "PR", "ME", "MC", "MP", "FT"] +sub_froms = ["solution_", "InputRouterTop_IR_DTC", "VMRouterCMTop", "VMRouterTop", "TrackletEngine", "TrackletCalculator", "TrackletProcessor", "ProjectionRouterTop", "MatchEngineTop", "MatchCalculator", "MatchProcessor", "TrackBuilder","ProjectionCalculator", "VMStubMERouterTop"] +sub_tos = ["", "IR", "VMR", "VMR", "TE", "TC", "TP", "PR", "ME", "MC", "MP", "FT","PC","VMSMER"] #create file and write first line -core_file = 'scripts/xciMaker' +core_file = args.outputFile part = 'xcvu7p-flvb2104-2-e' dir_path = 'cgn' f = open(core_file, "w") @@ -49,7 +51,7 @@ #if (core_name.find('ME') != -1): # core_name = core_name + "PHIB" #f.write("tool_add_core -level 0 -inst " + core_name + " " + core_dir_complete + "\n") - os.symlink('../' + core_dir_folder, dir_path + '/' + core_name) + os.symlink('../../' + core_dir_folder, dir_path + '/' + args.subPath + '/' + core_name) core_names.append(core_name) f.write(core_name + ":\n") f.write("\tvivado -nolog -nojou -mode batch -source scripts/ip_tools.tcl -tclargs " + core_name + " " + core_dir_folder + " " + part + " " + core_dir_complete + "\n") diff --git a/IntegrationTests/common/script/emp/kf_link_mod.py b/IntegrationTests/common/script/emp/kf_link_mod.py index a9fee26b6f2..7ca9d46cb94 100644 --- a/IntegrationTests/common/script/emp/kf_link_mod.py +++ b/IntegrationTests/common/script/emp/kf_link_mod.py @@ -5,8 +5,11 @@ import sys file_to_mod = '../../../../KalmanFilter/kfin/firmware/hdl/kfin_layerEncoding.vhd' +if 'DualFPGA' in os.getcwd(): + file_to_mod = '../../../KalmanFilter/kfin/firmware/hdl/kfin_layerEncoding.vhd' search_line_string = ' file f: text open read_mode is "/heplnw039/tschuh/work/src/l1tk-for-emp/kfin/firmware/luts/layerEncoding.mem";' -replace_line_path = os.path.abspath('../../../../KalmanFilter/kfin/firmware/luts/layerEncoding.mem') +replace_line_path = os.path.abspath('../../../KalmanFilter/kfin/firmware/luts/layerEncoding.mem') +#replace_line_path = os.path.abspath('../../../../KalmanFilter/kfin/firmware/luts/layerEncoding.mem') replace_line_string = ' file f: text open read_mode is "' + replace_line_path + '";' diff --git a/IntegrationTests/common/script/emp/lut_copy.py b/IntegrationTests/common/script/emp/lut_copy.py deleted file mode 100644 index 5000c2be5a3..00000000000 --- a/IntegrationTests/common/script/emp/lut_copy.py +++ /dev/null @@ -1,24 +0,0 @@ -import argparse - -# Create argument parser -parser = argparse.ArgumentParser(description="Add pre synth instructions.") - -# Optional arguments -parser.add_argument("-s", "--pre_synth_file", dest="preSynthPath", help="pre-synth file", type=str, default="../../../../../emp-fwk/components/info/firmware/cfg/set_generics_presynth.tcl") - -# Parse arguments -args = parser.parse_args() - -# Already added the line? -with open(args.preSynthPath) as psf: - for line in psf: - pass - last_line = line - -# Add lines -if (last_line != "# LUTs added"): - with open(args.preSynthPath, "a") as presynth_file: - presynth_file.write("\n# Copy LUTs to xsim or synth_1 directory") - presynth_file.write("\nfile delete -force ./LUTs") - presynth_file.write("\nfile copy -force ../../../../../src/firmware-hls/emData/LUTsCMReduced ./LUTs") - presynth_file.write("\n# LUTs added") diff --git a/IntegrationTests/common/script/emp/pre_msim.tcl b/IntegrationTests/common/script/emp/pre_msim.tcl deleted file mode 100644 index c3debb272a5..00000000000 --- a/IntegrationTests/common/script/emp/pre_msim.tcl +++ /dev/null @@ -1,3 +0,0 @@ -# Copy LUTs to xsim or synth_1 directory -file delete -force ./LUTs -file copy -force ../../../../../../../src/firmware-hls/emData/LUTsCMReduced ./LUTs diff --git a/IntegrationTests/common/script/emp/pre_qsim.tcl b/IntegrationTests/common/script/emp/pre_qsim.tcl deleted file mode 100644 index 08b7ab6ebd6..00000000000 --- a/IntegrationTests/common/script/emp/pre_qsim.tcl +++ /dev/null @@ -1,3 +0,0 @@ -# Copy LUTs to xsim or synth_1 directory -file delete -force ./LUTs -file copy -force ../../src/firmware-hls/emData/LUTsCMReduced ./LUTs diff --git a/KalmanFilter b/KalmanFilter index f265d5a3af3..3ebaccdc062 160000 --- a/KalmanFilter +++ b/KalmanFilter @@ -1 +1 @@ -Subproject commit f265d5a3af3120d015c9b203fd2ecb30acfc8a37 +Subproject commit 3ebaccdc0626a359d10f0928c3b69326685c7449 diff --git a/README.md b/README.md index 473870cc31e..07cda75c56f 100644 --- a/README.md +++ b/README.md @@ -276,128 +276,14 @@ In order to keep the GitHub repository public we use GitHub Actions and GitLab C ## EMP -Build the tracklet chain in EMP. +This section details how to the track finder firmware can be integrated in the EMP framework and deployed on an Apollo board. -Currently the supported chain configurations for EMP builds are: +### Building EMP -* **Skinny Chain (combined, unsplit modules)** - * InputRouter to KalmanFilter - * Target = Apollo VU13P (1 FPGA) - * EMP build path = `IntegrationTests/ReducedCombinedConfig/IRtoKF` +In order to reduce the number of redundant locations for EMP build instructions (and thus to reduce out-of-date information), please find the most recent EMP build instructions on the [apollo site](https://apollo-lhc.gitlab.io/cornell-cm/Manual/TFFirmware/02-EMPTF/). -* **Barrel Chain (combined, unsplit modules)** - * InputRouter to KalmanFilter - * Target = Apollo VU13P (1 FPGA) - * EMP build path = `IntegrationTests/CombinedBarrelConfig/IRtoKF` - -* **Some info** +### Information for developers - * The EMP firmware uses a subset of the [SURF library](https://github.com/slaclab/surf). - More info on that in `IntegrationTests/common/hdl/surf_subset/README.md` (Note: this may be unused for the IRtoKF chain) - * `firmware-hls/KalmanFilter` is a git sub-module link to the repo containing the [Kalman Filter firmware repo](https://github.com/cms-L1TK/l1tk-for-emp/tree/d0d3ba506bf77926862f0d7f3ebf781c041da6eb). Note that different KalmanFilter configurations are needed for the reduced chain, the barrel chain, and the full chain. The Makefile updates this repository to point to the appropriate branch, but if possible, it could be useful for the KalmanFilter repository to support different configurations. - * Some python and TCL scripts are needed to implement and simulate the EMP firmware. - More info on that in [this README](https://github.com/cms-L1TK/firmware-hls/blob/doc_emp/IntegrationTests/ReducedConfig/IRtoKF/firmware/scripts/README.md). +Currently, the EMP build is created in multiple steps. First, one runs the fpga1, fpga2, or all rule in [this makefile](IntegrationTests/DualFPGA/firmware/Makefile), which in turns runs the makefiles in the `CombinedConfig_FPGA1` or `CombinedConfig_FPGA2` integration tests to download necessary LUTs/MemPrints, generate the pattern recognition VHDL wrapper, and compile the pattern recognition HLS modules. This is currently done with Vivado 2020 or earlier since the pattern recognition HLS is incompatible with Vitis, the successor to Vivado HLS. -* **Note** See [here](https://apollo-lhc.gitlab.io/cornell-cm/Manual/TFFirmware/02-EMPTF/) for more detailed instructions, particularly with regards to installing the prerequisites noted below and for performing tests on Apollo hardware. - -### Prerequisites - -* Xilinx Vivado 2020.1 (HLS build) and 2021.2 (project build) -* ipbb: The [IPbus Builder Tool](https://github.com/ipbus/ipbb) incl. uHAL. Tested with dev/2022g -* Python 3 -* Questasim v2021.1_2 for Questa simulation - -### Quick instructions - -**Step 1: Setup the work area** - -First source Xilinx Vivado 2020.1 - -``` -ipbb init -cd -ipbb add git ssh://git@gitlab.cern.ch:7999/p2-xware/firmware/emp-fwk.git -b v0.8.0 -ipbb add git https://github.com/apollo-lhc/CM_FPGA_FW -b v2.2.1 -ipbb add git https://gitlab.cern.ch/ttc/legacy_ttc.git -b v2.1 -ipbb add git ssh://git@gitlab.cern.ch:7999/cms-tcds/cms-tcds2-firmware.git -b v0_1_1 -ipbb add git https://gitlab.cern.ch/HPTD/tclink.git -r fda0bcf -ipbb add git https://github.com/ipbus/ipbus-firmware -b v1.9 -ipbb add git https://gitlab.cern.ch/dth_p1-v2/slinkrocket_ips.git -b v03.09 -ipbb add git ssh://git@gitlab.cern.ch:7999/dth_p1-v2/slinkrocket.git -b v03.10 -ipbb add git https://gitlab.cern.ch/gbt-fpga/gbt-fpga.git -b gbt_fpga_6_1_0 -ipbb add git https://gitlab.cern.ch/gbt-fpga/lpgbt-fpga.git -b v.2.1 -ipbb add git https://:@gitlab.cern.ch:8443/gbtsc-fpga-support/gbt-sc.git -b gbt_sc_4_1 -ipbb add git https://github.com/cms-L1TK/firmware-hls.git -``` - -*Note: You need to be a member of the `cms-tcds2-users` egroup in order to clone the `cms-tcds2-firmware` repository. In order to add yourself to that egroup, go to the "Members" tab of [this page](https://e-groups.cern.ch/e-groups/Egroup.do?egroupId=10380295), and click on the "Add me" button; you may need to wait ~ 24 hours to get access to the GitLab repo.* - -``` -cd src/firmware-hls -make -C /firmware -cd - -``` - -Source Xilinx Vivado 2021.2 for the following steps - -### Vivado/Questa Simulation - -**Step 2: Create an ipbb project area** - -* For questa simulation testbench: -``` -ipbb proj create sim qsim firmware-hls: 'qsim.dep' -cd proj/qsim -``` - -* For vivado simulation testbench: -``` -ipbb proj create vivado vsim firmware-hls: 'vsim.dep' -cd proj/vsim -``` - -**Step 3: Simulation** - -* For questa simulation testbench: - -``` -ipbb sim setup-simlib -ipbb sim ipcores -ipbb sim fli-udp -ipbb sim generate-project #(rerun this if you change VHDL) - -./run_sim -c xil_defaultlib.top -Gsourcefile= -Gsinkfile= -Gplaylen=xyz -Gcaplen=xyz -do 'run 50.0us' -do quit -``` -where `xyz = number of events * 108`, where default is 9 events. - -where `input.txt` follows the standard EMP pattern file convention. An input file is provided in `../../src/firmware-hls//firmware/mem/in.txt` - -* For vivado simulation testbench -``` -ipbb vivado generate-project -cd vsim -vivado vsim.xpr -``` - -and start the simulation from GUI (first time will take long). - -### Implementation - -**Step 2: Create an ipbb project area** - -``` -ipbb proj create vivado apollo firmware-hls: 'apollo.dep' -cd proj/apollo -``` - -**Step 3: Compile** - -*Note: Note: For the following commands, you need to ensure that can find & use the `gen_ipbus_addr_decode` script - e.g. for a standard uHAL installation:* -``` -export PATH=/opt/cactus/bin/uhal/tools:$PATH LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH -``` - -``` -ipbb ipbus gendecoders -ipbb vivado generate-project synth -j8 impl -j8 package -``` +Next, the project is generated using the ipbb tool. One points ipbb to one of the configuration files in [this directory](IntegrationTests/DualFPGA/firmware/cfg/), which ipbb uses to generate the project. This includes adding relevant source and constraint files, running any setup tcl scripts, and recursively calling other configuration files in other dependencies such as `emp-fwk` and the KalmanFilter fit, which is currently included as a submodule in this repository.