TrackBuilder updates

[aehart]

This PR makes three updates to the TrackBuilder:

• The TrackBuilder now outputs something on every iteration. Previously, if the track that was built had too few matches, nothing would be written in the C++. Now, an invalid track is written, thus simulating the gaps in valid output that are present in the FW.
• A "done" signal has been added, which goes high for one clock cycle when no more full matches are available for processing. Hopefully, this addresses DR wishes an extra done signal from TB #307.
• The latency pragma has been added to the main processing loop. This is so that the latency of each TrackBuilder is the same, which I believe simplifies integration into chains with multiple TrackBuilders.

The latency and pipelining of the L1L2 TrackBuilder is unchanged, while the minimum clock period reported by HLS improves slightly from 3.486 ns to 3.420 ns. The LUT usage decreases slightly, while the FF usage increases:

	L1L2 before	L1L2 after
BRAM_18K	0	0
DSP48E	0	0
FF	7841	10908
LUT	35359	34445
URAM	0	0