diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile
index 60f77af59f1..6537846ba0a 100644
--- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile
+++ b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile
@@ -4,7 +4,7 @@ input_file = mem/in.txt
 proj_path = ../../../../proj
 hls_script_path = ../../script
 
-all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion
+all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input
 
 $(core_dir):
 	@mkdir cgn mem
@@ -32,9 +32,6 @@ add_common_files:
 hdl_add_files: $(core_file)
 	cd hdl; ln -s ../../../hdl/*.vhd .
 
-lut_inclusion:
-	@python3 scripts/lut_copy.py
-
 $(input_file): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsCMBarrel/InputStubs -o $(input_file)
 
diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/lut_copy.py b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/lut_copy.py
deleted file mode 100644
index 945f4de3de6..00000000000
--- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/lut_copy.py
+++ /dev/null
@@ -1,24 +0,0 @@
-import argparse
-
-# Create argument parser
-parser = argparse.ArgumentParser(description="Add pre synth instructions.")
-
-# Optional arguments
-parser.add_argument("-s", "--pre_synth_file", dest="preSynthPath", help="pre-synth file", type=str, default="../../../../../emp-fwk/components/info/firmware/cfg/set_generics_presynth.tcl")
-
-# Parse arguments
-args = parser.parse_args()
-
-# Already added the line?
-with open(args.preSynthPath) as psf:
-    for line in psf:
-        pass
-    last_line = line
-
-# Add lines
-if (last_line != "# LUTs added"):
-    with open(args.preSynthPath, "a") as presynth_file:
-        presynth_file.write("\n# Copy LUTs to xsim or synth_1 directory")
-        presynth_file.write("\nfile delete -force ./LUTs")
-        presynth_file.write("\nfile copy -force ../../../../../src/firmware-hls/emData/LUTsCMBarrel ./LUTs")
-        presynth_file.write("\n# LUTs added")
diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl
deleted file mode 100644
index 6a4bb777631..00000000000
--- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Copy LUTs to xsim or synth_1 directory
-file delete -force ./LUTs
-file copy -force ../../../../../../../src/firmware-hls/emData/LUTsCMBarrel ./LUTs
diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl
deleted file mode 100644
index e67aae690e5..00000000000
--- a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt
-set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl ]]
-append lut_script "/pre_msim.tcl"
-add_files -fileset utils_1 -norecurse $lut_script
-#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1]
-#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt
-set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]"
-eval ${pre_path}
-
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top top [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-set_property target_language VHDL [current_project]
-set_property simulator_language VHDL [current_project]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
diff --git a/IntegrationTests/DualFPGA/firmware/Makefile b/IntegrationTests/DualFPGA/firmware/Makefile
index b2fb4d231f4..98cbee6dba1 100644
--- a/IntegrationTests/DualFPGA/firmware/Makefile
+++ b/IntegrationTests/DualFPGA/firmware/Makefile
@@ -6,11 +6,11 @@ input_file_fpga2 = mem/in_fpga2.txt
 fpga1_hls_script_path = ../../CombinedConfig_FPGA1/script 
 fpga2_hls_script_path = ../../CombinedConfig_FPGA2/script
 
-all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2 lut_inclusion
+all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2 
 
-fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1 lut_inclusion
+fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1
 
-fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2 lut_inclusion
+fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2 
 
 $(core_dir):
 	@mkdir cgn mem
@@ -50,9 +50,6 @@ hdl_add_files_fpga2: $(core_file)
 	cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/SectorProcessor.vhd SectorProcessor_f2.vhd
 	cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/memUtil_pkg.vhd memUtil_pkg_f2.vhd
 
-lut_inclusion:
-	@python3 scripts/lut_copy_dual.py
-
 $(input_file_fpga1): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsSplit/InputStubs -o $(input_file_fpga1)
 
@@ -65,4 +62,4 @@ apollo_input_fpga1: $(input_file_fpga1)
 apollo_input_fpga2: $(input_file_fpga2)
 	@python3 scripts/split_emp_input.py -i $(input_file_fpga2) -o mem/in_fpga2_
 
-.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2 lut_inclusion 
+.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2 
diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
index 9e3df9f3cc2..9a6ac6946df 100644
--- a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
+++ b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
@@ -3,15 +3,14 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f1.dep
-setup ../ucf/vsim_f1.tcl
+setup ../ucf/vsim.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f1.vhd
 src emp_project_decl_f1.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-
-src -u sim ../scripts/pre_msim.tcl
+src ../mem/in_fpga1.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep
diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
index 3d429e7ffaa..c079df8f08b 100644
--- a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
+++ b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
@@ -3,15 +3,14 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f2.dep
-setup ../ucf/vsim_f2.tcl
+setup ../ucf/vsim.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f2.vhd
 src emp_project_decl_f2.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-
-src -u sim ../scripts/pre_msim.tcl
+src ../mem/in_fpga2.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep
diff --git a/IntegrationTests/DualFPGA/firmware/scripts/lut_copy.py b/IntegrationTests/DualFPGA/firmware/scripts/lut_copy.py
deleted file mode 100644
index 51a0f08c80f..00000000000
--- a/IntegrationTests/DualFPGA/firmware/scripts/lut_copy.py
+++ /dev/null
@@ -1,24 +0,0 @@
-import argparse
-
-# Create argument parser
-parser = argparse.ArgumentParser(description="Add pre synth instructions.")
-
-# Optional arguments
-parser.add_argument("-s", "--pre_synth_file", dest="preSynthPath", help="pre-synth file", type=str, default="../../../../emp-fwk/components/info/firmware/cfg/set_generics_presynth.tcl")
-
-# Parse arguments
-args = parser.parse_args()
-
-# Already added the line?
-with open(args.preSynthPath) as psf:
-    for line in psf:
-        pass
-    last_line = line
-
-# Add lines
-if (last_line != "# LUTs added"):
-    with open(args.preSynthPath, "a") as presynth_file:
-        presynth_file.write("\n# Copy LUTs to xsim or synth_1 directory")
-        presynth_file.write("\nfile delete -force ./LUTs")
-        presynth_file.write("\nfile copy -force ../../../../../src/firmware-hls/emData/LUTsCM ./LUTs")
-        presynth_file.write("\n# LUTs added")
diff --git a/IntegrationTests/DualFPGA/firmware/scripts/lut_copy_dual.py b/IntegrationTests/DualFPGA/firmware/scripts/lut_copy_dual.py
deleted file mode 100644
index 51a0f08c80f..00000000000
--- a/IntegrationTests/DualFPGA/firmware/scripts/lut_copy_dual.py
+++ /dev/null
@@ -1,24 +0,0 @@
-import argparse
-
-# Create argument parser
-parser = argparse.ArgumentParser(description="Add pre synth instructions.")
-
-# Optional arguments
-parser.add_argument("-s", "--pre_synth_file", dest="preSynthPath", help="pre-synth file", type=str, default="../../../../emp-fwk/components/info/firmware/cfg/set_generics_presynth.tcl")
-
-# Parse arguments
-args = parser.parse_args()
-
-# Already added the line?
-with open(args.preSynthPath) as psf:
-    for line in psf:
-        pass
-    last_line = line
-
-# Add lines
-if (last_line != "# LUTs added"):
-    with open(args.preSynthPath, "a") as presynth_file:
-        presynth_file.write("\n# Copy LUTs to xsim or synth_1 directory")
-        presynth_file.write("\nfile delete -force ./LUTs")
-        presynth_file.write("\nfile copy -force ../../../../../src/firmware-hls/emData/LUTsCM ./LUTs")
-        presynth_file.write("\n# LUTs added")
diff --git a/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl b/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl
deleted file mode 100644
index fe3078a28af..00000000000
--- a/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Copy LUTs to xsim or synth_1 directory
-file delete -force ./LUTs
-file copy -force ../../../../../../../src/firmware-hls/emData/LUTsCM ./LUTs
diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl
deleted file mode 100644
index a52cf7a04e0..00000000000
--- a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga1.txt
-set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl ]]
-append lut_script "/pre_msim.tcl"
-add_files -fileset utils_1 -norecurse $lut_script
-#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1]
-#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt
-set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]"
-eval ${pre_path}
-
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top top [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-set_property target_language VHDL [current_project]
-set_property simulator_language VHDL [current_project]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl
deleted file mode 100644
index 6bd684727c0..00000000000
--- a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga2.txt
-set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl ]]
-append lut_script "/pre_msim.tcl"
-add_files -fileset utils_1 -norecurse $lut_script
-#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1]
-#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt
-set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]"
-eval ${pre_path}
-
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top top [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-set_property target_language VHDL [current_project]
-set_property simulator_language VHDL [current_project]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile
index 2d41486f8b8..6fbec263cac 100644
--- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile
+++ b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile
@@ -4,7 +4,7 @@ input_file = mem/in.txt
 proj_path = ../../../../proj
 hls_script_path = ../../script
 
-all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion
+all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input
 
 $(core_dir):
 	@mkdir cgn mem
@@ -32,9 +32,6 @@ add_common_files:
 hdl_add_files: $(core_file)
 	cd hdl; ln -s ../../../hdl/*.vhd .
 
-lut_inclusion:
-	@python3 scripts/lut_copy.py
-
 $(input_file): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsReducedCM/InputStubs -o $(input_file)
 
@@ -53,4 +50,4 @@ sim: $(input_file) $(core_file) $(core_dir)
 	@cd $(hls_script_path); vivado -mode batch -source runSim.tcl
 	@python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt
 
-.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input lut_inclusion core_patch
+.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/lut_copy.py b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/lut_copy.py
deleted file mode 100644
index 5000c2be5a3..00000000000
--- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/lut_copy.py
+++ /dev/null
@@ -1,24 +0,0 @@
-import argparse
-
-# Create argument parser
-parser = argparse.ArgumentParser(description="Add pre synth instructions.")
-
-# Optional arguments
-parser.add_argument("-s", "--pre_synth_file", dest="preSynthPath", help="pre-synth file", type=str, default="../../../../../emp-fwk/components/info/firmware/cfg/set_generics_presynth.tcl")
-
-# Parse arguments
-args = parser.parse_args()
-
-# Already added the line?
-with open(args.preSynthPath) as psf:
-    for line in psf:
-        pass
-    last_line = line
-
-# Add lines
-if (last_line != "# LUTs added"):
-    with open(args.preSynthPath, "a") as presynth_file:
-        presynth_file.write("\n# Copy LUTs to xsim or synth_1 directory")
-        presynth_file.write("\nfile delete -force ./LUTs")
-        presynth_file.write("\nfile copy -force ../../../../../src/firmware-hls/emData/LUTsCMReduced ./LUTs")
-        presynth_file.write("\n# LUTs added")
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl
deleted file mode 100644
index c3debb272a5..00000000000
--- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Copy LUTs to xsim or synth_1 directory
-file delete -force ./LUTs
-file copy -force ../../../../../../../src/firmware-hls/emData/LUTsCMReduced ./LUTs
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl
deleted file mode 100644
index 2ec077c64b3..00000000000
--- a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/mem/in.txt
-set lut_script [file dirname [file normalize ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl ]]
-append lut_script "/pre_msim.tcl"
-add_files -fileset utils_1 -norecurse $lut_script
-#set_property STEPS.SYNTH_DESIGN.TCL.PRE $lut_script [get_runs sim_1]
-#add_files -fileset sim_1 -norecurse ../../src/firmware-hls/firmware/mem/out.txt
-set pre_path "set_property -name {xsim.compile.tcl.pre} -value {$lut_script} -objects \[\get_filesets \sim_1\]"
-eval ${pre_path}
-
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top top [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-set_property target_language VHDL [current_project]
-set_property simulator_language VHDL [current_project]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
diff --git a/IntegrationTests/common/cfg/qsim.dep b/IntegrationTests/common/cfg/qsim.dep
index c448086b216..0ddc6209970 100644
--- a/IntegrationTests/common/cfg/qsim.dep
+++ b/IntegrationTests/common/cfg/qsim.dep
@@ -3,7 +3,6 @@
 
 # Dependancies
 include -c emp-fwk:boards/testbench top.dep
-setup ../scripts/pre_qsim.tcl
 
 include payload.dep
 src common/hdl/emp/tb_decl.vhd
diff --git a/IntegrationTests/common/cfg/vsim.dep b/IntegrationTests/common/cfg/vsim.dep
index 8f982110dc3..61199b21ce7 100644
--- a/IntegrationTests/common/cfg/vsim.dep
+++ b/IntegrationTests/common/cfg/vsim.dep
@@ -15,6 +15,5 @@ src -c emp-fwk:components/links/slink emp_slink_types.vhd
 #src -c emp-fwk:components/framework emp_framework_decl.vhd 
 
 #src -u sim ../mem/in.txt
-src -u sim ../scripts/pre_msim.tcl
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2.dep
diff --git a/IntegrationTests/common/script/emp/pre_qsim.tcl b/IntegrationTests/common/script/emp/pre_qsim.tcl
deleted file mode 100644
index 08b7ab6ebd6..00000000000
--- a/IntegrationTests/common/script/emp/pre_qsim.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Copy LUTs to xsim or synth_1 directory
-file delete -force ./LUTs
-file copy -force ../../src/firmware-hls/emData/LUTsCMReduced ./LUTs
diff --git a/IntegrationTests/common/ucf/vsim.tcl b/IntegrationTests/common/ucf/vsim.tcl
new file mode 100644
index 00000000000..345b5f84c7f
--- /dev/null
+++ b/IntegrationTests/common/ucf/vsim.tcl
@@ -0,0 +1,10 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
diff --git a/README.md b/README.md
index 473870cc31e..07cda75c56f 100644
--- a/README.md
+++ b/README.md
@@ -276,128 +276,14 @@ In order to keep the GitHub repository public we use GitHub Actions and GitLab C
 
 ## EMP
 
-Build the tracklet chain in EMP.
+This section details how to the track finder firmware can be integrated in the EMP framework and deployed on an Apollo board.
 
-Currently the supported chain configurations for EMP builds are:
+### Building EMP
 
-* **Skinny Chain (combined, unsplit modules)**
-  * InputRouter to KalmanFilter
-    * Target = Apollo VU13P (1 FPGA)
-    * EMP build path = `IntegrationTests/ReducedCombinedConfig/IRtoKF`
+In order to reduce the number of redundant locations for EMP build instructions (and thus to reduce out-of-date information), please find the most recent EMP build instructions on the [apollo site](https://apollo-lhc.gitlab.io/cornell-cm/Manual/TFFirmware/02-EMPTF/).
 
-* **Barrel Chain (combined, unsplit modules)**
-  * InputRouter to KalmanFilter
-    * Target = Apollo VU13P (1 FPGA)
-    * EMP build path = `IntegrationTests/CombinedBarrelConfig/IRtoKF`
-    
-* **Some info**
+### Information for developers
 
-    * The EMP firmware uses a subset of the [SURF library](https://github.com/slaclab/surf).
-    More info on that in `IntegrationTests/common/hdl/surf_subset/README.md` (Note: this may be unused for the IRtoKF chain)
-    * `firmware-hls/KalmanFilter` is a git sub-module link to the repo containing the [Kalman Filter firmware repo](https://github.com/cms-L1TK/l1tk-for-emp/tree/d0d3ba506bf77926862f0d7f3ebf781c041da6eb). Note that different KalmanFilter configurations are needed for the reduced chain, the barrel chain, and the full chain. The Makefile updates this repository to point to the appropriate branch, but if possible, it could be useful for the KalmanFilter repository to support different configurations.
-    * Some python and TCL scripts are needed to implement and simulate the EMP firmware.
-    More info on that in [this README](https://github.com/cms-L1TK/firmware-hls/blob/doc_emp/IntegrationTests/ReducedConfig/IRtoKF/firmware/scripts/README.md).
+Currently, the EMP build is created in multiple steps. First, one runs the fpga1, fpga2, or all rule in [this makefile](IntegrationTests/DualFPGA/firmware/Makefile), which in turns runs the makefiles in the `CombinedConfig_FPGA1` or `CombinedConfig_FPGA2` integration tests to download necessary LUTs/MemPrints, generate the pattern recognition VHDL wrapper, and compile the pattern recognition HLS modules. This is currently done with Vivado 2020 or earlier since the pattern recognition HLS is incompatible with Vitis, the successor to Vivado HLS.
 
-* **Note** See [here](https://apollo-lhc.gitlab.io/cornell-cm/Manual/TFFirmware/02-EMPTF/) for more detailed instructions, particularly with regards to installing the prerequisites noted below and for performing tests on Apollo hardware.
-
-### Prerequisites
-
-* Xilinx Vivado 2020.1 (HLS build) and 2021.2 (project build)
-* ipbb: The [IPbus Builder Tool](https://github.com/ipbus/ipbb) incl. uHAL. Tested with dev/2022g
-* Python 3
-* Questasim v2021.1_2 for Questa simulation
-
-### Quick instructions
-
-**Step 1: Setup the work area**
-
-First source Xilinx Vivado 2020.1
-
-```
-ipbb init <project name>
-cd <project name>
-ipbb add git ssh://git@gitlab.cern.ch:7999/p2-xware/firmware/emp-fwk.git -b v0.8.0
-ipbb add git https://github.com/apollo-lhc/CM_FPGA_FW -b v2.2.1
-ipbb add git https://gitlab.cern.ch/ttc/legacy_ttc.git -b v2.1
-ipbb add git ssh://git@gitlab.cern.ch:7999/cms-tcds/cms-tcds2-firmware.git -b v0_1_1
-ipbb add git https://gitlab.cern.ch/HPTD/tclink.git -r fda0bcf
-ipbb add git https://github.com/ipbus/ipbus-firmware -b v1.9
-ipbb add git https://gitlab.cern.ch/dth_p1-v2/slinkrocket_ips.git -b v03.09
-ipbb add git ssh://git@gitlab.cern.ch:7999/dth_p1-v2/slinkrocket.git -b v03.10
-ipbb add git https://gitlab.cern.ch/gbt-fpga/gbt-fpga.git -b gbt_fpga_6_1_0
-ipbb add git https://gitlab.cern.ch/gbt-fpga/lpgbt-fpga.git -b v.2.1
-ipbb add git https://:@gitlab.cern.ch:8443/gbtsc-fpga-support/gbt-sc.git -b gbt_sc_4_1
-ipbb add git https://github.com/cms-L1TK/firmware-hls.git
-```
-
-*Note: You need to be a member of the `cms-tcds2-users` egroup in order to clone the `cms-tcds2-firmware` repository. In order to add yourself to that egroup, go to the "Members" tab of [this page](https://e-groups.cern.ch/e-groups/Egroup.do?egroupId=10380295), and click on the "Add me" button; you may need to wait ~ 24 hours to get access to the GitLab repo.*
-
-```
-cd src/firmware-hls
-make -C <EMP build path>/firmware
-cd -
-```
-
-Source Xilinx Vivado 2021.2 for the following steps
-
-### Vivado/Questa Simulation
-
-**Step 2: Create an ipbb project area**
-
-* For questa simulation testbench:
-```
-ipbb proj create sim qsim firmware-hls:<EMP build path> 'qsim.dep'
-cd proj/qsim
-```
-
-* For vivado simulation testbench:
-```
-ipbb proj create vivado vsim firmware-hls:<EMP build path> 'vsim.dep'
-cd proj/vsim
-```
-
-**Step 3: Simulation**
-
-* For questa simulation testbench:
-
-```
-ipbb sim setup-simlib
-ipbb sim ipcores
-ipbb sim fli-udp
-ipbb sim generate-project #(rerun this if you change VHDL)
-
-./run_sim -c xil_defaultlib.top -Gsourcefile=<input.txt> -Gsinkfile=<out.txt> -Gplaylen=xyz -Gcaplen=xyz -do 'run 50.0us' -do quit 
-```
-where `xyz = number of events * 108`, where default is 9 events.
-
-where `input.txt` follows the standard EMP pattern file convention. An input file is provided in `../../src/firmware-hls/<EMP build path>/firmware/mem/in.txt`
-
-* For vivado simulation testbench
-```
-ipbb vivado generate-project
-cd vsim
-vivado vsim.xpr
-```
-
-and start the simulation from GUI (first time will take long).
-
-### Implementation
-
-**Step 2: Create an ipbb project area**
-
-```
-ipbb proj create vivado apollo firmware-hls:<EMP build path> 'apollo.dep'
-cd proj/apollo
-```
-
-**Step 3: Compile**
-
-*Note: Note: For the following commands, you need to ensure that can find & use the `gen_ipbus_addr_decode` script - e.g. for a standard uHAL installation:*
-```
-export PATH=/opt/cactus/bin/uhal/tools:$PATH LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
-```
-
-```
-ipbb ipbus gendecoders
-ipbb vivado generate-project synth -j8 impl -j8 package
-```
+Next, the project is generated using the ipbb tool. One points ipbb to one of the configuration files in [this directory](IntegrationTests/DualFPGA/firmware/cfg/), which ipbb uses to generate the project. This includes adding relevant source and constraint files, running any setup tcl scripts, and recursively calling other configuration files in other dependencies such as `emp-fwk` and the KalmanFilter fit, which is currently included as a submodule in this repository.