Cleanup based on suggestions from Andrew. Also updated README

cms-L1TK · Oct 24, 2024 · 63a435e · 63a435e
1 parent ffde743
commit 63a435e
Show file tree

Hide file tree

Showing 21 changed files with 27 additions and 324 deletions.
diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/Makefile
@@ -4,7 +4,7 @@ input_file = mem/in.txt
 proj_path = ../../../../proj
 hls_script_path = ../../script
 
-all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion
+all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input
 
 $(core_dir):
 	@mkdir cgn mem
@@ -32,9 +32,6 @@ add_common_files:
 hdl_add_files: $(core_file)
 	cd hdl; ln -s ../../../hdl/*.vhd .
 
-lut_inclusion:
-	@python3 scripts/lut_copy.py
-
 $(input_file): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsCMBarrel/InputStubs -o $(input_file)
 

diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/lut_copy.py b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/lut_copy.py
diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/scripts/pre_msim.tcl
diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl
diff --git a/IntegrationTests/DualFPGA/firmware/Makefile b/IntegrationTests/DualFPGA/firmware/Makefile
@@ -6,11 +6,11 @@ input_file_fpga2 = mem/in_fpga2.txt
 fpga1_hls_script_path = ../../CombinedConfig_FPGA1/script 
 fpga2_hls_script_path = ../../CombinedConfig_FPGA2/script
 
-all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2 lut_inclusion
+all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2 
 
-fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1 lut_inclusion
+fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1
 
-fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2 lut_inclusion
+fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2 
 
 $(core_dir):
 	@mkdir cgn mem
@@ -50,9 +50,6 @@ hdl_add_files_fpga2: $(core_file)
 	cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/SectorProcessor.vhd SectorProcessor_f2.vhd
 	cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/memUtil_pkg.vhd memUtil_pkg_f2.vhd
 
-lut_inclusion:
-	@python3 scripts/lut_copy_dual.py
-
 $(input_file_fpga1): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsSplit/InputStubs -o $(input_file_fpga1)
 
@@ -65,4 +62,4 @@ apollo_input_fpga1: $(input_file_fpga1)
 apollo_input_fpga2: $(input_file_fpga2)
 	@python3 scripts/split_emp_input.py -i $(input_file_fpga2) -o mem/in_fpga2_
 
-.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2 lut_inclusion 
+.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2 
diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
@@ -3,15 +3,14 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f1.dep
-setup ../ucf/vsim_f1.tcl
+setup ../ucf/vsim.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f1.vhd
 src emp_project_decl_f1.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-
-src -u sim ../scripts/pre_msim.tcl
+src ../mem/in_fpga1.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep
diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
@@ -3,15 +3,14 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f2.dep
-setup ../ucf/vsim_f2.tcl
+setup ../ucf/vsim.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f2.vhd
 src emp_project_decl_f2.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-
-src -u sim ../scripts/pre_msim.tcl
+src ../mem/in_fpga2.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep
diff --git a/IntegrationTests/DualFPGA/firmware/scripts/lut_copy.py b/IntegrationTests/DualFPGA/firmware/scripts/lut_copy.py
diff --git a/IntegrationTests/DualFPGA/firmware/scripts/lut_copy_dual.py b/IntegrationTests/DualFPGA/firmware/scripts/lut_copy_dual.py
diff --git a/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl b/IntegrationTests/DualFPGA/firmware/scripts/pre_msim.tcl
diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl
diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/Makefile
@@ -4,7 +4,7 @@ input_file = mem/in.txt
 proj_path = ../../../../proj
 hls_script_path = ../../script
 
-all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input lut_inclusion
+all: add_common_files $(core_file) hdl_add_files xciCreation kfin_adj $(input_file) apollo_input
 
 $(core_dir):
 	@mkdir cgn mem
@@ -32,9 +32,6 @@ add_common_files:
 hdl_add_files: $(core_file)
 	cd hdl; ln -s ../../../hdl/*.vhd .
 
-lut_inclusion:
-	@python3 scripts/lut_copy.py
-
 $(input_file): $(core_dir)
 	@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsReducedCM/InputStubs -o $(input_file)
 
@@ -53,4 +50,4 @@ sim: $(input_file) $(core_file) $(core_dir)
 	@cd $(hls_script_path); vivado -mode batch -source runSim.tcl
 	@python3 scripts/fwtosim_comparison.py -e mem/out.txt -s $(hls_script_path)/dataOut/TF_L1L2.txt
 
-.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input lut_inclusion core_patch
+.PHONY: sim all hdl_add_files xciCreation kfin_adj apollo_input core_patch
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/lut_copy.py b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/lut_copy.py
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/scripts/pre_msim.tcl
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl
diff --git a/IntegrationTests/common/cfg/qsim.dep b/IntegrationTests/common/cfg/qsim.dep
@@ -3,7 +3,6 @@
 
 # Dependancies
 include -c emp-fwk:boards/testbench top.dep
-setup ../scripts/pre_qsim.tcl
 
 include payload.dep
 src common/hdl/emp/tb_decl.vhd

diff --git a/IntegrationTests/common/cfg/vsim.dep b/IntegrationTests/common/cfg/vsim.dep
@@ -15,6 +15,5 @@ src -c emp-fwk:components/links/slink emp_slink_types.vhd
 #src -c emp-fwk:components/framework emp_framework_decl.vhd 
 
 #src -u sim ../mem/in.txt
-src -u sim ../scripts/pre_msim.tcl
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2.dep
diff --git a/IntegrationTests/common/script/emp/pre_qsim.tcl b/IntegrationTests/common/script/emp/pre_qsim.tcl
diff --git a/IntegrationTests/common/ucf/vsim.tcl b/IntegrationTests/common/ucf/vsim.tcl
@@ -0,0 +1,10 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]