diff --git a/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl
new file mode 100644
index 00000000000..b6f27fa0f2d
--- /dev/null
+++ b/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl
@@ -0,0 +1,11 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
index 9a6ac6946df..6831eb996c5 100644
--- a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
+++ b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep
@@ -3,14 +3,13 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f1.dep
-setup ../ucf/vsim.tcl
+setup ../ucf/vsim_f1.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f1.vhd
 src emp_project_decl_f1.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-src ../mem/in_fpga1.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep
diff --git a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
index c079df8f08b..34995ec5f43 100644
--- a/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
+++ b/IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep
@@ -3,14 +3,13 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f2.dep
-setup ../ucf/vsim.tcl
+setup ../ucf/vsim_f2.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f2.vhd
 src emp_project_decl_f2.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-src ../mem/in_fpga2.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep
diff --git a/IntegrationTests/common/ucf/vsim.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl
similarity index 82%
rename from IntegrationTests/common/ucf/vsim.tcl
rename to IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl
index 345b5f84c7f..bd2bcfe54fa 100644
--- a/IntegrationTests/common/ucf/vsim.tcl
+++ b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl
@@ -1,4 +1,5 @@
 set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga1.txt
 
 # Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
 set_property source_mgmt_mode None [current_project]
diff --git a/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl
new file mode 100644
index 00000000000..336efc644a8
--- /dev/null
+++ b/IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl
@@ -0,0 +1,11 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga2.txt
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
diff --git a/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl
new file mode 100644
index 00000000000..4db8b33251a
--- /dev/null
+++ b/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl
@@ -0,0 +1,11 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/mem/in.txt
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]