Fix issue introduced by attempting to combine vsim.tcl scripts

IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/ucf/vsim.tcl

@@ -0,0 +1,11 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/CombinedBarrelConfig/IRtoKF/firmware/mem/in.txt
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]

IntegrationTests/DualFPGA/firmware/cfg/vsim_f1.dep

@@ -3,14 +3,13 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f1.dep
-setup ../ucf/vsim.tcl
+setup ../ucf/vsim_f1.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f1.vhd
 src emp_project_decl_f1.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-src ../mem/in_fpga1.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p1.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep

IntegrationTests/DualFPGA/firmware/cfg/vsim_f2.dep

@@ -3,14 +3,13 @@
 @fpga_speed_grade = "-2-e"
 
 include payload_f2.dep
-setup ../ucf/vsim.tcl
+setup ../ucf/vsim_f2.tcl
 
 include -c emp-fwk:boards/testbench top.dep
 
 src tb_decl_f2.vhd
 src emp_project_decl_f2.vhd 
 src -c emp-fwk:components/links/slink emp_slink_types.vhd
-src ../mem/in_fpga2.txt
 
 include -c emp-fwk:boards/apollo/cm_v2/vu13p device.dep packages_cm_v2_p2.dep
 #include -c emp-fwk:boards/apollo/cm_v2/vu13p cm_v2_p1_2.dep device.dep packages_cm_v2_p1.dep

IntegrationTests/common/ucf/vsim.tcl → IntegrationTests/DualFPGA/firmware/ucf/vsim_f1.tcl

@@ -1,4 +1,5 @@
 set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga1.txt
 
 # Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
 set_property source_mgmt_mode None [current_project]

IntegrationTests/DualFPGA/firmware/ucf/vsim_f2.tcl

@@ -0,0 +1,11 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/DualFPGA/firmware/mem/in_fpga2.txt
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]

IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/ucf/vsim.tcl

@@ -0,0 +1,11 @@
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+add_files -fileset sim_1 -norecurse ../../src/firmware-hls/IntegrationTests/ReducedCombinedConfig/IRtoKF/firmware/mem/in.txt
+
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top top [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property target_language VHDL [current_project]
+set_property simulator_language VHDL [current_project]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]