From a41228bcbfcf89f6f671072c36b88557b5a4d6de Mon Sep 17 00:00:00 2001 From: Lara Herzog Date: Wed, 6 Mar 2024 10:27:09 +0100 Subject: [PATCH 1/9] add JTAG support to the core Co-Authored-By: Martijn Bastiaan --- .gitignore | 3 + Cargo.lock | 10 + Cargo.toml | 1 + cabal.project | 1 - clash-vexriscv-sim/app/HdlTest.hs | 11 +- clash-vexriscv-sim/app/VexRiscvSimulation.hs | 60 +- clash-vexriscv-sim/src/Utils/Cpu.hs | 39 +- clash-vexriscv-sim/src/Utils/Interconnect.hs | 9 +- clash-vexriscv-sim/tests/tests.hs | 2 +- clash-vexriscv/Makefile | 23 +- clash-vexriscv/clash-vexriscv.cabal | 2 + clash-vexriscv/example-cpu/ExampleCpu.yaml | 1 + .../example-cpu/ExampleCpu.yaml.license | 3 + clash-vexriscv/example-cpu/VexRiscv.v | 1930 ++++++++++++++--- clash-vexriscv/example-cpu/build.sbt | 3 +- .../src/main/scala/example/ExampleCpu.scala | 17 +- clash-vexriscv/src/VexRiscv.hs | 122 +- clash-vexriscv/src/VexRiscv/FFI.hsc | 68 + clash-vexriscv/src/VexRiscv/JtagTcpBridge.hs | 50 + .../src/VexRiscv/JtagTcpBridgeHaskell.hs | 186 ++ clash-vexriscv/src/ffi/impl.cpp | 207 ++ clash-vexriscv/src/ffi/interface.h | 18 + debug-test/Cargo.toml | 18 + debug-test/build.rs | 23 + debug-test/memory.x | 18 + debug-test/src/bin/print_a.rs | 32 + debug-test/src/bin/print_b.rs | 32 + debug-test/src/main.rs | 106 + rust-toolchain.toml | 2 +- shell.nix | 1 + vexriscv_gdb.cfg | 45 + vexriscv_sim.cfg | 70 + 32 files changed, 2797 insertions(+), 316 deletions(-) create mode 100644 clash-vexriscv/example-cpu/ExampleCpu.yaml create mode 100644 clash-vexriscv/example-cpu/ExampleCpu.yaml.license create mode 100644 clash-vexriscv/src/VexRiscv/JtagTcpBridge.hs create mode 100644 clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs create mode 100644 debug-test/Cargo.toml create mode 100644 debug-test/build.rs create mode 100644 debug-test/memory.x create mode 100644 debug-test/src/bin/print_a.rs create mode 100644 debug-test/src/bin/print_b.rs create mode 100644 debug-test/src/main.rs create mode 100644 vexriscv_gdb.cfg create mode 100644 vexriscv_sim.cfg diff --git a/.gitignore b/.gitignore index a8ccd80..407020e 100644 --- a/.gitignore +++ b/.gitignore @@ -65,3 +65,6 @@ log vivado_* tight_setup_hold_pins.txt .Xil + +# Verilator debug output +simulation_dump.vcd diff --git a/Cargo.lock b/Cargo.lock index 1e0609d..2725653 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -44,6 +44,16 @@ version = "1.1.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "6548a0ad5d2549e111e1f6a11a6c2e2d00ce6a3dafe22948d67c2b443f775e52" +[[package]] +name = "debug-test" +version = "0.1.0" +dependencies = [ + "heapless", + "panic-halt", + "riscv", + "riscv-rt", +] + [[package]] name = "embedded-hal" version = "0.2.7" diff --git a/Cargo.toml b/Cargo.toml index 596decd..10b2165 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,5 +13,6 @@ opt-level = "z" [workspace] members = [ "clash-vexriscv-sim/test-programs", + "debug-test", ] resolver = "2" diff --git a/cabal.project b/cabal.project index 253c2a3..eb88ec9 100644 --- a/cabal.project +++ b/cabal.project @@ -7,7 +7,6 @@ packages: clash-vexriscv-sim/ write-ghc-environment-files: always - tests: True diff --git a/clash-vexriscv-sim/app/HdlTest.hs b/clash-vexriscv-sim/app/HdlTest.hs index b82c153..f04dd29 100644 --- a/clash-vexriscv-sim/app/HdlTest.hs +++ b/clash-vexriscv-sim/app/HdlTest.hs @@ -10,10 +10,13 @@ import VexRiscv circuit :: "CLK" ::: Clock System -> "RST" ::: Reset System -> - "INPUT" ::: Signal System Input -> - "OUTPUT" ::: Signal System Output -circuit clk rst input = - withClockResetEnable clk rst enableGen vexRiscv input + "CPU_COMB_INPUT" ::: Signal System CpuIn -> + "JTAG_IN_" ::: Signal System JtagIn -> + "" ::: + ( "CPU_OUTPUT" ::: Signal System CpuOut + , "JTAG_OUT_" ::: Signal System JtagOut) +circuit clk rst input jtagIn = + vexRiscv clk rst input jtagIn makeTopEntity 'circuit diff --git a/clash-vexriscv-sim/app/VexRiscvSimulation.hs b/clash-vexriscv-sim/app/VexRiscvSimulation.hs index fcfabdc..5298542 100644 --- a/clash-vexriscv-sim/app/VexRiscvSimulation.hs +++ b/clash-vexriscv-sim/app/VexRiscvSimulation.hs @@ -5,16 +5,18 @@ {-# LANGUAGE MultiWayIf #-} {-# LANGUAGE GADTs #-} +{-# OPTIONS_GHC -fconstraint-solver-iterations=10 #-} + import Clash.Prelude import Protocols.Wishbone -import VexRiscv (Output(iBusWbM2S, dBusWbM2S)) +import VexRiscv (CpuOut(iBusWbM2S, dBusWbM2S)) import qualified Data.List as L import Control.Monad (forM_, when) import Data.Char (chr) -import Data.Maybe (catMaybes) +import Data.Maybe (catMaybes, fromMaybe) import System.Environment (getArgs) import System.IO (putChar, hFlush, stdout) import Text.Printf (printf) @@ -22,6 +24,7 @@ import Text.Printf (printf) import Utils.ProgramLoad (loadProgram) import Utils.Cpu (cpu) +import System.Exit (exitFailure) -------------------------------------- -- @@ -59,9 +62,9 @@ debugConfig = -- {- InspectBusses - 50 0 - (Just 300) + 0 + (Just 100) True True -- -} @@ -77,37 +80,56 @@ main = do withClockResetEnable @System clockGen resetGen enableGen $ loadProgram @System elfFile - let cpuOut@(unbundle -> (_circuit, writes, iBus, dBus)) = + let cpuOut@(unbundle -> (_circuit, writes, _iBus, _dBus)) = withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $ - bundle (cpu iMem dMem) + let (circ, writes1, iBus, dBus) = cpu (Just 7894) iMem dMem + dBus' = register Nothing dBus + in bundle (circ, writes1, iBus, dBus') case debugConfig of RunCharacterDevice -> - forM_ (sample_lazy @System (bundle (dBus, iBus, writes))) $ \(dS2M, iS2M, write) -> do - when (err dS2M) $ - putStrLn "D-bus ERR reply" + forM_ (sample_lazy @System (bundle (register @System (unpack 0) cpuOut, cpuOut))) $ + \((_out, write, dS2M0, iS2M0), (out1, _write, _dS2M, _iS2M)) -> do + let + iS2M = fromMaybe emptyWishboneS2M iS2M0 + dS2M = fromMaybe emptyWishboneS2M dS2M0 + + when (err dS2M) $ do + let dBusM2S = dBusWbM2S out1 + let dAddr = toInteger (addr dBusM2S) -- `shiftL` 2 + printf "D-bus ERR reply % 8X (% 8X)\n" (toInteger $ dAddr `shiftL` 2) (toInteger dAddr) + exitFailure + + when (err iS2M) $ do + let iBusM2S = iBusWbM2S out1 + let iAddr = toInteger (addr iBusM2S) -- `shiftL` 2 + printf "I-bus ERR reply % 8X (% 8X)\n" (toInteger $ iAddr `shiftL` 2) (toInteger iAddr) + printf "%s\n" (showX iBusM2S) + exitFailure - when (err iS2M) $ - putStrLn "I-bus ERR reply" - case write of Just (address, value) | address == 0x0000_1000 -> do let (_ :: BitVector 24, b :: BitVector 8) = unpack value putChar $ chr (fromEnum b) hFlush stdout + pure () _ -> pure () -- performPrintsToStdout 0x0000_1000 (sample_lazy $ bitCoerce <$> writes) InspectBusses initCycles uninteresting interesting iEnabled dEnabled -> do - + let skipTotal = initCycles + uninteresting let sampled = case interesting of Nothing -> L.zip [0 ..] $ sample_lazy @System cpuOut Just nInteresting -> - let total = initCycles + uninteresting + nInteresting in L.zip [0 ..] $ L.take total $ sample_lazy @System cpuOut + let total = initCycles + uninteresting + nInteresting in + L.zip [0 ..] $ L.take total $ sample_lazy @System cpuOut - forM_ sampled $ \(i, (out, _, iBusS2M, dBusS2M)) -> do - let doPrint = i >= skipTotal + forM_ sampled $ \(i, (out, _, iBusS2M0, dBusS2M0)) -> do + let + iBusS2M = fromMaybe emptyWishboneS2M iBusS2M0 + dBusS2M = fromMaybe emptyWishboneS2M dBusS2M0 + doPrint = i >= skipTotal -- I-bus interactions @@ -143,6 +165,9 @@ main = do <> ")" putStrLn $ " - iS2M: " <> iResp <> " - " <> iRespData + when (err iBusS2M) + exitFailure + -- D-bus interactions when (doPrint && dEnabled) $ do @@ -192,6 +217,9 @@ main = do <> writeDat <> "> - " putStrLn $ "dS2M: " <> dResp <> dRespData + + when (err dBusS2M) + exitFailure InspectWrites -> forM_ (catMaybes $ sample_lazy @System writes) $ \(address, value) -> do printf "W: % 8X <- % 8X\n" (toInteger address) (toInteger value) diff --git a/clash-vexriscv-sim/src/Utils/Cpu.hs b/clash-vexriscv-sim/src/Utils/Cpu.hs index 325492c..6c90b0f 100644 --- a/clash-vexriscv-sim/src/Utils/Cpu.hs +++ b/clash-vexriscv-sim/src/Utils/Cpu.hs @@ -5,12 +5,16 @@ {-# LANGUAGE ApplicativeDo #-} {-# LANGUAGE NumericUnderscores #-} {-# LANGUAGE RecordWildCards #-} + +{-# OPTIONS_GHC -Wno-orphans #-} + module Utils.Cpu where import Clash.Prelude import Protocols.Wishbone import VexRiscv +import VexRiscv.JtagTcpBridge as JTag import VexRiscv.VecToTuple (vecToTuple) import GHC.Stack (HasCallStack) @@ -18,6 +22,8 @@ import GHC.Stack (HasCallStack) import Utils.ProgramLoad (Memory) import Utils.Interconnect (interconnectTwo) +createDomain vXilinxSystem{vName="Basic50", vPeriod= hzToPeriod 50_000_000} + {- Address space @@ -27,24 +33,39 @@ Address space -} cpu :: (HasCallStack, HiddenClockResetEnable dom) => + Maybe Integer -> Memory dom -> Memory dom -> - ( Signal dom Output, + ( Signal dom CpuOut, -- writes Signal dom (Maybe (BitVector 32, BitVector 32)), -- iBus responses - Signal dom (WishboneS2M (BitVector 32)), + Signal dom (Maybe (WishboneS2M (BitVector 32))), -- dBus responses - Signal dom (WishboneS2M (BitVector 32)) + Signal dom (Maybe (WishboneS2M (BitVector 32))) + ) +cpu jtagPort bootIMem bootDMem = + ( output + , writes + , mux validI (Just <$> iS2M) (pure Nothing) + , mux validD (Just <$> dS2M) (pure Nothing) ) -cpu bootIMem bootDMem = (output, writes, iS2M, dS2M) where - output = vexRiscv input + (output, jtagOut) = vexRiscv hasClock hasReset input jtagIn + + jtagIn = case jtagPort of + Just port -> vexrJtagBridge (fromInteger port) jtagOut + Nothing -> pure JTag.defaultIn + -- (unbundle -> (jtagIn', _debugReset)) = unsafePerformIO $ jtagTcpBridge' 7894 hasReset (jtagOut <$> output) + dM2S = dBusWbM2S <$> output + validD = fmap busCycle dM2S .&&. fmap strobe dM2S iM2S = unBusAddr . iBusWbM2S <$> output + validI = fmap busCycle iM2S .&&. fmap strobe iM2S - iS2M = bootIMem (mapAddr (\x -> x - 0x2000_0000) <$> iM2S) + iS2M = bootIMem (mapAddr (\x -> -- trace (printf "I-addr = % 8X (% 8X)\n" (toInteger $ x - 0x2000_0000) (toInteger x)) + x - 0x2000_0000) <$> iM2S) dummy = dummyWb @@ -52,12 +73,14 @@ cpu bootIMem bootDMem = (output, writes, iS2M, dS2M) bootDS2M = bootDMem bootDM2S (dS2M, vecToTuple . unbundle -> (dummyM2S, bootDM2S)) = interconnectTwo - (unBusAddr <$> dM2S) + ((\x -> + -- trace (printf "DBUS %08X" (toInteger (addr x))) + x) <$> (unBusAddr <$> dM2S)) ((0x0000_0000, dummyS2M) :> (0x4000_0000, bootDS2M) :> Nil) input = ( \iBus dBus -> - Input + CpuIn { timerInterrupt = low, externalInterrupt = low, softwareInterrupt = low, diff --git a/clash-vexriscv-sim/src/Utils/Interconnect.hs b/clash-vexriscv-sim/src/Utils/Interconnect.hs index eea320b..5f09815 100644 --- a/clash-vexriscv-sim/src/Utils/Interconnect.hs +++ b/clash-vexriscv-sim/src/Utils/Interconnect.hs @@ -35,9 +35,12 @@ interconnectTwo m2s ((aAddr', aS2M') :> (bAddr', bS2M') :> Nil) = Vec 2 (WishboneM2S 32 4 (BitVector 32)) ) go m@WishboneM2S{..} aAddr aS2M bAddr bS2M - | not (busCycle && strobe) = (emptyWishboneS2M, m :> m :> Nil) - | addr >= bAddr = (bS2M, emptyWishboneM2S :> m { addr = addr - bAddr } :> Nil) - | addr >= aAddr = (aS2M, m { addr = addr - aAddr } :> emptyWishboneM2S :> Nil) + | not (busCycle && strobe) = + (emptyWishboneS2M, m :> m :> Nil) + | addr >= bAddr = + (bS2M, emptyWishboneM2S :> m { addr = addr - bAddr } :> Nil) + | addr >= aAddr = + (aS2M, m { addr = addr - aAddr } :> emptyWishboneM2S :> Nil) | otherwise = ( emptyWishboneS2M { err = True }, emptyWishboneM2S :> emptyWishboneM2S :> Nil diff --git a/clash-vexriscv-sim/tests/tests.hs b/clash-vexriscv-sim/tests/tests.hs index 03af70d..23283e4 100644 --- a/clash-vexriscv-sim/tests/tests.hs +++ b/clash-vexriscv-sim/tests/tests.hs @@ -39,7 +39,7 @@ runProgramExpect act n expected = withSystemTempFile "ELF" $ \fp _ -> do let _all@(unbundle -> (_circuit, writes, _iBus, _dBus)) = withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $ - bundle (cpu iMem dMem) + bundle (cpu Nothing iMem dMem) let output = L.take (BS.length expected) $ flip mapMaybe (sampleN_lazy n writes) $ \case diff --git a/clash-vexriscv/Makefile b/clash-vexriscv/Makefile index db1a711..a909e6b 100644 --- a/clash-vexriscv/Makefile +++ b/clash-vexriscv/Makefile @@ -7,13 +7,12 @@ OUT_DIR = build_out_dir VERILATOR_DIR = $(OUT_DIR)/verilator_output FFI_DIR = src/ffi - -VERILATOR_FLAGS = -CFLAGS '-O3 -fPIC' -Wno-fatal +1364-2001ext+v +VERILATOR_FLAGS = -CFLAGS '-O3 -fPIC' -Wno-fatal +1364-2001ext+v --trace VERILATOR_CFLAGS = $(shell pkg-config --cflags verilator) FFI_CPPFLAGS = $(VERILATOR_CFLAGS) -fPIC -O3 -I$(VERILATOR_DIR) -all: $(OUT_DIR)/libVexRiscvFFI.a +all: $(OUT_DIR)/libVexRiscvFFI.a # $(OUT_DIR)/libVexRiscvFFI.so clean: rm $(VERILATOR_DIR) -rf @@ -23,6 +22,8 @@ clean: $(CPU_DIR)/VexRiscv.v: $(CPU_DIR)/src/main/scala/example/ExampleCpu.scala cd $(CPU_DIR); sbt "runMain example.ExampleCpu" cd $(CPU_DIR); sed -i -E '/\/\/ Git hash :.*$$/d' VexRiscv.v + # cd $(CPU_DIR); sed -i 's/module VexRiscv/module VexRiscvInner/g' VexRiscv.v + # cd $(CPU_DIR); cat ../example-cpu/VexRiscvWrapped.v >> VexRiscv.v $(OUT_DIR)/VexRiscv.v: $(CPU_DIR)/VexRiscv.v mkdir -p $(OUT_DIR) @@ -37,6 +38,10 @@ $(VERILATOR_DIR)/VVexRiscv__ALL.a: $(VERILATOR_DIR)/VVexRiscv.mk $(OUT_DIR)/impl.o: $(FFI_DIR)/impl.cpp $(FFI_DIR)/interface.h $(CXX) $(FFI_CPPFLAGS) -c $(FFI_DIR)/impl.cpp -o $(OUT_DIR)/impl.o +$(OUT_DIR)/verilated_vcd_c.o: $(shell pkg-config --variable=includedir verilator)/verilated_vcd_c.cpp + $(CXX) $(FFI_CPPFLAGS) -c $(shell pkg-config --variable=includedir verilator)/verilated_vcd_c.cpp -o $(OUT_DIR)/verilated_vcd_c.o + + $(OUT_DIR)/verilated.o: $(shell pkg-config --variable=includedir verilator)/verilated.cpp $(CXX) $(FFI_CPPFLAGS) -c $(shell pkg-config --variable=includedir verilator)/verilated.cpp -o $(OUT_DIR)/verilated.o @@ -46,11 +51,19 @@ $(OUT_DIR)/verilated_threads.o: $(shell pkg-config --variable=includedir verilat $(OUT_DIR)/VVexRiscv__ALL.a: $(VERILATOR_DIR)/VVexRiscv__ALL.a cp $(VERILATOR_DIR)/VVexRiscv__ALL.a $(OUT_DIR)/VVexRiscv__ALL.a -$(OUT_DIR)/libVexRiscvFFI.a: $(OUT_DIR)/VVexRiscv__ALL.a $(OUT_DIR)/impl.o $(OUT_DIR)/verilated.o $(OUT_DIR)/verilated_threads.o +$(OUT_DIR)/libVexRiscvFFI.a: $(OUT_DIR)/VVexRiscv__ALL.a $(OUT_DIR)/impl.o $(OUT_DIR)/verilated.o $(OUT_DIR)/verilated_threads.o $(OUT_DIR)/verilated_vcd_c.o rm -f $(OUT_DIR)/libVexRiscvFFI.a cp $(OUT_DIR)/VVexRiscv__ALL.a $(OUT_DIR)/libVexRiscvFFI.a ar r \ $(OUT_DIR)/libVexRiscvFFI.a \ $(OUT_DIR)/impl.o \ $(OUT_DIR)/verilated.o \ - $(OUT_DIR)/verilated_threads.o + $(OUT_DIR)/verilated_threads.o \ + $(OUT_DIR)/verilated_vcd_c.o + +$(OUT_DIR)/libVexRiscvFFI.so: $(OUT_DIR)/libVexRiscvFFI.a + rm -f $(OUT_DIR)/libVexRiscvFFI.so + $(CXX) -shared -o $(OUT_DIR)/libVexRiscvFFI.so \ + -Wl,--whole-archive \ + $(OUT_DIR)/libVexRiscvFFI.a \ + -Wl,--no-whole-archive diff --git a/clash-vexriscv/clash-vexriscv.cabal b/clash-vexriscv/clash-vexriscv.cabal index d761071..4ae60fb 100644 --- a/clash-vexriscv/clash-vexriscv.cabal +++ b/clash-vexriscv/clash-vexriscv.cabal @@ -104,6 +104,7 @@ library VexRiscv VexRiscv.ClockTicks VexRiscv.FFI + VexRiscv.JtagTcpBridge VexRiscv.TH VexRiscv.VecToTuple @@ -116,6 +117,7 @@ library directory >= 1.3 && < 1.4, filepath, Glob, + network, process >= 1.6 && < 1.8, string-interpolate, tagged, diff --git a/clash-vexriscv/example-cpu/ExampleCpu.yaml b/clash-vexriscv/example-cpu/ExampleCpu.yaml new file mode 100644 index 0000000..c20c879 --- /dev/null +++ b/clash-vexriscv/example-cpu/ExampleCpu.yaml @@ -0,0 +1 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 5} diff --git a/clash-vexriscv/example-cpu/ExampleCpu.yaml.license b/clash-vexriscv/example-cpu/ExampleCpu.yaml.license new file mode 100644 index 0000000..a6df6eb --- /dev/null +++ b/clash-vexriscv/example-cpu/ExampleCpu.yaml.license @@ -0,0 +1,3 @@ +SPDX-FileCopyrightText: 2024 Google LLC + +SPDX-License-Identifier: Apache-2.0 diff --git a/clash-vexriscv/example-cpu/VexRiscv.v b/clash-vexriscv/example-cpu/VexRiscv.v index 9f4089f..9c059f5 100644 --- a/clash-vexriscv/example-cpu/VexRiscv.v +++ b/clash-vexriscv/example-cpu/VexRiscv.v @@ -7,6 +7,7 @@ module VexRiscv ( input timerInterrupt, input externalInterrupt, input softwareInterrupt, + output debug_resetOut, output iBusWishbone_CYC, output iBusWishbone_STB, input iBusWishbone_ACK, @@ -29,6 +30,10 @@ module VexRiscv ( input dBusWishbone_ERR, output [2:0] dBusWishbone_CTI, output [1:0] dBusWishbone_BTE, + input jtag_tms, + input jtag_tdi, + output jtag_tdo, + input jtag_tck, input clk, input reset ); @@ -143,6 +148,20 @@ module VexRiscv ( wire FpuPlugin_fpu_io_port_0_completion_payload_flags_DZ; wire FpuPlugin_fpu_io_port_0_completion_payload_flags_NV; wire FpuPlugin_fpu_io_port_0_completion_payload_written; + wire jtagBridge_1_io_jtag_tdo; + wire jtagBridge_1_io_remote_cmd_valid; + wire jtagBridge_1_io_remote_cmd_payload_last; + wire [0:0] jtagBridge_1_io_remote_cmd_payload_fragment; + wire jtagBridge_1_io_remote_rsp_ready; + wire systemDebugger_1_io_remote_cmd_ready; + wire systemDebugger_1_io_remote_rsp_valid; + wire systemDebugger_1_io_remote_rsp_payload_error; + wire [31:0] systemDebugger_1_io_remote_rsp_payload_data; + wire systemDebugger_1_io_mem_cmd_valid; + wire [31:0] systemDebugger_1_io_mem_cmd_payload_address; + wire [31:0] systemDebugger_1_io_mem_cmd_payload_data; + wire systemDebugger_1_io_mem_cmd_payload_wr; + wire [1:0] systemDebugger_1_io_mem_cmd_payload_size; wire [51:0] _zz_memory_MUL_LOW; wire [51:0] _zz_memory_MUL_LOW_1; wire [51:0] _zz_memory_MUL_LOW_2; @@ -152,6 +171,12 @@ module VexRiscv ( wire [49:0] _zz_memory_MUL_LOW_6; wire [51:0] _zz_memory_MUL_LOW_7; wire [49:0] _zz_memory_MUL_LOW_8; + wire _zz_decode_DO_EBREAK; + wire [30:0] _zz_decode_DO_EBREAK_1; + wire [30:0] _zz_decode_DO_EBREAK_2; + wire [30:0] _zz_decode_DO_EBREAK_3; + wire [30:0] _zz_decode_DO_EBREAK_4; + wire [30:0] _zz_decode_DO_EBREAK_5; wire [31:0] _zz_decode_FORMAL_PC_NEXT; wire [2:0] _zz_decode_FORMAL_PC_NEXT_1; wire [31:0] _zz_decode_LEGAL_INSTRUCTION; @@ -238,7 +263,7 @@ module VexRiscv ( wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_21; wire _zz__zz_decode_BRANCH_CTRL_2_22; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_23; - wire [34:0] _zz__zz_decode_BRANCH_CTRL_2_24; + wire [35:0] _zz__zz_decode_BRANCH_CTRL_2_24; wire _zz__zz_decode_BRANCH_CTRL_2_25; wire _zz__zz_decode_BRANCH_CTRL_2_26; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_27; @@ -255,7 +280,7 @@ module VexRiscv ( wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_38; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_39; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_40; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_41; + wire [32:0] _zz__zz_decode_BRANCH_CTRL_2_41; wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_42; wire _zz__zz_decode_BRANCH_CTRL_2_43; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; @@ -280,7 +305,7 @@ module VexRiscv ( wire _zz__zz_decode_BRANCH_CTRL_2_63; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_64; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; - wire [28:0] _zz__zz_decode_BRANCH_CTRL_2_66; + wire [29:0] _zz__zz_decode_BRANCH_CTRL_2_66; wire _zz__zz_decode_BRANCH_CTRL_2_67; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_68; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; @@ -292,17 +317,17 @@ module VexRiscv ( wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_75; wire _zz__zz_decode_BRANCH_CTRL_2_76; wire _zz__zz_decode_BRANCH_CTRL_2_77; - wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_78; + wire [27:0] _zz__zz_decode_BRANCH_CTRL_2_78; wire _zz__zz_decode_BRANCH_CTRL_2_79; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_81; - wire [24:0] _zz__zz_decode_BRANCH_CTRL_2_82; + wire [25:0] _zz__zz_decode_BRANCH_CTRL_2_82; wire _zz__zz_decode_BRANCH_CTRL_2_83; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_84; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_85; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_86; wire _zz__zz_decode_BRANCH_CTRL_2_87; - wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_88; + wire [23:0] _zz__zz_decode_BRANCH_CTRL_2_88; wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_89; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_91; @@ -314,105 +339,102 @@ module VexRiscv ( wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_97; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_98; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_99; - wire [19:0] _zz__zz_decode_BRANCH_CTRL_2_100; + wire [20:0] _zz__zz_decode_BRANCH_CTRL_2_100; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_101; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_102; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; + wire _zz__zz_decode_BRANCH_CTRL_2_104; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_105; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_106; - wire _zz__zz_decode_BRANCH_CTRL_2_107; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_107; + wire [16:0] _zz__zz_decode_BRANCH_CTRL_2_108; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_109; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_110; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_111; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_112; - wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_113; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_114; - wire _zz__zz_decode_BRANCH_CTRL_2_115; + wire _zz__zz_decode_BRANCH_CTRL_2_112; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_113; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_114; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_117; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_119; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; + wire _zz__zz_decode_BRANCH_CTRL_2_118; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_119; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_120; - wire _zz__zz_decode_BRANCH_CTRL_2_121; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_122; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_123; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_124; - wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_125; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_126; - wire _zz__zz_decode_BRANCH_CTRL_2_127; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; + wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_122; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_123; + wire _zz__zz_decode_BRANCH_CTRL_2_124; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_125; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_126; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_128; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_129; + wire _zz__zz_decode_BRANCH_CTRL_2_130; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_131; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_132; - wire _zz__zz_decode_BRANCH_CTRL_2_133; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; - wire _zz__zz_decode_BRANCH_CTRL_2_135; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_136; + wire _zz__zz_decode_BRANCH_CTRL_2_132; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_133; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_134; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_136; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_137; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_140; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_141; - wire [5:0] _zz__zz_decode_BRANCH_CTRL_2_142; - wire _zz__zz_decode_BRANCH_CTRL_2_143; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_138; + wire [5:0] _zz__zz_decode_BRANCH_CTRL_2_139; + wire _zz__zz_decode_BRANCH_CTRL_2_140; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_141; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_142; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_145; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_146; + wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_145; + wire _zz__zz_decode_BRANCH_CTRL_2_146; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_147; - wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_148; - wire _zz__zz_decode_BRANCH_CTRL_2_149; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_150; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_151; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_152; - wire _zz__zz_decode_BRANCH_CTRL_2_153; - wire _zz__zz_decode_BRANCH_CTRL_2_154; - wire [8:0] _zz__zz_decode_BRANCH_CTRL_2_155; - wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_156; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_157; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_158; - wire _zz__zz_decode_BRANCH_CTRL_2_159; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_160; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_148; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_149; + wire _zz__zz_decode_BRANCH_CTRL_2_150; + wire _zz__zz_decode_BRANCH_CTRL_2_151; + wire [8:0] _zz__zz_decode_BRANCH_CTRL_2_152; + wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_153; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_154; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_155; + wire _zz__zz_decode_BRANCH_CTRL_2_156; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_157; + wire _zz__zz_decode_BRANCH_CTRL_2_158; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_159; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_160; wire _zz__zz_decode_BRANCH_CTRL_2_161; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_162; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_163; - wire _zz__zz_decode_BRANCH_CTRL_2_164; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_165; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_166; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_167; - wire _zz__zz_decode_BRANCH_CTRL_2_168; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_169; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_162; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_163; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_164; + wire _zz__zz_decode_BRANCH_CTRL_2_165; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_166; + wire _zz__zz_decode_BRANCH_CTRL_2_167; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_168; + wire [5:0] _zz__zz_decode_BRANCH_CTRL_2_169; wire _zz__zz_decode_BRANCH_CTRL_2_170; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_171; - wire [5:0] _zz__zz_decode_BRANCH_CTRL_2_172; - wire _zz__zz_decode_BRANCH_CTRL_2_173; - wire _zz__zz_decode_BRANCH_CTRL_2_174; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_175; + wire _zz__zz_decode_BRANCH_CTRL_2_171; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_172; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_173; + wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_174; + wire _zz__zz_decode_BRANCH_CTRL_2_175; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_176; - wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_177; - wire _zz__zz_decode_BRANCH_CTRL_2_178; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_179; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_177; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_178; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_179; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_180; - wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_181; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_182; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_183; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_184; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_185; - wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_186; - wire _zz__zz_decode_BRANCH_CTRL_2_187; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_188; - wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_189; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_190; - wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_191; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_181; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_182; + wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_183; + wire _zz__zz_decode_BRANCH_CTRL_2_184; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_185; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_186; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_187; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_188; + wire _zz__zz_decode_BRANCH_CTRL_2_189; + wire _zz__zz_decode_BRANCH_CTRL_2_190; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_191; wire _zz__zz_decode_BRANCH_CTRL_2_192; - wire _zz__zz_decode_BRANCH_CTRL_2_193; - wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_194; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_193; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_194; wire _zz__zz_decode_BRANCH_CTRL_2_195; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_196; - wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_197; - wire _zz__zz_decode_BRANCH_CTRL_2_198; wire _zz_RegFilePlugin_regFile_port; wire _zz_decode_RegFilePlugin_rs1Data; wire _zz_RegFilePlugin_regFile_port_1; @@ -471,6 +493,7 @@ module VexRiscv ( wire [31:0] execute_REGFILE_WRITE_DATA; wire [31:0] memory_MEMORY_STORE_DATA_RF; wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_DO_EBREAK; wire memory_FPU_COMMIT_LOAD; wire execute_FPU_COMMIT_LOAD; wire decode_FPU_COMMIT_LOAD; @@ -547,6 +570,8 @@ module VexRiscv ( wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; @@ -669,7 +694,7 @@ module VexRiscv ( reg execute_arbitration_haltItself; reg execute_arbitration_haltByOther; reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; + reg execute_arbitration_flushIt; reg execute_arbitration_flushNext; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; @@ -704,7 +729,7 @@ module VexRiscv ( wire lastStageIsValid /* verilator public */ ; wire lastStageIsFiring /* verilator public */ ; reg IBusSimplePlugin_fetcherHalt; - wire IBusSimplePlugin_forceNoDecodeCond; + reg IBusSimplePlugin_forceNoDecodeCond; reg IBusSimplePlugin_incomingInstruction; wire IBusSimplePlugin_pcValids_0; wire IBusSimplePlugin_pcValids_1; @@ -752,6 +777,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_when_DBusCachedPlugin_l393; wire [31:0] CsrPlugin_csrMapping_readDataSignal; wire [31:0] CsrPlugin_csrMapping_readDataInit; wire [31:0] CsrPlugin_csrMapping_writeDataSignal; @@ -767,13 +793,13 @@ module VexRiscv ( wire CsrPlugin_exceptionPendings_3; wire contextSwitching; reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; + reg CsrPlugin_forceMachineWire; reg CsrPlugin_selfException_valid; reg [3:0] CsrPlugin_selfException_payload_code; wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire CsrPlugin_allowEbreakException; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -807,7 +833,16 @@ module VexRiscv ( wire FpuPlugin_port_completion_payload_written /* verilator public */ ; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_inDebugNoFetchFlag; + reg BranchPlugin_inDebugNoFetchFlag; + wire debug_bus_cmd_valid; + reg debug_bus_cmd_ready; + wire debug_bus_cmd_payload_wr; + wire [7:0] debug_bus_cmd_payload_address; + wire [31:0] debug_bus_cmd_payload_data; + reg [31:0] debug_bus_rsp_data; + reg IBusSimplePlugin_injectionPort_valid; + reg IBusSimplePlugin_injectionPort_ready; + wire [31:0] IBusSimplePlugin_injectionPort_payload; wire IBusSimplePlugin_externalFlush; wire IBusSimplePlugin_jump_pcLoad_valid; wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; @@ -835,7 +870,7 @@ module VexRiscv ( reg IBusSimplePlugin_decodePc_flushed; reg [31:0] IBusSimplePlugin_decodePc_pcReg /* verilator public */ ; wire [31:0] IBusSimplePlugin_decodePc_pcPlus; - wire IBusSimplePlugin_decodePc_injectedDecode; + reg IBusSimplePlugin_decodePc_injectedDecode; wire when_Fetcher_l183; wire when_Fetcher_l195; wire IBusSimplePlugin_iBusRsp_redoFetch; @@ -1096,7 +1131,7 @@ module VexRiscv ( wire when_CsrPlugin_l1189; wire when_CsrPlugin_l1193; wire [11:0] execute_CsrPlugin_csrAddress; - wire [40:0] _zz_decode_BRANCH_CTRL_2; + wire [41:0] _zz_decode_BRANCH_CTRL_2; wire _zz_decode_BRANCH_CTRL_3; wire _zz_decode_BRANCH_CTRL_4; wire _zz_decode_BRANCH_CTRL_5; @@ -1108,6 +1143,7 @@ module VexRiscv ( wire _zz_decode_BRANCH_CTRL_11; wire _zz_decode_BRANCH_CTRL_12; wire _zz_decode_BRANCH_CTRL_13; + wire _zz_decode_BRANCH_CTRL_14; wire [1:0] _zz_decode_SRC1_CTRL_2; wire [1:0] _zz_decode_ALU_CTRL_2; wire [1:0] _zz_decode_SRC2_CTRL_2; @@ -1115,7 +1151,7 @@ module VexRiscv ( wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; wire [3:0] _zz_decode_FPU_OPCODE_2; wire [1:0] _zz_decode_SHIFT_CTRL_2; - wire [1:0] _zz_decode_BRANCH_CTRL_14; + wire [1:0] _zz_decode_BRANCH_CTRL_15; wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; @@ -1284,6 +1320,46 @@ module VexRiscv ( reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg DebugPlugin_hardwareBreakpoints_4_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_4_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l267; + wire when_DebugPlugin_l271; + wire when_DebugPlugin_l271_1; + wire when_DebugPlugin_l272; + wire when_DebugPlugin_l272_1; + wire when_DebugPlugin_l273; + wire when_DebugPlugin_l274; + wire when_DebugPlugin_l275; + wire when_DebugPlugin_l275_1; + wire when_DebugPlugin_l295; + wire when_DebugPlugin_l298; + wire when_DebugPlugin_l311; + reg _zz_3; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l331; wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; wire when_Pipeline_l124_1; @@ -1419,28 +1495,30 @@ module VexRiscv ( wire when_Pipeline_l124_66; reg memory_to_writeBack_FPU_COMMIT_LOAD; wire when_Pipeline_l124_67; - reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + reg decode_to_execute_DO_EBREAK; wire when_Pipeline_l124_68; - reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; wire when_Pipeline_l124_69; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; wire when_Pipeline_l124_70; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; wire when_Pipeline_l124_71; - reg [31:0] execute_to_memory_MUL_LL; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; wire when_Pipeline_l124_72; - reg [33:0] execute_to_memory_MUL_LH; + reg [31:0] execute_to_memory_MUL_LL; wire when_Pipeline_l124_73; - reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_LH; wire when_Pipeline_l124_74; - reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] execute_to_memory_MUL_HL; wire when_Pipeline_l124_75; - reg [33:0] memory_to_writeBack_MUL_HH; + reg [33:0] execute_to_memory_MUL_HH; wire when_Pipeline_l124_76; - reg execute_to_memory_BRANCH_DO; + reg [33:0] memory_to_writeBack_MUL_HH; wire when_Pipeline_l124_77; - reg [31:0] execute_to_memory_BRANCH_CALC; + reg execute_to_memory_BRANCH_DO; wire when_Pipeline_l124_78; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_79; reg [51:0] memory_to_writeBack_MUL_LOW; wire when_Pipeline_l151; wire when_Pipeline_l154; @@ -1448,6 +1526,10 @@ module VexRiscv ( wire when_Pipeline_l154_1; wire when_Pipeline_l151_2; wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l365; + wire when_Fetcher_l363; + wire when_Fetcher_l381; + wire when_Fetcher_l401; wire when_CsrPlugin_l1277; reg execute_CsrPlugin_csr_768; wire when_CsrPlugin_l1277_1; @@ -1494,6 +1576,8 @@ module VexRiscv ( wire _zz_dBus_cmd_ready_5; reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; + wire debug_bus_cmd_fire; + reg debug_bus_cmd_fire_regNext; `ifndef SYNTHESIS reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_decode_BRANCH_CTRL_string; @@ -1570,7 +1654,7 @@ module VexRiscv ( reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; reg [63:0] _zz_decode_FPU_OPCODE_2_string; reg [71:0] _zz_decode_SHIFT_CTRL_2_string; - reg [31:0] _zz_decode_BRANCH_CTRL_14_string; + reg [31:0] _zz_decode_BRANCH_CTRL_15_string; reg [23:0] _zz_FpuPlugin_port_cmd_payload_roundMode_string; reg [23:0] _zz_FpuPlugin_port_cmd_payload_roundMode_1_string; reg [63:0] writeBack_FpuPlugin_commit_payload_opcode_string; @@ -1601,6 +1685,11 @@ module VexRiscv ( assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_decode_DO_EBREAK_1 = (decode_PC >>> 1); + assign _zz_decode_DO_EBREAK_2 = (decode_PC >>> 1); + assign _zz_decode_DO_EBREAK_3 = (decode_PC >>> 1); + assign _zz_decode_DO_EBREAK_4 = (decode_PC >>> 1); + assign _zz_decode_DO_EBREAK_5 = (decode_PC >>> 1); assign _zz_decode_FORMAL_PC_NEXT_1 = (decode_IS_RVC ? 3'b010 : 3'b100); assign _zz_decode_FORMAL_PC_NEXT = {29'd0, _zz_decode_FORMAL_PC_NEXT_1}; assign _zz__zz_IBusSimplePlugin_jump_pcLoad_payload_1 = (_zz_IBusSimplePlugin_jump_pcLoad_payload - 3'b001); @@ -1673,6 +1762,7 @@ module VexRiscv ( assign _zz_IBusSimplePlugin_jump_pcLoad_payload_5 = {_zz_IBusSimplePlugin_jump_pcLoad_payload_3,_zz_IBusSimplePlugin_jump_pcLoad_payload_2}; assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_DO_EBREAK = (DebugPlugin_hardwareBreakpoints_0_pc == _zz_decode_DO_EBREAK_1); assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; @@ -1769,7 +1859,7 @@ module VexRiscv ( assign _zz__zz_decode_BRANCH_CTRL_2_68 = (_zz__zz_decode_BRANCH_CTRL_2_69 == _zz__zz_decode_BRANCH_CTRL_2_70); assign _zz__zz_decode_BRANCH_CTRL_2_71 = {_zz__zz_decode_BRANCH_CTRL_2_72,_zz__zz_decode_BRANCH_CTRL_2_73}; assign _zz__zz_decode_BRANCH_CTRL_2_75 = {_zz__zz_decode_BRANCH_CTRL_2_76,_zz__zz_decode_BRANCH_CTRL_2_77}; - assign _zz__zz_decode_BRANCH_CTRL_2_79 = (|_zz_decode_BRANCH_CTRL_13); + assign _zz__zz_decode_BRANCH_CTRL_2_79 = (|_zz_decode_BRANCH_CTRL_14); assign _zz__zz_decode_BRANCH_CTRL_2_80 = (|_zz__zz_decode_BRANCH_CTRL_2_81); assign _zz__zz_decode_BRANCH_CTRL_2_82 = {_zz__zz_decode_BRANCH_CTRL_2_83,{_zz__zz_decode_BRANCH_CTRL_2_86,_zz__zz_decode_BRANCH_CTRL_2_88}}; assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h88000010; @@ -1785,7 +1875,7 @@ module VexRiscv ( assign _zz__zz_decode_BRANCH_CTRL_2_73 = ((decode_INSTRUCTION & 32'h00000030) == 32'h0); assign _zz__zz_decode_BRANCH_CTRL_2_76 = ((decode_INSTRUCTION & 32'h00000060) == 32'h00000040); assign _zz__zz_decode_BRANCH_CTRL_2_77 = ((decode_INSTRUCTION & 32'h0000005c) == 32'h00000004); - assign _zz__zz_decode_BRANCH_CTRL_2_81 = _zz_decode_BRANCH_CTRL_13; + assign _zz__zz_decode_BRANCH_CTRL_2_81 = _zz_decode_BRANCH_CTRL_14; assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|(_zz__zz_decode_BRANCH_CTRL_2_84 == _zz__zz_decode_BRANCH_CTRL_2_85)); assign _zz__zz_decode_BRANCH_CTRL_2_86 = (|_zz__zz_decode_BRANCH_CTRL_2_87); assign _zz__zz_decode_BRANCH_CTRL_2_88 = {(|_zz__zz_decode_BRANCH_CTRL_2_89),{_zz__zz_decode_BRANCH_CTRL_2_95,{_zz__zz_decode_BRANCH_CTRL_2_97,_zz__zz_decode_BRANCH_CTRL_2_100}}}; @@ -1795,7 +1885,7 @@ module VexRiscv ( assign _zz__zz_decode_BRANCH_CTRL_2_89 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_90) == 32'h00000034),{(_zz__zz_decode_BRANCH_CTRL_2_91 == _zz__zz_decode_BRANCH_CTRL_2_92),(_zz__zz_decode_BRANCH_CTRL_2_93 == _zz__zz_decode_BRANCH_CTRL_2_94)}}; assign _zz__zz_decode_BRANCH_CTRL_2_95 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h00001000)); assign _zz__zz_decode_BRANCH_CTRL_2_97 = (|(_zz__zz_decode_BRANCH_CTRL_2_98 == _zz__zz_decode_BRANCH_CTRL_2_99)); - assign _zz__zz_decode_BRANCH_CTRL_2_100 = {(|{_zz__zz_decode_BRANCH_CTRL_2_101,_zz__zz_decode_BRANCH_CTRL_2_103}),{(|_zz__zz_decode_BRANCH_CTRL_2_105),{_zz__zz_decode_BRANCH_CTRL_2_107,{_zz__zz_decode_BRANCH_CTRL_2_110,_zz__zz_decode_BRANCH_CTRL_2_113}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_100 = {(|{_zz__zz_decode_BRANCH_CTRL_2_101,_zz__zz_decode_BRANCH_CTRL_2_102}),{(|_zz__zz_decode_BRANCH_CTRL_2_103),{_zz__zz_decode_BRANCH_CTRL_2_104,{_zz__zz_decode_BRANCH_CTRL_2_105,_zz__zz_decode_BRANCH_CTRL_2_108}}}}; assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00000034; assign _zz__zz_decode_BRANCH_CTRL_2_91 = (decode_INSTRUCTION & 32'h00003074); assign _zz__zz_decode_BRANCH_CTRL_2_92 = 32'h00001010; @@ -1804,104 +1894,101 @@ module VexRiscv ( assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00001000; assign _zz__zz_decode_BRANCH_CTRL_2_98 = (decode_INSTRUCTION & 32'h00003000); assign _zz__zz_decode_BRANCH_CTRL_2_99 = 32'h00002000; - assign _zz__zz_decode_BRANCH_CTRL_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_102) == 32'h00002000); - assign _zz__zz_decode_BRANCH_CTRL_2_103 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_104) == 32'h00001000); - assign _zz__zz_decode_BRANCH_CTRL_2_105 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_106) == 32'h00000070); - assign _zz__zz_decode_BRANCH_CTRL_2_107 = (|(_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109)); - assign _zz__zz_decode_BRANCH_CTRL_2_110 = (|{_zz__zz_decode_BRANCH_CTRL_2_111,_zz__zz_decode_BRANCH_CTRL_2_112}); - assign _zz__zz_decode_BRANCH_CTRL_2_113 = {(|_zz__zz_decode_BRANCH_CTRL_2_114),{_zz__zz_decode_BRANCH_CTRL_2_115,{_zz__zz_decode_BRANCH_CTRL_2_120,_zz__zz_decode_BRANCH_CTRL_2_125}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_102 = 32'h00002010; - assign _zz__zz_decode_BRANCH_CTRL_2_104 = 32'h00005000; - assign _zz__zz_decode_BRANCH_CTRL_2_106 = 32'h10003070; - assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h10003034); - assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h10000030; - assign _zz__zz_decode_BRANCH_CTRL_2_111 = ((decode_INSTRUCTION & 32'h00001070) == 32'h00001070); - assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00002070) == 32'h00002070); - assign _zz__zz_decode_BRANCH_CTRL_2_114 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz__zz_decode_BRANCH_CTRL_2_115 = (|{(_zz__zz_decode_BRANCH_CTRL_2_116 == _zz__zz_decode_BRANCH_CTRL_2_117),(_zz__zz_decode_BRANCH_CTRL_2_118 == _zz__zz_decode_BRANCH_CTRL_2_119)}); - assign _zz__zz_decode_BRANCH_CTRL_2_120 = (|{_zz__zz_decode_BRANCH_CTRL_2_121,{_zz__zz_decode_BRANCH_CTRL_2_122,_zz__zz_decode_BRANCH_CTRL_2_123}}); - assign _zz__zz_decode_BRANCH_CTRL_2_125 = {(|_zz_decode_BRANCH_CTRL_12),{(|_zz__zz_decode_BRANCH_CTRL_2_126),{_zz__zz_decode_BRANCH_CTRL_2_135,{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_155}}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_116 = (decode_INSTRUCTION & 32'h00000034); - assign _zz__zz_decode_BRANCH_CTRL_2_117 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_118 = (decode_INSTRUCTION & 32'h00000064); - assign _zz__zz_decode_BRANCH_CTRL_2_119 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_121 = ((decode_INSTRUCTION & 32'h00000030) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_122 = _zz_decode_BRANCH_CTRL_6; - assign _zz__zz_decode_BRANCH_CTRL_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_124) == 32'h00000060); - assign _zz__zz_decode_BRANCH_CTRL_2_126 = {_zz_decode_BRANCH_CTRL_11,{_zz__zz_decode_BRANCH_CTRL_2_127,{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_132}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_135 = (|{_zz_decode_BRANCH_CTRL_11,{_zz__zz_decode_BRANCH_CTRL_2_136,_zz__zz_decode_BRANCH_CTRL_2_137}}); - assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz__zz_decode_BRANCH_CTRL_2_142}); - assign _zz__zz_decode_BRANCH_CTRL_2_155 = {(|_zz__zz_decode_BRANCH_CTRL_2_156),{_zz__zz_decode_BRANCH_CTRL_2_161,{_zz__zz_decode_BRANCH_CTRL_2_166,_zz__zz_decode_BRANCH_CTRL_2_172}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_124 = 32'h00003060; - assign _zz__zz_decode_BRANCH_CTRL_2_127 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_128) == 32'h00004020); - assign _zz__zz_decode_BRANCH_CTRL_2_129 = (_zz__zz_decode_BRANCH_CTRL_2_130 == _zz__zz_decode_BRANCH_CTRL_2_131); - assign _zz__zz_decode_BRANCH_CTRL_2_132 = {_zz__zz_decode_BRANCH_CTRL_2_133,_zz_decode_BRANCH_CTRL_10}; - assign _zz__zz_decode_BRANCH_CTRL_2_136 = _zz_decode_BRANCH_CTRL_10; - assign _zz__zz_decode_BRANCH_CTRL_2_137 = (_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139); - assign _zz__zz_decode_BRANCH_CTRL_2_141 = _zz_decode_BRANCH_CTRL_9; - assign _zz__zz_decode_BRANCH_CTRL_2_142 = {_zz__zz_decode_BRANCH_CTRL_2_143,{_zz__zz_decode_BRANCH_CTRL_2_145,_zz__zz_decode_BRANCH_CTRL_2_148}}; - assign _zz__zz_decode_BRANCH_CTRL_2_156 = {_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_157,_zz__zz_decode_BRANCH_CTRL_2_158}}; - assign _zz__zz_decode_BRANCH_CTRL_2_161 = (|{_zz__zz_decode_BRANCH_CTRL_2_162,_zz__zz_decode_BRANCH_CTRL_2_163}); - assign _zz__zz_decode_BRANCH_CTRL_2_166 = (|_zz__zz_decode_BRANCH_CTRL_2_167); - assign _zz__zz_decode_BRANCH_CTRL_2_172 = {_zz__zz_decode_BRANCH_CTRL_2_173,{_zz__zz_decode_BRANCH_CTRL_2_176,_zz__zz_decode_BRANCH_CTRL_2_186}}; - assign _zz__zz_decode_BRANCH_CTRL_2_128 = 32'h00004020; - assign _zz__zz_decode_BRANCH_CTRL_2_130 = (decode_INSTRUCTION & 32'h00000060); - assign _zz__zz_decode_BRANCH_CTRL_2_131 = 32'h00000060; - assign _zz__zz_decode_BRANCH_CTRL_2_133 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_134) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h02000060); - assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_143 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_144) == 32'h00000010); - assign _zz__zz_decode_BRANCH_CTRL_2_145 = (_zz__zz_decode_BRANCH_CTRL_2_146 == _zz__zz_decode_BRANCH_CTRL_2_147); - assign _zz__zz_decode_BRANCH_CTRL_2_148 = {_zz__zz_decode_BRANCH_CTRL_2_149,{_zz__zz_decode_BRANCH_CTRL_2_151,_zz__zz_decode_BRANCH_CTRL_2_152}}; - assign _zz__zz_decode_BRANCH_CTRL_2_157 = _zz_decode_BRANCH_CTRL_4; - assign _zz__zz_decode_BRANCH_CTRL_2_158 = {_zz_decode_BRANCH_CTRL_7,_zz__zz_decode_BRANCH_CTRL_2_159}; - assign _zz__zz_decode_BRANCH_CTRL_2_162 = _zz_decode_BRANCH_CTRL_5; - assign _zz__zz_decode_BRANCH_CTRL_2_163 = {_zz__zz_decode_BRANCH_CTRL_2_164,_zz_decode_BRANCH_CTRL_7}; - assign _zz__zz_decode_BRANCH_CTRL_2_167 = {_zz__zz_decode_BRANCH_CTRL_2_168,_zz__zz_decode_BRANCH_CTRL_2_170}; + assign _zz__zz_decode_BRANCH_CTRL_2_101 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_102 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_103 = _zz_decode_BRANCH_CTRL_13; + assign _zz__zz_decode_BRANCH_CTRL_2_104 = (|_zz_decode_BRANCH_CTRL_13); + assign _zz__zz_decode_BRANCH_CTRL_2_105 = (|(_zz__zz_decode_BRANCH_CTRL_2_106 == _zz__zz_decode_BRANCH_CTRL_2_107)); + assign _zz__zz_decode_BRANCH_CTRL_2_108 = {(|{_zz__zz_decode_BRANCH_CTRL_2_109,_zz__zz_decode_BRANCH_CTRL_2_110}),{(|_zz__zz_decode_BRANCH_CTRL_2_111),{_zz__zz_decode_BRANCH_CTRL_2_112,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_122}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_106 = (decode_INSTRUCTION & 32'h10003034); + assign _zz__zz_decode_BRANCH_CTRL_2_107 = 32'h10000030; + assign _zz__zz_decode_BRANCH_CTRL_2_109 = ((decode_INSTRUCTION & 32'h00001070) == 32'h00001070); + assign _zz__zz_decode_BRANCH_CTRL_2_110 = ((decode_INSTRUCTION & 32'h00002070) == 32'h00002070); + assign _zz__zz_decode_BRANCH_CTRL_2_111 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_BRANCH_CTRL_2_112 = (|{(_zz__zz_decode_BRANCH_CTRL_2_113 == _zz__zz_decode_BRANCH_CTRL_2_114),(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116)}); + assign _zz__zz_decode_BRANCH_CTRL_2_117 = (|{_zz__zz_decode_BRANCH_CTRL_2_118,{_zz__zz_decode_BRANCH_CTRL_2_119,_zz__zz_decode_BRANCH_CTRL_2_120}}); + assign _zz__zz_decode_BRANCH_CTRL_2_122 = {(|_zz_decode_BRANCH_CTRL_12),{(|_zz__zz_decode_BRANCH_CTRL_2_123),{_zz__zz_decode_BRANCH_CTRL_2_132,{_zz__zz_decode_BRANCH_CTRL_2_137,_zz__zz_decode_BRANCH_CTRL_2_152}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_113 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_BRANCH_CTRL_2_114 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_118 = ((decode_INSTRUCTION & 32'h00000030) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_119 = _zz_decode_BRANCH_CTRL_6; + assign _zz__zz_decode_BRANCH_CTRL_2_120 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_121) == 32'h00000060); + assign _zz__zz_decode_BRANCH_CTRL_2_123 = {_zz_decode_BRANCH_CTRL_11,{_zz__zz_decode_BRANCH_CTRL_2_124,{_zz__zz_decode_BRANCH_CTRL_2_126,_zz__zz_decode_BRANCH_CTRL_2_129}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_132 = (|{_zz_decode_BRANCH_CTRL_11,{_zz__zz_decode_BRANCH_CTRL_2_133,_zz__zz_decode_BRANCH_CTRL_2_134}}); + assign _zz__zz_decode_BRANCH_CTRL_2_137 = (|{_zz__zz_decode_BRANCH_CTRL_2_138,_zz__zz_decode_BRANCH_CTRL_2_139}); + assign _zz__zz_decode_BRANCH_CTRL_2_152 = {(|_zz__zz_decode_BRANCH_CTRL_2_153),{_zz__zz_decode_BRANCH_CTRL_2_158,{_zz__zz_decode_BRANCH_CTRL_2_163,_zz__zz_decode_BRANCH_CTRL_2_169}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00003060; + assign _zz__zz_decode_BRANCH_CTRL_2_124 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_125) == 32'h00004020); + assign _zz__zz_decode_BRANCH_CTRL_2_126 = (_zz__zz_decode_BRANCH_CTRL_2_127 == _zz__zz_decode_BRANCH_CTRL_2_128); + assign _zz__zz_decode_BRANCH_CTRL_2_129 = {_zz__zz_decode_BRANCH_CTRL_2_130,_zz_decode_BRANCH_CTRL_10}; + assign _zz__zz_decode_BRANCH_CTRL_2_133 = _zz_decode_BRANCH_CTRL_10; + assign _zz__zz_decode_BRANCH_CTRL_2_134 = (_zz__zz_decode_BRANCH_CTRL_2_135 == _zz__zz_decode_BRANCH_CTRL_2_136); + assign _zz__zz_decode_BRANCH_CTRL_2_138 = _zz_decode_BRANCH_CTRL_9; + assign _zz__zz_decode_BRANCH_CTRL_2_139 = {_zz__zz_decode_BRANCH_CTRL_2_140,{_zz__zz_decode_BRANCH_CTRL_2_142,_zz__zz_decode_BRANCH_CTRL_2_145}}; + assign _zz__zz_decode_BRANCH_CTRL_2_153 = {_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_154,_zz__zz_decode_BRANCH_CTRL_2_155}}; + assign _zz__zz_decode_BRANCH_CTRL_2_158 = (|{_zz__zz_decode_BRANCH_CTRL_2_159,_zz__zz_decode_BRANCH_CTRL_2_160}); + assign _zz__zz_decode_BRANCH_CTRL_2_163 = (|_zz__zz_decode_BRANCH_CTRL_2_164); + assign _zz__zz_decode_BRANCH_CTRL_2_169 = {_zz__zz_decode_BRANCH_CTRL_2_170,{_zz__zz_decode_BRANCH_CTRL_2_173,_zz__zz_decode_BRANCH_CTRL_2_183}}; + assign _zz__zz_decode_BRANCH_CTRL_2_125 = 32'h00004020; + assign _zz__zz_decode_BRANCH_CTRL_2_127 = (decode_INSTRUCTION & 32'h00000060); + assign _zz__zz_decode_BRANCH_CTRL_2_128 = 32'h00000060; + assign _zz__zz_decode_BRANCH_CTRL_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_131) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_135 = (decode_INSTRUCTION & 32'h02000060); + assign _zz__zz_decode_BRANCH_CTRL_2_136 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_140 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_141) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_142 = (_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144); + assign _zz__zz_decode_BRANCH_CTRL_2_145 = {_zz__zz_decode_BRANCH_CTRL_2_146,{_zz__zz_decode_BRANCH_CTRL_2_148,_zz__zz_decode_BRANCH_CTRL_2_149}}; + assign _zz__zz_decode_BRANCH_CTRL_2_154 = _zz_decode_BRANCH_CTRL_4; + assign _zz__zz_decode_BRANCH_CTRL_2_155 = {_zz_decode_BRANCH_CTRL_7,_zz__zz_decode_BRANCH_CTRL_2_156}; + assign _zz__zz_decode_BRANCH_CTRL_2_159 = _zz_decode_BRANCH_CTRL_5; + assign _zz__zz_decode_BRANCH_CTRL_2_160 = {_zz__zz_decode_BRANCH_CTRL_2_161,_zz_decode_BRANCH_CTRL_7}; + assign _zz__zz_decode_BRANCH_CTRL_2_164 = {_zz__zz_decode_BRANCH_CTRL_2_165,_zz__zz_decode_BRANCH_CTRL_2_167}; + assign _zz__zz_decode_BRANCH_CTRL_2_170 = (|_zz__zz_decode_BRANCH_CTRL_2_171); assign _zz__zz_decode_BRANCH_CTRL_2_173 = (|_zz__zz_decode_BRANCH_CTRL_2_174); - assign _zz__zz_decode_BRANCH_CTRL_2_176 = (|_zz__zz_decode_BRANCH_CTRL_2_177); - assign _zz__zz_decode_BRANCH_CTRL_2_186 = {_zz__zz_decode_BRANCH_CTRL_2_187,{_zz__zz_decode_BRANCH_CTRL_2_188,_zz__zz_decode_BRANCH_CTRL_2_194}}; - assign _zz__zz_decode_BRANCH_CTRL_2_134 = 32'h02000020; - assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00000050; - assign _zz__zz_decode_BRANCH_CTRL_2_146 = (decode_INSTRUCTION & 32'h00001030); - assign _zz__zz_decode_BRANCH_CTRL_2_147 = 32'h00001030; - assign _zz__zz_decode_BRANCH_CTRL_2_149 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_150) == 32'h00002030); - assign _zz__zz_decode_BRANCH_CTRL_2_151 = _zz_decode_BRANCH_CTRL_8; - assign _zz__zz_decode_BRANCH_CTRL_2_152 = {_zz__zz_decode_BRANCH_CTRL_2_153,_zz__zz_decode_BRANCH_CTRL_2_154}; - assign _zz__zz_decode_BRANCH_CTRL_2_159 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_160) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_165) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_168 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_169) == 32'h00006010); - assign _zz__zz_decode_BRANCH_CTRL_2_170 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_171) == 32'h00004010); - assign _zz__zz_decode_BRANCH_CTRL_2_174 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_175) == 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_177 = {_zz__zz_decode_BRANCH_CTRL_2_178,{_zz__zz_decode_BRANCH_CTRL_2_179,_zz__zz_decode_BRANCH_CTRL_2_181}}; - assign _zz__zz_decode_BRANCH_CTRL_2_187 = (|_zz_decode_BRANCH_CTRL_6); - assign _zz__zz_decode_BRANCH_CTRL_2_188 = (|_zz__zz_decode_BRANCH_CTRL_2_189); - assign _zz__zz_decode_BRANCH_CTRL_2_194 = {_zz__zz_decode_BRANCH_CTRL_2_195,_zz__zz_decode_BRANCH_CTRL_2_198}; - assign _zz__zz_decode_BRANCH_CTRL_2_150 = 32'h00002030; - assign _zz__zz_decode_BRANCH_CTRL_2_153 = ((decode_INSTRUCTION & 32'h00002024) == 32'h00000024); - assign _zz__zz_decode_BRANCH_CTRL_2_154 = ((decode_INSTRUCTION & 32'h00000064) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_160 = 32'h00000070; - assign _zz__zz_decode_BRANCH_CTRL_2_165 = 32'h00000020; - assign _zz__zz_decode_BRANCH_CTRL_2_169 = 32'h00006014; - assign _zz__zz_decode_BRANCH_CTRL_2_171 = 32'h00005014; - assign _zz__zz_decode_BRANCH_CTRL_2_175 = 32'h00006014; - assign _zz__zz_decode_BRANCH_CTRL_2_178 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz__zz_decode_BRANCH_CTRL_2_179 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_180) == 32'h00000020); - assign _zz__zz_decode_BRANCH_CTRL_2_181 = {(_zz__zz_decode_BRANCH_CTRL_2_182 == _zz__zz_decode_BRANCH_CTRL_2_183),{_zz_decode_BRANCH_CTRL_6,{_zz__zz_decode_BRANCH_CTRL_2_184,_zz__zz_decode_BRANCH_CTRL_2_185}}}; - assign _zz__zz_decode_BRANCH_CTRL_2_189 = {(_zz__zz_decode_BRANCH_CTRL_2_190 == _zz__zz_decode_BRANCH_CTRL_2_191),{_zz__zz_decode_BRANCH_CTRL_2_192,_zz__zz_decode_BRANCH_CTRL_2_193}}; - assign _zz__zz_decode_BRANCH_CTRL_2_195 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_196,_zz__zz_decode_BRANCH_CTRL_2_197}}); - assign _zz__zz_decode_BRANCH_CTRL_2_198 = (|{_zz_decode_BRANCH_CTRL_4,_zz_decode_BRANCH_CTRL_3}); - assign _zz__zz_decode_BRANCH_CTRL_2_180 = 32'h00000038; - assign _zz__zz_decode_BRANCH_CTRL_2_182 = (decode_INSTRUCTION & 32'h00004050); - assign _zz__zz_decode_BRANCH_CTRL_2_183 = 32'h00004000; - assign _zz__zz_decode_BRANCH_CTRL_2_184 = ((decode_INSTRUCTION & 32'h00006024) == 32'h00002020); - assign _zz__zz_decode_BRANCH_CTRL_2_185 = {((decode_INSTRUCTION & 32'h00005024) == 32'h00001020),((decode_INSTRUCTION & 32'h90000034) == 32'h90000010)}; - assign _zz__zz_decode_BRANCH_CTRL_2_190 = (decode_INSTRUCTION & 32'h00000044); - assign _zz__zz_decode_BRANCH_CTRL_2_191 = 32'h00000040; - assign _zz__zz_decode_BRANCH_CTRL_2_192 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz__zz_decode_BRANCH_CTRL_2_193 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz__zz_decode_BRANCH_CTRL_2_196 = _zz_decode_BRANCH_CTRL_3; - assign _zz__zz_decode_BRANCH_CTRL_2_197 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_183 = {_zz__zz_decode_BRANCH_CTRL_2_184,{_zz__zz_decode_BRANCH_CTRL_2_185,_zz__zz_decode_BRANCH_CTRL_2_191}}; + assign _zz__zz_decode_BRANCH_CTRL_2_131 = 32'h02000020; + assign _zz__zz_decode_BRANCH_CTRL_2_141 = 32'h00000050; + assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001030; + assign _zz__zz_decode_BRANCH_CTRL_2_146 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_147) == 32'h00002030); + assign _zz__zz_decode_BRANCH_CTRL_2_148 = _zz_decode_BRANCH_CTRL_8; + assign _zz__zz_decode_BRANCH_CTRL_2_149 = {_zz__zz_decode_BRANCH_CTRL_2_150,_zz__zz_decode_BRANCH_CTRL_2_151}; + assign _zz__zz_decode_BRANCH_CTRL_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_157) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_161 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_162) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_165 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_166) == 32'h00006010); + assign _zz__zz_decode_BRANCH_CTRL_2_167 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_168) == 32'h00004010); + assign _zz__zz_decode_BRANCH_CTRL_2_171 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_172) == 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_174 = {_zz__zz_decode_BRANCH_CTRL_2_175,{_zz__zz_decode_BRANCH_CTRL_2_176,_zz__zz_decode_BRANCH_CTRL_2_178}}; + assign _zz__zz_decode_BRANCH_CTRL_2_184 = (|_zz_decode_BRANCH_CTRL_6); + assign _zz__zz_decode_BRANCH_CTRL_2_185 = (|_zz__zz_decode_BRANCH_CTRL_2_186); + assign _zz__zz_decode_BRANCH_CTRL_2_191 = {_zz__zz_decode_BRANCH_CTRL_2_192,_zz__zz_decode_BRANCH_CTRL_2_195}; + assign _zz__zz_decode_BRANCH_CTRL_2_147 = 32'h00002030; + assign _zz__zz_decode_BRANCH_CTRL_2_150 = ((decode_INSTRUCTION & 32'h00002024) == 32'h00000024); + assign _zz__zz_decode_BRANCH_CTRL_2_151 = ((decode_INSTRUCTION & 32'h00000064) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_157 = 32'h00000070; + assign _zz__zz_decode_BRANCH_CTRL_2_162 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_166 = 32'h00006014; + assign _zz__zz_decode_BRANCH_CTRL_2_168 = 32'h00005014; + assign _zz__zz_decode_BRANCH_CTRL_2_172 = 32'h00006014; + assign _zz__zz_decode_BRANCH_CTRL_2_175 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_176 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_177) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_178 = {(_zz__zz_decode_BRANCH_CTRL_2_179 == _zz__zz_decode_BRANCH_CTRL_2_180),{_zz_decode_BRANCH_CTRL_6,{_zz__zz_decode_BRANCH_CTRL_2_181,_zz__zz_decode_BRANCH_CTRL_2_182}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_186 = {(_zz__zz_decode_BRANCH_CTRL_2_187 == _zz__zz_decode_BRANCH_CTRL_2_188),{_zz__zz_decode_BRANCH_CTRL_2_189,_zz__zz_decode_BRANCH_CTRL_2_190}}; + assign _zz__zz_decode_BRANCH_CTRL_2_192 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_193,_zz__zz_decode_BRANCH_CTRL_2_194}}); + assign _zz__zz_decode_BRANCH_CTRL_2_195 = (|{_zz_decode_BRANCH_CTRL_4,_zz_decode_BRANCH_CTRL_3}); + assign _zz__zz_decode_BRANCH_CTRL_2_177 = 32'h00000038; + assign _zz__zz_decode_BRANCH_CTRL_2_179 = (decode_INSTRUCTION & 32'h00004050); + assign _zz__zz_decode_BRANCH_CTRL_2_180 = 32'h00004000; + assign _zz__zz_decode_BRANCH_CTRL_2_181 = ((decode_INSTRUCTION & 32'h00006024) == 32'h00002020); + assign _zz__zz_decode_BRANCH_CTRL_2_182 = {((decode_INSTRUCTION & 32'h00005024) == 32'h00001020),((decode_INSTRUCTION & 32'h90000034) == 32'h90000010)}; + assign _zz__zz_decode_BRANCH_CTRL_2_187 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_BRANCH_CTRL_2_188 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_189 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_190 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz__zz_decode_BRANCH_CTRL_2_193 = _zz_decode_BRANCH_CTRL_3; + assign _zz__zz_decode_BRANCH_CTRL_2_194 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00000004); always @(posedge clk) begin if(_zz_decode_RegFilePlugin_rs1Data) begin _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; @@ -2030,6 +2117,42 @@ module VexRiscv ( .clk (clk ), //i .reset (reset ) //i ); + JtagBridge jtagBridge_1 ( + .io_jtag_tms (jtag_tms ), //i + .io_jtag_tdi (jtag_tdi ), //i + .io_jtag_tdo (jtagBridge_1_io_jtag_tdo ), //o + .io_jtag_tck (jtag_tck ), //i + .io_remote_cmd_valid (jtagBridge_1_io_remote_cmd_valid ), //o + .io_remote_cmd_ready (systemDebugger_1_io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (jtagBridge_1_io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (jtagBridge_1_io_remote_cmd_payload_fragment ), //o + .io_remote_rsp_valid (systemDebugger_1_io_remote_rsp_valid ), //i + .io_remote_rsp_ready (jtagBridge_1_io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (systemDebugger_1_io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (systemDebugger_1_io_remote_rsp_payload_data[31:0]), //i + .clk (clk ), //i + .reset (reset ) //i + ); + SystemDebugger systemDebugger_1 ( + .io_remote_cmd_valid (jtagBridge_1_io_remote_cmd_valid ), //i + .io_remote_cmd_ready (systemDebugger_1_io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (jtagBridge_1_io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (jtagBridge_1_io_remote_cmd_payload_fragment ), //i + .io_remote_rsp_valid (systemDebugger_1_io_remote_rsp_valid ), //o + .io_remote_rsp_ready (jtagBridge_1_io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (systemDebugger_1_io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (systemDebugger_1_io_remote_rsp_payload_data[31:0]), //o + .io_mem_cmd_valid (systemDebugger_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (debug_bus_cmd_ready ), //i + .io_mem_cmd_payload_address (systemDebugger_1_io_mem_cmd_payload_address[31:0]), //o + .io_mem_cmd_payload_data (systemDebugger_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (systemDebugger_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (systemDebugger_1_io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (debug_bus_cmd_fire_regNext ), //i + .io_mem_rsp_payload (debug_bus_rsp_data[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); always @(*) begin case(_zz_IBusSimplePlugin_jump_pcLoad_payload_5) 2'b00 : _zz_IBusSimplePlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; @@ -2914,12 +3037,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_decode_BRANCH_CTRL_14) - BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_14_string = "INC "; - BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_14_string = "B "; - BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_14_string = "JAL "; - BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_14_string = "JALR"; - default : _zz_decode_BRANCH_CTRL_14_string = "????"; + case(_zz_decode_BRANCH_CTRL_15) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_15_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_15_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_15_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_15_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_15_string = "????"; endcase end always @(*) begin @@ -3161,6 +3284,7 @@ module VexRiscv ( assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || (((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && _zz_decode_DO_EBREAK)) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_decode_DO_EBREAK_2))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_decode_DO_EBREAK_3))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_decode_DO_EBREAK_4))) || (DebugPlugin_hardwareBreakpoints_4_valid && (DebugPlugin_hardwareBreakpoints_4_pc == _zz_decode_DO_EBREAK_5))))) && DebugPlugin_allowEBreak); assign memory_FPU_COMMIT_LOAD = execute_to_memory_FPU_COMMIT_LOAD; assign execute_FPU_COMMIT_LOAD = decode_to_execute_FPU_COMMIT_LOAD; assign decode_FPU_COMMIT_LOAD = (decode_FPU_OPCODE == FpuOpcode_LOAD); @@ -3184,21 +3308,21 @@ module VexRiscv ( assign _zz_decode_to_execute_FPU_OPCODE = _zz_decode_to_execute_FPU_OPCODE_1; assign memory_FPU_RSP = execute_to_memory_FPU_RSP; assign execute_FPU_RSP = decode_to_execute_FPU_RSP; - assign decode_FPU_RSP = _zz_decode_BRANCH_CTRL_2[29]; + assign decode_FPU_RSP = _zz_decode_BRANCH_CTRL_2[30]; assign memory_FPU_COMMIT = execute_to_memory_FPU_COMMIT; assign execute_FPU_COMMIT = decode_to_execute_FPU_COMMIT; - assign decode_FPU_COMMIT = _zz_decode_BRANCH_CTRL_2[28]; + assign decode_FPU_COMMIT = _zz_decode_BRANCH_CTRL_2[29]; assign memory_FPU_ENABLE = execute_to_memory_FPU_ENABLE; assign execute_FPU_ENABLE = decode_to_execute_FPU_ENABLE; - assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; - assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; - assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; + assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[27]; + assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; + assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[25]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; + assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[24]; assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; - assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[19]; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[20]; assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; @@ -3220,6 +3344,8 @@ module VexRiscv ( assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_decode_FORMAL_PC_NEXT); assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[19]; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; @@ -3267,9 +3393,9 @@ module VexRiscv ( assign writeBack_FPU_COMMIT = memory_to_writeBack_FPU_COMMIT; assign writeBack_FPU_RSP = memory_to_writeBack_FPU_RSP; assign writeBack_FPU_FORKED = memory_to_writeBack_FPU_FORKED; - assign decode_FPU_ARG = _zz_decode_BRANCH_CTRL_2[36 : 35]; + assign decode_FPU_ARG = _zz_decode_BRANCH_CTRL_2[37 : 36]; assign decode_FPU_OPCODE = _zz_decode_FPU_OPCODE; - assign decode_FPU_ENABLE = _zz_decode_BRANCH_CTRL_2[27]; + assign decode_FPU_ENABLE = _zz_decode_BRANCH_CTRL_2[28]; assign writeBack_FPU_OPCODE = _zz_writeBack_FPU_OPCODE; assign writeBack_FPU_ENABLE = memory_to_writeBack_FPU_ENABLE; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; @@ -3299,7 +3425,7 @@ module VexRiscv ( assign _zz_decode_SRC1 = decode_RS1; assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[2]; - assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[22]; + assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[23]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; @@ -3400,6 +3526,13 @@ module VexRiscv ( if(FpuPlugin_port_cmd_isStall) begin decode_arbitration_haltItself = 1'b1; end + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase end always @(*) begin @@ -3458,6 +3591,9 @@ module VexRiscv ( if(when_FpuPlugin_l214) begin execute_arbitration_haltByOther = 1'b1; end + if(when_DebugPlugin_l295) begin + execute_arbitration_haltByOther = 1'b1; + end end always @(*) begin @@ -3470,12 +3606,31 @@ module VexRiscv ( end end - assign execute_arbitration_flushIt = 1'b0; + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + always @(*) begin execute_arbitration_flushNext = 1'b0; if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushNext = 1'b1; + end + end + if(_zz_3) begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_3) begin + execute_arbitration_flushNext = 1'b1; + end end always @(*) begin @@ -3570,9 +3725,26 @@ module VexRiscv ( if(when_CsrPlugin_l1077) begin IBusSimplePlugin_fetcherHalt = 1'b1; end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l311) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @(*) begin + IBusSimplePlugin_forceNoDecodeCond = 1'b0; + if(_zz_3) begin + IBusSimplePlugin_forceNoDecodeCond = 1'b1; + end end - assign IBusSimplePlugin_forceNoDecodeCond = 1'b0; always @(*) begin IBusSimplePlugin_incomingInstruction = 1'b0; if(IBusSimplePlugin_iBusRsp_stages_1_input_valid) begin @@ -3583,6 +3755,13 @@ module VexRiscv ( end end + always @(*) begin + _zz_when_DBusCachedPlugin_l393 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l393 = 1'b1; + end + end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; @@ -3591,6 +3770,9 @@ module VexRiscv ( if(decode_FpuPlugin_forked) begin CsrPlugin_thirdPartyWake = 1'b1; end + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end end always @(*) begin @@ -3619,11 +3801,41 @@ module VexRiscv ( end end - assign CsrPlugin_forceMachineWire = 1'b0; - assign CsrPlugin_allowInterrupts = 1'b1; - assign CsrPlugin_allowException = 1'b1; - assign CsrPlugin_allowEbreakException = 1'b1; - assign BranchPlugin_inDebugNoFetchFlag = 1'b0; + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l331) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + always @(*) begin + BranchPlugin_inDebugNoFetchFlag = 1'b0; + if(DebugPlugin_godmode) begin + BranchPlugin_inDebugNoFetchFlag = 1'b1; + end + end + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); assign _zz_IBusSimplePlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; @@ -3679,7 +3891,13 @@ module VexRiscv ( end assign IBusSimplePlugin_decodePc_pcPlus = (IBusSimplePlugin_decodePc_pcReg + _zz_IBusSimplePlugin_decodePc_pcPlus); - assign IBusSimplePlugin_decodePc_injectedDecode = 1'b0; + always @(*) begin + IBusSimplePlugin_decodePc_injectedDecode = 1'b0; + if(when_Fetcher_l363) begin + IBusSimplePlugin_decodePc_injectedDecode = 1'b1; + end + end + assign when_Fetcher_l183 = (decode_arbitration_isFiring && (! IBusSimplePlugin_decodePc_injectedDecode)); assign when_Fetcher_l195 = (IBusSimplePlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; @@ -3957,6 +4175,16 @@ module VexRiscv ( assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); always @(*) begin decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase if(IBusSimplePlugin_forceNoDecodeCond) begin decode_arbitration_isValid = 1'b0; end @@ -4071,7 +4299,7 @@ module VexRiscv ( end end - assign when_DBusCachedPlugin_l393 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); always @(*) begin dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_arbitration_haltByOther) begin @@ -4461,7 +4689,8 @@ module VexRiscv ( assign _zz_decode_BRANCH_CTRL_10 = ((decode_INSTRUCTION & 32'h00000070) == 32'h00000010); assign _zz_decode_BRANCH_CTRL_11 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_decode_BRANCH_CTRL_12 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_decode_BRANCH_CTRL_13 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_BRANCH_CTRL_13 = ((decode_INSTRUCTION & 32'h10003070) == 32'h00000070); + assign _zz_decode_BRANCH_CTRL_14 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_9,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|{_zz__zz_decode_BRANCH_CTRL_2_4,_zz__zz_decode_BRANCH_CTRL_2_6}),{(|_zz__zz_decode_BRANCH_CTRL_2_8),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_24}}}}}}; assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[1 : 0]; assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; @@ -4471,14 +4700,14 @@ module VexRiscv ( assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[18 : 17]; assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; - assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[21 : 20]; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; - assign _zz_decode_FPU_OPCODE_2 = _zz_decode_BRANCH_CTRL_2[33 : 30]; + assign _zz_decode_FPU_OPCODE_2 = _zz_decode_BRANCH_CTRL_2[34 : 31]; assign _zz_decode_FPU_OPCODE_1 = _zz_decode_FPU_OPCODE_2; - assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[38 : 37]; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[39 : 38]; assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; - assign _zz_decode_BRANCH_CTRL_14 = _zz_decode_BRANCH_CTRL_2[40 : 39]; - assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_14; + assign _zz_decode_BRANCH_CTRL_15 = _zz_decode_BRANCH_CTRL_2[41 : 40]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_15; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; @@ -5018,6 +5247,65 @@ module VexRiscv ( assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l244) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin + IBusSimplePlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + IBusSimplePlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); assign when_Pipeline_l124 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); @@ -5113,18 +5401,19 @@ module VexRiscv ( assign when_Pipeline_l124_64 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_65 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_66 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_67 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_68 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_69 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); - assign when_Pipeline_l124_70 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_71 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_67 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_68 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_69 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_70 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); + assign when_Pipeline_l124_71 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_72 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_73 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_74 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_75 = (! writeBack_arbitration_isStuck); - assign when_Pipeline_l124_76 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_75 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_76 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_77 = (! memory_arbitration_isStuck); - assign when_Pipeline_l124_78 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_78 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_79 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -5151,6 +5440,20 @@ module VexRiscv ( assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + IBusSimplePlugin_injectionPort_ready = 1'b0; + case(switch_Fetcher_l365) + 3'b100 : begin + IBusSimplePlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l363 = (switch_Fetcher_l365 != 3'b000); + assign when_Fetcher_l381 = (! decode_arbitration_isStuck); + assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); @@ -5280,6 +5583,12 @@ module VexRiscv ( assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; + assign debug_bus_cmd_valid = systemDebugger_1_io_mem_cmd_valid; + assign debug_bus_cmd_payload_wr = systemDebugger_1_io_mem_cmd_payload_wr; + assign debug_bus_cmd_payload_data = systemDebugger_1_io_mem_cmd_payload_data; + assign debug_bus_cmd_payload_address = systemDebugger_1_io_mem_cmd_payload_address[7:0]; + assign debug_bus_cmd_fire = (debug_bus_cmd_valid && debug_bus_cmd_ready); + assign jtag_tdo = jtagBridge_1_io_jtag_tdo; always @(posedge clk or posedge reset) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= 32'h20000000; @@ -5332,15 +5641,30 @@ module VexRiscv ( writeBack_FpuPlugin_commit_rValid <= 1'b0; execute_LightShifterPlugin_isActive <= 1'b0; HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_4_valid <= 1'b0; + _zz_3 <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; + switch_Fetcher_l365 <= 3'b000; decode_to_execute_FPU_FORKED <= 1'b0; execute_to_memory_FPU_FORKED <= 1'b0; memory_to_writeBack_FPU_FORKED <= 1'b0; iBus_cmd_rValid <= 1'b0; _zz_dBus_cmd_ready <= 1'b0; _zz_dBus_rsp_valid <= 1'b0; + debug_bus_cmd_fire_regNext <= 1'b0; end else begin if(IBusSimplePlugin_fetchPc_correction) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; @@ -5562,6 +5886,84 @@ module VexRiscv ( execute_LightShifterPlugin_isActive <= 1'b0; end HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_DebugPlugin_l225) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l271) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l271_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l272) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l272_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l273) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l274) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l275) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l275_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + 6'h10 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_0_valid <= debug_bus_cmd_payload_data[0]; + end + end + 6'h11 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_1_valid <= debug_bus_cmd_payload_data[0]; + end + end + 6'h12 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_2_valid <= debug_bus_cmd_payload_data[0]; + end + end + 6'h13 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_3_valid <= debug_bus_cmd_payload_data[0]; + end + end + 6'h14 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_4_valid <= debug_bus_cmd_payload_data[0]; + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l311) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + _zz_3 <= (DebugPlugin_stepIt && decode_arbitration_isFiring); if(when_Pipeline_l124_61) begin decode_to_execute_FPU_FORKED <= _zz_decode_to_execute_FPU_FORKED; end @@ -5589,6 +5991,29 @@ module VexRiscv ( if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end + case(switch_Fetcher_l365) + 3'b000 : begin + if(IBusSimplePlugin_injectionPort_valid) begin + switch_Fetcher_l365 <= 3'b001; + end + end + 3'b001 : begin + switch_Fetcher_l365 <= 3'b010; + end + 3'b010 : begin + switch_Fetcher_l365 <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l381) begin + switch_Fetcher_l365 <= 3'b100; + end + end + 3'b100 : begin + switch_Fetcher_l365 <= 3'b000; + end + default : begin + end + endcase if(execute_CsrPlugin_csr_768) begin if(execute_CsrPlugin_writeEnable) begin CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; @@ -5655,6 +6080,7 @@ module VexRiscv ( end end _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + debug_bus_cmd_fire_regNext <= debug_bus_cmd_fire; end end @@ -5754,6 +6180,51 @@ module VexRiscv ( end HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusSimplePlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_lastStageRegFileWrite_payload_data; + end + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h10 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'h11 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'h12 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'h13 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'h14 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_hardwareBreakpoints_4_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l295) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; if(when_Pipeline_l124) begin decode_to_execute_PC <= _zz_decode_SRC2; end @@ -5947,41 +6418,47 @@ module VexRiscv ( memory_to_writeBack_FPU_COMMIT_LOAD <= memory_FPU_COMMIT_LOAD; end if(when_Pipeline_l124_67) begin - execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end if(when_Pipeline_l124_68) begin - memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end if(when_Pipeline_l124_69) begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end if(when_Pipeline_l124_70) begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_memory_to_writeBack_REGFILE_WRITE_DATA; + execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; end if(when_Pipeline_l124_71) begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_memory_to_writeBack_REGFILE_WRITE_DATA; end if(when_Pipeline_l124_72) begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + execute_to_memory_MUL_LL <= execute_MUL_LL; end if(when_Pipeline_l124_73) begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + execute_to_memory_MUL_LH <= execute_MUL_LH; end if(when_Pipeline_l124_74) begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + execute_to_memory_MUL_HL <= execute_MUL_HL; end if(when_Pipeline_l124_75) begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + execute_to_memory_MUL_HH <= execute_MUL_HH; end if(when_Pipeline_l124_76) begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + memory_to_writeBack_MUL_HH <= memory_MUL_HH; end if(when_Pipeline_l124_77) begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end if(when_Pipeline_l124_78) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_79) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end + if(when_Fetcher_l401) begin + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_injectionPort_payload; + end if(when_CsrPlugin_l1277) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -6021,6 +6498,845 @@ module VexRiscv ( end +endmodule + +module SystemDebugger ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input clk, + input reset +); + + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire when_Fragment_l346; + wire when_Fragment_l349; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire io_mem_cmd_isStall; + wire when_Fragment_l372; + + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); + assign when_Fragment_l349 = (dispatcher_counter == 3'b111); + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; + assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; + assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); + assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @(posedge clk or posedge reset) begin + if(reset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= 3'b000; + end else begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_counter <= (dispatcher_counter + 3'b001); + if(when_Fragment_l349) begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last) begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= 3'b000; + end + end + if(when_Fragment_l372) begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module JtagBridge ( + input io_jtag_tms, + input io_jtag_tdi, + output io_jtag_tdo, + input io_jtag_tck, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input clk, + input reset +); + localparam JtagState_RESET = 4'd0; + localparam JtagState_IDLE = 4'd1; + localparam JtagState_IR_SELECT = 4'd2; + localparam JtagState_IR_CAPTURE = 4'd3; + localparam JtagState_IR_SHIFT = 4'd4; + localparam JtagState_IR_EXIT1 = 4'd5; + localparam JtagState_IR_PAUSE = 4'd6; + localparam JtagState_IR_EXIT2 = 4'd7; + localparam JtagState_IR_UPDATE = 4'd8; + localparam JtagState_DR_SELECT = 4'd9; + localparam JtagState_DR_CAPTURE = 4'd10; + localparam JtagState_DR_SHIFT = 4'd11; + localparam JtagState_DR_EXIT1 = 4'd12; + localparam JtagState_DR_PAUSE = 4'd13; + localparam JtagState_DR_EXIT2 = 4'd14; + localparam JtagState_DR_UPDATE = 4'd15; + + wire flowCCByToggle_1_io_output_valid; + wire flowCCByToggle_1_io_output_payload_last; + wire [0:0] flowCCByToggle_1_io_output_payload_fragment; + wire [3:0] _zz_jtag_tap_isBypass; + wire [3:0] _zz_jtag_tap_isBypass_1; + wire [1:0] _zz_jtag_tap_instructionShift; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + wire system_cmd_toStream_valid; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_payload_last; + wire [0:0] system_cmd_toStream_payload_fragment; + (* async_reg = "true" *) reg system_rsp_valid; + (* async_reg = "true" *) reg system_rsp_payload_error; + (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; + wire io_remote_rsp_fire; + wire [3:0] jtag_tap_fsm_stateNext; + reg [3:0] jtag_tap_fsm_state; + wire [3:0] _zz_jtag_tap_fsm_stateNext; + wire [3:0] _zz_jtag_tap_fsm_stateNext_1; + wire [3:0] _zz_jtag_tap_fsm_stateNext_2; + wire [3:0] _zz_jtag_tap_fsm_stateNext_3; + wire [3:0] _zz_jtag_tap_fsm_stateNext_4; + wire [3:0] _zz_jtag_tap_fsm_stateNext_5; + wire [3:0] _zz_jtag_tap_fsm_stateNext_6; + wire [3:0] _zz_jtag_tap_fsm_stateNext_7; + wire [3:0] _zz_jtag_tap_fsm_stateNext_8; + wire [3:0] _zz_jtag_tap_fsm_stateNext_9; + wire [3:0] _zz_jtag_tap_fsm_stateNext_10; + wire [3:0] _zz_jtag_tap_fsm_stateNext_11; + wire [3:0] _zz_jtag_tap_fsm_stateNext_12; + wire [3:0] _zz_jtag_tap_fsm_stateNext_13; + wire [3:0] _zz_jtag_tap_fsm_stateNext_14; + wire [3:0] _zz_jtag_tap_fsm_stateNext_15; + reg [3:0] _zz_jtag_tap_fsm_stateNext_16; + reg [3:0] jtag_tap_instruction; + reg [3:0] jtag_tap_instructionShift; + reg jtag_tap_bypass; + reg jtag_tap_tdoUnbufferd; + reg jtag_tap_tdoDr; + wire jtag_tap_tdoIr; + wire jtag_tap_isBypass; + reg jtag_tap_tdoUnbufferd_regNext; + wire jtag_idcodeArea_ctrl_tdi; + wire jtag_idcodeArea_ctrl_enable; + wire jtag_idcodeArea_ctrl_capture; + wire jtag_idcodeArea_ctrl_shift; + wire jtag_idcodeArea_ctrl_update; + wire jtag_idcodeArea_ctrl_reset; + wire jtag_idcodeArea_ctrl_tdo; + reg [31:0] jtag_idcodeArea_shifter; + wire when_JtagTap_l120; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_capture; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_update; + wire jtag_writeArea_ctrl_reset; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + reg jtag_writeArea_valid; + reg jtag_writeArea_data; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_update; + wire jtag_readArea_ctrl_reset; + wire jtag_readArea_ctrl_tdo; + reg [33:0] jtag_readArea_full_shifter; + `ifndef SYNTHESIS + reg [79:0] jtag_tap_fsm_stateNext_string; + reg [79:0] jtag_tap_fsm_state_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_1_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_2_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_3_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_4_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_5_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_6_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_7_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_8_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_9_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_10_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_11_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_12_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_13_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_14_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_15_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_16_string; + `endif + + + assign _zz_jtag_tap_isBypass = jtag_tap_instruction; + assign _zz_jtag_tap_isBypass_1 = 4'b1111; + assign _zz_jtag_tap_instructionShift = 2'b01; + FlowCCByToggle flowCCByToggle_1 ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1_io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o + .io_jtag_tck (io_jtag_tck ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + initial begin + `ifndef SYNTHESIS + jtag_tap_fsm_state = {1{$urandom}}; + `endif + end + + `ifndef SYNTHESIS + always @(*) begin + case(jtag_tap_fsm_stateNext) + JtagState_RESET : jtag_tap_fsm_stateNext_string = "RESET "; + JtagState_IDLE : jtag_tap_fsm_stateNext_string = "IDLE "; + JtagState_IR_SELECT : jtag_tap_fsm_stateNext_string = "IR_SELECT "; + JtagState_IR_CAPTURE : jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : jtag_tap_fsm_stateNext_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : jtag_tap_fsm_stateNext_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : jtag_tap_fsm_stateNext_string = "IR_UPDATE "; + JtagState_DR_SELECT : jtag_tap_fsm_stateNext_string = "DR_SELECT "; + JtagState_DR_CAPTURE : jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : jtag_tap_fsm_stateNext_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : jtag_tap_fsm_stateNext_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : jtag_tap_fsm_stateNext_string = "DR_UPDATE "; + default : jtag_tap_fsm_stateNext_string = "??????????"; + endcase + end + always @(*) begin + case(jtag_tap_fsm_state) + JtagState_RESET : jtag_tap_fsm_state_string = "RESET "; + JtagState_IDLE : jtag_tap_fsm_state_string = "IDLE "; + JtagState_IR_SELECT : jtag_tap_fsm_state_string = "IR_SELECT "; + JtagState_IR_CAPTURE : jtag_tap_fsm_state_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : jtag_tap_fsm_state_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : jtag_tap_fsm_state_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : jtag_tap_fsm_state_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : jtag_tap_fsm_state_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : jtag_tap_fsm_state_string = "IR_UPDATE "; + JtagState_DR_SELECT : jtag_tap_fsm_state_string = "DR_SELECT "; + JtagState_DR_CAPTURE : jtag_tap_fsm_state_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : jtag_tap_fsm_state_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : jtag_tap_fsm_state_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : jtag_tap_fsm_state_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : jtag_tap_fsm_state_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : jtag_tap_fsm_state_string = "DR_UPDATE "; + default : jtag_tap_fsm_state_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_1) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_1_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_1_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_1_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_1_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_1_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_1_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_1_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_1_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_1_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_1_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_1_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_1_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_1_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_1_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_1_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_1_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_1_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_2) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_2_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_2_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_2_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_2_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_2_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_2_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_2_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_2_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_2_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_2_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_2_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_2_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_2_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_2_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_2_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_2_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_2_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_3) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_3_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_3_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_3_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_3_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_3_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_3_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_3_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_3_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_3_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_3_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_3_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_3_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_3_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_3_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_3_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_3_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_3_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_4) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_4_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_4_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_4_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_4_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_4_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_4_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_4_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_4_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_4_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_4_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_4_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_4_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_4_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_4_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_4_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_4_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_4_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_5) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_5_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_5_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_5_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_5_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_5_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_5_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_5_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_5_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_5_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_5_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_5_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_5_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_5_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_5_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_5_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_5_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_5_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_6) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_6_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_6_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_6_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_6_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_6_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_6_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_6_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_6_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_6_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_6_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_6_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_6_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_6_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_6_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_6_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_6_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_6_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_7) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_7_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_7_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_7_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_7_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_7_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_7_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_7_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_7_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_7_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_7_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_7_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_7_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_7_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_7_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_7_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_7_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_7_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_8) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_8_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_8_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_8_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_8_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_8_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_8_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_8_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_8_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_8_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_8_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_8_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_8_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_8_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_8_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_8_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_8_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_8_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_9) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_9_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_9_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_9_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_9_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_9_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_9_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_9_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_9_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_9_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_9_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_9_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_9_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_9_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_9_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_9_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_9_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_9_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_10) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_10_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_10_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_10_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_10_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_10_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_10_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_10_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_10_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_10_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_10_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_10_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_10_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_10_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_10_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_10_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_10_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_10_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_11) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_11_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_11_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_11_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_11_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_11_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_11_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_11_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_11_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_11_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_11_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_11_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_11_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_11_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_11_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_11_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_11_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_11_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_12) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_12_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_12_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_12_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_12_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_12_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_12_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_12_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_12_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_12_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_12_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_12_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_12_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_12_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_12_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_12_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_12_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_12_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_13) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_13_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_13_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_13_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_13_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_13_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_13_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_13_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_13_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_13_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_13_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_13_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_13_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_13_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_13_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_13_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_13_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_13_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_14) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_14_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_14_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_14_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_14_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_14_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_14_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_14_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_14_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_14_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_14_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_14_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_14_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_14_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_14_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_14_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_14_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_14_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_15) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_15_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_15_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_15_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_15_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_15_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_15_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_15_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_15_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_15_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_15_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_15_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_15_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_15_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_15_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_15_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_15_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_15_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_16) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_16_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_16_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_16_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_16_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_16_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_16_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_16_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_16_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_16_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_16_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_16_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_16_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_16_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_16_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_16_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_16_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_16_string = "??????????"; + endcase + end + `endif + + assign system_cmd_toStream_valid = system_cmd_valid; + assign system_cmd_toStream_payload_last = system_cmd_payload_last; + assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; + assign io_remote_cmd_valid = system_cmd_toStream_valid; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; + assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); + assign io_remote_rsp_ready = 1'b1; + assign _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_RESET : JtagState_IDLE); + assign _zz_jtag_tap_fsm_stateNext_1 = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); + assign _zz_jtag_tap_fsm_stateNext_2 = (io_jtag_tms ? JtagState_RESET : JtagState_IR_CAPTURE); + assign _zz_jtag_tap_fsm_stateNext_3 = (io_jtag_tms ? JtagState_IR_EXIT1 : JtagState_IR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_4 = (io_jtag_tms ? JtagState_IR_EXIT1 : JtagState_IR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_5 = (io_jtag_tms ? JtagState_IR_UPDATE : JtagState_IR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_6 = (io_jtag_tms ? JtagState_IR_EXIT2 : JtagState_IR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_7 = (io_jtag_tms ? JtagState_IR_UPDATE : JtagState_IR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_8 = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); + assign _zz_jtag_tap_fsm_stateNext_9 = (io_jtag_tms ? JtagState_IR_SELECT : JtagState_DR_CAPTURE); + assign _zz_jtag_tap_fsm_stateNext_10 = (io_jtag_tms ? JtagState_DR_EXIT1 : JtagState_DR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_11 = (io_jtag_tms ? JtagState_DR_EXIT1 : JtagState_DR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_12 = (io_jtag_tms ? JtagState_DR_UPDATE : JtagState_DR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_13 = (io_jtag_tms ? JtagState_DR_EXIT2 : JtagState_DR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_14 = (io_jtag_tms ? JtagState_DR_UPDATE : JtagState_DR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_15 = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); + always @(*) begin + case(jtag_tap_fsm_state) + JtagState_IDLE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_1; + end + JtagState_IR_SELECT : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_2; + end + JtagState_IR_CAPTURE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_3; + end + JtagState_IR_SHIFT : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_4; + end + JtagState_IR_EXIT1 : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_5; + end + JtagState_IR_PAUSE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_6; + end + JtagState_IR_EXIT2 : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_7; + end + JtagState_IR_UPDATE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_8; + end + JtagState_DR_SELECT : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_9; + end + JtagState_DR_CAPTURE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_10; + end + JtagState_DR_SHIFT : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_11; + end + JtagState_DR_EXIT1 : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_12; + end + JtagState_DR_PAUSE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_13; + end + JtagState_DR_EXIT2 : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_14; + end + JtagState_DR_UPDATE : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext_15; + end + default : begin + _zz_jtag_tap_fsm_stateNext_16 = _zz_jtag_tap_fsm_stateNext; + end + endcase + end + + assign jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_16; + always @(*) begin + jtag_tap_tdoUnbufferd = jtag_tap_bypass; + case(jtag_tap_fsm_state) + JtagState_IR_SHIFT : begin + jtag_tap_tdoUnbufferd = jtag_tap_tdoIr; + end + JtagState_DR_SHIFT : begin + if(jtag_tap_isBypass) begin + jtag_tap_tdoUnbufferd = jtag_tap_bypass; + end else begin + jtag_tap_tdoUnbufferd = jtag_tap_tdoDr; + end + end + default : begin + end + endcase + end + + always @(*) begin + jtag_tap_tdoDr = 1'b0; + if(jtag_idcodeArea_ctrl_enable) begin + jtag_tap_tdoDr = jtag_idcodeArea_ctrl_tdo; + end + if(jtag_writeArea_ctrl_enable) begin + jtag_tap_tdoDr = jtag_writeArea_ctrl_tdo; + end + if(jtag_readArea_ctrl_enable) begin + jtag_tap_tdoDr = jtag_readArea_ctrl_tdo; + end + end + + assign jtag_tap_tdoIr = jtag_tap_instructionShift[0]; + assign jtag_tap_isBypass = ($signed(_zz_jtag_tap_isBypass) == $signed(_zz_jtag_tap_isBypass_1)); + assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext; + assign jtag_idcodeArea_ctrl_tdo = jtag_idcodeArea_shifter[0]; + assign jtag_idcodeArea_ctrl_tdi = io_jtag_tdi; + assign jtag_idcodeArea_ctrl_enable = (jtag_tap_instruction == 4'b0001); + assign jtag_idcodeArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); + assign jtag_idcodeArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); + assign jtag_idcodeArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); + assign jtag_idcodeArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); + assign when_JtagTap_l120 = (jtag_tap_fsm_state == JtagState_RESET); + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); + assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; + assign system_cmd_valid = flowCCByToggle_1_io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign jtag_writeArea_ctrl_tdo = 1'b0; + assign jtag_writeArea_ctrl_tdi = io_jtag_tdi; + assign jtag_writeArea_ctrl_enable = (jtag_tap_instruction == 4'b0010); + assign jtag_writeArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); + assign jtag_writeArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); + assign jtag_writeArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); + assign jtag_writeArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign jtag_readArea_ctrl_tdi = io_jtag_tdi; + assign jtag_readArea_ctrl_enable = (jtag_tap_instruction == 4'b0011); + assign jtag_readArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); + assign jtag_readArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); + assign jtag_readArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); + assign jtag_readArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); + always @(posedge clk) begin + if(io_remote_cmd_valid) begin + system_rsp_valid <= 1'b0; + end + if(io_remote_rsp_fire) begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @(posedge io_jtag_tck) begin + jtag_tap_fsm_state <= jtag_tap_fsm_stateNext; + jtag_tap_bypass <= io_jtag_tdi; + case(jtag_tap_fsm_state) + JtagState_IR_CAPTURE : begin + jtag_tap_instructionShift <= {2'd0, _zz_jtag_tap_instructionShift}; + end + JtagState_IR_SHIFT : begin + jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1); + end + JtagState_IR_UPDATE : begin + jtag_tap_instruction <= jtag_tap_instructionShift; + end + JtagState_DR_SHIFT : begin + jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1); + end + default : begin + end + endcase + if(jtag_idcodeArea_ctrl_enable) begin + if(jtag_idcodeArea_ctrl_shift) begin + jtag_idcodeArea_shifter <= ({jtag_idcodeArea_ctrl_tdi,jtag_idcodeArea_shifter} >>> 1); + end + end + if(jtag_idcodeArea_ctrl_capture) begin + jtag_idcodeArea_shifter <= 32'h10001fff; + end + if(when_JtagTap_l120) begin + jtag_tap_instruction <= 4'b0001; + end + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if(jtag_readArea_ctrl_enable) begin + if(jtag_readArea_ctrl_capture) begin + jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(jtag_readArea_ctrl_shift) begin + jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); + end + end + end + + always @(negedge io_jtag_tck) begin + jtag_tap_tdoUnbufferd_regNext <= jtag_tap_tdoUnbufferd; + end + + endmodule module FpuCore ( @@ -14296,6 +15612,78 @@ module StreamFifoLowLatency ( end +endmodule + +module FlowCCByToggle ( + input io_input_valid, + input io_input_payload_last, + input [0:0] io_input_payload_fragment, + output io_output_valid, + output io_output_payload_last, + output [0:0] io_output_payload_fragment, + input io_jtag_tck, + input clk, + input reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_m2sPipe_valid; + reg outputArea_flow_m2sPipe_payload_last; + reg [0:0] outputArea_flow_m2sPipe_payload_fragment; + + BufferCC inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + initial begin + `ifndef SYNTHESIS + inputArea_target = $urandom; + outputArea_hit = $urandom; + `endif + end + + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + always @(posedge io_jtag_tck) begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @(posedge clk) begin + outputArea_hit <= outputArea_target; + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end + end + + always @(posedge clk or posedge reset) begin + if(reset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + end else begin + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + endmodule module StreamArbiter_1 ( @@ -15219,3 +16607,29 @@ module StreamFork ( assign io_outputs_1_payload_value = io_input_payload_value; endmodule + +module BufferCC ( + input io_dataIn, + output io_dataOut, + input clk, + input reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + initial begin + `ifndef SYNTHESIS + buffers_0 = $urandom; + buffers_1 = $urandom; + `endif + end + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule diff --git a/clash-vexriscv/example-cpu/build.sbt b/clash-vexriscv/example-cpu/build.sbt index 9dd4bc8..0321f5f 100644 --- a/clash-vexriscv/example-cpu/build.sbt +++ b/clash-vexriscv/example-cpu/build.sbt @@ -17,7 +17,8 @@ lazy val root = (project in file(".")) libraryDependencies ++= Seq( "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion, "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion, - compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion) + compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion), + "org.yaml" % "snakeyaml" % "1.8" ) ) diff --git a/clash-vexriscv/example-cpu/src/main/scala/example/ExampleCpu.scala b/clash-vexriscv/example-cpu/src/main/scala/example/ExampleCpu.scala index 0516325..35c6ca6 100644 --- a/clash-vexriscv/example-cpu/src/main/scala/example/ExampleCpu.scala +++ b/clash-vexriscv/example-cpu/src/main/scala/example/ExampleCpu.scala @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: 2022 Google LLC +// SPDX-FileCopyrightText: 2022-2024 Google LLC // // SPDX-License-Identifier: Apache-2.0 @@ -6,6 +6,7 @@ package example import spinal.core._ import spinal.lib._ +import spinal.lib.com.jtag.Jtag import vexriscv.plugin._ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} import vexriscv.ip.{DataCacheConfig} @@ -100,7 +101,12 @@ object ExampleCpu extends App { new BranchPlugin( earlyBranch = false, catchAddressMisaligned = true - ) + ), + new DebugPlugin( + debugClockDomain = ClockDomain.current, + hardwareBreakpointCount = 5 + ), + new YamlPlugin("ExampleCpu.yaml") ) ) @@ -121,6 +127,13 @@ object ExampleCpu extends App { plugin.dBus.setAsDirectionLess() master(plugin.dBus.toWishbone()).setName("dBusWishbone") } + + case plugin: DebugPlugin => plugin.debugClockDomain { + plugin.io.bus.setAsDirectionLess() + val jtag = slave(new Jtag()).setName("jtag") + jtag <> plugin.io.bus.fromJtag() + } + case _ => } } diff --git a/clash-vexriscv/src/VexRiscv.hs b/clash-vexriscv/src/VexRiscv.hs index adf4ba7..366fa7b 100644 --- a/clash-vexriscv/src/VexRiscv.hs +++ b/clash-vexriscv/src/VexRiscv.hs @@ -7,6 +7,7 @@ {-# LANGUAGE MagicHash #-} {-# LANGUAGE TemplateHaskellQuotes #-} {-# LANGUAGE QuasiQuotes #-} +-- {-# LANGUAGE AllowAmbiguousTypes #-} {-# OPTIONS_GHC -fconstraint-solver-iterations=10 #-} @@ -25,6 +26,7 @@ import Foreign.Storable import GHC.IO (unsafePerformIO, unsafeInterleaveIO) import GHC.Stack (HasCallStack) import Language.Haskell.TH.Syntax +import Protocols import Protocols.Wishbone import VexRiscv.ClockTicks @@ -34,7 +36,20 @@ import VexRiscv.VecToTuple import qualified VexRiscv.FFI as FFI -data Input = Input +data JtagIn = JtagIn + { testClock :: "TCK" ::: Bit + , testModeSelect :: "TMS" ::: Bit + , testDataIn :: "TDI" ::: Bit + } + deriving (Generic, Eq, NFDataX, ShowX, BitPack) + +data JtagOut = JtagOut + { testDataOut :: "TDO" ::: Bit + , debugReset :: "RST" ::: Bit + } + deriving (Generic, NFDataX, ShowX, Eq, BitPack) + +data CpuIn = CpuIn { timerInterrupt :: "TIMER_INTERRUPT" ::: Bit , externalInterrupt :: "EXTERNAL_INTERRUPT" ::: Bit , softwareInterrupt :: "SOFTWARE_INTERRUPT" ::: Bit @@ -43,12 +58,20 @@ data Input = Input } deriving (Generic, NFDataX, ShowX, Eq, BitPack) -data Output = Output +data CpuOut = CpuOut { iBusWbM2S :: "IBUS_OUT_" ::: WishboneM2S 30 4 (BitVector 32) , dBusWbM2S :: "DBUS_OUT_" ::: WishboneM2S 30 4 (BitVector 32) } deriving (Generic, NFDataX, ShowX, Eq, BitPack) + +data Jtag (dom :: Domain) + +instance Protocol (Jtag dom) where + type Fwd (Jtag dom) = Signal dom JtagOut + type Bwd (Jtag dom) = Signal dom JtagIn + + -- When passing S2M values from Haskell to VexRiscv over the FFI, undefined -- bits/values cause errors when forcing their evaluation to something that can -- be passed through the FFI. @@ -62,9 +85,19 @@ defaultX dflt val | hasUndefined val = dflt | otherwise = val -vexRiscv :: (HasCallStack, HiddenClockResetEnable dom) => Signal dom Input -> Signal dom Output -vexRiscv input = - Output <$> +vexRiscv :: + forall dom . + ( HasCallStack + , KnownDomain dom) => + Clock dom -> + Reset dom -> + Signal dom CpuIn -> + Signal dom JtagIn -> + ( Signal dom CpuOut + , Signal dom JtagOut + ) +vexRiscv clk rst cpuInput jtagInput = + ( CpuOut <$> (WishboneM2S <$> iBus_ADR <*> iBus_DAT_MOSI @@ -88,10 +121,19 @@ vexRiscv input = <*> (unpack <$> dBus_CTI) <*> (unpack <$> dBus_BTE) ) + , JtagOut <$> jtag_TDO1 <*> debug_resetOut1 + ) where + + jtag_TDO1 = + jtag_TDO + + debug_resetOut1 = + debug_resetOut + (unbundle -> (timerInterrupt, externalInterrupt, softwareInterrupt, iBusS2M, dBusS2M)) - = (\(Input a b c d e) -> (a, b, c, d, e)) <$> input + = (\(CpuIn a b c d e) -> (a, b, c, d, e)) <$> cpuInput (unbundle -> (iBus_DAT_MISO, iBus_ACK, iBus_ERR)) = (\(WishboneS2M a b c _ _) -> (a, b, c)) @@ -105,11 +147,16 @@ vexRiscv input = . (if clashSimulation then makeDefined else id) <$> dBusS2M + (unbundle -> (jtag_TCK, jtag_TMS, jtag_TDI)) + = bitCoerce <$> jtagInput + sourcePath = $(do cpuSrcPath <- runIO $ getPackageRelFilePath "example-cpu/VexRiscv.v" pure $ LitE $ StringL cpuSrcPath ) + -- TODO: Remove need for 'vexRiscv#' by doing construction / deconstruction of + -- product types in HDL using BlackBoxHaskell functions. ( iBus_CYC , iBus_STB , iBus_WE @@ -126,7 +173,9 @@ vexRiscv input = , dBus_SEL , dBus_CTI , dBus_BTE - ) = vexRiscv# sourcePath hasClock hasReset + , debug_resetOut + , jtag_TDO + ) = vexRiscv# sourcePath clk rst timerInterrupt externalInterrupt softwareInterrupt @@ -139,8 +188,9 @@ vexRiscv input = dBus_ERR dBus_DAT_MISO - - + jtag_TCK + jtag_TMS + jtag_TDI vexRiscv# @@ -161,6 +211,11 @@ vexRiscv# -> Signal dom Bool -- ^ dBus_ERR -> Signal dom (BitVector 32) -- ^ dBus_DAT_MISO + -> Signal dom Bit -- ^ jtag_TCK + -> Signal dom Bit -- ^ jtag_TMS + -> Signal dom Bit -- ^ jtag_TDI + + -- output signals -> ( @@ -183,6 +238,9 @@ vexRiscv# , Signal dom (BitVector 4) -- ^ dBus_SEL , Signal dom (BitVector 3) -- ^ dBus_CTI , Signal dom (BitVector 2) -- ^ dBus_BTE + + , Signal dom Bit -- ^ debug_resetOut + , Signal dom Bit -- ^ jtag_TDO ) vexRiscv# !_sourcePath clk rst0 timerInterrupt @@ -194,7 +252,11 @@ vexRiscv# !_sourcePath clk rst0 dBus_ACK dBus_ERR - dBus_DAT_MISO = unsafePerformIO $ do + dBus_DAT_MISO + + jtag_TCK + jtag_TMS + jtag_TDI = unsafePerformIO $ do (v, initStage1, initStage2, stepRising, stepFalling, _shutDown) <- vexCPU let @@ -211,6 +273,9 @@ vexRiscv# !_sourcePath clk rst0 <*> (boolToBit <$> dBus_ACK) <*> (unpack <$> dBus_DAT_MISO) <*> (boolToBit <$> dBus_ERR) + <*> jtag_TCK + <*> jtag_TMS + <*> jtag_TDI simInitThenCycles :: Signal dom NON_COMB_INPUT -> @@ -286,12 +351,20 @@ vexRiscv# !_sourcePath clk rst0 , truncateB . pack <$> dBus_SEL , truncateB . pack <$> dBus_CTI , truncateB . pack <$> dBus_BTE + + -- JTAG + , FFI.jtag_debug_resetOut <$> output + , FFI.jtag_TDO <$> output ) {-# NOINLINE vexRiscv# #-} {-# ANN vexRiscv# ( let primName = 'vexRiscv# - ( _ + + + ( + -- ARGs + _ , srcPath , clk , rst @@ -304,9 +377,12 @@ vexRiscv# !_sourcePath clk rst0 , dBus_ACK , dBus_ERR , dBus_DAT_MISO - ) = vecToTuple (indicesI @13) + , jtag_TCK + , jtag_TMS + , jtag_TDI - ( iBus_CYC + -- GENSYMs + , iBus_CYC , iBus_STB , iBus_WE , iBus_ADR @@ -322,9 +398,11 @@ vexRiscv# !_sourcePath clk rst0 , dBus_SEL , dBus_CTI , dBus_BTE - ) = vecToTuple $ (\x -> extend @_ @16 @13 x + 1) <$> indicesI @16 + , debug_resetOut + , jtag_TDO - cpu = extend @_ @_ @1 dBus_BTE + 1 + , cpu + ) = vecToTuple $ indicesI @35 in InlineYamlPrimitive [Verilog] [__i| BlackBox: @@ -353,6 +431,9 @@ vexRiscv# !_sourcePath clk rst0 wire [2:0] ~GENSYM[dBus_CTI][#{dBus_CTI}]; wire [1:0] ~GENSYM[dBus_BTE][#{dBus_BTE}]; + wire ~GENSYM[debug_resetOut][#{debug_resetOut}]; + wire ~GENSYM[jtag_TDO][#{jtag_TDO}]; + VexRiscv ~GENSYM[cpu][#{cpu}] ( .timerInterrupt ( ~ARG[#{timerInterrupt}] ), .externalInterrupt ( ~ARG[#{externalInterrupt}] ), @@ -382,6 +463,13 @@ vexRiscv# !_sourcePath clk rst0 .dBusWishbone_CTI ( ~SYM[#{dBus_CTI}] ), .dBusWishbone_BTE ( ~SYM[#{dBus_BTE}] ), + .jtag_tms ( ~ARG[#{jtag_TMS}]), + .jtag_tdi ( ~ARG[#{jtag_TDI}]), + .jtag_tck ( ~ARG[#{jtag_TCK}]), + .jtag_tdo ( ~SYM[#{jtag_TDO}] ), + + .debug_resetOut ( ~SYM[#{debug_resetOut}] ), + .clk ( ~ARG[#{clk}] ), .reset ( ~ARG[#{rst}] ) ); @@ -402,7 +490,9 @@ vexRiscv# !_sourcePath clk rst0 ~SYM[#{dBus_DAT_MOSI}], ~SYM[#{dBus_SEL}], ~SYM[#{dBus_CTI}], - ~SYM[#{dBus_BTE}] + ~SYM[#{dBus_BTE}], + ~SYM[#{debug_resetOut}], + ~SYM[#{jtag_TDO}] }; // vexRiscv end diff --git a/clash-vexriscv/src/VexRiscv/FFI.hsc b/clash-vexriscv/src/VexRiscv/FFI.hsc index 9fd456c..572cad8 100644 --- a/clash-vexriscv/src/VexRiscv/FFI.hsc +++ b/clash-vexriscv/src/VexRiscv/FFI.hsc @@ -18,6 +18,8 @@ import Data.Word data VexRiscv +data VexRiscvJtagBridge + foreign import ccall unsafe "vexr_init" vexrInit :: IO (Ptr VexRiscv) foreign import ccall unsafe "vexr_shutdown" vexrShutdown :: Ptr VexRiscv -> IO () @@ -26,6 +28,10 @@ foreign import ccall unsafe "vexr_init_stage2" vexrInitStage2 :: Ptr VexRiscv -> foreign import ccall unsafe "vexr_step_rising_edge" vexrStepRisingEdge :: Ptr VexRiscv -> Word64 -> Ptr NON_COMB_INPUT -> Ptr OUTPUT -> IO () foreign import ccall unsafe "vexr_step_falling_edge" vexrStepFallingEdge :: Ptr VexRiscv -> Word64 -> Ptr COMB_INPUT -> IO () +foreign import ccall unsafe "vexr_jtag_bridge_init" vexrJtagBridgeInit :: Word16 -> IO (Ptr VexRiscvJtagBridge) +foreign import ccall unsafe "vexr_jtag_bridge_step" vexrJtagBridgeStep :: Ptr VexRiscvJtagBridge -> Ptr JTAG_OUTPUT -> Ptr JTAG_INPUT -> IO () +foreign import ccall unsafe "vexr_jtag_bridge_shutdown" vexrJtagBridgeShutdown :: Ptr VexRiscvJtagBridge -> IO () + -- | CPU input that cannot combinatorially depend on the CPU output data NON_COMB_INPUT = NON_COMB_INPUT { reset :: Bit @@ -43,6 +49,10 @@ data COMB_INPUT = COMB_INPUT , dBusWishbone_ACK :: Bit , dBusWishbone_DAT_MISO :: Word32 , dBusWishbone_ERR :: Bit + + , jtag_TCK :: Bit + , jtag_TMS :: Bit + , jtag_TDI :: Bit } deriving (Show) @@ -64,6 +74,22 @@ data OUTPUT = OUTPUT , dBusWishbone_SEL :: Word8 , dBusWishbone_CTI :: Word8 , dBusWishbone_BTE :: Word8 + + , jtag_debug_resetOut :: Bit + , jtag_TDO :: Bit + } + deriving (Show) + +data JTAG_INPUT = JTAG_INPUT + { tck :: Bit + , tms :: Bit + , tdi :: Bit + } + deriving (Show) + +data JTAG_OUTPUT = JTAG_OUTPUT + { debug_resetOut :: Bit + , tdo :: Bit } deriving (Show) @@ -102,6 +128,9 @@ instance Storable COMB_INPUT where <*> (#peek COMB_INPUT, dBusWishbone_ACK) ptr <*> (#peek COMB_INPUT, dBusWishbone_DAT_MISO) ptr <*> (#peek COMB_INPUT, dBusWishbone_ERR) ptr + <*> (#peek COMB_INPUT, jtag_TCK) ptr + <*> (#peek COMB_INPUT, jtag_TMS) ptr + <*> (#peek COMB_INPUT, jtag_TDI) ptr {-# INLINE poke #-} poke ptr this = do @@ -112,6 +141,10 @@ instance Storable COMB_INPUT where (#poke COMB_INPUT, dBusWishbone_ACK) ptr (dBusWishbone_ACK this) (#poke COMB_INPUT, dBusWishbone_DAT_MISO) ptr (dBusWishbone_DAT_MISO this) (#poke COMB_INPUT, dBusWishbone_ERR) ptr (dBusWishbone_ERR this) + + (#poke COMB_INPUT, jtag_TCK) ptr (jtag_TCK this) + (#poke COMB_INPUT, jtag_TMS) ptr (jtag_TMS this) + (#poke COMB_INPUT, jtag_TDI) ptr (jtag_TDI this) return () instance Storable OUTPUT where @@ -137,6 +170,9 @@ instance Storable OUTPUT where <*> (#peek OUTPUT, dBusWishbone_CTI) ptr <*> (#peek OUTPUT, dBusWishbone_BTE) ptr + <*> (#peek OUTPUT, jtag_debug_resetOut) ptr + <*> (#peek OUTPUT, jtag_TDO) ptr + {-# INLINE poke #-} poke ptr this = do (#poke OUTPUT, iBusWishbone_CYC) ptr (iBusWishbone_CYC this) @@ -156,4 +192,36 @@ instance Storable OUTPUT where (#poke OUTPUT, dBusWishbone_SEL) ptr (dBusWishbone_SEL this) (#poke OUTPUT, dBusWishbone_CTI) ptr (dBusWishbone_CTI this) (#poke OUTPUT, dBusWishbone_BTE) ptr (dBusWishbone_BTE this) + + (#poke OUTPUT, jtag_debug_resetOut) ptr (jtag_debug_resetOut this) + (#poke OUTPUT, jtag_TDO) ptr (jtag_TDO this) + return () + +instance Storable JTAG_OUTPUT where + alignment _ = #alignment JTAG_OUTPUT + sizeOf _ = #size JTAG_OUTPUT + {-# INLINE peek #-} + peek ptr = const JTAG_OUTPUT <$> pure () + <*> (#peek JTAG_OUTPUT, debug_resetOut) ptr + <*> (#peek JTAG_OUTPUT, tdo) ptr + + {-# INLINE poke #-} + poke ptr this = do + (#poke JTAG_OUTPUT, debug_resetOut) ptr (debug_resetOut this) + (#poke JTAG_OUTPUT, tdo) ptr (tdo this) + +instance Storable JTAG_INPUT where + alignment _ = #alignment JTAG_INPUT + sizeOf _ = #size JTAG_INPUT + {-# INLINE peek #-} + peek ptr = const JTAG_INPUT <$> pure () + <*> (#peek JTAG_INPUT, tck) ptr + <*> (#peek JTAG_INPUT, tms) ptr + <*> (#peek JTAG_INPUT, tdi) ptr + + {-# INLINE poke #-} + poke ptr this = do + (#poke JTAG_INPUT, tck) ptr (tck this) + (#poke JTAG_INPUT, tms) ptr (tms this) + (#poke JTAG_INPUT, tdi) ptr (tdi this) return () diff --git a/clash-vexriscv/src/VexRiscv/JtagTcpBridge.hs b/clash-vexriscv/src/VexRiscv/JtagTcpBridge.hs new file mode 100644 index 0000000..eb0f011 --- /dev/null +++ b/clash-vexriscv/src/VexRiscv/JtagTcpBridge.hs @@ -0,0 +1,50 @@ +-- SPDX-FileCopyrightText: 2023 Google LLC +-- +-- SPDX-License-Identifier: Apache-2.0 + +{-# LANGUAGE RecordWildCards #-} +module VexRiscv.JtagTcpBridge (vexrJtagBridge, defaultIn) where + +import Clash.Prelude + +import Clash.Signal.Internal + +import VexRiscv +import VexRiscv.FFI + +import Foreign +import System.IO.Unsafe (unsafePerformIO) +import Network.Socket (PortNumber) + +defaultIn :: JtagIn +defaultIn = JtagIn { testClock = low, testModeSelect = low, testDataIn = low } + +{-# NOINLINE inner #-} +inner :: (t -> IO JtagIn) -> Signal dom t -> Signal dom JtagIn +inner jtagBridgeStep (o :- outs) = unsafePerformIO $ do + in' <- jtagBridgeStep o + let ins' = inner jtagBridgeStep outs + pure $ in' :- (in' `deepseqX` ins') + +vexrJtagBridge :: PortNumber -> Signal dom JtagOut -> Signal dom JtagIn +vexrJtagBridge port out = inner jtagBridgeStep out + where + (_, jtagBridgeStep) = unsafePerformIO $ vexrJtagBridge' port + +vexrJtagBridge' :: + PortNumber -> + IO ( IO () -- ^ delete function + , JtagOut -> IO JtagIn -- ^ step function + ) +vexrJtagBridge' port = do + bridge <- vexrJtagBridgeInit (fromIntegral port) + let + shutDown = vexrJtagBridgeShutdown bridge + + step JtagOut{..} = alloca $ \outFFI -> alloca $ \inFFI -> do + poke outFFI (JTAG_OUTPUT debugReset testDataOut) + vexrJtagBridgeStep bridge outFFI inFFI + JTAG_INPUT{..} <- peek inFFI + let input = JtagIn { testClock = tck, testModeSelect = tms, testDataIn = tdi } + pure input + pure (shutDown, step) diff --git a/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs b/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs new file mode 100644 index 0000000..3c6092d --- /dev/null +++ b/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs @@ -0,0 +1,186 @@ +-- SPDX-FileCopyrightText: 2023 Google LLC +-- +-- SPDX-License-Identifier: Apache-2.0 + +module VexRiscv.JtagTcpBridge where + +import Clash.Prelude + +import Clash.Signal.Internal +import Network.Socket +import Protocols +import Protocols.Internal (CSignal(..), Reverse) +import VexRiscv (JtagIn(..), JtagOut(..), Jtag) +import Control.Concurrent (MVar, forkIO, newEmptyMVar, putMVar, takeMVar, tryTakeMVar) +import Control.Monad (when) +import Network.Socket.ByteString (sendAll, recv) + +import qualified Data.ByteString as BS +import System.IO.Unsafe (unsafePerformIO) +import Debug.Trace (trace) + +data NetworkThreadToMainMsg + = Connected + | Disconnected + | DataReceived [BitVector 8] + +data MainToNetworkThreadMsg + = ReadMore + | Send (BitVector 8) + +data NetworkThreadState + = NoClient + | PerformRead Socket + | WaitForNextRead Socket + deriving (Show) + +data MainThreadState + = MDisconnected + | MWaitForRead + | MProcessing (BitVector 2) [BitVector 8] + deriving (Show) + +jtagTcpBridge :: + (HiddenClockResetEnable dom) => + PortNumber -> + Circuit + (Jtag dom, Reverse (CSignal dom Bool)) + () +jtagTcpBridge port = + Circuit $ \((jtagOut, _), ()) -> unsafePerformIO $ do + (enable, jtagIn) <- jtagTcpBridge' port jtagOut + pure ((jtagIn, CSignal $ fromEnable enable), ()) + +jtagTcpBridge' :: + (KnownDomain dom) => + PortNumber -> + Signal dom JtagOut -> + IO (Enable dom, Signal dom JtagIn) +jtagTcpBridge' port jtagOut = do + + (n2m, m2n) <- server port + + (unbundle -> (enable, jtagIn)) <- client n2m m2n MDisconnected jtagOut + + pure (toEnable enable, jtagIn) + +{-# NOINLINE jtagTcpBridge' #-} + +server :: PortNumber -> IO (MVar NetworkThreadToMainMsg, MVar MainToNetworkThreadMsg) +server port = withSocketsDo $ do + sock <- setup + + threadToMainChan <- newEmptyMVar + mainToThreadChan <- newEmptyMVar + + let + thread NoClient = do + (clientSock, _) <- accept sock + putMVar threadToMainChan Connected + thread (PerformRead clientSock) + thread (PerformRead clientSock) = do + buf <- recv clientSock 100 + if BS.null buf then do + putMVar threadToMainChan Disconnected + thread NoClient + else do + let dat = pack <$> BS.unpack buf + putMVar threadToMainChan (DataReceived dat) + thread (WaitForNextRead clientSock) + + thread (WaitForNextRead clientSock) = do + msg <- takeMVar mainToThreadChan + case msg of + ReadMore -> thread (PerformRead clientSock) + Send byte -> do + sendAll clientSock (BS.singleton $ unpack byte) + thread (WaitForNextRead clientSock) + + _ <- forkIO $ thread NoClient + + pure (threadToMainChan, mainToThreadChan) + + where + setup = do + sock <- socket AF_INET Stream 0 + + setSocketOption sock NoDelay 0 + + bind sock (SockAddrInet port (tupleToHostAddress (127, 0, 0, 1))) + + listen sock 1 + + pure sock + +defaultIn :: JtagIn +defaultIn = JtagIn { testModeSelect = low, testDataIn = low } + +dbg :: Show a => a -> a +dbg x = + trace (show x) + x + +clientSleep :: BitVector 2 +clientSleep = 4 + +client :: + (KnownDomain dom) => + MVar NetworkThreadToMainMsg -> + MVar MainToNetworkThreadMsg -> + MainThreadState -> + Signal dom JtagOut -> + IO (Signal dom (Bool, JtagIn)) +client n2m m2n MDisconnected (_out :- outs) = do + msg <- tryTakeMVar n2m + case msg of + Nothing -> + pure $ _out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MDisconnected outs) + Just Connected -> do + pure $ _out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MWaitForRead outs) + Just Disconnected -> do + errorX "????" + Just (DataReceived _xs) -> do + errorX "????" + +client n2m m2n MWaitForRead (out :- outs) = do + msg <- tryTakeMVar n2m + case msg of + Nothing -> + pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MWaitForRead outs) + Just Disconnected -> + pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MDisconnected outs) + Just (DataReceived xs) -> + client n2m m2n (MProcessing 0 xs) (out :- outs) + Just Connected -> + errorX "????" + +client n2m m2n (MProcessing _ []) (out :- outs) = do + putMVar m2n ReadMore + pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MWaitForRead outs) +client n2m m2n (MProcessing 0 (x:xs)) (out :- outs) = do + let tms = x ! (0 :: Int) + tdi = x ! (1 :: Int) + tck = x ! (3 :: Int) + + sendTdo = bitToBool $ x ! (2 :: Int) + + enable = bitToBool tck + + when sendTdo $ do + let tdo = bitToBool $ testDataOut out + -- putStrLn $ "send TDO " <> show tdo + putMVar m2n $ Send $ boolToBV tdo + + let inDat = JtagIn { testModeSelect = tms, testDataIn = tdi } + + when enable $ do + -- putStrLn "Enable" + -- putStrLn $ "IN " <> showX inDat + pure () + + pure $ (enable, inDat) :- unsafePerformIO (client n2m m2n (MProcessing clientSleep xs) outs) +client n2m m2n (MProcessing n xs) (out :- outs) = do + pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n (MProcessing (n - 1) xs) outs) + + +{-# NOINLINE client #-} diff --git a/clash-vexriscv/src/ffi/impl.cpp b/clash-vexriscv/src/ffi/impl.cpp index 230e2c6..e305f3c 100644 --- a/clash-vexriscv/src/ffi/impl.cpp +++ b/clash-vexriscv/src/ffi/impl.cpp @@ -6,6 +6,31 @@ #include "verilated.h" #include "interface.h" +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + int server_socket, client_handle; + struct sockaddr_in server_addr; + struct sockaddr_storage server_storage; + + uint32_t timer; + socklen_t addr_size; + uint32_t self_sleep; + uint32_t check_new_connections_timer; + uint8_t rx_buffer[100]; + int32_t rx_buffer_size; + int32_t rx_buffer_remaining; + JTAG_INPUT prev_input; + + uint64_t tck_change_counter; +} vexr_jtag_bridge_data; + extern "C" { VVexRiscv* vexr_init(); void vexr_shutdown(VVexRiscv *top); @@ -14,9 +39,15 @@ extern "C" { void vexr_init_stage2(VVexRiscv *top, const COMB_INPUT *input); void vexr_step_rising_edge(VVexRiscv *top, uint64_t time_add, const NON_COMB_INPUT *input, OUTPUT *output); void vexr_step_falling_edge(VVexRiscv *top, uint64_t time_add, const COMB_INPUT *input); + + vexr_jtag_bridge_data *vexr_jtag_bridge_init(uint16_t port); + void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output, JTAG_INPUT *input); + void vexr_jtag_bridge_shutdown(vexr_jtag_bridge_data *bridge_data); } static VerilatedContext* contextp = 0; +static bool set_socket_blocking_enabled(int fd, bool blocking); +static void connection_reset(vexr_jtag_bridge_data *bridge_data); VVexRiscv* vexr_init() { @@ -47,6 +78,10 @@ void set_comb_inputs(VVexRiscv *top, const COMB_INPUT *input) top->dBusWishbone_ACK = input->dBusWishbone_ACK; top->dBusWishbone_DAT_MISO = input->dBusWishbone_DAT_MISO; top->dBusWishbone_ERR = input->dBusWishbone_ERR; + + top->jtag_tck = input->jtag_TCK; + top->jtag_tms = input->jtag_TMS; + top->jtag_tdi = input->jtag_TDI; } // Set all outputs @@ -68,6 +103,9 @@ void set_ouputs(VVexRiscv *top, OUTPUT *output) output->dBusWishbone_SEL = top->dBusWishbone_SEL; output->dBusWishbone_CTI = top->dBusWishbone_CTI; output->dBusWishbone_BTE = top->dBusWishbone_BTE; + + output->jtag_debug_resetOut = top->debug_resetOut; + output->jtag_TDO = top->jtag_tdo; } void vexr_init_stage1(VVexRiscv *top, const NON_COMB_INPUT *input, OUTPUT *output) @@ -127,3 +165,172 @@ void vexr_step_falling_edge(VVexRiscv *top, uint64_t time_add, const COMB_INPUT // Evaluate the simulation top->eval(); } + +vexr_jtag_bridge_data *vexr_jtag_bridge_init(uint16_t port) +{ + vexr_jtag_bridge_data *d = new vexr_jtag_bridge_data; + + d->prev_input = { 0, 0, 0 }; + + d->tck_change_counter = 0; + + d->timer = 0; + d->self_sleep = 0; + d->check_new_connections_timer = 0; + d->rx_buffer_size = 0; + d->rx_buffer_remaining = 0; + + d->server_socket = socket(PF_INET, SOCK_STREAM, 0); + assert(d->server_socket != -1); + int flag = 1; + setsockopt( + d->server_socket, /* socket affected */ + IPPROTO_TCP, /* set option at TCP level */ + TCP_NODELAY, /* name of option */ + (char *) &flag, /* the cast is historical cruft */ + sizeof(int) /* length of option value */ + ); + + set_socket_blocking_enabled(d->server_socket, 0); + + d->server_addr.sin_family = AF_INET; + d->server_addr.sin_port = htons(port); + d->server_addr.sin_addr.s_addr = inet_addr("127.0.0.1"); + memset(d->server_addr.sin_zero, '\0', sizeof(d->server_addr.sin_zero)); + + bind( + d->server_socket, + (struct sockaddr *) &d->server_addr, + sizeof(d->server_addr) + ); + + listen(d->server_socket, 1); + + d->client_handle = -1; + d->addr_size = sizeof(d->server_storage); + + return d; +} + +void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output, JTAG_INPUT *input) +{ + const int WAIT_PERIOD = 83333; + // We set the input values to their last here + // so that only the "successful" path has to update them + + *input = d->prev_input; + + if(d->timer != 0) { + d->timer -= 1; + return; + } + d->check_new_connections_timer++; + if (d->check_new_connections_timer == 200) { + d->check_new_connections_timer = 0; + int new_client_handle = accept( + d->server_socket, + (struct sockaddr *) &d->server_storage, + &d->addr_size + ); + if (new_client_handle != -1) { + if(d->client_handle != -1){ + connection_reset(d); + } + d->client_handle = new_client_handle; + printf("\n[JTAG BRIDGE] got new connection\n"); + } else { + if(d->client_handle == -1) + d->self_sleep = 200; + } + } + if (d->self_sleep) { + d->self_sleep--; + } else if (d->client_handle != -1) { + int n; + + if (d->rx_buffer_remaining == 0) { + if (ioctl(d->client_handle, FIONREAD, &n) != 0) { + connection_reset(d); + } else if (n >= 1) { + d->rx_buffer_size = read( + d->client_handle, + &d->rx_buffer, + 100 + ); + if (d->rx_buffer_size < 0) { + connection_reset(d); + } else { + d->rx_buffer_remaining = d->rx_buffer_size; + } + } else { + d->self_sleep = 30; + } + } + + if (d->rx_buffer_remaining != 0){ + uint8_t buffer = d->rx_buffer[d->rx_buffer_size - (d->rx_buffer_remaining--)]; + input->tms = (buffer & 1) != 0; + input->tdi = (buffer & 2) != 0; + input->tck = (buffer & 8) != 0; + + // printf("\n[JTAG_BRIDGE] "); + // printf("%d %d %d %d\n", + // d->tck_change_counter, + // input->jtag_TCK, + // input->jtag_TMS, + // input->jtag_TDI + // ); + + if (input->tck != d->prev_input.tck) { + d->tck_change_counter++; + } + + + + d->prev_input = *input; + if(buffer & 4){ + buffer = (output->tdo != 0); + // printf("\n[JTAG_BRIDGE] [TDO] %d\n", buffer); + if (-1 == send(d->client_handle, &buffer, 1, 0)) { + connection_reset(d); + } + } + } + } + d->timer = 27; // 3; value used by VexRiscv regression test +} + +void vexr_jtag_bridge_shutdown(vexr_jtag_bridge_data *bridge_data) +{ + if (bridge_data->client_handle != -1) { + shutdown(bridge_data->client_handle, SHUT_RDWR); + usleep(100); + } + if (bridge_data->server_socket != -1) { + close(bridge_data->server_socket); + usleep(100); + } +} + + +/** Returns true on success, or false if there was an error */ +static bool set_socket_blocking_enabled(int fd, bool blocking) +{ + if (fd < 0) return false; + +#ifdef WIN32 + unsigned long mode = blocking ? 0 : 1; + return (ioctlsocket(fd, FIONBIO, &mode) == 0) ? true : false; +#else + int flags = fcntl(fd, F_GETFL, 0); + if (flags < 0) return false; + flags = blocking ? (flags&~O_NONBLOCK) : (flags|O_NONBLOCK); + return (fcntl(fd, F_SETFL, flags) == 0) ? true : false; +#endif +} + +static void connection_reset(vexr_jtag_bridge_data *bridge_data) { + printf("[JTAG BRIDGE] closed connection\n"); + shutdown(bridge_data->client_handle, SHUT_RDWR); + bridge_data->client_handle = -1; +} diff --git a/clash-vexriscv/src/ffi/interface.h b/clash-vexriscv/src/ffi/interface.h index e82759a..5cd543e 100644 --- a/clash-vexriscv/src/ffi/interface.h +++ b/clash-vexriscv/src/ffi/interface.h @@ -24,6 +24,10 @@ typedef struct { bit dBusWishbone_ACK; uint32_t dBusWishbone_DAT_MISO; bit dBusWishbone_ERR; + + bit jtag_TCK; + bit jtag_TMS; + bit jtag_TDI; } COMB_INPUT; typedef struct { @@ -44,6 +48,20 @@ typedef struct { uint8_t dBusWishbone_SEL; uint8_t dBusWishbone_CTI; uint8_t dBusWishbone_BTE; + + bit jtag_debug_resetOut; + bit jtag_TDO; } OUTPUT; +typedef struct { + bit tck; + bit tms; + bit tdi; +} JTAG_INPUT; + +typedef struct { + bit debug_resetOut; + bit tdo; +} JTAG_OUTPUT; + #endif diff --git a/debug-test/Cargo.toml b/debug-test/Cargo.toml new file mode 100644 index 0000000..65c1785 --- /dev/null +++ b/debug-test/Cargo.toml @@ -0,0 +1,18 @@ +# SPDX-FileCopyrightText: 2022 Google LLC +# +# SPDX-License-Identifier: CC0-1.0 + +[package] +name = "debug-test" +version = "0.1.0" +edition = "2021" +license = "Apache-2.0" +authors = ["Google LLC"] + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +riscv-rt = "0.11.0" +riscv = "^0.10" +heapless = { version = "0.7", default-features = false } +panic-halt = "0.2.0" diff --git a/debug-test/build.rs b/debug-test/build.rs new file mode 100644 index 0000000..0d6ad00 --- /dev/null +++ b/debug-test/build.rs @@ -0,0 +1,23 @@ +// SPDX-FileCopyrightText: 2022 Google LLC +// +// SPDX-License-Identifier: Apache-2.0 + +use std::env; +use std::fs; +use std::path::Path; + +/// Put the linker script somewhere the linker can find it. +fn main() { + let out_dir = env::var("OUT_DIR").expect("No out dir"); + let dest_path = Path::new(&out_dir).join("memory.x"); + fs::write(dest_path, include_bytes!("memory.x")).expect("Could not write file"); + + if env::var("CARGO_CFG_TARGET_ARCH").unwrap() == "riscv32" { + println!("cargo:rustc-link-arg=-Tmemory.x"); + println!("cargo:rustc-link-arg=-Tlink.x"); // linker script from riscv-rt + } + println!("cargo:rustc-link-search={out_dir}"); + + println!("cargo:rerun-if-changed=memory.x"); + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/debug-test/memory.x b/debug-test/memory.x new file mode 100644 index 0000000..211d12c --- /dev/null +++ b/debug-test/memory.x @@ -0,0 +1,18 @@ +/* +SPDX-FileCopyrightText: 2022 Google LLC + +SPDX-License-Identifier: CC0-1.0 +*/ + +MEMORY +{ + DATA : ORIGIN = 0x40000000, LENGTH = 512K + INSTR : ORIGIN = 0x20000000, LENGTH = 512K +} + +REGION_ALIAS("REGION_TEXT", INSTR); +REGION_ALIAS("REGION_RODATA", DATA); +REGION_ALIAS("REGION_DATA", DATA); +REGION_ALIAS("REGION_BSS", DATA); +REGION_ALIAS("REGION_HEAP", DATA); +REGION_ALIAS("REGION_STACK", DATA); diff --git a/debug-test/src/bin/print_a.rs b/debug-test/src/bin/print_a.rs new file mode 100644 index 0000000..1d8a7b5 --- /dev/null +++ b/debug-test/src/bin/print_a.rs @@ -0,0 +1,32 @@ +// SPDX-FileCopyrightText: 2022 Google LLC +// +// SPDX-License-Identifier: Apache-2.0 + +#![no_std] +#![cfg_attr(not(test), no_main)] + +#[cfg(not(test))] +use riscv_rt::entry; + +#[cfg(not(test))] +extern crate panic_halt; + +const ADDR: *mut u8 = 0x0000_1000 as *mut u8; + +fn print(s: &str) { + for b in s.bytes() { + unsafe { + ADDR.write_volatile(b); + } + } +} + +fn done() -> ! { + loop {}; +} + +#[cfg_attr(not(test), entry)] +fn main() -> ! { + print("[CPU] a\n"); + done(); +} diff --git a/debug-test/src/bin/print_b.rs b/debug-test/src/bin/print_b.rs new file mode 100644 index 0000000..1e5bde1 --- /dev/null +++ b/debug-test/src/bin/print_b.rs @@ -0,0 +1,32 @@ +// SPDX-FileCopyrightText: 2022 Google LLC +// +// SPDX-License-Identifier: Apache-2.0 + +#![no_std] +#![cfg_attr(not(test), no_main)] + +#[cfg(not(test))] +use riscv_rt::entry; + +#[cfg(not(test))] +extern crate panic_halt; + +const ADDR: *mut u8 = 0x0000_1000 as *mut u8; + +fn print(s: &str) { + for b in s.bytes() { + unsafe { + ADDR.write_volatile(b); + } + } +} + +fn done() -> ! { + loop {}; +} + +#[cfg_attr(not(test), entry)] +fn main() -> ! { + print("[CPU] b\n"); + done(); +} diff --git a/debug-test/src/main.rs b/debug-test/src/main.rs new file mode 100644 index 0000000..de1d685 --- /dev/null +++ b/debug-test/src/main.rs @@ -0,0 +1,106 @@ +// SPDX-FileCopyrightText: 2022 Google LLC +// +// SPDX-License-Identifier: Apache-2.0 + +#![no_std] +#![cfg_attr(not(test), no_main)] + +use core::fmt::Write; + +use heapless::String; +#[cfg(not(test))] +use riscv_rt::entry; + +#[cfg(not(test))] +extern crate panic_halt; + +const ADDR: *mut u8 = 0x0000_1000 as *mut u8; + +fn print(s: &str) { + for b in s.bytes() { + unsafe { + ADDR.write_volatile(b); + } + } +} + +#[cfg_attr(not(test), entry)] +fn main() -> ! { + print("hello, world.\n"); + + print("I am here to be debugged!\n"); + + loop { + for i in 0..30 { + let mut s = String::<16>::new(); + let _ = writeln!(s, "Hey! {i}"); + print(&s); + } + + print("wheeeey!\n"); + + // unsafe { + // riscv::asm::ebreak(); + // } + } +} + +#[export_name = "UserSoft"] +fn user_soft_handler() { + loop { + print("INTERRUPT UserSoft"); + } +} + +#[export_name = "MachineSoft"] +fn machine_soft_handler() { + loop { + print("INTERRUPT MachineSoft"); + } +} + +#[export_name = "UserTimer"] +fn user_timer_handler() { + loop { + print("INTERRUPT UserTimer"); + } +} + +#[export_name = "MachineTimer"] +fn machine_timer_handler() { + loop { + print("INTERRUPT MachineTimer"); + } +} + +#[export_name = "UserExternal"] +fn user_ext_handler() { + loop { + print("INTERRUPT UserExternal"); + } +} + +#[export_name = "MachineExternal"] +fn machine_ext_handler() { + loop { + print("INTERRUPT MachineExternal"); + } +} + +#[export_name = "DefaultHandler"] +fn default_handler() { + loop { + print("INTERRUPT default handler"); + } +} + +#[export_name = "ExceptionHandler"] +fn exception_handler(_trap_frame: &riscv_rt::TrapFrame) -> ! { + riscv::interrupt::free(|| { + print("... caught an exception. Looping forever now.\n"); + }); + loop { + // print(""); + continue; + } +} diff --git a/rust-toolchain.toml b/rust-toolchain.toml index feb678b..22968aa 100644 --- a/rust-toolchain.toml +++ b/rust-toolchain.toml @@ -1,5 +1,5 @@ # SPDX-FileCopyrightText: 2022-2023 Google LLC -# +# # SPDX-License-Identifier: CC0-1.0 [toolchain] diff --git a/shell.nix b/shell.nix index 22dfb2d..714afdd 100644 --- a/shell.nix +++ b/shell.nix @@ -24,6 +24,7 @@ pkgs.mkShell { # VexRiscV needs a special openocd pkgs.openocd-vexriscv + pkgs.gdb # For Cabal to clone git repos pkgs.git diff --git a/vexriscv_gdb.cfg b/vexriscv_gdb.cfg new file mode 100644 index 0000000..f6af1a4 --- /dev/null +++ b/vexriscv_gdb.cfg @@ -0,0 +1,45 @@ +# Execute using: +# +# gdb --command=vexriscv_gdb.cfg +# + +# SPDX-FileCopyrightText: 2024 Google LLC +# +# SPDX-License-Identifier: CC0-1.0 + +# Assume "print_a" is running on the CPU +file "target/riscv32imc-unknown-none-elf/debug/print_a" + +# Work around issues where simulation is too slow to respond to keep-alive messages, +# confusing either OpenOCD or GDB. Note that it will still complain about "missed" +# deadlines, but it won't fail.. +set remotetimeout unlimited + +# Connect to OpenOCD +target extended-remote :3333 + +# List registers +i r + +# break on main function entrance +break main + +# Jump to start address, should run until it hits main +jump _start + +# Run until we hit function "done", meaning it should have printed "a" +disable 1 +break print_a::done +continue +disable 2 + +# Load program +file "target/riscv32imc-unknown-none-elf/debug/print_b" +load + +# Jump to start address. Should now output "b". +break print_b::done +jump _start + +# Stop running GDB +quit diff --git a/vexriscv_sim.cfg b/vexriscv_sim.cfg new file mode 100644 index 0000000..5b185bd --- /dev/null +++ b/vexriscv_sim.cfg @@ -0,0 +1,70 @@ +# Execute using: +# +# openocd-vexriscv -f vexriscv_sim.cfg +# + +# SPDX-FileCopyrightText: 2024 Google LLC +# +# SPDX-License-Identifier: CC0-1.0 + +adapter driver jtag_tcp +adapter speed 64000 +transport select jtag + + +set _ENDIAN little +set _TAP_TYPE 1234 + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # set useful default + set _CPUTAPID 0x10001fff +} + +set _CHIPNAME vexrisc_ocd + +# The JTAG TAP itself is given the name "bridge", because it refers to the +# JtagBridge that's part of the VexRiscv/SpinalHDL debug infrastructure. +# In the example design, there is the JtagBridge controls a single CPU, but +# the capability is there for 1 JTAG TAP + JtagBridge to control multiple +# VexRiscv CPUs. +jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF + +# There is 1 CPU controlled by the "bridge" JTAG TAP, "cpu0" +target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge + +# The JtagBridge/SystemDebugger receives commands in a serialized way. It gets synchronized into +# a parallel bus, and a response is received. Along the way, there may be various clock domain +# crossings or pipeline delays. +# readWaitCycles instructs OpenOCD to insert idle JTAG clock cycles before shifting out +# the response. +# There aren't many transactions where read-back throughput is important, so there's little +# points in lowballing this number. +vexriscv readWaitCycles 10 + +# When the Verilog of a SpinalHDL design with one or more VexRiscv CPUs is created, the system +# also creates a .yaml file with information that's sideband information that's important for +# OpenOCD to control the CPU correctly. +# A good example of this are the number of hardware breakpoints that are supported by the CPU. +vexriscv cpuConfigFile clash-vexriscv/example-cpu/ExampleCpu.yaml + +# The rate at which OpenOCD polls active JTAG TAPs to check if there has been a notable +# event. (E.g. to check if the CPU has hit a breakpoint.) +# For some reason, making this number really low has an impact on the CPU while semihosting is +# enabled? +poll_period 50 + +# Initialize all JTAG TAPs and targets. +init + +echo "Halting processor" + +# Halts the CPU and issue a soft reset. +# The DebugPlugin has a resetOut signal that can be used reset external logic. It is not +# used to reset anything inside the VexRiscv itself though. In our small example, +# resetOut is not connected to anything, so we could have used "halt" instead. +# soft_reset_halt +halt + +sleep 1000 From b0b173f6b39458257ee91007999787b5c58ada2c Mon Sep 17 00:00:00 2001 From: Lara Herzog Date: Wed, 6 Mar 2024 11:19:59 +0100 Subject: [PATCH 2/9] Add dual-port storage, von Neumann architecture Co-authored-by: Martijn Bastiaan --- clash-vexriscv-sim/app/VexRiscvSimulation.hs | 19 +++--- clash-vexriscv-sim/src/Utils/Cpu.hs | 56 +++++++++++------- clash-vexriscv-sim/src/Utils/ProgramLoad.hs | 42 +++++++++++++ clash-vexriscv-sim/src/Utils/Storage.hs | 62 +++++++++++++++++++- clash-vexriscv-sim/tests/tests.hs | 5 +- clash-vexriscv/src/ffi/impl.cpp | 2 +- 6 files changed, 148 insertions(+), 38 deletions(-) diff --git a/clash-vexriscv-sim/app/VexRiscvSimulation.hs b/clash-vexriscv-sim/app/VexRiscvSimulation.hs index 5298542..0979a7c 100644 --- a/clash-vexriscv-sim/app/VexRiscvSimulation.hs +++ b/clash-vexriscv-sim/app/VexRiscvSimulation.hs @@ -1,4 +1,4 @@ --- SPDX-FileCopyrightText: 2022 Google LLC +-- SPDX-FileCopyrightText: 2022-2024 Google LLC -- -- SPDX-License-Identifier: Apache-2.0 {-# LANGUAGE NumericUnderscores #-} @@ -16,13 +16,13 @@ import qualified Data.List as L import Control.Monad (forM_, when) import Data.Char (chr) -import Data.Maybe (catMaybes, fromMaybe) +import Data.Maybe (catMaybes) import System.Environment (getArgs) import System.IO (putChar, hFlush, stdout) import Text.Printf (printf) -import Utils.ProgramLoad (loadProgram) +import Utils.ProgramLoad (loadProgramDmem) import Utils.Cpu (cpu) import System.Exit (exitFailure) @@ -78,21 +78,18 @@ main = do (iMem, dMem) <- withClockResetEnable @System clockGen resetGen enableGen $ - loadProgram @System elfFile + loadProgramDmem @System elfFile let cpuOut@(unbundle -> (_circuit, writes, _iBus, _dBus)) = withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $ let (circ, writes1, iBus, dBus) = cpu (Just 7894) iMem dMem - dBus' = register Nothing dBus + dBus' = register emptyWishboneS2M dBus in bundle (circ, writes1, iBus, dBus') case debugConfig of RunCharacterDevice -> forM_ (sample_lazy @System (bundle (register @System (unpack 0) cpuOut, cpuOut))) $ - \((_out, write, dS2M0, iS2M0), (out1, _write, _dS2M, _iS2M)) -> do - let - iS2M = fromMaybe emptyWishboneS2M iS2M0 - dS2M = fromMaybe emptyWishboneS2M dS2M0 + \((_out, write, dS2M, iS2M), (out1, _write, _dS2M, _iS2M)) -> do when (err dS2M) $ do let dBusM2S = dBusWbM2S out1 @@ -125,10 +122,8 @@ main = do let total = initCycles + uninteresting + nInteresting in L.zip [0 ..] $ L.take total $ sample_lazy @System cpuOut - forM_ sampled $ \(i, (out, _, iBusS2M0, dBusS2M0)) -> do + forM_ sampled $ \(i, (out, _, iBusS2M, dBusS2M)) -> do let - iBusS2M = fromMaybe emptyWishboneS2M iBusS2M0 - dBusS2M = fromMaybe emptyWishboneS2M dBusS2M0 doPrint = i >= skipTotal -- I-bus interactions diff --git a/clash-vexriscv-sim/src/Utils/Cpu.hs b/clash-vexriscv-sim/src/Utils/Cpu.hs index 6c90b0f..bffe6a6 100644 --- a/clash-vexriscv-sim/src/Utils/Cpu.hs +++ b/clash-vexriscv-sim/src/Utils/Cpu.hs @@ -19,7 +19,7 @@ import VexRiscv.VecToTuple (vecToTuple) import GHC.Stack (HasCallStack) -import Utils.ProgramLoad (Memory) +import Utils.ProgramLoad (Memory, DMemory) import Utils.Interconnect (interconnectTwo) createDomain vXilinxSystem{vName="Basic50", vPeriod= hzToPeriod 50_000_000} @@ -34,21 +34,21 @@ Address space cpu :: (HasCallStack, HiddenClockResetEnable dom) => Maybe Integer -> - Memory dom -> - Memory dom -> + DMemory dom -> + DMemory dom -> ( Signal dom CpuOut, -- writes Signal dom (Maybe (BitVector 32, BitVector 32)), -- iBus responses - Signal dom (Maybe (WishboneS2M (BitVector 32))), + Signal dom (WishboneS2M (BitVector 32)), -- dBus responses - Signal dom (Maybe (WishboneS2M (BitVector 32))) + Signal dom (WishboneS2M (BitVector 32)) ) cpu jtagPort bootIMem bootDMem = ( output , writes - , mux validI (Just <$> iS2M) (pure Nothing) - , mux validD (Just <$> dS2M) (pure Nothing) + , iS2M + , dS2M ) where (output, jtagOut) = vexRiscv hasClock hasReset input jtagIn @@ -56,27 +56,39 @@ cpu jtagPort bootIMem bootDMem = jtagIn = case jtagPort of Just port -> vexrJtagBridge (fromInteger port) jtagOut Nothing -> pure JTag.defaultIn - -- (unbundle -> (jtagIn', _debugReset)) = unsafePerformIO $ jtagTcpBridge' 7894 hasReset (jtagOut <$> output) - dM2S = dBusWbM2S <$> output - validD = fmap busCycle dM2S .&&. fmap strobe dM2S + {- + 00000000 - dummy area + 20000000 - instruction memory + 40000000 - data memory + -} + + -- The I-bus is only split once, for the D-mem and everything below. + (iS2M, vecToTuple . unbundle -> (iMemIM2S, dMemIM2S)) = interconnectTwo + (unBusAddr . iBusWbM2S <$> output) + ((0x0000_0000, iMemIS2M) :> (0x4000_0000, dMemIS2M) :> Nil) - iM2S = unBusAddr . iBusWbM2S <$> output - validI = fmap busCycle iM2S .&&. fmap strobe iM2S + -- Because the dummy region should never be accessed by the instruction bus + -- it's just "ignored" + (iMemIS2M, iMemDS2M) = bootIMem (mapAddr (\x -> complement 0x2000_0000 .&. x) <$> iMemIM2S) iMemDM2S - iS2M = bootIMem (mapAddr (\x -> -- trace (printf "I-addr = % 8X (% 8X)\n" (toInteger $ x - 0x2000_0000) (toInteger x)) - x - 0x2000_0000) <$> iM2S) + -- needed for 'writes' below + dM2S = dBusWbM2S <$> output - dummy = dummyWb + -- because of the memory map having the dummy at 0x0.., then instructions + -- and then data memory, the D-bus is split in an "upper" and "lower" region, + -- where the "upper" region is just the D-mem, the "lower" region gets split + -- again for the instruction memory and the dummy + (dS2M, vecToTuple . unbundle -> (dLowerRegionM2S, dUpperRegionM2S)) = interconnectTwo + (unBusAddr <$> dM2S) + ((0x0000_0000, dLowerRegionS2M) :> (0x4000_0000, dUpperRegionS2M) :> Nil) - dummyS2M = dummy dummyM2S - bootDS2M = bootDMem bootDM2S + (dLowerRegionS2M, vecToTuple . unbundle -> (dDummyM2S, iMemDM2S)) = interconnectTwo + dLowerRegionM2S + ((0x0000_0000, dDummyS2M) :> (0x2000_0000, iMemDS2M) :> Nil) - (dS2M, vecToTuple . unbundle -> (dummyM2S, bootDM2S)) = interconnectTwo - ((\x -> - -- trace (printf "DBUS %08X" (toInteger (addr x))) - x) <$> (unBusAddr <$> dM2S)) - ((0x0000_0000, dummyS2M) :> (0x4000_0000, bootDS2M) :> Nil) + (dUpperRegionS2M, dMemIS2M) = bootDMem dUpperRegionM2S dMemIM2S + dDummyS2M = dummyWb dDummyM2S input = ( \iBus dBus -> diff --git a/clash-vexriscv-sim/src/Utils/ProgramLoad.hs b/clash-vexriscv-sim/src/Utils/ProgramLoad.hs index 5c74cc3..6adf86d 100644 --- a/clash-vexriscv-sim/src/Utils/ProgramLoad.hs +++ b/clash-vexriscv-sim/src/Utils/ProgramLoad.hs @@ -18,6 +18,48 @@ import Control.Exception (assert) import Utils.ReadElf import Utils.Storage +type DMemory dom = + Signal dom (WishboneM2S 32 4 (BitVector 32)) -> + Signal dom (WishboneM2S 32 4 (BitVector 32)) -> + (Signal dom (WishboneS2M (BitVector 32)), Signal dom (WishboneS2M (BitVector 32))) + +loadProgramDmem :: (HiddenClockResetEnable dom) => FilePath -> IO (DMemory dom, DMemory dom) +loadProgramDmem path = do + elfBytes <- BS.readFile path + let (entry, iMem, dMem) = readElfFromMemory elfBytes + + assert (entry == 0x2000_0000) (pure ()) + + let + endianSwap dat = + L.concatMap (\(a, b, c, d) -> [d, c, b, a]) $ + chunkFill4 0 dat + + -- endian swap instructions + iMemContents = endianSwap $ + content iMem <> [0, 0, 0, 0, 0, 0, 0, 0] + dMemContents = endianSwap $ + content dMem <> [0, 0, 0, 0, 0, 0, 0, 0] + + + let instrMem = dualPortStorage iMemContents + dataMem = dualPortStorage dMemContents + + pure (instrMem, dataMem) + where + content :: BinaryData -> [BitVector 8] + content bin = L.map snd $ I.toAscList bin + + chunkFill4 :: a -> [a] -> [(a, a, a, a)] + chunkFill4 fill = \case + [] -> [] + [a] -> [(a, fill, fill, fill)] + [a, b] -> [(a, b, fill, fill)] + [a, b, c] -> [(a, b, c, fill)] + (a:b:c:d:rest) -> (a, b, c, d) : chunkFill4 fill rest + + + type Memory dom = ( Signal dom (WishboneM2S 32 4 (BitVector 32)) -> diff --git a/clash-vexriscv-sim/src/Utils/Storage.hs b/clash-vexriscv-sim/src/Utils/Storage.hs index b053779..8e34acc 100644 --- a/clash-vexriscv-sim/src/Utils/Storage.hs +++ b/clash-vexriscv-sim/src/Utils/Storage.hs @@ -5,11 +5,16 @@ {-# LANGUAGE ApplicativeDo #-} {-# LANGUAGE RecordWildCards #-} +-- it doesn't like lazy matching on `Signal`s it seems? +{-# OPTIONS_GHC -Wno-incomplete-patterns #-} + module Utils.Storage ( storage + , dualPortStorage ) where import Clash.Prelude +import Clash.Signal.Internal (Signal((:-))) import Data.Either (isLeft) import Protocols.Wishbone @@ -40,6 +45,61 @@ instance NFDataX MappedMemory where -- 'BitVector'. rnfX x = seq x () +dualPortStorage :: + forall dom. + ( KnownDomain dom, + HiddenClockResetEnable dom + ) => + [BitVector 8] -> + -- ^ contents + Signal dom (WishboneM2S 32 4 (BitVector 32)) -> + -- ^ in A + Signal dom (WishboneM2S 32 4 (BitVector 32)) -> + -- ^ in B + ( Signal dom (WishboneS2M (BitVector 32)) + -- ^ out A + , Signal dom (WishboneS2M (BitVector 32)) + -- ^ out B + ) +dualPortStorage contents portA portB = (aReply, bReply) + where + actualResult = storage contents inSignal + + (_port, inSignal, aReply, bReply) = unbundle $ go A portA portB actualResult + + go !currentPort (a :- inA) (b :- inB) ~(res :- actualResult') + -- neither active, just say A is current, do nothing + | not aActive && not bActive = + (A, a, res, emptyWishboneS2M) :- (res `seq` next) + -- A current, A active -> do A + | currentPort == A && aActive = + (A, a, res, emptyWishboneS2M) :- (res `seq` next) + -- current A, A not active but B is, do B and switch to B + | currentPort == A && not aActive && bActive = + (B, b, emptyWishboneS2M, res) :- (res `seq` next) + -- current B, B active -> do B + | currentPort == B && bActive = + (B, b, emptyWishboneS2M, res) :- (res `seq` next) + -- current B, B not active, but A is, do A and switch to A + | currentPort == B && not bActive && aActive = + (A, a, res, emptyWishboneS2M) :- (res `seq` next) + where + aActive = strobe a && busCycle a + bActive = strobe b && busCycle b + + nextPort = case (currentPort, aActive, bActive) of + (_, False, False) -> A + (A, False, True) -> B + (A, True, _) -> A + (B, _, True) -> B + (B, True, False) -> A + + next = go nextPort inA inB actualResult' + +data AorB = A | B deriving (Generic, NFDataX, Eq) + + + storage :: forall dom. ( KnownDomain dom, @@ -53,7 +113,7 @@ storage contents = mealy go (MappedMemory $ I.fromAscList $ L.zip [0..] contents where size = L.length contents - go (MappedMemory mem) WishboneM2S{..} + go (MappedMemory !mem) WishboneM2S{..} | not (busCycle && strobe) = (MappedMemory mem, emptyWishboneS2M) | addr >= fromIntegral size = (MappedMemory mem, emptyWishboneS2M { err = True }) diff --git a/clash-vexriscv-sim/tests/tests.hs b/clash-vexriscv-sim/tests/tests.hs index 23283e4..8166768 100644 --- a/clash-vexriscv-sim/tests/tests.hs +++ b/clash-vexriscv-sim/tests/tests.hs @@ -21,7 +21,7 @@ import System.IO.Temp (withSystemTempFile) import Test.Tasty import Test.Tasty.HUnit (Assertion, testCase, (@?=)) -import Utils.ProgramLoad (loadProgram) +import Utils.ProgramLoad (loadProgramDmem) import Utils.Cpu (cpu) @@ -35,7 +35,8 @@ runProgramExpect :: Assertion runProgramExpect act n expected = withSystemTempFile "ELF" $ \fp _ -> do act fp - (iMem, dMem) <- withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $ loadProgram fp + (iMem, dMem) <- withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $ + loadProgramDmem fp let _all@(unbundle -> (_circuit, writes, _iBus, _dBus)) = withClockResetEnable @System clockGen (resetGenN (SNat @2)) enableGen $ diff --git a/clash-vexriscv/src/ffi/impl.cpp b/clash-vexriscv/src/ffi/impl.cpp index e305f3c..26f2f3e 100644 --- a/clash-vexriscv/src/ffi/impl.cpp +++ b/clash-vexriscv/src/ffi/impl.cpp @@ -297,7 +297,7 @@ void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output, } } } - d->timer = 27; // 3; value used by VexRiscv regression test + d->timer = 3; } void vexr_jtag_bridge_shutdown(vexr_jtag_bridge_data *bridge_data) From 95f15230bc1a3dd794c2fd4baebb776160faf5f6 Mon Sep 17 00:00:00 2001 From: Martijn Bastiaan Date: Wed, 6 Mar 2024 17:27:32 +0100 Subject: [PATCH 3/9] Style fixes by dictionary / HLint --- clash-vexriscv-sim/src/Utils/Storage.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clash-vexriscv-sim/src/Utils/Storage.hs b/clash-vexriscv-sim/src/Utils/Storage.hs index 8e34acc..13ad197 100644 --- a/clash-vexriscv-sim/src/Utils/Storage.hs +++ b/clash-vexriscv-sim/src/Utils/Storage.hs @@ -36,12 +36,12 @@ instance NFDataX MappedMemory where -- WHNF ~ NF, so we only need to check the values. hasUndefined m = isLeft (isX (unMappedMemory m)) - || (any hasUndefined $ I.elems $ unMappedMemory m) + || any hasUndefined (I.elems $ unMappedMemory m) -- Not a product type, so no spine ensureSpine = id - -- This is a strict map, so we dont need to do anything. Note that WHNF ~ NF for + -- This is a strict map, so we don't need to do anything. Note that WHNF ~ NF for -- 'BitVector'. rnfX x = seq x () From 6e0df33e7899bf3501adcb1a792735ef55dced6f Mon Sep 17 00:00:00 2001 From: Martijn Bastiaan Date: Thu, 7 Mar 2024 10:42:24 +0100 Subject: [PATCH 4/9] Add GDB tests --- clash-vexriscv-sim/clash-vexriscv-sim.cabal | 16 +++- clash-vexriscv-sim/tests/Tests/Jtag.hs | 96 +++++++++++++++++++++ clash-vexriscv-sim/tests/tests.hs | 7 +- 3 files changed, 112 insertions(+), 7 deletions(-) create mode 100644 clash-vexriscv-sim/tests/Tests/Jtag.hs diff --git a/clash-vexriscv-sim/clash-vexriscv-sim.cabal b/clash-vexriscv-sim/clash-vexriscv-sim.cabal index fe75768..f35e3a6 100644 --- a/clash-vexriscv-sim/clash-vexriscv-sim.cabal +++ b/clash-vexriscv-sim/clash-vexriscv-sim.cabal @@ -105,6 +105,7 @@ executable clash-vexriscv-bin main-is: VexRiscvSimulation.hs hs-source-dirs: app default-language: Haskell2010 + ghc-options: -threaded -rtsopts "-with-rtsopts=-M100M" build-depends: base, clash-prelude, @@ -122,18 +123,25 @@ test-suite unittests type: exitcode-stdio-1.0 -- TODO: enable parallel tests: -- ghc-options: -threaded -rtsopts -with-rtsopts=-N + build-tool-depends: + clash-vexriscv-sim:clash-vexriscv-bin ghc-options: -threaded main-is: tests.hs + other-modules: + Tests.Jtag build-depends: + async, base, + bytestring, clash-prelude, clash-protocols, - clash-vexriscv, clash-vexriscv-sim, - bytestring, + clash-vexriscv, containers, directory, - temporary >=1.1 && <1.4, + extra, + filepath, + process, tasty >= 1.2 && < 1.6, tasty-hunit >= 0.10 && < 0.11, - filepath + temporary >=1.1 && <1.4, diff --git a/clash-vexriscv-sim/tests/Tests/Jtag.hs b/clash-vexriscv-sim/tests/Tests/Jtag.hs new file mode 100644 index 0000000..5d4baaf --- /dev/null +++ b/clash-vexriscv-sim/tests/Tests/Jtag.hs @@ -0,0 +1,96 @@ +-- | Tests for the JTAG debug interface +module Tests.Jtag where + +import Prelude + +import Control.Monad.Extra (ifM) +import Data.List.Extra (trim) +import Data.Maybe (fromJust) +import System.Exit +import System.IO +import System.Process + +import Test.Tasty +import Test.Tasty.HUnit + +cabalListBin :: String -> IO FilePath +cabalListBin name = do + trim <$> readProcess "cabal" ["-v0", "list-bin", name] "" + +getProjectRoot :: IO FilePath +getProjectRoot = trim <$> readProcess "git" ["rev-parse", "--show-toplevel"] "" + +getSimulateExecPath :: IO FilePath +getSimulateExecPath = cabalListBin "clash-vexriscv-sim:clash-vexriscv-bin" + +getPrintElfPath :: IO FilePath +getPrintElfPath = pure "target/riscv32imc-unknown-none-elf/debug/print_a" + +getOpenOcdCfgPath :: IO FilePath +getOpenOcdCfgPath = pure "vexriscv_sim.cfg" + +getGdbCmdPath :: IO FilePath +getGdbCmdPath = pure "vexriscv_gdb.cfg" + +expectLine :: Handle -> String -> Assertion +expectLine h expected = do + line <- hGetLine h + ifM + (pure $ null line) + (expectLine h expected) + (expected @?= line) + +waitForLine :: Handle -> String -> IO () +waitForLine h expected = do + line <- hGetLine h + if line == expected + then pure () + else waitForLine h expected + +test :: Assertion +test = do + simulateExecPath <- getSimulateExecPath + printElfPath <- getPrintElfPath + projectRoot <- getProjectRoot + openocdCfgPath <- getOpenOcdCfgPath + gdbCmdPath <- getGdbCmdPath + + let + vexRiscvProc = (proc simulateExecPath [printElfPath]){ + std_out = CreatePipe + , cwd = Just projectRoot + } + + openOcdProc = (proc "openocd-vexriscv" ["-f", openocdCfgPath]){ + std_err = CreatePipe + , cwd = Just projectRoot + } + + gdbProc = (proc "gdb" ["--command", gdbCmdPath]){ + std_out = CreatePipe -- Comment this line to see GDB output + , cwd = Just projectRoot + } + + withCreateProcess vexRiscvProc $ \_ (fromJust -> vexRiscvStdOut) _ _ -> do + hSetBuffering vexRiscvStdOut LineBuffering + expectLine vexRiscvStdOut "[CPU] a" + + -- CPU has started, so we can start OpenOCD + withCreateProcess openOcdProc $ \_ _ (fromJust -> openOcdStdErr) _ -> do + waitForLine openOcdStdErr "Halting processor" + + -- OpenOCD has started, so we can start GDB + withCreateProcess gdbProc $ \_ _ _ gdbProcHandle -> do + expectLine vexRiscvStdOut "[CPU] a" + expectLine vexRiscvStdOut "[CPU] b" + + gdbExitCode <- waitForProcess gdbProcHandle + ExitSuccess @?= gdbExitCode + +tests :: TestTree +tests = testGroup "JTAG" + [ testCase "Basic GDB commands, breakpoints, and program loading" test + ] + +main :: IO () +main = defaultMain tests diff --git a/clash-vexriscv-sim/tests/tests.hs b/clash-vexriscv-sim/tests/tests.hs index 8166768..39cf1be 100644 --- a/clash-vexriscv-sim/tests/tests.hs +++ b/clash-vexriscv-sim/tests/tests.hs @@ -7,6 +7,7 @@ import Clash.Prelude import qualified Data.ByteString as BS import qualified Data.List as L +import qualified Tests.Jtag as Jtag import Control.Monad (forM) import Data.Maybe (catMaybes, mapMaybe) @@ -17,7 +18,6 @@ import System.Exit (exitFailure) import System.FilePath import System.IO import System.IO.Temp (withSystemTempFile) - import Test.Tasty import Test.Tasty.HUnit (Assertion, testCase, (@?=)) @@ -128,8 +128,9 @@ main = do let tests = testGroup "VexRiscv Tests" - [ testGroup "Debug builds" debugTestCases, - testGroup "Release builds" releaseTestCases + [ testGroup "Debug builds" debugTestCases + , testGroup "Release builds" releaseTestCases + , Jtag.tests ] defaultMain tests From 12cf4894601206eac3bd93e05fe50f738ea7b8d1 Mon Sep 17 00:00:00 2001 From: Martijn Bastiaan Date: Thu, 7 Mar 2024 10:53:45 +0100 Subject: [PATCH 5/9] Connect JTAG reset out to CPU reset in, in `cpu` --- clash-vexriscv-sim/clash-vexriscv-sim.cabal | 6 +++++ .../data/vexriscv_gdb.cfg | 2 +- .../data/vexriscv_sim.cfg | 0 clash-vexriscv-sim/src/Utils/Cpu.hs | 14 ++++++++++-- clash-vexriscv-sim/tests/Tests/Jtag.hs | 22 +++++++++++++++---- clash-vexriscv-sim/tests/tests.hs | 2 +- debug-test/src/bin/print_a.rs | 2 +- debug-test/src/bin/print_b.rs | 2 +- 8 files changed, 40 insertions(+), 10 deletions(-) rename vexriscv_gdb.cfg => clash-vexriscv-sim/data/vexriscv_gdb.cfg (96%) rename vexriscv_sim.cfg => clash-vexriscv-sim/data/vexriscv_sim.cfg (100%) diff --git a/clash-vexriscv-sim/clash-vexriscv-sim.cabal b/clash-vexriscv-sim/clash-vexriscv-sim.cabal index f35e3a6..e30a40c 100644 --- a/clash-vexriscv-sim/clash-vexriscv-sim.cabal +++ b/clash-vexriscv-sim/clash-vexriscv-sim.cabal @@ -7,6 +7,9 @@ author: QBayLogic B.V. maintainer: devops@qbaylogic.com Copyright: Copyright © 2022 Google LLC +extra-source-files: + data/*.cfg + common common-options default-extensions: BangPatterns @@ -125,9 +128,12 @@ test-suite unittests -- ghc-options: -threaded -rtsopts -with-rtsopts=-N build-tool-depends: clash-vexriscv-sim:clash-vexriscv-bin + autogen-modules: + Paths_clash_vexriscv_sim ghc-options: -threaded main-is: tests.hs other-modules: + Paths_clash_vexriscv_sim Tests.Jtag build-depends: async, diff --git a/vexriscv_gdb.cfg b/clash-vexriscv-sim/data/vexriscv_gdb.cfg similarity index 96% rename from vexriscv_gdb.cfg rename to clash-vexriscv-sim/data/vexriscv_gdb.cfg index f6af1a4..362d7c7 100644 --- a/vexriscv_gdb.cfg +++ b/clash-vexriscv-sim/data/vexriscv_gdb.cfg @@ -1,6 +1,6 @@ # Execute using: # -# gdb --command=vexriscv_gdb.cfg +# gdb --command vexriscv_gdb.cfg # # SPDX-FileCopyrightText: 2024 Google LLC diff --git a/vexriscv_sim.cfg b/clash-vexriscv-sim/data/vexriscv_sim.cfg similarity index 100% rename from vexriscv_sim.cfg rename to clash-vexriscv-sim/data/vexriscv_sim.cfg diff --git a/clash-vexriscv-sim/src/Utils/Cpu.hs b/clash-vexriscv-sim/src/Utils/Cpu.hs index bffe6a6..faed33f 100644 --- a/clash-vexriscv-sim/src/Utils/Cpu.hs +++ b/clash-vexriscv-sim/src/Utils/Cpu.hs @@ -21,6 +21,7 @@ import GHC.Stack (HasCallStack) import Utils.ProgramLoad (Memory, DMemory) import Utils.Interconnect (interconnectTwo) +import Clash.Explicit.Prelude (unsafeOrReset) createDomain vXilinxSystem{vName="Basic50", vPeriod= hzToPeriod 50_000_000} @@ -32,7 +33,12 @@ Address space 0b0100 0x4000_0000 data memory -} cpu :: - (HasCallStack, HiddenClockResetEnable dom) => + ( HasCallStack + , HiddenClockResetEnable dom + -- XXX: VexRiscv responds asynchronously to the reset signal. Figure out how + -- convenient it is to use this within a design with synchronous resets. + -- , HasAsynchronousReset dom + ) => Maybe Integer -> DMemory dom -> DMemory dom -> @@ -51,7 +57,11 @@ cpu jtagPort bootIMem bootDMem = , dS2M ) where - (output, jtagOut) = vexRiscv hasClock hasReset input jtagIn + (output, jtagOut) = vexRiscv hasClock (hasReset `unsafeOrReset` jtagReset) input jtagIn + + jtagReset = + unsafeFromActiveHigh $ register False $ + bitToBool . debugReset <$> jtagOut jtagIn = case jtagPort of Just port -> vexrJtagBridge (fromInteger port) jtagOut diff --git a/clash-vexriscv-sim/tests/Tests/Jtag.hs b/clash-vexriscv-sim/tests/Tests/Jtag.hs index 5d4baaf..50948a1 100644 --- a/clash-vexriscv-sim/tests/Tests/Jtag.hs +++ b/clash-vexriscv-sim/tests/Tests/Jtag.hs @@ -1,3 +1,7 @@ +-- SPDX-FileCopyrightText: 2024 Google LLC +-- +-- SPDX-License-Identifier: Apache-2.0 + -- | Tests for the JTAG debug interface module Tests.Jtag where @@ -13,6 +17,8 @@ import System.Process import Test.Tasty import Test.Tasty.HUnit +import Paths_clash_vexriscv_sim (getDataFileName) + cabalListBin :: String -> IO FilePath cabalListBin name = do trim <$> readProcess "cabal" ["-v0", "list-bin", name] "" @@ -27,10 +33,10 @@ getPrintElfPath :: IO FilePath getPrintElfPath = pure "target/riscv32imc-unknown-none-elf/debug/print_a" getOpenOcdCfgPath :: IO FilePath -getOpenOcdCfgPath = pure "vexriscv_sim.cfg" +getOpenOcdCfgPath = getDataFileName "data/vexriscv_sim.cfg" getGdbCmdPath :: IO FilePath -getGdbCmdPath = pure "vexriscv_gdb.cfg" +getGdbCmdPath = getDataFileName "data/vexriscv_gdb.cfg" expectLine :: Handle -> String -> Assertion expectLine h expected = do @@ -47,6 +53,13 @@ waitForLine h expected = do then pure () else waitForLine h expected +-- | Run three processes in parallel: +-- +-- 1. The VexRiscv simulation. It opens a TCP socket for OpenOCD to connect to. +-- 2. OpenOCD. It connects to the VexRiscv simulation and exposes a GDB server. +-- 3. GDB. It connects to the OpenOCD GDB server and bunch of commands. See the +-- file produced by 'getGdbCmdPath' for the commands. +-- test :: Assertion test = do simulateExecPath <- getSimulateExecPath @@ -67,8 +80,8 @@ test = do } gdbProc = (proc "gdb" ["--command", gdbCmdPath]){ - std_out = CreatePipe -- Comment this line to see GDB output - , cwd = Just projectRoot + std_out = CreatePipe, -- Comment this line to see GDB output + cwd = Just projectRoot } withCreateProcess vexRiscvProc $ \_ (fromJust -> vexRiscvStdOut) _ _ -> do @@ -77,6 +90,7 @@ test = do -- CPU has started, so we can start OpenOCD withCreateProcess openOcdProc $ \_ _ (fromJust -> openOcdStdErr) _ -> do + hSetBuffering openOcdStdErr LineBuffering waitForLine openOcdStdErr "Halting processor" -- OpenOCD has started, so we can start GDB diff --git a/clash-vexriscv-sim/tests/tests.hs b/clash-vexriscv-sim/tests/tests.hs index 39cf1be..81f2c78 100644 --- a/clash-vexriscv-sim/tests/tests.hs +++ b/clash-vexriscv-sim/tests/tests.hs @@ -1,4 +1,4 @@ --- SPDX-FileCopyrightText: 2022-2023 Google LLC +-- SPDX-FileCopyrightText: 2022-2024 Google LLC -- -- SPDX-License-Identifier: Apache-2.0 {-# LANGUAGE NumericUnderscores #-} diff --git a/debug-test/src/bin/print_a.rs b/debug-test/src/bin/print_a.rs index 1d8a7b5..296c683 100644 --- a/debug-test/src/bin/print_a.rs +++ b/debug-test/src/bin/print_a.rs @@ -22,7 +22,7 @@ fn print(s: &str) { } fn done() -> ! { - loop {}; + loop {} } #[cfg_attr(not(test), entry)] diff --git a/debug-test/src/bin/print_b.rs b/debug-test/src/bin/print_b.rs index 1e5bde1..cb689c5 100644 --- a/debug-test/src/bin/print_b.rs +++ b/debug-test/src/bin/print_b.rs @@ -22,7 +22,7 @@ fn print(s: &str) { } fn done() -> ! { - loop {}; + loop {} } #[cfg_attr(not(test), entry)] From bf01da028fe561f03841db7c6828bc6fdf219432 Mon Sep 17 00:00:00 2001 From: Martijn Bastiaan Date: Thu, 7 Mar 2024 11:16:26 +0100 Subject: [PATCH 6/9] Follow XDG standard on CI (like newer Cabals) --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 30db84a..2928b70 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -131,7 +131,7 @@ jobs: uses: actions/cache@v3 with: path: | - ~/.cabal/store + ~/.local/state/cabal/store/ key: packages-cachebust-2-${{ matrix.ghc }}-${{ hashFiles('cabal.project.freeze', 'cabal.project') }} restore-keys: packages-cachebust-2-${{ matrix.ghc }} From 44c69d12bfc570c1946aa5f8da20a44777041b36 Mon Sep 17 00:00:00 2001 From: Martijn Bastiaan Date: Thu, 7 Mar 2024 11:41:27 +0100 Subject: [PATCH 7/9] Added HDL generation test Tests the bare minimum: whether HDL can be generated using Clash --- .github/workflows/ci.yml | 4 ++++ .gitignore | 3 +++ clash-vexriscv-sim/app/Clash.hs | 10 --------- clash-vexriscv-sim/app/HdlTest.hs | 22 ++++-------------- clash-vexriscv-sim/clash-vexriscv-sim.cabal | 18 ++++++++------- clash-vexriscv-sim/src/Utils/Instance.hs | 25 +++++++++++++++++++++ clash-vexriscv/clash-vexriscv.cabal | 7 ++++++ clash-vexriscv/src/VexRiscv.hs | 8 +++---- 8 files changed, 57 insertions(+), 40 deletions(-) delete mode 100644 clash-vexriscv-sim/app/Clash.hs create mode 100644 clash-vexriscv-sim/src/Utils/Instance.hs diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2928b70..4605214 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -183,3 +183,7 @@ jobs: - name: Run `clash-vexriscv-sim` unittests run: | cabal run clash-vexriscv-sim:unittests + + - name: Run `clash-vexriscv-sim` HDL test + run: | + cabal run clash-vexriscv-sim:hdl-test diff --git a/.gitignore b/.gitignore index 407020e..fc2b16f 100644 --- a/.gitignore +++ b/.gitignore @@ -68,3 +68,6 @@ tight_setup_hold_pins.txt # Verilator debug output simulation_dump.vcd + +# Clash output +verilog diff --git a/clash-vexriscv-sim/app/Clash.hs b/clash-vexriscv-sim/app/Clash.hs deleted file mode 100644 index ba548f1..0000000 --- a/clash-vexriscv-sim/app/Clash.hs +++ /dev/null @@ -1,10 +0,0 @@ --- SPDX-FileCopyrightText: 2023 Google LLC --- --- SPDX-License-Identifier: Apache-2.0 - -import Prelude -import System.Environment (getArgs) -import Clash.Main (defaultMain) - -main :: IO () -main = getArgs >>= defaultMain diff --git a/clash-vexriscv-sim/app/HdlTest.hs b/clash-vexriscv-sim/app/HdlTest.hs index f04dd29..73b0586 100644 --- a/clash-vexriscv-sim/app/HdlTest.hs +++ b/clash-vexriscv-sim/app/HdlTest.hs @@ -1,24 +1,10 @@ --- SPDX-FileCopyrightText: 2023 Google LLC +-- SPDX-FileCopyrightText: 2023-2024 Google LLC -- -- SPDX-License-Identifier: Apache-2.0 -import Clash.Prelude -import Clash.Annotations.TH +import Prelude -import VexRiscv - -circuit :: - "CLK" ::: Clock System -> - "RST" ::: Reset System -> - "CPU_COMB_INPUT" ::: Signal System CpuIn -> - "JTAG_IN_" ::: Signal System JtagIn -> - "" ::: - ( "CPU_OUTPUT" ::: Signal System CpuOut - , "JTAG_OUT_" ::: Signal System JtagOut) -circuit clk rst input jtagIn = - vexRiscv clk rst input jtagIn - -makeTopEntity 'circuit +import qualified Clash.Main as Clash main :: IO () -main = pure () +main = Clash.defaultMain ["Utils.Instance", "-main-is", "circuit", "--verilog"] diff --git a/clash-vexriscv-sim/clash-vexriscv-sim.cabal b/clash-vexriscv-sim/clash-vexriscv-sim.cabal index e30a40c..e860fbc 100644 --- a/clash-vexriscv-sim/clash-vexriscv-sim.cabal +++ b/clash-vexriscv-sim/clash-vexriscv-sim.cabal @@ -46,6 +46,13 @@ common common-options -- Prelude isn't imported by default as Clash offers Clash.Prelude NoImplicitPrelude + + -- See https://github.com/clash-lang/clash-compiler/pull/2511 + if impl(ghc >= 9.4) + CPP-Options: -DCLASH_OPAQUE=OPAQUE + else + CPP-Options: -DCLASH_OPAQUE=NOINLINE + ghc-options: -Wall -Wcompat @@ -76,6 +83,7 @@ library default-language: Haskell2010 exposed-modules: Utils.Cpu + Utils.Instance Utils.Interconnect Utils.ProgramLoad Utils.ReadElf @@ -88,19 +96,13 @@ library clash-vexriscv, elf >= 0.31 && < 0.32, -executable clash - import: common-options - main-is: app/Clash.hs - build-Depends: base, clash-ghc - +-- XXX: Doesn't really belong in clash-vexriscv-SIM executable hdl-test import: common-options main-is: app/HdlTest.hs build-Depends: base, - clash-prelude, - clash-protocols, - clash-vexriscv, + clash-ghc, clash-vexriscv-sim, executable clash-vexriscv-bin diff --git a/clash-vexriscv-sim/src/Utils/Instance.hs b/clash-vexriscv-sim/src/Utils/Instance.hs new file mode 100644 index 0000000..0ba606c --- /dev/null +++ b/clash-vexriscv-sim/src/Utils/Instance.hs @@ -0,0 +1,25 @@ +-- SPDX-FileCopyrightText: 2024 Google LLC +-- +-- SPDX-License-Identifier: Apache-2.0 +{-# LANGUAGE CPP #-} + +-- | A dummy instance to test whether Clash can generate HDL for the VexRiscv +module Utils.Instance where + +import Clash.Prelude +import Clash.Annotations.TH + +import VexRiscv + +circuit :: + "CLK" ::: Clock System -> + "RST" ::: Reset System -> + "CPU_IN" ::: Signal System CpuIn -> + "JTAG_IN" ::: Signal System JtagIn -> + "" ::: + ( "CPU_OUTPUT" ::: Signal System CpuOut + , "JTAG_OUT" ::: Signal System JtagOut ) +circuit clk rst input jtagIn = + vexRiscv clk rst input jtagIn +{-# CLASH_OPAQUE circuit #-} +makeTopEntity 'circuit diff --git a/clash-vexriscv/clash-vexriscv.cabal b/clash-vexriscv/clash-vexriscv.cabal index 4ae60fb..7ae96cb 100644 --- a/clash-vexriscv/clash-vexriscv.cabal +++ b/clash-vexriscv/clash-vexriscv.cabal @@ -70,6 +70,13 @@ common common-options -- Prelude isn't imported by default as Clash offers Clash.Prelude NoImplicitPrelude + + -- See https://github.com/clash-lang/clash-compiler/pull/2511 + if impl(ghc >= 9.4) + CPP-Options: -DCLASH_OPAQUE=OPAQUE + else + CPP-Options: -DCLASH_OPAQUE=NOINLINE + ghc-options: -Wall -Wcompat diff --git a/clash-vexriscv/src/VexRiscv.hs b/clash-vexriscv/src/VexRiscv.hs index 366fa7b..098aba3 100644 --- a/clash-vexriscv/src/VexRiscv.hs +++ b/clash-vexriscv/src/VexRiscv.hs @@ -2,12 +2,12 @@ -- -- SPDX-License-Identifier: Apache-2.0 +{-# LANGUAGE CPP #-} +{-# LANGUAGE MagicHash #-} {-# LANGUAGE NamedFieldPuns #-} +{-# LANGUAGE QuasiQuotes #-} {-# LANGUAGE RecordWildCards #-} -{-# LANGUAGE MagicHash #-} {-# LANGUAGE TemplateHaskellQuotes #-} -{-# LANGUAGE QuasiQuotes #-} --- {-# LANGUAGE AllowAmbiguousTypes #-} {-# OPTIONS_GHC -fconstraint-solver-iterations=10 #-} @@ -356,7 +356,7 @@ vexRiscv# !_sourcePath clk rst0 , FFI.jtag_debug_resetOut <$> output , FFI.jtag_TDO <$> output ) -{-# NOINLINE vexRiscv# #-} +{-# CLASH_OPAQUE vexRiscv# #-} {-# ANN vexRiscv# ( let primName = 'vexRiscv# From 3bd03ded076f598e16c387f41d56b84bc4217962 Mon Sep 17 00:00:00 2001 From: Martijn Bastiaan Date: Thu, 7 Mar 2024 11:46:32 +0100 Subject: [PATCH 8/9] Disable JTAG tests due to CI environment --- .github/workflows/ci.yml | 4 ++++ clash-vexriscv-sim/tests/tests.hs | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4605214..9e298a1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -172,6 +172,10 @@ jobs: with: name: vexriscv-test-binaries + - name: Work around dubious owner error + run: | + git config --global --add safe.directory "$(pwd)" + - name: Extract VexRiscv Integration Tests run: | tar -x -f vexriscv-test-binaries.tar diff --git a/clash-vexriscv-sim/tests/tests.hs b/clash-vexriscv-sim/tests/tests.hs index 81f2c78..497997f 100644 --- a/clash-vexriscv-sim/tests/tests.hs +++ b/clash-vexriscv-sim/tests/tests.hs @@ -7,7 +7,6 @@ import Clash.Prelude import qualified Data.ByteString as BS import qualified Data.List as L -import qualified Tests.Jtag as Jtag import Control.Monad (forM) import Data.Maybe (catMaybes, mapMaybe) @@ -130,7 +129,8 @@ main = do "VexRiscv Tests" [ testGroup "Debug builds" debugTestCases , testGroup "Release builds" releaseTestCases - , Jtag.tests + -- XXX: Disabled, we need to add OpenOCD + GDB to CI (or use the Nix shell?) + -- , Jtag.tests ] defaultMain tests From 9c4ad84d41ee831ddcbb092bec221387af234da6 Mon Sep 17 00:00:00 2001 From: Lara Herzog Date: Thu, 7 Mar 2024 16:09:04 +0100 Subject: [PATCH 9/9] remove unused code --- clash-vexriscv/Makefile | 2 - .../src/VexRiscv/JtagTcpBridgeHaskell.hs | 186 ------------------ clash-vexriscv/src/ffi/impl.cpp | 18 -- 3 files changed, 206 deletions(-) delete mode 100644 clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs diff --git a/clash-vexriscv/Makefile b/clash-vexriscv/Makefile index a909e6b..ccc34a1 100644 --- a/clash-vexriscv/Makefile +++ b/clash-vexriscv/Makefile @@ -22,8 +22,6 @@ clean: $(CPU_DIR)/VexRiscv.v: $(CPU_DIR)/src/main/scala/example/ExampleCpu.scala cd $(CPU_DIR); sbt "runMain example.ExampleCpu" cd $(CPU_DIR); sed -i -E '/\/\/ Git hash :.*$$/d' VexRiscv.v - # cd $(CPU_DIR); sed -i 's/module VexRiscv/module VexRiscvInner/g' VexRiscv.v - # cd $(CPU_DIR); cat ../example-cpu/VexRiscvWrapped.v >> VexRiscv.v $(OUT_DIR)/VexRiscv.v: $(CPU_DIR)/VexRiscv.v mkdir -p $(OUT_DIR) diff --git a/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs b/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs deleted file mode 100644 index 3c6092d..0000000 --- a/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs +++ /dev/null @@ -1,186 +0,0 @@ --- SPDX-FileCopyrightText: 2023 Google LLC --- --- SPDX-License-Identifier: Apache-2.0 - -module VexRiscv.JtagTcpBridge where - -import Clash.Prelude - -import Clash.Signal.Internal -import Network.Socket -import Protocols -import Protocols.Internal (CSignal(..), Reverse) -import VexRiscv (JtagIn(..), JtagOut(..), Jtag) -import Control.Concurrent (MVar, forkIO, newEmptyMVar, putMVar, takeMVar, tryTakeMVar) -import Control.Monad (when) -import Network.Socket.ByteString (sendAll, recv) - -import qualified Data.ByteString as BS -import System.IO.Unsafe (unsafePerformIO) -import Debug.Trace (trace) - -data NetworkThreadToMainMsg - = Connected - | Disconnected - | DataReceived [BitVector 8] - -data MainToNetworkThreadMsg - = ReadMore - | Send (BitVector 8) - -data NetworkThreadState - = NoClient - | PerformRead Socket - | WaitForNextRead Socket - deriving (Show) - -data MainThreadState - = MDisconnected - | MWaitForRead - | MProcessing (BitVector 2) [BitVector 8] - deriving (Show) - -jtagTcpBridge :: - (HiddenClockResetEnable dom) => - PortNumber -> - Circuit - (Jtag dom, Reverse (CSignal dom Bool)) - () -jtagTcpBridge port = - Circuit $ \((jtagOut, _), ()) -> unsafePerformIO $ do - (enable, jtagIn) <- jtagTcpBridge' port jtagOut - pure ((jtagIn, CSignal $ fromEnable enable), ()) - -jtagTcpBridge' :: - (KnownDomain dom) => - PortNumber -> - Signal dom JtagOut -> - IO (Enable dom, Signal dom JtagIn) -jtagTcpBridge' port jtagOut = do - - (n2m, m2n) <- server port - - (unbundle -> (enable, jtagIn)) <- client n2m m2n MDisconnected jtagOut - - pure (toEnable enable, jtagIn) - -{-# NOINLINE jtagTcpBridge' #-} - -server :: PortNumber -> IO (MVar NetworkThreadToMainMsg, MVar MainToNetworkThreadMsg) -server port = withSocketsDo $ do - sock <- setup - - threadToMainChan <- newEmptyMVar - mainToThreadChan <- newEmptyMVar - - let - thread NoClient = do - (clientSock, _) <- accept sock - putMVar threadToMainChan Connected - thread (PerformRead clientSock) - thread (PerformRead clientSock) = do - buf <- recv clientSock 100 - if BS.null buf then do - putMVar threadToMainChan Disconnected - thread NoClient - else do - let dat = pack <$> BS.unpack buf - putMVar threadToMainChan (DataReceived dat) - thread (WaitForNextRead clientSock) - - thread (WaitForNextRead clientSock) = do - msg <- takeMVar mainToThreadChan - case msg of - ReadMore -> thread (PerformRead clientSock) - Send byte -> do - sendAll clientSock (BS.singleton $ unpack byte) - thread (WaitForNextRead clientSock) - - _ <- forkIO $ thread NoClient - - pure (threadToMainChan, mainToThreadChan) - - where - setup = do - sock <- socket AF_INET Stream 0 - - setSocketOption sock NoDelay 0 - - bind sock (SockAddrInet port (tupleToHostAddress (127, 0, 0, 1))) - - listen sock 1 - - pure sock - -defaultIn :: JtagIn -defaultIn = JtagIn { testModeSelect = low, testDataIn = low } - -dbg :: Show a => a -> a -dbg x = - trace (show x) - x - -clientSleep :: BitVector 2 -clientSleep = 4 - -client :: - (KnownDomain dom) => - MVar NetworkThreadToMainMsg -> - MVar MainToNetworkThreadMsg -> - MainThreadState -> - Signal dom JtagOut -> - IO (Signal dom (Bool, JtagIn)) -client n2m m2n MDisconnected (_out :- outs) = do - msg <- tryTakeMVar n2m - case msg of - Nothing -> - pure $ _out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MDisconnected outs) - Just Connected -> do - pure $ _out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MWaitForRead outs) - Just Disconnected -> do - errorX "????" - Just (DataReceived _xs) -> do - errorX "????" - -client n2m m2n MWaitForRead (out :- outs) = do - msg <- tryTakeMVar n2m - case msg of - Nothing -> - pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MWaitForRead outs) - Just Disconnected -> - pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MDisconnected outs) - Just (DataReceived xs) -> - client n2m m2n (MProcessing 0 xs) (out :- outs) - Just Connected -> - errorX "????" - -client n2m m2n (MProcessing _ []) (out :- outs) = do - putMVar m2n ReadMore - pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n MWaitForRead outs) -client n2m m2n (MProcessing 0 (x:xs)) (out :- outs) = do - let tms = x ! (0 :: Int) - tdi = x ! (1 :: Int) - tck = x ! (3 :: Int) - - sendTdo = bitToBool $ x ! (2 :: Int) - - enable = bitToBool tck - - when sendTdo $ do - let tdo = bitToBool $ testDataOut out - -- putStrLn $ "send TDO " <> show tdo - putMVar m2n $ Send $ boolToBV tdo - - let inDat = JtagIn { testModeSelect = tms, testDataIn = tdi } - - when enable $ do - -- putStrLn "Enable" - -- putStrLn $ "IN " <> showX inDat - pure () - - pure $ (enable, inDat) :- unsafePerformIO (client n2m m2n (MProcessing clientSleep xs) outs) -client n2m m2n (MProcessing n xs) (out :- outs) = do - pure $ out `deepseqX` (False, defaultIn) :- unsafePerformIO (client n2m m2n (MProcessing (n - 1) xs) outs) - - -{-# NOINLINE client #-} diff --git a/clash-vexriscv/src/ffi/impl.cpp b/clash-vexriscv/src/ffi/impl.cpp index 26f2f3e..7fe8dad 100644 --- a/clash-vexriscv/src/ffi/impl.cpp +++ b/clash-vexriscv/src/ffi/impl.cpp @@ -27,8 +27,6 @@ typedef struct { int32_t rx_buffer_size; int32_t rx_buffer_remaining; JTAG_INPUT prev_input; - - uint64_t tck_change_counter; } vexr_jtag_bridge_data; extern "C" { @@ -172,8 +170,6 @@ vexr_jtag_bridge_data *vexr_jtag_bridge_init(uint16_t port) d->prev_input = { 0, 0, 0 }; - d->tck_change_counter = 0; - d->timer = 0; d->self_sleep = 0; d->check_new_connections_timer = 0; @@ -214,7 +210,6 @@ vexr_jtag_bridge_data *vexr_jtag_bridge_init(uint16_t port) void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output, JTAG_INPUT *input) { - const int WAIT_PERIOD = 83333; // We set the input values to their last here // so that only the "successful" path has to update them @@ -273,19 +268,6 @@ void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output, input->tdi = (buffer & 2) != 0; input->tck = (buffer & 8) != 0; - // printf("\n[JTAG_BRIDGE] "); - // printf("%d %d %d %d\n", - // d->tck_change_counter, - // input->jtag_TCK, - // input->jtag_TMS, - // input->jtag_TDI - // ); - - if (input->tck != d->prev_input.tck) { - d->tck_change_counter++; - } - - d->prev_input = *input; if(buffer & 4){