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Chip_da_Tunetaro.kicad_pcb-bak
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Chip_da_Tunetaro.kicad_pcb-bak
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(kicad_pcb (version 20171130) (host pcbnew "(5.1.2)-1")
(general
(thickness 1.6)
(drawings 21)
(tracks 618)
(zones 0)
(modules 67)
(nets 72)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user hide)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.3)
(trace_clearance 0.3)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.5 1.5)
(pad_drill 1)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(C1-Pad2)")
(net 2 GND)
(net 3 "Net-(D1-Pad1)")
(net 4 LED1)
(net 5 LED2)
(net 6 "Net-(D2-Pad1)")
(net 7 "Net-(D3-Pad1)")
(net 8 LED3)
(net 9 "Net-(J1-Pad11)")
(net 10 CLK_SN)
(net 11 CLK_AY)
(net 12 5V)
(net 13 MUDA1)
(net 14 DATA)
(net 15 LATCH)
(net 16 SCK)
(net 17 3V3)
(net 18 MUDA2)
(net 19 CONTROL1)
(net 20 CONTROL2)
(net 21 CONTROL3)
(net 22 CONTROL4)
(net 23 RIGHT_IN)
(net 24 CHECK3)
(net 25 CHECK4)
(net 26 CHECK1)
(net 27 CHECK2)
(net 28 LEFT_IN)
(net 29 MUDA3)
(net 30 SCL)
(net 31 SDA)
(net 32 CLK_SAA)
(net 33 SW)
(net 34 16MHz)
(net 35 bias)
(net 36 LEFT_OUT)
(net 37 "Net-(C5-Pad2)")
(net 38 AMP_IN_L)
(net 39 "Net-(C6-Pad1)")
(net 40 "Net-(C7-Pad2)")
(net 41 RIGHT_OUT)
(net 42 "Net-(C8-Pad1)")
(net 43 AMP_IN_R)
(net 44 "Net-(JP2-Pad1)")
(net 45 "Net-(JP2-Pad2)")
(net 46 "Net-(JP3-Pad2)")
(net 47 "Net-(JP3-Pad1)")
(net 48 FLOW_OUT_SHIELD)
(net 49 "Net-(JP4-Pad2)")
(net 50 "Net-(JP5-Pad1)")
(net 51 "Net-(JP5-Pad2)")
(net 52 "Net-(JP6-Pad1)")
(net 53 "Net-(JP6-Pad2)")
(net 54 "Net-(JP7-Pad2)")
(net 55 "Net-(JP7-Pad1)")
(net 56 "Net-(JP8-Pad2)")
(net 57 "Net-(JP8-Pad1)")
(net 58 FLOW_OUT_L)
(net 59 "Net-(R1-Pad2)")
(net 60 FLOW_OUT_R)
(net 61 "Net-(R2-Pad2)")
(net 62 "Net-(R11-Pad1)")
(net 63 "Net-(R11-Pad2)")
(net 64 "Net-(R12-Pad1)")
(net 65 "Net-(R12-Pad2)")
(net 66 "Net-(R13-Pad2)")
(net 67 "Net-(R14-Pad1)")
(net 68 "Net-(R14-Pad2)")
(net 69 "Net-(R15-Pad1)")
(net 70 FLOW_IN_R)
(net 71 FLOW_IN_L)
(net_class Default "これはデフォルトのネット クラスです。"
(clearance 0.3)
(trace_width 0.3)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net 16MHz)
(add_net 3V3)
(add_net 5V)
(add_net AMP_IN_L)
(add_net AMP_IN_R)
(add_net CHECK1)
(add_net CHECK2)
(add_net CHECK3)
(add_net CHECK4)
(add_net CLK_AY)
(add_net CLK_SAA)
(add_net CLK_SN)
(add_net CONTROL1)
(add_net CONTROL2)
(add_net CONTROL3)
(add_net CONTROL4)
(add_net DATA)
(add_net FLOW_IN_L)
(add_net FLOW_IN_R)
(add_net FLOW_OUT_L)
(add_net FLOW_OUT_R)
(add_net FLOW_OUT_SHIELD)
(add_net GND)
(add_net LATCH)
(add_net LED1)
(add_net LED2)
(add_net LED3)
(add_net LEFT_IN)
(add_net LEFT_OUT)
(add_net MUDA1)
(add_net MUDA2)
(add_net MUDA3)
(add_net "Net-(C1-Pad2)")
(add_net "Net-(C5-Pad2)")
(add_net "Net-(C6-Pad1)")
(add_net "Net-(C7-Pad2)")
(add_net "Net-(C8-Pad1)")
(add_net "Net-(J1-Pad11)")
(add_net "Net-(JP2-Pad1)")
(add_net "Net-(JP2-Pad2)")
(add_net "Net-(JP3-Pad1)")
(add_net "Net-(JP3-Pad2)")
(add_net "Net-(JP4-Pad2)")
(add_net "Net-(JP5-Pad1)")
(add_net "Net-(JP5-Pad2)")
(add_net "Net-(JP6-Pad1)")
(add_net "Net-(JP6-Pad2)")
(add_net "Net-(JP7-Pad1)")
(add_net "Net-(JP7-Pad2)")
(add_net "Net-(JP8-Pad1)")
(add_net "Net-(JP8-Pad2)")
(add_net "Net-(R1-Pad2)")
(add_net "Net-(R11-Pad1)")
(add_net "Net-(R11-Pad2)")
(add_net "Net-(R12-Pad1)")
(add_net "Net-(R12-Pad2)")
(add_net "Net-(R13-Pad2)")
(add_net "Net-(R14-Pad1)")
(add_net "Net-(R14-Pad2)")
(add_net "Net-(R15-Pad1)")
(add_net "Net-(R2-Pad2)")
(add_net RIGHT_IN)
(add_net RIGHT_OUT)
(add_net SCK)
(add_net SCL)
(add_net SDA)
(add_net bias)
)
(net_class hoso ""
(clearance 0.2)
(trace_width 0.2)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(D1-Pad1)")
(add_net "Net-(D2-Pad1)")
(add_net "Net-(D3-Pad1)")
(add_net SW)
)
(module bongorian:chip (layer F.Cu) (tedit 0) (tstamp 5D31FCF7)
(at 122.5 100.5)
(fp_text reference gg1 (at 0 0) (layer F.SilkS) hide
(effects (font (size 1.524 1.524) (thickness 0.3)))
)
(fp_text value LOGO (at 0.75 0) (layer F.SilkS) hide
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(module bongorian:ESP32-DEVKITC locked (layer B.Cu) (tedit 5D30ECBA) (tstamp 5D313F4A)
(at 160 102 180)
(path /5D2E8AF5)
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(pad 30 thru_hole circle (at 12.7 -0.86) (size 1.56 1.56) (drill 1.04) (layers *.Cu *.Mask)
(net 16 SCK))
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(pad 33 thru_hole circle (at 12.7 6.76) (size 1.56 1.56) (drill 1.04) (layers *.Cu *.Mask)
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(net 14 DATA))
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)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer B.Cu) (tedit 5AE50EF0) (tstamp 5D313D9A)
(at 176 87.5 90)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1n (at 1.25 -2.05 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 1.25 0 90) (layer B.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)) (justify mirror))
)
(fp_line (start 3.55 1.05) (end -1.05 1.05) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.05) (end 3.55 1.05) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end 3.55 -1.05) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end -1.05 -1.05) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer B.SilkS) (width 0.12))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer B.SilkS) (width 0.12))
(fp_line (start 2.75 0.8) (end -0.25 0.8) (layer B.Fab) (width 0.1))
(fp_line (start 2.75 -0.8) (end 2.75 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end 2.75 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end -0.25 -0.8) (layer B.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(C1-Pad2)"))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5D313DAB)
(at 147.5 75.5 90)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5CBC7B12)
(fp_text reference C2 (at 2.75 -1.75 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 0.1u (at 1.25 2.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))