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07.srt
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[字幕生成:BLACK 字幕校对:志宇]
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刚才刷完抖音刷到深夜
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然后现在睡不着了,起来录个课
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今天已经来到LLVM的第三节
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深度剖析LLVM
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今天要讲的内容主要是围绕LLVM的后端
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就是后端CodeGen生成会员代码或者生成一些代码的指令
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接着会聊一聊基于LLVM的一些AI项目
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在进入正式的内容之前
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其实我有一个非常大的疑问
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就是一开始我做一些MySQL的进阶视频的时候
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我的粉丝量永远不超过100个
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也就是说我没有一个视频是超过100的浏览量
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几乎没有人看
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但是当我就发现我要不要做一些AI系统
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AI框架计算图比较通用性的东西
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于是我就做了一些视频
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然后这些视频的浏览量都不超过200到300
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那时候我的粉丝量的增加非常可怜
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基本上运作了两三个月也就300多个粉丝
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然后我想着最近大模型非常火
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要不要来搞些大模型的教程呢
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于是我又去系列的去梳理了大模型
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从张量并行,流水型并行,通讯原语
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各种大模型相关的技术全部都梳理了一遍之后
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然后我就发现
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似乎都好像也不爱看这玩意
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我的粉丝量永远上不去600
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也就是我耕耘了两个月之后
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我发现还是没有什么观看
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结果什么鬼
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我一开始以为LLVM这种老到掉渣
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而且还很硬很难啃的技术
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居然浏览量
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居然浏览量是我发过所有视频里面最高的
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我就想问问
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就是给我涨粉的这些粉丝
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你们给我弹幕
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或者你看到这条视频的人
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你告诉我为什么你会去看LLVM
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那要是后面我讲完LLVM之后呢
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我讲完传统编译器
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又去讲AI编译器
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我估计又没什么人来观看了
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好了
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吐槽的东西或者我的疑问呢
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我现在真的是满头包
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回到正式的内容
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这一节还是介绍LLVM的一个架构
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那主要是集中在后端
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可以看到回顾一下上两节的内容
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上一节讲了LLVM的前端
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前端主要是对高级语言
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做一些词法的分析
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把那些词呢
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把高级语言的特性的编上token
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然后给语法分析
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语法分析主要是分析
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我这句话有没有写错
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而语意分析才是真正的去分析
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写的代码的逻辑有没有问题
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在这一步语法到语意分析
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它传输的是一个AST
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语法数这么一个概念
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那像这种就是所谓的语法数
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语法分析这个环节呢
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输出一个语法数
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给语意分析
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然后去分析每一句话
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逻辑
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代码到底错在哪里
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到底有没有错
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接着呢就走到了LLVM的优化层了
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优化层有非常多的Path
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不同的Path处理不同的任务
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那中间的所有的箭头都是处理
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LLVM这个数据结构的
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Path里面呢主要有两个概念
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第一个是分析的Path
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第二个是转换的Path
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而转换的Path才是真正处理的Path
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那接着呢今天要讲讲
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LLVM的后端CodeGene
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如何生成代码
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在这一节里面呢
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就会把编译器的前端
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优化层还有后端都讲了
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那在后端里面呢
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其实是最复杂的
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也是跟硬件强相关的
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所以看到每一个后端呢
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它都跟实际的硬件是相关的
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但是即使是硬件相关呢
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LLVM的后端呢
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也对它们做了一个约束
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做了一些指定的选择
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计算机的分配在做调度
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代码布局
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最后做到代码的组装
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那在这一步工作呢
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大部分都叫它
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CodeGene代码生成
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总的来说呢
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就是把LLVM的IR呢
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变成目标代码
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或者汇编代码
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在后端的处理呢
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实际上呢是非常复杂的
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整个后端的Pipeline流水线呢
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用到了不同的IR
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不同的指令
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那第一个呢
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就是LLVM的IR
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还有Selection DAG图
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还有Machine Instruction
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还有MC Instruction
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在最后一个阶段呢
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把LLVM的IR呢
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转换成为目标的汇编代码了
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需要经过非常多的
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若干的步骤
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就是下面看到的
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这个Pipeline
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LLVM IR最后呢
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就会变成跟后端
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非常之亲密友好的
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一些具体的指令
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函数或者全局变量的
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具体的表示
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还有寄存器的表示
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流水线越往下走呢
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就越贴近
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实际硬件的目标指令
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图中白色的这些Path呢
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就是一些非必要的Path
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而这些灰色的Path呢
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就叫做必须的Path
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也叫做Super Path
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下面可以看到
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这里面有五个Super Path
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也会逐个的Super Path
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去展开
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第一个Super Path呢
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叫做指令选择
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Instruction Selection
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LLVM IR呢
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作为指令选择的
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一个输入
149
00:05:27,000 --> 00:05:28,000
然后在输入的时候呢
150
00:05:28,000 --> 00:05:29,000
就会把它变成一个
151
00:05:29,000 --> 00:05:30,000
Selection DAG
152
00:05:30,000 --> 00:05:31,000
那DAG呢
153
00:05:31,000 --> 00:05:32,000
就是有相无款图
154
00:05:32,000 --> 00:05:33,000
把IR
155
00:05:33,000 --> 00:05:35,000
变成正正的一个图
156
00:05:35,000 --> 00:05:36,000
每一个DAG图呢
157
00:05:36,000 --> 00:05:37,000
就表示
158
00:05:37,000 --> 00:05:39,000
单一的一个基本块的计算
159
00:05:39,000 --> 00:05:40,000
那既然是图
160
00:05:40,000 --> 00:05:41,000
那就有节点和编
161
00:05:41,000 --> 00:05:43,000
节点就表示
162
00:05:43,000 --> 00:05:44,000
具体执行的指令
163
00:05:44,000 --> 00:05:45,000
而边呢
164
00:05:45,000 --> 00:05:46,000
就代表编码之间的
165
00:05:46,000 --> 00:05:48,000
一个数据流的依赖关系
166
00:05:48,000 --> 00:05:49,000
目标呢
167
00:05:49,000 --> 00:05:50,000
就是家出的这一行
168
00:05:50,000 --> 00:05:52,000
希望把LLVM的代码
169
00:05:52,000 --> 00:05:53,000
或者LLVM的IR呢
170
00:05:53,000 --> 00:05:55,000
生成程序库
171
00:05:55,000 --> 00:05:56,000
能够运行呢
172
00:05:56,000 --> 00:05:57,000
基于数的模式匹配的
173
00:05:57,000 --> 00:05:59,000
指令选择的算法
174
00:05:59,000 --> 00:06:00,000
这句话呢
175
00:06:00,000 --> 00:06:01,000
有点拗口
176
00:06:01,000 --> 00:06:02,000
其实到这个步骤为止呢
177
00:06:02,000 --> 00:06:03,000
指令选择
178
00:06:03,000 --> 00:06:05,000
把LLVM IR变成
179
00:06:05,000 --> 00:06:07,000
一个DAG图
180
00:06:07,000 --> 00:06:08,000
这个DAG图呢
181
00:06:08,000 --> 00:06:09,000
其实就是目标的
182
00:06:09,000 --> 00:06:11,000
机器代码的一个节点
183
00:06:11,000 --> 00:06:12,000
这些节点呢
184
00:06:12,000 --> 00:06:13,000
就代表目标的
185
00:06:13,000 --> 00:06:14,000
机器的指令了
186
00:06:14,000 --> 00:06:16,000
而不是LLVM的指令了
187
00:06:16,000 --> 00:06:17,000
LLVM的指令
188
00:06:17,000 --> 00:06:18,000
就是3D子结构嘛
189
00:06:18,000 --> 00:06:19,000
在上一节里面
190
00:06:19,000 --> 00:06:20,000
讲到了
191
00:06:20,000 --> 00:06:21,000
而现在呢
192
00:06:21,000 --> 00:06:23,000
就是真正的机器的指令
193
00:06:23,000 --> 00:06:24,000
变成DAG
194
00:06:24,000 --> 00:06:25,000
那DAG是一个图
195
00:06:25,000 --> 00:06:27,000
图非常方便用于建树
196
00:06:27,000 --> 00:06:29,000
通过指令选择算法呢
197
00:06:29,000 --> 00:06:31,000
去执行DAG的指令
198
00:06:31,000 --> 00:06:33,000
那第二个步骤呢
199
00:06:33,000 --> 00:06:34,000
就是指令调度
200
00:06:34,000 --> 00:06:36,000
Instruction Scheduling
201
00:06:36,000 --> 00:06:37,000
第二个步骤
202
00:06:37,000 --> 00:06:38,000
可以看到
203
00:06:38,000 --> 00:06:39,000
实际上有两个
204
00:06:39,000 --> 00:06:41,000
Instruction Scheduling
205
00:06:41,000 --> 00:06:42,000
从Pipeline里面呢
206
00:06:42,000 --> 00:06:43,000
可以看到
207
00:06:43,000 --> 00:06:45,000
它有两个Instruction Scheduling
208
00:06:45,000 --> 00:06:47,000
就是两个指令调度
209
00:06:47,000 --> 00:06:48,000
现在讲讲
210
00:06:48,000 --> 00:06:50,000
第一次指令调度的工作
211
00:06:50,000 --> 00:06:51,000
也就是我做一个
212
00:06:51,000 --> 00:06:53,000
寄存器的预分配
213
00:06:53,000 --> 00:06:54,000
刚才的第一步工作呢
214
00:06:54,000 --> 00:06:55,000
已经把它变成一个
215
00:06:55,000 --> 00:06:56,000
DAG的图了
216
00:06:56,000 --> 00:06:58,000
我对这些DAG的图的指令呢
217
00:06:58,000 --> 00:06:59,000
做一个排序
218
00:06:59,000 --> 00:07:01,000
就是对节点进行排序
219
00:07:01,000 --> 00:07:02,000
尽可能多的
220
00:07:02,000 --> 00:07:03,000
去发现这些
221
00:07:03,000 --> 00:07:04,000
可以并行的一些指令
222
00:07:04,000 --> 00:07:06,000
同时把指令呢
223
00:07:06,000 --> 00:07:08,000
变成另外一种表示形式
224
00:07:08,000 --> 00:07:09,000
那这种表示形式
225
00:07:09,000 --> 00:07:10,000
其实也叫做IR
226
00:07:10,000 --> 00:07:11,000
但是这个IR呢
227
00:07:11,000 --> 00:07:13,000
叫做Machine Instruction
228
00:07:13,000 --> 00:07:15,000
三地址的表示方式
229
00:07:15,000 --> 00:07:16,000
在第三个步骤呢
230
00:07:16,000 --> 00:07:19,000
就是寄存器的分配
231
00:07:19,000 --> 00:07:21,000
Register Allocation
232
00:07:21,000 --> 00:07:23,000
在前面的章节里面
233
00:07:23,000 --> 00:07:24,000
其实已经谈到了
234
00:07:24,000 --> 00:07:26,000
寄存器是非常昂贵的
235
00:07:26,000 --> 00:07:28,000
而每一个硬件的寄存器
236
00:07:28,000 --> 00:07:29,000
都是有限的
237
00:07:29,000 --> 00:07:30,000
但是LVM IR里面呢
238
00:07:30,000 --> 00:07:32,000
就有两个比较重要的特性
239
00:07:32,000 --> 00:07:34,000
一个是SSA
240
00:07:34,000 --> 00:07:35,000
那第二个特性呢
241
00:07:35,000 --> 00:07:37,000
就是寄存器假设是无限的
242
00:07:37,000 --> 00:07:39,000
所以LVM IR里面用百分
243
00:07:39,000 --> 00:07:41,000
还代表无限的寄存器
244
00:07:41,000 --> 00:07:42,000
这个特性呢
245
00:07:42,000 --> 00:07:43,000
保持到这一步为止呢
246
00:07:43,000 --> 00:07:44,000
就终止了
247
00:07:44,000 --> 00:07:46,000
把LVM IR里面
248
00:07:46,000 --> 00:07:47,000
无限虚拟的寄存器呢
249
00:07:47,000 --> 00:07:49,000
转换成为实际上有目标
250
00:07:49,000 --> 00:07:50,000
有地址