add component name to more error messages

charlesreiss · Jul 14, 2022 · 39fc71b · 39fc71b
1 parent 99dadd5
commit 39fc71b
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Showing 3 changed files with 29 additions and 17 deletions.
diff --git a/src/errors.rs b/src/errors.rs
@@ -52,7 +52,7 @@ pub enum Error {
         new_span: Span
     },
     DoubleAssignedFixedOutWire { name: String, span: Span, fixed_name: String },
-    RedeclaredBuiltinWire(String, Span),
+    RedeclaredBuiltinWire { name: String, span: Span, fixed_name: String },
     PartialFixedInput {
         name: String,
         found_inputs: Vec<String>,
@@ -406,9 +406,9 @@ impl Error {
                 error_continue(output, &format!("but would also be used by register declared here:"))?;
                 write!(output, "{}", contents.show_region(new_span.0, new_span.1))?;
             },
-            Error::RedeclaredBuiltinWire(ref name, ref new_span) => {
-                error(output, &format!("Builtin wire '{}' redeclared here:", name))?;
-                write!(output, "{}", contents.show_region(new_span.0, new_span.1))?;
+            Error::RedeclaredBuiltinWire { ref name, ref span, ref fixed_name } => {
+                error(output, &format!("Builtin wire '{}' (part of the {}) redeclared here:", name, fixed_name))?;
+                write!(output, "{}", contents.show_region(span.0, span.1))?;
             },
             Error::PartialFixedInput { ref name, ref found_inputs, ref missing_inputs } => {
                 // FIXME: error should identify missing input
@@ -626,7 +626,7 @@ impl error::Error for Error {
             Error::DoubleAssignedRegisterWire {..} => "wire assigned by register also assigned manually",
             Error::DoubleDeclaredRegisterOutWire {..} => "multiply declared register out wire found",
             Error::RedeclaredWire(_,_,_) => "multiply defined wire found",
-            Error::RedeclaredBuiltinWire(_,_) => "redefined wire from fixed functionality",
+            Error::RedeclaredBuiltinWire {..} => "redefined wire from fixed functionality",
             Error::PartialFixedInput {..} => "part of fixed functionality set, but not all",
             Error::WireLoop(_) => "circular dependency between wires found",
             Error::InvalidWireWidth(_) => "wire width out of range",

diff --git a/src/program.rs b/src/program.rs
@@ -600,18 +600,25 @@ const FALSE = 0;
 
 fn check_double_declare<'a, 'b>(errors: &'b mut Vec<Error>, name: &'a str, span: Span,
                        wire_decl_spans: &'b mut HashMap<&'a str, Span>,
-                       wires: &'b HashMap<&'a str, WireWidth>) {
+                       fixed_to_component_name: &'b HashMap<&'a str, &'a str>) {
     match wire_decl_spans.get(name) {
         Some(other_span) => {
             errors.push(
                 Error::RedeclaredWire(String::from(name), span, *other_span)
             );
         },
         None => {
-            if wires.contains_key(name) {
-                errors.push(
-                    Error::RedeclaredBuiltinWire(String::from(name), span)
-                );
+            match fixed_to_component_name.get(name) {
+                Some(fixed_name) => {
+                    errors.push(
+                        Error::RedeclaredBuiltinWire {
+                            name: String::from(name),
+                            span: span,
+                            fixed_name: String::from(*fixed_name),
+                        }
+                    );
+                },
+                None => {},
             }
         },
     }
@@ -635,35 +642,38 @@ impl Program {
         let mut needed_wires = HashSet::new();
         let mut assignments = HashMap::new();
         let mut register_banks_raw = Vec::new();
-        let mut fixed_out_wires = HashMap::new();
+        let mut fixed_to_component_name = HashMap::new();
+        let mut fixed_out_wires = HashSet::new();
         let mut register_in_spans = HashMap::new();
         let mut wire_to_type = HashMap::new();
         let mut errors = Vec::new();
         for fixed in &fixed_functions {
             for ref in_wire in &fixed.in_wires {
                 wire_to_type.insert(in_wire.name.clone(), WireType::BuiltinInput);
                 wires.insert(in_wire.name.as_str(), in_wire.width);
+                fixed_to_component_name.insert(in_wire.name.as_str(), fixed.name.as_str());
             }
             for ref decl in &fixed.out_wire {
                 wire_to_type.insert(decl.name.clone(), WireType::BuiltinOutput);
                 wires.insert(decl.name.as_str(), decl.width);
-                fixed_out_wires.insert(decl.name.as_str(), fixed.name.as_str());
+                fixed_out_wires.insert(decl.name.as_str());
+                fixed_to_component_name.insert(decl.name.as_str(), fixed.name.as_str());
             }
         }
         for statement in &statements {
             match *statement {
                 Statement::ConstDecls(ref decls) => {
                     for ref decl in decls {
                         check_double_declare(&mut errors, decl.name.as_str(), decl.name_span,
-                                        &mut wire_decl_spans, &wires);
+                                             &mut wire_decl_spans, &fixed_to_component_name);
                         wire_to_type.insert(decl.name.clone(), WireType::Constant);
                         constants_raw.insert(decl.name.as_str(), &decl.value);
                     }
                 },
                 Statement::WireDecls(ref decls) => {
                     for ref decl in decls {
                         check_double_declare(&mut errors, decl.name.as_str(), decl.span,
-                                        &mut wire_decl_spans, &wires);
+                                             &mut wire_decl_spans, &fixed_to_component_name);
                         wires.insert(decl.name.as_str(), decl.width);
                         wire_to_type.insert(decl.name.clone(), WireType::Normal);
                         needed_wires.insert(decl.name.as_str());
@@ -679,12 +689,14 @@ impl Program {
                                         *assign_spans.get(name.as_str()).unwrap(),
                                     )
                                 );
-                            } else if fixed_out_wires.contains_key(name.as_str()) {
+                            } else if fixed_out_wires.contains(name.as_str()) {
                                 errors.push(
                                     Error::DoubleAssignedFixedOutWire {
                                         name: name.clone(), 
                                         span: *span,
-                                        fixed_name: String::from(*fixed_out_wires.get(name.as_str()).unwrap()),
+                                        fixed_name: String::from(
+                                            *fixed_to_component_name.get(name.as_str()).unwrap()
+                                        ),
                                     }
                                 );
                             }

diff --git a/src/tests.rs b/src/tests.rs
@@ -950,7 +950,7 @@ pc = 0;
 Stat = STAT_AOK;
 ");
     debug!("error message is {}", message);
-    assert!(message.contains("Builtin wire 'i10bytes' redeclared here:"));
+    assert_regex_match(&message, "Builtin wire 'i10bytes'.*redeclared here:");
     assert!(message.contains("wire i10bytes : 64"));
 }